CN111063305A - 像素电路、显示面板及像素电路基准电压的补偿方法 - Google Patents

像素电路、显示面板及像素电路基准电压的补偿方法 Download PDF

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CN111063305A
CN111063305A CN202010012085.0A CN202010012085A CN111063305A CN 111063305 A CN111063305 A CN 111063305A CN 202010012085 A CN202010012085 A CN 202010012085A CN 111063305 A CN111063305 A CN 111063305A
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thin film
film transistor
signal
node
pixel circuit
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肖翔
薛炎
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to PCT/CN2020/075594 priority patent/WO2021138965A1/zh
Priority to US16/757,394 priority patent/US11322091B2/en
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Abstract

本发明提供像素电路、显示面板及像素电路基准电压的补偿方法，包括呈阵列式排布的多个像素内部驱动电路。每一像素内部驱动电路均包括：第一薄膜晶体管(T1)、第二薄膜晶体管(T2)、第四薄膜晶体管(T4)、第一电容(C1)、有机发光二极管(D1)以及补偿模块。通过设置了一补偿模块，该补补偿模块接入一扫描信号(EM)，所述补偿模块一端连接所述第一节点(G)，另一端连接所述电源电压(VDD)，用以补偿因第一电容(C1)耦合导致所述第一节点(G)的电位下降，进而保持基准电压Vgs保持不变，流经驱动薄膜晶体管(即第一薄膜晶体管)的电流不发生变化，进而面板发光均匀。

Description

像素电路、显示面板及像素电路基准电压的补偿方法
技术领域
本发明涉及显示技术领域，特别是一种像素电路、显示面板及像素电路基准电压的补偿方法。
背景技术
有机电致发光二极管(organic light emitting diode，OLED)是一种自发光的显示技术，具有视角宽、对比度高、功耗低、色彩鲜艳等优点。由于这些优势，在显示行业所占的比重正在逐年增加。氧化物薄膜晶体管由于迁移率高，均匀性好等优点而在大尺寸AMOLED中广泛使用。但随着面板使用时间延长，薄膜晶体管以及OLED的电性会发生漂移，最终因显示不均匀等问题而失效。
如图1所示，传统的有源有机电致发光二极管(active matrix organic lightemitting diode，AMOLED)的像素电路为3T1C，Data信号写入节点G点阶段时，在T2的栅极关闭时，由于电容C1的耦合效应导致G点的电压下降，引起流经T1的电流发生变化(如图2中的标记10处，电流曲线爬升有一波动)，且面板不用位置的耦合效应不同，导致面板发光不均匀。
因此，急需提供一种新的像素电路、显示面板及像素电路基准电压的补偿方法，用以对因第一电容(C1)耦合导致所述第一节点(G)的电位下降进行补偿，提升面板显示的均匀性。
发明内容
本发明的目的是，提供一种像素电路、显示面板及像素电路基准电压的补偿方法，用以对因第一电容(C1)耦合导致所述第一节点(G)的电位下降进行补偿，提升面板显示的均匀性。
为达到上述目的，提供一种像素电路，包括呈阵列式排布的多个像素内部驱动电路；每一像素内部驱动电路均包括：第一薄膜晶体管(T1)，所述第一薄膜晶体管的栅极电性连接第一节点(G)，所述第一薄膜晶体管的源极电性连接第二节点(S)，所述第一薄膜晶体管的漏极接入电源电压(VDD)；第二薄膜晶体管(T2)，所述第二薄膜晶体管的栅极接入写入信号(WR)，所述第二薄膜晶体管的源极接入数据信号(Data)，所述第二薄膜晶体管的漏极电性连接第一节点(G)；第一电容(C1)，一端连接所述第一节点(G)，另一端连接所述第二节点(S)；第四薄膜晶体管(T4)，所述第四薄膜晶体管的栅极接入读取信号(RD)，所述第四薄膜晶体管的源极电性连接第二节点(S)，所述第四薄膜晶体管的漏极电性连接所述参考电压信号(Ref)；有机发光二极管(D1)，所述有机发光二极管(D1)的阳极电性连接所述第二节点(S)，所述有机发光二极管(D1)的阴极接地；补偿模块，接入一扫描信号(EM)，所述补偿模块一端连接所述第一节点(G)，另一端连接所述电源电压(VDD)，用以补偿因第一电容(C1)耦合导致所述第一节点(G)的电位下降。
进一步地，所述补偿模块包括第三薄膜晶体管(T3)以及第二电容(Cp)；第三薄膜晶体管(T3)，所述第三薄膜晶体管的栅极接入扫描信号(EM)，所述第三薄膜晶体管的源极电性连接第一节点(G)，所述第三薄膜晶体管的漏极电性连接第二电容(C2)的一端；所述第二电容(Cp)的另一端电性连接所述电源电压(VDD)。
进一步地，第三薄膜晶体管(T3)与所述第二薄膜晶体管(T2)的宽长比相同。
进一步地，所述第一薄膜晶体管(T1)、所述第二薄膜晶体管(T2)、所述第三薄膜晶体管(T3)、及所述第四薄膜晶体管(T4)均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管。
进一步地，所述写入信号(WR)以及所述扫描信号(EM)通过外部时序控制器提供；和/或，所述扫描信号(EM)与所述写入信号(WR)的延迟负载一致。
进一步地，所述写入信号(WR)、所述扫描信号(EM)、及所述数据信号(Data)相组合，先后对应于写入阶段以及发光阶段；在所述写入阶段，所述写入信号(WR)提供高电位，所述扫描信号(EM)提供低电位，所述数据信号(Data)提供高电位；在所述发光阶段，所述写入信号(WR)提供低电位，所述扫描信号(EM)提供高电位，所述数据信号(Data)提供低电位。
进一步地，在所述写入阶段，所述扫描信号(EM)提供低电位与所述第一薄膜晶体管的阈值电压之差大于最高灰阶的数据信号的电压。
进一步地，所述像素电路包括：NMOS电路、PMOS电路或CMOS电路。
本发明提供一种显示面板，包括前文所述的像素电路，所述显示面板为AMOLED显示面板。
本发明还提供一种像素电路基准电压的补偿方法，包括如下步骤：提供前文所述的补偿电路；进入写入阶段，在所述写入阶段，所述写入信号(WR)提供高电位，所述扫描信号(EM)提供低电位，所述数据信号(Data)经过一延迟后提供高电位，所述第二薄膜晶体管(T2)、所述第三薄膜晶体管(T3)、及所述第四薄膜晶体管(T4)均打开，所述数据信号(Data)和所述参考电压(Vref)分别对第一节点(G)和第二节点(S)点写入初始电位；进入发光阶段，在所述发光阶段，所述写入信号(WR)提供低电位，所述扫描信号(EM)提供高电位，所述数据信号(Data)经过一延迟后提供低电位，所述第二薄膜晶体管(T2)以及所述第三薄膜晶体管(T3)关闭，且所述电源电压(VDD)开始对第二节点(S)充电，第一节点(G)的电位由于第一电容(C)的耦合而下降，所述扫描信号(EM)通过所述补偿模块将所述第一节点(G)的电位拉高，使所述基准电压Vgs保持不变。
本发明的有益效果是：本发明提供像素电路、显示面板及像素电路基准电压的补偿方法，通过设置了一补偿模块，该补补偿模块接入一扫描信号(EM)，所述补偿模块一端连接所述第一节点(G)，另一端连接所述电源电压(VDD)，用以补偿因第一电容(C1)耦合导致所述第一节点(G)的电位下降，进而保持基准电压Vgs保持不变，流经驱动薄膜晶体管(即第一薄膜晶体管)的电流不发生变化，进而面板发光均匀。
附图说明
下面结合附图和实施例对本发明作进一步的描述。
图1为现有技术的像素混合补偿电路的电路图。
图2为现有技术的像素混合补偿电路的时序图。
图3为本发明提供的像素混合补偿电路的电路图。
图4为本发明提供的像素混合补偿电路的时序图。
像素混合补偿电路100；外部补偿电路200；
模数转换器201；电压比较器202；控制模块203；
存储器204；数模转换器205。
具体实施方式
为了更好地理解本发明的内容，下面通过具体的实施例对本发明作进一步说明，但本发明的实施和保护范围不限于此。
如图3所示，本发明提供一种像素电路，包括呈阵列式排布的多个像素内部驱动电路。
每一像素内部驱动电路均包括：第一薄膜晶体管(T1)、第二薄膜晶体管(T2)、第四薄膜晶体管(T4)、第一电容(C1)、有机发光二极管(D1)以及补偿模块。
所述第一薄膜晶体管(T1)的栅极电性连接第一节点(G)，所述第一薄膜晶体管的源极电性连接第二节点(S)，所述第一薄膜晶体管的漏极接入电源电压(VDD)。
所述第二薄膜晶体管的栅极接入写入信号(WR)，所述第二薄膜晶体管的源极接入数据信号(Data)，所述第二薄膜晶体管的漏极电性连接第一节点(G)。
所述第一电容(C1)一端连接所述第一节点(G)，另一端连接所述第二节点(S)。
所述第四薄膜晶体管的栅极接入读取信号(RD)，所述第四薄膜晶体管的源极电性连接第二节点(S)，所述第四薄膜晶体管的漏极电性连接所述参考电压信号(Ref)。
所述有机发光二极管(D1)的阳极电性连接所述第二节点(S)，所述有机发光二极管(D1)的阴极接电源电压(VSS)。
所述补偿模块接入一扫描信号(EM)，所述补偿模块一端连接所述第一节点(G)，另一端连接所述电源电压(VDD)，用以补偿因第一电容(C1)耦合导致所述第一节点(G)的电位下降，进而保持基准电压Vgs保持不变，流经驱动薄膜晶体管(即第一薄膜晶体管)的电流不发生变化，进而面板发光均匀。
所述补偿模块包括第三薄膜晶体管(T3)以及第二电容(Cp)。
第三薄膜晶体管(T3)，所述第三薄膜晶体管的栅极接入扫描信号(EM)，所述第三薄膜晶体管的源极电性连接第一节点(G)，所述第三薄膜晶体管的漏极电性连接第二电容(C2)的一端。第三薄膜晶体管(T3)与所述第二薄膜晶体管(T2)的宽长比相同。
所述第二电容(Cp)的另一端电性连接所述电源电压(VDD)。
所述第一薄膜晶体管(T1)、所述第二薄膜晶体管(T2)、所述第三薄膜晶体管(T3)、及所述第四薄膜晶体管(T4)均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管。
所述写入信号(WR)以及所述扫描信号(EM)通过外部时序控制器提供；和/或，所述扫描信号(EM)与所述写入信号(WR)的延迟负载一致。
如图4所示，所述写入信号(WR)、所述扫描信号(EM)、及所述数据信号(Data)相组合，先后对应于写入阶段以及发光阶段。
在所述写入阶段，所述写入信号(WR)提供高电位，所述扫描信号(EM)提供低电位，所述数据信号(Data)提供高电位。
在所述发光阶段，所述写入信号(WR)提供低电位，所述扫描信号(EM)提供高电位，所述数据信号(Data)提供低电位。
在所述写入阶段，所述扫描信号(EM)提供低电位与所述第一薄膜晶体管的阈值电压之差大于最高灰阶的数据信号的电压。
图4中的电流测试曲线，在爬升的时候，并没有波动，电流并无较大的变化。
所述像素电路包括：NMOS电路、PMOS电路或CMOS电路。
本发明提供一种像素电路，通过设置了一补偿模块，该补补偿模块接入一扫描信号(EM)，所述补偿模块一端连接所述第一节点(G)，另一端连接所述电源电压(VDD)，用以补偿因第一电容(C1)耦合导致所述第一节点(G)的电位下降，进而保持基准电压Vgs保持不变，流经驱动薄膜晶体管(即第一薄膜晶体管)的电流不发生变化，进而面板发光均匀。
本发明还提供一种显示面板，包括所述的像素电路，所述显示面板为AMOLED显示面板。
本发明还提供一种像素电路基准电压的补偿方法，包括如下步骤S1)～S3)。
S1)提供所述的像素电路。
S2)进入写入阶段，在所述写入阶段，所述写入信号(WR)提供高电位，所述扫描信号(EM)提供低电位，所述数据信号(Data)经过一延迟后提供高电位，所述第二薄膜晶体管(T2)、所述第三薄膜晶体管(T3)、及所述第四薄膜晶体管(T4)均打开，所述数据信号(Data)和所述参考电压(Vref)分别对第一节点(G)和第二节点(S)点写入初始电位。
S3)进入发光阶段，在所述发光阶段，所述写入信号(WR)提供低电位，所述扫描信号(EM)提供高电位，所述数据信号(Data)经过一延迟后提供低电位，所述第二薄膜晶体管(T2)以及所述第三薄膜晶体管(T3)关闭，且所述电源电压(VDD)开始对第二节点(S)充电，第一节点(G)的电位由于第一电容(C)的耦合而下降，所述扫描信号(EM)通过所述补偿模块将所述第一节点(G)的电位拉高，使所述基准电压Vgs保持不变。
应当指出，对于经充分说明的本发明来说，还可具有多种变换及改型的实施方案，并不局限于上述实施方式的具体实施例。上述实施例仅仅作为本发明的说明，而不是对本发明的限制。总之，本发明的保护范围应包括那些对于本领域普通技术人员来说显而易见的变换或替代以及改型。

Claims (10)

1.一种像素电路，其特征在于，包括呈阵列式排布的多个像素内部驱动电路；
每一像素内部驱动电路均包括：
第一薄膜晶体管(T1)，所述第一薄膜晶体管(T1)的栅极电性连接第一节点(G)，所述第一薄膜晶体管的源极电性连接第二节点(S)，所述第一薄膜晶体管的漏极接入电源电压(VDD)；
第二薄膜晶体管(T2)，所述第二薄膜晶体管的栅极接入写入信号(WR)，所述第二薄膜晶体管的源极接入数据信号(Data)，所述第二薄膜晶体管的漏极电性连接第一节点(G)；
第一电容(C1)，一端连接所述第一节点(G)，另一端连接所述第二节点(S)；
第四薄膜晶体管(T4)，所述第四薄膜晶体管的栅极接入读取信号(RD)，所述第四薄膜晶体管的源极电性连接第二节点(S)，所述第四薄膜晶体管的漏极电性连接所述参考电压信号(Ref)；
有机发光二极管(D1)，所述有机发光二极管(D1)的阳极电性连接所述第二节点(S)，所述有机发光二极管(D1)的阴极接电源电压(VSS)；
补偿模块，接入一扫描信号(EM)，所述补偿模块的一端连接所述第一节点(G)，另一端连接所述电源电压(VDD)，用以补偿因第一电容(C1)耦合导致所述第一节点(G)的电位下降。
2.根据权利要求1所述的像素电路，其特征在于，
所述补偿模块包括第三薄膜晶体管(T3)以及第二电容(Cp)；
第三薄膜晶体管(T3)，所述第三薄膜晶体管的栅极接入扫描信号(EM)，所述第三薄膜晶体管的源极电性连接第一节点(G)，所述第三薄膜晶体管的漏极电性连接第二电容(C2)的一端；
所述第二电容(Cp)的另一端电性连接所述电源电压(VDD)。
3.根据权利要求2所述的像素电路，其特征在于，
第三薄膜晶体管(T3)与所述第二薄膜晶体管(T2)的宽长比相同。
4.根据权利要求1所述的像素电路，其特征在于，
所述第一薄膜晶体管(T1)、所述第二薄膜晶体管(T2)、所述第三薄膜晶体管(T3)、及所述第四薄膜晶体管(T4)均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管。
5.根据权利要求1所述的像素电路，其特征在于，
所述写入信号(WR)以及所述扫描信号(EM)通过外部时序控制器提供；
和/或，
所述扫描信号(EM)与所述写入信号(WR)的延迟负载一致。
6.根据权利要求2所述的像素电路，其特征在于，
所述写入信号(WR)、所述扫描信号(EM)、及所述数据信号(Data)相组合，先后对应于写入阶段以及发光阶段；
在所述写入阶段，所述写入信号(WR)提供高电位，所述扫描信号(EM)提供低电位，所述数据信号(Data)提供高电位；
在所述发光阶段，所述写入信号(WR)提供低电位，所述扫描信号(EM)提供高电位，所述数据信号(Data)提供低电位。
7.根据权利要求6所述的像素电路，其特征在于，
在所述写入阶段，所述扫描信号(EM)提供低电位与所述第一薄膜晶体管的阈值电压之差大于最高灰阶的数据信号的电压。
8.根据权利要求1所述的像素电路，其特征在于，
所述像素电路包括：NMOS电路、PMOS电路或CMOS电路。
9.一种显示面板，其特征在于，包括如权利要求1～8任一项所述的像素电路，所述显示面板为AMOLED显示面板。
10.一种像素电路基准电压的补偿方法，其特征在于，包括如下步骤：
提供如权利要求1～8任一项所述的像素电路；
进入写入阶段，在所述写入阶段，所述写入信号(WR)提供高电位，所述扫描信号(EM)提供低电位，所述数据信号(Data)经过一延迟后提供高电位，所述第二薄膜晶体管(T2)、所述第三薄膜晶体管(T3)、及所述第四薄膜晶体管(T4)均打开，所述数据信号(Data)和所述参考电压(Vref)分别对第一节点(G)和第二节点(S)点写入初始电位；
进入发光阶段，在所述发光阶段，所述写入信号(WR)提供低电位，所述扫描信号(EM)提供高电位，所述数据信号(Data)经过一延迟后提供低电位，所述第二薄膜晶体管(T2)以及所述第三薄膜晶体管(T3)关闭，且所述电源电压(VDD)开始对第二节点(S)充电，第一节点(G)的电位由于第一电容(C)的耦合而下降，所述扫描信号(EM)通过所述补偿模块将所述第一节点(G)的电位拉高，使所述基准电压Vgs保持不变。
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