WO2020216201A1 - 像素电路及其驱动方法、显示基板、显示装置 - Google Patents

像素电路及其驱动方法、显示基板、显示装置 Download PDF

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Publication number
WO2020216201A1
WO2020216201A1 PCT/CN2020/085768 CN2020085768W WO2020216201A1 WO 2020216201 A1 WO2020216201 A1 WO 2020216201A1 CN 2020085768 W CN2020085768 W CN 2020085768W WO 2020216201 A1 WO2020216201 A1 WO 2020216201A1
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Prior art keywords
node
circuit
transistor
potential
emission control
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PCT/CN2020/085768
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English (en)
French (fr)
Inventor
陈帅
唐秀珠
张智
刘丰伟
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京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 重庆京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/256,705 priority Critical patent/US11244624B2/en
Publication of WO2020216201A1 publication Critical patent/WO2020216201A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, a display substrate, and a display device.
  • OLED Organic light emitting diode
  • an OLED display panel includes pixel units arranged in an array, and each pixel unit includes a switching transistor, a driving transistor, and an OLED.
  • the switching transistor can output the data signal provided by the data signal terminal to the driving transistor, and the driving transistor can output a driving current to the OLED according to the DC power signal provided by the DC power terminal and the data signal to drive the OLED to emit light.
  • the present disclosure provides a pixel circuit and a driving method thereof, a display substrate, and a display device.
  • the technical solutions are as follows:
  • a pixel circuit in one aspect, includes a light emission control circuit, a compensation circuit, and a driving circuit;
  • the light-emitting control circuit is respectively connected to a first scan signal terminal, a light-emitting control signal terminal, a data signal terminal, a DC power terminal, a first node, a second node, a third node, and a light-emitting element, and the light-emitting control circuit is used to respond to The first scan signal from the first scan signal terminal and the data signal from the data signal terminal are used to control the potential of the first node and to respond to the light emission control signal from the light emission control signal terminal to The second node outputs the DC power signal provided by the DC power terminal, and controls the on-off of the third node and the light-emitting element;
  • the compensation circuit is respectively connected to the first node and the second node, and the compensation circuit is configured to adjust the potential of the first node according to the potential of the second node;
  • the driving circuit is respectively connected to the first node, the second node, and the third node, and the driving circuit is configured to respond to the potential of the first node and the potential of the second node to The third node outputs a driving signal.
  • the compensation circuit includes: a storage capacitor
  • One end of the storage capacitor is connected to the first node, and the other end of the storage capacitor is connected to the second node.
  • the driving circuit includes: a driving transistor
  • the gate of the driving transistor is connected to the first node, the first electrode of the driving transistor is connected to the second node, and the second electrode of the driving transistor is connected to the third node.
  • the light-emitting control circuit includes: a data writing sub-circuit, a compensation sub-circuit, and a light-emitting control sub-circuit;
  • the data writing sub-circuit is respectively connected to the first scan signal terminal, the data signal terminal and the third node, and the data writing sub-circuit is used to respond to the first scan signal to The third node outputs the data signal;
  • the compensation sub-circuit is respectively connected to the first scan signal terminal, the first node, and the fourth node, and the compensation sub-circuit is configured to control the first node in response to the second scan signal Connected to the fourth node, the fourth node is also connected to the first pole of the driving transistor in the driving circuit;
  • the light-emitting control sub-circuit is respectively connected to the light-emitting control signal terminal, the DC power terminal, the second node, the fourth node, the third node and the light-emitting element, and the light-emitting control sub-circuit
  • the circuit is used for outputting the DC power signal to the second node in response to the light emission control signal, controlling the on-off of the second node and the fourth node, and controlling the third node and the The on and off of the light-emitting element.
  • the data writing sub-circuit includes: a data writing transistor
  • the gate of the data writing transistor is connected to the first scan signal terminal, the first electrode of the data writing transistor is connected to the data signal terminal, and the second electrode of the data writing transistor is connected to the The third node is connected.
  • the compensation sub-circuit includes: a compensation transistor
  • the gate of the compensation transistor is connected to the first scan signal terminal, the first electrode of the compensation transistor is connected to the first node, and the second electrode of the compensation transistor is connected to the fourth node.
  • the light emission control sub-circuit includes: a first light emission control transistor, a second light emission control transistor, and a third light emission control transistor;
  • the gate of the first light emission control transistor is connected to the light emission control signal terminal, the first electrode of the first light emission control transistor is connected to the DC power supply terminal, and the second electrode of the first light emission control transistor is connected to the The second node connection;
  • the gate of the second light emission control transistor is connected to the light emission control signal terminal, the first electrode of the second light emission control transistor is connected to the second node, and the second electrode of the second light emission control transistor is connected to the The fourth node connection;
  • the gate of the third light emission control transistor is connected to the light emission control signal terminal, the first electrode of the third light emission control transistor is connected to the third node, and the second electrode of the third light emission control transistor is connected to the The light-emitting element is connected.
  • the light emission control circuit further includes: a first reset sub-circuit and a second reset sub-circuit;
  • the first reset sub-circuit is respectively connected to the second scan signal terminal, the initial power terminal and the first node, and the first reset sub-circuit is configured to respond to the second scan signal from the second scan signal terminal, Outputting the initial power signal provided by the initial power terminal to the first node;
  • the second reset sub-circuit is respectively connected to the second node, the third scan signal terminal and the reset power terminal, and the second reset sub-circuit is configured to respond to the third scan signal from the third scan signal terminal, Outputting the reset power signal provided by the reset power terminal to the second node.
  • the first reset sub-circuit includes: a first reset transistor
  • the gate of the first reset transistor is connected to the second scan signal terminal, the first electrode of the first reset transistor is connected to the initial power terminal, and the second electrode of the first reset transistor is connected to the First node connection;
  • the second reset sub-circuit includes: a second reset transistor; the gate of the second reset transistor is connected to the third scan signal terminal, and the first electrode of the second reset transistor is connected to the The reset power terminal is connected, and the second electrode of the second reset transistor is connected to the second node.
  • the transistors included in the pixel circuit are all P-type transistors.
  • a method for driving a pixel circuit which is applied to the pixel circuit as described in the above aspect, and the method includes:
  • the potential of the first scan signal provided by the first scan signal terminal is the first potential
  • the light emitting control circuit responds to the first scan signal and controls the potential of the first node according to the data signal provided by the data signal terminal ;
  • the potential of the lighting control signal provided by the lighting control signal terminal is the first potential
  • the lighting control circuit responds to the lighting control signal to output the DC power signal provided by the DC power terminal to the second node, and controls the third
  • the node is turned on with the light-emitting element
  • the compensation circuit adjusts the potential of the first node according to the potential of the second node
  • the drive circuit responds to the potential of the first node and the potential of the second node to transfer the signal to the third node. Output drive signal.
  • the light-emitting control circuit includes: a data writing sub-circuit, a compensation sub-circuit, and a light-emitting control sub-circuit;
  • the electric potential of the first scan signal is the first electric potential
  • the data signal terminal is transmitted to the first electric potential through the data writing sub-circuit, the driving circuit and the compensation sub-circuit.
  • the node outputs the data signal
  • the potential of the lighting control signal is the first potential
  • the DC power supply terminal outputs the DC power supply signal to the second node through the lighting control sub-circuit
  • the third node is connected to The light-emitting element is turned on.
  • the light-emitting control circuit further includes: a first reset sub-circuit and a second reset sub-circuit, the first reset sub-circuit is respectively connected to the second scan signal terminal, the initial power terminal and the first node;
  • the second reset sub-circuit is respectively connected to the second node, the third scan signal terminal and the reset power terminal; before the data writing phase, the method further includes:
  • the potential of the second scan signal provided by the second scan signal terminal and the potential of the third scan signal provided by the third scan signal terminal are both the first potential
  • the first reset sub-circuit responds to all
  • the second scan signal outputs the initial power signal provided by the initial power supply terminal to the first node
  • the second reset sub-circuit outputs the reset to the second node in response to the third scan signal
  • the reset power signal provided by the power terminal, wherein the potential of the initial power signal is the first potential
  • the potential of the third scan signal provided by the third scan signal terminal is the first potential
  • the second reset sub-circuit sends the signal to the second node in response to the third scan signal. Output the reset power signal.
  • the potential of the DC power supply signal is a second potential, and the second potential is a high potential relative to the first potential.
  • a display substrate includes: a plurality of pixel units, among the plurality of pixel units, at least one of the pixel units includes: a light-emitting element, and a device connected to the light-emitting element
  • the display substrate includes: a plurality of pixel units, among the plurality of pixel units, at least one of the pixel units includes: a light-emitting element, and a device connected to the light-emitting element.
  • each of the pixel units includes: a light-emitting element, and the pixel circuit described in the foregoing aspect connected to the light-emitting element.
  • the light-emitting element is an organic light-emitting diode.
  • a display device including: a driving circuit, and the display substrate as described in the above aspect.
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of still another pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of still another pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of still another pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 7 is a flowchart of a driving method of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 8 is a flowchart of another method for driving a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 9 is a timing diagram of each signal terminal in a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 10 is an equivalent circuit diagram of a pixel circuit in the reset stage provided by an embodiment of the present disclosure.
  • FIG. 11 is an equivalent circuit diagram of a pixel circuit in the data writing stage according to an embodiment of the present disclosure.
  • FIG. 12 is an equivalent circuit diagram of a pixel circuit in the light-emitting stage provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 14 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • the transistors used in the embodiments of the present disclosure are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable.
  • the source electrode is referred to as the first electrode and the drain electrode is referred to as the second electrode; alternatively, the drain electrode may be referred to as the first electrode and the source electrode is referred to as the second electrode.
  • the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain.
  • the switching transistor used in the embodiment of the present disclosure may be a P-type switching transistor, which is turned on when the gate is at a low level, and is turned off when the gate is at a high level.
  • multiple signals in each embodiment of the present disclosure correspond to a first potential and a second potential.
  • the first potential and the second potential only represent that the potential of the signal has two state quantities, and does not mean that the first potential or the second potential in the full text has a specific value.
  • multiple pixel units included in the OLED display panel can all be connected to the same DC power terminal, that is, one DC power terminal can drive the entire OLED display panel.
  • the size of the OLED display panel is larger (that is, the number of pixel units included in the OLED display panel is larger), the number of pixel units that need to be driven by a DC power supply terminal will be larger, and the signal routing is provided for the DC power supply terminal That will be longer.
  • the potential of the DC power signal provided by the DC power supply terminal may continue to decrease with the extension of the signal trace, that is, the DC power signal will cause a voltage drop problem.
  • the threshold voltage of the driving transistor included in each pixel unit may be different due to factors such as the process and materials when the transistor is fabricated, and the threshold voltage of each driving transistor may drift to different degrees as the use time increases. .
  • the driving current output by the driving transistor to the OLED is related to the potential of the DC power signal provided by the DC power terminal and the threshold voltage of the driving transistor, it may be affected by factors such as the voltage drop of the DC power signal and the threshold voltage drift of the driving transistor. This causes differences in the driving currents output by the driving transistors in each pixel unit, which in turn leads to poor display brightness uniformity of the OLED display panel and poor display effects.
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • the pixel circuit may include: a light emission control circuit 10, a compensation circuit 20 and a driving circuit 30.
  • the light emission control circuit 10 can be respectively connected to the first scan signal terminal S1, the light emission control signal terminal EM, the data signal terminal D, the DC power supply terminal VDD, the first node P1, the second node P2, the third node P3 and the light emitting element O1. .
  • the light emission control circuit 10 can control the potential of the first node P1 in response to the first scan signal from the first scan signal terminal S1 and the data signal from the data signal terminal D.
  • the light emission control circuit 10 can also respond to the light emission control signal from the light emission control signal terminal EM, output the DC power signal provided by the DC power terminal VDD to the second node P2, and control the on and off of the third node P3 and the light emitting element O1.
  • the light emission control circuit 10 may control the potential of the first node P1 according to the data signal provided by the data signal terminal D when the potential of the first scan signal provided by the first scan signal terminal S1 is the first potential, for example, light emission control
  • the circuit 10 may output a data signal to the first node P1.
  • the light emission control circuit 10 can also output the DC power signal provided by the DC power supply terminal VDD to the second node P2 when the light emission control signal provided by the light emission control signal terminal EM is at the first potential, and control the third node P3 and the light emitting element O1 is turned on.
  • the potential of the DC power signal may be a second potential, and the second potential may be a high potential relative to the first potential.
  • the compensation circuit 20 can be connected to the first node P1 and the second node P2 respectively.
  • the compensation circuit 20 can adjust the potential of the first node P1 according to the potential of the second node P2.
  • the compensation circuit 20 can adjust the potential of the first node P1 according to the potential of the second node P2 through a coupling effect (that is, the characteristic that the potential difference between the two ends of the compensation circuit 20 cannot change suddenly).
  • the light emission control circuit 10 can output the DC power signal to the second node P2 and control the third node P3 and the light emitting element when the potential of the light emission control signal is the first potential, that is, when the OLED is driven to emit light. O1 is turned on. Therefore, when the OLED is driven to emit light, the potential of the second node P2 is the potential of the DC power signal, and the potential of the third node P3 is the potential of the anode of the light-emitting element O1.
  • the driving circuit 30 may be connected to the first node P1, the second node P2, and the third node P3, respectively.
  • the driving circuit 30 can output a driving signal to the third node P3 in response to the potential of the first node P1 and the potential of the second node P2.
  • the driving circuit 30 may output a driving signal to the third node P3 according to the potential of the first node P1 and the potential of the second node P2 when the potential of the first node P1 is the first potential, and the driving signal is It is a signal for driving the light-emitting element O1 to emit light.
  • the compensation circuit 20 adjusts the potential of the first node P1 based on the potential of the second node P2 to make the drive circuit 30
  • the output driving signal is independent of the potential of the second node P2.
  • the driving signal output by the driving circuit 30 to the light-emitting element O1 is independent of the potential of the DC power signal, thereby solving the problem that the voltage drop at the DC power terminal causes the display panel to display The problem of uneven brightness.
  • the embodiments of the present disclosure provide a pixel circuit, which includes a light emission control circuit, a compensation circuit, and a driving circuit. Since the light-emitting control circuit can output the DC power signal provided by the DC power terminal to the second node, and control the third node to be turned on with the light-emitting element, the compensation circuit can adjust the potential of the first node according to the potential of the second node. When the circuit is driven, the potential finally written to the first node is only related to the threshold voltage of the driving transistor, the potential of the data signal provided by the data signal terminal, and the potential of the second node.
  • the drive signal output by the drive circuit is related to the potential difference between the first node and the second node, the drive signal output by the drive circuit can be made independent of the potential of the second node, that is, independent of the DC power signal, thereby avoiding
  • the pixel circuit provided in the embodiments of the present disclosure can ensure a better display effect of the display panel.
  • the potential that the light emission control circuit finally writes to the first node is also related to the threshold voltage of the driving transistor, it is also possible to make the driving signal output by the driving circuit independent of the threshold voltage of the driving transistor. Therefore, the problem of uneven display brightness due to different or drifting threshold voltages of the driving transistors can be avoided, and the display effect of the display panel is further ensured.
  • FIG. 2 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • the compensation circuit 20 may include a storage capacitor C1.
  • One end of the storage capacitor C1 can be connected to the first node P1, and the other end of the storage capacitor C1 can be connected to the second node P2.
  • the storage capacitor C1 can adjust the potential of the first node P1 according to the potential of the second node P2 through its coupling effect.
  • the light emission control circuit 10 may include: a data writing sub-circuit 101, a compensation sub-circuit 102, and a light-emission control sub-circuit 103.
  • the data writing sub-circuit 101 may be connected to the first scan signal terminal S1, the data signal terminal D, and the third node P3, respectively.
  • the data writing sub-circuit 101 can output a data signal to the third node P3 in response to the first scan signal.
  • the data writing sub-circuit 101 may output a data signal to the third node P3 when the potential of the first scan signal is the first potential.
  • the compensation sub-circuit 102 may be connected to the first scan signal terminal S1, the first node P1, and the fourth node P4, respectively.
  • the compensation sub-circuit 102 can control the on-off of the first node P1 and the fourth node P4 in response to the first scan signal, and the fourth node P4 can also be connected to the first pole of the driving transistor T1 in the driving circuit 30.
  • the compensation sub-circuit 102 may control the first node P1 and the fourth node P4 to conduct when the potential of the first scan signal is the first potential.
  • the compensation sub-circuit 102 can write the threshold voltage of the driving transistor included in the driving circuit 30 to the first node P1, so that the driving signal output by the driving circuit 30 is independent of the threshold voltage of the driving transistor T1. The problem of uneven display brightness caused by the threshold voltage is avoided, and the display effect of the display panel is further improved.
  • the light emission control sub-circuit 103 can be connected to the light emission control signal terminal EM, the DC power supply terminal VDD, the second node P2, the third node P3, the fourth node P4, and the light emitting element O1, respectively.
  • the lighting control sub-circuit 103 can respond to the lighting control signal, output a DC power signal to the second node P2, control the on and off of the second node P2 and the fourth node P4, and control the on and off of the third node P3 and the light-emitting element O1 .
  • the lighting control sub-circuit 103 may output a DC power signal to the second node P2 when the potential of the lighting control signal is the first potential, control the second node P2 and the fourth node P4 to conduct, and control the third node P3 is connected to the light-emitting element O1.
  • FIG. 3 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • the data writing sub-circuit 101 may include: a data writing transistor M1.
  • the gate of the data writing transistor M1 can be connected to the first scan signal terminal S1
  • the first electrode of the data writing transistor M1 can be connected to the data signal terminal D
  • the second electrode of the data writing transistor M1 can be connected to the first scan signal terminal S1.
  • the compensation sub-circuit 102 may include a compensation transistor K1.
  • the gate of the compensation transistor K1 may be connected to the first scan signal terminal S1, the first pole of the compensation transistor K1 may be connected to the first node P1, and the second pole of the compensation transistor K1 may be connected to the fourth node P4.
  • the light emission control sub-circuit 103 may include: a first light emission control transistor L1, a second light emission control transistor L2, and a third light emission control transistor L3.
  • the gate of the first light emission control transistor L1 can be connected to the light emission control signal terminal EM, the first electrode of the first light emission control transistor L1 can be connected to the DC power supply terminal VDD, and the second electrode of the first light emission control transistor L1 can be Connect with the second node P2.
  • the gate of the second light emission control transistor L2 can be connected to the light emission control signal terminal EM, the first electrode of the second light emission control transistor L2 can be connected to the second node P2, and the second electrode of the second light emission control transistor L2 can be Connected to the fourth node P4.
  • the gate of the third light emission control transistor L3 may be connected to the light emission control signal terminal EM, the first electrode of the third light emission control transistor L3 may be connected to the third node P3, and the second electrode of the third light emission control transistor L3 may be Connect to the light-emitting element O1.
  • FIG. 4 is a schematic structural diagram of still another pixel circuit provided by an embodiment of the present disclosure.
  • the light emission control circuit 10 may further include: a first reset sub-circuit 104 and a second reset sub-circuit 105.
  • the first reset sub-circuit 104 may be connected to the second scan signal terminal S2, the initial power terminal Vinit, and the first node P1, respectively.
  • the first reset sub-circuit 104 may output the initial power signal provided by the initial power terminal Vinit to the first node P1 in response to the second scan signal provided by the second scan signal terminal S2.
  • the first reset sub-circuit 104 may output the initial power signal provided by the initial power terminal Vinit to the first node P1 when the potential of the second scan signal is the first potential, and the potential of the initial power signal may be the first Potential.
  • the first reset sub-circuit 104 can output the initial power signal at the first potential to the first node P1, it can also ensure that each driving circuit 30 starts working from the same bias voltage state, which further improves the display effect of the display panel.
  • the second reset sub-circuit 105 can be respectively connected to the third scan signal terminal S3, the reset power terminal VSS, and the second node P2.
  • the second reset sub-circuit 105 can output the reset power signal provided by the reset power terminal VSS to the second node P2 in response to the third scan signal provided by the third scan signal terminal S3.
  • the second reset sub-circuit 105 may output the reset power signal provided by the reset power terminal VSS to the second node P2 when the potential of the third scan signal is the first potential, and the potential of the reset power signal may be zero.
  • FIG. 5 is a schematic structural diagram of still another pixel circuit provided by an embodiment of the present disclosure.
  • the first reset sub-circuit 104 may include: a first reset transistor F1.
  • the gate of the first reset transistor F1 can be connected to the second scan signal terminal S2, the first electrode of the first reset transistor F1 can be connected to the initial power supply terminal Vinit, and the second electrode of the first reset transistor F1 can be connected to the first A node P1 is connected.
  • the second reset sub-circuit 105 may include: a second reset transistor F2.
  • the gate of the second reset transistor F2 can be connected to the third scan signal terminal S3, the first electrode of the second reset transistor F2 can be connected to the reset power terminal VSS, and the second electrode of the second reset transistor F2 can be connected to the Two-node P2 connection.
  • FIG. 6 is a schematic structural diagram of still another pixel circuit provided by an embodiment of the present disclosure.
  • the driving circuit 30 may include: a driving transistor T1.
  • the gate of the driving transistor T1 can be connected to the first node P1, the first electrode of the driving transistor T1 can be connected to the second node P2, and the second electrode of the driving transistor T1 can be connected to the third node P3.
  • the first pole of the driving transistor T1 can be directly connected to the fourth node P4, and further can be connected to the second node P2 through the second light-emitting control transistor L2.
  • the light-emitting element O1 may also be connected to the reset power terminal VSS, and the potential of the reset power signal provided by the reset power terminal VSS may be a third potential, for example, 0.
  • the third potential may be a high potential relative to the first potential, and the third potential may be a low potential relative to the second potential.
  • each transistor is a P-type transistor, and the first potential is a low potential relative to the second potential.
  • the respective transistors may also be N-type transistors.
  • the first potential may be a high potential relative to the second potential.
  • the embodiments of the present disclosure provide a pixel circuit, which includes a light emission control circuit, a compensation circuit, and a driving circuit. Since the light-emitting control circuit can output the DC power signal provided by the DC power terminal to the second node, and control the third node to be turned on with the light-emitting element, the compensation circuit can adjust the potential of the first node according to the potential of the second node. When the circuit is driven, the potential finally written to the first node is only related to the threshold voltage of the driving transistor, the potential of the data signal provided by the data signal terminal, and the potential of the second node.
  • the drive signal output by the drive circuit is related to the potential difference between the first node and the second node, the drive signal output by the drive circuit can be made independent of the potential of the second node, that is, independent of the DC power signal, thereby avoiding
  • the pixel circuit provided in the embodiments of the present disclosure can ensure a better display effect of the display panel.
  • FIG. 7 is a flowchart of a method for driving a pixel circuit according to an embodiment of the present disclosure, which can be applied to the pixel circuit shown in any one of FIGS. 1 to 6. As shown in Figure 7, the method may include:
  • Step 401 In the data writing stage, the potential of the first scan signal provided by the first scan signal terminal is the first potential, and the light emitting control circuit controls the first node according to the data signal provided by the data signal terminal in response to the first scan signal The potential.
  • Step 402 During the lighting stage, the potential of the lighting control signal provided by the lighting control signal terminal is the first potential, and the lighting control circuit responds to the lighting control signal to output the DC power signal provided by the DC power terminal to the second node and control the third node
  • the compensation circuit adjusts the potential of the first node according to the potential of the second node
  • the driving circuit responds to the potential of the first node and the potential of the second node to output a driving signal to the third node.
  • the embodiments of the present disclosure provide a driving method for a pixel circuit.
  • the light-emitting control circuit can output the DC power signal provided by the DC power terminal to the second node or control the third node and the light-emitting element to conduct
  • the compensation circuit can adjust the potential of the first node according to the potential of the second node. Therefore, when the pixel circuit is driven, the potential finally written to the first node is only equal to the threshold voltage of the driving transistor and the data signal terminal.
  • the potential of the provided data signal is related to the potential of the second node.
  • the drive signal output by the drive circuit is related to the potential difference between the first node and the second node, the drive signal output by the drive circuit can be made independent of the potential of the second node, that is, independent of the DC power signal, thereby avoiding
  • the driving method provided by the embodiments of the present disclosure can ensure a better display effect of the display panel.
  • the light emission control circuit 10 may include: a data writing sub-circuit 101, a compensation sub-circuit 102 and a light emission control sub-circuit 103.
  • the above step 401 may include: in the data writing stage, the potential of the first scan signal is the first potential.
  • the data signal terminal D can output a data signal to the first node P1 through the data writing sub-circuit 101, the driving circuit 30 and the compensation sub-circuit 102.
  • the above step 402 may include: in the light-emitting phase, the potential of the light-emitting control signal is the first potential, the DC power supply terminal VDD may output the DC power signal to the second node P2 through the light-emitting control sub-circuit 103, and the second node P2 and the fourth node P2 The node P4 is turned on, and the third node P3 and the light emitting element O1 can be turned on.
  • the light emission control circuit 10 may further include: a first reset sub-circuit 104 and a second reset sub-circuit 105.
  • the first reset sub-circuit 104 can be respectively connected to the second scan signal terminal S2, the initial power terminal Vinit and the first node P1.
  • the second reset sub-circuit 105 is respectively connected to the third scan signal terminal S3, the reset power terminal VSS and the second node P2.
  • the method may further include:
  • Step 403 In the reset stage, the potential of the second scan signal provided by the second scan signal terminal and the potential of the third scan signal provided by the third scan signal terminal are the first potential, and the light emitting control circuit responds to the second scan signal and the third scan signal.
  • the scan signal outputs the initial power signal provided by the initial power terminal to the first node, and outputs the reset power signal provided by the reset power terminal to the second node.
  • the first reset sub-circuit 104 may output the initial power signal provided by the initial power terminal to the first node in response to the second scan signal.
  • the second reset sub-circuit 105 may output the reset power signal provided by the reset power terminal to the second node in response to the third scan signal.
  • the potential of the third scan signal provided by the third scan signal terminal is also the first potential
  • the second reset sub-circuit 105 in the light emission control circuit can respond to the first potential.
  • the potential of the initial power signal is the first potential.
  • the pixel circuit can also output the initial power signal at the first potential to the first node P1 before the data writing stage, it can also ensure that the drive transistors included in each drive circuit all start to work from the same bias state, and further Improved the display effect of the display panel.
  • the transistors in the pixel circuit are all P-type transistors
  • the potential of the initial power signal provided by the initial power terminal Vint is the first potential
  • the DC power signal provided by the DC power terminal VDD The potential is the second potential
  • the first potential is a low potential relative to the second potential.
  • FIG. 9 is a timing diagram of each signal terminal in a pixel circuit provided by an embodiment of the present disclosure.
  • the potential of the second scan signal provided by the second scan signal terminal S2 and the potential of the third scan signal provided by the third scan signal terminal S3 are both the first potential, and the first reset The transistor F1 and the second reset transistor F2 are turned on.
  • the initial power terminal Vinit outputs the initial power signal at the first potential to the first node P1 through the first reset transistor F1 to reset the first node P1 and drive the transistor T1 to turn on.
  • the reset power terminal VSS outputs a reset power signal to the second node P2 through the second reset transistor F2, so as to reset the second node P2. Assuming that the potential Vss of the reset power signal is zero, the potential of the second node P2 is zero.
  • the potential of the first scan signal provided by the first scan signal terminal S1 and the potential of the light emission control signal provided by the light emission control signal terminal EM are both the second potential, and the data is written
  • the input transistor M1, the compensation transistor K1, the first light emission control transistor L1, the second light emission control transistor L2, and the third light emission control transistor L3 are all turned off, and the light emitting element O1 does not emit light.
  • FIG. 10 for the equivalent circuit diagram of the pixel circuit in the reset stage t1.
  • the potential of the second scan signal jumps to the second potential, and the first reset transistor F1 is turned off.
  • the potential of the third scan signal remains at the first potential, and the second reset transistor F2 remains on.
  • the potential of the first scan signal jumps to the first potential, and the compensation transistor K1 and the data writing transistor M1 are turned on.
  • the driving transistor T1 Since the driving transistor T1 is turned on during the reset phase t1, the data signal terminal D can output the data signal to the first node P1 through the data writing transistor M1, the driving transistor T1, and the compensation transistor K1 during the data writing phase t2 until the first node P1
  • the potential of a node P1 becomes: Vdata+Vth, Vdata is the potential of the data signal, Vth is the threshold voltage of the driving transistor T1, and Vth is less than zero.
  • the second reset transistor F2 since the second reset transistor F2 is turned on, the potential of the second node P2 can be maintained at Vss.
  • the potential of the light emission control signal remains at the second potential
  • the first light emission control transistor L1, the second light emission control transistor L2, and the third light emission control transistor L3 are all kept off, and the light emitting element O1 remains Does not emit light.
  • the potential of the first scan signal and the potential of the third scan signal are both the second potential.
  • the potential of the first scan signal first jumps to the second potential, so that the data writing transistor M1 and the compensation transistor K1 are turned off.
  • the potential of the third scan signal jumps to the second potential again, so that the second reset transistor F2 is turned off.
  • the potential of the light-emission control signal provided by the light-emission control signal terminal EM jumps to the first potential, the first light-emission control transistor L1, the second light-emission control transistor L2, and the third light-emission control
  • the transistor L3 is turned on, the second node P2 and the fourth node P3 are turned on, and the third node P3 and the light emitting element O1 are turned on.
  • the DC power supply terminal VDD can output a DC power signal to the second node P2 through the first light emitting control transistor L1, Furthermore, the DC power signal is output to the fourth node P4 through the second light-emitting control transistor L2.
  • the potential of the second node P2 and the fourth node P4 becomes Vdd. Since the source and drain of the driving transistor T1 are the same in the manufacturing process (ie, the manufacturing process), at this time, the fourth node P4 can be used as the source of the driving transistor T1, and correspondingly, the source potential Vs of the driving transistor T1 That can become Vdd. Since the potential of the second node P2 is Vss in the data writing phase t2, it can be determined that the potential change of the second node P2 is Vdd-Vss in the light-emitting phase t3.
  • the compensation transistor K1 Since the compensation transistor K1 is turned off, during the light-emitting phase t3, under the coupling effect of the storage capacitor C1, the potential of the first node P1 (that is, the gate of the driving transistor T1) can become: Vdd-Vss+Vdata+ Vth, the driving transistor T1 is turned on.
  • the equivalent circuit diagram of the pixel circuit in the light-emitting stage t3, refer to FIG. 12.
  • the driving transistor T1 can output a driving signal to the third node P3 according to the potential of the first node P1 and the potential of the second node P2, so as to drive the light-emitting element O1 to emit light.
  • the driving current I OLED generated by the driving transistor T1 can satisfy:
  • I OLED ⁇ (Vgs-Vth) 2 Formula (1).
  • ⁇ satisfies: ⁇ n is the carrier mobility of the driving transistor T1, C ox is the capacitance of the gate insulating layer of the driving transistor T1, W/L is the aspect ratio of the driving transistor T1, and the ⁇ is determined after the display panel manufacturing process constant.
  • the driving current I OLED output by the driving transistor T1 can be calculated as:
  • the embodiments of the present disclosure provide a driving method for a pixel circuit.
  • the light-emitting control circuit can output the DC power signal provided by the DC power terminal to the second node or control the third node and the light-emitting element to conduct
  • the compensation circuit can adjust the potential of the first node according to the potential of the second node. Therefore, when the pixel circuit is driven, the potential finally written to the first node is only equal to the threshold voltage of the driving transistor and the data signal terminal.
  • the potential of the provided data signal is related to the potential of the second node.
  • the drive signal output by the drive circuit is related to the difference between the potentials of the first node and the second node, the drive signal output by the drive circuit can be made independent of the potential of the second node, that is, independent of the DC power signal. Therefore, the problem of uneven display brightness of the display panel caused by the voltage drop of the DC power supply terminal is avoided, and the display effect of the display panel is better.
  • the display substrate may include: a plurality of pixel units px. At least one pixel unit px of the plurality of pixel units px may include a light-emitting element, and the pixel circuit provided in the above-mentioned embodiment connected to the light-emitting element. For example, the pixel circuit shown in any one of FIGS. 1 to 6.
  • each pixel unit px in the display substrate may include: a light-emitting element, and the pixel circuit provided in the above-mentioned embodiment connected to the light-emitting element.
  • the light-emitting element may be OLED or AMOLED.
  • an embodiment of the present disclosure also provides a display device. As shown in FIG. 14, the display device can drive a circuit, and the display substrate 100 provided in the above-mentioned embodiment connected to the drive circuit.
  • the display device may include a gate driving circuit 200 for providing scan signals, and a source driving circuit 300 for providing data signals.
  • the display device can be: OLED display device, AMOLED display device, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator and other products or components with display function.

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Abstract

提供了一种像素电路及其驱动方法、显示基板、显示装置。由于发光控制电路可以向第二节点输出直流电源端提供的直流电源信号，并控制第三节点与发光元件导通，补偿电路可以根据第二节点的电位调节第一节点的电位。因此在对像素电路进行驱动时，即可使得最终写入至第一节点的电位仅与驱动晶体管的阈值电压、数据信号端提供的数据信号的电位和第二节点的电位有关。并且，由于驱动电路输出的驱动信号与第一节点和第二节点电位之差有关，因此即可使得驱动电路输出的驱动信号与第二节点的电位无关，即与直流电源信号的电位无关。从而避免了由于直流电源端的电位因传输降低造成显示面板显示亮度不均匀的问题，显示面板显示效果较好。

Description

像素电路及其驱动方法、显示基板、显示装置
本公开要求于2019年4月22日提交的申请号为201910323658.9、发明名称为“像素电路及其驱动方法、显示基板、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别涉及一种像素电路及其驱动方法、显示基板、显示装置。
背景技术
有机发光二极管(organic light emitting diode，OLED)作为一种电流型发光器件，因其所具有的低能耗、自发光、快速响应和宽视角等特点而越来越多地被应用于高性能显示面板中。
相关技术中，OLED显示面板包括阵列排布的像素单元，每个像素单元包括：开关晶体管、驱动晶体管和OLED。开关晶体管可以将数据信号端提供的数据信号输出至驱动晶体管，驱动晶体管可以根据直流电源端提供的直流电源信号和该数据信号向OLED输出驱动电流以驱动OLED发光。
发明内容
本公开提供了一种像素电路及其驱动方法、显示基板、显示装置，所述技术方案如下：
一方面，提供了一种像素电路，所述像素电路包括：发光控制电路、补偿电路和驱动电路；
所述发光控制电路分别与第一扫描信号端、发光控制信号端、数据信号端、直流电源端、第一节点、第二节点、第三节点和发光元件连接，所述发光控制电路用于响应于来自所述第一扫描信号端的第一扫描信号和来自所述数据信号端的数据信号，控制所述第一节点的电位，以及用于响应于来自所述发光控制信号端的发光控制信号，向所述第二节点输出所述直流电源端提供的直流电源 信号，和控制所述第三节点与所述发光元件的通断；
所述补偿电路分别与所述第一节点和第二节点连接，所述补偿电路用于根据所述第二节点的电位调整所述第一节点的电位；
所述驱动电路分别与所述第一节点、所述第二节点和所述第三节点连接，所述驱动电路用于响应于所述第一节点的电位和所述第二节点的电位，向所述第三节点输出驱动信号。
可选的，所述补偿电路包括：存储电容；
所述存储电容的一端与所述第一节点连接，所述存储电容的另一端与所述第二节点连接。
可选的，所述驱动电路包括：驱动晶体管；
所述驱动晶体管的栅极与所述第一节点连接，所述驱动晶体管的第一极与所述第二节点连接，所述驱动晶体管的第二极与所述第三节点连接。
可选的，所述发光控制电路包括：数据写入子电路、补偿子电路和发光控制子电路；
所述数据写入子电路分别与所述第一扫描信号端、所述数据信号端和所述第三节点连接，所述数据写入子电路用于响应于所述第一扫描信号，向所述第三节点输出所述数据信号；
所述补偿子电路分别与所述第一扫描信号端、所述第一节点和所述第四节点连接，所述补偿子电路用于响应于所述第二扫描信号，控制所述第一节点与所述第四节点的通断，所述第四节点还与所述驱动电路中驱动晶体管的第一极连接；
所述发光控制子电路分别与所述发光控制信号端、所述直流电源端、所述第二节点、所述第四节点、所述第三节点和所述发光元件连接，所述发光控制子电路用于响应于所述发光控制信号，向所述第二节点输出所述直流电源信号，控制所述第二节点与所述第四节点的通断，以及控制所述第三节点与所述发光元件的通断。
可选的，所述数据写入子电路包括：数据写入晶体管；
所述数据写入晶体管的栅极与所述第一扫描信号端连接，所述数据写入晶体管的第一极与所述数据信号端连接，所述数据写入晶体管的第二极与所述第三节点连接。
可选的，所述补偿子电路包括：补偿晶体管；
所述补偿晶体管的栅极与所述第一扫描信号端连接，所述补偿晶体管的第一极与所述第一节点连接，所述补偿晶体管的第二极与所述第四节点连接。
可选的，所述发光控制子电路包括：第一发光控制晶体管和第二发光控制晶体管和第三发光控制晶体管；
所述第一发光控制晶体管的栅极与所述发光控制信号端连接，所述第一发光控制晶体管的第一极与所述直流电源端连接，所述第一发光控制晶体管的第二极与所述第二节点连接；
所述第二发光控制晶体管的栅极与所述发光控制信号端连接，所述第二发光控制晶体管的第一极与所述第二节点连接，所述第二发光控制晶体管的第二极与所述第四节点连接；
所述第三发光控制晶体管的栅极与所述发光控制信号端连接，所述第三发光控制晶体管的第一极与所述第三节点连接，所述第三发光控制晶体管的第二极与所述发光元件连接。
可选的，所述发光控制电路还包括：第一复位子电路和第二复位子电路；
所述第一复位子电路分别与第二扫描信号端、初始电源端和所述第一节点连接，所述第一复位子电路用于响应于来自所述第二扫描信号端的第二扫描信号，向所述第一节点输出所述初始电源端提供的初始电源信号；
所述第二复位子电路分别与所述第二节点、第三扫描信号端和复位电源端连接，所述第二复位子电路用于响应于来自所述第三扫描信号端的第三扫描信号，向所述第二节点输出所述复位电源端提供的复位电源信号。
可选的，所述第一复位子电路包括：第一复位晶体管；
所述第一复位晶体管的栅极与所述第二扫描信号端连接，所述第一复位晶体管的第一极与所述初始电源端连接，所述第一复位晶体管的第二极与所述第一节点连接；
可选的，所述第二复位子电路包括：第二复位晶体管；所述第二复位晶体管的栅极与所述第三扫描信号端连接，所述第二复位晶体管的第一极与所述复位电源端连接，所述第二复位晶体管的第二极与所述第二节点连接。
可选的，所述像素电路包括的晶体管均为P型晶体管。
另一方面，提供了一种像素电路的驱动方法，应用于如上述方面所述的像 素电路，所述方法包括：
数据写入阶段，第一扫描信号端提供的第一扫描信号的电位为第一电位，发光控制电路响应于所述第一扫描信号，根据数据信号端提供的数据信号，控制第一节点的电位；
发光阶段，发光控制信号端提供的发光控制信号的电位为第一电位，所述发光控制电路响应于所述发光控制信号，向第二节点输出直流电源端提供的直流电源信号，以及控制第三节点与发光元件导通，补偿电路根据第二节点的电位调节所述第一节点的电位，驱动电路响应于所述第一节点的电位和所述第二节点的电位，向所述第三节点输出驱动信号。
可选的，所述发光控制电路包括：数据写入子电路、补偿子电路和发光控制子电路；
在所述数据写入阶段，所述第一扫描信号的电位为第一电位，所述数据信号端通过所述数据写入子电路、所述驱动电路和所述补偿子电路向所述第一节点输出所述数据信号；
在所述发光阶段，所述发光控制信号的电位为第一电位，所述直流电源端通过所述发光控制子电路向所述第二节点输出所述直流电源信号，且所述第三节点与所述发光元件导通。
可选的，所述发光控制电路还包括：第一复位子电路和第二复位子电路，所述第一复位子电路分别与第二扫描信号端、初始电源端和所述第一节点连接；所述第二复位子电路分别与所述第二节点、第三扫描信号端和复位电源端连接；在所述数据写入阶段之前，所述方法还包括：
复位阶段，所述第二扫描信号端提供的第二扫描信号的电位和所述第三扫描信号端提供的第三扫描信号的电位均为第一电位，所述第一复位子电路响应于所述第二扫描信号，向所述第一节点输出所述初始电源端提供的初始电源信号，所述第二复位子电路响应于所述第三扫描信号，向所述第二节点输出所述复位电源端提供的复位电源信号，其中，所述初始电源信号的电位为第一电位；
在所述数据写入阶段，所述第三扫描信号端提供的第三扫描信号的电位为第一电位，所述第二复位子电路响应于所述第三扫描信号，向所述第二节点输出所述复位电源信号。
可选的，所述直流电源信号的电位为第二电位，所述第二电位相对于所述 第一电位为高电位。
又一方面，提供了一种显示基板，所述显示基板包括：多个像素单元，所述多个像素单元中，至少一个所述像素单元包括：发光元件，以及与所述发光元件连接的如上述方面所述的像素电路。
可选的，每个所述像素单元均包括：发光元件，以及与所述发光元件连接的如上述方面所述的像素电路。
可选的，所述发光元件为有机发光二极管。
再一方面，提供了一种显示装置，所述显示装置包括：驱动电路，以及如上述方面所述的显示基板。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种像素电路的结构示意图；
图2是本公开实施例提供的另一种像素电路的结构示意图；
图3是本公开实施例提供的又一种像素电路的结构示意图；
图4是本公开实施例提供的再一种像素电路的结构示意图；
图5是本公开实施例提供的再一种像素电路的结构示意图；
图6是本公开实施例提供的再一种像素电路的结构示意图；
图7是本公开实施例提供的一种像素电路的驱动方法的流程图；
图8是本公开实施例提供的另一种像素电路的驱动方法的流程图；
图9是本公开实施例提供的一种像素电路中各信号端的时序图；
图10是本公开实施例提供的一种像素电路在复位阶段的等效电路图；
图11是本公开实施例提供的一种像素电路在数据写入阶段的等效电路图；
图12是本公开实施例提供的一种像素电路在发光阶段的等效电路图；
图13是本公开实施例提供的一种显示基板的结构示意图；
图14是本公开实施例提供的一种显示装置的结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用本公开的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，将其中源极称为第一极，漏极称为第二极；或者，可以将漏极称为第一极，源极称为第二极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、且信号输出端为漏极。本公开实施例所采用的开关晶体管可以为P型开关晶体管，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止。此外，本公开各个实施例中的多个信号都对应有第一电位和第二电位。第一电位和第二电位仅代表该信号的电位有2个状态量，不代表全文中第一电位或第二电位具有特定的数值。
相关技术中，OLED显示面板包括的多个像素单元均可以与同一个直流电源端连接，即一个直流电源端可以驱动整个OLED显示面板。当OLED显示面板的尺寸较大(即OLED显示面板包括的像素单元的数量较多)时，一个直流电源端需要驱动的像素单元的数量即会较多，为该直流电源端设置的信号走线即会较长。受信号走线上寄生电容的影响，该直流电源端提供的直流电源信号的电位随着信号走线的延长可能会不断下降，即直流电源信号会产生电压降问题。另外，受制备晶体管时的工艺及材料等因素的影响，各个像素单元包括的驱动晶体管的阈值电压可能不同，且随着使用时间的延长，各个驱动晶体管的阈值电压可能还会发生不同程度的漂移。
由于驱动晶体管输出至OLED的驱动电流与直流电源端提供的直流电源信号的电位，以及驱动晶体管的阈值电压均有关，因此受直流电源信号的电压降以及驱动晶体管的阈值电压漂移等因素影响，可能造成各个像素单元中的驱动晶体管输出的驱动电流存在差异，进而导致OLED显示面板的显示亮度均一性较差，显示效果不好。
本公开实施例提供了一种像素电路，可以解决相关技术中OLED显示面板 的显示亮度均一性较差，显示效果不好的问题。图1是本公开实施例提供的一种像素电路的结构示意图。如图1所示，该像素电路可以包括：发光控制电路10、补偿电路20和驱动电路30。
该发光控制电路10可以分别与第一扫描信号端S1、发光控制信号端EM、数据信号端D、直流电源端VDD、第一节点P1、第二节点P2、第三节点P3和发光元件O1连接。该发光控制电路10可以响应于来自第一扫描信号端S1的第一扫描信号和来自数据信号端D的数据信号，控制第一节点P1的电位。该发光控制电路10还可以响应于来自发光控制信号端EM的发光控制信号，向第二节点P2输出直流电源端VDD提供的直流电源信号，和控制第三节点P3与发光元件O1的通断。
示例的，发光控制电路10可以在第一扫描信号端S1提供的第一扫描信号的电位为第一电位时，根据数据信号端D提供的数据信号，控制第一节点P1的电位，例如发光控制电路10可以向第一节点P1输出数据信号。发光控制电路10还可以在发光控制信号端EM提供的发光控制信号的电位为第一电位时，向第二节点P2输出直流电源端VDD提供的直流电源信号，并控制第三节点P3与发光元件O1导通。
在本公开实施例中，该直流电源信号的电位可以为第二电位，且该第二电位相对于第一电位可以为高电位。
该补偿电路20可以分别与第一节点P1和第二节点P2连接。该补偿电路20可以根据第二节点P2的电位调整第一节点P1的电位。
示例的，该补偿电路20可以通过耦合作用(即补偿电路20两端的电位差无法突变的特性)，根据第二节点P2的电位调整第一节点P1的电位。
在本公开实施例中，由于发光控制电路10可以在发光控制信号的电位为第一电位时，即在驱动OLED发光时，向第二节点P2输出直流电源信号以及控制第三节点P3和发光元件O1导通。因此可以使得在驱动OLED发光时，该第二节点P2的电位为直流电源信号的电位，该第三节点P3的电位为发光元件O1阳极的电位。
该驱动电路30可以分别与第一节点P1、第二节点P2和第三节点P3连接。该驱动电路30可以响应于第一节点P1的电位和第二节点P2的电位，向第三节点P3输出驱动信号。
示例的，该驱动电路30可以在第一节点P1的电位为第一电位时，根据该第一节点P1的电位和第二节点P2的电位，向第三节点P3输出驱动信号，该驱动信号即为用于驱动发光元件O1发光的信号。
由于该驱动电路30输出的驱动信号与第一节点P1和第二节点P2的电位差值有关，因此通过补偿电路20基于第二节点P2的电位调节第一节点P1的电位，可以使得驱动电路30输出的驱动信号与第二节点P2的电位无关。又由于该第二节点P2的电位为直流电源信号的电位，因此可以使得驱动电路30输出至发光元件O1的驱动信号与直流电源信号的电位无关，进而可以解决直流电源端电压降造成显示面板显示亮度不均一的问题。
综上所述，本公开实施例提供了一种像素电路，该像素电路包括发光控制电路、补偿电路和驱动电路。由于发光控制电路可以向第二节点输出直流电源端提供的直流电源信号，且控制第三节点与发光元件导通，补偿电路可以根据第二节点的电位调节第一节点的电位，因此在对像素电路进行驱动时，即可使最终写入至第一节点的电位仅与驱动晶体管的阈值电压、数据信号端提供的数据信号的电位和该第二节点的电位有关。并且，由于驱动电路输出的驱动信号与第一节点和第二节点的电位之差有关，因此即可使得驱动电路输出的驱动信号与第二节点的电位无关，即与直流电源信号无关，从而避免了由于直流电源端电压降造成显示面板显示亮度不均匀的问题，本公开实施例提供的像素电路可以确保显示面板显示效果较好。
另外，在本公开实施例中，由于发光控制电路最终写入至第一节点的电位还与驱动晶体管的阈值电压有关，因此还可以使得驱动电路输出的驱动信号与驱动晶体管的阈值电压也无关，从而还可以避免由于驱动晶体管的阈值电压不同或漂移造成显示亮度不均匀的问题，进一步保证了显示面板的显示效果。
可选的，图2是本公开实施例提供的另一种像素电路的结构示意图。如图2所示，该补偿电路20可以包括：存储电容C1。
该存储电容C1的一端可以与第一节点P1连接，该存储电容C1的另一端可以与第二节点P2连接。相应的，该存储电容C1可以通过其耦合作用，根据第二节点P2的电位调节第一节点P1的电位。
如图2所示，该发光控制电路10可以包括：数据写入子电路101、补偿子 电路102和发光控制子电路103。
该数据写入子电路101可以分别与第一扫描信号端S1、数据信号端D和第三节点P3连接。该数据写入子电路101可以响应于第一扫描信号，向第三节点P3输出数据信号。
示例的，该数据写入子电路101可以在第一扫描信号的电位为第一电位时，向第三节点P3输出数据信号。
该补偿子电路102可以分别与第一扫描信号端S1、第一节点P1和第四节点P4连接。该补偿子电路102可以响应于第一扫描信号，控制第一节点P1与第四节点P4的通断，该第四节点P4还可以与驱动电路30中的驱动晶体管T1的第一极连接。
示例的，该补偿子电路102可以在第一扫描信号的电位为第一电位时，控制第一节点P1与第四节点P4导通。相应的，该补偿子电路102即可以将驱动电路30包括的驱动晶体管的阈值电压写入至第一节点P1，进而即可以使得驱动电路30输出的驱动信号与驱动晶体管T1的阈值电压也无关，避免了由于阈值电压造成显示亮度不均匀的问题，进一步改善了显示面板的显示效果。
该发光控制子电路103可以分别与发光控制信号端EM、直流电源端VDD、第二节点P2、第三节点P3、第四节点P4和发光元件O1连接。该发光控制子电路103可以响应于发光控制信号，向第二节点P2输出直流电源信号，控制第二节点P2与第四节点P4的通断，以及控制第三节点P3与发光元件O1的通断。
示例的，该发光控制子电路103可以在发光控制信号的电位为第一电位时，向第二节点P2输出直流电源信号，控制第二节点P2与第四节点P4导通，以及控制第三节点P3与发光元件O1导通。
图3是本公开实施例提供的又一种像素电路的结构示意图。如图3所示，该数据写入子电路101可以包括：数据写入晶体管M1。
该数据写入晶体管M1的栅极可以与第一扫描信号端S1连接，该数据写入晶体管M1的第一极可以与数据信号端D连接，该数据写入晶体管M1的第二极可以与第三节点P3连接。
可选的，参考图3，该补偿子电路102可以包括：补偿晶体管K1。
该补偿晶体管K1的栅极可以与第一扫描信号端S1连接，该补偿晶体管K1的第一极可以与第一节点P1连接，该补偿晶体管K1的第二极可以与第四节点 P4连接。
可选的，参考图3，该发光控制子电路103可以包括：第一发光控制晶体管L1、第二发光控制晶体管L2和第三发光控制晶体管L3。
该第一发光控制晶体管L1的栅极可以与发光控制信号端EM连接，该第一发光控制晶体管L1的第一极可以与直流电源端VDD连接，该第一发光控制晶体管L1的第二极可以与第二节点P2连接。
该第二发光控制晶体管L2的栅极可以与发光控制信号端EM连接，该第二发光控制晶体管L2的第一极可以与第二节点P2连接，该第二发光控制晶体管L2的第二极可以与第四节点P4连接。
该第三发光控制晶体管L3的栅极可以与发光控制信号端EM连接，该第三发光控制晶体管L3的第一极可以与第三节点P3连接，该第三发光控制晶体管L3的第二极可以与发光元件O1连接。
图4是本公开实施例提供的再一种像素电路的结构示意图。如图4所示，该发光控制电路10还可以包括：第一复位子电路104和第二复位子电路105。
该第一复位子电路104可以分别与第二扫描信号端S2、初始电源端Vinit以及第一节点P1连接。该第一复位子电路104可以响应于第二扫描信号端S2提供的第二扫描信号，向第一节点P1输出初始电源端Vinit提供的初始电源信号。
示例的，该第一复位子电路104可以在第二扫描信号的电位为第一电位时，向第一节点P1输出初始电源端Vinit提供的初始电源信号，该初始电源信号的电位可以为第一电位。
由于第一复位子电路104可以向第一节点P1输出处于第一电位的初始电源信号，因此还可以保证各个驱动电路30均从相同的偏压状态开始工作，进一步改善了显示面板的显示效果。
该第二复位子电路105可以分别与第三扫描信号端S3、复位电源端VSS以及第二节点P2连接。该第二复位子电路105可以响应于第三扫描信号端S3提供的第三扫描信号，向第二节点P2输出复位电源端VSS提供的复位电源信号。
示例的，该第二复位子电路105可以在第三扫描信号的电位为第一电位时，向第二节点P2输出复位电源端VSS提供的复位电源信号，该复位电源信号的电位可以为0。
图5是本公开实施例提供的再一种像素电路的结构示意图。如图5所示，该第一复位子电路104可以包括：第一复位晶体管F1。
该第一复位晶体管F1的栅极可以与第二扫描信号端S2连接，该第一复位晶体管F1的第一极可以与初始电源端Vinit连接，该第一复位晶体管F1的第二极可以与第一节点P1连接。
可选的，参考图5，该第二复位子电路105可以包括：第二复位晶体管F2。
该第二复位晶体管F2的栅极可以与第三扫描信号端S3连接，该第二复位晶体管F2的第一极可以与复位电源端VSS连接，该第二复位晶体管F2的第二极可以与第二节点P2连接。
图6是本公开实施例提供的再一种像素电路的结构示意图。如图6所示，该驱动电路30可以包括：驱动晶体管T1。
该驱动晶体管T1的栅极可以与第一节点P1连接，该驱动晶体管T1的第一极可以与第二节点P2连接，该驱动晶体管T1的第二极可以与第三节点P3连接。其中，该驱动晶体管T1的第一极可以直接与第四节点P4连接，进而可以通过该第二发光控制晶体管L2与该第二节点P2连接。
参考图2至图6可以看出，该发光元件O1还可以与复位电源端VSS连接，该复位电源端VSS提供的复位电源信号的电位可以为第三电位，例如可以为0。并且，该第三电位相对于第一电位可以为高电位，该第三电位相对于第二电位可以为低电位。
需要说明的是，在上述实施例中，均是以各个晶体管为P型晶体管，且第一电位为相对于该第二电位低电位为例进行的说明。当然，该各个晶体管还可以采用N型晶体管，当该各个晶体管采用N型晶体管时，该第一电位相对于该第二电位可以为高电位。
综上所述，本公开实施例提供了一种像素电路，该像素电路包括发光控制电路、补偿电路和驱动电路。由于发光控制电路可以向第二节点输出直流电源端提供的直流电源信号，且控制第三节点与发光元件导通，补偿电路可以根据第二节点的电位调节第一节点的电位，因此在对像素电路进行驱动时，即可使最终写入至第一节点的电位仅与驱动晶体管的阈值电压、数据信号端提供的数据信号的电位和第二节点的电位有关。并且，由于驱动电路输出的驱动信号与第一节点和第二节点的电位之差有关，因此即可使得驱动电路输出的驱动信号 与第二节点的电位无关，即与直流电源信号无关，从而避免了由于直流电源端电压降造成显示面板显示亮度不均匀的问题，本公开实施例提供的像素电路可以确保显示面板显示效果较好。
图7是本公开实施例提供的一种像素电路的驱动方法流程图，可以应用于如图1至图6任一所示的像素电路中。如图7所示，该方法可以包括：
步骤401、数据写入阶段，第一扫描信号端提供的第一扫描信号的电位为第一电位，发光控制电路响应于该第一扫描信号，根据数据信号端提供的数据信号，控制第一节点的电位。
步骤402、发光阶段，发光控制信号端提供的发光控制信号的电位为第一电位，发光控制电路响应于发光控制信号，向第二节点输出直流电源端提供的直流电源信号，以及控制第三节点与发光元件导通，补偿电路根据第二节点的电位调节第一节点的电位，驱动电路响应于第一节点的电位和第二节点的电位，向第三节点输出驱动信号。
综上所述，本公开实施例提供了一种像素电路的驱动方法，由于在发光阶段，发光控制电路可以向第二节点输出直流电源端提供的直流电源信号或控制第三节点与发光元件导通，补偿电路可以根据第二节点的电位调节第一节点的电位，因此在对像素电路进行驱动时，即可使得最终写入至第一节点的电位仅与驱动晶体管的阈值电压、数据信号端提供的数据信号的电位和第二节点的电位有关。并且，由于驱动电路输出的驱动信号与第一节点和第二节点的电位之差有关，因此即可使得驱动电路输出的驱动信号与第二节点的电位无关，即与直流电源信号无关，从而避免了由于直流电源端的电压降造成的显示面板显示亮度不均匀的问题，本公开实施例提供的驱动方法可以确保显示面板显示效果较好。
可选的，参考图2至图6，发光控制电路10可以包括：数据写入子电路101、补偿子电路102和发光控制子电路103。
相应的，上述步骤401即可以包括：在数据写入阶段，第一扫描信号的电位为第一电位。数据信号端D可以通过数据写入子电路101、驱动电路30和补偿子电路102向第一节点P1输出数据信号。
上述步骤402即可以包括：在发光阶段，发光控制信号的电位为第一电位， 直流电源端VDD可以通过发光控制子电路103向第二节点P2输出直流电源信号，且第二节点P2与第四节点P4导通，第三节点P3与发光元件O1可以导通。
可选的，参考图4至图6，该发光控制电路10还可以包括：第一复位子电路104和第二复位子电路105。且该第一复位子电路104可以分别与第二扫描信号端S2、初始电源端Vinit以及第一节点P1连接。该第二复位子电路105分别与第三扫描信号端S3、复位电源端VSS以及第二节点P2连接。相应的，参考图8，在数据写入阶段之前，即在上述步骤401之前，该方法还可以包括：
步骤403、复位阶段，第二扫描信号端提供的第二扫描信号的电位和第三扫描信号端提供的第三扫描信号的电位为第一电位，发光控制电路响应于第二扫描信号和第三扫描信号，向第一节点输出初始电源端提供的初始电源信号，并向第二节点输出复位电源端提供的复位电源信号。
例如，该第一复位子电路104可以响应于第二扫描信号，向第一节点输出初始电源端提供的初始电源信号。第二复位子电路105可以响应于第三扫描信号，向第二节点输出复位电源端提供的复位电源信号。
并且，在上述步骤402所示的数据写入阶段，该第三扫描信号端提供的第三扫描信号的电位也为第一电位，发光控制电路中的第二复位子电路105可以响应于该第三扫描信号，向第二节点输出该复位电源信号。
其中，该初始电源信号的电位为第一电位。
由于该像素电路还可以在数据写入阶段之前，向第一节点P1输出处于第一电位的初始电源信号，因此还可以保证各个驱动电路包括的驱动晶体管均从相同的偏压状态开始工作，进一步改善了显示面板的显示效果。
以图6所示的像素电路为例，并以像素电路中的晶体管均为P型晶体管，初始电源端Vint提供的初始电源信号的电位为第一电位，直流电源端VDD提供的直流电源信号的电位为第二电位，且第一电位相对于第二电位为低电位为例，详细介绍本公开实施例提供的像素电路的驱动原理。
图9是本公开实施例提供的一种像素电路中各信号端的时序图。如图9所示，在复位阶段t1，第二扫描信号端S2提供的第二扫描信号的电位，和第三扫描信号端S3提供的第三扫描信号的电位均为第一电位，第一复位晶体管F1和第二复位晶体管F2开启。初始电源端Vinit通过该第一复位晶体管F1向第一节点P1输出处于第一电位的初始电源信号，实现对第一节点P1的复位，驱动晶 体管T1开启。复位电源端VSS通过第二复位晶体管F2向第二节点P2输出复位电源信号，实现对第二节点P2的复位。假设该复位电源信号的电位Vss为0，则该第二节点P2的电位即为0。
另外，在该复位阶段t1，如图9所示，第一扫描信号端S1提供的第一扫描信号的电位，和发光控制信号端EM提供的发光控制信号的电位均为第二电位，数据写入晶体管M1、补偿晶体管K1、第一发光控制晶体管L1、第二发光控制晶体管L2以及第三发光控制晶体管L3均关断，发光元件O1不发光。像素电路在复位阶段t1的等效电路图可以参考图10。
在数据写入阶段t2，第二扫描信号的电位跳变为第二电位，第一复位晶体管F1关断。第三扫描信号的电位保持为第一电位，第二复位晶体管F2保持开启。第一扫描信号的电位跳变为第一电位，补偿晶体管K1和数据写入晶体管M1开启。由于在复位阶段t1，驱动晶体管T1开启，因此在该数据写入阶段t2，数据信号端D可以通过数据写入晶体管M1、驱动晶体管T1和补偿晶体管K1向第一节点P1输出数据信号，直至第一节点P1的电位变为：Vdata+Vth，Vdata为数据信号的电位，Vth为驱动晶体管T1的阈值电压，且Vth小于0。并且，由于第二复位晶体管F2开启，因此该第二节点P2的电位可以保持为Vss。
另外，在该数据写入阶段t2，发光控制信号的电位保持为第二电位，第一发光控制晶体管L1、第二发光控制晶体管L2以及第三发光控制晶体管L3均保持关断，发光元件O1依然不发光。像素电路在数据写入阶段t2的等效电路图可以参考图11。
在发光阶段t3，第一扫描信号的电位和第三扫描信号的电位均为第二电位。例如，第一扫描信号的电位先跳变为第二电位，使得数据写入晶体管M1和补偿晶体管K1关断。然后，第三扫描信号的电位再跳变为第二电位，使得第二复位晶体管F2关断。并且，如图9所示，在发光阶段t3，发光控制信号端EM提供的发光控制信号的电位跳变为第一电位，第一发光控制晶体管L1、第二发光控制晶体管L2和第三发光控制晶体管L3开启，第二节点P2与第四节点P3导通，且第三节点P3和发光元件O1导通，直流电源端VDD可以通过第一发光控制晶体管L1向第二节点P2输出直流电源信号，进而再通过第二发光控制晶体管L2向第四节点P4输出直流电源信号。
假设该直流电源信号的电位为Vdd，则该第二节点P2和第四节点P4的电 位即变为Vdd。由于驱动晶体管T1的源漏极在制程(即制作工艺)上是相同的，因此此时，可以将第四节点P4作为驱动晶体管T1的源极，相应的，该驱动晶体管T1的源极电位Vs即可以变为Vdd。由于在数据写入阶段t2，第二节点P2的电位为Vss，因此可以确定该发光阶段t3中，第二节点P2的电位变化量为Vdd-Vss。又由于该补偿晶体管K1关断，因此在发光阶段t3，在存储电容C1的耦合作用下，该第一节点P1(即驱动晶体管T1的栅极)的电位可以变为：Vdd-Vss+Vdata+Vth，驱动晶体管T1开启。该像素电路在发光阶段t3的等效电路图可以参考图12。
在发光阶段t3，该驱动晶体管T1即可以根据第一节点P1的电位和第二节点P2的电位，向第三节点P3输出驱动信号，从而驱动发光元件O1发光。
由于在发光阶段t3中，驱动晶体管T1的栅极电位Vg为：Vdd-Vss+Vdata+Vth，驱动晶体管T1的源极电位Vs为Vdd，因此驱动晶体管T1的栅源电位差Vgs即可以满足：Vgs＝Vg-Vs＝Vdd-Vss+Vdata+Vth-Vdd＝Vdata+Vth-Vss。
在本公开实施例中，该驱动晶体管T1产生的驱动电流I OLED可以满足：
I OLED＝β×(Vgs-Vth) 2    公式(1)。
其中，β满足：
Figure PCTCN2020085768-appb-000001
μ n为驱动晶体管T1的载流子迁移率，C ox为驱动晶体管T1的栅极绝缘层的电容，W/L为驱动晶体管T1的宽长比，该β为在显示面板制造工艺确定后的常数。
将上述计算得到的栅源电位差Vgs代入公式(1)即可以计算得到驱动晶体管T1输出的驱动电流I OLED为：
I OLED＝β×(Vgs-Vth) 2＝β(Vdata-Vss) 2    公式(2)。
从公式(2)可以看出，对于图6所示的像素电路，在发光元件O1正常工作时，用于驱动发光元件O1的驱动电流I OLED的大小仅与β，数据信号端D提供的数据信号以及复位电源端VSS提供的复位电源信号有关，而与驱动晶体管T1的阈值电压Vth以及直流电源端VDD提供的直流电源信号无关。其中，若该复位电源端VSS提供的复位电源信号的电位为0，则该驱动电流I OLED的大小仅与β以及数据信号端D提供的数据信号有关。因此不仅可以解决由于直流电源端VDD的电压降问题造成显示面板显示亮度均一性较差的问题，而且也避免了由于驱动晶体管的阈值电压Vth发生漂移而造成显示面板显示亮度均一性较差的问题，保证了显示面板显示亮度均一性。
综上所述，本公开实施例提供了一种像素电路的驱动方法，由于在发光阶段，发光控制电路可以向第二节点输出直流电源端提供的直流电源信号或控制第三节点与发光元件导通，补偿电路可以根据第二节点的电位调节第一节点的电位，因此在对像素电路进行驱动时，即可使得最终写入至第一节点的电位仅与驱动晶体管的阈值电压、数据信号端提供的数据信号的电位和第二节点的电位有关。并且，由于驱动电路输出的驱动信号与第一节点和第二节点电位之差有关，因此即可使得驱动电路输出的驱动信号与第二节点的电位无关，即与直流电源信号无关。从而避免了由于直流电源端的电压降造成的显示面板显示亮度不均匀的问题，显示面板显示效果较好。
本公开实施例提供了一种显示基板，如图13所示，该显示基板可以包括：多个像素单元px。该多个像素单元px中的至少一个像素单元px可以包括发光元件，以及与该发光元件连接的如上述实施例所提供的像素电路。例如，如图1至图6任一所示的像素电路。
可选的，该显示基板中的每个像素单元px均可以包括：发光元件，以及与该发光元件连接的如上述实施例所提供的像素电路。其中，该发光元件可以为OLED或者AMOLED。
另外，本公开实施例还提供了一种显示装置，如图14所示，该显示装置可以驱动电路，以及与该驱动电路连接的如上述实施例提供的显示基板100。
示例的，如图14所示，该显示装置可以包括用于提供扫描信号的栅极驱动电路200，以及用于提供数据信号的源极驱动电路300。
该显示装置可以为：OLED显示装置、AMOLED显示装置、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的像素电路和各子电路的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种像素电路，所述像素电路包括：发光控制电路、补偿电路和驱动电路；
    所述发光控制电路分别与第一扫描信号端、发光控制信号端、数据信号端、直流电源端、第一节点、第二节点、第三节点和发光元件连接，所述发光控制电路用于响应于来自所述第一扫描信号端的第一扫描信号和来自所述数据信号端的数据信号，控制所述第一节点的电位，以及用于响应于来自所述发光控制信号端的发光控制信号，向所述第二节点输出所述直流电源端提供的直流电源信号，和控制所述第三节点与所述发光元件的通断；
    所述补偿电路分别与所述第一节点和所述第二节点连接，所述补偿电路用于根据所述第二节点的电位调整所述第一节点的电位；
    所述驱动电路分别与所述第一节点、所述第二节点和所述第三节点连接，所述驱动电路用于响应于所述第一节点的电位和所述第二节点的电位，向所述第三节点输出驱动信号。
  2. 根据权利要求1所述的像素电路，所述补偿电路包括：存储电容；
    所述存储电容的一端与所述第一节点连接，所述存储电容的另一端与所述第二节点连接。
  3. 根据权利要求1或2所述的像素电路，所述驱动电路包括：驱动晶体管；
    所述驱动晶体管的栅极与所述第一节点连接，所述驱动晶体管的第一极与所述第二节点连接，所述驱动晶体管的第二极与所述第三节点连接。
  4. 根据权利要求1至3任一所述的像素电路，所述发光控制电路包括：数据写入子电路、补偿子电路和发光控制子电路；
    所述数据写入子电路分别与所述第一扫描信号端、所述数据信号端和所述第三节点连接，所述数据写入子电路用于响应于所述第一扫描信号，向所述第三节点输出所述数据信号；
    所述补偿子电路分别与所述第一扫描信号端、所述第一节点和第四节点连 接，所述补偿子电路用于响应于所述第一扫描信号，控制所述第一节点与所述第四节点的通断，其中，所述第四节点还与所述驱动电路中驱动晶体管的第一极连接；
    所述发光控制子电路分别与所述发光控制信号端、所述直流电源端、所述第二节点、所述第四节点、所述第三节点和所述发光元件连接，所述发光控制子电路用于响应于所述发光控制信号，向所述第二节点输出所述直流电源信号，控制所述第二节点与所述第四节点的通断，以及控制所述第三节点与所述发光元件的通断。
  5. 根据权利要求4所述的像素电路，所述数据写入子电路包括：数据写入晶体管；
    所述数据写入晶体管的栅极与所述第一扫描信号端连接，所述数据写入晶体管的第一极与所述数据信号端连接，所述数据写入晶体管的第二极与所述第三节点连接。
  6. 根据权利要求4或5所述的像素电路，所述补偿子电路包括：补偿晶体管；
    所述补偿晶体管的栅极与所述第一扫描信号端连接，所述补偿晶体管的第一极与所述第一节点连接，所述补偿晶体管的第二极与所述第四节点连接。
  7. 根据权利要求4至6任一所述的像素电路，所述发光控制子电路包括：第一发光控制晶体管、第二发光控制晶体管和第三发光控制晶体管；
    所述第一发光控制晶体管的栅极与所述发光控制信号端连接，所述第一发光控制晶体管的第一极与所述直流电源端连接，所述第一发光控制晶体管的第二极与所述第二节点连接；
    所述第二发光控制晶体管的栅极与所述发光控制信号端连接，所述第二发光控制晶体管的第一极与所述第二节点连接，所述第二发光控制晶体管的第二极与所述第四节点连接；
    所述第三发光控制晶体管的栅极与所述发光控制信号端连接，所述第三发光控制晶体管的第一极与所述第三节点连接，所述第三发光控制晶体管的第二 极与所述发光元件连接。
  8. 根据权利要求4至7任一所述的像素电路，所述发光控制电路还包括：第一复位子电路和第二复位子电路；
    所述第一复位子电路分别与第二扫描信号端、初始电源端和所述第一节点连接，所述复位子电路用于响应于来自所述第二扫描信号端的第二扫描信号，向所述第一节点输出所述初始电源端提供的初始电源信号；
    所述第二复位子电路分别与所述第二节点、第三扫描信号端和复位电源端连接，所述第二复位子电路用于响应于来自所述第三扫描信号端的第三扫描信号，向所述第二节点输出所述复位电源端提供的复位电源信号。
  9. 根据权利要求8所述的像素电路，所述第一复位子电路包括：第一复位晶体管；
    所述第一复位晶体管的栅极与所述第二扫描信号端连接，所述第一复位晶体管的第一极与所述初始电源端连接，所述第一复位晶体管的第二极与所述第一节点连接。
  10. 根据权利要求8所述的像素电路，所述第二复位子电路包括：第二复位晶体管；
    所述第二复位晶体管的栅极与所述第三扫描信号端连接，所述第二复位晶体管的第一极与所述复位电源端连接，所述第二复位晶体管的第二极与所述第二节点连接。
  11. 根据权利要求3，5-7，9，以及10中任一所述的像素电路，所述像素电路包括的晶体管均为P型晶体管。
  12. 根据权利要求4所述的像素电路，所述补偿电路包括：存储电容；所述驱动电路包括：驱动晶体管；所述数据写入子电路包括：数据写入晶体管；所述补偿子电路包括：补偿晶体管；所述发光控制子电路包括：第一发光控制晶体管、第二发光控制晶体管和第三发光控制晶体管；所述电路还包括第一复 位晶体管和第二复位晶体管；
    所述存储电容的一端与所述第一节点连接，所述存储电容的另一端与所述第二节点连接；
    所述驱动晶体管的栅极与所述第一节点连接，所述驱动晶体管的第一极与第四节点连接，所述驱动晶体管的第二极与所述第三节点连接；
    所述数据写入晶体管的栅极与所述第一扫描信号端连接，所述数据写入晶体管的第一极与所述数据信号端连接，所述数据写入晶体管的第二极与所述第三节点连接；
    所述补偿晶体管的栅极与所述第一扫描信号端连接，所述补偿晶体管的第一极与所述第一节点连接，所述补偿晶体管的第二极与第四节点连接，所述第四节点还与所述驱动晶体管的第一极连接；
    所述第一发光控制晶体管的栅极与所述发光控制信号端连接，所述第一发光控制晶体管的第一极与所述直流电源端连接，所述第一发光控制晶体管的第二极与所述第二节点连接；
    所述第二发光控制晶体管的栅极与所述发光控制信号端连接，所述第二发光控制晶体管的第一极与所述第二节点连接，所述第二发光控制晶体管的第二极与所述第四节点连接；
    所述第三发光控制晶体管的栅极与所述发光控制信号端连接，所述第三发光控制晶体管的第一极与所述第三节点连接，所述第三发光控制晶体管的第二极与所述发光元件连接；
    所述第一复位晶体管的栅极与所述第二扫描信号端连接，所述第一复位晶体管的第一极与所述初始电源端连接，所述第一复位晶体管的第二极与所述第一节点连接；
    所述第二复位晶体管的栅极与所述第三扫描信号端连接，所述第二复位晶体管的第一极与所述复位电源端连接，所述第二复位晶体管的第二极与所述第二节点连接；
    所述像素电路包括的晶体管均为P型晶体管。
  13. 一种像素电路的驱动方法，应用于如权利要求1至12任一所述的像素电路，所述方法包括：
    数据写入阶段，第一扫描信号端提供的第一扫描信号的电位为第一电位，发光控制电路响应于所述第一扫描信号，根据数据信号端提供的数据信号，控制第一节点的电位；
    发光阶段，发光控制信号端提供的发光控制信号的电位为第一电位，所述发光控制电路响应于所述发光控制信号，向第二节点输出直流电源端提供的直流电源信号，以及控制第三节点与发光元件导通，补偿电路根据所述第二节点的电位调节所述第一节点的电位，驱动电路响应于所述第一节点的电位和所述第二节点的电位，向所述第三节点输出驱动信号。
  14. 根据权利要求13所述的方法，所述发光控制电路包括：数据写入子电路、补偿子电路和发光控制子电路；
    在所述数据写入阶段，所述第一扫描信号的电位为第一电位，所述数据信号端通过所述数据写入子电路、所述驱动电路和所述补偿子电路向所述第一节点输出所述数据信号；
    在所述发光阶段，所述发光控制信号的电位为第一电位，所述直流电源端通过所述发光控制子电路向所述第二节点输出所述直流电源信号，且所述第二节点与第四节点导通，所述第三节点与所述发光元件导通。
  15. 根据权利要求14所述的方法，所述发光控制电路还包括：第一复位子电路和第二复位子电路，所述第一复位子电路分别与第二扫描信号端、初始电源端和所述第一节点连接，所述第二复位子电路分别与所述第二节点、第三扫描信号端和复位电源端连接；在所述数据写入阶段之前，所述方法还包括：
    复位阶段，所述第二扫描信号端提供的第二扫描信号的电位和所述第三扫描信号端提供的第三扫描信号的电位均为第一电位，所述第一复位子电路响应于所述第二扫描信号向所述第一节点输出所述初始电源端提供的初始电源信号，所述第二复位子电路响应于所述第三扫描信号，向所述第二节点输出所述复位电源端提供的复位电源信号；
    在所述数据写入阶段，所述第三扫描信号端提供的第三扫描信号的电位为第一电位，所述第二复位子电路响应于所述第三扫描信号，向所述第二节点输出所述复位电源端提供的复位电源信号；
    其中，所述初始电源信号的电位为第一电位。
  16. 根据权利要求13至15任一所述的方法，所述直流电源信号的电位为第二电位，所述第二电位相对于所述第一电位为高电位。
  17. 一种显示基板，所述显示基板包括：多个像素单元，所述多个像素单元中，至少一个所述像素单元包括：发光元件，以及与所述发光元件连接的如权利要求1至11任一所述的像素电路。
  18. 根据权利要求17所述的显示基板，每个所述像素单元均包括：发光元件，以及与所述发光元件连接的如权利要求1至11任一所述的像素电路。
  19. 根据权利要求17或18所述的显示基板，所述发光元件为有机发光二极管。
  20. 一种显示装置，所述显示装置包括：驱动电路，以及如权利要求17至19任一所述的显示基板。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110010076B (zh) * 2019-04-22 2021-01-01 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板、显示装置
CN113593458B (zh) * 2021-07-29 2023-12-26 京东方科技集团股份有限公司 显示面板及其检测电路的驱动方法、显示装置
CN116264850A (zh) * 2021-08-30 2023-06-16 京东方科技集团股份有限公司 像素电路、驱动方法、显示基板和显示装置
CN114882832B (zh) * 2022-05-20 2023-06-27 Tcl华星光电技术有限公司 像素驱动电路、显示面板和驱动方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN203179479U (zh) * 2013-04-26 2013-09-04 京东方科技集团股份有限公司 一种像素单元电路以及显示装置
US20140306946A1 (en) * 2013-04-12 2014-10-16 Samsung Display Co., Ltd. Organic light emitting display device and method of driving the same
CN105355170A (zh) * 2015-12-10 2016-02-24 友达光电股份有限公司 主动矩阵有机发光二极管显示器的像素补偿电路
CN105590955A (zh) * 2015-12-25 2016-05-18 昆山国显光电有限公司 像素电路及其驱动方法和有源矩阵有机发光显示器
CN110010076A (zh) * 2019-04-22 2019-07-12 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板、显示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014115543A (ja) * 2012-12-11 2014-06-26 Samsung Display Co Ltd 表示装置及びその画素回路の駆動方法
CN106128360B (zh) * 2016-09-08 2018-11-13 京东方科技集团股份有限公司 像素电路、显示面板、显示设备及驱动方法
CN106652904B (zh) * 2017-03-17 2019-01-18 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示装置
CN107086024A (zh) 2017-05-04 2017-08-22 成都晶砂科技有限公司 单晶硅晶体管cmos驱动显示的像素补偿电路及显示设备
CN107342048A (zh) * 2017-08-17 2017-11-10 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN108877667A (zh) * 2018-07-26 2018-11-23 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示面板及显示装置
CN109087609A (zh) * 2018-11-13 2018-12-25 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板、显示装置
CN117765880A (zh) * 2019-01-18 2024-03-26 京东方科技集团股份有限公司 像素电路、驱动方法、电致发光显示面板及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140306946A1 (en) * 2013-04-12 2014-10-16 Samsung Display Co., Ltd. Organic light emitting display device and method of driving the same
CN203179479U (zh) * 2013-04-26 2013-09-04 京东方科技集团股份有限公司 一种像素单元电路以及显示装置
CN105355170A (zh) * 2015-12-10 2016-02-24 友达光电股份有限公司 主动矩阵有机发光二极管显示器的像素补偿电路
CN105590955A (zh) * 2015-12-25 2016-05-18 昆山国显光电有限公司 像素电路及其驱动方法和有源矩阵有机发光显示器
CN110010076A (zh) * 2019-04-22 2019-07-12 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板、显示装置

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