WO2021184893A1 - 像素电路及其驱动方法、显示基板、显示装置 - Google Patents

像素电路及其驱动方法、显示基板、显示装置 Download PDF

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Publication number
WO2021184893A1
WO2021184893A1 PCT/CN2020/140327 CN2020140327W WO2021184893A1 WO 2021184893 A1 WO2021184893 A1 WO 2021184893A1 CN 2020140327 W CN2020140327 W CN 2020140327W WO 2021184893 A1 WO2021184893 A1 WO 2021184893A1
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Prior art keywords
circuit
transistor
coupled
control
node
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PCT/CN2020/140327
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English (en)
French (fr)
Inventor
丛宁
玄明花
张粲
杨明
王灿
袁丽君
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US17/418,808 priority Critical patent/US11670220B2/en
Publication of WO2021184893A1 publication Critical patent/WO2021184893A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, a display substrate, and a display device.
  • Micro light emitting diodes are widely used in various display devices due to their high brightness, high luminous efficiency, small size, and low power consumption.
  • the pixel circuit that drives the Micro LED to emit light generally includes: a driving transistor and a switching transistor.
  • the switching transistor can output the data voltage provided by the data signal terminal it is coupled to the driving transistor;
  • the driving transistor can convert the data voltage into a driving current for driving the Micro LED to emit light and output it to the Micro LED to drive the Micro LED to emit light.
  • the size of the drive current is related to the threshold voltage of the drive transistor, when the threshold voltage of the drive transistor drifts, it will cause the drive current output to the Micro LED to be abnormal, which in turn leads to the uniformity of the display brightness of the Micro LED display device. Lower, the display effect is poor.
  • the present disclosure provides a pixel circuit and a driving method thereof, a display substrate, and a display device.
  • the technical solution is as follows:
  • a pixel circuit in one aspect, includes: a drive circuit, a light emission control circuit, and a compensation circuit;
  • the driving circuit is respectively coupled to a first power terminal, a gate signal terminal, a first data signal terminal, and a first connection node, and the driving circuit is configured to respond to a first power signal from the first power terminal, from The gate driving signal of the gate signal terminal and the first data signal from the first data signal terminal output a driving current to the first connection node;
  • the lighting control circuit is connected to the first connection node, the gate signal terminal, the reset signal terminal, the lighting control signal terminal, the second power terminal, the second data signal terminal, the first control node, and the second control node, respectively.
  • the second connection node is coupled to the light-emitting element, and the light-emitting control circuit is configured to output to the first connection node and the first control node the signal from the second power supply terminal in response to the reset signal from the reset signal terminal
  • the second power signal is used to output the second data signal from the second data signal terminal to the first control node in response to the gate drive signal, and is used to respond to the light emission control signal from the light emission control signal terminal Controlling the on-off of the second connection node and the light-emitting element, and controlling the on-off of the first connection node and the second connection node in response to the potential of the second control node;
  • the compensation circuit is respectively coupled to a third power terminal, the light-emitting control signal terminal, the reset signal terminal, the first control node, the second control node, and the second connection node, and the compensation A circuit for adjusting the potential of the second control node according to the potential of the first control node, for adjusting the potential of the second control node according to the potential of the second connection node in response to the reset signal, and It is used for adjusting the potential of the second control node according to the potential of the first control node and the third power signal from the third power terminal in response to the light emission control signal.
  • the compensation circuit includes: a first compensation sub-circuit and a second compensation sub-circuit;
  • the first compensation sub-circuit is respectively coupled to the light-emitting control signal terminal, the third power terminal, the first control node and the second control node, and the first compensation sub-circuit is used for
  • the potential of the first control node adjusts the potential of the second control node, and is used to adjust the second control node according to the third power signal and the potential of the first control node in response to the light emission control signal The potential;
  • the second compensation sub-circuit is respectively coupled to the reset signal terminal, the second connection node and the second control node, and the second compensation sub-circuit is configured to respond to the reset signal according to the first The potential of the second connection node adjusts the potential of the second control node.
  • the first compensation sub-circuit includes: a first compensation transistor, a second compensation transistor, a compensation capacitor, and a compensation resistor;
  • the gate of the first compensation transistor is coupled to the light emission control signal terminal, the first pole of the first compensation transistor is coupled to the third power terminal, and the second pole of the first compensation transistor is coupled to the The first control node is coupled;
  • the gate of the second compensation transistor is coupled to the light emission control signal terminal, the first pole of the second compensation transistor is coupled to one end of the compensation resistor, and the second pole of the second compensation transistor is coupled to The second control node is coupled;
  • the other end of the compensation resistor is coupled to the third power terminal
  • One end of the compensation capacitor is coupled to the first control node, and the other end of the compensation capacitor is coupled to the second control node.
  • the second compensation sub-circuit includes: a third compensation transistor
  • the gate of the third compensation transistor is coupled to the reset signal terminal, the first pole of the third compensation transistor is coupled to the second connection node, and the second pole of the third compensation transistor is coupled to the reset signal terminal.
  • the second control node is coupled.
  • the light-emitting control circuit is further configured to output the second power signal to the light-emitting element in response to the reset signal;
  • the light-emitting control circuit includes: a first reset sub-circuit, a first data writing A sub-circuit, a first light-emitting control sub-circuit, and a switch sub-circuit;
  • the first reset sub-circuit is respectively coupled to the reset signal terminal, the second power terminal, the first connection node, the first control node, and the light-emitting element, and the first reset sub-circuit Configured to output the second power signal to the first connection node, the first control node, and the light-emitting element in response to the reset signal;
  • the first data writing sub-circuit is respectively coupled to the gate signal terminal, the second data signal terminal and the first control node, and the first data writing sub-circuit is configured to respond to the A gate drive signal to output the second data signal to the first control node;
  • the first lighting control sub-circuit is respectively coupled to the lighting control signal terminal, the second connection node and the light-emitting element, and the first lighting control sub-circuit is used to control the lighting control signal in response to the lighting control signal.
  • the switch sub-circuit is respectively coupled to the second control node, the first connection node, and the second connection node, and the switch sub-circuit is configured to control the second control node in response to the potential of the second control node. The on-off of the first connection node and the second connection node.
  • the first reset sub-circuit includes: a first reset transistor, a second reset transistor, and a third reset transistor;
  • the gates of the first reset transistor, the second reset transistor and the third reset transistor are all coupled to the reset signal terminal;
  • the first electrodes of the first reset transistor, the second reset transistor and the third reset transistor are all coupled to the second power terminal;
  • the second electrode of the first reset transistor is coupled to the first connection node, the second electrode of the second reset transistor is coupled to the first control node, and the second electrode of the third reset transistor Coupled with the light-emitting element.
  • the first data writing sub-circuit includes: a first data writing transistor
  • the gate of the first data writing transistor is coupled to the gate signal terminal, the first electrode of the first data writing transistor is coupled to the second data signal terminal, and the first data writing transistor The second electrode of the input transistor is coupled to the first control node.
  • the first light emission control sub-circuit includes: a first light emission control transistor
  • the gate of the first emission control transistor is coupled to the emission control signal terminal, the first pole of the first emission control transistor is coupled to the second connection node, and the first pole of the first emission control transistor is coupled to the second connection node.
  • the diode is coupled with the light-emitting element.
  • the switch sub-circuit includes: a switch transistor
  • the gate of the switching transistor is coupled to the second control node, the first pole of the switching transistor is coupled to the first connection node, and the second pole of the switching transistor is coupled to the second connection node Coupling.
  • the pixel circuit further includes: a switch control circuit connected in series between the driving circuit and the first connection node;
  • the switch control circuit is respectively coupled to the light emission control signal terminal, the drive circuit and the first connection node, and the switch control circuit is used to control the drive circuit and the light emission control signal in response to the light emission control signal.
  • the on-off of the first connection node is respectively coupled to the light emission control signal terminal, the drive circuit and the first connection node, and the switch control circuit is used to control the drive circuit and the light emission control signal in response to the light emission control signal. The on-off of the first connection node.
  • the switch control circuit includes: a switch control transistor
  • the gate of the switch control transistor is coupled to the light emission control signal terminal, the first pole of the switch control transistor is coupled to the drive circuit, and the second pole of the switch control transistor is connected to the first Node coupling.
  • the driving circuit includes: a second data writing sub-circuit, a second reset sub-circuit, a second light-emitting control sub-circuit, a storage sub-circuit, a third compensation sub-circuit, and a driving sub-circuit;
  • the second data writing sub-circuit is respectively coupled to the gate signal terminal, the first data signal terminal and the third connection node, and the second data writing sub-circuit is configured to respond to the gate signal A driving signal to output the first data signal to the third connection node;
  • the second reset sub-circuit is respectively coupled to the reset signal terminal, the second power terminal, and the third control node, and the second reset sub-circuit is used to respond to the reset signal to the third control node.
  • the node outputs the second power signal
  • the second lighting control sub-circuit is respectively coupled to the lighting control signal terminal, the first power terminal and the third connection node, and the second lighting control sub-circuit is configured to respond to the lighting control signal Outputting the first power signal to the third connection node;
  • the storage sub-circuit is respectively coupled to the third control node and the first power terminal, and the storage sub-circuit is used to control the potential of the third control node;
  • the third compensation sub-circuit is respectively coupled to the gate signal terminal, the first connection node and the first control node, and the third compensation sub-circuit is configured to respond to the gate drive signal according to Adjusting the potential of the third control node by the potential of the first connection node;
  • the driving sub-circuit is respectively coupled to the third control node, the third connection node, and the first connection node, and the driving sub-circuit is configured to respond to the potential of the third control node and the The potential of the third connection node outputs a driving current to the first connection node.
  • the second data writing subcircuit includes: a second data writing transistor; the second reset subcircuit includes: a fourth reset transistor; the second light emission control subcircuit includes: a second light emission control A transistor; the storage sub-circuit includes: a storage capacitor; the third compensation sub-circuit includes: a fourth compensation transistor; the drive sub-circuit includes: a drive transistor;
  • the gate of the second data writing transistor is coupled to the gate signal terminal, the first electrode of the second data writing transistor is coupled to the first data signal terminal, and the second data writing transistor The second electrode of the input transistor is coupled to the third connection node;
  • the gate of the fourth reset transistor is coupled to the reset signal terminal, the first pole of the fourth reset transistor is coupled to the second power supply terminal, and the second pole of the fourth reset transistor is coupled to the reset signal terminal.
  • the third control node is coupled;
  • the gate of the second light-emission control transistor is coupled to the light-emission control signal terminal, the first electrode of the second light-emission control transistor is coupled to the first power supply terminal, and the first electrode of the second light-emission control transistor
  • the two poles are coupled to the third connection node;
  • One end of the storage capacitor is coupled to the third control node, and the other end of the storage capacitor is coupled to the first power terminal;
  • the gate of the fourth compensation transistor is coupled to the gate signal terminal, the first pole of the fourth compensation transistor is coupled to the first connection node, and the second pole of the fourth compensation transistor is coupled to the The third control node is coupled;
  • the gate of the driving transistor is coupled to the third control node, the first stage of the driving transistor is coupled to the third connection node, and the second electrode of the driving transistor is coupled to the first connection node Coupling.
  • a method for driving a pixel circuit for driving the pixel circuit as described in the above aspect, and the method includes:
  • the potential of the reset signal provided by the reset signal terminal is the first potential
  • the light emitting control circuit outputs the second power signal from the second power terminal to the first connection node and the first control node in response to the reset signal
  • the compensation circuit is based on
  • the potential of the first control node adjusts the potential of the second control node
  • the light emission control circuit also controls the conduction of the first connection node and the second connection node in response to the potential of the second control node
  • the compensation The circuit further adjusts the potential of the second control node according to the potential of the second connection node in response to the reset signal;
  • the potential of the gate drive signal provided by the gate signal terminal is the first potential
  • the light-emitting control circuit outputs the first control node from the second data signal terminal in response to the gate drive signal.
  • the compensation circuit adjusts the potential of the second control node according to the potential of the first control node;
  • the driving circuit responds to the first power signal from the first power terminal, the gate drive signal, and the first data signal from the first data signal terminal to output a driving current to the first connection node, and the light-emitting control signal
  • the potential of the light-emitting control signal provided by the terminal is the first potential
  • the compensation circuit adjusts the second control node according to the potential of the first control node and the third power signal from the third power terminal in response to the light-emitting control signal
  • the light emission control circuit controls the first connection node and the second connection node to conduct in response to the potential of the second control node, and controls the second connection node in response to the light emission control signal Conducted with the light-emitting element.
  • a display substrate in yet another aspect, includes a plurality of pixel units. Among the plurality of pixel units, at least one of the pixel units includes a light-emitting element, and a light-emitting element coupled to the light-emitting element.
  • the light-emitting element includes: a miniature light-emitting diode.
  • a display device including: a signal driving circuit, and the display substrate as described in the foregoing aspect;
  • the signal driving circuit is coupled to each signal terminal in the pixel circuit included in the display substrate, and the signal driving circuit is used to provide a signal for each signal terminal.
  • FIG. 1 is a schematic diagram of luminous efficiency and current density of a Micro LED provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of still another pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of still another pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of still another pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of still another pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 9 is a flowchart of a driving method of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 10 is a timing diagram of each signal terminal of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 11 is an equivalent circuit diagram of a pixel circuit in the reset stage provided by an embodiment of the present disclosure.
  • FIG. 12 is an equivalent circuit diagram of a pixel circuit in the data writing stage according to an embodiment of the present disclosure.
  • FIG. 13 is an equivalent circuit diagram of a pixel circuit provided by an embodiment of the present disclosure in a light-emitting stage
  • FIG. 14 is a schematic diagram of a coefficient value of a second control node potential in the related art.
  • 15 is a schematic diagram of a coefficient value of a second control node potential provided by an embodiment of the present disclosure.
  • 16 is a schematic diagram of a relationship between light-emitting duration and data signal potential provided by an embodiment of the present disclosure
  • FIG. 17 is a simulation diagram of the relationship between light-emitting duration and data signal potential provided by an embodiment of the present disclosure.
  • FIG. 18 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 19 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • the transistors used in the embodiments of the present disclosure are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable.
  • the source electrode is referred to as the first electrode and the drain electrode is referred to as the second electrode.
  • the drain electrode may be referred to as the first electrode and the source electrode is referred to as the second electrode.
  • the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain.
  • the switching transistor used in the embodiments of the present disclosure may be a P-type switching transistor, which is turned on when the gate is at a low level, and is turned off when the gate is at a high level.
  • multiple signals in the various embodiments of the present disclosure correspond to a first potential and a second potential.
  • the first potential and the second potential only represent that the potential of the signal has two state quantities, and does not mean that the first potential or the second potential in the full text has a specific value.
  • the first potential is an effective potential as an example for description.
  • Micro LED can be understood as a kind of self-luminous element after miniaturizing and matrixing the LED, and its luminous efficiency has a certain relationship with the current density of the driving current output to it.
  • Figure 1 shows the relationship between the luminous efficiency and current density of a Micro LED.
  • the horizontal axis that is, the x-axis
  • the vertical axis that is, the y-axis
  • the luminous efficiency of Micro LED will change with the current density, and the luminous efficiency of the Micro LED will change significantly at low current density (the 0-J1 interval shown in Figure 1).
  • the luminous efficiency is relatively stable at the density (J1-J2 interval as shown in Figure 1) and will not change significantly.
  • the color coordinates of the Micro LED will also change with the current density.
  • the pixel circuit in the related technology is used to drive the Micro LED to emit light, the brightness of the Micro LED will also be affected by the threshold voltage drift.
  • the stability of the luminous efficiency of the Micro LED is poor, and the display uniformity of the Micro LED display device is poor.
  • the embodiments of the present disclosure provide a pixel circuit, which can not only avoid the phenomenon of poor display brightness uniformity due to the drift of the threshold voltage of the driving transistor, but also can be controlled by adjusting the size of the driving current and the light-emitting duration of the Micro LED.
  • the gray scale ensures that the Micro LED can always work at a high current density, which means that the luminous efficiency of the Micro LED can always be stable.
  • FIG. 2 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • the pixel circuit may include: a driving circuit 10, a light emission control circuit 20 and a compensation circuit 30.
  • the driving circuit 10 can be respectively coupled to the first power terminal VDD, the gate signal terminal G1, the first data signal terminal DI, and the first connection node P1.
  • the driving circuit 10 can respond to the first power signal from the first power terminal VDD, the gate drive signal from the gate signal terminal G1, and the first data signal from the first data signal terminal DI to the first connection node P1. Output drive current.
  • the light-emitting control circuit 20 can be respectively connected to the first connection node P1, the gate signal terminal G1, the reset signal terminal RST, the light-emitting control signal terminal EM, the second power terminal Vint, the second data signal terminal DT, the first control node N1, and the The second control node N2, the second connection node P2 and the light emitting element L1 are coupled.
  • the light emission control circuit 20 can be used to output a second power signal from the second power terminal Vint to the first connection node P1 and the first control node N1 in response to the reset signal from the reset signal terminal RST, for responding to the gate driving
  • the signal outputs the second data signal from the second data signal terminal DT to the first control node N1 for controlling the on/off of the second connection node P2 and the light emitting element L1 in response to the light emission control signal from the light emission control signal terminal EM, and It is used to control the on-off of the first connection node P1 and the second connection node P2 in response to the potential of the second control node N2.
  • the light emission control circuit 20 may output the second power signal from the second power terminal Vint to the first connection node P1 and the first control node N1 when the potential of the reset signal provided by the reset signal terminal RST is the first potential.
  • the potential of the second power signal may be the second potential, so as to realize the resetting of the first connection node P1 and the first control node N1.
  • the first potential may be an effective potential
  • the second potential may be an ineffective potential
  • the first potential may be a low potential relative to the second potential, that is, the voltage of the signal at the first potential is smaller than the signal at the second potential The voltage.
  • the light emission control circuit 20 may output the second data signal from the second data signal terminal DT to the first control node N1 when the potential of the gate driving signal provided by the gate signal terminal G1 is the first potential.
  • the second connection node P2 and the light emitting element L1 can be controlled to be conductive.
  • the first connection node P1 and the second connection node P2 can be controlled to be conductive. If the first potential is lower than the second potential, that is, the light emission control circuit 20 can control the first connection node P1 and the second connection node P2 to conduct when the potential of the second control node N2 is less than the potential threshold.
  • the compensation circuit 30 can be respectively coupled to the third power terminal VSS, the light emission control signal terminal EM, the reset signal terminal RST, the first control node N1, the second control node N2, and the second connection node P2.
  • the compensation circuit 30 can adjust the potential of the second control node N2 according to the potential of the first control node N1, can adjust the potential of the second control node N2 according to the potential of the second connection node P2 in response to the reset signal, and can respond to the light emission control The signal adjusts the potential of the second control node N2 according to the potential of the first control node N1 and the third power signal from the third power terminal VSS.
  • the compensation circuit 30 can adjust the potential of the second control node N2 according to the potential of the first control node N1 through coupling.
  • the compensation circuit 30 can adjust the potential of the second control node N2 according to the potential of the second connection node P2 when the potential of the reset signal is the first potential.
  • the compensation circuit 30 can adjust the potential of the second control node N2 according to the potential of the first control node N1 and the third power signal when the potential of the light emission control signal is the first potential.
  • the potential of the third power signal may be a third potential, and the third potential may also be a low potential relative to the second potential.
  • the third power signal terminal VSS may be a ground terminal.
  • the driving circuit 10 described in the embodiment of the present disclosure can control the magnitude of the driving current based on the first data signal; the light emitting control circuit 20 and the compensation circuit 30 can control the output of the driving current based on the second data signal.
  • the length of time to the light-emitting element L1, that is, the light-emitting time length of the light-emitting element L1 is controlled.
  • the first data signal can also be referred to as a current control data signal;
  • the second data signal can also be referred to as a duration control data signal.
  • the driving circuit 10 can be called a current control circuit; the circuit composed of the light emission control circuit 20 and the compensation circuit 30 can be called a time control circuit.
  • the embodiments of the present disclosure provide a pixel circuit including a compensation circuit. Because the compensation circuit can adjust the potential of the second control node (that is, the gate of the transistor that controls the on and off of the first connection node and the second connection node) according to the potential of the first control node, and can adjust the potential of the second control node according to the second connection node (that is, control The potential of the second pole of the transistor that turns on and off the first connection node and the second connection node adjusts the potential of the second control node. Therefore, when driving the pixel circuit, the potential of each control signal can be controlled so that the potential finally output to the second control node is less affected by the threshold voltage of the transistor, that is, the threshold voltage drift caused by the display uniformity is reduced. Influence, the display effect of the display device provided by the embodiment of the present disclosure is better.
  • FIG. 3 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • the compensation circuit 30 may include: a first compensation sub-circuit 301 and a second compensation sub-circuit 302.
  • the first compensation sub-circuit 301 can be respectively coupled to the emission control signal terminal EM, the third power supply terminal VSS, the first control node N1 and the second control node N2.
  • the first compensation sub-circuit 301 can adjust the potential of the second control node N2 according to the potential of the first control node N1, and can adjust the second control node according to the third power signal and the potential of the first control node N1 in response to the light emission control signal.
  • the first compensation sub-circuit 301 can adjust the potential of the second control node N2 according to the potential of the first control node N1 through coupling; And the potential of the first control node N1 to adjust the potential of the second control node N2.
  • the first compensation sub-circuit 301 can pull down the potential of the first control node N1 through the third power signal, and then further pull down the second control node N1 based on the potential of the first control node N1. The potential of the node N2, thereby realizing the adjustment of the potential of the second control node N2.
  • the second compensation sub-circuit 302 can be respectively coupled to the reset signal terminal RST, the second connection node P2 and the second control node N2.
  • the second compensation sub-circuit 302 can adjust the potential of the second control node N2 according to the potential of the second connection node P2 in response to the reset signal.
  • the second compensation sub-circuit 302 may adjust the potential of the second control node N2 according to the potential of the second connection node P2 when the potential of the reset signal is the first potential.
  • FIG. 4 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • the first compensation sub-circuit 301 may include: a first compensation transistor B1, a second compensation transistor B2, a compensation capacitor C1, and a compensation resistor R1.
  • the gate of the first compensation transistor B1 may be coupled to the light emission control signal terminal EM, the first pole of the first compensation transistor B1 may be coupled to the third power terminal VSS, and the second pole of the first compensation transistor B1 The pole can be coupled with the first control node N1.
  • the gate of the second compensation transistor B2 may be coupled to the emission control signal terminal EM, the first pole of the second compensation transistor B2 may be coupled to one end of the compensation resistor R1, and the second pole of the second compensation transistor B2 may be coupled to the first pole
  • the two control nodes N2 are coupled.
  • the other end of the compensation resistor R1 can be coupled to the third power terminal VSS.
  • One end of the compensation capacitor C1 can be coupled to the first control node N1, and the other end of the compensation capacitor C1 can be coupled to the second control node N2.
  • the second compensation sub-circuit 302 may include: a third compensation transistor B3.
  • the gate of the third compensation transistor B3 may be coupled to the reset signal terminal RST, the first pole of the third compensation transistor B3 may be coupled to the second connection node P2, and the second pole of the third compensation transistor B3 may be coupled to the The second control node N2 is coupled.
  • the light-emitting control circuit 20 may also output a second power signal to the light-emitting element L1 in response to the reset signal.
  • the light emission control circuit 20 may include: a first reset sub-circuit 201, a first data writing sub-circuit 202, a first light-emission control sub-circuit 203, and a switch sub-circuit 204.
  • the first reset sub-circuit 201 may be respectively coupled to the reset signal terminal RST, the second power terminal Vint, the first connection node P1, the first control node N1 and the light emitting element L1.
  • the first reset sub-circuit 201 can output a second power signal to the first connection node P1, the first control node N1, and the light emitting element L1 in response to the reset signal.
  • the first reset sub-circuit 201 can output the second power signal at the second potential to the first connection node P1, the first control node N1 and the light-emitting element L1 when the potential of the reset signal is the first potential, thereby achieving Reset the first connection node P1, the first control node N1, and the light-emitting element L1.
  • each circuit included in the light-emitting control circuit 20 and the compensation circuit 30 can be operated from the same potential. , To ensure the working reliability of the pixel circuit.
  • the first data writing sub-circuit 202 may be respectively coupled to the gate signal terminal G1, the second data signal terminal DT and the first control node N1.
  • the first data writing sub-circuit 202 can output a second data signal to the first control node N1 in response to the gate driving signal.
  • the first data writing sub-circuit 202 may output the second data signal to the first control node N1 when the potential of the gate driving signal is the first potential.
  • the first light emission control sub-circuit 203 can be respectively coupled to the light emission control signal terminal EM, the second connection node P2 and the light emitting element L1.
  • the first light-emission control sub-circuit 203 can control the on/off of the second connection node P2 and the light-emitting element L1 in response to the light-emission control signal.
  • the first light-emitting control sub-circuit 203 may control the second connection node P2 and the light-emitting element L1 to conduct when the potential of the light-emitting control signal is the first potential.
  • the switch sub-circuit 204 can be respectively coupled to the second control node N2, the first connection node P1, and the second connection node P2.
  • the switch sub-circuit 204 can control the on-off of the first connection node P1 and the second connection node P2 in response to the potential of the second control node N2.
  • the switch sub-circuit 204 may control the first connection node P1 and the second connection node P2 to conduct when the potential of the second control node N2 is the first potential.
  • the first reset sub-circuit 201 may include: a first reset transistor F1, a second reset transistor F2, and a third reset transistor F3.
  • the gates of the first reset transistor F1, the second reset transistor F2 and the third reset transistor F3 may all be coupled to the reset signal terminal RST.
  • the first electrodes of the first reset transistor F1, the second reset transistor F2 and the third reset transistor F3 may all be coupled to the second power terminal Vint.
  • the second pole of the first reset transistor F1 may be coupled to the first connection node P1
  • the second pole of the second reset transistor F2 may be coupled to the first control node N1
  • the second pole of the third reset transistor F3 may be coupled to The light emitting element L1 is coupled.
  • the first data writing sub-circuit 202 may include: a first data writing transistor D1.
  • the gate of the first data writing transistor D1 may be coupled to the gate signal terminal G1, the first electrode of the first data writing transistor D1 may be coupled to the second data signal terminal DT, and the first data writing transistor D1 may be coupled to the second data signal terminal DT.
  • the second electrode of the transistor D1 may be coupled to the first control node N1.
  • the first light-emission control sub-circuit 203 may include: a first light-emission control transistor M1.
  • the gate of the first emission control transistor M1 may be coupled to the emission control signal terminal EM, the first pole of the first emission control transistor M1 may be coupled to the second connection node P2, and the second pole of the first emission control transistor M1 It can be coupled with the light-emitting element L1.
  • the switch sub-circuit 204 may include a switch transistor K1.
  • the gate of the switching transistor K1 may be coupled to the second control node N2, the first pole of the switching transistor K1 may be coupled to the first connection node P1, and the second pole of the switching transistor K1 may be coupled to the second connection node P2 Coupling.
  • FIG. 5 is a schematic structural diagram of still another pixel circuit provided by an embodiment of the present disclosure. As shown in FIG. 5, the pixel circuit may further include: a switch control circuit 40 connected in series between the driving circuit 10 and the first connection node P1.
  • the switch control circuit 40 can be respectively coupled to the light emission control signal terminal EM, the driving circuit 10 and the first connection node P1.
  • the switch control circuit 40 can control the on and off of the driving circuit 10 and the first connection node P1 in response to the light emission control signal.
  • the switch control circuit 40 may control the driving circuit 10 and the first connection node P1 to conduct when the potential of the light emission control signal is the first potential, so that the driving circuit 10 passes the driving current generated by the driving circuit 40 through the switch control circuit 40. Output to the first connection node P1.
  • the switch control circuit 40 By providing the switch control circuit 40, it is possible to prevent the driving current from being output to the light-emitting element L1 by mistake when the signal provided by any signal terminal other than the light-emitting control signal terminal EM is unstable. That is, it can be ensured that the driving current is output to the light-emitting element L1 only when the potential of the light-emitting control signal is an effective potential. The reliability of the pixel circuit driving the light-emitting element L1 to emit light is further improved.
  • FIG. 6 is a schematic structural diagram of still another pixel circuit provided by an embodiment of the present disclosure.
  • the switch control circuit 40 may include: a switch control transistor Q1.
  • the gate of the switch control transistor Q1 may be coupled to the light emission control signal terminal EM, the first pole of the switch control transistor Q1 may be coupled to the driving circuit 10, and the second pole of the switch control transistor Q1 may be connected to the first connection node P1 is coupled.
  • FIG. 7 is a schematic structural diagram of still another pixel circuit provided by an embodiment of the present disclosure.
  • the driving circuit 10 may include: a second data writing sub-circuit 101, a second reset sub-circuit 102, a second light emission control sub-circuit 103, a storage sub-circuit 104, a third compensation sub-circuit 105, and a driving sub-circuit.
  • Subcircuit 106 may include: a second data writing sub-circuit 101, a second reset sub-circuit 102, a second light emission control sub-circuit 103, a storage sub-circuit 104, a third compensation sub-circuit 105, and a driving sub-circuit.
  • the second data writing sub-circuit 101 may be respectively coupled to the gate signal terminal G1, the first data signal terminal DI, and the third connection node P3.
  • the second data writing sub-circuit 101 may output the first data signal to the third connection node P3 in response to the gate driving signal.
  • the second data writing sub-circuit 101 may output the first data signal to the third connection node P3 when the potential of the gate driving signal is the first potential.
  • the second reset sub-circuit 102 can be respectively coupled to the reset signal terminal RST, the second power terminal Vint and the third control node N3.
  • the second reset sub-circuit 102 can output a second power signal to the third control node N3 in response to the reset signal.
  • the second reset sub-circuit 102 may output the second power signal at the second potential to the third control node N3 when the potential of the reset signal is the first potential, so as to reset the third control node N3.
  • the second light emission control sub-circuit 103 may be respectively coupled to the light emission control signal terminal EM, the first power terminal VDD, and the third connection node P3.
  • the second light emission control sub-circuit 103 can output the first power signal to the third connection node P3 in response to the light emission control signal.
  • the second light emission control sub-circuit 103 can output the first power signal at the first potential to the third connection node P3 when the potential of the light emission control signal is the first potential, so as to charge the third connection node P3.
  • the storage sub-circuit 104 may be respectively coupled to the third control node N3 and the first power supply terminal VDD.
  • the storage sub-circuit 104 can control the potential of the third control node N3.
  • the storage sub-circuit 104 can be used to store the potential output to the third control node N3.
  • the third compensation sub-circuit 105 can be respectively coupled to the gate signal terminal G1, the first connection node P1 and the first control node N1.
  • the third compensation sub-circuit 105 can adjust the potential of the third control node N3 according to the potential of the first connection node P1 in response to the gate driving signal.
  • the third compensation sub-circuit 105 may adjust the potential of the third control node N3 according to the potential of the first connection node P1 when the potential of the gate drive signal is the first potential.
  • the pixel circuit further includes a switch control circuit 40 connected in series between the drive circuit 10 and the first connection node P1
  • the connection point between the drive circuit 10 and the switch control circuit 40 can be marked as fourth Connect to node P4.
  • the third compensation sub-circuit 105 is connected to the fourth connection node P4, and adjusts the potential of the third control node N3 based on the potential of the fourth connection node P4.
  • the switch control circuit 40 is also used to control the on/off of the fourth connection node P4 and the first connection node P1 in response to the light emission control signal.
  • the driving sub-circuit 106 can be respectively coupled to the third control node N3, the third connection node P3, and the first connection node P1.
  • the driving sub-circuit 106 can output a driving current to the first connection node P1 in response to the potential of the third control node N3 and the potential of the third connection node P3.
  • the driving sub-circuit 106 may output a driving current to the first connection node P1 based on the potential of the third control node N3 and the potential of the third connection node P3 when the potential of the third control node N3 is the first potential.
  • the pixel circuit further includes a switch control circuit 40, and the driving sub-circuit 106 is connected to the fourth connection node P4.
  • FIG. 8 is a schematic structural diagram of still another pixel circuit provided by an embodiment of the present disclosure.
  • the second data writing sub-circuit 101 may include: a second data writing transistor D2.
  • the second reset sub-circuit 102 may include: a fourth reset transistor F4.
  • the second light emission control sub-circuit 103 may include: a second light emission control transistor M2.
  • the storage sub-circuit 104 may include a storage capacitor C2.
  • the third compensation sub-circuit 105 may include: a fourth compensation transistor B4.
  • the driving sub-circuit 106 may include a driving transistor T1.
  • the gate of the second data writing transistor D2 may be coupled to the gate signal terminal G1
  • the first pole of the second data writing transistor D2 may be coupled to the first data signal terminal DI
  • the second data writing transistor D2 The second pole may be coupled with the third connection node P3.
  • the gate of the fourth reset transistor F4 may be coupled to the reset signal terminal RST, the first pole of the fourth reset transistor F4 may be coupled to the second power supply terminal Vint, and the second pole of the fourth reset transistor F4 may be coupled to the third control terminal.
  • the node N3 is coupled.
  • the gate of the second emission control transistor M2 may be coupled to the emission control signal terminal EM, the first pole of the second emission control transistor M2 may be coupled to the first power supply terminal VDD, and the second pole of the second emission control transistor M2 may be It is coupled to the third connection node P3.
  • One end of the storage capacitor C2 can be coupled to the third control node N3, and the other end of the storage capacitor C2 can be coupled to the first power terminal VDD.
  • the gate of the fourth compensation transistor B4 may be coupled to the gate signal terminal G1, the first pole of the fourth compensation transistor B4 may be coupled to the first connection node P1, and the second pole of the fourth compensation transistor B4 may be coupled to the third The control node N3 is coupled.
  • the switch control transistor Q1 is included, referring to FIG. 8, the first pole of the fourth compensation transistor B4 is coupled to the fourth connection node P4.
  • the gate of the driving transistor T1 may be coupled to the third control node N3, the first stage of the driving transistor T1 may be coupled to the third connection node P3, and the second pole of the driving transistor T1 may be coupled to the first connection node P1.
  • the second pole of the driving transistor T1 is coupled to the fourth connection node P4.
  • each transistor is a P-type transistor, and the first potential is a low potential relative to the second potential.
  • the transistors can also be N-type transistors. When the transistors are N-type transistors, the first potential can be a high potential relative to the second potential.
  • the driving circuit 10 may also be a structure including other numbers of transistors.
  • the 2T1C structure or the 4T1C structure which is not limited in the embodiment of the present disclosure.
  • the embodiments of the present disclosure provide a pixel circuit including a compensation circuit. Because the compensation circuit can adjust the potential of the second control node (that is, the gate of the transistor that controls the on and off of the first connection node and the second connection node) according to the potential of the first control node, and can adjust the potential of the second control node according to the second connection node (that is, control The potential of the second pole of the transistor that turns on and off the first connection node and the second connection node adjusts the potential of the second control node. Therefore, when driving the pixel circuit, the potential of each control signal can be controlled so that the potential finally output to the second control node is less affected by the threshold voltage of the transistor, that is, the threshold voltage drift caused by the display uniformity is reduced. Influence, the display device provided by the embodiment of the present disclosure has a better display effect.
  • FIG. 9 is a flowchart of a method for driving a pixel circuit provided by an embodiment of the present disclosure, and the method can be applied to any of the pixel circuits shown in FIG. 2 to FIG. 8. As shown in Figure 9, the method may include:
  • Step 901 In the reset phase, the potential of the reset signal provided by the reset signal terminal is the first potential, the light emitting control circuit outputs the second power signal from the second power terminal to the first connection node and the first control node in response to the reset signal, and the compensation circuit The potential of the second control node is adjusted according to the potential of the first control node.
  • the light emission control circuit also controls the conduction of the first connection node and the second connection node in response to the potential of the second control node, and the compensation circuit also responds to the reset signal according to the second The potential of the connection node adjusts the potential of the second control node.
  • the potential of the second power signal may be a second potential, and the second potential may be a high potential relative to the first potential.
  • Step 902 In the data writing stage, the potential of the gate driving signal provided by the gate signal terminal is the first potential, and the light emitting control circuit outputs the second data signal from the second data signal terminal to the first control node in response to the gate driving signal , The compensation circuit adjusts the potential of the second control node according to the potential of the first control node.
  • Step 903 In the light-emitting control phase, the driving circuit responds to the first power signal from the first power terminal, the gate drive signal, and the first data signal from the first data signal terminal to output a driving current to the first connection node, and the light-emitting control signal terminal
  • the light-emission control signal provided has a first potential.
  • the compensation circuit responds to the light-emission control signal to adjust the potential of the second control node according to the potential of the first control node and the third power signal from the third power terminal.
  • the light-emission control circuit responds to the first control node.
  • the potential of the two control nodes controls the first connection node and the second connection node to conduct, and controls the second connection node and the light emitting element to conduct in response to the light emission control signal.
  • the potential of the third power signal may be a third potential, and the third potential may be a low potential relative to the second potential.
  • the embodiments of the present disclosure provide a method for driving a pixel circuit. Because of this method, the compensation circuit can adjust the potential of the second control node (that is, the gate of the transistor that controls the on and off of the first connection node and the second connection node) according to the potential of the first control node, and can adjust the potential of the second control node according to the second connection node. (That is, the second pole of the transistor that controls the on and off of the first connection node and the second connection node) adjusts the potential of the second control node.
  • the second control node that is, the gate of the transistor that controls the on and off of the first connection node and the second connection node
  • the potential of each control signal can be controlled so that the potential finally output to the second control node is less affected by the threshold voltage of the transistor, that is, the threshold voltage drift caused by the display uniformity is reduced. Influence, the display device provided by the embodiment of the present disclosure has a better display effect.
  • the circuit composed of the light emission control circuit 20 and the compensation circuit 30 as the duration control circuit 100, and each transistor included in the pixel circuit is a P-type transistor, and the first potential (that is, the effective potential) is opposite to Taking the second potential (ie, the invalid potential) as a low potential, and the third potential being a low potential relative to the first potential as an example, the driving principle of the pixel circuit provided by the embodiment of the present disclosure is described in detail.
  • FIG. 10 is a timing diagram of each signal terminal in a pixel circuit provided by an embodiment of the present disclosure.
  • the potential of the reset signal provided by the reset signal terminal RST is the first potential
  • Both and the third compensation transistor B3 are turned on.
  • the second power terminal Vint can output the second power signal at the second potential to the first connection node P1 through the first reset transistor F1, so as to reset the first connection node P1.
  • the second power terminal Vint can output the second power signal at the second potential to the first control node N1 through the second reset transistor F2, so as to reset the first control node N1.
  • the second power terminal Vint can output the second power signal at the second potential to the light-emitting element L1 through the third reset transistor F3, so as to reset the light-emitting element L1.
  • the second power terminal Vint can output the second power signal at the second potential to the third control node N3 through the fourth reset transistor F4, so as to reset the third control node N3.
  • the storage capacitor C2 can store the potential of the third control node N3.
  • the potential of the second control node N2 also becomes the second potential. Accordingly, the switching transistor K1 is turned on, and the first connection node P1 and the second connection node P2 are turned on. At this time, the third compensation transistor B3 can adjust the potential of the second control node N2 according to the potential of the second connection node P2, thereby writing the second power signal and the threshold voltage of the switching transistor K1 to the second control node N2.
  • the third compensation transistor B3 can adjust the potential of the second control node N2 according to the potential of the second connection node P2, thereby writing the second power signal and the threshold voltage of the switching transistor K1 to the second control node N2.
  • the potential of the gate drive signal provided by the gate signal terminal G1 and the potential of the light emission control signal provided by the light emission control signal terminal EM are both the second potential, except for the above-mentioned turn-on All other transistors except the transistors are turned off.
  • the equivalent circuit diagram of the pixel circuit in the reset stage t1 can refer to FIG. 11 (the dotted line in the figure refers to the disconnection).
  • the potential of the second power signal is Vint0
  • the threshold voltage of the switching transistor K1 is Vth1.
  • the potential of the first control node N1 is: Vint0
  • the potential of the second control node N2 is: Vint0+Vth1
  • the potential of the third control node N3 is: Vint0.
  • the potential of the gate signal provided by the gate drive signal terminal G1 is the first potential
  • the first data signal terminal DI provides the first data signal
  • the second data signal terminal DT provides The second data signal (the first data signal and the second data signal are not shown in FIG. 10).
  • the first data writing transistor D1, the second data writing transistor D2, and the fourth compensation transistor B4 are all turned on.
  • the first data signal terminal DI can output the first data signal to the third connection node P3 through the second data writing transistor D2, so as to charge the third connection node P3.
  • the second data signal terminal DT can output the second data signal to the first control node N1 through the first data writing transistor D1, so as to charge the first control node N1.
  • the potential of the second control node N2 becomes the sum of the second data signal and the threshold voltage of the switching transistor K1.
  • the third control node N3 Since in the reset phase t1, the third control node N3 is written with the second power signal of the second potential, and the storage capacitor C2 stores the potential of the third control node N3, therefore, in the data writing phase t2, the driving transistor T1 Can be turned on. At this time, the potential of the third connection node P3 is output to the fourth connection node P4 through the driving transistor T1, and the fourth compensation transistor B4 adjusts the potential of the third control node N3 according to the potential of the fourth connection node P4. Thus, the first data signal and the threshold voltage of the driving transistor T1 are written to the third control node N3, and the storage capacitor C2 continues to store the potential of the third control node N3.
  • the potential of the reset signal provided by the reset signal terminal RST and the potential of the light emission control signal provided by the light emission control signal terminal EM are both the second potential, except for the above data writing All transistors other than the transistors turned on in phase t2 are turned off.
  • the equivalent circuit diagram of the pixel circuit in the data writing stage t2 can refer to FIG. 12 (the dotted line in the figure refers to the disconnection).
  • the potential of the first data signal is VdataI
  • the potential of the second data signal is VdataT
  • the threshold voltage of the driving transistor T1 is Vth2
  • the first control node The potential of N1 becomes: VdataT
  • the potential of the second control node N2 is: VdataT+Vth1
  • the potential of the third control node N3 is: VdataI+Vth2.
  • the light-emission control signal provided by the light-emission control signal terminal EM has a first potential, the first light-emission control transistor M1, the second light-emission control transistor M2, the first compensation transistor B1, and the second Both the compensation transistor B2 and the switch control transistor Q1 are turned on.
  • the potential of the third control node N3 is the sum of the first data signal and the threshold voltage of the driving transistor T1, and the driving transistor T1 is turned on.
  • the first power terminal VDD outputs the first power signal at the first potential to the third connection node P3 through the second light-emitting control transistor M3.
  • the driving transistor T1 transmits the first power signal to the third connection node P3 based on the first power signal and the potential of the third control node N3.
  • the four connection node P4 outputs the drive current.
  • the potential of the fourth connection node P4 can be continuously output to the first connection node P1 through the switch control transistor Q1.
  • the third power terminal VSS can output the third power signal of the third potential to the first control node N1 through the RC discharge circuit composed of the first compensation transistor B1, the second compensation transistor B2, the compensation resistor R1 and the compensation capacitor C1, and pull it down.
  • the first control node N1 potential Assuming that the third power terminal VSS is a ground terminal, the first control node N1 is grounded. Under the coupling effect of the compensation capacitor C1, the potential of the second control node N2 begins to decrease until it decreases to turn on the switching transistor K1.
  • the switching transistor K1 When the switching transistor K1 is turned on, the first connection node P1 and the second connection node P2 can be controlled to be turned on, and the driving current can be further output to the second connection node P2 through the switching transistor K1, and then through the first light-emitting control transistor M1 The output is output to the light-emitting element L1, thereby driving the light-emitting element L1 to emit light. This stage continues until the potential of the light-emitting control signal provided by the light-emitting control signal terminal EM jumps to the first potential.
  • the potential of the gate driving signal provided by the gate signal terminal G1 and the potential of the light-emitting control signal provided by the light-emitting control signal terminal EM are both the second potential, except for the above-mentioned light-emitting All transistors other than the transistors turned on in phase t3 are turned off.
  • the equivalent circuit diagram of the pixel circuit in the light-emitting stage t3 refer to FIG. 13.
  • the potential of the first power signal is VDD1
  • the potential of the third power signal is 0
  • the potential of the first data signal is VdataI
  • the potential of the second data signal is VdataT
  • the threshold voltage of the switching transistor K1 is Vth1
  • the drive The threshold voltage of the transistor T1 is Vth2
  • the resistance value of the compensation resistor R1 is r1
  • the capacitance value of the compensation capacitor C1 is c1.
  • the potential of the first control node N1 becomes: 0; the potential of the second control node N2 becomes: (VdataT+Vth1)*e (-t/r1*c1 ) ; The potential of the third control node N3 is: VdataI+Vth2.
  • the compensation principle of the threshold voltage Vth1 of the driving transistor T1 is introduced as follows:
  • Vg1 the potential of the gate of the driving transistor T1 (such as the third control node N3) is denoted as Vg1
  • the source of the driving transistor T1 such as the third connection node P3
  • the gate-source voltage of the driving transistor T1 are denoted as Vg1.
  • Vgs1 the Vgs1 provided by the embodiments of the present disclosure can satisfy:
  • k is the characteristics of the driving transistor T1 itself, which is determined by the carrier mobility of the driving transistor T1, the capacitance of the gate insulating layer, and the aspect ratio.
  • the light-emitting element L1 is a Micro LED
  • the potential of the first data signal provided by the first data signal terminal DI can be flexibly set, that is, flexible Setting VdataI enables the Micro LED to work under high current density, that is, the region with stable luminous efficiency, to ensure display stability.
  • the compensation principle of the threshold voltage Vth2 of the switching transistor K1 is introduced as follows:
  • the switching transistor K1 is turned on under the condition that the absolute value of the gate-source voltage difference is greater than or equal to the absolute value of the threshold voltage.
  • the voltage difference is recorded as Vgs2, and the conduction condition is
  • Vgs2 Under the action of the RC discharge circuit, Vgs2 can satisfy:
  • the coefficient value becomes: 1-e (-t/r1*c1) ; if the threshold voltage of the switching transistor K1 is not compensated, the coefficient The value is e (-t/r1*c1) .
  • Figure 14 shows a schematic diagram of the coefficients before compensation
  • Figure 15 shows a schematic diagram of the coefficients after compensation.
  • the horizontal axis represents time, and the vertical axis represents the obtained coefficient value. Comparing FIG. 14 and FIG. 15, it can be seen that the coefficient value of the threshold voltage of the switching transistor K1 before compensation is about 1, and the coefficient value after compensation is about 0.001.
  • the impact of the threshold voltage drift of the switching transistor K1 on the light-emitting duration of the light-emitting element L1 is effectively reduced.
  • the threshold voltage of the switching transistor K1 and the threshold voltage of the driving transistor T1 By compensating the threshold voltage of the switching transistor K1 and the threshold voltage of the driving transistor T1, the impact of threshold voltage drift on the display uniformity is effectively reduced, the mura phenomenon of the display device is greatly reduced, and the display is improved. The display effect of the device.
  • FIG. 16 shows the relationship between the light-emitting duration and the potential of the second data signal provided by the second data signal terminal DT. relation.
  • the horizontal axis may refer to time t00, and the vertical axis may refer to potential (unit: volt V).
  • FIG. 16 also shows the light-emitting time sequence corresponding to the light-emitting element L1.
  • the emission time (emission time1) t01 corresponding to the second data signal VdataT1 with a larger potential is smaller than the emission time (emission time2) t02 corresponding to the second data signal VdataT2 with a smaller potential.
  • the light-emitting brightness of the light-emitting element L1 has a linear relationship with the light-emitting duration in each frame of the display stage, the light-emitting brightness corresponding to the light-emitting element L1 is also different under different light-emitting durations. That is, through the control of the light-emitting duration, the adjustment of the gray scale is also flexibly realized.
  • FIG. 17 also shows the simulation results of the potentials and light-emitting durations of different second data signals.
  • the horizontal axis refers to time t00 (unit: milliseconds: ms), and the vertical axis refers to potential (unit: V).
  • V N2 of the second control node N2 when the driving switch transistor K1 is turned on is about 1V
  • FIG. 17 it can be seen that the time required for the second data signal of different sizes to drop to about 1V is different.
  • the required time t00 from 2V to about 1V is 798.28 microseconds ( ⁇ s); the time required to decrease from 3V to about 1V is 1.2082ms; the time required to decrease from 4V to 1V is 1.4953ms; The time required to reach about 1V, t00, is 1.7156ms.
  • the longer the time required to decrease to about 1V the shorter the light-emitting time of the light-emitting element L1 is correspondingly shorter.
  • the potential VdataT of the second data signal and the potential V N2 of the second control node N2 satisfy:
  • V N2 (VdataT-Vint0)*e (-t/r1*c1) formula (7);
  • the light-emitting time t00 of the light-emitting element L1 can satisfy:
  • the embodiments of the present disclosure provide a method for driving a pixel circuit. Because of this method, the compensation circuit can adjust the potential of the second control node (that is, the gate of the transistor that controls the on and off of the first connection node and the second connection node) according to the potential of the first control node, and can adjust the potential of the second control node according to the second connection node. (That is, the second pole of the transistor that controls the on and off of the first connection node and the second connection node) adjusts the potential of the second control node.
  • the second control node that is, the gate of the transistor that controls the on and off of the first connection node and the second connection node
  • the potential of each control signal can be controlled so that the potential finally output to the second control node is less affected by the threshold voltage of the transistor, that is, the threshold voltage drift caused by the display uniformity is reduced. Influence, the display device provided by the embodiment of the present disclosure has a better display effect.
  • FIG. 18 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate 001 may include: a plurality of pixel units 00.
  • each pixel unit 00 may include a light-emitting element L1
  • at least one pixel unit 01 may include a pixel circuit 01 as shown in any one of FIGS. 2 to 8.
  • each pixel unit 00 included in the display substrate 001 shown in FIG. 18 includes the pixel circuit 01 shown in any one of FIGS. 2 to 8.
  • the light-emitting element may include: Micro LED.
  • FIG. 19 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure. As shown in FIG. 19, the display device may include: a signal driving circuit 02, and a display substrate 001 as shown in FIG. 18.
  • the signal driving circuit 02 can be coupled to each signal terminal of the pixel circuit 01 included in the display substrate 001, and the signal driving circuit 02 can be used to provide signals for each signal terminal.
  • the signal driving circuit 02 may include a gate driving circuit and a source driving circuit.
  • the gate driving circuit may be connected to the gate signal terminal G1 in the pixel circuit 01 to provide a gate signal for the gate signal terminal G1.
  • the source driving circuit may be connected to the first data signal terminal DI and the second data signal terminal DT in the pixel circuit 01 to provide data signals for the first data signal terminal DI and the second data signal terminal DT.
  • the gate driving circuit may be connected to the gate signal terminal G1 through a gate line, and the source driving circuit may be connected to the data signal terminals DI and DT through a data signal line.
  • the gate signal terminals G1 included in the pixel circuits located in the same row may be connected to the same gate line, and the first data signal terminals DI included in the pixel circuits located in the same column may be connected to the same first data line and are located in the same column.
  • the second data signal terminal DT included in the pixel circuit may be connected to the same second data line.
  • the gate driving circuit may sequentially output a gate driving signal at the first potential to the gate signal terminal G1 connected to each row of pixel circuits through each gate line.
  • the source driving circuit may have different potentials of the first data signal output to the same first data line at different moments. That is, the source driving circuit transmits the same first data line to different rows located in the same column.
  • the potential of the first data signal output by each first data signal terminal DI included in the pixel circuit may be different; the second data signal terminal DT is the same, and will not be repeated here.
  • first data Line two pixel circuits located in the first row, first column and second row, first column, and the same first data line connected to the first data signal terminal DI of the two pixel circuits are called first data Line as an example. It is assumed that in the data writing stage when the pixel circuits of the first row are driven, the potential of the first data signal provided by the source driving circuit to the pixel circuits located in the first row and first column through the first data line is VdataI1. In the data writing stage when the pixel circuits of the second row are driven, the potential of the first data signal provided by the source driving circuit to the pixel circuits located in the second row and first column through the first data line is VdataI2. Then VdataI1 and VdataI2 may be the same or different.
  • the display device can be: Micro LED display device, liquid crystal panel, electronic paper, OLED panel, AMOLED panel, mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame and other products with display function or part.

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Abstract

一种像素电路（01）及其驱动方法、显示基板（001）、显示装置。像素电路（01）包括补偿电路（30），由于补偿电路（30）可以根据第一控制节点（N1）的电位调整第二控制节点（N2）的电位，且可以根据第二连接节点（P2）的电位调整第二控制节点（N2）的电位。因此在对像素电路（01）进行驱动时，可以通过控制各控制信号的电位，使得最终输出至第二控制节点（N2）的电位受晶体管的阈值电压影响较小，即降低了阈值电压漂移对显示均一性造成的影响。

Description

像素电路及其驱动方法、显示基板、显示装置
本公开要求于2020年3月17日提交的申请号为202010188767.7、发明名称为“像素电路及其驱动方法、显示基板、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别涉及一种像素电路及其驱动方法、显示基板、显示装置。
背景技术
微型发光二极管(micro light emitting diode，Micro LED)因其高亮度、高发光效率、体积小且功耗低等诸多优点被广泛的应用于各类显示装置中。
相关技术中，驱动Micro LED发光的像素电路一般包括：驱动晶体管和开关晶体管。其中，开关晶体管可以将其所耦接的数据信号端提供的数据电压输出至驱动晶体管；驱动晶体管可以将该数据电压转换为用于驱动Micro LED发光的驱动电流输出至Micro LED以驱动Micro LED发光。
但是，由于驱动电流的大小与驱动晶体管的阈值电压相关，因此当驱动晶体管的阈值电压发生漂移时，会导致输出至Micro LED的驱动电流出现异常，进而导致Micro LED显示装置的显示亮度的均匀性较低，显示效果较差。
发明内容
本公开提供了一种像素电路及其驱动方法、显示基板、显示装置。所述技术方案如下：
一方面，提供了一种像素电路，所述像素电路包括：驱动电路、发光控制电路和补偿电路；
所述驱动电路分别与第一电源端、栅极信号端、第一数据信号端和第一连接节点耦接，所述驱动电路用于响应于来自所述第一电源端的第一电源信号，来自所述栅极信号端的栅极驱动信号以及来自所述第一数据信号端的第一数据 信号，向所述第一连接节点输出驱动电流；
所述发光控制电路分别与所述第一连接节点、所述栅极信号端、复位信号端、发光控制信号端、第二电源端、第二数据信号端、第一控制节点、第二控制节点、第二连接节点和发光元件耦接，所述发光控制电路用于响应于来自所述复位信号端的复位信号向所述第一连接节点和所述第一控制节点输出来自所述第二电源端的第二电源信号，用于响应于所述栅极驱动信号向所述第一控制节点输出来自所述第二数据信号端的第二数据信号，用于响应于来自所述发光控制信号端的发光控制信号控制所述第二连接节点与所述发光元件的通断，以及用于响应于所述第二控制节点的电位控制所述第一连接节点和所述第二连接节点的通断；
所述补偿电路分别与第三电源端、所述发光控制信号端、所述复位信号端、所述第一控制节点、所述第二控制节点和所述第二连接节点耦接，所述补偿电路用于根据所述第一控制节点的电位调整所述第二控制节点的电位，用于响应于所述复位信号根据所述第二连接节点的电位调整所述第二控制节点的电位，以及用于响应于所述发光控制信号根据所述第一控制节点的电位，以及来自所述第三电源端的第三电源信号调整所述第二控制节点的电位。
可选的，所述补偿电路包括：第一补偿子电路和第二补偿子电路；
所述第一补偿子电路分别与所述发光控制信号端、所述第三电源端、所述第一控制节点和所述第二控制节点耦接，所述第一补偿子电路用于根据所述第一控制节点的电位调整所述第二控制节点的电位，以及用于响应于所述发光控制信号根据所述第三电源信号和所述第一控制节点的电位调整所述第二控制节点的电位；
所述第二补偿子电路分别与所述复位信号端、所述第二连接节点和所述第二控制节点耦接，所述第二补偿子电路用于响应于所述复位信号根据所述第二连接节点的电位调整所述第二控制节点的电位。
可选的，所述第一补偿子电路包括：第一补偿晶体管、第二补偿晶体管、补偿电容和补偿电阻；
所述第一补偿晶体管的栅极与所述发光控制信号端耦接，所述第一补偿晶体管的第一极与所述第三电源端耦接，所述第一补偿晶体管的第二极与所述第一控制节点耦接；
所述第二补偿晶体管的栅极与所述发光控制信号端耦接，所述第二补偿晶体管的第一极与所述补偿电阻的一端耦接，所述第二补偿晶体管的第二极与所述第二控制节点耦接；
所述补偿电阻的另一端与所述第三电源端耦接；
所述补偿电容的一端与所述第一控制节点耦接，所述补偿电容的另一端与所述第二控制节点耦接。
可选的，所述第二补偿子电路包括：第三补偿晶体管；
所述第三补偿晶体管的栅极与所述复位信号端耦接，所述第三补偿晶体管的第一极与所述第二连接节点耦接，所述第三补偿晶体管的第二极与所述第二控制节点耦接。
可选的，所述发光控制电路还用于响应于所述复位信号，向所述发光元件输出所述第二电源信号；所述发光控制电路包括：第一复位子电路、第一数据写入子电路、第一发光控制子电路和开关子电路；
所述第一复位子电路分别与所述复位信号端、所述第二电源端、所述第一连接节点、所述第一控制节点和所述发光元件耦接，所述第一复位子电路用于响应于所述复位信号向所述第一连接节点、所述第一控制节点和所述发光元件输出所述第二电源信号；
所述第一数据写入子电路分别与所述栅极信号端、所述第二数据信号端和所述第一控制节点耦接，所述第一数据写入子电路用于响应于所述栅极驱动信号向所述第一控制节点输出所述第二数据信号；
所述第一发光控制子电路分别与所述发光控制信号端、所述第二连接节点和所述发光元件耦接，所述第一发光控制子电路用于响应于所述发光控制信号控制所述第二连接节点和所述发光元件的通断；
所述开关子电路分别与所述第二控制节点、所述第一连接节点和所述第二连接节点耦接，所述开关子电路用于响应于所述第二控制节点的电位控制所述第一连接节点和所述第二连接节点的通断。
可选的，所述第一复位子电路包括：第一复位晶体管、第二复位晶体管和第三复位晶体管；
所述第一复位晶体管、所述第二复位晶体管和所述第三复位晶体管的栅极均与所述复位信号端耦接；
所述第一复位晶体管、所述第二复位晶体管和所述第三复位晶体管的第一极均与所述第二电源端耦接；
所述第一复位晶体管的第二极与所述第一连接节点耦接，所述第二复位晶体管的第二极与所述第一控制节点耦接，所述第三复位晶体管的第二极与所述发光元件耦接。
可选的，所述第一数据写入子电路包括：第一数据写入晶体管；
所述第一数据写入晶体管的栅极与所述栅极信号端耦接，所述第一数据写入晶体管的第一极与所述第二数据信号端耦接，所述第一数据写入晶体管的第二极与所述第一控制节点耦接。
可选的，所述第一发光控制子电路包括：第一发光控制晶体管；
所述第一发光控制晶体管的栅极与所述发光控制信号端耦接，所述第一发光控制晶体管的第一极与所述第二连接节点耦接，所述第一发光控制晶体管的第二极与所述发光元件耦接。
可选的，所述开关子电路包括：开关晶体管；
所述开关晶体管的栅极与所述第二控制节点耦接，所述开关晶体管的第一极与所述第一连接节点耦接，所述开关晶体管的第二极与所述第二连接节点耦接。
可选的，所述像素电路还包括：串联在所述驱动电路和所述第一连接节点之间的开关控制电路；
所述开关控制电路分别与所述发光控制信号端、所述驱动电路和所述第一连接节点耦接，所述开关控制电路用于响应于所述发光控制信号控制所述驱动电路和所述第一连接节点的通断。
可选的，所述开关控制电路包括：开关控制晶体管；
所述开关控制晶体管的栅极与所述发光控制信号端耦接，所述开关控制晶体管的第一极与所述驱动电路耦接，所述开关控制晶体管的第二极与所述第一连接节点耦接。
可选的，所述驱动电路包括：第二数据写入子电路、第二复位子电路、第二发光控制子电路、存储子电路、第三补偿子电路和驱动子电路；
所述第二数据写入子电路分别与所述栅极信号端、所述第一数据信号端和第三连接节点耦接，所述第二数据写入子电路用于响应于所述栅极驱动信号向 所述第三连接节点输出所述第一数据信号；
所述第二复位子电路分别与所述复位信号端、所述第二电源端和第三控制节点耦接，所述第二复位子电路用于响应于所述复位信号向所述第三控制节点输出所述第二电源信号；
所述第二发光控制子电路分别与所述发光控制信号端、所述第一电源端和所述第三连接节点耦接，所述第二发光控制子电路用于响应于所述发光控制信号向所述第三连接节点输出所述第一电源信号；
所述存储子电路分别与所述第三控制节点和所述第一电源端耦接，所述存储子电路用于控制所述第三控制节点的电位；
所述第三补偿子电路分别与所述栅极信号端、所述第一连接节点和所述第一控制节点耦接，所述第三补偿子电路用于响应于所述栅极驱动信号根据所述第一连接节点的电位调整所述第三控制节点的电位；
所述驱动子电路分别与所述第三控制节点、所述第三连接节点和所述第一连接节点耦接，所述驱动子电路用于响应于所述第三控制节点的电位和所述第三连接节点的电位，向所述第一连接节点输出驱动电流。
可选的，所述第二数据写入子电路包括：第二数据写入晶体管；所述第二复位子电路包括：第四复位晶体管；所述第二发光控制子电路包括：第二发光控制晶体管；所述存储子电路包括：存储电容；所述第三补偿子电路包括：第四补偿晶体管；所述驱动子电路包括：驱动晶体管；
所述第二数据写入晶体管的栅极与所述栅极信号端耦接，所述第二数据写入晶体管的第一极与所述第一数据信号端耦接，所述第二数据写入晶体管的第二极与所述第三连接节点耦接；
所述第四复位晶体管的栅极与所述复位信号端耦接，所述第四复位晶体管的第一极与所述第二电源端耦接，所述第四复位晶体管的第二极与所述第三控制节点耦接；
所述第二发光控制晶体管的栅极与所述发光控制信号端耦接，所述第二发光控制晶体管的第一极与所述第一电源端耦接，所述第二发光控制晶体管的第二极与所述第三连接节点耦接；
所述存储电容的一端与所述第三控制节点耦接，所述存储电容的另一端与所述第一电源端耦接；
所述第四补偿晶体管的栅极与所述栅极信号端耦接，所述第四补偿晶体管的第一极与所述第一连接节点耦接，所述第四补偿晶体管的第二极与所述第三控制节点耦接；
所述驱动晶体管的栅极与所述第三控制节点耦接，所述驱动晶体管的第一级与所述第三连接节点耦接，所述驱动晶体管的第二极与所述第一连接节点耦接。
另一方面，提供了一种像素电路的驱动方法，用于驱动如上述方面所述的像素电路，所述方法包括：
复位阶段，复位信号端提供的复位信号的电位为第一电位，发光控制电路响应于所述复位信号向第一连接节点和第一控制节点输出来自第二电源端的第二电源信号，补偿电路根据所述第一控制节点的电位调整第二控制节点的电位，所述发光控制电路还响应于所述第二控制节点的电位控制所述第一连接节点和第二连接节点导通，所述补偿电路还响应于所述复位信号根据所述第二连接节点的电位调整所述第二控制节点的电位；
数据写入阶段，栅极信号端提供的栅极驱动信号的电位为第一电位，所述发光控制电路响应于所述栅极驱动信号向所述第一控制节点输出来自第二数据信号端的第二数据信号，所述补偿电路根据所述第一控制节点的电位调整所述第二控制节点的电位；
发光控制阶段，驱动电路响应于来自第一电源端的第一电源信号、所述栅极驱动信号和来自第一数据信号端的第一数据信号，向所述第一连接节点输出驱动电流，发光控制信号端提供的发光控制信号的电位为第一电位，所述补偿电路响应于所述发光控制信号根据所述第一控制节点的电位和来自第三电源端的第三电源信号调整所述第二控制节点的电位，所述发光控制电路响应于所述第二控制节点的电位控制所述第一连接节点和所述第二连接节点导通，以及响应于所述发光控制信号控制所述第二连接节点和所述发光元件导通。
又一方面，提供了一种显示基板，所述显示基板包括：多个像素单元，所述多个像素单元中，至少一个所述像素单元包括：发光元件，以及与所述发光元件耦接的如上述方面所述的像素电路。
可选的，所述发光元件包括：微型发光二极管。
再一方面，提供了一种显示装置，所述显示装置包括：信号驱动电路，以 及如上述方面所述的显示基板；
所述信号驱动电路与所述显示基板包括的像素电路中的各信号端耦接，所述信号驱动电路用于为所述各信号端提供信号。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种Micro LED的发光效率和电流密度示意图；
图2是本公开实施例提供的一种像素电路的结构示意图；
图3是本公开实施例提供的另一种像素电路的结构示意图；
图4是本公开实施例提供的又一种像素电路的结构示意图；
图5是本公开实施例提供的再一种像素电路的结构示意图；
图6是本公开实施例提供的再一种像素电路的结构示意图；
图7是本公开实施例提供的再一种像素电路的结构示意图；
图8是本公开实施例提供的再一种像素电路的结构示意图；
图9是本公开实施例提供的一种像素电路的驱动方法流程图；
图10是本公开实施例提供的一种像素电路各信号端的时序图；
图11是本公开实施例提供的一种像素电路在复位阶段的等效电路图；
图12是本公开实施例提供的一种像素电路在数据写入阶段的等效电路图；
图13是本公开实施例提供的一种像素电路在发光阶段的等效电路图；
图14是相关技术中的一种第二控制节点电位的系数值示意图；
图15是本公开实施例提供的一种第二控制节点电位的系数值示意图；
图16是本公开实施例提供的一种发光时长和数据信号电位关系示意图；
图17是本公开实施例提供的一种发光时长和数据信号电位关系仿真图；
图18是本公开实施例提供的一种显示基板的结构示意图；
图19是本公开实施例提供的一种显示装置的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用本公开的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，将其中源极称为第一极，漏极称为第二极，或者，可以将漏极称为第一极，源极称为第二极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。本公开实施例所采用的开关晶体管可以为P型开关晶体管，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止。此外，本公开各个实施例中的多个信号都对应有第一电位和第二电位。第一电位和第二电位仅代表该信号的电位有2个状态量，不代表全文中第一电位或第二电位具有特定的数值。本公开实施例中以第一电位为有效电位为例进行说明。
Micro LED可以理解为将LED微缩化和矩阵化后的一种自发光元件，其发光效率和输出至其的驱动电流的电流密度具有一定关系。例如，图1示出了一种Micro LED的发光效率和电流密度的关系。如图1所示，其横轴，即x轴可以是指电流密度；其纵轴，即y轴可以是指发光效率。
参考图1可以看出，Micro LED的发光效率会随着电流密度的变化而变化，且在低电流密度下(如图1所示的0-J1区间)发光效率的变化较为明显，在高电流密度下(如图1所示的J1-J2区间)发光效率较为稳定，不会发生明显变化。Micro LED的色坐标也会随着电流密度的变化而发生变化。且若采用相关技术中的像素电路驱动Micro LED发光，Micro LED的发光亮度还会受到阈值电压漂移的影响。相关技术中Micro LED的发光效率稳定性较差，Micro LED显示装置的显示均一性较差。
本公开实施例提供了一种像素电路，该像素电路不仅能够避免因驱动晶体管的阈值电压漂移而造成显示亮度均一性较差的现象，而且能够通过调节驱动电流大小和Micro LED的发光时长共同控制灰阶，保证Micro LED可以始终工作在高电流密度下，即使得Micro LED的发光效率能够始终保证稳定。
图2是本公开实施例提供的一种像素电路的结构示意图。如图2所示，该像素电路可以包括：驱动电路10、发光控制电路20和补偿电路30。
该驱动电路10可以分别与第一电源端VDD、栅极信号端G1、第一数据信号端DI和第一连接节点P1耦接。该驱动电路10可以响应于来自第一电源端VDD的第一电源信号，来自栅极信号端G1的栅极驱动信号以及来自第一数据信号端DI的第一数据信号，向第一连接节点P1输出驱动电流。
该发光控制电路20可以分别与第一连接节点P1、栅极信号端G1、复位信号端RST、发光控制信号端EM、第二电源端Vint、第二数据信号端DT、第一控制节点N1、第二控制节点N2、第二连接节点P2和发光元件L1耦接。该发光控制电路20可以用于响应于来自复位信号端RST的复位信号向第一连接节点P1和第一控制节点N1输出来自第二电源端Vint的第二电源信号，用于响应于栅极驱动信号向第一控制节点N1输出来自第二数据信号端DT的第二数据信号，用于响应于来自发光控制信号端EM的发光控制信号控制第二连接节点P2与发光元件L1的通断，以及用于响应于第二控制节点N2的电位控制第一连接节点P1和第二连接节点P2的通断。
例如，该发光控制电路20可以在复位信号端RST提供的复位信号的电位为第一电位时，向第一连接节点P1和第一控制节点N1输出来自第二电源端Vint的第二电源信号，该第二电源信号的电位可以为第二电位，从而实现对第一连接节点P1和第一控制节点N1的复位。可选的，该第一电位可以为有效电位，该第二电位可以为无效电位，且第一电位相对于第二电位可以为低电位，即第一电位的信号的电压小于第二电位的信号的电压。
又例如，该发光控制电路20可以在栅极信号端G1提供的栅极驱动信号的电位为第一电位时，向第一控制节点N1输出来自第二数据信号端DT的第二数据信号。可以在发光控制信号端EM提供的发光控制信号的电位为第一电位时，控制第二连接节点P2与发光元件L1导通。且可以在第二控制节点N2的电位为第一电位时，控制第一连接节点P1和第二连接节点P2导通。若第一电位相对于第二电位为低电位，则也即是发光控制电路20可以在第二控制节点N2的电位小于电位阈值时，控制第一连接节点P1和第二连接节点P2导通。
该补偿电路30可以分别与第三电源端VSS、发光控制信号端EM、复位信号端RST、第一控制节点N1、第二控制节点N2和第二连接节点P2耦接。该补 偿电路30可以根据第一控制节点N1的电位调整第二控制节点N2的电位，可以响应于复位信号根据第二连接节点P2的电位调整第二控制节点N2的电位，以及可以响应于发光控制信号根据第一控制节点N1的电位和来自第三电源端VSS的第三电源信号调整第二控制节点N2的电位。
例如，该补偿电路30可以通过耦合作用根据第一控制节点N1的电位调整第二控制节点N2的电位。该补偿电路30可以在复位信号的电位为第一电位时，根据第二连接节点P2的电位调整第二控制节点N2的电位。且该补偿电路30可以在发光控制信号的电位为第一电位时，根据第一控制节点N1的电位和第三电源信号调整第二控制节点N2的电位。
可选的，该第三电源信号的电位可以为第三电位，且第三电位相对于第二电位也可以为低电位。如，该第三电源信号端VSS可以为地端。
基于上述各电路的功能可以得出：本公开实施例记载的驱动电路10可以基于第一数据信号控制驱动电流的大小；发光控制电路20和补偿电路30可以基于第二数据信号控制将驱动电流输出至发光元件L1的时长，即控制发光元件L1的发光时长。相应的，该第一数据信号也可以称为电流控制数据信号；第二数据信号也可以称为时长控制数据信号。驱动电路10可以称为电流控制电路；发光控制电路20和补偿电路30组成的电路可以称为时间控制电路。
综上所述，本公开实施例提供了一种像素电路，该像素电路包括补偿电路。由于该补偿电路可以根据第一控制节点的电位调整第二控制节点(即控制第一连接节点和第二连接节点通断的晶体管的栅极)的电位，且可以根据第二连接节点(即控制第一连接节点和第二连接节点通断的晶体管的第二极)的电位调整第二控制节点的电位。因此在对像素电路进行驱动时，可以通过控制各控制信号的电位，使得最终输出至第二控制节点的电位受该晶体管的阈值电压影响较小，即降低了阈值电压漂移对显示均一性造成的影响，本公开实施例提供的显示装置的显示效果较好。
图3是本公开实施例提供的另一种像素电路的结构示意图。如图3所示，该补偿电路30可以包括：第一补偿子电路301和第二补偿子电路302。
该第一补偿子电路301可以分别与发光控制信号端EM、第三电源端VSS、第一控制节点N1和第二控制节点N2耦接。该第一补偿子电路301可以根据第 一控制节点N1的电位调整第二控制节点N2的电位，且可以响应于发光控制信号根据第三电源信号和第一控制节点N1的电位调整第二控制节点N2的电位。
例如，该第一补偿子电路301可以通过耦合作用，根据第一控制节点N1的电位调整第二控制节点N2的电位；且可以在发光控制信号的电位为第一电位时，根据第三电源信号和第一控制节点N1的电位调整第二控制节点N2的电位。可选的，若有效电位为低电位，则该第一补偿子电路301可以通过第三电源信号拉低第一控制节点N1的电位，再基于第一控制节点N1的电位进一步拉低第二控制节点N2的电位，从而实现对第二控制节点N2电位的调整。
该第二补偿子电路302可以分别与复位信号端RST、第二连接节点P2和第二控制节点N2耦接。该第二补偿子电路302可以响应于复位信号根据第二连接节点P2的电位调整第二控制节点N2的电位。
例如，该第二补偿子电路302可以在复位信号的电位为第一电位时，根据第二连接节点P2的电位调整第二控制节点N2的电位。
图4是本公开实施例提供的另一种像素电路的结构示意图。如图4所示，该第一补偿子电路301可以包括：第一补偿晶体管B1、第二补偿晶体管B2、补偿电容C1和补偿电阻R1。
参考图4，该第一补偿晶体管B1的栅极可以与发光控制信号端EM耦接，第一补偿晶体管B1的第一极可以与第三电源端VSS耦接，第一补偿晶体管B1的第二极可以与第一控制节点N1耦接。
该第二补偿晶体管B2的栅极可以与发光控制信号端EM耦接，第二补偿晶体管B2的第一极可以与补偿电阻R1的一端耦接，第二补偿晶体管B2的第二极可以与第二控制节点N2耦接。
该补偿电阻R1的另一端可以与第三电源端VSS耦接。
该补偿电容C1的一端可以与第一控制节点N1耦接，补偿电容C1的另一端可以与第二控制节点N2耦接。
可选的，参考图4，该第二补偿子电路302可以包括：第三补偿晶体管B3。
该第三补偿晶体管B3的栅极可以与复位信号端RST耦接，该第三补偿晶体管B3的第一极可以与第二连接节点P2耦接，该第三补偿晶体管B3的第二极可以与第二控制节点N2耦接。
可选的，该发光控制电路20还可以响应于复位信号，向发光元件L1输出 第二电源信号。继续参考图3，该发光控制电路20可以包括：第一复位子电路201、第一数据写入子电路202、第一发光控制子电路203和开关子电路204。
其中，该第一复位子电路201可以分别与复位信号端RST、第二电源端Vint、第一连接节点P1、第一控制节点N1和发光元件L1耦接。该第一复位子电路201可以响应于复位信号向第一连接节点P1、第一控制节点N1和发光元件L1输出第二电源信号。
例如，该第一复位子电路201可以在复位信号的电位为第一电位时，向第一连接节点P1、第一控制节点N1和发光元件L1输出处于第二电位的第二电源信号，从而实现对第一连接节点P1、第一控制节点N1和发光元件L1的复位。
通过设置第一复位子电路201先对第一连接节点P1、第一控制节点N1和发光元件L1进行复位，可以使得发光控制电路20和补偿电路30包括的各电路均能够从相同的电位开始工作，保证了像素电路的工作可靠性。
该第一数据写入子电路202可以分别与栅极信号端G1、第二数据信号端DT和第一控制节点N1耦接。该第一数据写入子电路202可以响应于栅极驱动信号向第一控制节点N1输出第二数据信号。
例如，该第一数据写入子电路202可以在栅极驱动信号的电位为第一电位时，向第一控制节点N1输出第二数据信号。
该第一发光控制子电路203可以分别与发光控制信号端EM、第二连接节点P2和发光元件L1耦接。该第一发光控制子电路203可以响应于发光控制信号控制第二连接节点P2和发光元件L1的通断。
例如，该第一发光控制子电路203可以在发光控制信号的电位为第一电位时，控制第二连接节点P2和发光元件L1导通。
该开关子电路204可以分别与第二控制节点N2、第一连接节点P1和第二连接节点P2耦接。该开关子电路204可以响应于第二控制节点N2的电位控制第一连接节点P1和第二连接节点P2的通断。
例如，该开关子电路204可以在第二控制节点N2的电位为第一电位时，控制第一连接节点P1和第二连接节点P2导通。
继续参考图4，该第一复位子电路201可以包括：第一复位晶体管F1、第二复位晶体管F2和第三复位晶体管F3。
该第一复位晶体管F1、第二复位晶体管F2和第三复位晶体管F3的栅极可 以均与复位信号端RST耦接。
该第一复位晶体管F1、第二复位晶体管F2和第三复位晶体管F3的第一极可以均与第二电源端Vint耦接。
该第一复位晶体管F1的第二极可以与第一连接节点P1耦接，第二复位晶体管F2的第二极可以与第一控制节点N1耦接，第三复位晶体管F3的第二极可以与发光元件L1耦接。
可选的，继续参考图4，该第一数据写入子电路202可以包括：第一数据写入晶体管D1。
该第一数据写入晶体管D1的栅极可以与栅极信号端G1耦接，该第一数据写入晶体管D1的第一极可以与第二数据信号端DT耦接，该第一数据写入晶体管D1的第二极可以与第一控制节点N1耦接。
可选的，继续参考图4，该第一发光控制子电路203可以包括：第一发光控制晶体管M1。
该第一发光控制晶体管M1的栅极可以与发光控制信号端EM耦接，第一发光控制晶体管M1的第一极可以与第二连接节点P2耦接，第一发光控制晶体管M1的第二极可以与发光元件L1耦接。
可选的，继续参考图4，该开关子电路204可以包括：开关晶体管K1。
该开关晶体管K1的栅极可以与第二控制节点N2耦接，该开关晶体管K1的第一极可以与第一连接节点P1耦接，该开关晶体管K1的第二极可以与第二连接节点P2耦接。
图5是本公开实施例提供的再一种像素电路的结构示意图。如图5所示，该像素电路还可以包括：串联在驱动电路10和第一连接节点P1之间的开关控制电路40。
该开关控制电路40可以分别与发光控制信号端EM、驱动电路10和第一连接节点P1耦接。该开关控制电路40可以响应于发光控制信号控制驱动电路10和第一连接节点P1的通断。
例如，该开关控制电路40可以在发光控制信号的电位为第一电位时，控制驱动电路10和第一连接节点P1导通，从而使得驱动电路10将其生成的驱动电流通过该开关控制电路40输出至第一连接节点P1。
通过设置开关控制电路40，可以避免驱动电流因除发光控制信号端EM之 外的任一信号端提供的信号不稳定时，误输出至发光元件L1。即可以保证仅在发光控制信号的电位为有效电位时，才向发光元件L1输出驱动电流。进一步提高了像素电路驱动发光元件L1发光的可靠性。
图6是本公开实施例提供的再一种像素电路的结构示意图。如图6所示，该开关控制电路40可以包括：开关控制晶体管Q1。
该开关控制晶体管Q1的栅极可以与发光控制信号端EM耦接，该开关控制晶体管Q1的第一极可以与驱动电路10耦接，该开关控制晶体管Q1的第二极可以与第一连接节点P1耦接。
图7是本公开实施例提供的再一种像素电路的结构示意图。如图7所示，该驱动电路10可以包括：第二数据写入子电路101、第二复位子电路102、第二发光控制子电路103、存储子电路104、第三补偿子电路105和驱动子电路106。
该第二数据写入子电路101可以分别与栅极信号端G1、第一数据信号端DI和第三连接节点P3耦接。该第二数据写入子电路101可以响应于栅极驱动信号向第三连接节点P3输出第一数据信号。
例如，该第二数据写入子电路101可以在栅极驱动信号的电位为第一电位时，向第三连接节点P3输出第一数据信号。
该第二复位子电路102可以分别与复位信号端RST、第二电源端Vint和第三控制节点N3耦接。该第二复位子电路102可以响应于复位信号向第三控制节点N3输出第二电源信号。
例如，该第二复位子电路102可以在复位信号的电位为第一电位时，向第三控制节点N3输出处于第二电位的第二电源信号，从而实现对第三控制节点N3的复位。
该第二发光控制子电路103可以分别与发光控制信号端EM、第一电源端VDD和第三连接节点P3耦接。该第二发光控制子电路103可以响应于发光控制信号向第三连接节点P3输出第一电源信号。
例如，该第二发光控制子电路103可以在发光控制信号的电位为第一电位时，向第三连接节点P3输出处于第一电位的第一电源信号，实现对第三连接节点P3的充电。
该存储子电路104可以分别与第三控制节点N3和第一电源端VDD耦接。该存储子电路104可以控制第三控制节点N3的电位。
例如，该存储子电路104可以用于存储输出至第三控制节点N3的电位。
该第三补偿子电路105可以分别与栅极信号端G1、第一连接节点P1和第一控制节点N1耦接。该第三补偿子电路105可以响应于栅极驱动信号根据第一连接节点P1的电位调整第三控制节点N3的电位。
例如，该第三补偿子电路105可以在栅极驱动信号的电位为第一电位时，根据第一连接节点P1的电位调整第三控制节点N3的电位。
需要说明的是，参考图7，若该像素电路还包括串联在驱动电路10和第一连接节点P1之间的开关控制电路40，驱动电路10与开关控制电路40的连接点可以记为第四连接节点P4。则相应的，参考图7，该第三补偿子电路105是与第四连接节点P4连接，并基于第四连接节点P4的电位调整第三控制节点N3的电位。且，该开关控制电路40也是用于响应于发光控制信号，控制第四连接节点P4和第一连接节点P1的通断。
该驱动子电路106可以分别与第三控制节点N3、第三连接节点P3和第一连接节点P1耦接。该驱动子电路106可以响应于第三控制节点N3的电位和第三连接节点P3的电位，向第一连接节点P1输出驱动电流。
例如，该驱动子电路106可以在第三控制节点N3的电位为第一电位时，基于第三控制节点N3的电位和第三连接节点P3的电位向第一连接节点P1输出驱动电流。同理，若参考图7，像素电路还包括开关控制电路40，则该驱动子电路106即是与第四连接节点P4连接。
图8是本公开实施例提供的再一种像素电路的结构示意图。如图8所示，该第二数据写入子电路101可以包括：第二数据写入晶体管D2。该第二复位子电路102可以包括：第四复位晶体管F4。该第二发光控制子电路103可以包括：第二发光控制晶体管M2。该存储子电路104可以包括：存储电容C2。该第三补偿子电路105可以包括：第四补偿晶体管B4。该驱动子电路106可以包括：驱动晶体管T1。
第二数据写入晶体管D2的栅极可以与栅极信号端G1耦接，第二数据写入晶体管D2的第一极可以与第一数据信号端DI耦接，第二数据写入晶体管D2的第二极可以与第三连接节点P3耦接。
第四复位晶体管F4的栅极可以与复位信号端RST耦接，第四复位晶体管F4的第一极可以与第二电源端Vint耦接，第四复位晶体管F4的第二极可以与 第三控制节点N3耦接。
第二发光控制晶体管M2的栅极可以与发光控制信号端EM耦接，第二发光控制晶体管M2的第一极可以与第一电源端VDD耦接，第二发光控制晶体管M2的第二极可以与第三连接节点P3耦接。
存储电容C2的一端可以与第三控制节点N3耦接，存储电容C2的另一端可以与第一电源端VDD耦接。
第四补偿晶体管B4的栅极可以与栅极信号端G1耦接，第四补偿晶体管B4的第一极可以与第一连接节点P1耦接，第四补偿晶体管B4的第二极可以与第三控制节点N3耦接。
同上述针对第三补偿子电路105的描述，若包括开关控制晶体管Q1，则参考图8，第四补偿晶体管B4的第一极是与第四连接节点P4耦接。
驱动晶体管T1的栅极可以与第三控制节点N3耦接，驱动晶体管T1的第一级可以与第三连接节点P3耦接，驱动晶体管T1的第二极可以与第一连接节点P1耦接。
同上述针对驱动子电路106的描述，若包括开关控制晶体管Q1，则参考图8，驱动晶体管T1的第二极是与第四连接节点P4耦接。
需要说明的是，本公开实施例记载的耦接可以包括：两端之间电连接或者两端之间直接连接(如两端之间通过信号线建立连接)。且，在上述实施例中，均是以各个晶体管为P型晶体管，且第一电位为相对于第二电位低电位为例进行的说明。当然，该各个晶体管还可以采用N型晶体管，当该各个晶体管采用N型晶体管时，该第一电位相对于该第二电位可以为高电位。
还需要说明的是，在本公开实施例中，该驱动电路10除了可以为图8所示的6T1C(即六个晶体管和一个电容器)的结构之外，还可以为包括其他数量的晶体管的结构，如2T1C结构或4T1C结构，本公开实施例对此不做限定。
综上所述，本公开实施例提供了一种像素电路，该像素电路包括补偿电路。由于该补偿电路可以根据第一控制节点的电位调整第二控制节点(即控制第一连接节点和第二连接节点通断的晶体管的栅极)的电位，且可以根据第二连接节点(即控制第一连接节点和第二连接节点通断的晶体管的第二极)的电位调整第二控制节点的电位。因此在对像素电路进行驱动时，可以通过控制各控制信号的电位，使得最终输出至第二控制节点的电位受该晶体管的阈值电压影响 较小，即降低了阈值电压漂移对显示均一性造成的影响，本公开实施例提供的显示装置显示效果较好。
图9是本公开实施例提供的一种像素电路的驱动方法流程图，该方法可以应用于如图2至图8任一所示的像素电路中。如图9所示，该方法可以包括：
步骤901、复位阶段，复位信号端提供的复位信号的电位为第一电位，发光控制电路响应于复位信号向第一连接节点和第一控制节点输出来自第二电源端的第二电源信号，补偿电路根据第一控制节点的电位调整第二控制节点的电位，发光控制电路还响应于第二控制节点的电位控制第一连接节点和第二连接节点导通，补偿电路还响应于复位信号根据第二连接节点的电位调整第二控制节点的电位。
可选的，该第二电源信号的电位可以为第二电位，且该第二电位相对于第一电位可以为高电位。
步骤902、数据写入阶段，栅极信号端提供的栅极驱动信号的电位为第一电位，发光控制电路响应于栅极驱动信号向第一控制节点输出来自第二数据信号端的第二数据信号，补偿电路根据第一控制节点的电位调整第二控制节点的电位。
步骤903、发光控制阶段，驱动电路响应于来自第一电源端的第一电源信号、栅极驱动信号和来自第一数据信号端的第一数据信号，向第一连接节点输出驱动电流，发光控制信号端提供的发光控制信号的电位为第一电位，补偿电路响应于发光控制信号根据第一控制节点的电位和来自第三电源端的第三电源信号调整第二控制节点的电位，发光控制电路响应于第二控制节点的电位控制第一连接节点和第二连接节点导通，以及响应于发光控制信号控制第二连接节点和发光元件导通。
可选的，该第三电源信号的电位可以为第三电位，且该第三电位相对于第二电位可以为低电位。
综上所述，本公开实施例提供了一种像素电路的驱动方法。由于该方法中，补偿电路可以根据第一控制节点的电位调整第二控制节点(即控制第一连接节点和第二连接节点通断的晶体管的栅极)的电位，且可以根据第二连接节点(即控制第一连接节点和第二连接节点通断的晶体管的第二极)的电位调整第二控 制节点的电位。因此在对像素电路进行驱动时，可以通过控制各控制信号的电位，使得最终输出至第二控制节点的电位受该晶体管的阈值电压影响较小，即降低了阈值电压漂移对显示均一性造成的影响，本公开实施例提供的显示装置显示效果较好。
以图8所示的像素电路01，发光控制电路20和补偿电路30组成的电路为时长控制电路100，且以像素电路包括的各晶体管均为P型晶体管，第一电位(即有效电位)相对于第二电位(即无效电位)为低电位，第三电位相对于第一电位为低电位为例，详细介绍本公开实施例提供的像素电路的驱动原理。
图10是本公开实施例提供的一种像素电路中各信号端的时序图。如图10所示，在复位阶段t1中，复位信号端RST提供的复位信号的电位为第一电位，第一复位晶体管F1、第二复位晶体管F2、第三复位晶体管F3、第四复位晶体管F4和第三补偿晶体管B3均开启。第二电源端Vint可以通过第一复位晶体管F1向第一连接节点P1输出处于第二电位的第二电源信号，从而实现对第一连接节点P1的复位。第二电源端Vint可以通过第二复位晶体管F2向第一控制节点N1输出处于第二电位的第二电源信号，从而实现对第一控制节点N1的复位。第二电源端Vint可以通过第三复位晶体管F3向发光元件L1输出处于第二电位的第二电源信号，从而实现对发光元件L1的复位。且第二电源端Vint可以通过第四复位晶体管F4向第三控制节点N3输出处于第二电位的第二电源信号，从而实现对第三控制节点N3的复位。存储电容C2可以存储第三控制节点N3的电位。
另外，因补偿电容C1的耦合作用，第二控制节点N2的电位也变为第二电位，相应的，开关晶体管K1开启，第一连接节点P1和第二连接节点P2导通。此时，第三补偿晶体管B3可以根据第二连接节点P2的电位调整第二控制节点N2的电位，从而将第二电源信号和开关晶体管K1的阈值电压写入至第二控制节点N2。除此之外，参考图10，在该复位阶段t1，栅极信号端G1提供的栅极驱动信号的电位以及发光控制信号端EM提供的发光控制信号的电位均为第二电位，除上述开启的晶体管外的其他晶体管均关断。该像素电路在复位阶段t1的等效电路图可以参考图11(图中虚线是指未连通)。
示例的，假设第二电源信号的电位为Vint0，开关晶体管K1的阈值电压为Vth1。则参考下述表1，在该复位阶段t1中，第一控制节点N1的电位即为：Vint0； 第二控制节点N2的电位即为：Vint0+Vth1；第三控制节点N3的电位即为：Vint0。
表1
  复位阶段t1 数据写入阶段t2 发光阶段t3
N1 Vint0 VdataT 0
N2 Vint0+Vth1 VdataT+Vth1 (VdataT+Vth1)*e (-t/r1*c1)
N3 Vint0 VdataI+Vth2 VdataI+Vth2
继续参考图10，在数据写入阶段t2中，栅极驱动信号端G1提供的栅极信号的电位为第一电位，第一数据信号端DI提供第一数据信号，第二数据信号端DT提供第二数据信号(图10未示出第一数据信号和第二数据信号)。第一数据写入晶体管D1、第二数据写入晶体管D2和第四补偿晶体管B4均开启。第一数据信号端DI可以通过第二数据写入晶体管D2向第三连接节点P3输出第一数据信号，实现对第三连接节点P3的充电。第二数据信号端DT可以通过第一数据写入晶体管D1向第一控制节点N1输出第二数据信号，实现对第一控制节点N1的充电。另外，因补偿电容C1的耦合作用，第二控制节点N2的电位变为第二数据信号与开关晶体管K1的阈值电压之和。
由于在复位阶段t1，第三控制节点N3被写入第二电位的第二电源信号，且存储电容C2存储了该第三控制节点N3的电位，因此在该数据写入阶段t2，驱动晶体管T1可以开启。此时，第三连接节点P3的电位通过该驱动晶体管T1输出至第四连接节点P4，第四补偿晶体管B4根据该第四连接节点P4的电位调整第三控制节点N3的电位。从而将第一数据信号和驱动晶体管T1的阈值电压写入至第三控制节点N3，存储电容C2继续存储该第三控制节点N3的电位。
除此之外，参考图10，在该数据写入阶段t2，复位信号端RST提供的复位信号的电位以及发光控制信号端EM提供的发光控制信号的电位均为第二电位，除上述数据写入阶段t2中开启的晶体管外的其他晶体管均关断。该像素电路在数据写入阶段t2的等效电路图可以参考图12(图中虚线是指未连通)。
示例的，假设第一数据信号的电位为VdataI，第二数据信号的电位为VdataT，驱动晶体管T1的阈值电压为Vth2，则参考上述表1，在该数据写入阶段t2中，第一控制节点N1的电位即变为：VdataT；第二控制节点N2的电位即为：VdataT+Vth1；第三控制节点N3的电位即为：VdataI+Vth2。
继续参考图10，在发光阶段t3中，发光控制信号端EM提供的发光控制信 号的电位为第一电位，第一发光控制晶体管M1、第二发光控制晶体管M2、第一补偿晶体管B1、第二补偿晶体管B2和开关控制晶体管Q1均开启。另外，因存储电容C2的存储作用，在该发光阶段t3，第三控制节点N3的电位为第一数据信号和驱动晶体管T1的阈值电压之和，驱动晶体管T1开启。第一电源端VDD通过第二发光控制晶体管M3向第三连接节点P3输出处于第一电位的第一电源信号，相应的，驱动晶体管T1基于第一电源信号和第三控制节点N3的电位向第四连接节点P4输出驱动电流。第四连接节点P4的电位可以通过该开关控制晶体管Q1继续输出至第一连接节点P1。
另外，在该发光阶段t3，第二连接节点P2和发光元件L1导通。第三电源端VSS可以通过第一补偿晶体管B1、第二补偿晶体管B2、补偿电阻R1和补偿电容C1组成的RC放电回路，向第一控制节点N1输出第三电位的第三电源信号，拉低第一控制节点N1的电位。假设第三电源端VSS为地端，则即将第一控制节点N1接地。在补偿电容C1的耦合作用下，第二控制节点N2的电位开始降低，直至降低至使得开关晶体管K1导通为止。在开关晶体管K1导通时，即可以控制第一连接节点P1和第二连接节点P2导通，驱动电流可以进一步通过开关晶体管K1输出至第二连接节点P2，并再通过第一发光控制晶体管M1输出至发光元件L1，从而实现驱动发光元件L1发光。此阶段一直持续至发光控制信号端EM提供的发光控制信号的电位跳变为第一电位为止。
除此之外，参考图10，在该发光阶段t3，栅极信号端G1提供的栅极驱动信号的电位以及发光控制信号端EM提供的发光控制信号的电位均为第二电位，除上述发光阶段t3中开启的晶体管外的其他晶体管均关断。该像素电路在发光阶段t3的等效电路图可以参考图13。
示例的，假设第一电源信号的电位为VDD1，第三电源信号的电位为0，第一数据信号的电位为VdataI，第二数据信号的电位为VdataT，开关晶体管K1的阈值电压为Vth1，驱动晶体管T1的阈值电压为Vth2，补偿电阻R1的阻值为r1，补偿电容C1的容值为c1。则参考上述表1，在该发光阶段t1，第一控制节点N1的电位即变为：0；第二控制节点N2的电位即变为：(VdataT+Vth1)*e (-t/r1*c1)；第三控制节点N3的电位为：VdataI+Vth2。
结合各节点电位，对驱动晶体管T1的阈值电压Vth1补偿原理介绍如下：
首先，若将驱动晶体管T1的栅极(如第三控制节点N3)的电位记为Vg1， 将驱动晶体管T1的源极(如第三连接节点P3)，且将驱动晶体管T1的栅源电压记为Vgs1，则本公开实施例提供的Vgs1可以满足：
Vgs1＝Vg1-Vs1＝VDD-(VdataI+Vth2)    公式(1)；
由于驱动晶体管T1产生的驱动电流I led满足：
I led＝k*(Vgs1-Vth2) 2    公式(2)；
将公式(1)计算得出的Vgs1代入公式(2)即可以得出本公开实施例记载的驱动晶体管T1最终输出的驱动电流I led满足：
I led＝k*(Vgs1-Vth2) 2＝k*(VDD1-VdataI) 2    公式(3)；
其中，k为驱动晶体管T1自身特性，由驱动晶体管T1的载流子迁移率、栅极绝缘层的电容以及的宽长比决定。从上述公式(3)可以看出，在发光元件L1正常工作时，用于驱动发光元件L1的驱动电流I led的大小只与第一电源端VDD提供的第一电源信号，以及第一数据信号端DI提供的第一数据信号的有关，而与驱动晶体管T1的阈值电压无关。因此输出至发光元件L1的驱动电流不会受驱动晶体管T1阈值电压漂移的影响，有效保证了显示均一性。
需要说明的是，若发光元件L1为Micro LED，由于在低电流密度下Micro LED的发光效率变化较为明显，因此可以通过灵活设置第一数据信号端DI提供的第一数据信号的电位，即灵活设置VdataI，使得Micro LED能够工作在高电流密度下，即发光效率稳定区域，保证显示稳定性。
结合各节点电位，对开关晶体管K1的阈值电压Vth2补偿原理介绍如下：
在本公开实施例中，开关晶体管K1导通条件为栅源电压差的绝对值大于等于阈值电压的绝对值，假设开关晶体管K1的栅极电位记为Vg2，源极电位记为Vs2，栅源电压差记为Vgs2，则导通条件即为|Vgs2|≥|Vth1|。在RC放电回路的作用下，Vgs2可以满足：
Vgs2＝Vg2-Vs2＝(VdataT+Vth1)e (-t/r1*c1)-Vs2    公式(4)；
其中t是指放电时间。将上述公式(4)与|Vgs1|≥|Vth1|结合，即可以得出：
Vs2-(VdataT+Vth1)e (-t/r1*c1)+Vth1≥0    公式(5)；整理得出本公开实施例记载的第二控制节点N2的电位满足下述条件时，开关晶体管K1开启：
Vs2-VdataT*e (-t/r1*c1)+(1-e (-t/r1*c1))*Vth1≥0    公式(6)。
根据上述公式(6)可以看出，对开关晶体管K1的阈值电压Vth1补偿后，系数值变为：1-e (-t/r1*c1)；若未补偿该开关晶体管K1的阈值电压，系数值为e (-t/r1*c1)。
图14示出了补偿前的系数示意图；图15示出了补偿后的系数示意图。其横轴均表示时间，纵轴均表示得出的系数值。对比图14和图15可以看出，对开关晶体管K1的阈值电压补偿前系数值约为1，补偿后系数值约为0.001。相应的，即有效降低了开关晶体管K1的阈值电压漂移对发光元件L1发光时长造成的影响。通过对开关晶体管K1的阈值电压，以及对驱动晶体管T1的阈值电压进行补偿，有效降低了阈值电压漂移对显示均一性造成的影响，大大减轻了显示装置的不均匀(mura)现象，提高了显示装置的显示效果。
下述实施例对第二数据信号对发光时长的影响，即控制发光元件L1发光时长的原理进行介绍：图16示出了发光时长和第二数据信号端DT提供的第二数据信号的电位的关系。其横轴可以是指时间t00，纵轴可以是指电位(单位：伏特V)。参考图16可以看出，第二数据信号的电位越大(如VdataT1)，第二控制节点N2的电位降至能够使得开关晶体管K1开启的电位V1所需的时间越长；第二数据信号的电位越大(如VdataT2)，第二控制节点N2的电位降至能够使得开关晶体管K1开启的电位V1所需的时间越短。
相应的，图16还示出了发光元件L1对应的发光时长时序。较大电位的第二数据信号VdataT1对应的发光时长(emission time1)t01，小于较小电位的第二数据信号VdataT2对应的发光时长(emission time2)t02。由于每帧显示阶段内，发光元件L1的发光亮度和发光时长呈线性关系，因此发光元件L1在不同的发光时长下对应的发光亮度也不同。即通过对发光时长的控制，也灵活的实现了对灰阶的调整。
例如，图17还示出了不同第二数据信号的电位和发光时长的仿真结果，其横轴是指时间t00(单位毫秒：ms)，纵轴是指电位(单位：V)。假设驱动开关晶体管K1开启的第二控制节点N2的电位V N2约为1V，参考图17可以看出从不同大小的第二数据信号降至1V左右所需时长不同。如从2V降至1V左右所需时长t00为798.28微秒(μs)；从3V降至1V左右所需时长t00为1.2082ms；从4V降至1V左右所需时长t00为1.4953ms；从5V降至1V左右所需时长t00为1.7156ms。降至1V左右所需时长越长，发光元件L1的发光时长相应的越短。
可选的，第二数据信号的电位VdataT和第二控制节点N2的电位V N2满足：
V N2＝(VdataT-Vint0)*e (-t/r1*c1)    公式(7)；
根据公式(7)可以推导出发光元件L1的发光时长t00可以满足：
t00＝r1*c1*ln[(VdataT-Vint0)/V N2]    公式(8)。
通过基于驱动电流和发光时长的双重控制，可以有效确保显示均一性。
综上所述，本公开实施例提供了一种像素电路的驱动方法。由于该方法中，补偿电路可以根据第一控制节点的电位调整第二控制节点(即控制第一连接节点和第二连接节点通断的晶体管的栅极)的电位，且可以根据第二连接节点(即控制第一连接节点和第二连接节点通断的晶体管的第二极)的电位调整第二控制节点的电位。因此在对像素电路进行驱动时，可以通过控制各控制信号的电位，使得最终输出至第二控制节点的电位受该晶体管的阈值电压影响较小，即降低了阈值电压漂移对显示均一性造成的影响，本公开实施例提供的显示装置显示效果较好。
可选的，图18是本公开实施例提供的一种显示基板的结构示意图。如图18所示，该显示基板001可以包括：多个像素单元00。多个像素单元00中，每个像素单元00可以包括发光元件L1，至少一个像素单元01可以包括如图2至图8任一所示的像素电路01。例如，图18示出的显示基板001包括的每个像素单元00均包括如图2至图8任一所示的像素电路01。
可选的，该发光元件可以包括：微型发光二极管Micro LED。
图19是本公开实施例提供的一种显示装置的结构示意图。如图19所示，该显示装置可以包括：信号驱动电路02，以及如图18所示的显示基板001。
其中，该信号驱动电路02可以与显示基板001包括的像素电路01中的各信号端耦接，信号驱动电路02可以用于为各信号端提供信号。
例如，该信号驱动电路02可以包括栅极驱动电路和源极驱动电路，栅极驱动电路可以与像素电路01中的栅极信号端G1连接，为栅极信号端G1提供栅极信号。源极驱动电路可以与像素电路01中的第一数据信号端DI和第二数据信号端DT连接，为第一数据信号端DI和第二数据信号端DT提供数据信号。
需要说明的是，栅极驱动电路可以通过栅线与栅极信号端G1连接，源极驱动电路可以通过数据信号线与数据信号端DI和DT连接。且，位于同一行的像素电路包括的栅极信号端G1可以与同一条栅线连接，位于同一列的像素电路包括的第一数据信号端DI可以与同一条第一数据线连接，位于同一列的像素电路包括的第二数据信号端DT可以与同一条第二数据线连接。
在正常工作时，栅极驱动电路可以通过各条栅线依次向各行像素电路连接的栅极信号端G1输出处于第一电位的栅极驱动信号。另外，源极驱动电路在不同时刻，向同一条第一数据线输出的第一数据信号的电位可能不同，即源极驱动电路通过同一条第一数据线，向位于同一列且不同行的各个像素电路包括的各个第一数据信号端DI输出的第一数据信号的电位可能不同；第二数据信号端DT同理，在此不再赘述。
例如，以位于第一行第一列和第二行第一列的两个像素电路，且该两个像素电路的第一数据信号端DI连接的同一条第一数据线称为第一条数据线为例。假设在驱动第一行像素电路时的数据写入阶段，源极驱动电路通过第一条数据线向位于第一行第一列的像素电路提供的第一数据信号的电位为VdataI1。在驱动第二行像素电路时的数据写入阶段，源极驱动电路通过该第一条数据线向位于第二行第一列的像素电路提供的第一数据信号的电位为VdataI2。则VdataI1和VdataI2可能相同，也可能不同。
可选的，该显示装置可以为：Micro LED显示装置、液晶面板、电子纸、OLED面板、AMOLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框等任何具有显示功能的产品或部件。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的像素电路、显示基板和显示装置的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (18)

  1. 一种像素电路，其中，所述像素电路包括：驱动电路、发光控制电路和补偿电路；
    所述驱动电路分别与第一电源端、栅极信号端、第一数据信号端和第一连接节点耦接，所述驱动电路用于响应于来自所述第一电源端的第一电源信号，来自所述栅极信号端的栅极驱动信号以及来自所述第一数据信号端的第一数据信号，向所述第一连接节点输出驱动电流；
    所述发光控制电路分别与所述第一连接节点、所述栅极信号端、复位信号端、发光控制信号端、第二电源端、第二数据信号端、第一控制节点、第二控制节点、第二连接节点和发光元件耦接，所述发光控制电路用于响应于来自所述复位信号端的复位信号向所述第一连接节点和所述第一控制节点输出来自所述第二电源端的第二电源信号，用于响应于所述栅极驱动信号向所述第一控制节点输出来自所述第二数据信号端的第二数据信号，用于响应于来自所述发光控制信号端的发光控制信号控制所述第二连接节点与所述发光元件的通断，以及用于响应于所述第二控制节点的电位控制所述第一连接节点和所述第二连接节点的通断；
    所述补偿电路分别与第三电源端、所述发光控制信号端、所述复位信号端、所述第一控制节点、所述第二控制节点和所述第二连接节点耦接，所述补偿电路用于根据所述第一控制节点的电位调整所述第二控制节点的电位，用于响应于所述复位信号根据所述第二连接节点的电位调整所述第二控制节点的电位，以及用于响应于所述发光控制信号根据所述第一控制节点的电位，以及来自所述第三电源端的第三电源信号调整所述第二控制节点的电位。
  2. 根据权利要求1所述的电路，其中，所述补偿电路包括：第一补偿子电路和第二补偿子电路；
    所述第一补偿子电路分别与所述发光控制信号端、所述第三电源端、所述第一控制节点和所述第二控制节点耦接，所述第一补偿子电路用于根据所述第一控制节点的电位调整所述第二控制节点的电位，以及用于响应于所述发光控制信号根据所述第三电源信号和所述第一控制节点的电位调整所述第二控制节 点的电位；
    所述第二补偿子电路分别与所述复位信号端、所述第二连接节点和所述第二控制节点耦接，所述第二补偿子电路用于响应于所述复位信号根据所述第二连接节点的电位调整所述第二控制节点的电位。
  3. 根据权利要求2所述的电路，其中，所述第一补偿子电路包括：第一补偿晶体管、第二补偿晶体管、补偿电容和补偿电阻；
    所述第一补偿晶体管的栅极与所述发光控制信号端耦接，所述第一补偿晶体管的第一极与所述第三电源端耦接，所述第一补偿晶体管的第二极与所述第一控制节点耦接；
    所述第二补偿晶体管的栅极与所述发光控制信号端耦接，所述第二补偿晶体管的第一极与所述补偿电阻的一端耦接，所述第二补偿晶体管的第二极与所述第二控制节点耦接；
    所述补偿电阻的另一端与所述第三电源端耦接；
    所述补偿电容的一端与所述第一控制节点耦接，所述补偿电容的另一端与所述第二控制节点耦接。
  4. 根据权利要求2所述的电路，其中，所述第二补偿子电路包括：第三补偿晶体管；
    所述第三补偿晶体管的栅极与所述复位信号端耦接，所述第三补偿晶体管的第一极与所述第二连接节点耦接，所述第三补偿晶体管的第二极与所述第二控制节点耦接。
  5. 根据权利要求1至4任一所述的电路，其中，所述发光控制电路还用于响应于所述复位信号，向所述发光元件输出所述第二电源信号；所述发光控制电路包括：第一复位子电路、第一数据写入子电路、第一发光控制子电路和开关子电路；
    所述第一复位子电路分别与所述复位信号端、所述第二电源端、所述第一连接节点、所述第一控制节点和所述发光元件耦接，所述第一复位子电路用于响应于所述复位信号向所述第一连接节点、所述第一控制节点和所述发光元件 输出所述第二电源信号；
    所述第一数据写入子电路分别与所述栅极信号端、所述第二数据信号端和所述第一控制节点耦接，所述第一数据写入子电路用于响应于所述栅极驱动信号向所述第一控制节点输出所述第二数据信号；
    所述第一发光控制子电路分别与所述发光控制信号端、所述第二连接节点和所述发光元件耦接，所述第一发光控制子电路用于响应于所述发光控制信号控制所述第二连接节点和所述发光元件的通断；
    所述开关子电路分别与所述第二控制节点、所述第一连接节点和所述第二连接节点耦接，所述开关子电路用于响应于所述第二控制节点的电位控制所述第一连接节点和所述第二连接节点的通断。
  6. 根据权利要求5所述的电路，其中，所述第一复位子电路包括：第一复位晶体管、第二复位晶体管和第三复位晶体管；
    所述第一复位晶体管、所述第二复位晶体管和所述第三复位晶体管的栅极均与所述复位信号端耦接；
    所述第一复位晶体管、所述第二复位晶体管和所述第三复位晶体管的第一极均与所述第二电源端耦接；
    所述第一复位晶体管的第二极与所述第一连接节点耦接，所述第二复位晶体管的第二极与所述第一控制节点耦接，所述第三复位晶体管的第二极与所述发光元件耦接。
  7. 根据权利要求5所述的电路，其中，所述第一数据写入子电路包括：第一数据写入晶体管；
    所述第一数据写入晶体管的栅极与所述栅极信号端耦接，所述第一数据写入晶体管的第一极与所述第二数据信号端耦接，所述第一数据写入晶体管的第二极与所述第一控制节点耦接。
  8. 根据权利要求5所述的电路，其中，所述第一发光控制子电路包括：第一发光控制晶体管；
    所述第一发光控制晶体管的栅极与所述发光控制信号端耦接，所述第一发 光控制晶体管的第一极与所述第二连接节点耦接，所述第一发光控制晶体管的第二极与所述发光元件耦接。
  9. 根据权利要求5所述的电路，其中，所述开关子电路包括：开关晶体管；
    所述开关晶体管的栅极与所述第二控制节点耦接，所述开关晶体管的第一极与所述第一连接节点耦接，所述开关晶体管的第二极与所述第二连接节点耦接。
  10. 根据权利要求1至9任一所述的电路，其中，所述像素电路还包括：串联在所述驱动电路和所述第一连接节点之间的开关控制电路；
    所述开关控制电路分别与所述发光控制信号端、所述驱动电路和所述第一连接节点耦接，所述开关控制电路用于响应于所述发光控制信号控制所述驱动电路和所述第一连接节点的通断。
  11. 根据权利要求10所述的电路，其中，所述开关控制电路包括：开关控制晶体管；
    所述开关控制晶体管的栅极与所述发光控制信号端耦接，所述开关控制晶体管的第一极与所述驱动电路耦接，所述开关控制晶体管的第二极与所述第一连接节点耦接。
  12. 根据权利要求1至11任一所述的电路，其中，所述驱动电路包括：第二数据写入子电路、第二复位子电路、第二发光控制子电路、存储子电路、第三补偿子电路和驱动子电路；
    所述第二数据写入子电路分别与所述栅极信号端、所述第一数据信号端和第三连接节点耦接，所述第二数据写入子电路用于响应于所述栅极驱动信号向所述第三连接节点输出所述第一数据信号；
    所述第二复位子电路分别与所述复位信号端、所述第二电源端和第三控制节点耦接，所述第二复位子电路用于响应于所述复位信号向所述第三控制节点输出所述第二电源信号；
    所述第二发光控制子电路分别与所述发光控制信号端、所述第一电源端和 所述第三连接节点耦接，所述第二发光控制子电路用于响应于所述发光控制信号向所述第三连接节点输出所述第一电源信号；
    所述存储子电路分别与所述第三控制节点和所述第一电源端耦接，所述存储子电路用于控制所述第三控制节点的电位；
    所述第三补偿子电路分别与所述栅极信号端、所述第一连接节点和所述第一控制节点耦接，所述第三补偿子电路用于响应于所述栅极驱动信号根据所述第一连接节点的电位调整所述第三控制节点的电位；
    所述驱动子电路分别与所述第三控制节点、所述第三连接节点和所述第一连接节点耦接，所述驱动子电路用于响应于所述第三控制节点的电位和所述第三连接节点的电位，向所述第一连接节点输出驱动电流。
  13. 根据权利要求12所述的电路，其中，所述第二数据写入子电路包括：第二数据写入晶体管；所述第二复位子电路包括：第四复位晶体管；所述第二发光控制子电路包括：第二发光控制晶体管；所述存储子电路包括：存储电容；所述第三补偿子电路包括：第四补偿晶体管；所述驱动子电路包括：驱动晶体管；
    所述第二数据写入晶体管的栅极与所述栅极信号端耦接，所述第二数据写入晶体管的第一极与所述第一数据信号端耦接，所述第二数据写入晶体管的第二极与所述第三连接节点耦接；
    所述第四复位晶体管的栅极与所述复位信号端耦接，所述第四复位晶体管的第一极与所述第二电源端耦接，所述第四复位晶体管的第二极与所述第三控制节点耦接；
    所述第二发光控制晶体管的栅极与所述发光控制信号端耦接，所述第二发光控制晶体管的第一极与所述第一电源端耦接，所述第二发光控制晶体管的第二极与所述第三连接节点耦接；
    所述存储电容的一端与所述第三控制节点耦接，所述存储电容的另一端与所述第一电源端耦接；
    所述第四补偿晶体管的栅极与所述栅极信号端耦接，所述第四补偿晶体管的第一极与所述第一连接节点耦接，所述第四补偿晶体管的第二极与所述第三控制节点耦接；
    所述驱动晶体管的栅极与所述第三控制节点耦接，所述驱动晶体管的第一级与所述第三连接节点耦接，所述驱动晶体管的第二极与所述第一连接节点耦接。
  14. 根据权利要求13所述的电路，其中，所述补偿电路包括：第一补偿晶体管、第二补偿晶体管、补偿电容、补偿电阻和第三补偿晶体管；所述发光控制电路包括：第一复位晶体管、第二复位晶体管、第三复位晶体管、第一数据写入晶体管、第一发光控制晶体管和开关晶体管；
    所述第一补偿晶体管的栅极与所述发光控制信号端耦接，所述第一补偿晶体管的第一极与所述第三电源端耦接，所述第一补偿晶体管的第二极与所述第一控制节点耦接；所述第二补偿晶体管的栅极与所述发光控制信号端耦接，所述第二补偿晶体管的第一极与所述补偿电阻的一端耦接，所述第二补偿晶体管的第二极与所述第二控制节点耦接；所述补偿电阻的另一端与所述第三电源端耦接；所述补偿电容的一端与所述第一控制节点耦接，所述补偿电容的另一端与所述第二控制节点耦接；所述第三补偿晶体管的栅极与所述复位信号端耦接，所述第三补偿晶体管的第一极与所述第二连接节点耦接，所述第三补偿晶体管的第二极与所述第二控制节点耦接；
    所述第一复位晶体管、所述第二复位晶体管和所述第三复位晶体管的栅极均与所述复位信号端耦接；所述第一复位晶体管、所述第二复位晶体管和所述第三复位晶体管的第一极均与所述第二电源端耦接；所述第一复位晶体管的第二极与所述第一连接节点耦接，所述第二复位晶体管的第二极与所述第一控制节点耦接，所述第三复位晶体管的第二极与所述发光元件耦接；所述第一数据写入晶体管的栅极与所述栅极信号端耦接，所述第一数据写入晶体管的第一极与所述第二数据信号端耦接，所述第一数据写入晶体管的第二极与所述第一控制节点耦接；所述第一发光控制晶体管的栅极与所述发光控制信号端耦接，所述第一发光控制晶体管的第一极与所述第二连接节点耦接，所述第一发光控制晶体管的第二极与所述发光元件耦接；所述开关晶体管的栅极与所述第二控制节点耦接，所述开关晶体管的第一极与所述第一连接节点耦接，所述开关晶体管的第二极与所述第二连接节点耦接；
    所述像素电路还包括：开关控制晶体管；所述开关控制晶体管的栅极与所 述发光控制信号端耦接，所述开关控制晶体管的第一极与所述驱动电路耦接，所述开关控制晶体管的第二极与所述第一连接节点耦接。
  15. 一种像素电路的驱动方法，其中，用于驱动如权利要求1至14任一所述的像素电路，所述方法包括：
    复位阶段，复位信号端提供的复位信号的电位为第一电位，发光控制电路响应于所述复位信号向第一连接节点和第一控制节点输出来自第二电源端的第二电源信号，补偿电路根据所述第一控制节点的电位调整第二控制节点的电位，所述发光控制电路还响应于所述第二控制节点的电位控制所述第一连接节点和第二连接节点导通，所述补偿电路还响应于所述复位信号根据所述第二连接节点的电位调整所述第二控制节点的电位；
    数据写入阶段，栅极信号端提供的栅极驱动信号的电位为第一电位，所述发光控制电路响应于所述栅极驱动信号向所述第一控制节点输出来自第二数据信号端的第二数据信号，所述补偿电路根据所述第一控制节点的电位调整所述第二控制节点的电位；
    发光控制阶段，驱动电路响应于来自第一电源端的第一电源信号、所述栅极驱动信号和来自第一数据信号端的第一数据信号，向所述第一连接节点输出驱动电流，发光控制信号端提供的发光控制信号的电位为第一电位，所述补偿电路响应于所述发光控制信号根据所述第一控制节点的电位和来自第三电源端的第三电源信号调整所述第二控制节点的电位，所述发光控制电路响应于所述第二控制节点的电位控制所述第一连接节点和所述第二连接节点导通，以及响应于所述发光控制信号控制所述第二连接节点和所述发光元件导通。
  16. 一种显示基板，其中，所述显示基板包括：多个像素单元，所述多个像素单元中，至少一个所述像素单元包括：发光元件，以及与所述发光元件耦接的如权利要求1至14任一所述的像素电路。
  17. 根据权利要求16所述的显示基板，其中，所述发光元件包括：微型发光二极管。
  18. 一种显示装置，其中，所述显示装置包括：信号驱动电路，以及如权利要求16或17所述的显示基板；
    所述信号驱动电路与所述显示基板包括的像素电路中的各信号端耦接，所述信号驱动电路用于为所述各信号端提供信号。
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