WO2019242557A1 - 像素电路及显示装置 - Google Patents

像素电路及显示装置 Download PDF

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Publication number
WO2019242557A1
WO2019242557A1 PCT/CN2019/091075 CN2019091075W WO2019242557A1 WO 2019242557 A1 WO2019242557 A1 WO 2019242557A1 CN 2019091075 W CN2019091075 W CN 2019091075W WO 2019242557 A1 WO2019242557 A1 WO 2019242557A1
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Prior art keywords
transistor
terminal
pole
electrode
voltage
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PCT/CN2019/091075
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English (en)
French (fr)
Inventor
王骏
黄中浩
赵永亮
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京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Priority to US16/622,547 priority Critical patent/US11373596B2/en
Publication of WO2019242557A1 publication Critical patent/WO2019242557A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present disclosure belongs to the field of display technology, and particularly relates to a pixel circuit and a display device.
  • OLEDs Organic Light Emitting Diodes
  • An OLED display panel usually includes a plurality of pixels arranged in a matrix. Driving and controlling each pixel for display depends on a pixel circuit inside the pixel.
  • the pixel circuit mainly includes a switching transistor, a capacitor, and a light emitting device OLED.
  • An embodiment of the present disclosure provides a pixel circuit including a switching transistor, a driving transistor, a storage capacitor, a threshold voltage extraction unit, a light emitting control unit, a light emitting device, and a compensation unit.
  • the light emitting device has a second connection to the driving transistor.
  • a first pole of the pole and a second pole receiving the first power voltage a first end of the storage capacitor is connected to a control pole of the driving transistor, a second end of the storage capacitor is connected to a reference voltage terminal, and the switch
  • the transistor transmits a data voltage signal to a first electrode of the driving transistor under the control of a scanning signal
  • the threshold voltage extraction unit is connected to a control electrode and a second electrode of the driving transistor under the control of the scanning signal.
  • the light-emitting control unit transmits a second power supply voltage to a first pole of the driving transistor under the control of a light-emitting control signal, and the compensation unit transmits a compensation voltage to a second pole of the switching transistor to Reducing the feed-through voltage of the switching transistor.
  • the compensation unit includes a compensation capacitor, a first terminal of the compensation capacitor is connected to a second pole of the switching transistor, a second terminal of the compensation capacitor is connected to a compensation voltage terminal, and the compensation voltage terminal The compensation voltage is provided.
  • the pixel circuit further includes a reset unit, and the reset unit transmits an initialization signal to a control electrode of the driving transistor under the control of a reset control signal.
  • the reset unit includes a reset transistor, a first pole of the reset transistor is connected to an initialization signal terminal, a second pole of the reset transistor is connected to a control electrode of the driving transistor, and the control of the reset transistor is A pole is connected to a reset signal terminal, the initialization signal terminal provides the initialization signal, and the reset signal terminal provides a reset control signal.
  • a first terminal of the compensation capacitor is connected to a second electrode of the switching transistor and a first electrode of the driving transistor, and a second terminal of the compensation capacitor is connected to the initialization signal terminal.
  • the initialization signal terminal is shared with the compensation voltage terminal
  • a first terminal of the compensation capacitor is connected to a second electrode of the switching transistor and a first electrode of the driving transistor, and a second terminal of the compensation capacitor is connected to the reset signal terminal.
  • the reset signal terminal is shared with the compensation voltage terminal.
  • the light emission control unit includes a first light emission control transistor, a first pole of the first light emission control transistor is connected to a second power supply voltage terminal, and a second pole of the first light emission control transistor is connected to the The second pole of the switching transistor, the first pole of the driving transistor, and the first end of the compensation capacitor.
  • the control pole of the first light-emitting control transistor is connected to a light-emitting control signal terminal, and the light-emitting control signal terminal provides light-emitting control. signal.
  • a first terminal of the compensation capacitor is connected to a second pole of the switching transistor, a second terminal of the compensation capacitor is connected to the second power voltage terminal, and the second power voltage terminal provides a first Two power supply voltages are shared with the compensation voltage terminal.
  • the light emission control unit further includes a second light emission control transistor, wherein a first pole of the second light emission control transistor is connected to the threshold voltage extraction unit and a second pole of the driving transistor, so The second pole of the second light-emitting control transistor is connected to the first pole of the light-emitting device, and the control pole of the second light-emitting control transistor is connected to the light-emitting control signal terminal.
  • the threshold voltage extraction unit includes a threshold voltage extraction transistor, a first pole of the threshold voltage extraction transistor is connected to a first terminal of the storage capacitor and a control electrode of the driving transistor, and the threshold voltage
  • the second electrode of the extraction transistor is connected to the second electrode of the driving transistor and the first electrode of the light emitting device, and the control electrode of the threshold voltage extraction transistor is connected to a scan line, and the scan line provides the scan signal.
  • a first terminal of the storage capacitor, a control electrode of the driving transistor and the threshold voltage extraction unit, a second terminal of the storage capacitor is connected to a second power supply voltage terminal, and the second power supply voltage The terminal provides a second power voltage and is shared with the reference voltage terminal.
  • a first pole of the switching transistor is connected to a data line
  • a second pole of the switching transistor is connected to a first end of the compensation unit, a first pole of the driving transistor, and the light emitting control unit.
  • the control electrode of the switching transistor is connected to a scan line, the data line provides the data voltage signal, and the scan line provides the scan signal.
  • the first pole of the driving transistor is connected to the first pole of the driving transistor and is connected to the light emitting control unit, the first terminal of the compensation unit, and the second pole of the switching transistor.
  • a second electrode of the driving transistor is connected to the threshold voltage extraction unit and the first electrode of the light emitting device, and a control electrode of the driving transistor is connected to the first terminal of the storage capacitor and the threshold voltage extraction unit.
  • An embodiment of the present disclosure also provides a display device including the pixel circuit described above.
  • FIG. 1 is a schematic structural diagram of a pixel circuit
  • FIG. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 4 is an operation timing diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. Since the source and drain of a transistor are interchangeable under certain conditions, the source of the transistor is There is no difference in the description of the connection relationship with the drain. In the embodiment of the present disclosure, in order to distinguish the source and the drain of a transistor, one of the source and the drain of the transistor is referred to as a first pole and the other is referred to as a second pole, and the gate of the transistor is referred to as The pole is called the control pole. In addition, the transistors can be divided into N-type transistors and P-type transistors according to the characteristics of the transistors.
  • the first pole of the P-type transistor may be the source of the P-type transistor
  • the second pole of the P-type transistor may be the drain of the P-type transistor
  • the gate ie, the gate of the P-type transistor
  • the technical solution for implementing the embodiments of the present disclosure by using N-type transistors can be easily conceived by those skilled in the art without paying creative labor.
  • the gate ie, the control electrode
  • the source and the drain of the N-type transistor are turned on.
  • FIG. 1 shows a schematic structural diagram of a pixel circuit.
  • the pixel circuit includes a light emitting device OLED, a light emitting control unit 1, a threshold voltage extraction unit 2, a reset unit 3, a switching transistor M2, a driving transistor M3, and a storage capacitor Cst.
  • the switching transistor M2 is turned on under the control of the scanning signal on the scanning line Scan to transmit the data voltage signal on the data line Data to the first pole of the driving transistor M3.
  • the signals are different. For example, when the switching transistor M2 is a P-type transistor, the scanning signal that controls its on is low, and the scanning signal that controls its off is high.
  • the voltage of the scanning signal of the tube M2 so that during the switching of the scanning signal between high and low, between the second pole and the control pole of the switching transistor M2 at different positions in the pixel circuit of the same row
  • the magnitude of the generated parasitic capacitance is different, that is, the feedthrough voltages generated at the second poles of the switching transistors M2 at different positions in the pixel circuits of the same row are different, resulting in uneven display of the display panel.
  • FIG. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • the pixel circuit of the embodiment of the present disclosure includes a light emitting device OLED, a light emitting control unit 1, a threshold voltage extraction unit 2, a reset unit 3, a switching transistor M2, a driving transistor M3, a storage capacitor Cst, and a compensation unit 4.
  • the light emitting device OLED has a first electrode connected to the drain of the driving transistor M3 and a second electrode receiving a first power supply voltage terminal VSS.
  • the first terminal of the storage capacitor Cst is connected to the gate of the driving transistor M3, and the second terminal of the storage capacitor Cst is connected to the reference voltage terminal Vref1.
  • the switching transistor M2 transmits the data voltage signal on the data line Data to the source of the driving transistor M3 under the control of the scanning signal on the scanning line Scan.
  • the threshold voltage extraction unit 2 is connected to the gate and the drain of the driving transistor M3 under the control of a scanning signal on the scanning line Scan.
  • the light emitting control unit 1 transmits the second power source voltage provided by the second power source voltage terminal VDD to the source of the driving transistor M3 and drives the light emitting device OLED to emit light under the control of the light emitting control signal provided by the light emitting control signal terminal EM.
  • the compensation unit 4 is configured to transmit the compensation voltage provided by the compensation voltage terminal Vref3 to the drain of the switching transistor M2 to reduce the feed-through voltage of the switching transistor M2.
  • a compensation unit 4 is added to the pixel circuit of this embodiment, and the compensation unit 4 can reduce the feed-through voltage generated by the switching transistor M2 by using a compensation voltage, so that the display of the pixel circuit of this embodiment is applied In the panel, since the feed-through voltage of the switching transistor M2 in each pixel circuit becomes smaller, the difference in the feed-through voltage of the switching transistor M2 at different positions can be greatly reduced, thereby effectively improving the display failure of the display panel. The problem of uniformity.
  • the compensation unit 4 may include a compensation capacitor Cc, a first terminal of the compensation capacitor Cc is connected to the drain of the switching transistor M2, and a second terminal of the compensation capacitor Cc is connected to the compensation voltage terminal Vref3.
  • the compensation voltage terminal Vref3 is used to provide a compensation voltage.
  • the reset unit 3 transmits the initialization signal provided by the initialization signal terminal Vref2 to the N1 node under the control of the reset control signal provided by the reset signal terminal Reset.
  • the N1 node is a connection node between the reset unit 3, the first end of the storage capacitor Cst, and the control electrode of the driving transistor M3.
  • the reset unit 3 may include a reset transistor M5.
  • the source of the reset transistor M5 is connected to the initialization signal terminal Vref2, the drain of the reset transistor M5 is connected to the N1 node, and the gate of the reset transistor M5 is connected to the reset signal terminal Reset.
  • the reset signal terminal Reset provides a reset control signal.
  • the initialization signal terminal Vref2 provides an initialization signal.
  • the reset unit 3 is not limited to include only the reset transistor M5.
  • the threshold voltage extraction unit 2 may include a threshold voltage extraction transistor M4.
  • the source of the threshold voltage extraction transistor M4 is connected to the N1 node
  • the drain of the threshold voltage extraction transistor M4 is connected to the N3 node
  • the gate of the threshold voltage extraction transistor M4 is connected to the scan line Scan.
  • the N3 node is a connection node between the drain of the driving transistor M3 and the first electrode of the light emitting device OLED.
  • the scan line Scan provides a scanning signal.
  • the light emission control unit 1 may include a first light emission control transistor M1.
  • the source of the first light emission control transistor M1 is connected to the second power supply voltage terminal VDD
  • the drain of the first light emission control transistor M1 is connected to the N2 node
  • the gate of the first light emission control transistor M1 is connected to the light emission control signal terminal EM.
  • the light emission control signal terminal EM provides a light emission control signal.
  • the light emission control unit 1 may further include a second light emission control transistor M6, a source of the second light emission control transistor M6 is connected to the N3 node, and a drain of the second light emission control transistor M6 is connected to the first electrode of the light emitting device OLED.
  • the second electrode of the light emitting device OLED is connected to the first power voltage terminal VSS.
  • the second terminal of the storage capacitor Cst can be directly connected to the second power voltage terminal VDD, and the second power voltage terminal VDD provides a second power voltage, that is, the second power voltage terminal VDD and the reference voltage terminal Vref1 can be In common, the second power supply voltage can be used as a reference voltage to reduce the setting of the signal port of the pixel circuit.
  • the source of the switching transistor M2 is connected to the data line Data
  • the drain of the switching transistor M2 is connected to the N2 node
  • the gate of the switching transistor M2 is connected to the scan line Scan.
  • the N2 node is a connection node between the first end of the compensation unit 4, the source of the driving transistor M3 and the light emitting control unit 1.
  • the data line Data provides a data voltage signal.
  • the scan line Scan provides a scanning signal.
  • the source of the driving transistor M3 is connected to the N2 node
  • the drain of the driving transistor M3 is connected to the N3 node
  • the gate of the driving transistor M3 is connected to the N1 node.
  • the N1 node is a connection node between the first end of the storage capacitor Cst and the threshold voltage extraction unit 2.
  • the N2 node is a connection node between the first end of the light emitting control unit 1 and the compensation unit 4 and the drain of the switching transistor M2.
  • the N3 node is a connection node between the threshold voltage extraction unit 2 and the first pole of the light emitting device OLED.
  • the initialization phase write a reset control signal to the reset signal terminal Reset.
  • the reset control signal is a low-level signal and the reset transistor M5 is turned on.
  • the initialization signal written by the initialization signal terminal Vref2 passes through the reset transistor M5. Reset the N1 node.
  • a scanning signal is written to the scanning line Scan.
  • the scanning signal is a low-level signal, and the switching transistor M2 and the threshold voltage extraction transistor M4 are turned on.
  • the data line Data The written data voltage signal is written to the N2 node.
  • the voltage at the N2 node is the sum of the data voltage and the feed-through voltage (V data + V feedthrough ).
  • the transistor M4 is turned on, the voltage at the N3 node is equal to the voltage at the N1 node, and the voltage at the N1 node is V data + V feedthrough -V th .
  • the T3 phase that is, the light-emitting phase
  • the light-emitting control signal is a low-level signal.
  • the first light-emitting control transistor M1 and the second light-emitting control transistor M6 are turned on.
  • the N2 node The voltage is the second power voltage provided by the second power voltage terminal VDD. Since the voltage at the N1 node is V data + V feedthrough -V th , the current that drives the light emitting device OLED to emit light is I ds , and I ds is calculated according to the following formula .
  • I ds K ⁇ (V gs -V th ) 2
  • K is 1/2 ⁇ Cox ⁇ W / L ⁇ mobility.
  • K is analyzed as a fixed value.
  • the feedthrough voltage of the switching transistor M2 in the pixel circuit shown in FIG. 1 can be calculated according to the following feedthrough voltage calculation formula.
  • Cox is the capacitance per unit area of the gate insulating layer of the switching transistor M2
  • V GH is the voltage value when the scanning signal is high level
  • V GL is the voltage value when the scanning signal is low level
  • V TH is the switching transistor
  • W is the channel width of the switching transistor M2
  • L is the channel length of the switching transistor M2
  • CgdM1 is the gate-drain parasitic capacitance of the first light-emitting control transistor M1
  • CgdM2 is the gate-drain parasitic capacitance of the switching transistor M2 Capacitance
  • C gdM6 is the gate-drain parasitic capacitance of the second light-emitting control transistor M6
  • Cst is the capacitance value of the storage capacitor Cst.
  • the feed-through voltage of the switching transistor M2 can be calculated by the following calculation formula.
  • Cc is the capacitance value of the compensation capacitor Cc.
  • the feed-through voltage of the switching transistor M2 in this embodiment is significantly reduced due to the addition of the compensation capacitor Cc. Therefore, in the display panel to which the pixel circuit of this embodiment is applied, the switching transistor M2 in each pixel circuit The feed-through voltages are all smaller, so the difference between the feed-through voltages of the switching transistors M2 at different positions can be greatly reduced, so that the problem of uneven display of the display panel can be effectively improved.
  • the pixel circuit includes a light emitting device OLED, a light emitting control unit 1, a threshold voltage extraction unit 2, a reset unit 3, a switching transistor M2, a driving transistor M3, and a memory.
  • the light emission control unit 1 includes a first light emission control transistor M1 and a second light emission control transistor M6.
  • the threshold voltage extraction unit 2 includes a threshold voltage extraction transistor M4.
  • the reset unit 3 includes a reset transistor M5.
  • the compensation unit 4 includes a compensation capacitor Cc.
  • the source of the switching transistor M2 is connected to the data line Data
  • the drain of the switching transistor M2 is connected to the N2 node
  • the gate of the switching transistor M2 is connected to the scan line Scan.
  • the source of the driving transistor M3 is connected to the N2 node
  • the drain of the driving transistor M3 is connected to the N3 node
  • the gate of the driving transistor M3 is connected to the N1 node.
  • the source of the first light emission control transistor M1 is connected to the second power voltage terminal VDD
  • the drain of the first light emission control transistor M1 is connected to the N2 node
  • the gate of the first light emission control transistor M1 is connected to the light emission control signal terminal.
  • the source of the second light emission control transistor M6 is connected to the N3 node
  • the drain of the second light emission control transistor M6 is connected to the first electrode of the light emitting device OLED
  • the gate of the second light emission control transistor M6 is connected to the light emission control signal terminal EM.
  • the second electrode of the light emitting device OLED is connected to the first power voltage terminal VSS.
  • the source of the threshold voltage extraction transistor M4 is connected to the N1 node
  • the drain of the threshold voltage extraction transistor M4 is connected to the N3 node
  • the gate of the threshold voltage extraction transistor M4 is connected to the scan line Scan.
  • the source of the reset transistor M5 is connected to the initialization signal terminal Vref2, the drain of the reset transistor M5 is connected to the N1 node, and the gate of the reset transistor M5 is connected to the reset signal terminal Reset.
  • the first terminal of the compensation capacitor Cc is connected to the N2 node, and the second terminal of the compensation capacitor Cc is connected to the second power voltage terminal VDD.
  • the compensation voltage terminal Vref3 is shared with the second power voltage terminal VDD. That is, in this embodiment, the second power supply voltage written by the second power supply voltage terminal VDD is used as the compensation voltage.
  • the initialization phase write a reset control signal to the reset signal terminal Reset.
  • the reset control signal is a low-level signal and the reset transistor M5 is turned on.
  • the initialization signal written by the initialization signal terminal Vref2 passes through the reset transistor M5. Reset the N1 node.
  • a scanning signal is written to the scanning line Scan.
  • the scanning signal is a low-level signal, and the switching transistor M2 and the threshold voltage extraction transistor M4 are turned on.
  • the data line Data The written data voltage signal is written to the N2 node.
  • the voltage at the N2 node is the sum of the data voltage and the feedthrough voltage (V data + V feedthrough ).
  • V data + V feedthrough the voltage at the N3 node is equal to the voltage at the N1 node, and the voltage at the N1 node is V data + V feedthrough -V th .
  • the T3 phase that is, the light-emitting phase
  • the light-emitting control signal is a low-level signal.
  • the first light-emitting control transistor M1 and the second light-emitting control transistor M6 are turned on.
  • the N2 node The voltage of N is the second power supply voltage VDD. Since the voltage at the N1 node is V data + V feedthrough -V th , the current that drives the light emitting device OLED to emit light is I ds , and I ds is calculated according to the following formula.
  • I ds K ⁇ (V gs -V th ) 2
  • K is 1/2 ⁇ Cox ⁇ W / L ⁇ mobility.
  • K is analyzed as a fixed value.
  • the feed-through voltage of the switching transistor M2 in the pixel circuit shown in FIG. 1 can be calculated according to the following feed-through voltage calculation formula.
  • Cox is the capacitance per unit area of the gate insulating layer of the switching transistor M2
  • V GH is the voltage value when the scanning signal is high level
  • V GL is the voltage value when the scanning signal is low level
  • V TH is the switching transistor
  • W is the channel width of the switching transistor M2
  • L is the channel length of the switching transistor M2
  • CgdM1 is the gate-drain parasitic capacitance of the first light-emitting control transistor M1
  • CgdM2 is the gate-drain parasitic capacitance of the switching transistor M2
  • the capacitance, C gdM6 is a gate-drain parasitic capacitance of the second light-emitting control transistor M6, and Cst is a storage capacitance Cst.
  • the feed-through voltage of the switching transistor M2 can be calculated by the following calculation formula.
  • Cc is the capacitance value of the compensation capacitor Cc.
  • the feed-through voltage of the switching transistor M2 in this embodiment is significantly reduced due to the addition of the compensation capacitor Cc. Therefore, in the display panel to which the pixel circuit of this embodiment is applied, the switching transistor M2 in each pixel circuit The feed-through voltage becomes smaller, so the difference in feed-through voltage of the switching transistor M2 at different positions can be greatly reduced, and the problem of uneven display of the display panel can be effectively improved.
  • An embodiment of the present disclosure also provides a pixel circuit.
  • the pixel circuit also includes a light emitting device OLED, a light emitting control unit 1, a threshold voltage extraction unit 2, a reset unit 3, a switching transistor M2, a driving transistor M3, Storage capacitor Cst and compensation unit 4.
  • the light emission control unit 1 includes a first light emission control transistor M1 and a second light emission control transistor M6.
  • the threshold voltage extraction unit 2 includes a threshold voltage extraction transistor M4.
  • the reset unit 3 includes a reset transistor M5.
  • the compensation unit 4 includes a compensation capacitor Cc.
  • the first terminal of the compensation capacitor Cc is connected to the N2 node, and the second terminal of the compensation capacitor Cc is connected to the initialization signal terminal Vref2.
  • the compensation voltage terminal Vref3 is shared with the initialization signal terminal Vref2. That is, in this embodiment, the initialization signal written by the source of the reset transistor M5 is used as the compensation voltage.
  • An embodiment of the present disclosure also provides a pixel circuit.
  • the pixel circuit also includes a light emitting device OLED, a light emitting control unit 1, a threshold voltage extraction unit 2, a reset unit 3, a switching transistor M2, a driving transistor M3, Storage capacitor Cst and compensation unit 4.
  • the light emission control unit 1 includes a first light emission control transistor M1 and a second light emission control transistor M6.
  • the threshold voltage extraction unit 2 includes a threshold voltage extraction transistor M4.
  • the reset unit 3 includes a reset transistor M5.
  • the compensation unit 4 includes a compensation capacitor Cc. In this embodiment, as shown in FIG. 7, the first terminal of the compensation capacitor Cc is connected to the N2 node, and the second terminal of the compensation capacitor Cc is connected to the gate of the reset transistor M5.
  • the compensation voltage terminal Vref3 is shared with the reset signal terminal Reset. That is, in this embodiment, the reset control signal written in the gate of the reset transistor M5 is used as the compensation voltage.
  • the first terminal of the compensation capacitor Cc included in the compensation unit 4 is connected to the N2 node (that is, the drain of the switching transistor M2), and the second terminal of the compensation capacitor Cc is simply connected to It is sufficient to provide a terminal or line of a fixed voltage in a period (including T2 and T3) when the switching transistor M2 starts to be turned on until the display of the current frame ends.
  • An embodiment of the present disclosure further provides a display device including any pixel circuit provided by the embodiments of the present disclosure.
  • the display device in this embodiment may include any product or component having a display function, such as an OLED display panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as an OLED display panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the uniformity of screen display of the display device of the embodiment is significantly improved.

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Abstract

一种像素电路及显示装置。像素电路包括开关晶体管（M2）、驱动晶体管（M3）、存储电容（Cst）、阈值电压提取单元（2）、发光控制单元（1）、发光器件（OLED）、以及补偿单元（4）。发光器件（OLED）具有连接驱动晶体管（M3）的第二极的第一极、以及接收第一电源电压的第二极。存储电容（Cst）的第一端连接驱动晶体管（M3）的控制极，存储电容（Cst）的第二端连接参考电压端（Vref1）。开关晶体管（M2）在扫描信号的控制下，将数据电压信号传输至驱动晶体管（M3）的第一极。阈值电压提取单元（2）在扫描信号的控制下，连接驱动晶体管（M3）的控制极和第二极。发光控制单元（1）在发光控制信号的控制下，将第二电源电压传输至驱动晶体管（M3）的第一极。补偿单元（4）将补偿电压传输至开关晶体管（M2）的第二极，以降低开关晶体管（M2）的馈通电压。

Description

像素电路及显示装置
相关申请的交叉引用
本申请要求于2018年6月21日提交的中国专利申请No.201810645427.5的优先权，该中国专利申请的内容通过引用的方式全部合并于此。
技术领域
本公开属于显示技术领域，具体涉及像素电路及显示装置。
背景技术
随着显示技术的发展，有机发光二极管(Organic Light Emitting Diode，OLED)因其所具有的自发光、快速响应、宽视角和可制作在柔性衬底上等特点而越来越多地被应用于高性能显示领域当中。
OLED显示面板通常包括矩阵式排布的多个像素，驱动和控制每个像素进行显示依赖于像素内部的像素电路。像素电路主要包括开关晶体管、电容和发光器件OLED。
公开内容
本公开的实施例提供一种像素电路，包括开关晶体管、驱动晶体管、存储电容、阈值电压提取单元、发光控制单元、发光器件、以及补偿单元，所述发光器件具有连接所述驱动晶体管的第二极的第一极、以及接收第一电源电压的第二极，所述存储电容的第一端连接所述驱动晶体管的控制极，所述存储电容的第二端连接参考电压端，所述开关晶体管在扫描信号的控制下，将数据电压信号传输至所述驱动晶体管的第一极，所述阈值电压提取单元在所述扫描信号的控制下，连接所述驱动晶体管的控制极和第二极，所述发光控制单元在发光控 制信号的控制下，将第二电源电压传输至所述驱动晶体管的第一极，以及所述补偿单元将补偿电压传输至所述开关晶体管的第二极，以降低所述开关晶体管的馈通电压。
在一些实施方式中，所述补偿单元包括补偿电容，所述补偿电容的第一端连接所述开关晶体管的第二极，所述补偿电容的第二端连接补偿电压端，所述补偿电压端提供所述补偿电压。
在一些实施方式中，所述像素电路还包括复位单元，所述复位单元在复位控制信号的控制下，将初始化信号传输至所述驱动晶体管的控制极。
在一些实施方式中，所述复位单元包括复位晶体管，所述复位晶体管的第一极连接初始化信号端，所述复位晶体管的第二极连接所述驱动晶体管的控制极，所述复位晶体管的控制极连接复位信号端，所述初始化信号端提供所述初始化信号，所述复位信号端提供复位控制信号。
在一些实施方式中，所述补偿电容的第一端连接所述开关晶体管的第二极和所述驱动晶体管的第一极，所述补偿电容的第二端连接所述初始化信号端，所述初始化信号端与所述补偿电压端共用
在一些实施方式中，所述补偿电容的第一端连接所述开关晶体管的第二极和所述驱动晶体管的第一极，所述补偿电容的第二端连接所述复位信号端，所述复位信号端与所述补偿电压端共用。
在一些实施方式中，所述发光控制单元包括第一发光控制晶体管，所述第一发光控制晶体管的第一极连接第二电源电压端，所述第一发光控制晶体管的第二极连接所述开关晶体管的第二极、所述驱动晶体管的第一极和所述补偿电容的第一端，所述第一发光控制晶体管的控制极连接发光控制信号端，所述发光控制信号端提供发光控制信号。
在一些实施方式中，所述补偿电容的第一端连接所述开关晶体管的第二极，所述补偿电容的第二端连接所述第二电源电压端，所述第二电源电压端提供第二电源电压、且与所述补偿电压端共用。
在一些实施方式中，所述发光控制单元还包括第二发光控制晶 体管，其中，所述第二发光控制晶体管的第一极连接所述阈值电压提取单元和所述驱动晶体管的第二极，所述第二发光控制晶体管的第二极连接所述发光器件的第一极，所述第二发光控制晶体管的控制极连接所述发光控制信号端。
在一些实施方式中，所述阈值电压提取单元包括阈值电压提取晶体管，所述阈值电压提取晶体管的第一极连接所述存储电容的第一端和所述驱动晶体管的控制极，所述阈值电压提取晶体管的第二极连接所述驱动晶体管的第二极和所述发光器件的第一极，所述阈值电压提取晶体管的控制极连接扫描线，所述扫描线提供所述扫描信号。
在一些实施方式中，所述存储电容的第一端所述驱动晶体管的控制极和所述阈值电压提取单元，所述存储电容的第二端连接第二电源电压端，所述第二电源电压端提供第二电源电压、且与所述参考电压端共用。
在一些实施方式中，所述开关晶体管的第一极连接数据线，所述开关晶体管的第二极连接所述补偿单元的第一端、所述驱动晶体管的第一极和所述发光控制单元，所述开关晶体管的控制极连接扫描线，所述数据线提供所述数据电压信号，所述扫描线提供所述扫描信号。
在一些实施方式中，所述驱动晶体管的第一极连接所述驱动晶体管的第一极连接所述发光控制单元、所述补偿单元的第一端和所述开关晶体管的第二极，所述驱动晶体管的第二极连接所述阈值电压提取单元和所述发光器件的第一极，所述驱动晶体管的控制极连接所述存储电容的第一端和所述阈值电压提取单元。
本公开的实施例还提供一种显示装置，其包括上述的像素电路。
附图说明
图1为一种像素电路的结构示意图；
图2为本公开的实施例的一种像素电路的结构示意图；
图3为本公开的实施例的一种像素电路的结构示意图；
图4为本公开的实施例的像素电路的工作时序图；
图5为本公开的实施例的一种像素电路的结构示意图；
图6为本公开的实施例的一种像素电路的结构示意图；以及
图7为本公开的实施例的一种像素电路的结构示意图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和实施例对本公开的技术方案作进一步详细描述。
本公开的实施例中所采用的晶体管可以为薄膜晶体管、场效应管、或其他特性相同的器件，由于晶体管的源极和漏极在一定条件下是可以互换的，所以对晶体管的源极和漏极的连接关系的描述上没有区别的。在本公开的实施例中，为区分晶体管的源极和漏极，将晶体管的源极和漏极中的一者称为第一极、另一者称为第二极，而将晶体管的栅极称为控制极。此外，按照晶体管的特性进行区分可以将晶体管分为N型晶体管和P型晶体管，以下实施例中是以采用P型晶体管为例进行说明的。当采用P型晶体管时，P型晶体管的第一极可为P型晶体管的源极，P型晶体管的第二极可为P型晶体管的漏极，P型晶体管的栅极(即，控制极)输入低电平时，P型晶体管的源极和漏极导通。应当理解的是，采用N型晶体管实现本公开的实施例的技术方案是本领域技术人员可以在不付出创造性劳动的前提下轻易想到的。对于N型晶体管而言，N型晶体管的栅极(即，控制极)输入高电平时，N型晶体管的源极和漏极导通。
图1示出了一种像素电路的结构示意图。如图1所示，该像素电路包括发光器件OLED、发光控制单元1、阈值电压提取单元2、复位单元3、开关晶体管M2、驱动晶体管M3和存储电容Cst。开关晶体管M2在扫描线Scan上的扫描信号的控制下导通以将数据线Data上的数据电压信号传输至驱动晶体管M3的第一极，但是，由于控制开关晶体管M2导通和关断的扫描信号不同，例如，开关晶体管M2为P型晶体管时，控制其导通的扫描信号为低电平，控制其关断的扫描信号则为高电平，因此，在扫描信号在高电平和低电平之间进行切换的过程中，开关晶体管M2的第二极和控制极之间会产生寄生电容， 从而导致在开关晶体管M2的第二极处产生馈通电压，与此同时，由于显示面板中位于同一行的像素电路中的开关晶体管M2通常连接同一条扫描线Scan，这样一来，由于扫描线Scan上存在电阻，因此，在扫描线Scan的电阻的作用下，远离扫描线Scan的扫描信号输入端的像素电路的开关晶体管M2的扫描信号的电压小于靠近扫描线Scan的扫描信号输入端的像素电路的开关晶体管M2的扫描信号的电压，从而，在扫描信号在高电平和低电平之间进行切换的过程中，同一行的像素电路中不同位置处的开关晶体管M2的第二极和控制极之间产生的寄生电容的大小不同，即，同一行的像素电路中不同位置处的开关晶体管M2的第二极处所产生的馈通电压不同，导致显示面板的显示不均一。
图2示出了本公开的实施例的一种像素电路的结构示意图。如图2所示，本公开的实施例的像素电路包括发光器件OLED、发光控制单元1、阈值电压提取单元2、复位单元3、开关晶体管M2、驱动晶体管M3、存储电容Cst以及补偿单元4。发光器件OLED具有连接驱动晶体管M3的漏极的第一极、以及接收第一电源电压端VSS的第二极。存储电容Cst的第一端连接驱动晶体管M3的栅极，存储电容Cst的第二端连接参考电压端Vref1。开关晶体管M2在扫描线Scan上的扫描信号的控制下，将数据线Data上的数据电压信号传输至驱动晶体管M3的源极。阈值电压提取单元2在扫描线Scan上的扫描信号的控制下，连接驱动晶体管M3的栅极和漏极。发光控制单元1在发光控制信号端EM提供的发光控制信号的控制下，将第二电源电压端VDD提供的第二电源电压传输至驱动晶体管M3的源极、以及驱动发光器件OLED发光。补偿单元4配置为将补偿电压端Vref3提供的补偿电压传输至开关晶体管M2的漏极，以降低开关晶体管M2的馈通电压。
由于在本实施例的像素电路中增设了补偿单元4，且该补偿单元4能够通过补偿电压来降低开关晶体管M2的所产生的馈通电压，这样一来，应用本实施例的像素电路的显示面板中，由于各个像素电路 中的开关晶体管M2的馈通电压均变小，因此，能够大幅度减小不同位置的开关晶体管M2的馈通电压的差异，从而可有效地改善显示面板的显示不均一的问题。
在本实施例的像素电路中，补偿单元4可以包括补偿电容Cc，补偿电容Cc的第一端连接开关晶体管M2的漏极，补偿电容Cc的第二端连接补偿电压端Vref3。补偿电压端Vref3用以提供补偿电压。当然，补偿单元4也不局限仅包含补偿电容Cc。根据电容公式C＝ε×ε 0×S/d，ε为电容器的绝缘层材料的介电常数，ε 0为真空介电常数，S为电容器面积，d为电容器绝缘层厚度。可以调整ε、ε 0、S、d来确定补偿电容Cc的大小。
如图3所示，在本实施例像素电路中，复位单元3在复位信号端Reset提供的复位控制信号的控制下，将初始化信号端Vref2提供的初始化信号传输至N1节点。N1节点为复位单元3、所述存储电容Cst的第一端、所述驱动晶体管M3的控制极之间的连接节点。
具体地，复位单元3可包括复位晶体管M5。复位晶体管M5的源极连接初始化信号端Vref2，复位晶体管M5的漏极连接所述N1节点，复位晶体管M5的栅极连接复位信号端Reset。复位信号端Reset提供复位控制信号。初始化信号端Vref2提供初始化信号。当然，复位单元3也不局限仅包括复位晶体管M5。
在本实施例的像素电路中，阈值电压提取单元2可包括阈值电压提取晶体管M4。阈值电压提取晶体管M4的源极连接N1节点，阈值电压提取晶体管M4的漏极连接N3节点，阈值电压提取晶体管M4的栅极连接扫描线Scan。N3节点为驱动晶体管M3的漏极和发光器件OLED的第一极之间的连接节点。扫描线Scan提供扫描信号。
在本实施例的像素电路中，发光控制单元1可包括第一发光控制晶体管M1。第一发光控制晶体管M1的源极连接第二电源电压端VDD，第一发光控制晶体管M1的漏极连接N2节点，第一发光控制晶体管M1的栅极连接发光控制信号端EM。发光控制信号端EM提供发光控制信号。发光控制单元1还可以包括第二发光控制晶体管M6，第二发光控制晶体管M6的源极连接N3节点，第二发光控制晶体管M6的漏 极连接发光器件OLED的第一极。发光器件OLED的第二极连接第一电源电压端VSS。
本实施例的像素电路中，存储电容Cst的第二端可以直接连接第二电源电压端VDD，第二电源电压端VDD提供第二电源电压，即第二电源电压端VDD与参考电压端Vref1可共用，第二电源电压可用作参考电压，以减少像素电路的信号端口的设置。
本实施例的像素电路中，开关晶体管M2的源极连接数据线Data，开关晶体管M2的漏极连接N2节点，开关晶体管M2的栅极连接扫描线Scan。N2节点为补偿单元4的第一端、驱动晶体管M3的源极和发光控制单元1之间的连接节点。数据线Data提供数据电压信号。扫描线Scan提供扫描信号。
本实施例的像素电路中，驱动晶体管M3的源极连接N2节点，驱动晶体管M3的漏极连接N3节点，驱动晶体管M3的栅极连接N1节点。N1节点为存储电容Cst的第一端和阈值电压提取单元2之间的连接节点。N2节点为发光控制单元1、补偿单元4的第一端和开关晶体管M2的漏极之间的连接节点。N3节点为阈值电压提取单元2和发光器件OLED的第一极之间的连接节点。
为了更清楚本实施例中的像素电路的实现方式，以下结合图3和4所示，对上述的像素电路的工作过程进行说明。
T1阶段，也即初始化阶段，给复位信号端Reset写入复位控制信号，该复位控制信号为低电平信号，复位晶体管M5导通，此时初始化信号端Vref2写入的初始化信号通过复位晶体管M5对N1节点进行复位。
T2阶段，也即数据写入及阈值电压提取阶段，给扫描线Scan写入扫描信号，该扫描信号为低电平信号，开关晶体管M2和阈值电压提取晶体管M4导通，此时数据线Data上写入的数据电压信号被写入至N2节点，同时由于开关晶体管M2的馈通效应，致使N2节点的电压为数据电压和馈通电压之和(V data+V feedthrough)，而由于阈值电压提取晶体管M4的导通，N3节点的电压等于N1节点的电压，而N1节点的电压为V data+V feedthrough-V th。
T3阶段，也即发光阶段，给发光控制信号端EM写入发光控制信号，该发光控制信号为低电平信号，第一发光控制晶体管M1和第二发光控制晶体管M6导通，此时N2节点的电压为第二电源电压端VDD提供的第二电源电压，由于N1节点的电压为V data+V feedthrough-V th，因此驱动发光器件OLED发光的电流为I ds，I ds按照如下公式计算得到。
I ds＝K×(V gs-V th) 2
＝K×(N2-N1-V th) 2
＝K×(VDD-V data-V feedthrough+|V th|-|V th|) 2
＝K×(VDD-V data-V feedthrough) 2
K为1/2×Cox×W/L×mobility，在本实施例中，将K作为定值进行分析。
图1中所示的像素电路中开关晶体管M2的馈通电压按照如下的馈通电压计算公式可以计算得到。
Figure PCTCN2019091075-appb-000001
C ox为开关晶体管M2的栅极绝缘层的单位面积上的电容大小，V GH为扫描信号为高电平时的电压值，V GL为扫描信号为低电平时的电压值，V TH为开关晶体管M2的阈值电压，W为开关晶体管M2的沟道宽度，L为开关晶体管M2的沟道长度，C gdM1为第一发光控制晶体管M1的栅漏寄生电容，C gdM2为开关晶体管M2的栅漏寄生电容，C gdM6为第二发光控制晶体管M6的栅漏寄生电容，Cst为存储电容Cst的电容值。
在本实施例中，由于增设了补偿电容Cc，开关晶体管M2的馈通电压可通过如下计算公式计算得到。
Figure PCTCN2019091075-appb-000002
Cc为补偿电容Cc的电容值。
可以得知由于增设了补偿电容Cc，因此本实施例中的开关晶体管M2的馈通电压明显减小，因此，应用本实施例的像素电路的显示面板中，由于各个像素电路中的开关晶体管M2的馈通电压均变小，因此，能够大幅度减小不同位置的开关晶体管M2的馈通电压的差异， 从而可有效地改善显示面板的显示不均一的问题。
本公开的实施例还提供一种像素电路，如图5所示，该像素电路包括发光器件OLED、发光控制单元1、阈值电压提取单元2、复位单元3、开关晶体管M2、驱动晶体管M3、存储电容Cst以及补偿单元4。发光控制单元1包括第一发光控制晶体管M1和第二发光控制晶体管M6。阈值电压提取单元2包括阈值电压提取晶体管M4。复位单元3包括复位晶体管M5。补偿单元4包括补偿电容Cc。
具体地，如图5所示，开关晶体管M2的源极连接数据线Data，开关晶体管M2的漏极连接N2节点，开关晶体管M2的栅极连接扫描线Scan。驱动晶体管M3的源极连接N2节点，驱动晶体管M3的漏极连接N3节点，驱动晶体管M3的栅极连接N1节点。发光控制单元1中，第一发光控制晶体管M1的源极连接第二电源电压端VDD，第一发光控制晶体管M1的漏极连接N2节点，第一发光控制晶体管M1的栅极连接发光控制信号端EM，第二发光控制晶体管M6的源极连接N3节点，第二发光控制晶体管M6的漏极连接发光器件OLED的第一极，第二发光控制晶体管M6的栅极连接发光控制信号端EM。发光器件OLED的第二极连接第一电源电压端VSS。阈值电压提取晶体管M4的源极连接N1节点，阈值电压提取晶体管M4的漏极连接N3节点，阈值电压提取晶体管M4的栅极连接扫描线Scan。复位晶体管M5的源极连接初始化信号端Vref2，复位晶体管M5的漏极连接N1节点，复位晶体管M5的栅极连接复位信号端Reset。补偿电容Cc的第一端连接N2节点，补偿电容Cc的第二端连接第二电源电压端VDD。此时，补偿电压端Vref3与第二电源电压端VDD共用。也就是说，在本实施例中，将第二电源电压端VDD所写入的第二电源电压作为补偿电压。
结合图4所示，对上述的像素电路的工作过程进行说明。
T1阶段，也即初始化阶段，给复位信号端Reset写入复位控制信号，该复位控制信号为低电平信号，复位晶体管M5导通，此时初始化信号端Vref2写入的初始化信号通过复位晶体管M5对N1节点进行复位。
T2阶段，也即数据写入及阈值电压提取阶段，给扫描线Scan写入扫描信号，该扫描信号为低电平信号，开关晶体管M2和阈值电压提取晶体管M4导通，此时数据线Data上写入的数据电压信号被写入至N2节点，同时由于开关晶体管M2的馈通效应，N2节点的电压为数据电压和馈通电压之和(V data+V feedthrough)，而由于阈值电压提取晶体管M4的导通，N3节点的电压等于N1节点的电压，而N1节点的电压为V data+V feedthrough-V th。
T3阶段，也即发光阶段，给发光控制信号端EM写入发光控制信号，该发光控制信号为低电平信号，第一发光控制晶体管M1和第二发光控制晶体管M6导通，此时N2节点的电压为第二电源电压VDD，由于N1节点的电压为V data+V feedthrough-V th，因此驱动发光器件OLED发光的电流为I ds，I ds按照如下公式计算得到。
I ds＝K×(V gs-V th) 2
＝K×(N2-N1-V th) 2
＝K×(VDD-V data-V feedthrough+|V th|-|V th|) 2
＝K×(VDD-V data-V feedthrough) 2
K为1/2×Cox×W/L×mobility，在本实施例中，将K作为定值进行分析。
图1中所示的像素电路中的开关晶体管M2的馈通电压按照如下的馈通电压计算公式可以计算得到。
Figure PCTCN2019091075-appb-000003
C ox为开关晶体管M2的栅极绝缘层的单位面积上的电容大小，V GH为扫描信号为高电平时的电压值，V GL为扫描信号为低电平时的电压值，V TH为开关晶体管M2的阈值电压，W为开关晶体管M2的沟道宽度，L为开关晶体管M2的沟道长度，C gdM1为第一发光控制晶体管M1的栅漏寄生电容，C gdM2为开关晶体管M2的栅漏寄生电容，C gdM6为第二发光控制晶体管M6的栅漏寄生电容，Cst为存储电容Cst。
在本实施例中，由于增设了补偿电容Cc，开关晶体管M2的馈通电压可通过如下计算公式计算得到。
Figure PCTCN2019091075-appb-000004
Cc为补偿电容Cc的电容值。
可以得知由于增设了补偿电容Cc，因此本实施例中的开关晶体管M2的馈通电压明显减小，因此，应用本实施例的像素电路的显示面板中，由于各个像素电路中的开关晶体管M2馈的通电压均变小，因此，能够大幅度减小不同位置的开关晶体管M2的馈通电压的差异，从而可有效地改善显示面板的显示不均一的问题。
本公开的实施例还提供一种像素电路，如图6所示，该像素电路同样包括发光器件OLED、发光控制单元1、阈值电压提取单元2、复位单元3、开关晶体管M2、驱动晶体管M3、存储电容Cst以及补偿单元4。发光控制单元1包括第一发光控制晶体管M1和第二发光控制晶体管M6。阈值电压提取单元2包括阈值电压提取晶体管M4。复位单元3包括复位晶体管M5。补偿单元4包括补偿电容Cc。本实施例中，如图6所示，补偿电容Cc的第一端连接N2节点，补偿电容Cc的第二端连接初始化信号端Vref2，此时，补偿电压端Vref3与初始化信号端Vref2共用。也就是说，在本实施例中，将复位晶体管M5的源极所写入的初始化信号作为补偿电压。
本公开的实施例还提供一种像素电路，如图7所示，该像素电路同样包括发光器件OLED、发光控制单元1、阈值电压提取单元2、复位单元3、开关晶体管M2、驱动晶体管M3、存储电容Cst以及补偿单元4。发光控制单元1包括第一发光控制晶体管M1和第二发光控制晶体管M6。阈值电压提取单元2包括阈值电压提取晶体管M4。复位单元3包括复位晶体管M5。补偿单元4包括补偿电容Cc。本实施例中，如图7所示，补偿电容Cc的第一端连接N2节点，补偿电容Cc的第二端连接复位晶体管M5的栅极，由于复位晶体管M5的栅极连接复位信号端Reset，此时，补偿电压端Vref3与复位信号端Reset共用。也就是说，在本实施例中，将复位晶体管M5的栅极所写入的 复位控制信号作为补偿电压。
事实上，本公开的实施例的像素电路中，补偿单元4所包括的补偿电容Cc的第一端连接N2节点(即，开关晶体管M2的漏极)，补偿电容Cc的第二端只要连接至在开关晶体管M2开始导通到当前帧的显示结束的时段(包括T2和T3)内提供定值电压的端或线即可。
本公开的实施例还提供一种显示装置，该显示装置包括本公开的实施例提供的任意一种像素电路。
本实施例中的显示装置可以包括OLED显示面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等具有显示功能的任何产品或部件。
由于具有本公开的实施例的像素电路，故本实施例的显示装置的画面显示的均匀性明显提高。
可以理解的是，以上实施例仅仅是为了说明本公开的技术方案的原理而采用的示例性实施例，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的实质的情况下，可以做出各种变型和改进，这些变型和改进也应视为落入本公开的保护范围内。

Claims (14)

  1. 一种像素电路，包括开关晶体管、驱动晶体管、存储电容、阈值电压提取单元、发光控制单元、发光器件、以及补偿单元，其中，
    所述发光器件具有连接所述驱动晶体管的第二极的第一极、以及接收第一电源电压的第二极，
    所述存储电容的第一端连接所述驱动晶体管的控制极，所述存储电容的第二端连接参考电压端，
    所述开关晶体管在扫描信号的控制下，将数据电压信号传输至所述驱动晶体管的第一极，
    所述阈值电压提取单元在所述扫描信号的控制下，连接所述驱动晶体管的控制极和第二极，
    所述发光控制单元在发光控制信号的控制下，将第二电源电压传输至所述驱动晶体管的第一极，以及
    所述补偿单元将补偿电压传输至所述开关晶体管的第二极，以降低所述开关晶体管的馈通电压。
  2. 根据权利要求1所述的像素电路，其中，所述补偿单元包括补偿电容，所述补偿电容的第一端连接所述开关晶体管的第二极，所述补偿电容的第二端连接补偿电压端，所述补偿电压端提供所述补偿电压。
  3. 根据权利要求2所述的像素电路，还包括复位单元，所述复位单元在复位控制信号的控制下，将初始化信号传输至所述驱动晶体管的控制极。
  4. 根据权利要求3所述的像素电路，其中，所述复位单元包括复位晶体管，其中，
    所述复位晶体管的第一极连接初始化信号端，所述复位晶体管的第二极连接所述驱动晶体管的控制极，所述复位晶体管的控制极连 接复位信号端，所述初始化信号端提供所述初始化信号，所述复位信号端提供复位控制信号。
  5. 根据权利要求4所述的像素电路，其中，所述补偿电容的第一端连接所述开关晶体管的第二极和所述驱动晶体管的第一极，所述补偿电容的第二端连接所述初始化信号端，所述初始化信号端与所述补偿电压端共用。
  6. 根据权利要求4所述的像素电路，其中，所述补偿电容的第一端连接所述开关晶体管的第二极和所述驱动晶体管的第一极，所述补偿电容的第二端连接所述复位信号端，所述复位信号端与所述补偿电压端共用。
  7. 根据权利要求2所述的像素电路，其中，所述发光控制单元包括第一发光控制晶体管，其中，
    所述第一发光控制晶体管的第一极连接第二电源电压端，所述第一发光控制晶体管的第二极连接所述开关晶体管的第二极、所述驱动晶体管的第一极和所述补偿电容的第一端，所述第一发光控制晶体管的控制极连接发光控制信号端，所述发光控制信号端提供发光控制信号。
  8. 根据权利要求7所述的像素电路，其中，所述补偿电容的第一端连接所述开关晶体管的第二极，所述补偿电容的第二端连接所述第二电源电压端，所述第二电源电压端提供第二电源电压、且与所述补偿电压端共用。
  9. 根据权利要求7或8所述的像素电路，其中，所述发光控制单元还包括第二发光控制晶体管，其中，
    所述第二发光控制晶体管的第一极连接所述阈值电压提取单元和所述驱动晶体管的第二极，所述第二发光控制晶体管的第二极连接 所述发光器件的第一极，所述第二发光控制晶体管的控制极连接所述发光控制信号端。
  10. 根据权利要求1或2所述的像素电路，其中，所述阈值电压提取单元包括阈值电压提取晶体管，其中，
    所述阈值电压提取晶体管的第一极连接所述存储电容的第一端和所述驱动晶体管的控制极，所述阈值电压提取晶体管的第二极连接所述驱动晶体管的第二极和所述发光器件的第一极，所述阈值电压提取晶体管的控制极连接扫描线，所述扫描线提供所述扫描信号。
  11. 根据权利要求1或2所述的像素电路，其中，所述存储电容的第一端连接所述驱动晶体管的控制极和所述阈值电压提取单元，所述存储电容的第二端连接第二电源电压端，所述第二电源电压端提供第二电源电压、且与所述参考电压端共用。
  12. 根据权利要求1或2所述的像素电路，其中，所述开关晶体管的第一极连接数据线，所述开关晶体管的第二极连接所述补偿单元的第一端、所述驱动晶体管的第一极和所述发光控制单元，所述开关晶体管的控制极连接扫描线，所述数据线提供所述数据电压信号，所述扫描线提供所述扫描信号。
  13. 根据权利要求1或2所述的像素电路，其中，所述驱动晶体管的第一极连接所述发光控制单元、所述补偿单元的第一端和所述开关晶体管的第二极，所述驱动晶体管的第二极连接所述阈值电压提取单元和所述发光器件的第一极，所述驱动晶体管的控制极连接所述存储电容的第一端和所述阈值电压提取单元。
  14. 一种显示装置，包括根据权利要求1至12中任一项所述的像素电路。
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