WO2021238479A1 - 一种像素驱动电路及其驱动方法、显示装置 - Google Patents

一种像素驱动电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2021238479A1
WO2021238479A1 PCT/CN2021/087380 CN2021087380W WO2021238479A1 WO 2021238479 A1 WO2021238479 A1 WO 2021238479A1 CN 2021087380 W CN2021087380 W CN 2021087380W WO 2021238479 A1 WO2021238479 A1 WO 2021238479A1
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Prior art keywords
circuit
sub
control
light
transistor
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PCT/CN2021/087380
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English (en)
French (fr)
Inventor
于洋
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京东方科技集团股份有限公司
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Priority to US17/763,364 priority Critical patent/US12027114B2/en
Publication of WO2021238479A1 publication Critical patent/WO2021238479A1/zh

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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel driving circuit, a driving method thereof, and a display device.
  • AMOLED Active-matrix Organic Light-Emitting Diode, active matrix organic light-emitting diode
  • AMOLED Active-matrix Organic Light-Emitting Diode, active matrix organic light-emitting diode
  • has many advantages such as self-luminous, ultra-thin, fast response, high contrast, and wide viewing angle. It is currently a display device that has received widespread attention .
  • Such an AMOLED display device includes a plurality of pixel driving circuits and a plurality of light-emitting elements, and the pixel driving circuit is used to drive the corresponding light-emitting elements to emit light, thereby realizing the display function of the AMOLED display device.
  • the existing pixel driving circuit has complex control signals required, and the driving transistor in the pixel driving circuit has the problem of poor display brightness uniformity of the display device due to threshold voltage drift.
  • the purpose of the present disclosure is to provide a pixel driving circuit, a driving method thereof, and a display device.
  • a first aspect of the present disclosure provides a pixel driving circuit for driving a light-emitting element, including:
  • the driver sub-circuit is used to control the conduction or disconnection of the connection between the first terminal of the driver sub-circuit and the second terminal of the driver sub-circuit under the control of its control terminal, the driver sub-circuit The second end of the circuit is connected to the light-emitting element;
  • a first storage sub-circuit the first end of the first storage sub-circuit is connected to the control end;
  • the power control sub-circuit is respectively connected to the light-emission control signal line, the first power line and the first end of the driving sub-circuit, and is used to control the conduction or disconnection of the first terminal under the control of the light-emission control signal line.
  • the compensation sub-circuit is respectively connected to the first gate line, the control terminal of the driver sub-circuit and the first terminal of the driver sub-circuit, and is used to control the conduction or disconnection under the control of the first gate line The connection between the control terminal of the driver sub-circuit and the first terminal of the driver sub-circuit;
  • the data writing sub-circuit is respectively connected to the second gate line, the data line and the second end of the first storage sub-circuit, and is used to control the conduction or disconnection of the second gate line under the control of the second gate line.
  • the first reset sub-circuit is respectively connected to the reset signal line, the first power line and the control terminal of the drive sub-circuit, and is used to control the conduction or disconnection of the first reset signal line under the control of the reset signal line.
  • the first control sub-circuit is respectively connected to the second end of the first gate line, the initialization signal line, and the driving sub-circuit, and is used to control the conduction and disconnection of all the circuits under the control of the first gate line.
  • the pixel driving circuit further includes a light-emitting control sub-circuit, and the second end of the driving sub-circuit is connected to the light-emitting element through the light-emitting control sub-circuit;
  • the light-emitting control sub-circuit is respectively connected to the light-emitting control signal line, the second end of the driving sub-circuit, and the light-emitting element, and is used to control on or off under the control of the light-emitting control signal line The connection between the second end of the driving sub-circuit and the light-emitting element.
  • the pixel driving circuit further includes:
  • a second storage sub-circuit the first end of the second storage sub-circuit is connected to the control end of the driving sub-circuit, and the second end of the second storage sub-circuit is connected to the light-emitting element.
  • the light emission control sub-circuit includes:
  • a sixth transistor the gate of the sixth transistor is connected to the light emission control signal line, the first electrode of the sixth transistor is connected to the second end of the driving sub-circuit, and the second terminal of the sixth transistor is The pole is connected to the light-emitting element.
  • the pixel driving circuit further includes:
  • the second reset sub-circuit is respectively connected to the reset signal line, the initialization signal line and the light-emitting element, and is used to control the conduction or disconnection of the initialization signal line and the light emitting element under the control of the reset signal line. The connection between the light-emitting elements.
  • the second reset sub-circuit includes a seventh transistor, the gate of the seventh transistor is connected to the reset signal line, and the first pole of the seventh transistor is connected to the initialization signal line, so The second electrode of the seventh transistor is connected to the light-emitting element.
  • the pixel driving circuit further includes:
  • the second control sub-circuit is respectively connected to the second end of the first gate line, the initialization signal line and the first storage sub-circuit, and is used to control the on or off under the control of the first gate line. Open the connection between the initialization signal line and the second end of the first storage sub-circuit.
  • the second control sub-circuit includes a ninth transistor, the gate of the ninth transistor is connected to the first gate line, and the first electrode of the ninth transistor is connected to the initialization signal line, The second terminal of the ninth transistor is connected to the second terminal of the first storage sub-circuit.
  • the driving sub-circuit includes a third transistor
  • the first storage sub-circuit includes a first capacitor, and a first end of the first capacitor is connected to the gate of the third transistor;
  • the first reset sub-circuit includes a first transistor, a gate of the first transistor is connected to the reset signal line, a first pole of the first transistor is connected to the first power line, and the first transistor is connected to the reset signal line.
  • the second electrode of the transistor is connected to the gate of the third transistor;
  • the compensation sub-circuit includes a second transistor, the gate of the second transistor is connected to the first gate line, the first electrode of the second transistor is connected to the first electrode of the third transistor, and the The second electrode of the second transistor is connected to the gate of the third transistor;
  • the data writing sub-circuit includes a fourth transistor, the gate of the fourth transistor is connected to the second gate line, the first electrode of the fourth transistor is connected to the data line, and the fourth transistor The second pole of is connected to the second end of the first capacitor;
  • the power control sub-circuit includes a fifth transistor, the gate of the fifth transistor is connected to the light emission control signal line, the first pole of the fifth transistor is connected to the first power line, and the fifth transistor is connected to the first power line.
  • the second pole of the transistor is connected to the first pole of the third transistor;
  • the first control sub-circuit includes an eighth transistor, the gate of the eighth transistor is connected to the first gate line, the first electrode of the eighth transistor is connected to the initialization signal line, and the eighth transistor is connected to the initialization signal line.
  • the second pole of the transistor is connected to the second end of the driving sub-circuit.
  • a second aspect of the present disclosure provides a display device including the above pixel driving circuit.
  • the display device includes a plurality of the pixel drive circuits distributed in an array, and the plurality of pixel drive circuits are divided into multiple rows of pixel drive circuits; the display device further includes a gate drive circuit and a light emitting signal control circuit , Multiple first gate lines, multiple second gate lines, multiple reset signal lines, and multiple light-emitting control signal lines;
  • the gate driving circuit includes a plurality of first shift register units corresponding to a plurality of rows of pixel driving circuits one-to-one;
  • the light-emitting signal control circuit includes a plurality of second shift register units
  • the plurality of first gate lines are in one-to-one correspondence with the plurality of first shift register units and the plurality of rows of pixel driving circuits, and each pixel driving circuit included in each row of pixel driving circuits corresponds to the corresponding first
  • the gate line is connected, and the first gate line is connected to the output terminal of the corresponding first shift register unit;
  • the plurality of second gate lines correspond to the plurality of rows of pixel driving circuits one-to-one, and each pixel driving circuit included in each row of pixel driving circuits is respectively connected to the corresponding second gate line, and all the pixel driving circuits corresponding to the current row are connected to each other.
  • the second gate line is connected to the output terminal of the first shift register unit corresponding to the pixel driving circuit in the next row next;
  • the multiple reset signal lines correspond to the multiple rows of pixel drive circuits one-to-one, each pixel drive circuit included in each row of pixel drive circuits is connected to a corresponding reset signal line, and the reset signal line corresponding to the pixel drive circuit of the current row Connected to the output terminal of the first shift register unit corresponding to the adjacent pixel driving circuit of the previous row;
  • the multiple light-emitting control signal lines correspond to the multiple rows of pixel drive circuits in a one-to-one correspondence, each pixel drive circuit included in each row of pixel drive circuits is respectively connected to a corresponding light-emitting control signal line, and each second shift register unit The output terminal of is connected to at least one corresponding light-emitting control signal line.
  • a third aspect of the present disclosure provides a driving method of the pixel driving circuit, which is applied to the above pixel driving circuit, and the driving method includes: in each work cycle,
  • the first power line inputs the power supply voltage Vd, and under the control of the reset signal line, the first reset sub-circuit controls the connection between the first power line and the control terminal of the drive sub-circuit;
  • the first reset sub-circuit controls the disconnection between the first power line and the control terminal of the drive sub-circuit;
  • the initialization signal line inputs the initialization voltage Vinit
  • the first control sub-circuit controls to turn on the connection between the initialization signal line and the second end of the driver sub-circuit, and the compensation sub-circuit controls the turn-on of the driver sub-circuit
  • the connection between the control terminal and the first terminal of the driver sub-circuit, so that the first terminal and the second terminal of the driver sub-circuit change from conducting to the cut-off, so that the control terminal of the driver sub-circuit is The potential changes from Vd to Vinit+Vth, and Vth is the threshold voltage corresponding to the driving sub-circuit;
  • the first control sub-circuit controls the disconnection of the connection between the initialization signal line and the second end of the drive sub-circuit, and the compensation sub-circuit controls the disconnection.
  • the connection with the second terminal of the first storage sub-circuit makes the potential of the second terminal of the first storage sub-circuit become Vdata, and the potential of the control terminal of the driver sub-circuit is at the first storage sub-circuit.
  • the power signal input terminal is input with a power voltage Vdd, and under the control of the light-emitting control signal line, the power control sub-circuit controls the first power line and the first driving sub-circuit to conduct.
  • the data writing sub-circuit controls the disconnection of the connection between the data line and the second end of the first storage sub-circuit, and the driving sub-circuit is in Under the control of the control terminal, the connection between the first terminal of the driving sub-circuit and the second terminal of the driving sub-circuit is controlled to drive the light-emitting element to emit light.
  • the pixel driving circuit further includes a light-emitting control sub-circuit, the second end of the driving sub-circuit is connected to the light-emitting element through the light-emitting control sub-circuit; the light-emitting control sub-circuit is respectively connected to the light-emitting element The control signal line and the second end of the driving sub-circuit are connected to the light-emitting element; the pixel driving circuit further includes a second storage sub-circuit, and the first end of the second storage sub-circuit is connected to the driving sub-circuit Connected to the control terminal of the second storage sub-circuit, and connected to the light-emitting element;
  • the driving method further includes:
  • the light-emission control sub-circuit controls to disconnect the second end of the driving sub-circuit from the The connection between the light-emitting elements
  • the light-emitting control sub-circuit controls the connection between the second end of the driving sub-circuit and the light-emitting element, and the driving sub-circuit
  • the potential of the control terminal is changed correspondingly under the bootstrap action of the second storage sub-circuit.
  • the pixel driving circuit further includes a second reset sub-circuit, and the second reset sub-circuit is respectively connected to the reset signal line, the initialization signal line and the light-emitting element;
  • the pixel drive circuit controls to turn on the connection between the initialization signal line and the light-emitting element
  • the pixel driving circuit controls to disconnect the initialization signal line and the light-emitting element. connect.
  • the pixel driving circuit further includes a second control sub-circuit, the second control sub-circuit is respectively connected to the first gate line, the initialization signal line and the second end of the first storage sub-circuit;
  • the second control sub-circuit controls to disconnect the initialization signal line from the first storage line.
  • the second control sub-circuit controls to turn on the connection between the initialization signal line and the second end of the first storage sub-circuit.
  • FIG. 1 is a schematic diagram of a first structure of a pixel driving circuit provided by an embodiment of the disclosure
  • FIG. 2 is a schematic diagram of a second structure of a pixel driving circuit provided by an embodiment of the disclosure
  • FIG. 3 is a schematic diagram of a third structure of a pixel driving circuit provided by an embodiment of the disclosure.
  • FIG. 4 is a schematic diagram of a fourth structure of a pixel driving circuit provided by an embodiment of the disclosure.
  • FIG. 5 is a schematic diagram of a fifth structure of a pixel driving circuit provided by an embodiment of the disclosure.
  • FIG. 6 is a schematic diagram of a first circuit of a pixel driving circuit provided by an embodiment of the disclosure.
  • FIG. 7 is a working timing diagram of a pixel driving circuit provided by an embodiment of the disclosure.
  • FIG. 8 is a schematic diagram of the operation of the pixel driving circuit provided by the embodiment of the disclosure during the reset period
  • FIG. 9 is a schematic diagram of the operation of the pixel driving circuit provided by the embodiment of the disclosure in the threshold compensation period
  • FIG. 10 is a schematic diagram of the operation of the pixel driving circuit provided by an embodiment of the disclosure during a data writing period
  • FIG. 11 is a schematic diagram of the operation of the pixel driving circuit provided by the embodiment of the disclosure during the light-emitting period
  • FIG. 12 is a schematic diagram of the connection of Gate GOA provided by an embodiment of the disclosure.
  • an embodiment of the present disclosure provides a pixel driving circuit for driving a light-emitting element EL, and the pixel driving circuit includes:
  • the driver sub-circuit 1 is used to control the conduction or disconnection of the connection between the first terminal of the driver sub-circuit 1 and the second terminal of the driver sub-circuit 1 under the control of its control terminal,
  • the second end of the driving sub-circuit 1 is connected to the light-emitting element EL;
  • the power control sub-circuit 3 is respectively connected to the light-emission control signal line EM, the first power line VDD and the first end of the driving sub-circuit 1, and is used to control the conduction or conduction under the control of the light-emission control signal line EM. Disconnect the connection between the first power line VDD and the first end of the driving sub-circuit 1;
  • the compensation sub-circuit 4 is respectively connected to the first gate line GA1, the control terminal of the driver sub-circuit 1 and the first terminal of the driver sub-circuit 1, and is used for controlling under the control of the first gate line GA1 Turn on or disconnect the connection between the control terminal of the driver sub-circuit 1 and the first terminal of the driver sub-circuit 1;
  • the data writing sub-circuit 5 is respectively connected to the second end of the second gate line GA2, the data line DA and the first storage sub-circuit 21, and is used to control the conduction under the control of the second gate line GA2 Or disconnect the connection between the data line DA and the second end of the first storage sub-circuit 21;
  • the first reset sub-circuit 61 is respectively connected to the reset signal line RE, the first power supply line VDD and the control terminal of the drive sub-circuit 1, and is used to control the conduction or conduction under the control of the reset signal line RE. Disconnect the connection between the first power line VDD and the control terminal of the driving sub-circuit 1;
  • the first control sub-circuit 71 is respectively connected to the first gate line GA1, the initialization signal line Init, and the second end of the driving sub-circuit 1, and is used to control the conduction under the control of the first gate line GA1.
  • the connection between the initialization signal line Init and the second end of the driving sub-circuit 1 is turned on and off.
  • the pixel driving circuit is applied to a display device, and the display device includes a substrate, a plurality of pixel driving circuits arrayed on the substrate, and a side of the plurality of pixel driving circuits facing away from the substrate, And the light-emitting elements EL correspond to the plurality of pixel driving circuits one-to-one.
  • the light-emitting element EL specifically includes an anode, a light-emitting functional layer, and a cathode that are sequentially stacked in a direction away from the substrate.
  • the anode of the light-emitting element EL can be connected to the corresponding pixel drive circuit to receive the corresponding pixel drive circuit.
  • the driving signal provided by the pixel driving circuit, the cathode can be connected to the negative power signal line VSS in the display device, and the negative power signal input by the negative power signal line VSS is received.
  • the light emitting function layer is used to connect the anode and The cathode emits light under the combined action of the cathode.
  • the initialization signal input from the initialization signal line Init, the first power signal input from the first power line VDD, and the negative power signal input from the negative power signal line VSS are all constant voltage signals, wherein the initialization signal
  • the potential Vinit of is less than the potential of the negative power signal, and the potential of the negative power signal is less than the potential Vd of the first power signal.
  • Vinit is -3V
  • the potential of the negative power signal is -2.4V
  • Vd is 4.6V.
  • the first power supply line VDD is input with the power supply voltage Vd, and under the control of the reset signal input by the reset signal line RE, the first reset sub-circuit 61 controls to turn on the first
  • the connection between the power line VDD and the control terminal of the driver sub-circuit 1 makes the potential of the control terminal (ie node N1) of the driver sub-circuit 1 become Vd, so as to realize the control terminal of the driver sub-circuit 1 Reset.
  • the dashed lines with arrows in FIGS. 8 to 11 represent signal trends.
  • the first reset sub-circuit 61 controls to disconnect the first power line VDD from the drive
  • the connection between Init and the second end of the driving sub-circuit 1 ie, the N3 node
  • the compensation sub-circuit 4 controls to turn on the connection between the control terminal of the driving sub-circuit 1 and the first terminal of the driving sub-circuit 1.
  • the potential of the control terminal becomes Vd, so that the first terminal and the second terminal included in the driving sub-circuit 1 can be electrically connected, and the connection between the first terminal and the second terminal of the driving sub-circuit 1
  • the relationship undergoes a process from on to off to realize the charging of the N1 node, so that the potential of the N1 node is finally changed from Vd to Vinit+Vth, and Vth is the threshold voltage corresponding to the driving sub-circuit 1.
  • the first control sub-circuit 71 controls to disconnect the initialization signal line Init and the The connection between the second terminal of the driver sub-circuit 1; under the control of the first scan signal input by the first gate line GA1, the compensation sub-circuit 4 controls to disconnect the control terminal of the driver sub-circuit 1 and the driver The connection between the first end of the circuit 1; the data line DA inputs the data voltage Vdata, and under the control of the second scan signal input from the second gate line GA2, the data writing sub-circuit 5 controls to turn on the data line DA and The connection between the second end of the first storage sub-circuit 21 causes the potential of the second end (ie, the N2 node) of the first storage sub-circuit 21 to become Vdata, because in the data writing period P3, The control terminal of the driving sub-circuit 1 is in a floating state, and the potential of the control terminal of the driving sub-circuit 1 changes
  • the initial potential of the second terminal of the first storage sub-circuit 21 is 0, then after the data voltage Vdata is written, the amount of change in the potential of the second terminal of the first storage sub-circuit 21 is Vdata. Under the bootstrap action of the first storage sub-circuit 21, the potential of the control terminal of the driving sub-circuit 1 becomes Vinit+Vth+Vdata correspondingly.
  • the power signal input terminal inputs the power voltage Vdd
  • the power control sub-circuit 3 controls The connection between the first power supply line VDD and the first end of the driving sub-circuit 1 is turned on; under the control of the second scan signal written by the second gate line GA2, the data writing sub-circuit 5 is controlled to be turned off Open the connection between the data line DA and the second end of the first storage sub-circuit 21; under the control of its control end, the driving sub-circuit 1 controls to turn on the first end of the driving sub-circuit 1 and The second end of the driving sub-circuit 1 is connected to drive the light-emitting element EL to emit light.
  • the N1 node is charged during the threshold compensation period P2, so that the potential of the N1 node is Vd becomes Vinit+Vth; at the same time, the connection between the initialization signal line Init and the second end of the driving sub-circuit 1 (that is, the N3 node) is turned on, so that the second end of the driving sub-circuit 1 The potential becomes Vinit; in the data writing period P3, the data voltage Vdata is written so that the potential of the control terminal of the driving sub-circuit 1 becomes Vinit+Vth+Vdata; in the light-emitting period P4, the power control sub-circuit 3 controls The connection between the first power line VDD and the first terminal of the driving sub-circuit 1 is turned on, so that the driving sub-circuit 1 is controlled to turn on the first terminal of the driving sub-circuit 1 under the control of its control
  • Vgs Vinit+Vth+Vdata-Voled Formula (1)
  • Voled is the working voltage of the light-emitting element EL, and the driving current I generated when the first terminal and the second terminal of the driving sub-circuit 1 are turned on and working in a saturated state is:
  • k is a constant related to the width-to-length ratio and mobility of the transistor included in the driving sub-circuit 1.
  • the driving current I has nothing to do with the threshold voltage Vth corresponding to the driving sub-circuit and the power supply voltage Vd; therefore, in the pixel driving circuit provided by the embodiment of the present disclosure, the threshold voltage Vth drift and the power supply voltage Vd are eliminated.
  • the influence on the driving current I effectively improves the uniformity of the driving current and ensures the uniformity of the display brightness of the display device.
  • the display device when the pixel drive circuit provided by the embodiment of the present disclosure is applied to a display device, the display device includes a plurality of pixel drive circuits distributed in an array, and the first gate line GA1 corresponding to the pixel drive circuit of the current row can be set to input
  • the first scan signal, the first scan signal can be multiplexed into the reset signal input by the reset signal line RE connected to the pixel driving circuit of the next adjacent row; the first scan signal can also be multiplexed into the adjacent previous row
  • the pixel drive circuit corresponds to the second scan signal input by the second gate line GA2; therefore, when the pixel drive circuit provided by the embodiment of the present disclosure is applied to a display device, the pixel drive circuit only needs gateGOA and EMGOA to provide The corresponding signal requires fewer control signals, and at the same time it is compatible with the existing GOA design.
  • the pixel driving circuit further includes a light-emitting control sub-circuit 8.
  • the second end of the driving sub-circuit 1 communicates with the light-emitting control sub-circuit 8 through the light-emitting control sub-circuit 8.
  • the element EL is connected;
  • the light-emission control sub-circuit 8 is respectively connected to the light-emission control signal line EM, the second end of the drive sub-circuit 1 and the light-emitting element EL, and is used for connecting to the light-emission control signal line EM Under control, the connection between the second end of the driving sub-circuit 1 and the light-emitting element EL is controlled to be turned on or off.
  • the light-emission control sub-circuit 8 controls to turn on the second end of the driving sub-circuit 1 and the light-emitting element The connection between ELs.
  • the emission control sub-circuit 8 controls to turn off the drive sub-circuit 1
  • the connection between the second end and the light-emitting element EL can well prevent the light-emitting element EL from emitting abnormally during the reset period P1, the threshold compensation period P2, and the data writing period P3.
  • the pixel driving circuit further includes: a second storage sub-circuit 22, the first end of the second storage sub-circuit 22 and the driving sub-circuit 1 The control terminal is connected, and the second terminal of the second storage sub-circuit 22 is connected to the light emitting element EL.
  • the second storage sub-circuit 22 includes a second capacitor Cst2, a first terminal of the second capacitor Cst2 is connected to the control terminal of the driving sub-circuit 1, and a second terminal of the second capacitor Cst2 It is connected to the light-emitting element EL.
  • the light-emitting element EL emits light, and the potential of the N4 node jumps from Vinit to Voled.
  • Voled is the operating voltage of the light-emitting element EL.
  • the potential of the N1 node jumps from Vinit+Vth+Vdata to Vinit+Vth+Vdata+(Voled-Vinit), that is, the potential of the N1 node becomes Vth+Vdata+Voled.
  • Voled is the working voltage of the light-emitting element EL, and the driving current I generated when the first terminal and the second terminal of the driving sub-circuit 1 are turned on and working in a saturated state is:
  • the driving current I has nothing to do with the working voltage Voled of the light-emitting element EL; therefore, in the pixel driving circuit provided by the embodiment of the present disclosure, the influence of Voled on the driving current I is eliminated, and the display brightness of the display device is guaranteed. Uniformity.
  • the pixel driving circuit provided by the embodiment of the present disclosure also eliminates the influence of the negative power signal input from the negative power signal line VSS connected to the light emitting element EL on the driving current I.
  • the light emission control sub-circuit 8 includes a sixth transistor T6, the gate of the sixth transistor T6 is connected to the light emission control signal line EM, and the sixth transistor T6 The first pole of T6 is connected to the second terminal of the driving sub-circuit 1, and the second pole of the sixth transistor T6 is connected to the light emitting element EL.
  • the sixth transistor T6 is turned on, thereby controlling the conduction between the second end of the driving sub-circuit 1 and the The connection between the light-emitting elements EL.
  • the sixth transistor T6 is turned off, thereby controlling to turn off the driving sub-circuit
  • the connection between the second end of 1 and the light-emitting element EL prevents abnormal light emission of the light-emitting element EL during the reset period P1, the threshold compensation period P2, and the data writing period P3.
  • the pixel driving circuit further includes: a second reset sub-circuit 62, which is connected to the reset signal line RE and the initialization signal line respectively. Init is connected to the light-emitting element EL, and is used to control the connection between the initialization signal line Init and the light-emitting element EL under the control of the reset signal line RE.
  • the second reset sub-circuit 62 controls to conduct between the initialization signal line Init and the anode of the light emitting element EL. To realize resetting the anode of the light-emitting element EL.
  • the second reset sub-circuit 62 controls to disconnect the initialization signal line Init and the light emitting element EL. The connection between the anodes.
  • the second reset sub-circuit 62 includes a seventh transistor T7, the gate of the seventh transistor T7 is connected to the reset signal line RE, and the seventh transistor T7 The first pole of T7 is connected to the initialization signal line Init, and the second pole of the seventh transistor T7 is connected to the light emitting element EL.
  • the seventh transistor T7 is turned on to control the conduction between the initialization signal line Init and the anode of the light emitting element EL.
  • the connection between them realizes resetting the anode of the light-emitting element EL.
  • the seventh transistor T7 is turned off to control the disconnection of the initialization signal line Init and the light emitting element EL.
  • the pixel driving circuit further includes:
  • the second control sub-circuit 72 is respectively connected to the first gate line GA1, the initialization signal line Init, and the second end of the first storage sub-circuit 21, and is used for under the control of the first gate line GA1, The connection between the initialization signal line Init and the second end of the first storage sub-circuit 21 is controlled to be turned on or off.
  • the second control The sub-circuit 72 controls to disconnect the connection between the initialization signal line Init and the second end of the first storage sub-circuit 21.
  • the second control sub-circuit 72 controls to turn on the initialization signal line Init and the first storage line.
  • the connection between the second ends of the sub-circuit 21 writes and maintains the potential of the N2 node at Vinit.
  • the potential change of the N2 node is Vdata-Vinit, and under the bootstrap action of the first storage sub-circuit 21, the potential of the N1 node becomes Vinit+Vth+Vdata-Vinit, namely: Vth +Vdata.
  • the driving current I is:
  • the driving current I has no relationship with the operating voltage Voled of the light-emitting element EL, the threshold voltage Vth corresponding to the driving sub-circuit 1, and the power supply voltage Vd.
  • the above arrangement of the pixel driving circuit further includes a second control sub-circuit 72, so that the N2 node has a stable potential before the data writing period P3 starts, which is more conducive to the writing of data signals.
  • the second control sub-circuit 72 includes a ninth transistor T9, the gate of the ninth transistor T9 is connected to the first gate line GA1, and the ninth transistor The first pole of T9 is connected to the initialization signal line Init, and the second pole of the ninth transistor T9 is connected to the second end of the first storage sub-circuit 21.
  • the ninth transistor T9 is turned off.
  • the connection between the initialization signal line Init and the second end of the first storage sub-circuit 21 is controlled to be disconnected.
  • the ninth transistor T9 is turned on, and the initialization signal line Init and the first gate line are controlled to be turned on.
  • the connection between the second ends of the storage sub-circuit 21 writes and maintains the potential of the N2 node at Vinit.
  • the driving sub-circuit 1 includes a third transistor T3; the first storage sub-circuit 21 includes a first capacitor Cst1.
  • the gate of the third transistor T3 is connected;
  • the first reset sub-circuit 61 includes a first transistor T1, the gate of the first transistor T1 is connected to the reset signal line RE, the first transistor T1 One pole is connected to the first power line VDD, the second pole of the first transistor T1 is connected to the gate of the third transistor T3;
  • the compensation sub-circuit 4 includes a second transistor T2, The gate of the transistor T2 is connected to the first gate line GA1, the first electrode of the second transistor T2 is connected to the first electrode of the third transistor T3, and the second electrode of the second transistor T2 is connected to the first electrode of the third transistor T3.
  • the gate of the third transistor T3 is connected;
  • the data writing sub-circuit 5 includes a fourth transistor T4, the gate of the fourth transistor T4 is connected to the second gate line GA2, and the fourth transistor T4
  • the first pole is connected to the data line DA, the second pole of the fourth transistor T4 is connected to the second end of the first capacitor Cst1;
  • the power control sub-circuit 3 includes a fifth transistor T5,
  • the gate of the fifth transistor T5 is connected to the light emission control signal line EM, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first power line VDD.
  • the first pole of the three transistor T3 is connected; the first control sub-circuit 71 includes an eighth transistor T8, the gate of the eighth transistor T8 is connected to the first gate line GA1, and the first electrode of the eighth transistor T8 One pole is connected to the initialization signal line Init, and the second pole of the eighth transistor T8 is connected to the second end of the driving sub-circuit 1.
  • the driver sub-circuit 1 includes a third transistor T3, the gate of the third transistor T3 serves as the control terminal of the driver sub-circuit 1, and the first pole of the third transistor T3 serves as the driver.
  • the first terminal of the circuit 1 and the second terminal of the third transistor T3 serve as the second terminal of the driving sub-circuit 1.
  • the first transistor T1, the third transistor T3, and the seventh transistor T7 are turned on, and the second transistor T2 and the fourth transistor T4 are turned on.
  • the fifth transistor T5, the sixth transistor T6, the eighth transistor T8 and the ninth transistor T9 are all off.
  • the second transistor T2, the third transistor T3, the eighth transistor T8, and the ninth transistor T9 are all turned on, and the first The transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all turned off.
  • the fourth transistor T4 is turned on, and the remaining transistors are all turned off.
  • the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are all turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are all turned off.
  • each of the transistors included can be selected as an N-type transistor, and the N-type transistor has the advantages of low hysteresis and compatibility with oxide thin film transistor design.
  • An embodiment of the present disclosure also provides a display device, which includes the pixel driving circuit provided in the foregoing embodiment.
  • the driving current I has nothing to do with the threshold voltage Vth corresponding to the driving sub-circuit, and the power supply voltage Vd; the threshold voltage Vth drift and the influence of the power supply voltage Vd on the driving current I are eliminated, effectively improving The uniformity of the driving current is ensured, and the uniformity of the display brightness of the display device is ensured. Therefore, when the display device provided by the embodiment of the present disclosure includes the above-mentioned pixel driving circuit, it also has the above-mentioned beneficial effects, which will not be repeated here.
  • the display device may be any product or component with a display function, such as a TV, a monitor, a digital photo frame, a mobile phone, a tablet computer, and the like.
  • the display device includes a plurality of pixel drive circuits distributed in an array, and the plurality of pixel drive circuits are divided into multiple rows of pixel drive circuits; the display device further includes a gate A pole driving circuit, a light emitting signal control circuit, a plurality of first gate lines GA1, a plurality of second gate lines GA2, a plurality of reset signal lines RE, and a plurality of light emitting control signal lines EM;
  • the gate driving circuit includes a plurality of first shift register units Gate GOA corresponding to a plurality of rows of pixel driving circuits one-to-one; the light-emitting signal control circuit includes a plurality of second shift register units;
  • the plurality of first gate lines GA1 are in one-to-one correspondence with the plurality of first shift register units Gate GOA and the plurality of rows of pixel driving circuits, and each pixel driving circuit included in each row of pixel driving circuits corresponds to
  • the first gate line GA1 is connected to the output terminal of the corresponding first shift register unit Gate GOA;
  • the plurality of second gate lines GA2 correspond to the plurality of rows of pixel driving circuits one-to-one, and each pixel driving circuit included in each row of pixel driving circuits is respectively connected to the corresponding second gate line GA2, and the pixel driving circuit of the current row (
  • the second gate line GA2 corresponding to A) in FIG. 12 is connected to the output terminal of the first shift register unit Gate GOA corresponding to the next row of pixel driving circuits (C in FIG. 12);
  • the multiple reset signal lines RE correspond to the multiple rows of pixel drive circuits one-to-one, and each pixel drive circuit included in each row of pixel drive circuits is respectively connected to the corresponding reset signal line RE, and the current row of pixel drive circuits (as shown in the figure) 12 A) the corresponding reset signal line RE is connected to the output terminal of the first shift register unit Gate GOA corresponding to the pixel driving circuit of the adjacent previous row (B in FIG. 12);
  • the multiple light emission control signal lines EM correspond to the multiple rows of pixel drive circuits one-to-one, each pixel drive circuit included in each row of pixel drive circuits is connected to a corresponding light emission control signal line EM, and each second shift The output terminal of the register unit is connected to at least one corresponding light-emitting control signal line.
  • the display device includes a plurality of the pixel driving circuits distributed in an array, the plurality of pixel driving circuits are divided into a plurality of rows of pixel driving circuits, for example, the plurality of rows of pixel driving circuits are arranged in sequence along the Y direction
  • Each row of pixel drive circuits includes a plurality of pixel drive circuits arranged in sequence along the X direction.
  • the X direction is a horizontal direction
  • the Y direction is a vertical direction.
  • At least part of the first gate line GA1, at least part of the second gate line GA2, at least part of the reset signal line RE, and at least part of the light emission control signal line EM are all along the X direction extend.
  • the gate driving circuit includes a plurality of first shift register units Gate GOA corresponding to a plurality of rows of pixel driving circuits one-to-one; the light-emitting signal control circuit includes a plurality of second shift register units EMGOA.
  • Each pixel drive circuit included in each row of pixel drive circuits multiplexes one first gate line GA1 corresponding to the row of pixel drive circuits.
  • Each pixel drive circuit included in each row of pixel drive circuits multiplexes one second gate line GA2 corresponding to the row of pixel drive circuits.
  • Each pixel drive circuit included in each row of pixel drive circuits multiplexes one reset signal line RE corresponding to the row of pixel drive circuits.
  • Each pixel drive circuit included in each row of pixel drive circuits multiplexes one light emission control signal line EM corresponding to the row of pixel drive circuits.
  • Each pixel drive circuit included in each row of pixel drive circuits is respectively connected to the corresponding second gate line GA2, and the signal transmitted by the second gate line GA2 corresponding to the pixel drive circuit in the current row is connected to the adjacent pixel drive circuit in the next row.
  • the signals transmitted by the corresponding first gate line GA1 are the same. Therefore, the second gate line GA2 corresponding to the pixel driving circuit in the current row and the first gate line GA1 corresponding to the adjacent pixel driving circuit in the next row can be both The output terminal of the first shift register unit corresponding to the pixel driving circuit of the next adjacent row is connected.
  • Each pixel drive circuit included in each row of pixel drive circuits is respectively connected to a corresponding reset signal line RE, and the reset signal line RE corresponding to the pixel drive circuit of the current row is connected to the first gate line corresponding to the pixel drive circuit of the adjacent previous row.
  • the signals transmitted by GA1 are the same. Therefore, the reset signal line RE corresponding to the pixel drive circuit of the current row and the first gate line GA1 corresponding to the pixel drive circuit of the adjacent previous row can be corresponded to the pixel drive circuit of the adjacent previous row.
  • the output terminal of the first shift register unit is connected.
  • the multiple light emission control signal lines EM correspond to the multiple rows of pixel drive circuits one-to-one, each pixel drive circuit included in each row of pixel drive circuits is respectively connected to a corresponding light emission control signal line, and each second shift register The output terminal of the unit is connected to at least one corresponding light-emitting control signal line. It should be noted that when each second shift register unit corresponds to multiple light-emitting control signal lines, the multiple light-emitting control signal lines are multiple light-emitting control signal lines arranged adjacently, and each light-emitting control signal line only corresponds to A second shift register unit.
  • the first gate line GA1 corresponding to the pixel drive circuit of the current row may be set to input a first scan signal, and the first scan signal can be multiplexed into the pixel drive circuit of the next row.
  • the reset signal input by the connected reset signal line RE it can also be set that the first scan signal is multiplexed into the second scan signal input by the second gate line GA2 correspondingly connected to the pixel driving circuit of the adjacent previous row; therefore, the above-mentioned embodiment
  • only gateGOA and EMGOA need to be provided to provide corresponding signals for the pixel drive circuit, which requires fewer control signals and is compatible with existing GOA designs.
  • the embodiment of the present disclosure also provides a driving method of the pixel driving circuit, which is applied to the pixel driving circuit provided in the above-mentioned embodiment, and the driving method includes: in each working cycle,
  • the first power line VDD is input with the power supply voltage Vd, and under the control of the reset signal line RE, the first reset sub-circuit 61 controls to turn on the first power line VDD and the control terminal of the driving sub-circuit 1 the connection between;
  • the first reset sub-circuit 61 controls to disconnect the connection between the first power line VDD and the control terminal of the driving sub-circuit 1; an initialization signal The line Init inputs the initialization voltage Vinit.
  • the first control sub-circuit 71 controls to turn on the connection between the initialization signal line Init and the second end of the driving sub-circuit 1, compensating the sub-circuit
  • the circuit 4 controls and turns on the connection between the control terminal of the driver sub-circuit 1 and the first terminal of the driver sub-circuit 1, so that the first terminal and the second terminal of the driver sub-circuit 1 are electrically conductive. ON becomes OFF, so that the potential of the control terminal of the driving sub-circuit 1 changes from Vd to Vinit+Vth, where Vth is the threshold voltage corresponding to the driving sub-circuit 1;
  • the first control sub-circuit 71 controls the disconnection between the initialization signal line Init and the second end of the driving sub-circuit 1, and the compensation sub-circuit
  • the circuit 4 controls the disconnection of the connection between the control terminal of the driving sub-circuit 1 and the first terminal of the driving sub-circuit 1; the data line DA inputs the data voltage Vdata, and under the control of the second gate line GA2, the data is written
  • the input sub-circuit 5 controls to turn on the connection between the data line DA and the second end of the first storage sub-circuit 21, so that the potential of the second end of the first storage sub-circuit 21 becomes Vdata, the The potential of the control terminal of the driving sub-circuit 1 changes correspondingly under the bootstrap action of the first storage sub-circuit 21;
  • the power signal input terminal is input with a power voltage Vdd
  • the power control sub-circuit 3 controls to conduct the first power line VDD and the driver
  • the data writing sub-circuit 5 controls the disconnection between the data line DA and the second end of the first storage sub-circuit 21
  • the driver sub-circuit 1 controls the connection between the first terminal of the driver sub-circuit 1 and the second terminal of the driver sub-circuit 1 to drive the light-emitting element EL to emit light.
  • the driving current I has nothing to do with the threshold voltage Vth corresponding to the driving sub-circuit and the power supply voltage Vd; therefore, the driving method provided by the embodiment of the present disclosure is used to drive the pixel.
  • the circuit eliminates the influence of the threshold voltage Vth drift and the power supply voltage Vd on the driving current I, effectively improving the uniformity of the driving current, and ensuring the uniformity of the display brightness of the display device.
  • the pixel driving circuit further includes a light-emitting control sub-circuit 8, and the second end of the driving sub-circuit 1 is connected to the light-emitting element EL through the light-emitting control sub-circuit 8; the light-emitting control sub-circuit The circuit 8 is respectively connected to the light-emitting control signal line EM, the second end of the driving sub-circuit 1 and the light-emitting element EL; the pixel driving circuit also includes a second storage sub-circuit 22, the second storage sub-circuit The first end of the circuit 22 is connected to the control end of the driving sub-circuit 1, and the second end of the second storage sub-circuit 22 is connected to the light-emitting element EL;
  • the driving method further includes:
  • the light emission control sub-circuit 8 controls to turn off the drive sub-circuit 1 The connection between the second end of and the light-emitting element EL;
  • the light-emission control sub-circuit 8 controls to turn on the connection between the second end of the driving sub-circuit 1 and the light-emitting element EL,
  • the potential of the control terminal of the driving sub-circuit 1 changes correspondingly under the bootstrap action of the second storage sub-circuit 22.
  • the light-emitting element EL emits light, and the potential of the N4 node jumps from Vinit to Voled.
  • Voled is the operating voltage of the light-emitting element EL.
  • the potential of the N1 node changes from Vinit. +Vth+Vdata jumps to Vinit+Vth+Vdata+(Voled-Vinit), that is, the potential of the N1 node becomes Vth+Vdata+Voled.
  • the influence of the negative power supply signal input from the negative power supply signal line VSS to which the light-emitting element EL is connected to the driving current I is also eliminated.
  • the pixel driving circuit further includes a second reset sub-circuit 62, and the second reset sub-circuit 62 is respectively connected to the reset signal line RE, the initialization signal line Init, and the light-emitting element EL. ;
  • the pixel driving circuit controls to turn on the connection between the initialization signal line Init and the light emitting element EL;
  • the pixel driving circuit controls to disconnect the initialization signal line Init from the Connection between the light-emitting elements EL.
  • the second reset sub-circuit 62 controls to conduct between the initialization signal line Init and the anode of the light emitting element EL. To realize resetting the anode of the light-emitting element EL.
  • the pixel driving circuit further includes a second control sub-circuit 72, the second control sub-circuit 72 is respectively connected with the first gate line GA1, the initialization signal line Init and the first storage sub-circuit The second end of 21 is connected;
  • the second control sub-circuit 72 controls to turn off the initialization signal line Init Connection with the second end of the first storage sub-circuit 21;
  • the second control sub-circuit 72 controls to turn on between the initialization signal line Init and the second end of the first storage sub-circuit 21 The connection between.
  • the second control sub-circuit 72 controls to turn on the initialization signal line Init and the first storage line.
  • the connection between the second ends of the sub-circuit 21 writes and maintains the potential of the N2 node at Vinit.
  • the potential change of the N2 node is Vdata-Vinit, and under the bootstrap action of the first storage sub-circuit 21, the potential of the N1 node becomes Vinit+Vth+Vdata-Vinit, namely: Vth +Vdata.
  • the above arrangement of the pixel driving circuit further includes a second control sub-circuit 72, so that the N2 node has a stable potential before the data writing period P3 starts, which is more conducive to the writing of data signals.

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Abstract

本公开提供一种像素驱动电路及其驱动方法、显示装置。该像素驱动电路中，第一存储子电路的第一端与控制端连接；电源控制子电路分别与发光控制信号线，第一电源线和驱动子电路的第一端连接；补偿子电路分别与第一栅线、驱动子电路的控制端和驱动子电路的第一端连接；数据写入子电路与第一存储子电路的第二端连接；第一复位子电路分别与复位信号线、第一电源线和驱动子电路的控制端连接；第一控制子电路分别与第一栅线、初始化信号线和驱动子电路的第二端连接。

Description

一种像素驱动电路及其驱动方法、显示装置
相关申请的交叉引用
本申请主张在2020年05月26日在中国提交的中国专利申请号No.202010455157.9的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素驱动电路及其驱动方法、显示装置。
背景技术
AMOLED(Active-matrix Organic Light-Emitting Diode，有源矩阵有机发光二极管)显示器件具有自发光、超薄、反应速度快、对比度高、视角广等诸多优点，是目前受到广泛关注的一种显示器件。
这种AMOLED显示器件包括多个像素驱动电路和多个发光元件，像素驱动电路用于驱动对应的发光元件发光，从而实现AMOLED显示器件的显示功能。但是现有的像素驱动电路存在所需要的控制信号复杂，以及像素驱动电路中驱动晶体管存在由于阈值电压漂移导致的显示器件的显示亮度均匀性较差的问题。
发明内容
本公开的目的在于提供一种像素驱动电路及其驱动方法、显示装置。
为了实现上述目的，本公开提供如下技术方案：
本公开的第一方面提供一种像素驱动电路，用于驱动发光元件，包括：
驱动子电路，所述驱动子电路用于在其控制端的控制下，控制导通或断开该驱动子电路的第一端与该驱动子电路的第二端之间的连接，所述驱动子电路的第二端与所述发光元件连接；
第一存储子电路，所述第一存储子电路的第一端与所述控制端连接；
电源控制子电路，分别与发光控制信号线，第一电源线和所述驱动子电路的第一端连接，用于在所述发光控制信号线的控制下，控制导通或断开所述第一电源线与所述驱动子电路的第一端之间的连接；
补偿子电路，分别与第一栅线、所述驱动子电路的控制端和所述驱动子电路的第一端连接，用于在所述第一栅线的控制下，控制导通或断开所述驱动子电路的控制端和所述驱动子电路的第一端之间的连接；
数据写入子电路，分别与第二栅线、数据线和所述第一存储子电路的第二端连接，用于在所述第二栅线的控制下，控制导通或断开所述数据线与所述第一存储子电路的第二端之间的连接；
第一复位子电路，分别与复位信号线、所述第一电源线和所述驱动子电路的控制端连接，用于在所述复位信号线的控制下，控制导通或断开所述第一电源线与所述驱动子电路的控制端之间的连接；
第一控制子电路，分别与所述第一栅线、初始化信号线和所述驱动子电路的第二端连接，用于在所述第一栅线的控制下，控制导通和断开所述初始化信号线与所述驱动子电路的第二端之间的连接。
可选的，所述像素驱动电路还包括发光控制子电路，所述驱动子电路的第二端通过所述发光控制子电路与所述发光元件连接；
所述发光控制子电路分别与所述发光控制信号线、所述驱动子电路的第二端和所述发光元件连接，用于在所述发光控制信号线的控制下，控制导通或断开所述驱动子电路的第二端与所述发光元件之间的连接。
可选的，所述像素驱动电路还包括：
第二存储子电路，所述第二存储子电路的第一端与所述驱动子电路的控制端连接，所述第二存储子电路的第二端与所述发光元件连接。
可选的，所述发光控制子电路包括：
第六晶体管，所述第六晶体管的栅极与所述发光控制信号线连接，所述第六晶体管的第一极与所述驱动子电路的第二端连接，所述第六晶体管的第二极与所述发光元件连接。
可选的，所述像素驱动电路还包括：
第二复位子电路，分别与所述复位信号线、所述初始化信号线和所述发光元件连接，用于在所述复位信号线的控制下，控制导通或断开所述初始化信号线与所述发光元件之间的连接。
可选的，所述第二复位子电路包括第七晶体管，所述第七晶体管的栅极与所述复位信号线连接，所述第七晶体管的第一极与所述初始化信号线连接，所述第七晶体管的第二极与所述发光元件连接。
可选的，所述像素驱动电路还包括：
第二控制子电路，分别与所述第一栅线、初始化信号线和所述第一存储子电路的第二端连接，用于在所述第一栅线的控制下，控制导通或断开所述初始化信号线与所述第一存储子电路的第二端之间的连接。
可选的，所述第二控制子电路包括第九晶体管，所述第九晶体管的栅极与所述第一栅线连接，所述第九晶体管的第一极与所述初始化信号线连接，所述第九晶体管的第二极与所述第一存储子电路的第二端连接。
可选的，所述驱动子电路包括第三晶体管；
所述第一存储子电路包括第一电容，所述第一电容的第一端与所述第三晶体管的栅极连接；
所述第一复位子电路包括第一晶体管，所述第一晶体管的栅极与所述复位信号线连接，所述第一晶体管的第一极与所述第一电源线连接，所述第一晶体管的第二极与所述第三晶体管的栅极连接；
所述补偿子电路包括第二晶体管，所述第二晶体管的栅极与所述第一栅线连接，所述第二晶体管的第一极与所述第三晶体管的第一极连接，所述第二晶体管的第二极与所述第三晶体管的栅极连接；
所述数据写入子电路包括第四晶体管，所述第四晶体管的栅极与所述第二栅线连接，所述第四晶体管的第一极与所述数据线连接，所述第四晶体管的第二极与所述第一电容的第二端连接；
所述电源控制子电路包括第五晶体管，所述第五晶体管的栅极与所述发光控制信号线连接，所述第五晶体管的第一极与所述第一电源线连接，所述第五晶体管的第二极与所述第三晶体管的第一极连接；
所述第一控制子电路包括第八晶体管，所述第八晶体管的栅极与所述第 一栅线连接，所述第八晶体管的第一极与所述初始化信号线连接，所述第八晶体管的第二极与所述驱动子电路的第二端连接。
基于上述像素驱动电路的技术方案，本公开的第二方面提供一种显示装置，包括上述像素驱动电路。
可选的，所述显示装置包括阵列分布的多个所述像素驱动电路，多个所述像素驱动电路划分为多行像素驱动电路；所述显示装置还包括栅极驱动电路、发光信号控制电路，多条第一栅线、多条第二栅线、多条复位信号线和多条发光控制信号线；
所述栅极驱动电路包括与多行像素驱动电路一一对应的多个第一移位寄存器单元；
所述发光信号控制电路包括多个第二移位寄存器单元；
所述多条第一栅线与所述多个第一移位寄存器单元和所述多行像素驱动电路均一一对应，每行像素驱动电路中包括的各像素驱动电路分别与对应的第一栅线连接，所述第一栅线与对应的第一移位寄存器单元的输出端连接；
所述多条第二栅线与所述多行像素驱动电路一一对应，每行像素驱动电路中包括的各像素驱动电路分别与对应的第二栅线连接，当前行像素驱动电路对应的所述第二栅线与相邻的下一行像素驱动电路对应的第一移位寄存器单元的输出端连接；
所述多条复位信号线与所述多行像素驱动电路一一对应，每行像素驱动电路中包括的各像素驱动电路分别与对应的复位信号线连接，当前行像素驱动电路对应的复位信号线与相邻的上一行像素驱动电路对应的第一移位寄存器单元的输出端连接；
所述多条发光控制信号线与所述多行像素驱动电路一一对应，每行像素驱动电路中包括的各像素驱动电路分别与对应的发光控制信号线连接，每个第二移位寄存器单元的输出端与对应的至少一条所述发光控制信号线连接。
基于上述像素驱动电路的技术方案，本公开的第三方面提供一种像素驱动电路的驱动方法，应用于上述像素驱动电路，所述驱动方法包括：在每一工作周期，
在复位时段，第一电源线输入电源电压Vd，在复位信号线的控制下，第 一复位子电路控制导通所述第一电源线与所述驱动子电路的控制端之间的连接；
在阈值补偿时段，在所述复位信号线的控制下，第一复位子电路控制断开所述第一电源线与所述驱动子电路的控制端之间的连接；初始化信号线输入初始化电压Vinit，在第一栅线的控制下，第一控制子电路控制导通所述初始化信号线与所述驱动子电路的第二端之间的连接，补偿子电路控制导通所述驱动子电路的控制端和所述驱动子电路的第一端之间的连接，以使所述驱动子电路的第一端与第二端之间由导通变为截止，使得所述驱动子电路的控制端的电位由Vd变为Vinit+Vth，Vth为所述驱动子电路对应的阈值电压；
在数据写入时段，在第一栅线的控制下，第一控制子电路控制断开所述初始化信号线与所述驱动子电路的第二端之间的连接，补偿子电路控制断开所述驱动子电路的控制端和所述驱动子电路的第一端之间的连接；数据线输入数据电压Vdata，在第二栅线的控制下，数据写入子电路控制导通所述数据线与所述第一存储子电路的第二端之间的连接，使所述第一存储子电路的第二端的电位变为Vdata，所述驱动子电路的控制端的电位在所述第一存储子电路的自举作用下相应改变；
在发光时段，所述电源信号输入端输入电源电压Vdd，在所述发光控制信号线的控制下，所述电源控制子电路控制导通所述第一电源线与所述驱动子电路的第一端之间的连接，在第二栅线的控制下，数据写入子电路控制断开所述数据线与所述第一存储子电路的第二端之间的连接，所述驱动子电路在其控制端的控制下，控制导通该驱动子电路的第一端与该驱动子电路的第二端之间的连接，以驱动发光元件发光。
可选的，所述像素驱动电路还包括发光控制子电路，所述驱动子电路的第二端通过所述发光控制子电路与所述发光元件连接；所述发光控制子电路分别与所述发光控制信号线、所述驱动子电路的第二端和所述发光元件连接；所述像素驱动电路还包括第二存储子电路，所述第二存储子电路的第一端与所述驱动子电路的控制端连接，所述第二存储子电路的第二端与所述发光元件连接；
所述驱动方法还包括：
在所述复位时段、所述阈值补偿时段和所述数据写入时段，在所述发光控制信号线的控制下，所述发光控制子电路控制断开所述驱动子电路的第二端与所述发光元件之间的连接；
在所述发光时段，在所述发光控制信号线的控制下，所述发光控制子电路控制导通所述驱动子电路的第二端与所述发光元件之间的连接，所述驱动子电路的控制端的电位在所述第二存储子电路的自举作用下相应改变。
可选的，所述像素驱动电路还包括第二复位子电路，所述第二复位子电路分别与所述复位信号线、所述初始化信号线和所述发光元件连接；
在所述复位时段，在所述复位信号线的控制下，所述像素驱动电路控制导通所述初始化信号线与所述发光元件之间的连接；
在所述阈值补偿时段、所述数据写入时段和所述发光时段，在所述复位信号线的控制下，所述像素驱动电路控制断开所述初始化信号线与所述发光元件之间的连接。
可选的，所述像素驱动电路还包括第二控制子电路，所述第二控制子电路分别与所述第一栅线、初始化信号线和所述第一存储子电路的第二端连接；
在所述复位时段、所述数据写入时段和所述发光时段，在所述第一栅线的控制下，所述第二控制子电路控制断开所述初始化信号线与所述第一存储子电路的第二端之间的连接；
所述阈值补偿时段，在所述第一栅线的控制下，所述第二控制子电路控制导通所述初始化信号线与所述第一存储子电路的第二端之间的连接。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例提供的像素驱动电路的第一结构示意图；
图2为本公开实施例提供的像素驱动电路的第二结构示意图；
图3为本公开实施例提供的像素驱动电路的第三结构示意图；
图4为本公开实施例提供的像素驱动电路的第四结构示意图；
图5为本公开实施例提供的像素驱动电路的第五结构示意图；
图6为本公开实施例提供的像素驱动电路的第一电路示意图；
图7为本公开实施例提供的像素驱动电路的工作时序图；
图8为本公开实施例提供的像素驱动电路在复位时段的工作示意图；
图9为本公开实施例提供的像素驱动电路在阈值补偿时段的工作示意图；
图10为本公开实施例提供的像素驱动电路在数据写入时段的工作示意图；
图11为本公开实施例提供的像素驱动电路在发光时段的工作示意图；
图12为本公开实施例提供的Gate GOA的连接示意图。
具体实施方式
为了进一步说明本公开实施例提供的像素驱动电路及其驱动方法、显示装置，下面结合说明书附图进行详细描述。
请参阅图1，本公开实施例提供了一种像素驱动电路，用于驱动发光元件EL，所述像素驱动电路包括：
驱动子电路1，所述驱动子电路1用于在其控制端的控制下，控制导通或断开该驱动子电路1的第一端与该驱动子电路1的第二端之间的连接，所述驱动子电路1的第二端与所述发光元件EL连接；
第一存储子电路21，所述第一存储子电路21的第一端与所述控制端连接；
电源控制子电路3，分别与发光控制信号线EM，第一电源线VDD和所述驱动子电路1的第一端连接，用于在所述发光控制信号线EM的控制下，控制导通或断开所述第一电源线VDD与所述驱动子电路1的第一端之间的连接；
补偿子电路4，分别与第一栅线GA1、所述驱动子电路1的控制端和所述驱动子电路1的第一端连接，用于在所述第一栅线GA1的控制下，控制导 通或断开所述驱动子电路1的控制端和所述驱动子电路1的第一端之间的连接；
数据写入子电路5，分别与第二栅线GA2、数据线DA和所述第一存储子电路21的第二端连接，用于在所述第二栅线GA2的控制下，控制导通或断开所述数据线DA与所述第一存储子电路21的第二端之间的连接；
第一复位子电路61，分别与复位信号线RE、所述第一电源线VDD和所述驱动子电路1的控制端连接，用于在所述复位信号线RE的控制下，控制导通或断开所述第一电源线VDD与所述驱动子电路1的控制端之间的连接；
第一控制子电路71，分别与所述第一栅线GA1、初始化信号线Init和所述驱动子电路1的第二端连接，用于在所述第一栅线GA1的控制下，控制导通和断开所述初始化信号线Init与所述驱动子电路1的第二端之间的连接。
具体的，所述像素驱动电路应用于显示装置，显示装置包括基底，阵列分布在所述基底上的多个像素驱动电路，以及位于所述多个像素驱动电路背向所述基底的一侧，且与所述多个像素驱动电路一一对应的发光元件EL。示例性的，所述发光元件EL具体包括沿远离所述基底的方向上依次层叠设置的阳极、发光功能层和阴极，发光元件EL的阳极能够与对应的所述像素驱动电路连接，接收对应的所述像素驱动电路提供的驱动信号，所述阴极能够与显示装置中的负电源信号线VSS连接，接收所述负电源信号线VSS输入的负电源信号，发光功能层用于在所述阳极和所述阴极的共同作用下发光。
需要说明，所述初始化信号线Init输入的初始化信号，所述第一电源线VDD输入的第一电源信号，以及所述负电源信号线VSS输入的负电源信号均为恒压信号，其中初始化信号的电位Vinit小于负电源信号的电位，负电源信号的电位小于第一电源信号的电位Vd。示例性的，Vinit取-3V，负电源信号的电位取-2.4V，Vd取4.6V。
请参阅图1、图6～图11，上述像素驱动电路在一个驱动周期的工作过程为：
在复位时段P1，如图7和图8所示，第一电源线VDD输入电源电压Vd，在复位信号线RE输入的复位信号的控制下，第一复位子电路61控制导通所述第一电源线VDD与所述驱动子电路1的控制端之间的连接，使所述驱动子 电路1的控制端(即N1节点)的电位变为Vd，实现对所述驱动子电路1的控制端复位。需要说明，图8～图11中的带箭头的虚线代表信号走向。
在阈值补偿时段P2，如图7和图9所示，在所述复位信号线RE输入的复位信号的控制下，第一复位子电路61控制断开所述第一电源线VDD与所述驱动子电路1的控制端之间的连接；初始化信号线Init输入初始化电压Vinit，在第一栅线GA1输入的第一扫描信号的控制下，第一控制子电路71控制导通所述初始化信号线Init与所述驱动子电路1的第二端(即N3节点)之间的连接，使所述驱动子电路1的第二端的电位变为Vinit；同时，在第一栅线GA1输入的第一扫描信号的控制下，补偿子电路4控制导通所述驱动子电路1的控制端和所述驱动子电路1的第一端之间的连接，由于在复位时段P1所述驱动子电路1的控制端的电位变为Vd，使得所述驱动子电路1能够将其包括的第一端和第二端导通连接，并使得所述驱动子电路1的第一端和第二端之间的连接关系经历由导通变为截止的过程，实现对N1节点的充电，使得N1节点的电位由Vd最终变为Vinit+Vth，Vth为所述驱动子电路1对应的阈值电压。
在数据写入时段P3，如图7和图10所示，在第一栅线GA1输入的第一扫描信号的控制下，第一控制子电路71控制断开所述初始化信号线Init与所述驱动子电路1的第二端之间的连接；在第一栅线GA1输入的第一扫描信号的控制下，补偿子电路4控制断开所述驱动子电路1的控制端和所述驱动子电路1的第一端之间的连接；数据线DA输入数据电压Vdata，在第二栅线GA2输入的第二扫描信号的控制下，数据写入子电路5控制导通所述数据线DA与所述第一存储子电路21的第二端之间的连接，使所述第一存储子电路21的第二端(即N2节点)的电位变为Vdata，由于在数据写入时段P3，所述驱动子电路1的控制端处于悬空状态，所述驱动子电路1的控制端的电位在所述第一存储子电路21的自举作用下相应改变。示例性的，所述第一存储子电路21的第二端的初始电位为0，则在写入数据电压Vdata之后，所述第一存储子电路21的第二端的电位的变化量为Vdata，在所述第一存储子电路21的自举作用下，所述驱动子电路1的控制端的电位相应变为Vinit+Vth+Vdata。
在发光时段P4，如图7和图11所示，所述电源信号输入端输入电源电压Vdd，在所述发光控制信号线EM输入的发光控制信号的控制下，所述电源控制子电路3控制导通所述第一电源线VDD与所述驱动子电路1的第一端之间的连接；在第二栅线GA2写入的第二扫描信号的控制下，数据写入子电路5控制断开所述数据线DA与所述第一存储子电路21的第二端之间的连接；所述驱动子电路1在其控制端的控制下，控制导通该驱动子电路1的第一端与该驱动子电路1的第二端之间的连接，以驱动发光元件EL发光。
根据上述像素驱动电路的具体结构和像素驱动电路在一个驱动周期的工作过程可知，本公开实施例提供的像素驱动电路中，在阈值补偿时段P2，实现对N1节点的充电，使得N1节点的电位由Vd变为Vinit+Vth；同时控制导通所述初始化信号线Init与所述驱动子电路1的第二端(即N3节点)之间的连接，使所述驱动子电路1的第二端的电位变为Vinit；在数据写入时段P3将数据电压Vdata写入，使所述驱动子电路1的控制端的电位变为Vinit+Vth+Vdata；在发光时段P4，所述电源控制子电路3控制导通所述第一电源线VDD与所述驱动子电路1的第一端之间的连接，使得所述驱动子电路1在其控制端的控制下，控制导通该驱动子电路1的第一端与该驱动子电路1的第二端之间的连接，此时所述驱动子电路1的控制端和第二端之间的电压Vgs为：
Vgs＝Vinit+Vth+Vdata-Voled   公式(1)
Voled为发光元件EL的工作电压，驱动子电路1将其第一端和第二端导通并工作在饱和状态时产生的驱动电流I为：
I＝k(Vgs-Vth) 2    公式(2)
将公式(1)代入公式(2)得到：
I＝k(Vinit+Vdata-Voled) 2      公式(3)
公式(3)中，k为与驱动子电路1中包括的晶体管的宽长比以及迁移率相关的常数。
由公式(3)可知驱动电流I与驱动子电路对应的阈值电压Vth，以及电源电压Vd均没有关系；因此，本公开实施例提供的像素驱动电路中，消除了阈值电压Vth漂移和电源电压Vd对驱动电流I的影响，有效提升了驱动电 流的均匀性，保证了显示器件显示亮度的均匀性。
另外，在将本公开实施例提供的像素驱动电路应用于显示装置中时，显示装置包括阵列分布的多个像素驱动电路，可设置当前行像素驱动电路对应连接的所述第一栅线GA1输入第一扫描信号，该第一扫描信号能够复用为相邻的下一行像素驱动电路对应连接的复位信号线RE输入的复位信号；还可设置该第一扫描信号复用为相邻的上一行像素驱动电路对应连接的第二栅线GA2输入的第二扫描信号；因此，在将本公开实施例提供的像素驱动电路应用于显示装置中时，所述像素驱动电路仅需要gateGOA和EMGOA来提供相应的信号，所需要的控制信号较少，且同时能够兼容现有的GOA设计。
如图2和图6所示，在一些实施例中，所述像素驱动电路还包括发光控制子电路8，所述驱动子电路1的第二端通过所述发光控制子电路8与所述发光元件EL连接；所述发光控制子电路8分别与所述发光控制信号线EM、所述驱动子电路1的第二端和所述发光元件EL连接，用于在所述发光控制信号线EM的控制下，控制导通或断开所述驱动子电路1的第二端与所述发光元件EL之间的连接。
具体地，如图7和图11所示，在发光时段P4，在发光控制信号线EM的控制下，发光控制子电路8控制导通所述驱动子电路1的第二端与所述发光元件EL之间的连接。
如图7～图10所示，在复位时段P1、阈值补偿时段P2和数据写入时段P3，在发光控制信号线EM的控制下，发光控制子电路8控制断开所述驱动子电路1的第二端与所述发光元件EL之间的连接，从而很好的避免了在复位时段P1、阈值补偿时段P2和数据写入时段P3所述发光元件EL异常发光。
如图3和图6所示，在一些实施例中，所述像素驱动电路还包括：第二存储子电路22，所述第二存储子电路22的第一端与所述驱动子电路1的控制端连接，所述第二存储子电路22的第二端与所述发光元件EL连接。
示例性的，所述第二存储子电路22包括第二电容Cst2，所述第二电容Cst2的第一端与所述驱动子电路1的控制端连接，所述第二电容Cst2的第二端与所述发光元件EL连接。
如图11所示，在发光时段P4，发光元件EL发光，N4节点的电位由Vinit 跳变至Voled，Voled为发光元件EL的工作电压，同时由于所述第二存储子电路22的耦合作用，N1节点的电位由Vinit+Vth+Vdata跳变至Vinit+Vth+Vdata+(Voled-Vinit)，即N1节点的电位变为Vth+Vdata+Voled。
此时所述驱动子电路1的控制端和第二端之间的电压Vgs为：
Vgs＝Vth+Vdata+Voled-Voled＝Vth+Vdata      公式(4)
Voled为发光元件EL的工作电压，驱动子电路1将其第一端和第二端导通并工作在饱和状态时产生的驱动电流I为：
I＝k(Vgs-Vth) 2＝k(Vdata) 2    公式(5)
由公式(5)可知驱动电流I与发光元件EL的工作电压Voled没有关系；因此，本公开实施例提供的像素驱动电路中，消除了Voled对驱动电流I的影响，保证了显示器件显示亮度的均匀性。另外，本公开实施例提供的像素驱动电路也消除了发光元件EL连接的负电源信号线VSS输入的负电源信号对驱动电流I的影响。
如图6所示，在一些实施例中，所述发光控制子电路8包括第六晶体管T6，所述第六晶体管T6的栅极与所述发光控制信号线EM连接，所述第六晶体管T6的第一极与所述驱动子电路1的第二端连接，所述第六晶体管T6的第二极与所述发光元件EL连接。
具体地，如图7和图11所示，在发光时段P4，在发光控制信号线EM的控制下，第六晶体管T6导通，从而控制导通所述驱动子电路1的第二端与所述发光元件EL之间的连接。
如图7～图10所示，在复位时段P1、阈值补偿时段P2和数据写入时段P3，在发光控制信号线EM的控制下，第六晶体管T6截止，从而控制断开所述驱动子电路1的第二端与所述发光元件EL之间的连接，从而很好的避免了在复位时段P1、阈值补偿时段P2和数据写入时段P3所述发光元件EL异常发光。
如图4和图6所示，在一些实施例中，所述像素驱动电路还包括：第二复位子电路62，第二复位子电路62分别与所述复位信号线RE、所述初始化信号线Init和所述发光元件EL连接，用于在所述复位信号线RE的控制下，控制导通或断开所述初始化信号线Init与所述发光元件EL之间的连接。
如图7和图8所示，在复位时段P1，在所述复位信号线RE的控制下，第二复位子电路62控制导通所述初始化信号线Init与所述发光元件EL的阳极之间的连接，实现对所述发光元件EL的阳极复位。
如图7、图9～图11所示，在阈值补偿时段P2、数据写入时段P3和发光时段P4，第二复位子电路62控制断开所述初始化信号线Init与所述发光元件EL的阳极之间的连接。
如图6所示，在一些实施例中，所述第二复位子电路62包括第七晶体管T7，所述第七晶体管T7的栅极与所述复位信号线RE连接，所述第七晶体管T7的第一极与所述初始化信号线Init连接，所述第七晶体管T7的第二极与所述发光元件EL连接。
如图7和图8所示，在复位时段P1，在所述复位信号线RE的控制下，第七晶体管T7导通，控制导通所述初始化信号线Init与所述发光元件EL的阳极之间的连接，实现对所述发光元件EL的阳极复位。
如图7、图9～图11所示，在阈值补偿时段P2、数据写入时段P3和发光时段P4，第七晶体管T7截止，控制断开所述初始化信号线Init与所述发光元件EL的阳极之间的连接。
如图5和图6所示，在一些实施例中，所述像素驱动电路还包括：
第二控制子电路72，分别与所述第一栅线GA1、初始化信号线Init和所述第一存储子电路21的第二端连接，用于在所述第一栅线GA1的控制下，控制导通或断开所述初始化信号线Init与所述第一存储子电路21的第二端之间的连接。
具体的，如图7、图8、图10和图11所示，在复位时段P1、数据写入时段P3和发光时段P4，在所述第一栅线GA1的控制下，所述第二控制子电路72控制断开所述初始化信号线Init与所述第一存储子电路21的第二端之间的连接。
如图7和图9所示，在阈值补偿时段P2，在所述第一栅线GA1的控制下，所述第二控制子电路72控制导通所述初始化信号线Init与所述第一存储子电路21的第二端之间的连接，将N2节点的电位写入并保持在Vinit。
在数据写入时段P3，N2节点的电位变化量为Vdata-Vinit，在所述第一 存储子电路21的自举作用下，N1节点的电位变为Vinit+Vth+Vdata-Vinit，即：Vth+Vdata。
当所述像素驱动电路包括所述发光控制子电路8和所述第二存储子电路22时，在发光时段P4，在所述第二存储子电路22的作用下，N1节点的电位变为Vth+Vdata+Voled-Vinit，Vgs＝Vth+Vdata+Voled-Vinit-Voled＝Vth+Vdata-Vinit。
驱动电流I为：
I＝k(Vgs-Vth) 2＝I＝k(Vdata-Vinit) 2     公式(6)
由公式(6)可知驱动电流I与发光元件EL的工作电压Voled，驱动子电路1对应的阈值电压Vth，以及电源电压Vd均没有关系。
上述设置所述像素驱动电路还包括第二控制子电路72，使得在数据写入时段P3开始之前，N2节点具有稳定的电位，这样更有利于数据信号的写入。
如图6所示，在一些实施例中，所述第二控制子电路72包括第九晶体管T9，所述第九晶体管T9的栅极与所述第一栅线GA1连接，所述第九晶体管T9的第一极与所述初始化信号线Init连接，所述第九晶体管T9的第二极与所述第一存储子电路21的第二端连接。
如图7、图8、图10和图11所示，在复位时段P1、数据写入时段P3和发光时段P4，在所述第一栅线GA1的控制下，所述第九晶体管T9截止，控制断开所述初始化信号线Init与所述第一存储子电路21的第二端之间的连接。
如图7和图9所示，在阈值补偿时段P2，在所述第一栅线GA1的控制下，所述第九晶体管T9导通，控制导通所述初始化信号线Init与所述第一存储子电路21的第二端之间的连接，将N2节点的电位写入并保持在Vinit。
如图6所示，在一些实施例中，所述驱动子电路1包括第三晶体管T3；所述第一存储子电路21包括第一电容Cst1，所述第一电容Cst1的第一端与所述第三晶体管T3的栅极连接；所述第一复位子电路61包括第一晶体管T1，所述第一晶体管T1的栅极与所述复位信号线RE连接，所述第一晶体管T1的第一极与所述第一电源线VDD连接，所述第一晶体管T1的第二极与所述第三晶体管T3的栅极连接；所述补偿子电路4包括第二晶体管T2，所述第 二晶体管T2的栅极与所述第一栅线GA1连接，所述第二晶体管T2的第一极与所述第三晶体管T3的第一极连接，所述第二晶体管T2的第二极与所述第三晶体管T3的栅极连接；所述数据写入子电路5包括第四晶体管T4，所述第四晶体管T4的栅极与所述第二栅线GA2连接，所述第四晶体管T4的第一极与所述数据线DA连接，所述第四晶体管T4的第二极与所述第一电容Cst1的第二端连接；所述电源控制子电路3包括第五晶体管T5，所述第五晶体管T5的栅极与所述发光控制信号线EM连接，所述第五晶体管T5的第一极与所述第一电源线VDD连接，所述第五晶体管T5的第二极与所述第三晶体管T3的第一极连接；所述第一控制子电路71包括第八晶体管T8，所述第八晶体管T8的栅极与所述第一栅线GA1连接，所述第八晶体管T8的第一极与所述初始化信号线Init连接，所述第八晶体管T8的第二极与所述驱动子电路1的第二端连接。
具体地，所述驱动子电路1包括第三晶体管T3，所述第三晶体管T3的栅极作为所述驱动子电路1的控制端，所述第三晶体管T3的第一极作为所述驱动子电路1的第一端，所述第三晶体管T3的第二极作为所述驱动子电路1的第二端。
如图7和图8所示，在复位时段P1，所述第一晶体管T1、所述第三晶体管T3和所述第七晶体管T7导通，所述第二晶体管T2、所述第四晶体管T4、第五晶体管T5、第六晶体管T6、第八晶体管T8和第九晶体管T9均截止。
如图7和图9所示，在阈值补偿时段P2，所述第二晶体管T2、所述第三晶体管T3、所述第八晶体管T8和所述第九晶体管T9均导通，所述第一晶体管T1、所述第四晶体管T4、所述第五晶体管T5、所述第六晶体管T6、所述第七晶体管T7均截止。
如图7和图10所示，在数据写入时段P3，所述第四晶体管T4导通，其余晶体管均截止。
如图7和图11所示，在发光时段P4，所述第三晶体管T3、所述第五晶体管T5和所述第六晶体管T6均导通，所述第一晶体管T1、所述第二晶体管T2、所述第四晶体管T4、所述第七晶体管T7、所述第八晶体管T8和所述第九晶体管T9均截止。
上述实施例提供的像素驱动电路中，所包括的各晶体管均可选为N型晶体管，N型晶体管具有磁滞小，与氧化物薄膜晶体管设计兼容等优点。
本公开实施例还提供了一种显示装置，包括上述实施例提供的像素驱动电路。
上述实施例提供的像素驱动电路中，驱动电流I与驱动子电路对应的阈值电压Vth，以及电源电压Vd均没有关系；消除了阈值电压Vth漂移和电源电压Vd对驱动电流I的影响，有效提升了驱动电流的均匀性，保证了显示器件显示亮度的均匀性。因此，本公开实施例提供的显示装置在包括上述像素驱动电路时，同样具有上述有益效果，此处不再赘述。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
如图12所示，在一些实施例中，所述显示装置包括阵列分布的多个所述像素驱动电路，多个所述像素驱动电路划分为多行像素驱动电路；所述显示装置还包括栅极驱动电路、发光信号控制电路，多条第一栅线GA1、多条第二栅线GA2、多条复位信号线RE和多条发光控制信号线EM；
所述栅极驱动电路包括与多行像素驱动电路一一对应的多个第一移位寄存器单元Gate GOA；所述发光信号控制电路包括多个第二移位寄存器单元；
所述多条第一栅线GA1与所述多个第一移位寄存器单元Gate GOA和所述多行像素驱动电路均一一对应，每行像素驱动电路中包括的各像素驱动电路分别与对应的第一栅线GA1连接，所述第一栅线GA1与对应的第一移位寄存器单元Gate GOA的输出端连接；
所述多条第二栅线GA2与所述多行像素驱动电路一一对应，每行像素驱动电路中包括的各像素驱动电路分别与对应的第二栅线GA2连接，当前行像素驱动电路(如图12中的A)对应的所述第二栅线GA2与相邻的下一行像素驱动电路(如图12中的C)对应的第一移位寄存器单元Gate GOA的输出端连接；
所述多条复位信号线RE与所述多行像素驱动电路一一对应，每行像素驱动电路中包括的各像素驱动电路分别与对应的复位信号线RE连接，当前行像素驱动电路(如图12中的A)对应的复位信号线RE与相邻的上一行像 素驱动电路(如图12中的B)对应的第一移位寄存器单元Gate GOA的输出端连接；
所述多条发光控制信号线EM与所述多行像素驱动电路一一对应，每行像素驱动电路中包括的各像素驱动电路分别与对应的发光控制信号线EM连接，每个第二移位寄存器单元的输出端与对应的至少一条所述发光控制信号线连接。
具体的，所述显示装置包括阵列分布的多个所述像素驱动电路，多个所述像素驱动电路划分为多行像素驱动电路，示例性的，所述多行像素驱动电路沿Y方向依次排列，每行像素驱动电路均包括沿X方向依次排列的多个像素驱动电路。示例性的，所述X方向为水平方向，所述Y方向为竖直方向。
示例性的，所述第一栅线GA1的至少部分、所述第二栅线GA2的至少部分、所述复位信号线RE的至少部分和所述发光控制信号线EM的至少部分均沿X方向延伸。
所述栅极驱动电路包括与多行像素驱动电路一一对应的多个第一移位寄存器单元Gate GOA；所述发光信号控制电路包括多个第二移位寄存器单元EMGOA。
每行像素驱动电路中包括的各像素驱动电路复用该行像素驱动电路对应的一条第一栅线GA1。每行像素驱动电路中包括的各像素驱动电路复用该行像素驱动电路对应的一条第二栅线GA2。每行像素驱动电路中包括的各像素驱动电路复用该行像素驱动电路对应的一条复位信号线RE。每行像素驱动电路中包括的各像素驱动电路复用该行像素驱动电路对应的一条发光控制信号线EM。
每行像素驱动电路中包括的各像素驱动电路分别与对应的第二栅线GA2连接，当前行像素驱动电路对应的所述第二栅线GA2传输的信号，与相邻的下一行像素驱动电路对应的所述第一栅线GA1传输的信号相同，因此，可以将当前行像素驱动电路对应的所述第二栅线GA2与相邻的下一行像素驱动电路对应的第一栅线GA1，均与该相邻的下一行像素驱动电路对应的第一移位寄存器单元的输出端连接。
每行像素驱动电路中包括的各像素驱动电路分别与对应的复位信号线 RE连接，当前行像素驱动电路对应的复位信号线RE与相邻的上一行像素驱动电路对应的所述第一栅线GA1传输的信号相同，因此，可以将当前行像素驱动电路对应的复位信号线RE与相邻的上一行像素驱动电路对应的第一栅线GA1，均与该相邻的上一行像素驱动电路对应的第一移位寄存器单元的输出端连接。
所述多条发光控制信号线EM与所述多行像素驱动电路一一对应，每行像素驱动电路中包括的各像素驱动电路分别与对应的发光控制信号线连接，每个第二移位寄存器单元的输出端与对应的至少一条所述发光控制信号线连接。需要说明，当每个第二移位寄存器单元对应多条发光控制信号线时，所述多条发光控制信号线为相邻布局的多条发光控制信号线，且每一条发光控制信号线仅对应一个第二移位寄存器单元。
上述实施例提供的显示装置中，可设置当前行像素驱动电路对应连接的所述第一栅线GA1输入第一扫描信号，该第一扫描信号能够复用为相邻的下一行像素驱动电路对应连接的复位信号线RE输入的复位信号；还可设置该第一扫描信号复用为相邻的上一行像素驱动电路对应连接的第二栅线GA2输入的第二扫描信号；因此，上述实施例提供的显示装置中，仅需要设置gateGOA和EMGOA来为像素驱动电路提供相应的信号，所需要的控制信号较少，且同时能够兼容现有的GOA设计。
本公开实施例还提供了一种像素驱动电路的驱动方法，应用于上述实施例提供的像素驱动电路，所述驱动方法包括：在每一工作周期，
在复位时段P1，第一电源线VDD输入电源电压Vd，在复位信号线RE的控制下，第一复位子电路61控制导通所述第一电源线VDD与所述驱动子电路1的控制端之间的连接；
在阈值补偿时段P2，在所述复位信号线RE的控制下，第一复位子电路61控制断开所述第一电源线VDD与所述驱动子电路1的控制端之间的连接；初始化信号线Init输入初始化电压Vinit，在第一栅线GA1的控制下，第一控制子电路71控制导通所述初始化信号线Init与所述驱动子电路1的第二端之间的连接，补偿子电路4控制导通所述驱动子电路1的控制端和所述驱动子电路1的第一端之间的连接，以使所述驱动子电路1的第一端与第二端之间 由导通变为截止，使得所述驱动子电路1的控制端的电位由Vd变为Vinit+Vth，Vth为所述驱动子电路1对应的阈值电压；
在数据写入时段P3，在第一栅线GA1的控制下，第一控制子电路71控制断开所述初始化信号线Init与所述驱动子电路1的第二端之间的连接，补偿子电路4控制断开所述驱动子电路1的控制端和所述驱动子电路1的第一端之间的连接；数据线DA输入数据电压Vdata，在第二栅线GA2的控制下，数据写入子电路5控制导通所述数据线DA与所述第一存储子电路21的第二端之间的连接，使所述第一存储子电路21的第二端的电位变为Vdata，所述驱动子电路1的控制端的电位在所述第一存储子电路21的自举作用下相应改变；
在发光时段P4，所述电源信号输入端输入电源电压Vdd，在所述发光控制信号线EM的控制下，所述电源控制子电路3控制导通所述第一电源线VDD与所述驱动子电路1的第一端之间的连接，在第二栅线GA2的控制下，数据写入子电路5控制断开所述数据线DA与所述第一存储子电路21的第二端之间的连接，所述驱动子电路1在其控制端的控制下，控制导通该驱动子电路1的第一端与该驱动子电路1的第二端之间的连接，以驱动发光元件EL发光。
采用本公开实施例提供的驱动方法驱动像素驱动电路时，驱动电流I与驱动子电路对应的阈值电压Vth，以及电源电压Vd均没有关系；因此，采用本公开实施例提供的驱动方法驱动像素驱动电路，消除了阈值电压Vth漂移和电源电压Vd对驱动电流I的影响，有效提升了驱动电流的均匀性，保证了显示器件显示亮度的均匀性。
在一些实施例中，所述像素驱动电路还包括发光控制子电路8，所述驱动子电路1的第二端通过所述发光控制子电路8与所述发光元件EL连接；所述发光控制子电路8分别与所述发光控制信号线EM、所述驱动子电路1的第二端和所述发光元件EL连接；所述像素驱动电路还包括第二存储子电路22，所述第二存储子电路22的第一端与所述驱动子电路1的控制端连接，所述第二存储子电路22的第二端与所述发光元件EL连接；
所述驱动方法还包括：
在所述复位时段P1、所述阈值补偿时段P2和所述数据写入时段P3，在所述发光控制信号线EM的控制下，所述发光控制子电路8控制断开所述驱动子电路1的第二端与所述发光元件EL之间的连接；
在所述发光时段P4，在所述发光控制信号线EM的控制下，所述发光控制子电路8控制导通所述驱动子电路1的第二端与所述发光元件EL之间的连接，所述驱动子电路1的控制端的电位在所述第二存储子电路22的自举作用下相应改变。
在发光时段P4，发光元件EL发光，N4节点的电位由Vinit跳变至Voled，Voled为发光元件EL的工作电压，同时由于所述第二存储子电路22的耦合作用，N1节点的电位由Vinit+Vth+Vdata跳变至Vinit+Vth+Vdata+(Voled-Vinit)，即N1节点的电位变为Vth+Vdata+Voled。此时所述驱动子电路1的控制端和第二端之间的电压Vgs为：Vgs＝Vth+Vdata+Voled-Voled＝Vth+Vdata，Voled为发光元件EL的工作电压，驱动子电路1将其第一端和第二端导通并工作在饱和状态时产生的驱动电流I为：I＝k(Vgs-Vth) 2＝k(Vdata) 2，因此，消除了Voled对驱动电流I的影响，保证了显示器件显示亮度的均匀性。另外，也消除了发光元件EL连接的负电源信号线VSS输入的负电源信号对驱动电流I的影响。
在一些实施例中，所述像素驱动电路还包括第二复位子电路62，所述第二复位子电路62分别与所述复位信号线RE、所述初始化信号线Init和所述发光元件EL连接；
在所述复位时段P1，在所述复位信号线RE的控制下，所述像素驱动电路控制导通所述初始化信号线Init与所述发光元件EL之间的连接；
在所述阈值补偿时段P2、所述数据写入时段P3和所述发光时段P4，在所述复位信号线RE的控制下，所述像素驱动电路控制断开所述初始化信号线Init与所述发光元件EL之间的连接。
如图7和图8所示，在复位时段P1，在所述复位信号线RE的控制下，第二复位子电路62控制导通所述初始化信号线Init与所述发光元件EL的阳极之间的连接，实现对所述发光元件EL的阳极复位。
在一些实施例中，所述像素驱动电路还包括第二控制子电路72，所述第 二控制子电路72分别与所述第一栅线GA1、初始化信号线Init和所述第一存储子电路21的第二端连接；
在所述复位时段P1、所述数据写入时段P3和所述发光时段P4，在所述第一栅线GA1的控制下，所述第二控制子电路72控制断开所述初始化信号线Init与所述第一存储子电路21的第二端之间的连接；
所述阈值补偿时段P2，在所述第一栅线GA1的控制下，所述第二控制子电路72控制导通所述初始化信号线Init与所述第一存储子电路21的第二端之间的连接。
如图7和图9所示，在阈值补偿时段P2，在所述第一栅线GA1的控制下，所述第二控制子电路72控制导通所述初始化信号线Init与所述第一存储子电路21的第二端之间的连接，将N2节点的电位写入并保持在Vinit。
在数据写入时段P3，N2节点的电位变化量为Vdata-Vinit，在所述第一存储子电路21的自举作用下，N1节点的电位变为Vinit+Vth+Vdata-Vinit，即：Vth+Vdata。
当所述像素驱动电路包括所述发光控制子电路8和所述第二存储子电路22时，在发光时段P4，在所述第二存储子电路22的作用下，N1节点的电位变为Vth+Vdata+Voled-Vinit，Vgs＝Vth+Vdata-Vinit。驱动电流I为：I＝k(Vgs-Vth) 2＝I＝k(Vdata-Vinit) 2，可知驱动电流I与发光元件EL的工作电压Voled，驱动子电路1对应的阈值电压Vth，以及电源电压Vd均没有关系。
上述设置所述像素驱动电路还包括第二控制子电路72，使得在数据写入时段P3开始之前，N2节点具有稳定的电位，这样更有利于数据信号的写入。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分 不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种像素驱动电路，用于驱动发光元件，包括：
    驱动子电路，所述驱动子电路用于在其控制端的控制下，控制导通或断开该驱动子电路的第一端与该驱动子电路的第二端之间的连接，所述驱动子电路的第二端与所述发光元件连接；
    第一存储子电路，所述第一存储子电路的第一端与所述控制端连接；
    电源控制子电路，分别与发光控制信号线，第一电源线和所述驱动子电路的第一端连接，用于在所述发光控制信号线的控制下，控制导通或断开所述第一电源线与所述驱动子电路的第一端之间的连接；
    补偿子电路，分别与第一栅线、所述驱动子电路的控制端和所述驱动子电路的第一端连接，用于在所述第一栅线的控制下，控制导通或断开所述驱动子电路的控制端和所述驱动子电路的第一端之间的连接；
    数据写入子电路，分别与第二栅线、数据线和所述第一存储子电路的第二端连接，用于在所述第二栅线的控制下，控制导通或断开所述数据线与所述第一存储子电路的第二端之间的连接；
    第一复位子电路，分别与复位信号线、所述第一电源线和所述驱动子电路的控制端连接，用于在所述复位信号线的控制下，控制导通或断开所述第一电源线与所述驱动子电路的控制端之间的连接；
    第一控制子电路，分别与所述第一栅线、初始化信号线和所述驱动子电路的第二端连接，用于在所述第一栅线的控制下，控制导通和断开所述初始化信号线与所述驱动子电路的第二端之间的连接。
  2. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路还包括发光控制子电路，所述驱动子电路的第二端通过所述发光控制子电路与所述发光元件连接；
    所述发光控制子电路分别与所述发光控制信号线、所述驱动子电路的第二端和所述发光元件连接，用于在所述发光控制信号线的控制下，控制导通或断开所述驱动子电路的第二端与所述发光元件之间的连接。
  3. 根据权利要求2所述的像素驱动电路，其中，所述像素驱动电路还包 括：
    第二存储子电路，所述第二存储子电路的第一端与所述驱动子电路的控制端连接，所述第二存储子电路的第二端与所述发光元件连接。
  4. 根据权利要求2所述的像素驱动电路，其中，所述发光控制子电路包括：
    第六晶体管，所述第六晶体管的栅极与所述发光控制信号线连接，所述第六晶体管的第一极与所述驱动子电路的第二端连接，所述第六晶体管的第二极与所述发光元件连接。
  5. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路还包括：
    第二复位子电路，分别与所述复位信号线、所述初始化信号线和所述发光元件连接，用于在所述复位信号线的控制下，控制导通或断开所述初始化信号线与所述发光元件之间的连接。
  6. 根据权利要求5所述的像素驱动电路，其中，所述第二复位子电路包括第七晶体管，所述第七晶体管的栅极与所述复位信号线连接，所述第七晶体管的第一极与所述初始化信号线连接，所述第七晶体管的第二极与所述发光元件连接。
  7. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路还包括：
    第二控制子电路，分别与所述第一栅线、初始化信号线和所述第一存储子电路的第二端连接，用于在所述第一栅线的控制下，控制导通或断开所述初始化信号线与所述第一存储子电路的第二端之间的连接。
  8. 根据权利要求7所述的像素驱动电路，其中，所述第二控制子电路包括第九晶体管，所述第九晶体管的栅极与所述第一栅线连接，所述第九晶体管的第一极与所述初始化信号线连接，所述第九晶体管的第二极与所述第一存储子电路的第二端连接。
  9. 根据权利要求1所述的像素驱动电路，其中，
    所述驱动子电路包括第三晶体管；
    所述第一存储子电路包括第一电容，所述第一电容的第一端与所述第三 晶体管的栅极连接；
    所述第一复位子电路包括第一晶体管，所述第一晶体管的栅极与所述复位信号线连接，所述第一晶体管的第一极与所述第一电源线连接，所述第一晶体管的第二极与所述第三晶体管的栅极连接；
    所述补偿子电路包括第二晶体管，所述第二晶体管的栅极与所述第一栅线连接，所述第二晶体管的第一极与所述第三晶体管的第一极连接，所述第二晶体管的第二极与所述第三晶体管的栅极连接；
    所述数据写入子电路包括第四晶体管，所述第四晶体管的栅极与所述第二栅线连接，所述第四晶体管的第一极与所述数据线连接，所述第四晶体管的第二极与所述第一电容的第二端连接；
    所述电源控制子电路包括第五晶体管，所述第五晶体管的栅极与所述发光控制信号线连接，所述第五晶体管的第一极与所述第一电源线连接，所述第五晶体管的第二极与所述第三晶体管的第一极连接；
    所述第一控制子电路包括第八晶体管，所述第八晶体管的栅极与所述第一栅线连接，所述第八晶体管的第一极与所述初始化信号线连接，所述第八晶体管的第二极与所述驱动子电路的第二端连接。
  10. 一种显示装置，包括如权利要求1～9中任一项所述的像素驱动电路。
  11. 根据权利要求10所述的显示装置，其中，所述显示装置包括阵列分布的多个所述像素驱动电路，多个所述像素驱动电路划分为多行像素驱动电路；所述显示装置还包括栅极驱动电路、发光信号控制电路，多条第一栅线、多条第二栅线、多条复位信号线和多条发光控制信号线；
    所述栅极驱动电路包括与多行像素驱动电路一一对应的多个第一移位寄存器单元；
    所述发光信号控制电路包括多个第二移位寄存器单元；
    所述多条第一栅线与所述多个第一移位寄存器单元和所述多行像素驱动电路均一一对应，每行像素驱动电路中包括的各像素驱动电路分别与对应的第一栅线连接，所述第一栅线与对应的第一移位寄存器单元的输出端连接；
    所述多条第二栅线与所述多行像素驱动电路一一对应，每行像素驱动电路中包括的各像素驱动电路分别与对应的第二栅线连接，当前行像素驱动电 路对应的所述第二栅线与相邻的下一行像素驱动电路对应的第一移位寄存器单元的输出端连接；
    所述多条复位信号线与所述多行像素驱动电路一一对应，每行像素驱动电路中包括的各像素驱动电路分别与对应的复位信号线连接，当前行像素驱动电路对应的复位信号线与相邻的上一行像素驱动电路对应的第一移位寄存器单元的输出端连接；
    所述多条发光控制信号线与所述多行像素驱动电路一一对应，每行像素驱动电路中包括的各像素驱动电路分别与对应的发光控制信号线连接，每个第二移位寄存器单元的输出端与对应的至少一条所述发光控制信号线连接。
  12. 一种像素驱动电路的驱动方法，应用于如权利要求1～9任一项所述的像素驱动电路，所述驱动方法包括：在每一工作周期，
    在复位时段，第一电源线输入电源电压Vd，在复位信号线的控制下，第一复位子电路控制导通所述第一电源线与所述驱动子电路的控制端之间的连接；
    在阈值补偿时段，在所述复位信号线的控制下，第一复位子电路控制断开所述第一电源线与所述驱动子电路的控制端之间的连接；初始化信号线输入初始化电压Vinit，在第一栅线的控制下，第一控制子电路控制导通所述初始化信号线与所述驱动子电路的第二端之间的连接，补偿子电路控制导通所述驱动子电路的控制端和所述驱动子电路的第一端之间的连接，以使所述驱动子电路的第一端与第二端之间由导通变为截止，使得所述驱动子电路的控制端的电位由Vd变为Vinit+Vth，Vth为所述驱动子电路对应的阈值电压；
    在数据写入时段，在第一栅线的控制下，第一控制子电路控制断开所述初始化信号线与所述驱动子电路的第二端之间的连接，补偿子电路控制断开所述驱动子电路的控制端和所述驱动子电路的第一端之间的连接；数据线输入数据电压Vdata，在第二栅线的控制下，数据写入子电路控制导通所述数据线与所述第一存储子电路的第二端之间的连接，使所述第一存储子电路的第二端的电位变为Vdata，所述驱动子电路的控制端的电位在所述第一存储子电路的自举作用下相应改变；
    在发光时段，所述电源信号输入端输入电源电压Vdd，在所述发光控制 信号线的控制下，所述电源控制子电路控制导通所述第一电源线与所述驱动子电路的第一端之间的连接，在第二栅线的控制下，数据写入子电路控制断开所述数据线与所述第一存储子电路的第二端之间的连接，所述驱动子电路在其控制端的控制下，控制导通该驱动子电路的第一端与该驱动子电路的第二端之间的连接，以驱动发光元件发光。
  13. 根据权利要求12所述的像素驱动电路的驱动方法，其中，所述像素驱动电路还包括发光控制子电路，所述驱动子电路的第二端通过所述发光控制子电路与所述发光元件连接；所述发光控制子电路分别与所述发光控制信号线、所述驱动子电路的第二端和所述发光元件连接；所述像素驱动电路还包括第二存储子电路，所述第二存储子电路的第一端与所述驱动子电路的控制端连接，所述第二存储子电路的第二端与所述发光元件连接；
    所述驱动方法还包括：
    在所述复位时段、所述阈值补偿时段和所述数据写入时段，在所述发光控制信号线的控制下，所述发光控制子电路控制断开所述驱动子电路的第二端与所述发光元件之间的连接；
    在所述发光时段，在所述发光控制信号线的控制下，所述发光控制子电路控制导通所述驱动子电路的第二端与所述发光元件之间的连接，所述驱动子电路的控制端的电位在所述第二存储子电路的自举作用下相应改变。
  14. 根据权利要求12所述的像素驱动电路的驱动方法，其中，所述像素驱动电路还包括第二复位子电路，所述第二复位子电路分别与所述复位信号线、所述初始化信号线和所述发光元件连接；
    在所述复位时段，在所述复位信号线的控制下，所述像素驱动电路控制导通所述初始化信号线与所述发光元件之间的连接；
    在所述阈值补偿时段、所述数据写入时段和所述发光时段，在所述复位信号线的控制下，所述像素驱动电路控制断开所述初始化信号线与所述发光元件之间的连接。
  15. 根据权利要求12所述的像素驱动电路的驱动方法，其中，所述像素驱动电路还包括第二控制子电路，所述第二控制子电路分别与所述第一栅线、初始化信号线和所述第一存储子电路的第二端连接；
    在所述复位时段、所述数据写入时段和所述发光时段，在所述第一栅线的控制下，所述第二控制子电路控制断开所述初始化信号线与所述第一存储子电路的第二端之间的连接；
    所述阈值补偿时段，在所述第一栅线的控制下，所述第二控制子电路控制导通所述初始化信号线与所述第一存储子电路的第二端之间的连接。
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