WO2018228202A1 - 像素电路、像素驱动方法和显示装置 - Google Patents

像素电路、像素驱动方法和显示装置 Download PDF

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Publication number
WO2018228202A1
WO2018228202A1 PCT/CN2018/089120 CN2018089120W WO2018228202A1 WO 2018228202 A1 WO2018228202 A1 WO 2018228202A1 CN 2018089120 W CN2018089120 W CN 2018089120W WO 2018228202 A1 WO2018228202 A1 WO 2018228202A1
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Prior art keywords
transistor
control
control signal
voltage
driving
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PCT/CN2018/089120
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English (en)
French (fr)
Inventor
杨盛际
董学
吕敬
陈小川
玄明花
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京东方科技集团股份有限公司
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Priority to US16/329,091 priority Critical patent/US20190228708A1/en
Publication of WO2018228202A1 publication Critical patent/WO2018228202A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a pixel driving method, and a display device.
  • the pixel display device of the AMOLED display device includes an Organic Light-Emitting Diode (OLED).
  • OLED Organic Light-Emitting Diode
  • the driving thin film transistor in each pixel generates a driving current in a saturated state, and the driving current drives the corresponding OLED to emit light.
  • An aspect of the present disclosure provides a pixel circuit including a driving transistor, a threshold compensating sub-circuit, and an emission control sub-circuit.
  • the control electrode, the first pole and the second pole of the driving transistor are connected to the threshold compensating sub-circuit; the threshold compensating sub-circuit and the data line, the first power terminal, the first control signal end, and the second control signal end
  • the third control signal end is connected to the illumination control sub-circuit; the illumination control sub-circuit is connected to the first end of the illumination device and the illumination control signal end; and the second end of the illumination device is connected to the second power supply end.
  • the threshold compensation sub-circuit is configured to write a reset voltage to the control electrode of the driving transistor in a reset phase under the control of the first control signal terminal, the second control signal terminal, and the third control signal terminal.
  • the reset voltage is equal to a sum of a first voltage supplied from the first power supply terminal and a threshold voltage of the driving transistor, and a control voltage is written to a gate electrode of the driving transistor in a data writing phase, the control A voltage is associated with the reset voltage and a data voltage provided from the data line.
  • the drive transistor is configured to generate a drive current in accordance with the control voltage during an illumination phase.
  • the illumination control sub-circuit is configured to output the drive current to the light-emitting device during the illumination phase under control of an illumination control signal terminal to drive the illumination device to emit light.
  • control voltage is equal to a difference between a second data voltage provided by the data line in the data writing phase and a first data voltage provided by the data line in the reset phase The sum of the reset voltages.
  • the threshold compensation sub-circuit includes a first transistor, a second transistor, a third transistor, and a capacitor.
  • a control electrode of the first transistor is connected to the first control signal end, a first pole of the first transistor is connected to the first power terminal, a second pole of the first transistor is opposite to the driving transistor a first pole connection;
  • a control electrode of the second transistor is coupled to the second control signal terminal, a first pole of the second transistor is coupled to the data line, and a second pole of the second transistor is coupled a first end of the capacitor is connected;
  • a control electrode of the third transistor is connected to the third control signal end, and a first pole of the third transistor is connected to a second pole of the driving transistor, A second pole of the three transistor is coupled to the second terminal of the capacitor and to the control electrode of the drive transistor.
  • the second control signal end and the third control signal end are the same control signal end.
  • the illumination control subcircuit includes a fourth transistor.
  • a control electrode of the fourth transistor is connected to the light emission control signal line, a first electrode of the fourth transistor is connected to a second electrode of the driving transistor, and a second electrode of the fourth transistor is coupled to the light emitting The first end of the device is connected.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, and the driving transistor are P-type transistors.
  • Another aspect of the present disclosure provides a display device including any of the above pixel circuits.
  • a further aspect of the present disclosure provides a pixel driving method using any of the above pixel circuits.
  • the pixel driving method includes:
  • a reset voltage is written to a gate of the driving transistor by the threshold compensation sub-circuit, the reset voltage being equal to a first voltage provided by the first power terminal and the driving transistor The sum of the threshold voltages;
  • a control voltage is written to a gate of the driving transistor by the threshold compensation sub-circuit, the control voltage being related to the reset voltage and a data voltage supplied by the data line;
  • a driving current is generated by the driving transistor according to the control voltage, and the driving current is output to the light emitting device through the light emitting control sub-circuit to drive the light emitting device to emit light.
  • writing a reset voltage to the gate of the driving transistor by the threshold compensation sub-circuit includes: the first transistor being in the first control Conducted under the control of the signal terminal, the second transistor is turned on under the control of the second control signal terminal, the third transistor is turned on under the control of the third control signal terminal, and the fourth transistor is in the The control of the light-emitting control signal terminal is cut off.
  • writing a control voltage to the gate of the driving transistor by the threshold compensation sub-circuit includes: the first transistor being in the first control The control of the signal terminal is turned off, the second transistor is turned on under the control of the second control signal terminal, the third transistor is turned on under the control of the third control signal terminal, and the fourth transistor is in the The illumination control signal is turned off under the control of the signal terminal.
  • a driving current is generated according to the control voltage by the driving transistor, and the driving current is output to the light emitting device through the light emitting control sub-circuit to drive
  • the illuminating device emits light, comprising: the first transistor is turned on under the control of the first control signal end, the second transistor is turned off under the control of the second control signal end, and the third transistor is in the The control of the third control signal terminal is turned off, and the fourth transistor is turned on under the control of the light emission control signal terminal.
  • FIG. 1 is a schematic structural view of a typical pixel circuit
  • FIG. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 3 is a flowchart of a pixel driving method according to an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of a specific circuit of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 5 is a timing chart showing the operation of the pixel circuit shown in FIG. 4;
  • FIG. 6 is an equivalent circuit diagram of the pixel circuit shown in FIG. 4 in a reset phase
  • FIG. 7 is an equivalent circuit diagram of the pixel circuit shown in FIG. 4 in a data writing phase
  • FIG. 8 is an equivalent circuit diagram of the pixel circuit shown in FIG. 4 in an emission phase
  • FIG. 9 is a flowchart of another pixel driving method according to an embodiment of the present disclosure.
  • FIG. 1 is a schematic structural view of a typical pixel circuit.
  • the pixel circuit is a 2T1C circuit, that is, includes two transistors (a switching transistor T0 and a driving transistor DTFT) and one storage capacitor C.
  • the control electrode of the driving transistor DTFT is connected to the first electrode of the switching transistor T0 and one end of the storage capacitor C.
  • the first electrode of the driving transistor DTFT is connected to the first level signal terminal VDD and the other end of the storage capacitor C, and the driving transistor DTFT
  • the second pole is connected to one end of the light emitting device OLED.
  • the control electrode of the switching transistor DTFT is connected to the scanning signal terminal Scan, and the first electrode of the switching transistor DTFT is connected to the data line Data.
  • the other end of the light emitting device OLED is connected to the second level signal terminal VSS.
  • the driving transistor DTFT drives the light emitting device OLED to emit light
  • the driving current is commonly controlled by the first level signal terminal VDD, the data line Data, and the driving transistor DTFT.
  • FIG. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure. As shown in FIG. 2, the pixel circuit includes a driving transistor DTFT, a threshold compensating sub-circuit 1 and an emission control sub-circuit 2.
  • the gate, the first pole, and the second pole of the driving transistor DTFT are connected to the threshold compensating sub-circuit 1.
  • the threshold compensation sub-circuit 1 is connected to the data line Data, the first power supply terminal, the first control signal terminal Scan1, the second control signal terminal Scan2, the third control signal terminal Scan3, and the light emission control sub-circuit 2.
  • the light-emitting control sub-circuit 2 is connected to the first end of the light-emitting device OLED and the light-emission control signal terminal EM.
  • the second end of the light emitting device OLED is connected to the second power terminal.
  • the threshold compensation sub-circuit 1 is configured to write a reset voltage to the gate electrode of the driving transistor DTFT in the reset phase under the control of the first control signal terminal Scan1, the second control signal terminal Scan2, and the third control signal terminal Scan3.
  • the reset voltage is equal to the sum of the first voltage supplied from the first power supply terminal and the threshold voltage of the driving transistor DTFT, and the control voltage is written to the control electrode of the driving transistor DTFT, the control voltage and the reset voltage in the data writing phase Corresponding to the data voltage supplied from the data line Data.
  • the driving transistor DTFT is configured to generate a driving current according to a control voltage in an emission phase.
  • the light emission control sub-circuit 2 is configured to output a drive current to the light emitting device OLED during the light emission phase under the control of the light emission control signal terminal EM to drive the light emitting device OLED to emit light.
  • the first power terminal is configured to provide a first voltage Vdd
  • the second power terminal is configured to provide a second voltage Vss.
  • the light-emitting device in this embodiment may be any current-driven light-emitting device including an LED (Light Emitting Diode) or an OLED (Organic Light Emitting Diode).
  • LED Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • an OLED is taken as an example for description.
  • a reset voltage having a value equal to the sum of the first voltage and the threshold voltage of the driving transistor DTFT is written to the gate electrode of the driving transistor DTFT by the threshold compensation sub-circuit 1 in the reset phase, and in the data Writing a control voltage related to the reset voltage and the data voltage supplied from the data line Data to the gate electrode of the driving transistor DTFT by the threshold compensating sub-circuit 1 in the writing phase can be caused by the driving transistor DTFT in the light emitting phase
  • the driving current is independent of the threshold voltage of the driving transistor DTFT, thus eliminating the influence of the drift of the threshold voltage of the driving transistor DTFT on the driving current of the light emitting device OLED, thereby effectively improving the luminance uniformity of each pixel in the display device.
  • FIG. 3 is a flowchart of a pixel driving method according to an embodiment of the present disclosure.
  • the pixel driving method can adopt a pixel circuit as shown in FIG. 2, and the specific structure of the pixel circuit can be referred to the foregoing content, and details are not described herein again.
  • the reset voltage is written to the gate of the driving transistor by the threshold compensation sub-circuit, and the reset voltage is equal to the first voltage and the driving transistor provided by the first power terminal. The sum of the threshold voltages.
  • control voltage is written to the gate of the driving transistor by the threshold compensation sub-circuit, and the control voltage is related to the reset voltage and the data voltage supplied by the data line.
  • the control voltage written to the control electrode of the driving transistor DTFT necessarily also includes the threshold of the first voltage and the driving transistor DTFT. A component of the sum of the voltages that enables threshold compensation of the drive transistor DTFT in a subsequent illumination phase.
  • the component of the data voltage supplied from the data line Data in the control voltage can control the magnitude of the drive current output from the driving transistor DTFT.
  • control voltage is equal to the sum of the difference between the second data voltage provided by the data line Data during the data write phase and the first data voltage provided during the reset phase and the reset voltage.
  • a drive current is generated according to the control voltage by the drive transistor, and a drive current is output to the light-emitting device through the light-emission control sub-circuit to drive the light-emitting device to emit light.
  • a reset voltage having a value equal to a sum of a first voltage and a threshold voltage of a driving transistor is written to a gate electrode of a driving transistor by a threshold compensation sub-circuit in a reset phase, and data is written
  • Writing a control voltage related to the reset voltage and the data voltage supplied from the data line to the control electrode of the driving transistor through the threshold compensation sub-circuit in the stage the driving current generated by the driving transistor and the driving transistor in the light-emitting phase can be made
  • the threshold voltage is independent, thus eliminating the influence of the drift of the threshold voltage of the driving transistor on the driving current of the light emitting device, thereby effectively improving the brightness uniformity of each pixel in the display device.
  • FIG. 4 is a schematic structural diagram of a specific circuit of a pixel circuit according to an embodiment of the present disclosure.
  • the threshold compensation sub-circuit 1 includes a first transistor T1, a second transistor T2, a third transistor T3, and a capacitor C.
  • the control electrode of the first transistor T1 is connected to the first control signal terminal Scan1, the first electrode of the first transistor T1 is connected to the first power terminal VDD, and the second electrode of the first transistor T1 is connected to the first electrode of the driving transistor DTFT. .
  • the control electrode of the second transistor T2 is connected to the second control signal terminal Scan2, the first electrode of the second transistor T2 is connected to the data line Data, and the second electrode of the second transistor T2 is connected to the first terminal of the capacitor C.
  • the control electrode of the third transistor T3 is connected to the third control signal terminal Scan3, the first electrode of the third transistor T3 is connected to the second electrode of the driving transistor DTFT, and the second electrode of the third transistor T3 is connected to the second terminal of the capacitor C. Connected to the gate of the drive transistor DTFT.
  • the second control signal end Scan2 and the third control signal end Scan3 may be the same control signal end.
  • the control electrode of the second transistor T2 and the control electrode of the third transistor T3 are controlled by the control signal provided by the same control signal terminal, thereby effectively reducing the signal in the pixel circuit while realizing the pixel driving.
  • the number of layouts is favorable for the pixel aperture ratio.
  • the light emission control sub-circuit 2 includes a fourth transistor T4, the control electrode of the fourth transistor T4 is connected to the light emission control signal terminal EM, and the first electrode and the drive transistor of the fourth transistor T4 The second pole of the DTFT is connected, and the second pole of the fourth transistor T4 is connected to the first end of the light emitting device OLED. The second end of the light emitting device OLED is connected to the second power terminal VSS.
  • the driving transistor DTFT, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 in the embodiment are respectively selected from the group consisting of a polysilicon thin film transistor, an amorphous silicon thin film transistor, and an oxide.
  • a thin film transistor and an organic thin film transistor One of a thin film transistor and an organic thin film transistor.
  • the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are used as a switching transistor, and the driving transistor DTFT is used as a driving tube.
  • control electrode as referred to in this embodiment may refer to a gate of a transistor
  • first pole may refer to one of a source and a drain of a transistor
  • second pole “Can refer to the other of the source and drain of the transistor.
  • FIG. 4 describes the structure of a pixel circuit according to an embodiment of the present disclosure, taking each transistor as a P-type transistor as an example, each transistor may be an N-type transistor or a P-type transistor independently.
  • the types of the respective transistors in the pixel circuit shown in FIG. 4 are the same (for example, all P-type transistors or N-type transistors), the same fabrication process can be employed to simultaneously prepare all the transistors, so that the pixel circuit can be shortened. Production cycle.
  • first end and second end of a light emitting device OLED may refer to the anode and cathode ends of a light emitting device OLED, respectively.
  • each transistor in the pixel circuit is a P-type transistor, and the second control signal terminal Scan2 and the third control signal terminal Scan3 are the same control signal terminal as an example.
  • the concept of the present disclosure is not limited thereto.
  • the first power supply terminal VDD supplies the first voltage Vdd
  • the second power supply terminal VSS provides the second voltage Vss
  • the threshold voltage of the driving transistor DTFT is Vth.
  • Vth takes a negative value.
  • FIG. 5 is a timing chart showing the operation of the pixel circuit shown in FIG. As shown in FIG. 5, the working process of the pixel circuit includes three phases: a reset phase t1, a data writing phase t2, and an illumination phase t3.
  • the first control signal terminal Scan1 provides a low level signal
  • the second control signal terminal Scan2 and the third control signal terminal Scan3 provide a low level signal
  • the illumination control signal terminal EM provides a high level signal.
  • the first transistor T1, the second transistor T2, and the third transistor T3 are both turned on, and the fourth transistor T4 is turned off.
  • FIG. 6 is an equivalent circuit diagram of the pixel circuit shown in FIG. 4 in a reset phase. As shown in FIG. 6, since the second transistor T2 is turned on, the first data voltage supplied from the data line Data is written to the first end of the capacitor C through the second transistor T2. It is assumed that the first data voltage is Vdata', that is, the voltage of the node a is Vdata' at this time.
  • the first power terminal VDD sequentially charges the gate electrode of the driving transistor DTFT through the first transistor T1, the driving transistor DTFT, and the third transistor T3 until the driving transistor DTFT is controlled.
  • the voltage of the pole rises to Vdd+Vth, the driving transistor DTFT is turned off, and charging is completed.
  • the voltage of the node b is the reset voltage, and its value is Vdd+Vth.
  • the fourth transistor T4 since the fourth transistor T4 is in an off state at this time, the driving current cannot flow through the fourth transistor T4, and the light emitting device OLED does not emit light.
  • the first control signal terminal Scan1 provides a high level signal
  • the second control signal terminal Scan2 and the third control signal terminal Scan3 provide a low level signal
  • the light emission control signal terminal EM provides a high level signal.
  • both the second transistor T2 and the third transistor T3 are turned on, and the first transistor T1 and the fourth transistor T4 are both turned off.
  • FIG. 7 is an equivalent circuit diagram of the pixel circuit shown in FIG. 4 at the data writing stage.
  • the node b is in a floating state.
  • the voltage of the first end (node a) of the capacitor C changes, so that the capacitor C keeps the voltage difference between its two ends unchanged, it will generate a bootstrap effect, so that its second end
  • the voltage at (node b) is equally variable. That is, at this time, the voltage of the second terminal of the capacitor C becomes Vdd+Vth+ ⁇ V, that is, the control voltage input to the gate electrode of the driving transistor DTFT is equal to the second data voltage supplied by the data line Data in the data writing phase. The sum of the difference between the first data voltage and the reset voltage provided during the reset phase.
  • the first control signal terminal Scan1 provides a low level signal
  • the second control signal terminal Scan2 and the third control signal terminal Scan3 provide a high level signal
  • the light emission control signal terminal EM provides a low level signal.
  • both the first transistor T1 and the fourth transistor T4 are turned on, and the second transistor T2 and the third transistor T3 are both turned off.
  • FIG. 8 is an equivalent circuit diagram of the pixel circuit shown in FIG. 4 in the light emitting phase.
  • the first transistor T1 since the first transistor T1 is turned on, the first voltage Vdd supplied from the first power supply terminal VDD is written to the first electrode of the driving transistor DTFT through the first transistor T1, and at this time, the driving transistor DTFT is again Turn on.
  • the saturation drive current formula of the drive transistor DTFT it can be obtained:
  • K is a constant and Vgs is the gate-source voltage of the driving transistor DTFT.
  • the driving current of the driving transistor DTFT is related to the hopping voltage (ie, the difference between the second data voltage and the first data voltage) provided by the data line Data in the data writing phase, and is independent of the threshold voltage of the driving transistor DTFT.
  • threshold voltage compensation for the driving transistor DTFT can be achieved.
  • control of the drive current output from the driving transistor DTFT can be realized.
  • each transistor in the above pixel circuit is a P-type thin film transistor, which is only an exemplary embodiment of the present disclosure, which does not limit the technical solution of the present disclosure. It will be appreciated by those skilled in the art that by changing the type of at least a portion of the transistors in the pixel circuit described above (e.g., changing the P-type transistor to an N-type transistor), and correspondingly changing the control signal provided by the control signal terminal ( Other embodiments may be derived, for example, from a low level to a low level, without departing from the spirit and scope of the disclosure.
  • FIG. 9 is a flowchart of another pixel driving method according to an embodiment of the present disclosure. This pixel driving method is based on the pixel circuit shown in FIG. 4 described above. As shown in FIG. 9, at step S201, in the reset phase, the first transistor is turned on under the control of the first control signal terminal, the second transistor is turned on under the control of the second control signal terminal, and the third transistor is in the third state. The control signal is turned on under the control of the signal terminal, and the fourth transistor is turned off under the control of the light-emitting control signal terminal.
  • step S201 initially, the first transistor T1, the second transistor T2, the third transistor T3, and the driving transistor DTFT are all turned on.
  • the first power terminal sequentially charges the gate electrode of the driving transistor DTFT through the first transistor T1, the driving transistor DTFT, and the third transistor T3 until the voltage of the gate electrode of the driving transistor DTFT reaches the reset voltage and is turned off.
  • the value of the reset voltage is equal to the sum of the first voltage supplied from the first power supply terminal and the threshold voltage of the driving transistor DTFT.
  • the first data voltage supplied from the data line Data is written to the first end of the capacitor C through the second transistor T2.
  • the first transistor is turned off under the control of the first control signal terminal
  • the second transistor is turned on under the control of the second control signal terminal
  • the third transistor is controlled under the control of the third control signal terminal.
  • the fourth transistor is turned off under the control of the light emission control signal terminal.
  • step S202 the first transistor T1 and the fourth transistor T4 are both turned off, and the second end of the capacitor C is in a floating state.
  • the second transistor T2 is turned on, so the second data voltage supplied from the data line Data is written to the first end of the capacitor C through the second transistor T2.
  • the second end of the capacitor C is jumped to a control voltage by a bootstrap action, the value of the control voltage being equal to the second data voltage provided by the data line Data in the data writing phase and the first data voltage supplied by the data line Data in the reset phase. The difference between the difference and the reset voltage.
  • the third transistor T3 can also be turned off under the control of the third control signal end Scan3 in the data writing phase, which is not described in detail herein.
  • step S203 in the light emitting phase, the first transistor is turned on under the control of the first control signal end, the second transistor is turned off under the control of the second control signal end, and the third transistor is turned off under the control of the third control signal end, The four transistors are turned on under the control of the light-emitting control signal terminal.
  • step S203 the first transistor T1 is turned on, and thus the first voltage supplied from the first power supply terminal is written to the first electrode of the driving transistor DTFT.
  • the driving transistor DTFT is turned on and outputs a driving current. This drive current is determined by the control voltage of the gate of the drive transistor DTFT.
  • K is a constant and Vgs is the gate-source voltage of the driving transistor DTFT.
  • the driving current of the driving transistor DTFT is related to the hopping voltage (ie, the difference between the second data voltage and the first data voltage) provided by the data line Data in the data writing phase, and is independent of the threshold voltage of the driving transistor DTFT.
  • threshold voltage compensation for the driving transistor DTFT can be achieved.
  • the drive current output from the drive transistor DTFT can be controlled.
  • a reset voltage having a value equal to a sum of a threshold voltage of a first voltage and a driving transistor is written to a gate electrode of a driving transistor by a threshold compensation sub-circuit in a reset phase
  • a control voltage associated with the reset voltage and the data voltage supplied from the data line is written to the gate of the driving transistor through the threshold compensating sub-circuit, so that the driving current generated by the driving transistor in the light-emitting phase can be made
  • the threshold voltage of the driving transistor is independent, thus eliminating the influence of the drift of the threshold voltage of the driving transistor on the driving current of the light emitting device, thereby effectively improving the luminance uniformity of each pixel in the display device.
  • Embodiments of the present disclosure also provide a display device including any of the above pixel circuits.

Abstract

本公开提供了一种像素电路、像素驱动方法和显示装置。像素电路包括驱动晶体管、阈值补偿子电路和发光控制子电路。阈值补偿子电路配置成，在第一控制信号端、第二控制信号端、第三控制信号端的控制下，在重置阶段将重置电压写入至驱动晶体管的控制极，并且在数据写入阶段将控制电压写入至驱动晶体管的控制极。驱动晶体管配置成，在发光阶段根据控制电压产生驱动电流。发光控制子电路配置成，在发光控制信号端的控制下，在发光阶段将驱动电流输出至发光器件，以驱动发光器件发光。

Description

像素电路、像素驱动方法和显示装置
相关申请
本申请要求享有2017年6月14日提交的中国专利申请No.201710447592.5的优先权，其全部公开内容通过引用并入本文。
技术领域
本公开涉及显示技术领域，特别涉及一种像素电路、像素驱动方法和显示装置。
背景技术
有源矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，简称：AMOLED)显示装置的应用越来越广泛。AMOLED显示装置的像素显示器件包括有机发光二极管(Organic Light-Emitting Diode，简称OLED)。每一个像素中的驱动薄膜晶体管在饱和状态下产生驱动电流，该驱动电流驱动相应的OLED发光。
发明内容
本公开的一方面提供了一种像素电路，包括驱动晶体管、阈值补偿子电路和发光控制子电路。所述驱动晶体管的控制极、第一极和第二极与所述阈值补偿子电路连接；所述阈值补偿子电路与数据线、第一电源端、第一控制信号端、第二控制信号端、第三控制信号端和所述发光控制子电路连接；所述发光控制子电路与发光器件的第一端和发光控制信号端连接；所述发光器件的第二端与第二电源端连接。所述阈值补偿子电路配置成，在第一控制信号端、第二控制信号端、第三控制信号端的控制下，在重置阶段将重置电压写入至所述驱动晶体管的控制极，所述重置电压等于所述第一电源端提供的第一电压与所述驱动晶体管的阈值电压的和，并且在数据写入阶段将控制电压写入至所述驱动晶体管的控制极，所述控制电压与所述重置电压和从所述数据线提供的数据电压相关。所述驱动晶体管配置成，在发光阶段根据所述控制电压产生驱动电流。所述发光控制子电路配置成，在发光控制信号端的控制下，在所述发光阶段将所述驱动电流输出至所述发 光器件，以驱动所述发光器件发光。
根据本公开的一些实施例，所述控制电压等于所述数据线在所述数据写入阶段提供的第二数据电压与所述数据线在所述重置阶段提供的第一数据电压的差与所述重置电压的和。
根据本公开的一些实施例，所述阈值补偿子电路包括第一晶体管、第二晶体管、第三晶体管和电容器。所述第一晶体管的控制极与所述第一控制信号端连接，所述第一晶体管的第一极与所述第一电源端连接，所述第一晶体管的第二极与所述驱动晶体管的第一极连接；所述第二晶体管的控制极与所述第二控制信号端连接，所述第二晶体管的第一极与所述数据线连接，所述第二晶体管的第二极与所述电容器的第一端连接；所述第三晶体管的控制极与所述第三控制信号端连接，所述第三晶体管的第一极与所述驱动晶体管的第二极连接，所述第三晶体管的第二极与所述电容器的第二端和所述驱动晶体管的控制极连接。
根据本公开的一些实施例，所述第二控制信号端和所述第三控制信号端为同一控制信号端。
根据本公开的一些实施例，所述发光控制子电路包括第四晶体管。所述第四晶体管的控制极与所述发光控制信号线连接，所述第四晶体管的第一极与所述驱动晶体管的第二极连接，所述第四晶体管的第二极与所述发光器件的第一端连接。
根据本公开的一些实施例，所述第一晶体管、第二晶体管、第三晶体管、第四晶体管和驱动晶体管为P型晶体管。
本公开的另一方面提供了一种显示装置，包括上述任一种像素电路。
本公开另外的方面提供了一种像素驱动方法，采用上述任一种像素电路。该像素驱动方法包括：
在重置阶段，通过所述阈值补偿子电路将重置电压写入至所述驱动晶体管的控制极，所述重置电压等于所述第一电源端提供的第一电压与所述驱动晶体管的阈值电压的和；
在数据写入阶段，通过所述阈值补偿子电路将控制电压写入至所述驱动晶体管的控制极，所述控制电压与所述重置电压和所述数据线所提供的数据电压相关；
在发光阶段，通过所述驱动晶体管根据所述控制电压产生驱动电流，并且通过所述发光控制子电路将所述驱动电流输出至所述发光器件，以驱动所述发光器件发光。
根据本公开的一些实施例，所述在重置阶段，通过所述阈值补偿子电路将重置电压写入至所述驱动晶体管的控制极，包括：所述第一晶体管在所述第一控制信号端的控制下导通，所述第二晶体管在所述第二控制信号端的控制下导通，所述第三晶体管在所述第三控制信号端的控制下导通，所述第四晶体管在所述发光控制信号端的控制下截止。
根据本公开的一些实施例，所述在数据写入阶段，通过所述阈值补偿子电路将控制电压写入至所述驱动晶体管的控制极，包括：所述第一晶体管在所述第一控制信号端的控制下截止，所述第二晶体管在所述第二控制信号端的控制下导通，所述第三晶体管在所述第三控制信号端的控制下导通，所述第四晶体管在所述发光控制信号端的控制下截止。
根据本公开的一些实施例，所述在发光阶段，通过所述驱动晶体管根据所述控制电压产生驱动电流，并且通过所述发光控制子电路将所述驱动电流输出至所述发光器件，以驱动所述发光器件发光，包括：所述第一晶体管在所述第一控制信号端的控制下导通，所述第二晶体管在所述第二控制信号端的控制下截止，所述第三晶体管在所述第三控制信号端的控制下截止，所述第四晶体管在所述发光控制信号端的控制下导通。
附图说明
图1为典型的像素电路的结构示意图；
图2为本公开实施例提供的一种像素电路的结构示意图；
图3为本公开实施例提供的一种像素驱动方法的流程图；
图4为本公开实施例提供的像素电路的具体电路结构示意图；
图5为图4所示的像素电路的工作时序图；
图6为图4所示的像素电路在重置阶段的等效电路图；
图7为图4所示的像素电路在数据写入阶段的等效电路图；
图8为图4所示的像素电路在发光阶段的等效电路图；以及
图9为本公开实施例提供的另一种像素驱动方法的流程图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的像素电路、像素驱动方法和显示装置进行详细描述。
图1为典型的像素电路的结构示意图。如图1所示，该像素电路为2T1C电路，即包括两个晶体管(开关晶体管T0和驱动晶体管DTFT)和1个存储电容器C。驱动晶体管DTFT的控制极与开关晶体管T0的第一极和存储电容器C的一端相连，驱动晶体管DTFT的第一极与第一电平信号端VDD和存储电容器C的另一端相连，并且驱动晶体管DTFT的第二极与发光器件OLED的一端相连。开关晶体管DTFT的控制极与扫描信号端Scan相连，开关晶体管DTFT的第一极与数据线Data相连。发光器件OLED的另一端与第二电平信号端VSS相连。当驱动晶体管DTFT驱动发光器件OLED发光时，驱动电流由第一电平信号端VDD、数据线Data以及驱动晶体管DTFT共同控制。
在实际使用中，OLED的发光亮度对其驱动电流的变化相当敏感。不幸的是，由于各像素电路中的驱动晶体管DTFT在制作过程中无法做到完全一致，另外还由于工艺制程和器件老化，以及工作过程中温度的变化等原因，各像素电路中的驱动晶体管DTFT的阈值电压Vth存在不均匀性，这样就导致流过每个像素的OLED的电流发生变化，使得显示亮度不均，进而影响整个图像的显示效果。图2为本公开实施例提供的一种像素电路的结构示意图。如图2所示，该像素电路包括：驱动晶体管DTFT、阈值补偿子电路1和发光控制子电路2。
驱动晶体管DTFT的控制极、第一极和第二极与阈值补偿子电路1连接。阈值补偿子电路1与数据线Data、第一电源端、第一控制信号端Scan1、第二控制信号端Scan2、第三控制信号端Scan3和发光控制子电路2连接。发光控制子电路2与发光器件OLED的第一端和发光控制信号端EM连接。发光器件OLED的第二端与第二电源端连接。
阈值补偿子电路1配置成，在第一控制信号端Scan1、第二控制信号端Scan2、第三控制信号端Scan3的控制下，在重置阶段将重置电压写入至驱动晶体管DTFT的控制极，重置电压等于第一电源端提供的 第一电压与驱动晶体管DTFT的阈值电压的和，并且，在数据写入阶段将控制电压写入至驱动晶体管DTFT的控制极，控制电压与重置电压和从数据线Data提供的数据电压相关。
驱动晶体管DTFT配置成，在发光阶段根据控制电压产生驱动电流。
发光控制子电路2配置成，在发光控制信号端EM的控制下，在发光阶段将驱动电流输出至发光器件OLED，以驱动发光器件OLED发光。
在本实施例中，第一电源端配置成提供第一电压Vdd，并且第二电源端配置成提供第二电压Vss。
需要说明的是，本实施例中的发光器件可以是包括LED(Light Emitting Diode，发光二极管)或OLED(Organic Light Emitting Diode，有机发光二极管)在内的任何电流驱动型发光器件。在本实施例中是以OLED为例进行的说明。
在上述像素电路中，通过在重置阶段中通过阈值补偿子电路1将值等于第一电压与驱动晶体管DTFT的阈值电压的和的重置电压写入至驱动晶体管DTFT的控制极，并且在数据写入阶段中通过阈值补偿子电路1将与重置电压和从数据线Data提供的数据电压相关的控制电压写入至驱动晶体管DTFT的控制极，可以使得在发光阶段由驱动晶体管DTFT所产生的驱动电流与驱动晶体管DTFT的阈值电压无关，因此消除了驱动晶体管DTFT的阈值电压的漂移对发光器件OLED的驱动电流的影响，从而有效提升显示装置中各像素的亮度均匀性。
图3为本公开实施例提供的一种像素驱动方法的流程图。该像素驱动方法可以采用如图2所示的像素电路，该像素电路的具体结构可参见前述内容，此处不再赘述。如图3所示，在步骤S101处，在重置阶段，通过阈值补偿子电路将重置电压写入至驱动晶体管的控制极，重置电压等于第一电源端提供的第一电压与驱动晶体管的阈值电压的和。
在步骤S102处，在数据写入阶段，通过阈值补偿子电路将控制电压写入至驱动晶体管的控制极，控制电压与重置电压和数据线所提供的数据电压相关。
在该步骤S102中，由于重置电压等于第一电压与驱动晶体管DTFT 的阈值电压的和，因此写入至驱动晶体管DTFT的控制极处的控制电压必然也包含第一电压与驱动晶体管DTFT的阈值电压的和的成分，该成分可在后续发光阶段中实现对驱动晶体管DTFT的阈值补偿。
此外，控制电压中由数据线Data提供的数据电压的成分可对驱动晶体管DTFT输出的驱动电流的大小进行控制。
在示例性实施例中，控制电压等于数据线Data在数据写入阶段提供的第二数据电压与在重置阶段提供的第一数据电压之差与重置电压的和。
在步骤S103处，在发光阶段，通过驱动晶体管根据控制电压产生驱动电流，并且通过发光控制子电路将驱动电流输出至发光器件，以驱动发光器件发光。
在上述像素驱动方法中，通过在重置阶段中通过阈值补偿子电路将值等于第一电压与驱动晶体管的阈值电压的和的重置电压写入至驱动晶体管的控制极，并且在数据写入阶段中通过阈值补偿子电路将与重置电压和从数据线提供的数据电压相关的控制电压写入至驱动晶体管的控制极，可以使得在发光阶段由驱动晶体管所产生的驱动电流与驱动晶体管的阈值电压无关，因此消除了驱动晶体管的阈值电压的漂移对发光器件的驱动电流的影响，从而有效提升显示装置中各像素的亮度均匀性。
图4为本公开实施例提供的像素电路的具体电路结构示意图。如图4所示，在示例性实施例中，阈值补偿子电路1包括：第一晶体管T1、第二晶体管T2、第三晶体管T3和电容器C。
第一晶体管T1的控制极与第一控制信号端Scan1连接，第一晶体管T1的第一极与第一电源端VDD连接，并且第一晶体管T1的第二极与驱动晶体管DTFT的第一极连接。
第二晶体管T2的控制极与第二控制信号端Scan2连接，第二晶体管T2的第一极与数据线Data连接，并且第二晶体管T2的第二极与电容器C的第一端连接。
第三晶体管T3的控制极与第三控制信号端Scan3连接，第三晶体管T3的第一极与驱动晶体管DTFT的第二极连接，并且第三晶体管T3的第二极与电容器C的第二端和驱动晶体管DTFT的控制极连接。
在示例实施例中，可选地，第二控制信号端Scan2和第三控制信 号端Scan3可以为同一控制信号端。在这样的情况下，第二晶体管T2的控制极和第三晶体管T3的控制极由同一控制信号端所提供的控制信号来控制，因此可在实现像素驱动的同时，有效减小像素电路中信号走线的布置数量，有利于像素开口率的提升。
在示例性实施例中，如图4所示，发光控制子电路2包括第四晶体管T4，第四晶体管T4的控制极与发光控制信号端EM连接，第四晶体管T4的第一极与驱动晶体管DTFT的第二极连接，并且第四晶体管T4的第二极与发光器件OLED的第一端连接。发光器件OLED的第二端与第二电源端VSS连接。
需要说明的是，在本实施例中的驱动晶体管DTFT、第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4分别独立选自多晶硅薄膜晶体管、非晶硅薄膜晶体管、氧化物薄膜晶体管以及有机薄膜晶体管等中的一种。第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4作为开关管来使用，并且驱动晶体管DTFT作为驱动管来使用。
如本文所使用的，在本实施例中涉及到的“控制极”可以是指晶体管的栅极，“第一极”可以是指晶体管的源极和漏极中的一个，并且“第二极”可以是指晶体管的源极和漏极中的另一个。
应当指出的是，尽管图4以各个晶体管为P型晶体管为例描述了根据本公开的实施例的像素电路的结构，但是各个晶体管可以独立地为N型晶体管或P型晶体管。当如图4所示的像素电路中的各个晶体管的类型相同(例如全部为P型晶体管或N型晶体管)时，可采用相同的制备工艺以同时制备出全部晶体管，因此可以缩短该像素电路的生产周期。
如本文所使用的，发光器件OLED的“第一端”和“第二端”可以分别是指发光器件OLED的阳极端和阴极端。
为便于本领域技术人员更好的理解本公开的技术方案，下面将结合附图，对本实施例提供的像素电路的工作过程进行详细描述。在下面描述中，以像素电路中的各晶体管均为P型晶体管，第二控制信号端Scan2和第三控制信号端Scan3为同一控制信号端为例进行描述。但是本公开的概念不限于此。
假设，第一电源端VDD提供第一电压Vdd，第二电源端VSS提 供第二电压Vss，并且驱动晶体管DTFT的阈值电压为Vth。对于P型晶体管而言，Vth取负值。
图5为图4所示的像素电路的工作时序图。如图5所示，该像素电路的工作过程包括三个阶段：重置阶段t1、数据写入阶段t2和发光阶段t3。
在重置阶段t1，第一控制信号端Scan1提供低电平信号，第二控制信号端Scan2和第三控制信号端Scan3提供低电平信号，发光控制信号端EM提供高电平信号。此时，第一晶体管T1、第二晶体管T2和第三晶体管T3均导通，第四晶体管T4截止。
图6为图4所示的像素电路在重置阶段的等效电路图。如图6所示，由于第二晶体管T2导通，由数据线Data提供的第一数据电压通过第二晶体管T2被写入至电容器C的第一端。假定第一数据电压为Vdata’，即此时节点a的电压为Vdata’。
由于第一晶体管T1和第三晶体管T3导通，因此第一电源端VDD依次通过第一晶体管T1、驱动晶体管DTFT和第三晶体管T3对驱动晶体管DTFT的控制极进行充电，直至驱动晶体管DTFT的控制极的电压上升至Vdd+Vth，驱动晶体管DTFT截止，充电结束。此时，节点b的电压为重置电压，且其值为Vdd+Vth。
需要说明的是，由于此时第四晶体管T4处于截止状态，因此驱动电流无法流过第四晶体管T4，此时发光器件OLED不会发光。
在数据写入阶段t2，第一控制信号端Scan1提供高电平信号，第二控制信号端Scan2和第三控制信号端Scan3提供低电平信号，发光控制信号端EM提供高电平信号。此时，第二晶体管T2和第三晶体管T3均导通，第一晶体管T1和第四晶体管T4均截止。
图7为图4所示的像素电路在数据写入阶段的等效电路图。如图7所示，数据线Data提供第二数据电压，且第二数据电压可以小于第一数据电压。由于第二晶体管T2导通，因此由数据线Data提供的第二数据电压通过第二晶体管T2被写入至电容器C的第一端。假定第二数据电压为Vdata，即此时节点a的电压为Vdata，其中Vdata＝Vdata’+ΔV，ΔV为第二数据电压Vdata与第一数据电压Vdata’的差，并且特别地，ΔV为负值。
由于第一晶体管T1和第四晶体管T4均截止，因此节点b处于浮 接(floating)状态。相较于前一阶段，电容器C的第一端(节点a)的电压发生了变化，因此电容器C为保证其自身两端电压差不变，则会产生自举作用，以使得其第二端(节点b)的电压发生等量跳变。也就是说，此时电容器C的第二端的电压变为Vdd+Vth+ΔV，即输入至驱动晶体管DTFT的控制极的控制电压等于数据线Data在数据写入阶段提供的第二数据电压与在重置阶段时提供的第一数据电压的差与重置电压的和。
在发光阶段t3，第一控制信号端Scan1提供低电平信号，第二控制信号端Scan2和第三控制信号端Scan3提供高电平信号，发光控制信号端EM提供低电平信号。此时，第一晶体管T1和第四晶体管T4均导通，第二晶体管T2和第三晶体管T3均截止。
图8为图4所示的像素电路在发光阶段的等效电路图。如图8所示，由于第一晶体管T1导通，因此由第一电源端VDD提供的第一电压Vdd通过第一晶体管T1被写入至驱动晶体管DTFT的第一极，此时驱动晶体管DTFT再次导通。根据驱动晶体管DTFT的饱和驱动电流公式可得：
I＝K*(Vgs-Vth) 2
＝K*(Vdd+Vth+ΔV-Vdd-Vth) 2
＝K*(ΔV) 2
其中，K为一个常量，Vgs为驱动晶体管DTFT的栅源电压。通过上式可知，驱动晶体管DTFT的驱动电流与数据线Data在数据写入阶段提供的跳变电压(即第二数据电压与第一数据电压的差)相关，而与驱动晶体管DTFT的阈值电压无关，因而可实现对驱动晶体管DTFT的阈值电压补偿。
此外，通过控制数据线Data在数据写入阶段提供的跳变电压，可实现对驱动晶体管DTFT输出的驱动电流的控制。
需要说明的是，上述像素电路中的各晶体管均为P型薄膜晶体管仅为本公开的一个示例性实施例，这并不会对本公开的技术方案产生限制。本领域技术人员应该知晓的是，通过就上述像素电路中的至少部分晶体管的类型进行改变(例如，将P型晶体管变为N型晶体管)， 并且相应地改变控制信号端所提供的控制信号(例如，由低电平变为低电平)，可以得到其它实施例而不脱离于本公开的精神和范围。
图9为本公开实施例提供的另一种像素驱动方法的流程图。该像素驱动方法基于上述图4所示的像素电路。如图9所示，在步骤S201处，在重置阶段，第一晶体管在第一控制信号端的控制下导通，第二晶体管在第二控制信号端的控制下导通，第三晶体管在第三控制信号端的控制下导通，第四晶体管在发光控制信号端的控制下截止。
在步骤S201中，最初，第一晶体管T1、第二晶体管T2、第三晶体管T3和驱动晶体管DTFT均导通。第一电源端依次通过第一晶体管T1、驱动晶体管DTFT和第三晶体管T3以对驱动晶体管DTFT的控制极进行充电，直至驱动晶体管DTFT的控制极的电压达到重置电压而截止。重置电压的值等于第一电源端提供的第一电压与驱动晶体管DTFT的阈值电压的和。
与此同时，由数据线Data提供的第一数据电压通过第二晶体管T2被写入至电容器C的第一端。
在步骤S202处，在数据写入阶段，第一晶体管在第一控制信号端的控制下截止，第二晶体管在第二控制信号端的控制下导通，第三晶体管在第三控制信号端的控制下导通，并且第四晶体管在发光控制信号端的控制下截止。
在步骤S202中，第一晶体管T1和第四晶体管T4均截止，电容器C的第二端处于浮接状态。第二晶体管T2导通，因此由数据线Data提供的第二数据电压通过第二晶体管T2被写入至电容器C的第一端。电容器C的第二端通过自举作用跳变至控制电压，该控制电压的值等于数据线Data在数据写入阶段提供的第二数据电压与数据线Data在重置阶段提供的第一数据电压的差与重置电压的和。
需要说明的是，在数据写入阶段中，由于第一晶体管T1和第四晶体管T4均处于截止状态，因此无论第三晶体管T3处于导通状态还是截止状态，其均不会影响电容C的第二端处于浮接状态。因此，作为本实施例中的一种可选方案，第三晶体管T3还可在数据写入阶段时在第三控制信号端Scan3的控制下截止，具体情况此处不进行详细描述。
在步骤S203处，在发光阶段，第一晶体管在第一控制信号端的控制下导通，第二晶体管在第二控制信号端的控制下截止，第三晶体管 在第三控制信号端的控制下截止，第四晶体管在发光控制信号端的控制下导通。
在步骤S203中，第一晶体管T1导通，因此由第一电源端提供的第一电压被写入至驱动晶体管DTFT的第一极。此时驱动晶体管DTFT导通，并输出驱动电流。该驱动电流由驱动晶体管DTFT的控制极的控制电压决定。
根据驱动晶体管DTFT的饱和驱动电流公式可得：
I＝K*(Vgs-Vth) 2
＝K*(Vdd+Vth+ΔV-Vdd-Vth) 2
＝K*(ΔV) 2
其中，K为一个常量，Vgs为驱动晶体管DTFT的栅源电压。通过上式可知，驱动晶体管DTFT的驱动电流与数据线Data在数据写入阶段提供的跳变电压(即第二数据电压与第一数据电压的差)相关，而与驱动晶体管DTFT的阈值电压无关，因而可实现对驱动晶体管DTFT的阈值电压补偿。
此外，通过控制数据线Data在数据写入阶段提供的跳变电压，可以对驱动晶体管DTFT输出的驱动电流进行控制。
在上述像素电路和像素驱动方法中，通过在重置阶段中通过阈值补偿子电路将值等于第一电压与驱动晶体管的阈值电压的和的重置电压写入至驱动晶体管的控制极，并且在数据写入阶段中通过阈值补偿子电路将与重置电压和从数据线提供的数据电压相关的控制电压写入至驱动晶体管的控制极，可以使得在发光阶段由驱动晶体管所产生的驱动电流与驱动晶体管的阈值电压无关，因此消除了驱动晶体管的阈值电压的漂移对发光器件的驱动电流的影响，从而有效提升显示装置中各像素的亮度均匀性。
本公开的实施例还提供了一种显示装置，包括上述任一种像素电路。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出 各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (12)

  1. 一种像素电路，包括驱动晶体管、阈值补偿子电路和发光控制子电路，其中
    所述驱动晶体管的控制极、第一极和第二极与所述阈值补偿子电路连接；
    所述阈值补偿子电路与数据线、第一电源端、第一控制信号端、第二控制信号端、第三控制信号端和所述发光控制子电路连接；
    所述发光控制子电路与发光器件的第一端和发光控制信号端连接；
    所述发光器件的第二端与第二电源端连接；
    所述阈值补偿子电路配置成，在第一控制信号端、第二控制信号端、第三控制信号端的控制下，在重置阶段将重置电压写入至所述驱动晶体管的控制极，所述重置电压等于所述第一电源端提供的第一电压与所述驱动晶体管的阈值电压的和，并且在数据写入阶段将控制电压写入至所述驱动晶体管的控制极，所述控制电压与所述重置电压和从所述数据线提供的数据电压相关；
    所述驱动晶体管配置成，在发光阶段根据所述控制电压产生驱动电流；
    所述发光控制子电路配置成，在发光控制信号端的控制下，在所述发光阶段将所述驱动电流输出至所述发光器件，以驱动所述发光器件发光。
  2. 根据权利要求1所述的像素电路，其中，所述控制电压等于所述数据线在所述数据写入阶段提供的第二数据电压与所述数据线在所述重置阶段提供的第一数据电压的差与所述重置电压的和。
  3. 根据权利要求1所述的像素电路，其中，所述阈值补偿子电路包括第一晶体管、第二晶体管、第三晶体管和电容器；
    所述第一晶体管的控制极与所述第一控制信号端连接，所述第一晶体管的第一极与所述第一电源端连接，所述第一晶体管的第二极与所述驱动晶体管的第一极连接；
    所述第二晶体管的控制极与所述第二控制信号端连接，所述第二晶体管的第一极与所述数据线连接，所述第二晶体管的第二极与所述电容器的第一端连接；
    所述第三晶体管的控制极与所述第三控制信号端连接，所述第三晶体管的第一极与所述驱动晶体管的第二极连接，所述第三晶体管的第二极与所述电容器的第二端和所述驱动晶体管的控制极连接。
  4. 根据权利要求1所述的像素电路，其中，所述第二控制信号端和所述第三控制信号端为同一控制信号端。
  5. 根据权利要求1所述的像素电路，其中，所述发光控制子电路包括第四晶体管，
    所述第四晶体管的控制极与所述发光控制信号线连接，所述第四晶体管的第一极与所述驱动晶体管的第二极连接，所述第四晶体管的第二极与所述发光器件的第一端连接。
  6. 根据权利要求1所述的像素电路，其中，所述阈值补偿子电路包括第一晶体管、第二晶体管、第三晶体管和电容器，所述发光控制子电路包括第四晶体管，
    所述第一晶体管的控制极与所述第一控制信号端连接，所述第一晶体管的第一极与所述第一电源端连接，所述第一晶体管的第二极与所述驱动晶体管的第一极连接；
    所述第二晶体管的控制极与所述第二控制信号端连接，所述第二晶体管的第一极与所述数据线连接，所述第二晶体管的第二极与所述电容器的第一端连接；
    所述第三晶体管的控制极与所述第三控制信号端连接，所述第三晶体管的第一极与所述驱动晶体管的第二极连接，所述第三晶体管的第二极与所述电容器的第二端和所述驱动晶体管的控制极连接；
    所述第四晶体管的控制极与所述发光控制信号线连接，所述第四晶体管的第一极与所述驱动晶体管的第二极连接，所述第四晶体管的第二极与所述发光器件的第一端连接。
  7. 根据权利要求6所述的像素电路，其中，所述第一晶体管、第二晶体管、第三晶体管、第四晶体管和驱动晶体管为P型晶体管。
  8. 一种显示装置，包括如权利要求1-7中任一所述的像素电路。
  9. 一种像素驱动方法，采用上述权利要求1-7中任一所述的像素电路，所述像素驱动方法包括：
    在重置阶段，通过所述阈值补偿子电路将重置电压写入至所述驱动晶体管的控制极，所述重置电压等于所述第一电源端提供的第一电 压与所述驱动晶体管的阈值电压的和；
    在数据写入阶段，通过所述阈值补偿子电路将控制电压写入至所述驱动晶体管的控制极，所述控制电压与所述重置电压和所述数据线所提供的数据电压相关；
    在发光阶段，通过所述驱动晶体管根据所述控制电压产生驱动电流，并且通过所述发光控制子电路将所述驱动电流输出至所述发光器件，以驱动所述发光器件发光。
  10. 根据权利要求9所述的像素驱动方法，其中，所述像素电路为权利要求6所述的像素电路，所述在重置阶段，通过所述阈值补偿子电路将重置电压写入至所述驱动晶体管的控制极，包括：
    所述第一晶体管在所述第一控制信号端的控制下导通，所述第二晶体管在所述第二控制信号端的控制下导通，所述第三晶体管在所述第三控制信号端的控制下导通，所述第四晶体管在所述发光控制信号端的控制下截止。
  11. 根据权利要求1所述的像素驱动方法，其中，所述像素电路为权利要求6所述的像素电路，所述在数据写入阶段，通过所述阈值补偿子电路将控制电压写入至所述驱动晶体管的控制极，包括：
    所述第一晶体管在所述第一控制信号端的控制下截止，所述第二晶体管在所述第二控制信号端的控制下导通，所述第三晶体管在所述第三控制信号端的控制下导通，所述第四晶体管在所述发光控制信号端的控制下截止。
  12. 根据权利要求1所述的像素驱动方法，其中，所述像素电路为权利要求6所述的像素电路，所述在发光阶段，通过所述驱动晶体管根据所述控制电压产生驱动电流，并且通过所述发光控制子电路将所述驱动电流输出至所述发光器件，以驱动所述发光器件发光，包括：
    所述第一晶体管在所述第一控制信号端的控制下导通，所述第二晶体管在所述第二控制信号端的控制下截止，所述第三晶体管在所述第三控制信号端的控制下截止，所述第四晶体管在所述发光控制信号端的控制下导通。
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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106991976A (zh) * 2017-06-14 2017-07-28 京东方科技集团股份有限公司 像素电路、像素驱动方法和显示装置
CN207474026U (zh) * 2017-10-31 2018-06-08 昆山国显光电有限公司 一种像素电路和显示装置
CN107908310B (zh) 2017-11-13 2019-12-06 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN107945740B (zh) * 2018-01-05 2020-08-18 信利（惠州）智能显示有限公司 像素电路的驱动方法
CN108447443B (zh) * 2018-05-14 2020-01-21 京东方科技集团股份有限公司 像素电路及驱动方法、显示装置
CN110189705B (zh) * 2019-06-19 2021-02-05 京东方科技集团股份有限公司 像素电路、显示面板和显示设备
CN110751928B (zh) * 2019-11-11 2022-04-08 Oppo广东移动通信有限公司 一种像素电路及其工作方法、显示装置
CN111292700A (zh) * 2020-03-31 2020-06-16 京东方科技集团股份有限公司 一种tft阈值电压补偿方法、装置及显示器
KR20220020079A (ko) * 2020-08-11 2022-02-18 삼성전자주식회사 디스플레이 장치 및 이의 제어 방법
CN112581908A (zh) * 2020-12-23 2021-03-30 上海天马有机发光显示技术有限公司 像素驱动电路、驱动方法、显示面板与显示装置
CN115440161B (zh) * 2022-11-09 2023-03-24 惠科股份有限公司 像素驱动电路和显示面板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130132708A (ko) * 2013-11-01 2013-12-05 호서대학교 산학협력단 Vdd 전원 라인 없이 문턱전압과 전압강하를 보상하는 유기발광 다이오드 화소 회로
CN104050916A (zh) * 2014-06-04 2014-09-17 上海天马有机发光显示技术有限公司 一种有机发光显示器的像素补偿电路及方法
CN104167170A (zh) * 2014-07-10 2014-11-26 京东方科技集团股份有限公司 像素电路及其驱动方法和显示装置
US20160180775A1 (en) * 2014-12-18 2016-06-23 Samsung Display Co., Ltd. Organic light emitting display and method for driving the same
CN106782322A (zh) * 2017-02-14 2017-05-31 深圳市华星光电技术有限公司 Amoled像素驱动电路及amoled像素驱动方法
CN106991976A (zh) * 2017-06-14 2017-07-28 京东方科技集团股份有限公司 像素电路、像素驱动方法和显示装置
CN107342047A (zh) * 2017-01-03 2017-11-10 京东方科技集团股份有限公司 像素电路及其驱动方法、以及显示面板

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0400213D0 (en) * 2004-01-07 2004-02-11 Koninkl Philips Electronics Nv Electroluminescent display devices
CN101976545A (zh) * 2010-10-26 2011-02-16 华南理工大学 Oled显示器的像素驱动电路及其驱动方法
JP5890656B2 (ja) * 2011-11-09 2016-03-22 三星ディスプレイ株式會社Ｓａｍｓｕｎｇ Ｄｉｓｐｌａｙ Ｃｏ．，Ｌｔｄ． 電気光学装置の駆動方法および電気光学装置
KR101411619B1 (ko) * 2012-09-27 2014-06-25 엘지디스플레이 주식회사 화소 회로와 그 구동 방법 및 이를 이용한 유기 발광 표시 장치
CN102930824B (zh) * 2012-11-13 2015-04-15 京东方科技集团股份有限公司 像素电路及驱动方法、显示装置
TW201441997A (zh) * 2013-04-24 2014-11-01 Wintek Corp 發光元件驅動電路及其相關的畫素電路與應用
CN104064139B (zh) * 2014-06-05 2016-06-29 上海天马有机发光显示技术有限公司 一种有机发光二极管像素补偿电路、显示面板和显示装置
JP2016109915A (ja) * 2014-12-08 2016-06-20 三星ディスプレイ株式會社Ｓａｍｓｕｎｇ Ｄｉｓｐｌａｙ Ｃｏ．，Ｌｔｄ． 画素回路、および表示装置
CN104409050B (zh) * 2014-12-24 2017-02-15 京东方科技集团股份有限公司 Oled像素电路及其驱动方法、显示面板及显示装置
CN104821150B (zh) * 2015-04-24 2018-01-16 北京大学深圳研究生院 像素电路及其驱动方法和显示装置
CN105161051A (zh) * 2015-08-21 2015-12-16 京东方科技集团股份有限公司 像素电路及其驱动方法、阵列基板、显示面板及显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130132708A (ko) * 2013-11-01 2013-12-05 호서대학교 산학협력단 Vdd 전원 라인 없이 문턱전압과 전압강하를 보상하는 유기발광 다이오드 화소 회로
CN104050916A (zh) * 2014-06-04 2014-09-17 上海天马有机发光显示技术有限公司 一种有机发光显示器的像素补偿电路及方法
CN104167170A (zh) * 2014-07-10 2014-11-26 京东方科技集团股份有限公司 像素电路及其驱动方法和显示装置
US20160180775A1 (en) * 2014-12-18 2016-06-23 Samsung Display Co., Ltd. Organic light emitting display and method for driving the same
CN107342047A (zh) * 2017-01-03 2017-11-10 京东方科技集团股份有限公司 像素电路及其驱动方法、以及显示面板
CN106782322A (zh) * 2017-02-14 2017-05-31 深圳市华星光电技术有限公司 Amoled像素驱动电路及amoled像素驱动方法
CN106991976A (zh) * 2017-06-14 2017-07-28 京东方科技集团股份有限公司 像素电路、像素驱动方法和显示装置

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