WO2018054350A1 - 像素电路及其驱动方法、阵列基板以及显示装置 - Google Patents

像素电路及其驱动方法、阵列基板以及显示装置 Download PDF

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Publication number
WO2018054350A1
WO2018054350A1 PCT/CN2017/102890 CN2017102890W WO2018054350A1 WO 2018054350 A1 WO2018054350 A1 WO 2018054350A1 CN 2017102890 W CN2017102890 W CN 2017102890W WO 2018054350 A1 WO2018054350 A1 WO 2018054350A1
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Prior art keywords
transistor
pole
control
phase
node
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PCT/CN2017/102890
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English (en)
French (fr)
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郑灿
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京东方科技集团股份有限公司
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Priority to US15/765,709 priority Critical patent/US10565933B2/en
Publication of WO2018054350A1 publication Critical patent/WO2018054350A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of semiconductor technologies, and in particular, to a pixel circuit and a driving method thereof, an array substrate, and a display device.
  • the display mainly includes two types: Thin Film Transistor-Liquid Crystal Display (TFT-LCD) and Organic Light-emitting Diode (OLED) display.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • OLED Organic Light-emitting Diode
  • OLED displays are current driven and require a constant current to control the brightness of the OLED.
  • the OLED display performs brightness control of the OLED through a pixel circuit.
  • a known 2T1C (2 transistors and 1 capacitor) pixel circuit includes a switching transistor T1, a driving transistor T2, and a storage capacitor Cs, wherein the gate of T1 is connected to the gate line, and the first pole is connected to the data line.
  • the second pole is connected to the control pole of T2; the first pole of T2 is connected to the power supply voltage Vdd, the second pole is connected to the anode of the OLED; the cathode of the OLED is grounded; and the storage capacitor Cs is connected in parallel between the gate source of T2.
  • the threshold voltage Vth of the driving TFTs of each pixel may be different, and drift may occur with use, which results in even if the same gate-source voltage Vgs is applied to the driving transistor.
  • the current I OLED also changes due to Vth, which affects the uniformity of the display.
  • Embodiments of the present disclosure provide a pixel circuit and a driving method thereof, an array substrate, and a display device.
  • an embodiment of the present disclosure provides a pixel circuit, the pixel circuit including:
  • a pre-charging sub-circuit configured to write a power supply voltage to the first node under control of the scan signal and the illumination control signal during a pre-charge phase, the first node being coupled to a control electrode of the drive transistor;
  • a reset sub-circuit configured to decrease a potential of the first node under control of a reference signal during a reset phase
  • a data writing sub-circuit configured to write a data voltage to the first node under control of a scan signal during a data writing phase, such that a potential of the first node is equal to the data voltage and the driving transistor The sum of threshold voltages;
  • the illumination control sub-circuit is configured to conduct the power source and the illumination unit through the drive transistor under the control of the illumination control signal during the illumination phase.
  • the pre-charging sub-circuit includes a first transistor and a second transistor, and a control electrode of the first transistor is connected to an emission control line, and a first pole of the first transistor Connected to the power line, the second pole of the first transistor is connected to the first pole of the driving transistor, the gate of the second transistor is connected to the gate line, the first pole of the second transistor is a first pole of the driving transistor is connected, a second pole of the second transistor is connected to a control pole of the driving transistor, the light emission control line is configured to output the light emission control signal, and the power line is configured to output the A power supply voltage of the power supply, the gate line configured to output the scan signal.
  • the reset sub-circuit includes a capacitor, one end of the capacitor is connected to a control pole of the driving transistor, and the other end of the capacitor is connected to a reference signal line, the reference The signal line is configured to output the reference signal.
  • the data writing sub-circuit includes a third transistor and a fourth transistor, a control electrode of the third transistor is connected to the gate line, and a third transistor One pole is connected to the data line, and the second pole of the third transistor is a second pole of the driving transistor is connected, a control electrode of the fourth transistor is connected to the reference signal line, and a first pole of the fourth transistor is connected to a second pole of the driving transistor, the fourth A second pole of the transistor is coupled to the illumination control subcircuit, and the data line is configured to output the data voltage.
  • the illumination control sub-circuit includes a fifth transistor, a control electrode of the fifth transistor is connected to the illumination control line, and a first pole of the fifth transistor is The second pole of the fourth transistor is connected, and the second pole of the fifth transistor is connected to the light emitting unit.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the driving transistor are thin film transistors.
  • the scan signal in each period, includes two pulses, and a previous one of the two pulses is configured to control the pre-charge sub-circuit to write a power supply voltage Into the first node, the latter one of the two pulses is configured to control the data write sub-circuit to write a data voltage to the first node, the period including the pre-charge phase, the reset phase , data writing phase and lighting phase.
  • the illumination control signal in each period, includes a pulse, and the pulse is configured to control the illumination control sub-circuit to conduct power and the illumination unit through the driving transistor,
  • Each cycle includes the precharge phase, the reset phase, the data write phase, and the illumination phase.
  • an embodiment of the present disclosure further provides an array substrate, the array substrate comprising a plurality of rows of any of the above pixel circuits.
  • the light emission control line of the pixel circuit of the Nth row is connected to the reference signal line of the pixel circuit of the (N+1)th row, and N is a positive integer.
  • an embodiment of the present disclosure further provides a display device including any of the above array substrates.
  • an embodiment of the present disclosure further provides a pixel circuit driving method for driving the pixel circuit described above, the method comprising:
  • the power supply voltage is written to the first node, and the first node is connected to the control electrode of the driving transistor;
  • the potential of the first node is lowered under the control of the reference signal
  • the data voltage is written to the first under the control of the scan signal a node, the potential of the first node being equal to a sum of the data voltage and a threshold voltage of the driving transistor;
  • the power source and the light emitting unit are turned on by the driving transistor under the control of the light emission control signal.
  • the scan signal in each period, includes two pulses, and a previous one of the two pulses is configured to write a power supply voltage to the first node, The latter of the two pulses is configured to write a data voltage to the first node, the period including the precharge phase, the reset phase, the data write phase, and the illumination phase.
  • an embodiment of the present disclosure provides a driving method of an array substrate for driving the array substrate, the method comprising driving a pixel circuit of the array substrate row by row using the pixel circuit driving method.
  • the light emission control signal of the pixel circuit of the Nth row and the reference signal of the pixel circuit of the (N+1)th row are the same signal, and N is a positive integer.
  • the scan signal in each period, includes two pulses, and a previous one of the two pulses is configured to write a power supply voltage to the first node, The latter of the two pulses is configured to write a data voltage to the first node, the period including the precharge phase, the reset phase, the data write phase, and the illumination phase.
  • the power supply voltage is written to the first node by the pre-charging sub-circuit, and then the potential of the first node is lowered by the reset sub-circuit, and the data voltage is written to the first node by the data writing sub-circuit,
  • the potential of the first node is made equal to the sum of the data voltage and the threshold voltage of the driving transistor, and finally the power source and the light emitting unit are turned on by the driving transistor, thereby driving the light emitting unit to emit light.
  • the resetting of the pixel circuit can be realized by writing and lowering the potential of the first node by the pre-charging sub-circuit and the reset sub-circuit, so that it is not necessary to use a separate reset circuit to generate a reset signal to achieve reset.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a specific implementation circuit of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 3 is a flowchart of a pixel driving method according to an embodiment of the present disclosure
  • FIG. 4 is a timing diagram of a control signal of a pixel circuit provided by an embodiment of the present disclosure.
  • An embodiment of the present disclosure provides a pixel circuit for driving an organic light emitting diode to emit light.
  • the pixel circuit includes: a driving transistor 100, a precharge sub-circuit 101, a reset sub-circuit 102, a data writing sub-circuit 103, and The illumination control sub-circuit 104.
  • the precharge sub-circuit 101 is configured to write a power supply voltage to the first node under control of the scan signal and the illumination control signal during the precharge phase, the first node being coupled to the control electrode of the drive transistor 100.
  • the reset sub-circuit 102 is configured to reduce the potential of the first node under the control of the reference signal during the reset phase;
  • the data write sub-circuit 103 is configured to write the data voltage to the first under the control of the scan signal during the data writing phase
  • the node is such that the potential of the first node is equal to the sum of the data voltage and the threshold voltage of the driving transistor 100.
  • the light emission control sub-circuit 104 is configured to conduct the power source and the light emitting unit OLED through the driving transistor 100 under the control of the light emission control signal in the light emitting phase, so that the light emitting unit OLED emits light.
  • the scan signal is provided by the gate line gate
  • the light emission control signal is provided by the light emission control line em
  • the power supply voltage is supplied by the power supply line Vdd
  • the power supply line Vdd is connected to the power supply
  • the data voltage is supplied by the data line data
  • the reference signal Provided by the reference signal line ref.
  • An embodiment of the present disclosure writes a power supply voltage to a first node through a precharge sub-circuit, and then reduces a potential of the first node by a reset sub-circuit, and writes the data voltage to the first node through the data write sub-circuit, so that the first The potential of the node is equal to the sum of the data voltage and the threshold voltage of the driving transistor, and finally the power source and the light emitting unit are turned on by the driving transistor, thereby driving the light emitting unit to emit light.
  • the resetting of the pixel circuit can be realized by writing and lowering the potential of the first node by the pre-charging sub-circuit and the reset sub-circuit, so that it is not necessary to use a separate reset circuit to generate a reset signal to achieve reset.
  • the pre-charging sub-circuit 101 may include a first transistor T1 and a second transistor T2, wherein a control electrode of the first transistor T1 is connected to the light-emission control line em, and the first pole and the power line of the first transistor T1 Vdd is connected, the second pole of the first transistor T1 is connected to the first pole of the driving transistor 100, and the gate of the second transistor T2 is connected to the gate line gate, the first pole of the second transistor T2 is the first of the driving transistor 100 The pole is connected, and the second pole of the second transistor T2 is connected to the control electrode of the driving transistor 100.
  • the pre-charging sub-circuit 101 controls the T1 by the illumination control signal outputted by the illumination control line em, and the T2 is controlled by the scan signal outputted by the gate line gate, and T1 and T2 are turned on to realize the power supply voltage input, wherein the potential of the first node N1 is Vdd.
  • the reset sub-circuit 102 may include a capacitor C1 having one end connected to the control electrode of the driving transistor 100 and the other end of the capacitor C1 connected to the reference signal line ref.
  • the reset sub-circuit 102 lowers the potential of the other end of C1 (reduced from VGH to V1) by the reference signal, and the potential of the one end of C1 is lowered due to the bootstrap action of the capacitor C1 (reduced from Vdd to Vdd+V1-VGH) ), thereby achieving a reduction in the potential of the first node N1.
  • the data writing sub-circuit 103 may include a third transistor T3 and a fourth transistor T4, wherein a control electrode of the third transistor T3 is connected to the gate line gate, and a first electrode of the third transistor T3 is connected to the data line data.
  • the second electrode of the third transistor T3 is connected to the second electrode of the driving transistor 100, and the control electrode of the fourth transistor T4 is connected to the reference signal line ref, and the first electrode of the fourth transistor T4 is connected to the second electrode of the driving transistor 100.
  • the second electrode of the fourth transistor T4 is connected to the light emission control sub-circuit 104.
  • the data writing sub-circuit 103 controls the third transistor T3 to be turned on by the scanning signal output from the gate line gate, and controls the fifth transistor T5 to be turned off by the lighting control signal output from the lighting control line em, thereby ensuring charging.
  • T2 and the driving transistor 100 form a diode connection, respectively.
  • the potential of the first node N1 is a low level Vdd+V1-VGH, and the data signal reaches the second pole of the driving transistor 100 through T3.
  • the driving transistor 100 Since the voltage Vdata of the data signal is at a high potential, the driving transistor 100 is reverse-conducted, and Vdata is charged to the first node N1 through T2 until the potential of the first node N1 reaches Vdata+Vth, the driving transistor 100 is turned off, and charging is completed.
  • the illumination control sub-circuit 104 includes a fifth transistor T5.
  • the control electrode of the fifth transistor T5 is connected to the emission control line em, and the first electrode of the fifth transistor T5 is connected to the second electrode of the fourth transistor T4.
  • the second pole of the transistor T5 is connected to the light emitting unit OLED.
  • the illuminating control sub-circuit 104 controls the first transistor T1 and the fifth transistor T5 to be turned on by the illuminating control signal outputted by the illuminating control line em.
  • the first pole potential of T3 is greater than the control pole, T3 is turned on, and the first of the driving transistor 100 is turned on.
  • the pole potential is greater than the control pole, and the driving transistor 100 is turned on.
  • T1, T4, and the driving transistors 100 and T5 are all turned on, thereby achieving conduction between the power source and the light emitting unit.
  • one end of the light emitting unit OLED is connected to the high voltage Vdd through T1 and T4, the driving transistors 100 and T5, and the other end is connected to the low voltage Vss, so that the light emitting unit OLED emits light under the action of Vdd and Vss.
  • the light emission control line em of the pixel circuit of the Nth row is connected to the reference signal line ref of the pixel circuit of the (N+1)th row, and is connected to the same output signal line of the scan driving unit.
  • N is a positive integer.
  • the illumination control signal is different from the reference signal by one phase, so that the illumination control line em of the pixel circuit of the Nth row and the reference signal line ref of the pixel circuit of the (N+1)th row can satisfy the above requirement.
  • the scan driving unit may be a Gate On Array (GOA) unit.
  • GOA Gate On Array
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the driving transistor 100 are thin film transistors.
  • the thin film transistor is small in size, low in power consumption, and convenient and accurate in control.
  • the driving transistor 100 may be a P-channel enhanced metal oxide semiconductor field effect transistor (MOSFET) tube or a P-type bipolar junction transistor (Bipolar Junction Transistor). BJT) tube.
  • MOSFET metal oxide semiconductor field effect transistor
  • BJT Bipolar Junction Transistor
  • the first to fifth transistors T1-T5 are respectively a Junction Field Effect Transistor (JFET) tube, an enhanced MOSFET tube, One or more of a depletion MOSFET and a BJT tube.
  • JFET Junction Field Effect Transistor
  • the first to fifth transistors T1-T5 and the driving transistor are both P-type transistors.
  • the embodiments of the present disclosure are not limited thereto, and the first to fifth transistors T1-T5 and the driving transistor may also be N-type transistors.
  • the transistors are P-type transistors, when the gate voltage of the transistor is less than the second-pole voltage, the transistor is turned on; when the fifth transistor is an N-type transistor When the gate voltage of the transistor is greater than the second pole voltage, the transistor is turned on.
  • the illumination control signal includes a pulse for controlling the illumination control sub-circuit 104 to conduct the power supply and the illumination unit through the drive transistor.
  • the scan signal includes two pulses, the previous one of the two pulses is used to control the precharge sub-circuit 101 to write the supply voltage to the first node, and the latter of the two pulses is used to control the data.
  • the write subcircuit 103 writes the data voltage to the first node, where each cycle includes a precharge phase, a reset phase, a data write phase, and an illumination phase.
  • the scan signal when the transistor is a P-type transistor, the scan signal includes two low-level pulses, and the light-emission control signal includes a high-level pulse.
  • the scan signal when the transistor is an N-type transistor, the scan signal includes two high-level pulses, and the light-emission control signal includes a low-level pulse.
  • the scan signal and the light-emission control signal can be simultaneously generated by the scan driving unit, thereby reducing the drive signal generating circuit.
  • the scan driving unit mainly includes a gate shift register, and the gate shift register can generate two level signals of VGH and VGL.
  • the illumination control signal may be implemented by a high level VGH, and the scan signal may be implemented with a low level VGL (eg, by controlling a timing signal to output two low level VGL pulses per period).
  • Embodiments of the present disclosure provide an array substrate including the pixel circuit provided in FIG. 1 or FIG.
  • the array substrate provided by the embodiment of the present disclosure has the same technical features as the above-described pixel circuit, the same technical problem can be solved, and the same technical effect is produced.
  • the embodiment of the present disclosure further provides a display device including any of the above array substrates.
  • the display device can be: electronic paper, OLED panel, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc. A product or part that exhibits functionality.
  • the display device provided by the embodiment of the present disclosure has the same technical features as any of the above array substrates, the same technical problem can be solved, and the same technical effect is produced.
  • FIG. 3 is a flowchart of a pixel circuit driving method according to an embodiment of the present disclosure, for driving the pixel circuit shown in FIG. 1 .
  • the method includes:
  • Step S11 In the pre-charging stage, under the control of the scanning signal and the lighting control signal, the power supply voltage is written into the first node, and the first node is connected to the control electrode of the driving transistor.
  • Step S12 In the reset phase, the potential of the first node is lowered under the control of the reference signal.
  • Step S13 In the data writing phase, the data voltage is written to the first node under the control of the scan signal, so that the potential of the first node is equal to the sum of the data voltage and the threshold voltage of the driving transistor.
  • Step S14 In the light emitting phase, under the control of the light emission control signal, the power source and the light emitting unit are turned on by the driving transistor.
  • the light emission control signal of the pixel circuit of the Nth row and the reference signal of the pixel circuit of the (N+1)th row are the same signal, and N is a positive integer.
  • the illumination control signal is different from the reference signal by one phase, so that the illumination control signal of the pixel circuit of the Nth row and the reference signal of the pixel circuit of the (N+1)th row can be realized by the same signal.
  • sharing the signal it is possible to avoid the separate generation of the reference signal generation circuit and reduce the circuit area.
  • FIG. 4 is a timing diagram of control signals of a pixel circuit provided by an embodiment of the present disclosure. It should be noted that the timing chart shown in FIG. 4 is exemplified by the fact that each transistor is a P-type transistor, and the present disclosure is not limited thereto.
  • the timing of the control signal of the pixel circuit includes three stages of a precharge phase t1+t2, a reset phase t3, a data writing phase t4, and an illumination phase t5.
  • the reference signal is at a high level VGH
  • the scan signal is at a low level VGL
  • the illumination control signal is at a low level VGL
  • the data voltage is at a low level V1.
  • the first transistor T1 and the second transistor T2 are turned on, the power supply voltage Vdd is written to the first node N1, and the driving transistor 100 is turned off.
  • the fourth transistor T4 is turned off, and the data voltage is not written to the other end of the capacitor C1 (connected to one end of the reference signal).
  • the scan signal jumps to a high level VGH.
  • the second transistor T2 is turned off, and one end of the first node N1 is maintained at a high potential Vdd by the capacitor C1.
  • the reference signal jumps to a low level V1, at which point the capacitor C1
  • the potential at the other end drops from VGH to V1.
  • the potential at one end of capacitor C1 also drops accordingly, from Vdd to Vdd+V1-VGH.
  • the light emission control signal jumps to the high potential VGH, so the first transistor T1 and the third transistor T3 are turned off, and the data voltage is jumped from V1 to the high potential Vdata.
  • the scan signal is hopped from VGH to VGL.
  • the second transistor T2, the third transistor T3 and the driving transistor 100 are turned on, and the second transistor T2 and the driving transistor 100 form a diode connection. Since the second pole potential of the driving transistor 100 is greater than the first potential, the driving transistor 100 is reverse-conducted, and the data voltage is written to the N1 node until the first node N1 reaches Vdata+Vth, and the driving transistor 100 is turned off. .
  • the scan signal is hopped from VGL to VGH, the illuminating control signal is changed from VGH to VGL, and the first transistor T1, the driving transistor 100, the fourth transistor T4, and the fifth transistor T5 are turned on, and the second transistor T2 and the third transistor T3 are turned off, the potential of the first node N1 is unchanged, and the power source and the light emitting unit OLED are turned on by the driving transistor 100.
  • the scan signal includes two pulses, and the previous one of the two pulses is used to control the precharge sub-circuit to write the power supply voltage to the first node, the latter of the two pulses.
  • the pulse is used to control the data write subcircuit to write the data voltage to the first node, each cycle including a precharge phase, a reset phase, a data write phase, and an illumination phase.
  • the scan signal can include two low level pulses.
  • the pixel driving method provided by the embodiment of the present disclosure has the corresponding technical features of any of the above pixel circuits, the same technical problem can be solved, and the same technical effect is produced.
  • a person skilled in the art may understand that all or part of the steps of implementing the above embodiments may be completed by hardware, or may be instructed by a program to execute related hardware, and the program may be stored in a computer readable storage medium.
  • the storage medium mentioned may be a read only memory, a magnetic disk or an optical disk or the like.

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Abstract

一种像素电路及其驱动方法、阵列基板以及显示装置。像素电路包括：驱动晶体管（100）；预充电子电路（101），配置成在预充电阶段（t1+t2），在扫描信号和发光控制信号的控制下，将电源电压（Vdd）写入第一节点（N1），第一节点（N1）与驱动晶体管（100）的控制极连接；复位子电路（102），配置成在复位阶段（t3），在参考信号的控制下降低第一节点（N1）的电位；数据写入子电路（103），配置成在数据写入阶段（t4），在扫描信号的控制下将数据电压（Vdata）写入第一节点（N1），使第一节点（N1）的电位等于数据电压（Vdata）与驱动晶体管（100）的阈值电压之和；发光控制子电路（104），配置成在发光阶段（t5），在发光控制信号的控制下，将电源与发光单元通过驱动晶体管（100）导通。

Description

像素电路及其驱动方法、阵列基板以及显示装置
相关申请
本申请要求享有2016年9月26日提交的中国专利申请No.201610853395.9的优先权，其全部公开内容通过引用并入本文。
技术领域
本公开涉及半导体技术领域，特别涉及一种像素电路及其驱动方法、阵列基板以及显示装置。
背景技术
目前，显示器主要包括薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)和有机发光二极管(Organic Light-emitting Diode，简称OLED)显示器两大类。
与TFT-LCD利用电压来控制显示的亮度不同，OLED显示器属于电流驱动，需要稳定的电流来控制OLED的亮度。实现时，OLED显示器通过像素电路来进行OLED的亮度控制。
例如，一种已知的2T1C(2个晶体管和1个电容)像素电路包括开关晶体管T1、驱动晶体管T2、和存储电容Cs，其中，T1的控制极连接栅线，其第一极连接数据线，其第二极连接T2的控制极；T2的第一极连接电源电压Vdd，第二极连接OLED的阳极；OLED的阴极接地；存储电容Cs并联在T2的栅源之间。当开始当前像素的扫描时，栅线提供的电压Vgate为低电平时(以开关晶体管T1为P型晶体管为例)，T1导通，将数据线上提供的数据电压Vdata写入存储电容Cs。当该扫描结束后，Vgate变高，T1关断。通过存储在Cs上的数据电压导通T2，从而驱动OLED发光。T2的驱动电流，即OLED的工作电流可以表示为IOLED＝K(Vgs-Vth)2，其中Vgs为T2的栅源电压，Vth为T2的阈值电压，K为系数，具体K＝μCoxW/(2L)，μ为载流子迁移率，Cox为栅电位面积电容，W、L分别为T2的沟道宽度和长度。
由于工艺制程和器件老化等原因，各像素点的驱动TFT的阈值电压Vth会存在差异，并且随着使用会产生漂移，这样就导致了即便相同的栅源电压Vgs施加在驱动晶体管上，产生的电流IOLED也会因Vth 的变化而变化，从而影响显示的均匀性。
发明内容
本公开实施例提供了一种像素电路及其驱动方法、阵列基板以及显示装置。
在一个方面中，本公开实施例提供了一种像素电路，所述像素电路包括：
驱动晶体管；
预充电子电路，配置成在预充电阶段，在扫描信号和发光控制信号的控制下，将电源电压写入第一节点，所述第一节点与所述驱动晶体管的控制极连接；
复位子电路，配置成在复位阶段，在参考信号的控制下降低所述第一节点的电位；
数据写入子电路，配置成在数据写入阶段，在扫描信号的控制下将数据电压写入所述第一节点，使所述第一节点的电位等于所述数据电压与所述驱动晶体管的阈值电压之和；
发光控制子电路，配置成在发光阶段，在发光控制信号的控制下，将电源与发光单元通过所述驱动晶体管导通。
在本公开实施例的一种实现方式中，所述预充电子电路包括第一晶体管和第二晶体管，所述第一晶体管的控制极与发光控制线连接，所述第一晶体管的第一极与电源线连接，所述第一晶体管的第二极与所述驱动晶体管的第一极连接，所述第二晶体管的控制极与栅线连接，所述第二晶体管的第一极与所述驱动晶体管的第一极连接，所述第二晶体管的第二极与所述驱动晶体管的控制极连接，所述发光控制线配置成输出所述发光控制信号，所述电源线配置成输出所述电源的电源电压，所述栅线配置成输出所述扫描信号。
在本公开实施例的一种实现方式中，所述复位子电路包括电容，所述电容的一端与所述驱动晶体管的控制极连接，所述电容的另一端与参考信号线连接，所述参考信号线配置成输出所述参考信号。
在本公开实施例的一种实现方式中，所述数据写入子电路包括第三晶体管和第四晶体管，所述第三晶体管的控制极与所述栅线连接，所述第三晶体管的第一极与数据线连接，所述第三晶体管的第二极与 所述驱动晶体管的第二极连接，所述第四晶体管的控制极与所述参考信号线连接，所述第四晶体管的第一极与所述驱动晶体管的第二极连接，所述第四晶体管的第二极与所述发光控制子电路连接，所述数据线配置成输出所述数据电压。
在本公开实施例的一种实现方式中，所述发光控制子电路包括第五晶体管，所述第五晶体管的控制极与所述发光控制线连接，所述第五晶体管的第一极与所述第四晶体管的第二极连接，所述第五晶体管的第二极与所述发光单元连接。
在本公开实施例的一种实现方式中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管和所述驱动晶体管为薄膜晶体管。
在本公开实施例的一种实现方式中，在每个周期内，所述扫描信号包括两个脉冲，所述两个脉冲中的前一个脉冲配置成控制所述预充电子电路将电源电压写入第一节点，所述两个脉冲中的后一个脉冲配置成控制所述数据写入子电路将数据电压写入所述第一节点，所述每个周期包括所述预充电阶段、复位阶段、数据写入阶段和发光阶段。
在本公开实施例的一种实现方式中，在每个周期内，所述发光控制信号包括一个脉冲，所述脉冲配置成控制发光控制子电路将电源与发光单元通过驱动晶体管导通，所述每个周期包括所述预充电阶段、复位阶段、数据写入阶段和发光阶段。
在另一方面中，本公开实施例还提供了一种阵列基板，所述阵列基板包括多行上述任一种像素电路。
在本公开实施例的一种实现方式中，第N行像素电路的发光控制线与第N+1行像素电路的参考信号线相连，N为正整数。
在又一方面中，本公开实施例还提供了一种显示装置，所述显示装置包括上述任一种阵列基板。
在另外的方面中，本公开实施例还提供了一种像素电路驱动方法，用于驱动上述的像素电路，所述方法包括：
在预充电阶段，在扫描信号和发光控制信号的控制下，将电源电压写入第一节点，所述第一节点与驱动晶体管的控制极连接；
在复位阶段，在参考信号的控制下降低所述第一节点的电位；
在数据写入阶段，在扫描信号的控制下将数据电压写入所述第一 节点，使所述第一节点的电位等于所述数据电压与所述驱动晶体管的阈值电压之和；
在发光阶段，在发光控制信号的控制下，将电源与发光单元通过所述驱动晶体管导通。
在本公开实施例的一种实现方式中，在每个周期内，所述扫描信号包括两个脉冲，所述两个脉冲中的前一个脉冲配置成将电源电压写入第一节点，所述两个脉冲中的后一个脉冲配置成将数据电压写入所述第一节点，所述每个周期包括所述预充电阶段、复位阶段、数据写入阶段和发光阶段。
在另外的方面中，本公开实施例提供了一种阵列基板的驱动方法，用于驱动上述阵列基板，所述方法包括使用上述像素电路驱动方法逐行驱动阵列基板的像素电路。
在本公开实施例的一种实现方式中，第N行像素电路的发光控制信号与第N+1行像素电路的参考信号为同一信号，N为正整数。
在本公开实施例的一种实现方式中，在每个周期内，所述扫描信号包括两个脉冲，所述两个脉冲中的前一个脉冲配置成将电源电压写入第一节点，所述两个脉冲中的后一个脉冲配置成将数据电压写入所述第一节点，所述每个周期包括所述预充电阶段、复位阶段、数据写入阶段和发光阶段。
在本公开的实施例中，通过预充电子电路将电源电压写入第一节点，然后通过复位子电路降低第一节点的电位，再通过数据写入子电路将数据电压写入第一节点，使第一节点的电位等于数据电压与驱动晶体管的阈值电压之和，最后将电源与发光单元通过驱动晶体管导通，从而驱动发光单元发光。由于在驱动晶体管导通前第一节点的电位等于数据电压Vdata和阈值电压Vth之和Vdata+Vth，因此当通过电源电压驱动显示器件发光时，驱动晶体管第一极和第二极间的电流(也即流过OLED电流)：Ids＝K(Vgs-Vth)2＝K(Vdata+Vth-Vdd-Vth)2＝K(Vdata-Vdd)2。根据该公式可以看出流过OLED的电流不受阈值电压Vth影响，从而实现了对阈值电压Vth的补偿。此外，在该像素电路工作过程中，通过预充电子电路和复位子电路写入和降低第一节点的电位，可以实现像素电路的复位，因而无需采用单独的复位电路产生复位信号以实现复位。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种像素电路的结构示意图；
图2是本公开实施例提供的像素电路的一种具体实现电路的结构示意图；
图3是本公开实施例提供的一种像素驱动方法的流程图；
图4是本公开实施例提供的像素电路的一种控制信号的时序图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
本公开实施例提供了一种像素电路，用于驱动有机发光二极管发光，参见图1，该像素电路包括：驱动晶体管100、预充电子电路101、复位子电路102、数据写入子电路103和发光控制子电路104。
预充电子电路101配置成在预充电阶段，在扫描信号和发光控制信号的控制下，将电源电压写入第一节点，第一节点与驱动晶体管100的控制极连接。复位子电路102配置成在复位阶段，在参考信号的控制下降低第一节点的电位；数据写入子电路103配置成在数据写入阶段，在扫描信号的控制下将数据电压写入第一节点，使第一节点的电位等于数据电压与驱动晶体管100的阈值电压之和。发光控制子电路104配置成在发光阶段，在发光控制信号的控制下，将电源与发光单元OLED通过驱动晶体管100导通，使得发光单元OLED发光。
如图1所示，扫描信号由栅线gate提供，发光控制信号由发光控制线em提供，电源电压由电源线Vdd提供，电源线Vdd与电源连接，并且数据电压由数据线data提供，参考信号由参考信号线ref提供。
本公开的实施例通过预充电子电路将电源电压写入第一节点，然后通过复位子电路降低第一节点的电位，再通过数据写入子电路将数据电压写入第一节点，使第一节点的电位等于数据电压与驱动晶体管 的阈值电压之和，最后将电源与发光单元通过驱动晶体管导通，从而驱动发光单元发光。由于在驱动晶体管导通前第一节点的电位等于数据电压Vdata和阈值电压Vth之和Vdata+Vth，因此当通过电源电压驱动显示器件发光时，驱动晶体管第一极和第二极间的电流(也即流过OLED电流)：Ids＝K(Vgs-Vth)2＝K(Vdata+Vth-Vdd-Vth)2＝K(Vdata-Vdd)2。根据该公式可以看出流过OLED的电流不受阈值电压Vth影响，从而实现了对阈值电压Vth的补偿。此外，在该像素电路工作过程中，通过预充电子电路和复位子电路写入和降低第一节点的电位，可以实现像素电路的复位，因而无需采用单独的复位电路产生复位信号以实现复位。
具体地，参见图2，预充电子电路101可以包括第一晶体管T1和第二晶体管T2，其中第一晶体管T1的控制极与发光控制线em连接，第一晶体管T1的第一极与电源线Vdd连接，第一晶体管T1的第二极与驱动晶体管100的第一极连接，并且第二晶体管T2的控制极与栅线gate连接，第二晶体管T2的第一极与驱动晶体管100的第一极连接，第二晶体管T2的第二极与驱动晶体管100的控制极连接。预充电子电路101通过发光控制线em输出的发光控制信号控制T1，通过栅线gate输出的扫描信号控制T2，T1、T2导通以实现电源电压输入，其中第一节点N1电位为Vdd。
参见图2，复位子电路102可以包括电容C1，电容C1的一端与驱动晶体管100的控制极连接，电容C1的另一端与参考信号线ref连接。复位子电路102通过参考信号降低C1的所述另一端的电位(由VGH降低至V1)，由于电容C1的自举作用，使得C1的所述一端电位降低(由Vdd降低至Vdd+V1-VGH)，进而实现第一节点N1电位的降低。
参见图2，数据写入子电路103可以包括第三晶体管T3和第四晶体管T4，其中第三晶体管T3的控制极与栅线gate连接，第三晶体管T3的第一极与数据线data连接，第三晶体管T3的第二极与驱动晶体管100的第二极连接，并且第四晶体管T4的控制极与参考信号线ref连接，第四晶体管T4的第一极与驱动晶体管100的第二极连接，第四晶体管T4的第二极与发光控制子电路104连接。数据写入子电路103通过栅线gate输出的扫描信号控制第三晶体管T3导通，通过发光控制线em输出的发光控制信号控制第五晶体管T5关断，从而保证充电。 充电时，T2和驱动晶体管100分别形成二极管连接。此时，第一节点N1电位为低电平Vdd+V1-VGH，数据信号通过T3到达驱动晶体管100的第二极。由于数据信号的电压Vdata为高电位，因此驱动晶体管100反向导通，Vdata通过T2充电到第一节点N1，直到第一节点N1的电位达到Vdata+Vth时，驱动晶体管100关断，完成充电。
参见图2，发光控制子电路104包括第五晶体管T5，第五晶体管T5的控制极与发光控制线em连接，第五晶体管T5的第一极与第四晶体管T4的第二极连接，第五晶体管T5的第二极与发光单元OLED连接。发光控制子电路104通过发光控制线em输出的发光控制信号控制第一晶体管T1和第五晶体管T5导通，T3第一极电位大于控制极，T3导通，导通后驱动晶体管100的第一极电位大于控制极，驱动晶体管100导通，此时T1、T4、驱动晶体管100、T5全部导通，从而实现电源和发光单元导通。
参见图2，发光单元OLED一端通过T1、T4、驱动晶体管100、T5连接高电压Vdd，另一端连接低电压Vss，使得发光单元OLED在Vdd和Vss的作用下发光。
在本公开实施例的一种实现方式中，第N行像素电路的发光控制线em与第N+1行像素电路的参考信号线ref相连，并且连接到扫描驱动单元的同一输出信号线上，N为正整数。发光控制信号与参考信号相差一个相位，因此第N行像素电路的发光控制线em与第N+1行像素电路的参考信号线ref刚好可以满足上述要求。通过共用信号，可以避免单独制作参考信号的产生电路，减小电路面积。扫描驱动单元可以是栅极驱动(Gate On Array，简称GOA)单元。
在本公开实施例的一种实现方式中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和驱动晶体管100为薄膜晶体管。薄膜晶体管体积小、功耗低、控制方便准确。
可选地，驱动晶体管100可以为P沟道增强型金属氧化物半导体场效应晶体(Metal Oxide Semiconductor Field Effect Transistor，简称MOSFET)管，也可以为P型双极结型晶体(Bipolar Junction Transistor，简称BJT)管。
可选地，第一至第五晶体管T1-T5可以分别为结型场效应晶体(Junction Field Effect Transistor，简称JFET)管、增强型MOSFET管、 耗尽型MOSFET管和BJT管中的一种或多种。
本实施例前文对各个信号的大小的描述均在P型晶体管的基础上作出的，即第一至第五晶体管T1-T5和驱动晶体管均为P型晶体管。当然，本公开实施例并不限制如此，第一至第五晶体管T1-T5和驱动晶体管也可以为N型晶体管。当上述晶体管(第一至第五晶体管T1-T5和驱动晶体管)为P型晶体管时，上述晶体管的控制极电压小于第二极电压时，上述晶体管导通；当上述第五晶体管为N型晶体管时，上述晶体管的控制极电压大于第二极电压时，上述晶体管导通。
在每个周期内，发光控制信号包括一个脉冲，该脉冲用于控制发光控制子电路104将电源与发光单元通过驱动晶体管导通。
在每个周期内，扫描信号包括两个脉冲，两个脉冲中的前一个脉冲用于控制预充电子电路101将电源电压写入第一节点，两个脉冲中的后一个脉冲用于控制数据写入子电路103将数据电压写入第一节点，其中每个周期包括预充电阶段、复位阶段、数据写入阶段和发光阶段。
相应地，当上述晶体管为P型晶体管时，扫描信号包括两个低电平脉冲，发光控制信号包括一个高电平脉冲。上述晶体管为N型晶体管时，扫描信号包括两个高电平脉冲，发光控制信号包括一个低电平脉冲。
当扫描信号包括两个低电平脉冲，发光控制信号包括一个高电平脉冲时，扫描信号和发光控制信号可以同时采用扫描驱动单元产生，从而减少驱动信号产生电路。扫描驱动单元主要包括栅极移位寄存器，栅极移位寄存器可以产生VGH和VGL两种电平信号。在本公开实施例中，发光控制信号可以采用高电平VGH实现，扫描信号可以采用低电平VGL实现(例如通过时序信号控制每个周期输出两个低电平VGL脉冲)。
本公开实施例提供了一种阵列基板，该阵列基板包括图1或图2提供的像素电路。
由于本公开实施例提供的阵列基板与上述像素电路具有相同的技术特征，所以也能解决同样的技术问题，产生相同的技术效果。
本公开实施例还提供了一种显示装置，该显示装置包括上述任一种阵列基板。该显示装置可以为：电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显 示功能的产品或部件。
由于本公开实施例提供的显示装置与上述任一种阵列基板具有相同的技术特征，所以也能解决同样的技术问题，产生相同的技术效果。
图3是本公开实施例提供的一种像素电路驱动方法的流程图，用于驱动图1所示的像素电路，参见图3，该方法包括：
步骤S11：在预充电阶段，在扫描信号和发光控制信号的控制下，将电源电压写入第一节点，第一节点与驱动晶体管的控制极连接。
步骤S12：在复位阶段，在参考信号的控制下降低第一节点的电位。
步骤S13：在数据写入阶段，在扫描信号的控制下将数据电压写入第一节点，使第一节点的电位等于数据电压与驱动晶体管的阈值电压之和。
步骤S14：在发光阶段，在发光控制信号的控制下，将电源与发光单元通过驱动晶体管导通。
在本公开实施例中，第N行像素电路的发光控制信号与第N+1行像素电路的参考信号为同一信号，N为正整数。发光控制信号与参考信号相差一个相位，因此第N行像素电路的发光控制信号与第N+1行像素电路的参考信号刚好可以采用同一信号实现。通过共用信号，可以避免单独制作参考信号的产生电路，减小电路面积。
图4是本公开实施例提供的像素电路的控制信号的时序图。需要说明的是，图4所示的时序图以各晶体管均为P型晶体管为例，本公开并不限制于此。
如图4所示，该像素电路的控制信号的时序包括预充电阶段t1+t2、复位阶段t3、数据写入阶段t4、发光阶段t5三个阶段。
在预充电阶段t1时间内，参考信号为高电平VGH，扫描信号为低电平VGL，发光控制信号为低电平VGL，数据电压为低电平V1。此时第一晶体管T1和第二晶体管T2导通，电源电压Vdd被写入第一节点N1，驱动晶体管100关断。另外，第四晶体管T4关断，数据电压不会写入到电容C1的另一端(接参考信号的一端)。
在预充电阶段t2时间内，扫描信号跳变为高电平VGH，此时，第二晶体管T2关断，第一节点N1的一端在电容C1的作用下，电位保持在高电位Vdd。
在复位阶段t3时间内，参考信号跳变为低电平V1，此时电容C1 另一端电位由VGH下降到V1，相应地，由于电容C1的自举作用，电容C1的一端的电位也相应下降，由Vdd下降至Vdd+V1-VGH。发光控制信号跳变为高电位VGH，因此第一晶体管T1、第三晶体管T3关断，数据电压由V1跳变至高电位Vdata。
在数据写入阶段t4时间内，扫描信号由VGH跳变至VGL，此时，第二晶体管T2、第三晶体管T3和驱动晶体管100导通，第二晶体管T2和驱动晶体管100形成二极管连接。由于此时，驱动晶体管100第二极电位大于第一极电位，因此驱动晶体管100反向导通，数据电压被写入到N1节点，直到第一节点N1电位达到Vdata+Vth时驱动晶体管100关断。
在发光阶段t5时间内，扫描信号由VGL跳变至VGH，发光控制信号由VGH跳变为VGL，第一晶体管T1、驱动晶体管100、第四晶体管T4和第五晶体管T5导通，第二晶体管T2和第三晶体管T3关断，第一节点N1电位不变，电源与发光单元OLED通过驱动晶体管100导通。此时，驱动晶体管100的电流Ids＝K(Vgs-Vth)2＝K(Vdata+Vth-Vdd-Vth)2＝K(Vdata-Vdd)2，根据该公式可以看出流过OLED的电流不受阈值电压Vth影响。
如图4所示，在每个周期内，扫描信号包括两个脉冲，两个脉冲中的前一个脉冲用于控制预充电子电路将电源电压写入第一节点，两个脉冲中的后一个脉冲用于控制数据写入子电路将数据电压写入第一节点，每个周期包括预充电阶段、复位阶段、数据写入阶段和发光阶段。
如图4所示，扫描信号可以包括两个低电平脉冲。
由于本公开实施例提供的像素驱动方法与上述任一种像素电路具有相应的技术特征，所以也能解决同样的技术问题，产生相同的技术效果。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
以上所述仅为本公开的示例性实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (17)

  1. 一种像素电路，包括：
    驱动晶体管；
    预充电子电路，配置成在预充电阶段，在扫描信号和发光控制信号的控制下，将电源电压写入第一节点，所述第一节点与所述驱动晶体管的控制极连接；
    复位子电路，配置成在复位阶段，在参考信号的控制下降低所述第一节点的电位；
    数据写入子电路，配置成在数据写入阶段，在所述扫描信号的控制下将数据电压写入所述第一节点，使所述第一节点的电位等于所述数据电压与所述驱动晶体管的阈值电压之和；
    发光控制子电路，配置成在发光阶段，在所述发光控制信号的控制下，将电源与发光单元通过所述驱动晶体管导通。
  2. 根据权利要求1所述的像素电路，其中，所述预充电子电路包括第一晶体管和第二晶体管，所述第一晶体管的控制极与发光控制线连接，所述第一晶体管的第一极与电源线连接，所述第一晶体管的第二极与所述驱动晶体管的第一极连接，所述第二晶体管的控制极与栅线连接，所述第二晶体管的第一极与所述驱动晶体管的第一极连接，所述第二晶体管的第二极与所述驱动晶体管的控制极连接，所述发光控制线配置成输出所述发光控制信号，所述电源线配置成输出所述电源的电源电压，所述栅线配置成输出所述扫描信号。
  3. 根据权利要求1所述的像素电路，其中，所述复位子电路包括电容，所述电容的一端与所述驱动晶体管的控制极连接，所述电容的另一端与参考信号线连接，所述参考信号线配置成输出所述参考信号。
  4. 根据权利要求1所述的像素电路，其中，所述数据写入子电路包括第三晶体管和第四晶体管，所述第三晶体管的控制极与所述栅线连接，所述第三晶体管的第一极与数据线连接，所述第三晶体管的第二极与所述驱动晶体管的第二极连接，所述第四晶体管的控制极与所述参考信号线连接，所述第四晶体管的第一极与所述驱动晶体管的第二极连接，所述第四晶体管的第二极与所述发光控制子电路连接，所述数据线配置成输出所述数据电压。
  5. 根据权利要求1所述的像素电路，其中，所述发光控制子电路包括第五晶体管，所述第五晶体管的控制极与所述发光控制线连接，所述第五晶体管的第一极与所述第四晶体管的第二极连接，所述第五晶体管的第二极与所述发光单元连接。
  6. 根据权利要求1所述的像素电路，其中，所述预充电子电路包括第一晶体管和第二晶体管，所述第一晶体管的控制极与发光控制线连接，所述第一晶体管的第一极与电源线连接，所述第一晶体管的第二极与所述驱动晶体管的第一极连接，所述第二晶体管的控制极与栅线连接，所述第二晶体管的第一极与所述驱动晶体管的第一极连接，所述第二晶体管的第二极与所述驱动晶体管的控制极连接，所述发光控制线配置成输出所述发光控制信号，所述电源线配置成输出所述电源的电源电压，所述栅线配置成输出所述扫描信号；
    所述复位子电路包括电容，所述电容的一端与所述驱动晶体管的控制极连接，所述电容的另一端与参考信号线连接，所述参考信号线配置成输出所述参考信号；
    所述数据写入子电路包括第三晶体管和第四晶体管，所述第三晶体管的控制极与所述栅线连接，所述第三晶体管的第一极与数据线连接，所述第三晶体管的第二极与所述驱动晶体管的第二极连接，所述第四晶体管的控制极与所述参考信号线连接，所述第四晶体管的第一极与所述驱动晶体管的第二极连接，所述第四晶体管的第二极与所述发光控制子电路连接，所述数据线配置成输出所述数据电压；并且
    所述发光控制子电路包括第五晶体管，所述第五晶体管的控制极与所述发光控制线连接，所述第五晶体管的第一极与所述第四晶体管的第二极连接，所述第五晶体管的第二极与所述发光单元连接。
  7. 根据权利要求6所述的像素电路，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管和所述驱动晶体管为薄膜晶体管。
  8. 根据权利要求1-7任一项所述的像素电路，其中，在每个周期内，所述扫描信号包括两个脉冲，所述两个脉冲中的前一个脉冲配置成控制所述预充电子电路将电源电压写入第一节点，所述两个脉冲中的后一个脉冲配置成控制所述数据写入子电路将数据电压写入所述第一节点，所述每个周期包括所述预充电阶段、复位阶段、数据写入阶 段和发光阶段。
  9. 根据权利要求1-7任一项所述的像素电路，其中，在每个周期内，所述发光控制信号包括一个脉冲，所述脉冲配置成控制发光控制子电路将电源与发光单元通过驱动晶体管导通，所述每个周期包括所述预充电阶段、复位阶段、数据写入阶段和发光阶段。
  10. 一种阵列基板，包括多行权利要求1-9任一项所述的像素电路。
  11. 根据权利要求10所述的阵列基板，其特征在于，第N行像素电路的发光控制线与第N+1行像素电路的参考信号线相连，N为正整数。
  12. 一种显示装置，包括权利要求10或11所述的阵列基板。
  13. 一种像素电路驱动方法，用于驱动权利要求1所述的像素电路，所述方法包括：
    在预充电阶段，在扫描信号和发光控制信号的控制下，将电源电压写入第一节点，所述第一节点与驱动晶体管的控制极连接；
    在复位阶段，在参考信号的控制下降低所述第一节点的电位；
    在数据写入阶段，在所述扫描信号的控制下将数据电压写入所述第一节点，使所述第一节点的电位等于所述数据电压与所述驱动晶体管的阈值电压之和；
    在发光阶段，在所述发光控制信号的控制下，将电源与发光单元通过所述驱动晶体管导通。
  14. 根据权利要求13所述的方法，其中，在每个周期内，所述扫描信号包括两个脉冲，所述两个脉冲中的前一个脉冲配置成将电源电压写入第一节点，所述两个脉冲中的后一个脉冲配置成将数据电压写入所述第一节点，所述每个周期包括所述预充电阶段、复位阶段、数据写入阶段和发光阶段。
  15. 一种阵列基板的驱动方法，用于驱动权利要求10所述的阵列基板，所述方法包括使用权利要求13所述的方法逐行驱动阵列基板的像素电路。
  16. 根据权利要求15所述的方法，其中，第N行像素电路的发光控制信号与第N+1行像素电路的参考信号为同一信号，N为正整数。
  17. 根据权利要求15所述的方法，其中，在每个周期内，所述扫描信号包括两个脉冲，所述两个脉冲中的前一个脉冲配置成将电源电 压写入第一节点，所述两个脉冲中的后一个脉冲配置成将数据电压写入所述第一节点，所述每个周期包括所述预充电阶段、复位阶段、数据写入阶段和发光阶段。
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