WO2020062811A1 - 像素电路及其驱动方法、显示面板、显示装置 - Google Patents

像素电路及其驱动方法、显示面板、显示装置 Download PDF

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Publication number
WO2020062811A1
WO2020062811A1 PCT/CN2019/079622 CN2019079622W WO2020062811A1 WO 2020062811 A1 WO2020062811 A1 WO 2020062811A1 CN 2019079622 W CN2019079622 W CN 2019079622W WO 2020062811 A1 WO2020062811 A1 WO 2020062811A1
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Prior art keywords
transistor
light
pixel circuit
voltage
capacitor
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PCT/CN2019/079622
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English (en)
French (fr)
Inventor
朱正勇
范龙飞
朱晖
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昆山国显光电有限公司
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Publication of WO2020062811A1 publication Critical patent/WO2020062811A1/zh
Priority to US16/841,713 priority Critical patent/US10984722B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0216—Interleaved control phases for different scan lines in the same sub-field, e.g. initialization, addressing and sustaining in plasma displays that are not simultaneous for all scan lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness

Definitions

  • the present application relates to the field of display, and in particular, to a pixel circuit and a driving method thereof, a display panel, and a display device.
  • Organic light-emitting display panels are increasingly used in the display field because of their advantages such as high contrast, low power consumption, wide viewing angle, and fast response speed.
  • an organic light emitting display panel includes pixel circuits arranged in an array.
  • the pixel circuit usually includes a plurality of light emitting diodes and a power source, and the current flowing through the light emitting diodes is related to the power supply voltage.
  • the display panel since the distance between each light emitting diode and the power source is different, the voltage drop on the line generated during the voltage transmission is also different, and the actual power source voltage obtained by each light emitting diode is different. Therefore, the current flowing through each light-emitting diode is different, and the brightness of the light-emitting diode is also different, resulting in uneven light emission brightness of the display panel.
  • the present application provides a pixel circuit, a driving method thereof, a display panel, and a display device.
  • a pixel circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a capacitor, and a light emitting diode;
  • the control terminal of the fourth transistor is used for inputting the first scanning signal;
  • the first pole of the fourth transistor is respectively connected to the second pole of the third transistor, the control terminal of the first transistor, and the first plate of the capacitor;
  • the second pole is connected to the second pole of the seventh transistor and is used for inputting the first reference voltage;
  • the control terminal of the third transistor is used to input a second scanning signal.
  • the first pole of the third transistor is connected to the second pole of the first transistor and the first pole of the sixth transistor, respectively.
  • the first pole of the first transistor is used to input the first pole.
  • the control terminal of the sixth transistor is used to input a first light-emitting control signal.
  • the second pole of the sixth transistor is respectively connected to the anode of the light-emitting diode and the first pole of the seventh transistor.
  • the cathode of the light-emitting diode is used to input the second power supply voltage.
  • the control terminal of the seven transistors is used to input a first scanning signal;
  • the control terminal of the second transistor is used to input a second scanning signal
  • the first pole of the second transistor is used to input a data voltage
  • the second pole of the second transistor is respectively connected to the second plate of the capacitor and the second pole of the fifth transistor.
  • the control terminal of the fifth transistor is used to input a second light-emitting control signal, and the first pole of the fifth transistor is used to input a second reference voltage.
  • the voltage value of the first reference voltage is less than the voltage value of the second power voltage.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are all P-type transistors or all N-type transistors.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor include a low temperature polysilicon thin film transistor, an oxide semiconductor thin film transistor, and an amorphous silicon thin film. Any of the transistors.
  • the second to seventh transistors are all switching transistors, and the first transistor is a driving transistor.
  • the capacitor is an energy storage capacitor
  • the light emitting diode is an organic light emitting diode
  • control terminal of each transistor is the gate of the transistor, the source of the first pole of each transistor, and the drain of the second pole of each transistor.
  • the first power supply voltage is a positive voltage and the second power supply voltage is a negative voltage.
  • a display panel includes a plurality of pixel circuits arranged in a matrix, wherein the pixel circuits are the above-mentioned pixel circuits.
  • a display device includes the display panel as described above.
  • a driving method of a pixel circuit includes a pixel circuit as described above, and the driving method includes:
  • the first scanning signal and the second light-emitting control signal are set as low-level signals, the second scanning signal and the first light-emitting control signal are set as high-level signals, and the first reference voltage initializes the pixel circuit;
  • the second scanning signal is set as a low-level signal
  • the first scanning signal, the first light-emitting control signal, and the second light-emitting control signal are set as high-level signals, and the data voltage is written into the pixel circuit;
  • the first light-emitting control signal and the second light-emitting control signal are set as low-level signals, and the first scanning signal and the second scanning signal are set as high-level signals, and the light-emitting diode emits light.
  • the first scan signal controls the fourth transistor and the seventh transistor to be turned on
  • the first reference voltage initializes the control terminal of the first transistor and the first plate of the capacitor through the fourth transistor, and the first transistor is turned on; the first reference voltage initializes the anode of the light emitting diode through the seventh transistor; and
  • the second light-emitting control signal controls the fifth transistor to turn on, and the second reference voltage initializes the second plate of the capacitor through the fifth transistor.
  • the voltage value of the first reference voltage is smaller than the voltage value of the second power voltage to ensure that the light emitting diode does not emit light during the initialization phase.
  • the second scan signal controls the second transistor to be turned on, and the data voltage is written to the second plate of the capacitor through the second transistor.
  • the second light-emitting control signal controls the fifth transistor to be turned on, and the second reference voltage compensates the first transistor through the fifth transistor and the capacitor, so that the current flowing through the first transistor and the The first supply voltage is irrelevant.
  • the control method of the pixel circuit compensates for the current-resistance voltage drop on the first power supply line by increasing the second reference voltage, and also compensates the influence of the threshold voltage on the light-emitting current, thereby improving the uniformity of the screen body's light emission.
  • FIG. 1 is a schematic diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 2 is a timing diagram of a method for controlling a pixel circuit according to an embodiment of the present application.
  • an embodiment of the present application provides a pixel circuit including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor.
  • T7 capacitor C1 and light emitting diode D1.
  • the first to seventh transistors T1 to T7 each include a control terminal, a first electrode, and a second electrode.
  • the pixel circuit further includes a first scan signal input terminal, a second scan signal input terminal, a first light emission control signal input terminal, a second light emission control signal input terminal, and a data signal input terminal.
  • the first scan signal input terminal is respectively connected to the control terminal of the fourth transistor T4 and the control terminal of the seventh transistor T7, and is used to input the first scan signal SCNA1.
  • the second scanning signal input terminal is respectively connected to the control terminals of the second transistor T2 and the third transistor T3, and is used for inputting the second scanning signal SCAN2.
  • the first light emission control signal input terminal is connected to the control terminal of the sixth transistor T6 and is used to input the first light emission control signal EM1.
  • the second light emission control signal input terminal is connected to the control terminal of the fifth transistor T5 and is used to input the second light emission control signal EM2.
  • the first light emission control signal EM1 is different from the second light emission control signal EM2, so the port of the first light emission control signal input terminal and the port of the second light emission control signal input terminal are also different.
  • the data signal input terminal is connected to the first pole of the second transistor T2 and is used to input a data voltage Vdata.
  • the control terminal of the fourth transistor T4 is used to input the first scan signal SCNA1, and the first pole of the fourth transistor T4 is respectively connected to the second pole of the third transistor T3, the control terminal of the first transistor T1, and the first terminal of the capacitor C1.
  • a pole plate; the second pole of the fourth transistor T4 is connected to the second pole of the seventh transistor T7, and is used for inputting the first reference voltage Vref1.
  • the control terminal of the third transistor T3 is used to input the second scan signal SCAN2.
  • the first pole of the third transistor T3 is connected to the second pole of the first transistor T1 and the first pole of the sixth transistor T6, respectively.
  • a first pole of the first transistor T1 is used to input a first power supply voltage VDD.
  • the control terminal of the sixth transistor T6 is used to input the first light-emitting control signal EM1, and the second pole of the sixth transistor T6 is respectively connected to the anode of the light-emitting diode D1 and the first pole of the seventh transistor T7.
  • the cathode of the light emitting diode D1 is used to input a second power supply voltage VSS.
  • the control terminal of the seventh transistor T7 is used to input a first scan signal SCAN1.
  • the control terminal of the second transistor T2 is used to input the second scan signal SCAN2, the first pole of the second transistor T2 is used to input the data voltage Vdata, and the second pole of the second transistor T2 is connected to the second plate of the capacitor C1 and the first pole, respectively.
  • the control terminal of the fifth transistor T5 is used to input the second light-emitting control signal EM2, and the first pole of the fifth transistor T5 is used to input the second reference voltage Vref2.
  • the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all switching transistors
  • the first transistor T1 is a driving transistor.
  • the capacitor C1 is an energy storage capacitor
  • the light emitting diode D1 is an OLED (Organic Light-Emitting Diode).
  • the transistors in this embodiment are all P-type transistors. Specifically, the control terminal of each transistor is the gate of the transistor, the source of the first electrode of each transistor, and the drain of the second electrode of each transistor. When a low level is applied to the control terminal of the transistor, the transistor is turned on.
  • the transistor may be an N-type transistor. When an N-type transistor is used as a transistor in a pixel circuit, a high-level signal is input to the control terminal of the transistor to make it conductive.
  • the first scan signal SCAN1 can control the fourth transistor T4 and the seventh transistor T7 to be turned on, so that the first reference voltage Vref1 initializes the gate of the first transistor T1 and the anode of the light emitting diode D1.
  • the second scan signal SCAN2 can control the second transistor T2 to be turned on, so that the data voltage Vdata is written into the second plate of the capacitor C1 through the second transistor T2.
  • the second light-emitting control signal EM2 can control the fifth transistor T5 to be turned on, so that the second reference voltage Vref2 compensates the control terminal of the first transistor T1 through the capacitor C1.
  • the first power supply voltage VDD may be a positive voltage
  • the second power supply voltage VSS may be a negative voltage.
  • Driving the first transistor T1 can generate a current under the action of the first power supply voltage VDD. This current flows through the light emitting diode D1 to cause the light emitting diode D1 to emit light. When the light emitting diode D1 emits light, a current flows from the light emitting diode D1 to the second power source.
  • the pixel circuit provided in the above embodiment initializes the first and second plates of the capacitor C1 by setting the first and second light-emitting control signals EM1 and EM2 to ensure that the initial states of the pixel circuits are the same.
  • the second reference voltage Vref2 is used to compensate the control terminal of the first transistor T1 through the capacitor C1, so that the driving current flowing through the first transistor T1 is related to the second reference voltage Vref2 and has nothing to do with the first power supply voltage VDD. Since the driving current flows through the power supply line, the driving current is not affected by the current-resistance voltage drop on the power supply line when the driving current is not related to the first power supply voltage VDD, thereby improving the uniformity of the light emission of the screen.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all P-type transistors or all N-type transistors. Transistor.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a low temperature polysilicon thin film transistor, an oxide semiconductor Any of a thin film transistor and an amorphous silicon thin film transistor.
  • An embodiment of the present application provides a display panel including a plurality of the aforementioned pixel circuits arranged in an array.
  • the display panel also includes a data driver, a scan driver, and a light emitting controller.
  • One end of the first scanning signal line and the second scanning signal line are respectively connected to the first scanning signal input terminal and the second scanning signal input terminal of each row of pixel circuits, and the other ends are connected to the scanning driver.
  • the scan driver provides a scan signal and transmits it to the pixel circuit through the scan signal line.
  • One end of the data signal line is connected to the data signal input end of each column of pixel circuits, and the other end is connected to the data driver.
  • the data driver provides the data voltage and transmits it to the pixel circuit through the data signal line.
  • One end of the plurality of light-emitting control signal lines is connected to each row of pixel circuits, and the other end is connected to a light-emitting controller.
  • the light-emitting controller provides a light-emitting control signal and transmits it to the pixel circuit through the light-emitting control signal line.
  • An embodiment of the present application provides a display device including the above display panel.
  • FIG. 1 and FIG. 2 is a pixel circuit provided by an embodiment of the present application
  • FIG. 2 is a timing signal diagram for driving the pixel circuit shown in FIG. 1.
  • the driving method includes the following three stages:
  • the first scan signal SCAN1 and the second light-emitting control signal EM2 are low-level signals, and the second scan signal SCAN2 and the first light-emitting control signal EM1 are high-level signals, so that the first reference voltage Vref1 is The pixel circuit is initialized.
  • the second scan signal SCAN2 is a low-level signal
  • the first scan signal SCAN1, the first light-emitting control signal EM1, and the second light-emitting control signal EM2 are high-level signals, so that the data voltage Vdata is written into the pixel. Circuit.
  • the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are low-level signals, and the first scan signal SCAN1 and the second scan signal SCAN2 are high-level signals, so that the light-emitting diode D1 emits light.
  • both the first scan signal SCAN1 and the second light emission control signal EM2 are at a low level. Since the first scan signal input terminal is connected to the control terminals of the fourth transistor T4 and the seventh transistor T7, and the fourth transistor T4 and the seventh transistor T7 are P-type transistors, the first scan signal SCAN1 controls the fourth transistor T4 and the seventh transistor.
  • the transistor T7 is turned on.
  • the first reference voltage Vref1 initializes the control terminal of the first transistor T1 and the first plate of the capacitor C1 through the fourth transistor T4. At the same time, the first reference voltage Vref1 initializes the anode of the light emitting diode D1 through the seventh transistor T7.
  • the second light-emitting control signal input terminal is connected to the control terminal of the fifth transistor T5, and the fifth transistor T5 is a P-type transistor, the second light-emitting control signal EM2 controls the fifth transistor T5 to turn on, so that the second reference voltage Vref2 is connected to the capacitor
  • the second plate of C1 is initialized.
  • the first and second plates of the capacitor C1 are initialized, and the potentials of the first and second plates of the capacitor C1 are maintained at the first reference voltage Vref1 and the second, respectively.
  • the light emitting current flows to the second power source through the first power source, the first transistor T1, the sixth transistor T6, and the light emitting diode D1, the light emitting current does not flow through the first reference voltage line providing the first reference voltage Vref1 and the second reference voltage Vref2. Second reference voltage line. Therefore, there is no current-resistance voltage drop on the first reference voltage line and the second reference voltage line, so the initialization state of each pixel circuit is the same, and the uniformity of light emission of the screen body can be better ensured.
  • the second scan signal SCAN2 is a low-level signal.
  • the second scan signal input terminal is connected to the control terminal of the second transistor T2, and the second transistor T2 is a P-type transistor. Therefore, the second scan signal SCAN2 controls the second transistor T2 to be turned on.
  • the data voltage Vdata is written into the second plate of the capacitor C1 through the second transistor T2, so that the potential of the second plate of the capacitor C1 is Vdata. Since the first reference voltage Vref1 initializes the control terminal of the first transistor T1 during the initialization phase t1, the first transistor T1 is turned on.
  • the potential of the first electrode of the first transistor T1 is VDD, and the potential of the control terminal of the first transistor T1 is VDD-
  • both the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at a low level.
  • the second light emission control signal EM2 controls the fifth transistor T5 to be turned on, so that the second reference voltage Vref2 is written into the second plate of the capacitor C1. Because the first scan signal SCAN1 and the second scan signal SCAN2 are high-level signals, the fourth transistor T4 and the third transistor T3 are turned off, and the capacity of the capacitor C1 is much larger than the capacity of the parasitic capacitance of the other transistor. The voltage difference across the capacitor C1 constant. The potential of the second plate of the capacitor C1 changes from Vdata to Vref2.
  • the potential of the first plate of the capacitor C1 will also change accordingly, that is, the change of the potential of the first plate of the capacitor C1 is Vref2- Vdata.
  • the first plate of the capacitor C1 is connected to the control terminal of the first transistor T1. Therefore, the potential change of the control terminal of the first transistor T1 is Vref2-Vdata, and the potential of the control terminal of the first transistor T1 is: VDD-
  • + Vref2-Vdata. Since the potential of the first electrode of the first transistor T1 is VDD, the gate-source voltage of the first transistor T1 is: Vgs Vref2-Vdata-
  • -Vth.
  • the driving current flowing through the first transistor T1 is independent of the voltage VDD of the first power source, so the first power line can be eliminated The effect of current-resistance voltage drop on drive current.
  • the driving current is related to the second reference voltage Vref2, and the current flowing through the light-emitting diode D1 does not pass through the second reference voltage line, so the current-resistance voltage drop does not occur on the second reference voltage line, which can improve the screen body Luminous uniformity.
  • the first scan signal SCAN1 and the second light-emitting control signal EM2 are low-level signals
  • the second scan signal SCAN2 and the first light-emitting control signal EM1 are high-level signals.
  • the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are turned on, and the second transistor T2, the third transistor T3, and the sixth transistor T6 are turned off.
  • the first reference voltage Vref1 initializes the control terminal of the first transistor T1 and the first plate of the capacitor C1 through the fourth transistor T4.
  • the first reference voltage Vref1 may be a negative voltage, and the first reference voltage Vref1 acts on a control terminal of the first transistor T1 to make the first transistor T1 conductive. Since the seventh transistor T7 is turned on, the first reference voltage Vref1 initializes the anode of the light emitting diode D1. Since the fifth transistor T5 is turned on, the second reference voltage Vref2 initializes the second plate of the capacitor C1 through the fifth transistor T5.
  • the voltage value of the first reference voltage Vref1 is smaller than the voltage value of the second power supply voltage VSS to ensure that the light-emitting diode D1 does not emit light during initialization.
  • Initialization can eliminate the effect of the residual current from the previous light-emitting phase on the current light-emitting phase.
  • initializing the first electrode plate and the second electrode plate of the capacitor C1 can ensure that all the pixel circuits are in the same initial state and improve the uniformity of the light emission of the screen body.
  • the second scan signal SCAN2 is a low-level signal
  • the first scan signal SCAN1, the first light-emitting control signal EM1, and the second light-emitting control signal EM2 are high-level signals.
  • the second transistor T2 and the third transistor T3 are turned on, and during the initialization phase, the first transistor T1 is turned on.
  • the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.
  • the second transistor T2 Since the second transistor T2 is turned on, the data voltage Vdata is written into the second plate of the capacitor C1 through the second transistor T2, so that the potential of the second plate of the capacitor C1 is Vdata. Since the first transistor T1 is turned on, the first power source charges the first pole of the first transistor T1. When the circuit state is stable, the potential of the first pole of the first transistor T1 is VDD, and the potential of the control terminal of the first transistor T1 is VDD-
  • the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are low-level signals, and the first scan signal SCAN1 and the second scan signal SCAN2 are both high-level signals.
  • the fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1 is kept on.
  • the second transistor T2, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 are turned off.
  • the fifth transistor T5 Since the fifth transistor T5 is turned on and the second reference voltage Vref2 is written into the second plate of the capacitor C1 through the fifth transistor T5, the potential of the second plate of the capacitor C1 is changed from Vdata to Vref2. Since the fourth transistor T4 and the third transistor T3 are turned off, and the capacity of the capacitor C1 is much larger than the parasitic capacitance of other transistors, the voltage difference between the capacitor C1 is unchanged. According to the capacitive coupling principle, when the voltage difference of the capacitor C1 remains unchanged, the potential of the first plate of the capacitor C1 will also change with the change of the potential of the second plate.
  • the potential of the second plate of the capacitor C1 changes from Vdata in the data writing stage t2 to Vref2 in the light emitting stage t3, and the change is Vref2-Vdata. Therefore, the change in the potential of the first plate of the capacitor C1 is the same as that of the second plate. The amount of potential change is the same. Since the control terminal of the first transistor T1 is connected to the first electrode plate of the capacitor C1, the potential change amount of the control terminal of the first transistor T1 is the same as the potential change amount of the first electrode plate. In the data writing phase t2, the potential of the control terminal of the first transistor T1 is VDD-
  • Vgs VDD-
  • + Vref2-Vdata-VDD Vref2-Vdata-
  • ) 2 K * (Vref2-Vdata) 2
  • K 1/2 * ⁇ * Cox * W / L.
  • ⁇ is the electron mobility of the first transistor T1
  • Cox is the gate oxide capacitance per unit area of the first transistor T1
  • W is the channel width of the first transistor T1
  • L is the channel length of the first transistor T1.
  • the driving current flowing through the first transistor T1 is the light emitting current flowing through the light emitting diode D1. It can be seen from the above formula that the light-emitting current flowing through the light-emitting diode D1 has nothing to do with the first power supply voltage VDD, and has nothing to do with the threshold voltage of the transistor. At the same time, the light emitting current does not flow through the second reference voltage line.
  • the circuit structure and the driving method provided by the embodiments of the present application compensate for the current-resistance voltage drop on the first power line by increasing the second reference voltage.
  • the circuit structure and the control method of the present application also compensate for the influence of the threshold voltage on the light emitting current, and improve the uniformity of the screen body's light emission.

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Abstract

本申请提供一种像素电路及其驱动方法、显示面板和显示装置。像素电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、电容和发光二极管。上述像素电路，通过设置第一发光控制信号和第二发光控制信号分别对电容的第一极板和第二极板进行初始化，以保证像素电路的初始状态相同。利用第二参考电压通过电容对第一晶体管的控制端进行补偿，以使流过第一晶体管的驱动电流与第二参考电压有关而与第一电源电压无关。

Description

像素电路及其驱动方法、显示面板、显示装置 技术领域
本申请涉及显示领域，特别是涉及一种像素电路及其驱动方法、显示面板、显示装置。
背景技术
有机发光显示面板因其具有对比度高、低功耗、视角广、反应速度快等优点，被越来越多地应用到显示领域。通常，有机发光显示面板中包含阵列排布的像素电路。像素电路通常包括多个发光二极管和电源，流经发光二极管的电流与电源电压有关。在显示面板中，由于每个发光二极管与电源的距离不同，故电压传输的过程中产生的线上压降也不同，每个发光二极管实际得到的电源电压不同。因此，流过每个发光二极管的电流不同，发光二极管的亮度也不同，导致显示面板的发光亮度不均匀。
发明内容
本申请提供一种像素电路及其驱动方法、显示面板、显示装置。
一种像素电路，包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、电容和发光二极管；其中，
第四晶体管的控制端用于输入第一扫描信号；第四晶体管的第一极分别连接第三晶体管的第二极、第一晶体管的控制端及电容的第一极板；第四晶体管的第二极连接第七晶体管的第二极，用于输入第一参考电压；
第三晶体管的控制端用于输入第二扫描信号，第三晶体管的第一极分别连接第一晶体管的第二极和第六晶体管的第一极，第一晶体管的第一极用于输入第一电源电压；
第六晶体管的控制端用于输入第一发光控制信号，第六晶体管的第二极分别连接发光二极管的阳极和第七晶体管的第一极，发光二极管的阴极用于输入第二电源电压，第七晶体管的控制端用于输入第一扫描信号；
第二晶体管的控制端用于输入第二扫描信号，第二晶体管的第一极用于输入数据电压，第二晶体管的第二极分别连接电容的第二极板和第五晶体管的第二极；并且
第五晶体管的控制端用于输入第二发光控制信号，第五晶体管的第一极用于输入第二参考电压。
在其中一个实施例中，第一参考电压的电压值小于第二电源电压的电压值。
在其中一个实施例中，第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管均为P型晶体管或均为N型晶体管。
在其中一个实施例中，第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管包括低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管以及非晶硅薄膜晶体管中的任一种。
在其中一个实施例中，第二晶体管至第七晶体管均为开关晶体管，第一晶体管为驱动晶体管。
在其中一个实施例中，电容为储能电容，发光二极管为有机发光二极管。
在其中一个实施例中，每个晶体管的控制端为晶体管的栅极，每个晶体管的第一极为晶体管的源极，每个晶体管的第二极为晶体管的漏极。
在其中一个实施例中，第一电源电压是正电压，第二电源电压是负电压。
一种显示面板，包括呈矩阵排列的多个像素电路，其中，像素电路为上述的像素电路。
一种显示装置，包括如上述的显示面板。
一种像素电路的驱动方法，像素电路包括如上述的像素电路，驱动方法包括：
初始化阶段，设置第一扫描信号和第二发光控制信号为低电平信号，设置第二扫描信号和第一发光控制信号为高电平信号，第一参考电压对像素电路进行初始化；
数据写入阶段，设置第二扫描信号为低电平信号，设置第一扫描信号、第一发光控制信号和第二发光控制信号为高电平信号，数据电压写入像素电路；
发光阶段，设置第一发光控制信号和第二发光控制信号为低电平信号，设置第一扫描信号及第二扫描信号为高电平信号，发光二极管发光。
在其中一个实施例中，在初始化阶段，第一扫描信号控制第四晶体管和第七晶体管打开；
第一参考电压通过第四晶体管对第一晶体管的控制端和电容的第一极板进行初始化，第一晶体管打开；第一参考电压通过第七晶体管对发光二极管的阳极进行初始化；并且
第二发光控制信号控制第五晶体管打开，第二参考电压通过第五晶体管对电容的第二极板进行初始化。
在其中一个实施例中，第一参考电压的电压值小于第二电源电压的电压值，以保证在初始化阶段发光二极管不发光。
在其中一个实施例中，在数据写入阶段，第二扫描信号控制第二晶体管打开，数据电压通 过第二晶体管写入电容的第二极板。
在其中一个实施例中，在发光阶段，第二发光控制信号控制第五晶体管打开，第二参考电压通过第五晶体管和电容对第一晶体管进行电压补偿，以使流过第一晶体管的电流与第一电源电压无关。
上述像素电路的控制方法，通过增加第二参考电压补偿了第一电源线上的电流-电阻压降，同时，也补偿了阈值电压对发光电流的影响，从而提高了屏体发光的均一性。
附图说明
图1为本申请的一个实施例提供的像素电路的示意图；
图2为本申请的一个实施例提供的像素电路的控制方法的时序图。
具体实施方式
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。下面的描述中阐述了很多具体细节以便于充分理解本申请。但是本申请能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似改进，因此本申请不受下面公开的具体实施例的限制。
需要说明的是，当元件被称为“设置于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。本文所使用的术语“垂直的”、“水平的”、“左”、“右”以及类似的表述只是为了说明的目的，并不表示是唯一的实施方式。
参见图1，本申请的一个实施例提供一种像素电路，包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、电容C1和发光二极管D1。其中，第一晶体管T1至第七晶体管T7均包括控制端、第一极和第二极。
像素电路还包括第一扫描信号输入端、第二扫描信号输入端、第一发光控制信号输入端、第二发光控制信号输入端和数据信号输入端。第一扫描信号输入端分别连接第四晶体管T4的控制端和第七晶体管T7的控制端，用于输入第一扫描信号SCNA1。第二扫描信号输入端分别连接第二晶体管T2和第三晶体管T3的控制端，用于输入第二扫描信号SCAN2。第一发光控制信号输入端连接第六晶体管T6的控制端，用于输入第一发光控制信号EM1。第二发光控制信号输入端连接第五晶体管T5的控制端，用于输入第二发光控制信号EM2。其中，第一发光 控制信号EM1与第二发光控制信号EM2不同，故第一发光控制信号输入端的端口与第二发光控制信号输入端的端口也不同。数据信号输入端连接第二晶体管T2的第一极，用于输入数据电压Vdata。
具体的，第四晶体管T4的控制端用于输入第一扫描信号SCNA1，第四晶体管T4的第一极分别连接第三晶体管T3的第二极、第一晶体管T1的控制端及电容C1的第一极板；第四晶体管T4的第二极连接第七晶体管T7的第二极，用于输入第一参考电压Vref1。第三晶体管T3的控制端用于输入第二扫描信号SCAN2，第三晶体管T3的第一极分别连接第一晶体管T1的第二极和第六晶体管T6的第一极。第一晶体管T1的第一极用于输入第一电源电压VDD。第六晶体管T6的控制端用于输入第一发光控制信号EM1，第六晶体管T6的第二极分别连接发光二极管D1的阳极和第七晶体管T7的第一极。发光二极管D1的阴极用于输入第二电源电压VSS。第七晶体管T7的控制端用于输入第一扫描信号SCAN1。第二晶体管T2的控制端用于输入第二扫描信号SCAN2，第二晶体管T2的第一极用于输入数据电压Vdata，第二晶体管T2的第二极分别连接电容C1的第二极板和第五晶体管T5的第二极。第五晶体管T5的控制端用于输入第二发光控制信号EM2，第五晶体管T5的第一极用于输入第二参考电压Vref2。
本实施例中，第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7均为开关晶体管，第一晶体管T1为驱动晶体管。电容C1为储能电容，发光二极管D1为OLED(Organic Light-Emitting Diode,有机发光二极管)。本实施例中的晶体管均采用P型晶体管。具体地，每个晶体管的控制端为晶体管的栅极，每个晶体管的第一极为晶体管的源极，每个晶体管的第二极为晶体管的漏极。当对晶体管的控制端施加低电平时，晶体管导通。当然，在其他实施例中，晶体管也可以是N型晶体管。在采用N型晶体管作为像素电路中的晶体管时，对晶体管的控制端输入高电平信号可以使其导通。
第一扫描信号SCAN1可控制第四晶体管T4和第七晶体管T7导通，以使第一参考电压Vref1对第一晶体管T1的栅极和发光二极管D1的阳极进行初始化。第二扫描信号SCAN2可控制第二晶体管T2导通，以使数据电压Vdata通过第二晶体管T2写入电容C1的第二极板。第二发光控制信号EM2可以控制第五晶体管T5导通，以使第二参考电压Vref2通过电容C1对第一晶体管T1的控制端进行补偿。
本实施例中，第一电源电压VDD可以是正电压，第二电源电压VSS可以是负电压。驱动第一晶体管T1可以在第一电源电压VDD的作用下产生电流。该电流流过发光二极管D1以使发光二极管D1发光。发光二极管D1发光时，电流从发光二极管D1流向第二电源。
上述实施例提供的像素电路，通过设置第一发光控制信号EM1和第二发光控制信号EM2分别对电容C1的第一极板和第二极板进行初始化，以保证像素电路的初始状态相同。利用第二参考电压Vref2通过电容C1对第一晶体管T1的控制端进行补偿，以使流过第一晶体管T1的驱动电流与第二参考电压Vref2有关而与第一电源电压VDD无关。由于驱动电流流经电源线，在驱动电流与第一电源电压VDD无关的情况下，驱动电流不会受到电源线上的电流-电阻压降的影响，进而可以提高屏体的发光均一性。
在一个实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7均为P型晶体管或均为N型晶体管。
在一个实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管以及非晶硅薄膜晶体管中的任一种。
本申请的一个实施例提供一种显示面板，包括阵列排布的多个前述像素电路。显示面板还包括数据驱动器、扫描驱动器和发光控制器。第一扫描信号线、第二扫描信号线一端分别对应连接每行像素电路的第一扫描信号输入端、第二扫描信号输入端，另一端连接扫描驱动器。扫描驱动器提供扫描信号，并通过扫描信号线传输至像素电路中。数据信号线一端连接每列像素电路的数据信号输入端，另一端连接数据驱动器。数据驱动器提供数据电压，并通过数据信号线传输至像素电路。多条发光控制信号线一端连接每行像素电路，另一端连接发光控制器。发光控制器提供发光控制信号，并通过发光控制信号线传输至像素电路。
本申请的一个实施例提供一种显示装置，包括上述显示面板。
请参见图1与图2，图1为本申请的一个实施例提供的一种像素电路，图2为驱动图1所示像素电路的时序信号图。所述驱动方法包括以下三个阶段：
初始化阶段t1，第一扫描信号SCAN1和所述第二发光控制信号EM2为低电平信号，第二扫描信号SCAN2和第一发光控制信号EM1为高电平信号，以使第一参考电压Vref1对像素电路进行初始化。
数据写入阶段t2，第二扫描信号SCAN2为低电平信号，第一扫描信号SCAN1、第一发光控制信号EM1和第二发光控制信号EM2为高电平信号，以使数据电压Vdata写入像素电路。
发光阶段t3，第一发光控制信号EM1和第二发光控制信号EM2为低电平信号，第一扫描信号SCAN1及第二扫描信号SCAN2为高电平信号，以使发光二极管D1发光。
具体的，在初始化阶段t1，第一扫描信号SCAN1和第二发光控制信号EM2均为低电平。 由于第一扫描信号输入端连接第四晶体管T4和第七晶体管T7的控制端，且第四晶体管T4和第七晶体管T7为P型晶体管，故第一扫描信号SCAN1控制第四晶体管T4和第七晶体管T7打开。第一参考电压Vref1通过第四晶体管T4对第一晶体管T1的控制端和电容C1的第一极板进行初始化。同时，第一参考电压Vref1通过第七晶体管T7对发光二极管D1的阳极进行初始化。由于第二发光控制信号输入端连接第五晶体管T5的控制端，且第五晶体管T5为P型晶体管，故第二发光控制信号EM2控制第五晶体管T5打开，以使第二参考电压Vref2对电容C1的第二极板进行初始化。本实施例中，在初始化阶段t1，电容C1的第一极板和第二极板被初始化，电容C1的第一极板和第二极板的电位分别保持为第一参考电压Vref1和第二参考电压Vref2。由于发光电流经第一电源、第一晶体管T1、第六晶体管T6和发光二极管D1流向第二电源，发光电流不流经提供第一参考电压Vref1的第一参考电压线和提供第二参考电压Vref2的第二参考电压线。因此第一参考电压线和第二参考电压线上不存在电流-电阻压降，故每个像素电路的初始化状态均相同，进而可以更好地保证屏体发光的均一性。
在数据写入阶段t2，第二扫描信号SCAN2为低电平信号。第二扫描信号输入端连接第二晶体管T2的控制端，第二晶体管T2为P型晶体管，故第二扫描信号SCAN2控制第二晶体管T2打开。数据电压Vdata通过第二晶体管T2被写入电容C1的第二极板，以使电容C1的第二极板的电位为Vdata。由于在初始化阶段t1，第一参考电压Vref1对第一晶体管T1的控制端进行初始化，使得第一晶体管T1导通。在数据写入阶段t2，电路状态稳定后，第一晶体管T1的第一极电位为VDD，第一晶体管T1的控制端电位为VDD-|Vth|，从而实现对阈值电压的补偿。
在发光阶段t3，第一发光控制信号EM1和第二发光控制信号EM2均为低电平。第二发光控制信号EM2控制第五晶体管T5打开，以使第二参考电压Vref2写入电容C1的第二极板。由于第一扫描信号SCAN1和第二扫描信号SCAN2为高电平信号，第四晶体管T4和第三晶体管T3截止，且电容C1的容量远大于其他晶体管的寄生电容的容量，电容C1两端的电压差不变。而电容C1的第二极板的电位由Vdata变为Vref2，根据电容耦合原理，电容C1的第一极板的电位也会随之变化，即电容C1的第一极板电位变化量为Vref2-Vdata。电容C1的第一极板连接第一晶体管T1的控制端，因此，第一晶体管T1的控制端的电位变化量为Vref2-Vdata，则第一晶体管T1的控制端的电位为：VDD-|Vth|+Vref2-Vdata。由于第一晶体管T1的第一极电位为VDD，故第一晶体管T1的栅源电压为：Vgs＝Vref2-Vdata-|Vth|。其中，|Vth|＝-Vth。根据流过第一晶体管T1的驱动电流的公式I＝K*(Vgs-Vth) 2可知，流过第一晶体管T1的驱动电 流与第一电源的电压VDD无关，故可消除第一电源线上电流-电阻压降对驱动电流的影响。驱动电流与第二参考电压Vref2有关，而流过发光二级管D1的电流不经过第二参考电压线，故第二参考电压线上不会产生电流-电阻压降，进而可以提高屏体的发光均一性。
下面介绍基于图1与图2所示像素电路的工作原理：
在初始化阶段t1，第一扫描信号SCAN1和第二发光控制信号EM2为低电平信号，第二扫描信号SCAN2和第一发光控制信号EM1为高电平信号。第四晶体管T4、第五晶体管T5、第七晶体管T7打开，第二晶体管T2、第三晶体管T3、第六晶体管T6截止。
由于第四晶体管T4导通，第一参考电压Vref1通过第四晶体管T4对第一晶体管T1的控制端和电容C1的第一极板进行初始化。其中，第一参考电压Vref1可以是负电压，第一参考电压Vref1作用于第一晶体管T1的控制端可以使第一晶体管T1导通。由于第七晶体管T7导通，第一参考电压Vref1对发光二极管D1的阳极进行初始化。由于第五晶体管T5导通，第二参考电压Vref2通过第五晶体管T5对电容C1的第二极板进行初始化。
第一参考电压Vref1的电压值小于第二电源电压VSS的电压值，以保证在初始化时发光二极管D1不发光。初始化可消除上一发光阶段的残留电流对本发光阶段的影响。并且，对电容C1的第一极板和第二极板进行初始化，可保证所有像素电路均处于同一初始状态，提高屏体的发光均一性。
在数据写入阶段t2，第二扫描信号SCAN2为低电平信号，第一扫描信号SCAN1、第一发光控制信号EM1和第二发光控制信号EM2为高电平信号。第二晶体管T2和第三晶体管T3导通，在初始化阶段，第一晶体管T1已导通。第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7截止。
由于第二晶体管T2导通，数据电压Vdata经过第二晶体管T2写入电容C1的第二极板，以使电容C1的第二极板的电位为Vdata。由于第一晶体管T1导通，第一电源对第一晶体管T1的第一极充电。当电路状态稳定后，第一晶体管T1的第一极电位为VDD，第一晶体管T1的控制端电位为VDD-|Vth|，因此实现了对第一晶体管T1的阈值电压的补偿。
在发光阶段t3，第一发光控制信号EM1和第二发光控制信号EM2为低电平信号，第一扫描信号SCAN1和第二扫描信号SCAN2均为高电平信号。第五晶体管T5和第六晶体管T6导通，第一晶体管T1保持导通状态。第二晶体管T2、第三晶体管T3、第四晶体管T4、第七晶体管T7截止。
由于第五晶体管T5导通，第二参考电压Vref2通过第五晶体管T5写入电容C1的第二极 板，故电容C1的第二极板的电位由Vdata变为Vref2。由于第四晶体管T4和第三晶体管T3截止，且电容C1的容量远大于其他晶体管的寄生电容，故电容C1的电压差不变。根据电容耦合原理，在电容C1的电压差保持不变的情况下，电容C1的第一极板的电位也会随第二极板的电位的变化而变化。而电容C1的第二极板电位由数据写入阶段t2的Vdata变为发光阶段t3的Vref2，变化量为Vref2-Vdata，故电容C1第一极板的电位的变化量与第二极板的电位变化量相同。由于第一晶体管T1的控制端与电容C1的第一极板连接，故第一晶体管T1控制端的电位变化量与第一极板的电位变化量相同。则在数据写入阶段t2，第一晶体管T1的控制端电位为VDD-|Vth|+Vref2-Vdata。因此，第一晶体管T1的栅源电压Vgs为：Vgs＝VDD-|Vth|+Vref2-Vdata-VDD＝Vref2-Vdata-|Vth|。流过第一晶体管T1的驱动电流为：I＝K*(Vgs-Vth) 2＝K*(Vref2-Vdata-|Vth|+|Vth|) 2＝K*(Vref2-Vdata) 2
其中，K＝1/2*μ*Cox*W/L。μ是第一晶体管T1的电子迁移率，Cox是第一晶体管T1单位面积的栅氧化层电容，W是第一晶体管T1的沟道宽度，L是第一晶体管T1的沟道长度。流过第一晶体管T1的驱动电流即为流过发光二极管D1的发光电流。由上述公式可以看出，流过发光二极管D1的发光电流与第一电源电压VDD无关，与晶体管的阈值电压也无关。同时，发光电流不流经第二参考电压线。因此，本申请的实施例提供的电路结构及其驱动方法通过增加第二参考电压补偿了第一电源线上的电流-电阻压降。同时，本申请的电路结构及其控制方法也补偿了阈值电压对发光电流的影响，提高了屏体发光的均一性。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种像素电路，包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、电容和发光二极管；其中，
    所述第四晶体管的控制端用于输入第一扫描信号；所述第四晶体管的第一极分别连接所述第三晶体管的第二极、所述第一晶体管的控制端及所述电容的第一极板；所述第四晶体管的第二极连接所述第七晶体管的第二极，用于输入第一参考电压；
    所述第三晶体管的控制端用于输入第二扫描信号，所述第三晶体管的第一极分别连接所述第一晶体管的第二极和所述第六晶体管的第一极，所述第一晶体管的第一极用于输入第一电源电压；
    所述第六晶体管的控制端用于输入第一发光控制信号，所述第六晶体管的第二极分别连接所述发光二极管的阳极和所述第七晶体管的第一极，所述发光二极管的阴极用于输入第二电源电压，所述第七晶体管的控制端用于输入所述第一扫描信号；
    所述第二晶体管的控制端用于输入所述第二扫描信号，所述第二晶体管的第一极用于输入数据电压，所述第二晶体管的第二极分别连接所述电容的第二极板和所述第五晶体管的第二极；并且
    所述第五晶体管的控制端用于输入第二发光控制信号，所述第五晶体管的第一极用于输入第二参考电压。
  2. 根据权利要求1所述的像素电路，其中，所述第一参考电压的电压值小于所述第二电源电压的电压值。
  3. 根据权利要求1所述的像素电路，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管和所述第七晶体管均为P型晶体管或均为N型晶体管。
  4. 根据权利要求1所述的像素电路，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管和所述第七晶体管包括低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管以及非晶硅薄膜晶体管中的任一种。
  5. 根据权利要求1所述的显示面板，其中，所述第二晶体管至所述第七晶体管均为开关晶体管，所述第一晶体管为驱动晶体管。
  6. 根据权利要求1所述的像素电路，其中，所述电容为储能电容，所述发光二极管为有机发光二极管。
  7. 根据权利要求1所述的显示面板，其中，每个晶体管的控制端为晶体管的栅极，每个晶体管的第一极为晶体管的源极，每个晶体管的第二极为晶体管的漏极。
  8. 根据权利要求1所述的像素电路，其中，所述第一电源电压是正电压，所述第二电源电压是负电压。
  9. 一种显示面板，包括呈矩阵排列的多个像素电路，其中，所述像素电路为如权利1-8中任一项所述的像素电路。
  10. 一种显示装置，包括如权利要求9所述的显示面板。
  11. 一种像素电路的驱动方法，所述像素电路包括如权利要求1所述的像素电路，所述驱动方法包括：
    初始化阶段，设置第一扫描信号和第二发光控制信号为低电平信号，设置第二扫描信号和第一发光控制信号为高电平信号，第一参考电压对所述像素电路进行初始化；
    数据写入阶段，设置所述第二扫描信号为低电平信号，设置所述第一扫描信号、所述第一发光控制信号和所述第二发光控制信号为高电平信号，数据电压写入所述像素电路；
    发光阶段，设置所述第一发光控制信号和所述第二发光控制信号为低电平信号，设置所述第一扫描信号及所述第二扫描信号为高电平信号，发光二极管发光。
  12. 根据权利要求11所述的像素电路的驱动方法，其中，在所述初始化阶段，所述第一扫描信号控制第四晶体管和第七晶体管打开；
    所述第一参考电压通过所述第四晶体管对第一晶体管的控制端和电容的第一极板进行初始化，所述第一晶体管打开；所述第一参考电压通过所述第七晶体管对所述发光二极管的阳极进行初始化；并且
    所述第二发光控制信号控制第五晶体管打开，第二参考电压通过所述第五晶体管对所述电容的第二极板进行初始化。
  13. 根据权利要求12所述的像素电路的驱动方法，其中，所述第一参考电压的电压值小于所述第二电源电压的电压值，以保证在所述初始化阶段所述发光二极管不发光。
  14. 根据权利要求12所述的像素电路的驱动方法，其中，在所述数据写入阶段，所述第二扫描信号控制第二晶体管打开，所述数据电压通过所述第二晶体管写入所述电容的第二极板。
  15. 根据权利要求14所述的像素电路的驱动方法，其中，在所述发光阶段，所述第二发光控制信号控制所述第五晶体管打开，所述第二参考电压通过所述第五晶体管和所述电容对所述第一晶体管进行电压补偿，以使流过所述第一晶体管的电流与第一电源电压无关。
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