WO2018161553A1 - 显示装置、显示面板、像素驱动电路和驱动方法 - Google Patents

显示装置、显示面板、像素驱动电路和驱动方法 Download PDF

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Publication number
WO2018161553A1
WO2018161553A1 PCT/CN2017/104597 CN2017104597W WO2018161553A1 WO 2018161553 A1 WO2018161553 A1 WO 2018161553A1 CN 2017104597 W CN2017104597 W CN 2017104597W WO 2018161553 A1 WO2018161553 A1 WO 2018161553A1
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Prior art keywords
transistor
storage capacitor
turned
driving
scan signal
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PCT/CN2017/104597
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English (en)
French (fr)
Inventor
青海刚
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US15/768,899 priority Critical patent/US10777132B2/en
Publication of WO2018161553A1 publication Critical patent/WO2018161553A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0213—Addressing of scan or signal lines controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/067—Special waveforms for scanning, where no circuit details of the gate driver are given
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel driving circuit, a display panel, a display device, and a driving method.
  • the related display device adopts LTPS (Low Temperature Poly-silicon) process or Oxide (oxide) process, due to process non-uniformity, the threshold voltage difference of the driving transistors at different positions may occur, and thus The illumination of pixels at different locations has an effect, resulting in uneven display.
  • LTPS Low Temperature Poly-silicon
  • Oxide Oxide
  • the threshold voltage of the driving tube is usually compensated by the pixel driving circuit itself to solve the problem of display unevenness caused by uneven threshold voltage.
  • the related art has a problem that the circuit has both a P-type transistor and an N-type transistor, which results in a complicated process and an increase in cost. If the transistor is completely changed to a P-type transistor, a control signal needs to be added to satisfy the circuit. The requirements will further complicate the design of the peripheral circuits.
  • an object of the present disclosure is to provide a pixel driving circuit that keeps the circuit control signal as simple as possible while ensuring a simple process.
  • Another object of the present disclosure is to propose a display panel. Still another object of the present disclosure is to provide a display device. Yet another object of the present disclosure is to propose a drive The method of pixels.
  • an embodiment of the present disclosure provides a pixel driving circuit including a driving transistor, a first scanning end, a second scanning end, a data input terminal, an illumination control terminal, a storage capacitor, a reset unit, and a write a compensation unit and an illumination control unit, wherein the storage capacitor is connected to the driving transistor; the reset unit is connected to the first scan end, and the reset unit is configured according to the first scan signal provided by the first scan end Turning on to reset the storage capacitor and charging the storage capacitor; the write compensation unit is respectively connected to the second scan end and the data input end, and the write compensation unit is configured according to the second scan The second scan signal provided by the terminal is turned on, so that the data signal provided by the data input terminal is written into the gate of the driving transistor, and the storage capacitor is discharged through the write compensation unit and the driving transistor until The driving transistor is turned off; the light emitting control unit is connected to the light emitting control end, and the light emitting control unit is provided according to the light emitting control end Light emission control signal the opening of the driving transistor
  • the reset unit is turned on according to the first scan signal provided by the first scan terminal to reset the storage capacitor and charge the storage capacitor
  • the write compensation unit is configured according to the second scan end.
  • the provided second scan signal is turned on, so that the data signal provided by the data input terminal is written to the gate of the driving transistor, and the storage capacitor is discharged through the write compensation unit and the driving transistor until the driving transistor is turned off, and the light emitting control unit is according to the light emitting control terminal.
  • the provided illumination control signal is turned on to drive the driving transistor to generate an emission current together with the storage capacitor to drive the illumination element in the pixel to emit light, and the first scan signal is output before the second scan signal, thereby eliminating the threshold voltage unevenness of the driving transistor. It has the effect of showing uniformity and can ensure the simplification of the process, while keeping the circuit control signal as simple as possible.
  • one end of the storage capacitor is connected to a second pole of the driving transistor
  • the light emitting control unit includes a first transistor and a second transistor, a gate of the first transistor and the The light emitting control end is connected, the second pole of the first transistor is connected to the first preset power source, the first pole of the first transistor is connected to the second pole of the driving transistor, and the gate of the second transistor And the light-emitting control end
  • the first pole of the second transistor is connected to the other end of the storage capacitor, and the second pole of the second transistor is connected to the gate of the driving transistor.
  • the reset unit shares the first transistor with the light emission control unit, the reset unit further includes a third transistor, a gate of the third transistor and the first The scan ends are connected, the first pole of the third transistor is connected to the second preset power source, and the second pole of the third transistor is connected to one end of the storage capacitor.
  • the write compensation unit includes a fourth transistor and a fifth transistor, a gate of the fourth transistor is connected to the second scan terminal, and a first pole of the fourth transistor is The second predetermined power source is connected, the second pole of the fourth transistor is connected to one end of the storage capacitor, the gate of the fifth transistor is connected to the second scan end, and the fifth transistor is A first pole is coupled to the data input, and a second pole of the fifth transistor is coupled to a gate of the drive transistor.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are all P-type transistors.
  • the working phase of the pixel driving circuit sequentially includes a reset phase, a write compensation phase, and an illumination driving phase, wherein in the reset phase, the first scan signal and the illumination
  • the control signal is low level and the second scan signal is high level, the first transistor, the second transistor, and the third transistor are turned on, and the fourth transistor and the fifth transistor are turned off.
  • the second preset power source resets the storage capacitor through the third transistor, and the first preset power source charges the storage capacitor through the first transistor; a phase, the first scan signal and the light emission control signal are at a high level, and the second scan signal is at a low level, and the first transistor, the second transistor, and the third transistor are turned off,
  • the fourth transistor and the fifth transistor are turned on, the data signal is written into a gate of the driving transistor through the fifth transistor, and the storage capacitor is discharged through the driving transistor
  • the driving transistor is turned off; in the illuminating driving phase, the first scan signal and the second scan signal are both at a high level, and the illuminating control signal is at a low level, the first transistor, the first transistor
  • the second transistor is turned on, the third transistor, The fourth transistor and the fifth transistor are turned off, and the driving transistor generates the illuminating current under the action of the storage capacitor.
  • a buffer phase is further included between the write compensation phase and the illumination driving phase, wherein in the buffering phase, the first scan signal, the second scan signal, and The light emission control signals are all at a high level, and the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are both turned off to suppress interference.
  • a falling edge of the second scan signal is provided to the second scan end and the light emission control end simultaneously with a rising edge of the light emission control signal.
  • another embodiment of the present disclosure proposes a display panel including the pixel driving circuit.
  • the influence of the threshold voltage unevenness of the driving transistor on the display uniformity can be eliminated, and the simplification of the process process can be ensured, and the simplification of the circuit control signal can be maintained as much as possible.
  • a further aspect of the present disclosure provides a display device including the display panel.
  • a further aspect of the present disclosure provides a method for driving a pixel by using a pixel driving circuit, including: a reset phase, the first scan signal and the light emission control signal are at a low level
  • the second scan signal is at a high level, the first transistor, the second transistor, and the third transistor are turned on, the fourth transistor and the fifth transistor are turned off, and the second preset power source is passed
  • the third transistor resets the storage capacitor while the first predetermined power source charges the storage capacitor through the first transistor; a write compensation phase, the first scan signal and the The light emission control signal is at a high level, and the second scan signal is at a low level, the first transistor, the second transistor, and the third transistor are turned off, the fourth transistor and the fifth transistor Turning on, the data signal is written into the gate of the driving transistor through the fifth transistor, and the storage capacitor is discharged through the driving transistor until the driving transistor is turned off; Movable stage, the first scan signal and the second scanning signal are high, and the emission control signal is low, the first
  • FIG. 1 is a schematic diagram of a pixel driving circuit in the related art
  • FIG. 3 is a block schematic diagram of a pixel driving circuit in accordance with an embodiment of the present disclosure
  • FIG. 4 is a circuit schematic diagram of a pixel driving circuit in accordance with one embodiment of the present disclosure.
  • FIG. 5 is a control timing diagram of a pixel driving circuit according to an embodiment of the present disclosure.
  • FIG. 6 is an equivalent circuit diagram of a pixel driving circuit in a reset phase, according to an embodiment of the present disclosure
  • FIG. 7 is an equivalent circuit diagram of a pixel driving circuit in a write compensation phase, according to an embodiment of the present disclosure.
  • FIG. 8 is an equivalent circuit diagram of a pixel driving circuit in a buffering stage, according to an embodiment of the present disclosure
  • FIG. 9 is an equivalent circuit diagram of a pixel driving circuit in an emission control stage, according to an embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of a pixel driving circuit in the related art. As shown in Figures 1 and 2, the pixel driving circuit works as follows:
  • stage 1' scan signal scan' is high level, EM' signal is low level, at this time transistors T1', T2', T3' in pixel drive circuit are turned on, transistor T4' is off, preset power supply VSS'
  • the storage capacitor Cst' is charged simultaneously with VDD', and the Vdata' signal is written to the gate of the drive transistor DTFT'.
  • the voltage across the storage capacitor Cst' is VDD’-VSS’;
  • phase 2' the scan signal scan' continues to be high, and the EM' signal also goes high.
  • the transistors T1' and T4' in the pixel driving circuit are turned off, T2', T3' are turned on, and the storage capacitor Cst 'Discharge through the drive transistor DTFT' until the potential of one end of the storage capacitor Cst' connected to the drive transistor DTFT' drops to Vdata'+
  • the scan signal scan' is at a low level
  • the EM' signal is at a low level.
  • the transistors T1' and T4' in the pixel drive circuit are turned on, T2', T3' are turned off, and the pixels emit light.
  • T1', T4', and DTFT' in the circuit are P-type transistors, and T2' and T3' are N-type transistors, the process process is complicated. The cost increases; if T2', T3' are all changed to P-type TFT, then the gates of T2', T3', T4' cannot share a scan signal Scan', and additional control signals must be added to meet the circuit requirements. This has led to further complications in the design of peripheral circuits.
  • the pixel driving circuit of the related art is complicated in process process or the control signal of the circuit is too complicated.
  • embodiments of the present disclosure propose a pixel driving circuit, a display device, and an electronic device.
  • a pixel driving circuit, a display device, and an electronic device of an embodiment of the present disclosure will be described below with reference to FIGS. 3 through 9.
  • the pixel driving circuit 100 includes a driving transistor T6, a first scanning terminal S1, a second scanning terminal S2, a data input terminal Vdata, an emission control terminal EM, a storage capacitor Cs, a reset unit 10, and write compensation.
  • Unit 20 and illumination control unit 30 are a driving transistor T6, a first scanning terminal S1, a second scanning terminal S2, a data input terminal Vdata, an emission control terminal EM, a storage capacitor Cs, a reset unit 10, and write compensation.
  • Unit 20 and illumination control unit 30 Unit
  • the storage capacitor Cs is connected to the driving transistor T6; the reset unit 10 is connected to the first scanning terminal S1, and the reset unit 10 is turned on according to the first scanning signal provided by the first scanning terminal S1 to reset the storage capacitor Cs.
  • the storage capacitor Cs is charged; the write compensation unit 20 is connected to the second scan terminal S2 and the data input terminal Vdata, respectively, and the write compensation unit 20 is turned on according to the second scan signal provided by the second scan terminal S2.
  • the data signal provided by the input terminal Vdata is written into the gate of the driving transistor T6, and the storage capacitor Cs is discharged through the writing compensation unit 20 and the driving transistor T6 until the driving transistor T6 is turned off; the light emission controlling unit 30 is connected to the light emitting control terminal EM.
  • the illumination control unit 30 is turned on according to the illumination control signal provided by the illumination control terminal EM to drive the driving transistor T6 to generate an illumination current to drive the illumination element DO in the pixel to emit light; wherein the first scan signal precedes the second scan Signal output.
  • the pixel driving circuit 100 can be used to drive pixel illumination in the pixel array. That is, each pixel in the pixel array is connected to the corresponding pixel driving circuit 100 to emit light under the driving of the corresponding pixel driving circuit 100. . Specifically, the light-emitting element DO of each pixel can be driven by the current generated by the driving transistor T6 in a saturated state, that is, the current drives the light.
  • the pixel array may employ a progressive scan mode, that is, sequential scans one after another in a row.
  • the upper row for example, the n-1th row of pixels is scanned first, and the current row is scanned after the nth row of pixels, the first scan signal may be the previous row scan signal, and the second scan signal is the current row scan signal.
  • the previous row of scan signals is supplied to the reset unit 10 through the first scan terminal S1, and the current row scan signal is supplied to the write compensation unit 20 through the second scan terminal S2, and the reset unit 10 can be turned on in the control of the scan signal in the previous row.
  • the storage capacitor Cs can be reset and the storage capacitor Cs can be charged by the reset unit 10, thereby using the scan signal of the previous row to correspond to each pixel of the current row.
  • the pixel driving circuit 100 performs setting and charges the storage capacitor Cs corresponding to each pixel of the current row.
  • the write compensation unit 20 can be turned on after the control of the current row scan signal.
  • the data signal provided by the data input terminal Vdata is written by the write compensation unit 20.
  • the gate of the driving transistor T6 is fixed, the gate potential of the driving transistor T6 is fixed, and the storage capacitor Cs is discharged by the writing compensation unit 20 and the driving transistor T6 until the driving transistor T6 is turned off, thereby achieving threshold compensation of the driving transistor T6, thereby utilizing the current line.
  • the scan signal compensates for the writing of the data signal and the voltage threshold for each pixel of the current line.
  • the illumination control The unit 30 can be turned on under the control of the illumination control signal provided by the illumination control terminal EM.
  • the illumination control unit 30 and the storage capacitor Cs jointly drive the drive transistor T6 to generate an illumination current to drive the illumination element DO in the pixel to emit light.
  • the pixel driving circuit 100 is reset and the storage capacitor Cs is charged by using the scanning signal of the previous row, and the data signal is written by the current row scanning signal to fix the gate potential of the driving transistor T6.
  • the storage capacitor Cs realizes the threshold compensation of the driving transistor T6 by self-discharging of the driving transistor T6 until the driving transistor T6 is automatically turned off, thereby eliminating the influence of the voltage threshold of the driving transistor T6 on display uniformity, and maintaining the circuit as much as possible while ensuring a simple process process.
  • the simplification of the control signal solves a pair of contradictions in the related art that either the process process is complicated or the control signal is complicated.
  • the light emitting element DO may be a light emitting diode, and more specifically, may be an organic light emitting diode.
  • one end of the storage capacitor Cs is connected to a second pole of the driving transistor T6, such as a source
  • the light emission control unit 30 includes a first transistor T1 and a second transistor T2, the first transistor.
  • the gate of the first transistor T1 is connected to the first predetermined power source VDD, and the first pole of the first transistor T1 is, for example, the drain and the second pole of the driving transistor T6.
  • the source is connected
  • the gate of the second transistor T2 is connected to the light-emitting control terminal EM
  • the first pole of the second transistor T2 is connected, for example, to the other end of the storage capacitor Cs
  • the second pole of the second transistor T2 is, for example, the source. It is connected to the gate of the driving transistor T6.
  • the first pole of the driving transistor T6 is connected to the anode of the light emitting element DO, and the cathode of the light emitting element DO is connected to the third preset power source VSS.
  • the first preset power source VDD can provide a high level
  • the third preset The power supply VSS can provide a low level.
  • the reset unit 10 shares the first transistor T1 with the light emission control unit 30, and the reset unit 10 further includes a third transistor T3, the gate of the third transistor T3 and the first
  • the first terminal of the third transistor T3 is connected to the second predetermined power source Vref, and the second electrode of the third transistor T3 is connected to one end of the storage capacitor Cs.
  • the second preset is connected to the second terminal T1.
  • Power supply Vref can provide parameters Test level, the reference level can be lower than the high level.
  • the write compensation unit 20 includes a fourth transistor T4 and a fifth transistor T5.
  • the gate of the fourth transistor T4 is connected to the second scan terminal S2, and the fourth transistor T4
  • the first pole, for example, the drain is connected to the second predetermined power source Vref
  • the second pole of the fourth transistor T4 for example, the source is connected to one end of the storage capacitor Cs
  • the gate of the fifth transistor T5 is connected to the second scan terminal S2
  • the first pole of the five transistor T5, for example, the drain is connected to the data input terminal Vdata
  • the second pole of the fifth transistor T5, for example, the source is connected to the gate of the driving transistor T6.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may each be a P-type transistor.
  • the driving transistor T6 may be a P-type transistor. More specifically, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the driving transistor T6 may each be a TFT (Thin Film Transistor) tube.
  • TFT Thin Film Transistor
  • the level value of the second preset power source Vref is less than or equal to the minimum level value of the data signal supplied from the data input terminal Vdata.
  • the pixel driving circuit 100 of the embodiment of the present disclosure includes six transistors and one storage capacitor Cs, T1 to T5 are switching transistors, and are used as circuit switches, and T6 is a driving tube. The current is controlled to drive the light emitting element DO to emit light. Moreover, the pixel driving circuit 100 employs three control signals, that is, a first scan signal, a second scan signal, and an illumination control signal.
  • the pixel driving circuit 100 of the embodiment of the present disclosure introduces three control signals, the first scanning signal is actually the scanning signal of the previous row, and only two control signals are still inside the actual input display device, thus achieving The simplified purpose of the circuit control signal.
  • the operational stages of the pixel drive circuit 100 of the embodiments of the present disclosure may sequentially include a reset phase, a write compensation phase, and an illumination drive phase as follows. Further, a buffer phase D3 as follows may be included between the write compensation phase D2 and the illumination driving phase D4. The following is an example in which the first scan signal is the previous row scan signal S(n-1), the second scan signal is the current row scan signal S(n), and the illumination control signal is the current row illumination control signal EM(n).
  • the first scan signal and the light emission control signal are at a low level and the second scan signal is at a high level
  • the first transistor T1, the second transistor T2, and the third transistor are T3 is turned on
  • the fourth transistor T4 and the fifth transistor T5 are turned off
  • the second preset power source Vref resets the storage capacitor Cs through the third transistor T3
  • the first preset power source VDD performs the storage capacitor Cs through the first transistor T1.
  • the previous row scan signal S(n-1), the current row light emission control signal EM(n) is at a low level, and the current row scan signal S(n) is at a high level.
  • the lower row scan signal S(n-1) of the lower level is supplied to the gate of the third transistor T3 through the first scan terminal S1, and the third transistor T3 is turned on under the driving of the low level, and is low in power.
  • the flat current row light emission control signal EM(n) is supplied to the gates of the first transistor T1 and the second transistor T2 through the light emission control terminal EM, and the first transistor T1 and the second transistor T2 are driven to be driven at a low level, while
  • the current line scan signal S(n) of a high level is supplied to the gates of the fourth transistor T4 and the fifth transistor T5 through the second scan terminal S2, and the fourth transistor T4 and the fifth transistor T5 are turned off by the high level. .
  • the equivalent circuit diagram is shown in Figure 6.
  • the reference level of the second preset power source Vref reaches the p point (ie, the other end of the storage capacitor Cs) and the g point through the third transistor T3 (ie, Driving the gate of the transistor T6, clearing and resetting the data of the previous stage, while the high level of the first preset power supply VDD charges the storage capacitor Cs through the first transistor T1, at the end of the reset phase D1,
  • the voltage difference across the storage capacitor Cs can be: VDD-Vref.
  • the first scan signal and the light emission control signal are at a high level, and the second scan signal is at a low level, the first transistor T1, the second transistor T2, and the The three transistors T3 are turned off, the fourth transistor T4 and the fifth transistor T5 are turned on, the data signal is written to the gate of the driving transistor T6 through the fifth transistor T5, and the storage capacitor Cs is discharged through the driving transistor T6 until the driving transistor T6 is turned off.
  • the previous row scan signal S(n-1), the current row light emission control signal EM(n) is at a high level, and the current row scan signal S(n) is at a low level.
  • the upper row scan signal S(n-1) of the high level is supplied to the gate of the third transistor T3 through the first scan terminal S1, and the third transistor T3 is driven by the high level.
  • the current row light emission control signal EM(n) of the high level is supplied to the gates of the first transistor T1 and the second transistor T2 through the light emission control terminal EM, and the first transistor T1 and the second transistor T2 are at a high level.
  • the current low row current row scan signal S(n) is supplied to the gates of the fourth transistor T4 and the fifth transistor T5 through the second scan terminal S2, and the fourth transistor T4 and the fifth transistor T5 are in low voltage Open under the flat drive.
  • the equivalent circuit diagram is shown in Figure 7.
  • the fourth transistor T4 and the fifth transistor T5 Due to the fourth transistor T4 and the fifth transistor T5, the other end of the storage capacitor Cs is still connected to the second preset power source Vref, and one end of the storage capacitor Cs is disconnected from the first preset power source VDD, but the potential is still a predetermined high level of the power supply VDD, while the data signal is written to the gate of the driving transistor T6, that is, the g point, through the fifth transistor T5. Since the data voltage Vdata is lower than the high level of the first predetermined power supply VDD, the driving transistor T6 It is not cut off.
  • the storage capacitor Cs discharges the low potential of the third predetermined power source VSS through the driving transistor T6 (but the generated current is insufficient to drive the light emitting element DO to emit light), and one end of the storage capacitor Cs is q.
  • the potential of the point begins to decrease until the potential drops to the sum of the voltage Vdata of the data signal and the absolute value of the threshold voltage, that is, Vdata+
  • the voltage difference across the storage capacitor Cs is Vdata+
  • the falling edge of the second scan signal is provided to the second scan terminal S2 and the light emission control terminal EM simultaneously with the rising edge of the light emission control signal. That is, when the external control signal is applied, the falling edge of the current line scanning signal S(n) must be aligned with the rising edge of the current line lighting control signal EM(n).
  • the falling edge of the second scan signal and the rising edge of the first scan signal need not be simultaneously provided to the second scan end S2 and the first scan end S1, that is, the previous line scan signal S(n-1)
  • the rising edge of the ) does not have to be aligned with the falling edge of the current line scan signal S(n), ie it may not be aligned.
  • the first scan signal, the second scan signal, and the light emission control signal are all at a high level, and the first transistor T1, the second transistor T2, the third transistor T3, and the fourth Both the transistor T4 and the fifth transistor T5 are turned off to suppress interference.
  • the upper line scanning signal S(n-1), the current line lighting control signal EM(n), and the current line scanning signal S(n) are at a high level.
  • the upper-level scan signal S(n-1) of the high level is supplied to the gate of the third transistor T3 through the first scan terminal S1, and the third transistor T3 is turned off under the driving of the high level, and the high voltage
  • the flat current row light emission control signal EM(n) is supplied to the gates of the first transistor T1 and the second transistor T2 through the light emission control terminal EM, and the first transistor T1 and the second transistor T2 are turned off by the high level driving while
  • the current line scan signal S(n) of a high level is supplied to the gates of the fourth transistor T4 and the fifth transistor T5 through the second scan terminal S2, and the fourth transistor T4 and the fifth transistor T5 are turned off by the high level.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all turned off to avoid unnecessary noise.
  • the first scanning signal and the second scanning signal are both at a high level, and the illuminating control signal is at a low level, and the first transistor T1 and the second transistor T2 are turned on.
  • the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned off, and the driving transistor T6 generates a light-emitting current under the action of the storage capacitor Cs.
  • the previous row scan signal S(n-1) and the current row scan signal S(n) are both at a high level, and the current row illumination control signal EM(n) is at a low level.
  • the upper-level scan signal S(n-1) of the high level is supplied to the gate of the third transistor T3 through the first scan terminal S1, and the third transistor T3 is turned off under the driving of the high level, and the high voltage
  • the flat current line scan signal S(n) is supplied to the gates of the fourth transistor T4 and the fifth transistor T5 through the second scan terminal S2, and the fourth transistor T4 and the fifth transistor T5 are turned off by the driving of the high level.
  • the current row light emission control signal EM(n) of the low level is supplied to the gates of the first transistor T1 and the second transistor T2 through the light emission control terminal EM, and the first transistor T1 and the second transistor T2 are driven at a low level. Open under. Among them, the equivalent circuit diagram is shown in Figure 9.
  • the illuminating current Ioled generated by the driving transistor T6 is:
  • K is a constant related to process and design.
  • the light-emission current Ioled supplied to the light-emitting element DO such as the organic light-emitting diode is only related to the voltage Vdata of the data signal and the reference voltage Vref of the second predetermined power source, and is independent of the threshold voltage Vthd of the driving transistor T6, thereby eliminating The effect of the voltage threshold of the drive transistor T6 on the display uniformity.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the driving transistor T6 of the embodiment of the present disclosure are all P-type transistors, thereby ensuring simplification of the process, and simultaneously The actual input still has only 2 control signals, so that the circuit control signal can be kept simple at the same time.
  • the reset unit is turned on according to the first scan signal provided by the first scan terminal to reset the storage capacitor and charge the storage capacitor
  • the write compensation unit is The second scan signal provided by the two scanning ends is turned on, so that the data signal provided by the data input terminal is written into the gate of the driving transistor, and the storage capacitor is discharged through the writing compensation unit and the driving transistor until the driving transistor is turned off
  • the light emitting control unit is The illumination control signal provided by the illumination control terminal is turned on to drive the driving transistor to generate an illumination current together with the storage capacitor to drive the illumination element in the pixel to emit light
  • the first scan signal is output before the second scan signal, thereby eliminating the threshold of the driving transistor.
  • an embodiment of the present disclosure also proposes a display panel including the pixel driving circuit of the above embodiment.
  • the influence of the threshold voltage unevenness of the driving transistor on the display uniformity can be eliminated, and the simplification of the process process can be ensured, and the simplification of the circuit control signal can be maintained as much as possible.
  • an embodiment of the present disclosure further provides a display device including the display panel of the above embodiment.
  • the influence of the threshold voltage unevenness of the driving transistor on the display uniformity can be eliminated, and the simplification of the process process can be ensured, and the simplification of the circuit control signal can be maintained as much as possible.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” or “second” may include at least one of the features, either explicitly or implicitly.
  • the meaning of "a plurality” is at least two, such as two, three, etc., unless specifically defined otherwise.
  • the terms “installation”, “connected”, “connected”, “fixed”, and the like, are to be understood broadly, and may be either a fixed connection or a detachable connection, unless explicitly stated or defined otherwise. , or integrated; can be mechanical or electrical connection; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of two elements or the interaction of two elements, unless otherwise specified Limited.
  • the specific meanings of the above terms in the present disclosure can be understood by those skilled in the art on a case-by-case basis.
  • the first feature "on” or “under” the second feature may be a direct contact of the first and second features, or the first and second features may be indirectly through an intermediate medium, unless otherwise explicitly stated and defined. contact.
  • the first feature "above”, “above” and “above” the second feature may be that the first feature is directly above or above the second feature, or merely that the first feature level is higher than the second feature.
  • the first feature is in the second feature "Lower”, “below” and “below” may be that the first feature is directly below or obliquely below the second feature, or merely that the first feature level is less than the second feature.
  • the influence of the threshold voltage unevenness of the driving transistor on the display uniformity can be eliminated, and the simplification of the process process can be ensured, and the simplification of the circuit control signal can be maintained as much as possible.

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Abstract

一种显示装置、显示面板和像素驱动电路（100），像素驱动电路（100）包括驱动晶体管、第一扫描端、第二扫描端、数据输入端、发光控制端、存储电容、重置单元（10）、写入补偿单元（20）和发光控制单元（30），其中，重置单元（10）根据第一扫描端提供的第一扫描信号开通，以对存储电容进行重置并对存储电容进行充电；写入补偿单元（20）根据第二扫描端提供的第二扫描信号开通，以使数据输入端提供的数据信号写入驱动晶体管的栅极，并使存储电容通过写入补偿单元（20）和驱动晶体管放电直至驱动晶体管截止；发光控制单元（30）根据发光控制端提供的发光控制信号开通，以与存储电容共同驱动驱动晶体管生成发光电流以驱动像素中的发光元件发光，从而简化工艺制程，同时简化电路控制信号。

Description

显示装置、显示面板、像素驱动电路和驱动方法
相关申请的交叉引用
本申请要求于2017年03月06日递交的中国专利申请第201710128154.2号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，特别涉及一种像素驱动电路、一种显示面板、一种显示装置以及一种驱动方法。
背景技术
相关的显示装置不管是采用LTPS(Low Temperature Poly-silicon，低温多晶硅)工艺还是采用Oxide(氧化物)工艺，由于工艺的不均匀性，都会导致不同位置的驱动晶体管出现阈值电压的差异，进而对不同位置的像素的发光产生影响，导致显示不均匀。
在相关技术中，通常是通过像素驱动电路本身对驱动管阈值电压做补偿，以解决阈值电压不均导致的显示不均匀性的问题。但是，相关技术存在的问题是，电路中既有P型晶体管又有N型晶体管，从而导致工艺制程复杂，成本增加，而如果将晶体管全部改成P型晶体管，那么需增加控制信号才能满足电路的要求，从而将会导致外围电路的设计进一步复杂化。
发明内容
本公开旨在至少在一定程度上解决相关技术中的技术问题之一。为此，本公开的一个目的在于提出一种像素驱动电路，该像素驱动电路在保证工艺制程简单的同时，尽量维持电路控制信号的简单化。
本公开的另一个目的在于提出一种显示面板。本公开的又一个目的在于提出一种显示装置。本公开的又一个目的在于提出一种驱动 像素的方法。
为达到上述目的，本公开一方面实施例提出了一种像素驱动电路，包括驱动晶体管、第一扫描端、第二扫描端、数据输入端、发光控制端、存储电容、重置单元、写入补偿单元和发光控制单元，其中，所述存储电容与所述驱动晶体管相连；所述重置单元与第一扫描端相连，所述重置单元根据所述第一扫描端提供的第一扫描信号开通，以对所述存储电容进行重置并对所述存储电容进行充电；所述写入补偿单元分别与第二扫描端和数据输入端相连，所述写入补偿单元根据所述第二扫描端提供的第二扫描信号开通，以使所述数据输入端提供的数据信号写入所述驱动晶体管的栅极，并使所述储存电容通过所述写入补偿单元和所述驱动晶体管放电直至所述驱动晶体管截止；所述发光控制单元与所述发光控制端相连，所述发光控制单元根据所述发光控制端提供的发光控制信号开通，以与所述储存电容共同驱动所述驱动晶体管生成所述发光电流以驱动像素中的发光元件发光；其中，所述第一扫描信号先于所述第二扫描信号输出。
根据本公开实施例提出的像素驱动电路，重置单元根据第一扫描端提供的第一扫描信号开通，以对存储电容进行重置并对存储电容进行充电，写入补偿单元根据第二扫描端提供的第二扫描信号开通，以使数据输入端提供的数据信号写入驱动晶体管的栅极，并使储存电容通过写入补偿单元和驱动晶体管放电直至驱动晶体管截止，发光控制单元根据发光控制端提供的发光控制信号开通，以与储存电容共同驱动驱动晶体管生成发光电流以驱动像素中的发光元件发光，且第一扫描信号先于第二扫描信号输出，从而能够消除驱动晶体管的阈值电压不均对显示均匀性的影响，并且能保证工艺制程的简单化，同时尽量维持电路控制信号的简单化。
根据本公开的一个实施例，所述存储电容的一端与所述驱动晶体管的第二极相连，所述发光控制单元包括第一晶体管和第二晶体管，所述第一晶体管的栅极与所述发光控制端相连，所述第一晶体管的第二极与第一预设电源相连，所述第一晶体管的第一极与所述驱动晶体管的第二极相连，所述第二晶体管的栅极与所述发光控制端相 连，所述第二晶体管的第一极与所述存储电容的另一端相连，所述第二晶体管的第二极与所述驱动晶体管的栅极相连。
根据本公开的一个实施例，所述重置单元与所述发光控制单元共用所述第一晶体管，所述重置单元还包括第三晶体管，所述第三晶体管的栅极与所述第一扫描端相连，所述第三晶体管的第一极与第二预设电源相连，所述第三晶体管的第二极与所述存储电容的一端相连。
根据本公开的一个实施例，所述写入补偿单元包括第四晶体管和第五晶体管，所述第四晶体管的栅极与所述第二扫描端相连，所述第四晶体管的第一极与所述第二预设电源相连，所述第四晶体管的第二极与所述存储电容的一端相连，所述第五晶体管的栅极与所述第二扫描端相连，所述第五晶体管的第一极与所述数据输入端相连，所述第五晶体管的第二极与所述驱动晶体管的栅极相连。
根据本公开的一个实施例，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管和所述第五晶体管均为P型晶体管。
根据本公开的一个实施例，所述像素驱动电路的工作阶段依次包括重置阶段、写入补偿阶段和发光驱动阶段，其中，在所述重置阶段，所述第一扫描信号和所述发光控制信号为低电平且所述第二扫描信号为高电平，所述第一晶体管、所述第二晶体管和所述第三晶体管开启，所述第四晶体管和所述第五晶体管截止，所述第二预设电源通过所述第三晶体管对所述存储电容进行重置，同时所述第一预设电源通过所述第一晶体管对所述存储电容进行充电；在所述写入补偿阶段，所述第一扫描信号和所述发光控制信号为高电平，且所述第二扫描信号为低电平，所述第一晶体管、所述第二晶体管和所述第三晶体管截止，所述第四晶体管和所述第五晶体管开启，所述数据信号通过所述第五晶体管写入所述驱动晶体管的栅极，所述存储电容通过所述驱动晶体管放电直至所述驱动晶体管截止；在所述发光驱动阶段，所述第一扫描信号和所述第二扫描信号均为高电平，且发光控制信号为低电平，所述第一晶体管、所述第二晶体管开启，所述第三晶体管、 所述第四晶体管和所述第五晶体管截止，所述驱动晶体管在所述存储电容的作用下生成所述发光电流。
根据本公开的一个实施例，在所述写入补偿阶段与所述发光驱动阶段之间还包括缓冲阶段，其中，在所述缓冲阶段，所述第一扫描信号、所述第二扫描信号和所述发光控制信号均为高电平，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管和所述第五晶体管均截止，以抑制干扰。
根据本公开的一个实施例，在所述写入补偿阶段，所述第二扫描信号的下降沿与所述发光控制信号的上升沿同时提供至第二扫描端和发光控制端。
为达到上述目的，本公开另一方面实施例提出了一种显示面板，包括所述的像素驱动电路。
根据本公开实施例提出的显示面板，能够消除驱动晶体管的阈值电压不均对显示均匀性的影响，并且能保证工艺制程的简单化，同时尽量维持电路控制信号的简单化。
为达到上述目的，本公开又一方面实施例提出了一种显示装置，包括所述的显示面板。
为达到上述目的，本公开又一方面实施例提出了一种利用像素驱动电路来驱动像素的方法，包括：重置阶段，所述第一扫描信号和所述发光控制信号为低电平且所述第二扫描信号为高电平，所述第一晶体管、所述第二晶体管和所述第三晶体管开启，所述第四晶体管和所述第五晶体管截止，所述第二预设电源通过所述第三晶体管对所述存储电容进行重置，同时所述第一预设电源通过所述第一晶体管对所述存储电容进行充电；写入补偿阶段，所述第一扫描信号和所述发光控制信号为高电平，且所述第二扫描信号为低电平，所述第一晶体管、所述第二晶体管和所述第三晶体管截止，所述第四晶体管和所述第五晶体管开启，所述数据信号通过所述第五晶体管写入所述驱动晶体管的栅极，所述存储电容通过所述驱动晶体管放电直至所述驱动晶体管截止；发光驱动阶段，所述第一扫描信号和所述第二扫描信号均为高电平，且发光控制信号为低电平，所述第一晶体管、所述第二晶体管 开启，所述第三晶体管、所述第四晶体管和所述第五晶体管截止，所述驱动晶体管在所述存储电容的作用下生成所述发光电流。
附图说明
图1是相关技术中像素驱动电路的原理图；
图2是相关技术中像素驱动电路的控制时序图；
图3是根据本公开实施例的像素驱动电路的方框示意图；
图4是根据本公开一个实施例的像素驱动电路的电路原理图；
图5是根据本公开一个实施例的像素驱动电路的控制时序图；
图6是根据本公开一个实施例的像素驱动电路在重置阶段的等效电路图；
图7是根据本公开一个实施例的像素驱动电路在写入补偿阶段的等效电路图；
图8是根据本公开一个实施例的像素驱动电路在缓冲阶段的等效电路图；以及
图9是根据本公开一个实施例的像素驱动电路在发光控制阶段的等效电路图。
具体实施方式
下面详细描述本公开的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，旨在用于解释本公开，而不能理解为对本公开的限制。
下面对相关技术中的像素驱动电路进行简单介绍。
图1是相关技术中像素驱动电路的原理图。如图1和图2所示，像素驱动电路的工作原理如下：
在阶段1’：扫描信号scan’为高电平，EM’信号为低电平，此时像素驱动电路中的晶体管T1’、T2’、T3’开启，晶体管T4’关闭，预设电源VSS’和VDD’同时对存储电容Cst’充电，Vdata’信号则写入到驱动管DTFT’的栅极，该阶段1’完成时存储电容Cst’两端的电压为 VDD’-VSS’；
在阶段2’：扫描信号scan’继续为高电平，EM’信号也变为高电平，此时像素驱动电路中的晶体管T1’、T4’截止，T2’、T3’开启，存储电容Cst’通过驱动管DTFT’放电，直到存储电容Cst’连接驱动管DTFT’的一端电位下降为Vdata’+|Vth’|(Vth’为驱动管DTFT’的阈值电压)，此时驱动管DTFT’自动截止，补偿完成；
在阶段3’：扫描信号scan’为低电平，EM’信号变为低电平，此时像素驱动电路中的晶体管T1’、T4’开启，T2’、T3’截止，像素发光。
上述电路虽然解决了阈值电压不均导致的显示不均匀性问题，但是由于电路中T1’、T4’、DTFT’为P型晶体管，而T2’、T3’为N型晶体管，因此导致工艺制程复杂，成本增加；而如果将T2’、T3’全部改成P型TFT，那么T2’、T3’、T4’的栅极不能共用一个扫描信号Scan’，必须另外增加控制信号才能满足电路的要求，这样就导致了外围电路的设计进一步复杂化。
由此可知，相关技术的像素驱动电路要么工艺制程复杂，要么电路的控制信号过于复杂。
基于此，本公开实施例提出了一种像素驱动电路、一种显示装置以及一种电子设备。
下面结合附图3至图9描述本公开实施例的像素驱动电路、显示装置以及电子设备。
图3是根据本公开实施例的像素驱动电路的方框示意图。如图3所示，该像素驱动电路100包括驱动晶体管T6、第一扫描端S1、第二扫描端S2、数据输入端Vdata、发光控制端EM、存储电容Cs、重置单元10、写入补偿单元20和发光控制单元30。
其中，存储电容Cs与驱动晶体管T6相连；重置单元10与第一扫描端S1相连，重置单元10根据第一扫描端S1提供的第一扫描信号开通，以对存储电容Cs进行重置并对存储电容Cs进行充电；写入补偿单元20分别与第二扫描端S2和数据输入端Vdata相连，写入补偿单元20根据第二扫描端S2提供的第二扫描信号开通，以使数 据输入端Vdata提供的数据信号写入驱动晶体管T6的栅极，并使储存电容Cs通过写入补偿单元20和驱动晶体管T6放电直至驱动晶体管T6截止；发光控制单元30与发光控制端EM相连，发光控制单元30根据发光控制端EM提供的发光控制信号开通，以与储存电容Cs共同驱动驱动晶体管T6生成发光电流以驱动像素中的发光元件DO发光；其中，第一扫描信号先于第二扫描信号输出。
需要说明的是，像素驱动电路100可用于驱动像素阵列中的像素发光，即言，像素阵列中每个像素均与对应的像素驱动电路100相连，以在对应的像素驱动电路100的驱动下发光。具体地，每个像素的发光元件DO能由驱动晶体管T6在饱和状态时产生的电流所驱动，即电流驱动发光。
在本公开一些实施例中，像素阵列可采用逐行扫描的扫描方式，即顺序地一行接着一行连续扫描。此时，上一行例如第n-1行像素先扫描，当前行例如第n行像素后扫描，第一扫描信号可为上一行扫描信号，且第二扫描信号为当前行扫描信号。
由此，在对当前行像素的扫描时，上一行扫描信号通过第一扫描端S1提供至重置单元10，当前行扫描信号通过第二扫描端S2提供至写入补偿单元20，重置单元10可在上一行扫描信号的控制先开通，此时通过重置单元10可对存储电容Cs进行重置并对存储电容Cs进行充电，从而利用上一行扫描信号对当前行的每个像素对应的像素驱动电路100进行置位和对当前行的每个像素对应的存储电容Cs进行充电。
在重置单元10在上一行扫描信号的控制关断后，写入补偿单元20可在当前行扫描信号的控制下后开通，此时数据输入端Vdata提供的数据信号通过写入补偿单元20写入驱动晶体管T6的栅极，固定驱动晶体管T6的栅极电位，并且储存电容Cs通过写入补偿单元20和驱动晶体管T6放电直至驱动晶体管T6截止，实现驱动晶体管T6的阈值补偿，从而利用当前行扫描信号对当前行的每个像素进行数据信号的写入和电压阈值的补偿。
在写入补偿单元20在当前行扫描信号的控制下关断后，发光控 制单元30可在发光控制端EM提供的发光控制信号的控制下开通，发光控制单元30与储存电容Cs共同驱动驱动晶体管T6生成发光电流，以驱动像素中的发光元件DO发光。
由此，在本公开实施例中，利用上一行扫描信号对像素驱动电路100进行重置和对存储电容Cs充电，利用当前行扫描信号写入数据信号以固定驱动晶体管T6的栅极电位，同时存储电容Cs通过驱动晶体管T6的自放电直至驱动晶体管T6自动截止实现驱动晶体管T6的阈值补偿，从而消除驱动晶体管T6的电压阈值对显示均匀性的影响，在保证工艺制程简单的同时，尽量维持电路控制信号的简单化，解决相关技术中要么工艺制程复杂要么控制信号复杂的一对矛盾。
根据本公开的一个具体实施例，发光元件DO可为发光二极管，更具体地，可为有机发光二极管。
下面结合图4至图9描述本公开实施例的像素驱动电路100的电路结构和工作原理。
根据本公开的一个实施例，如图4所示，存储电容Cs的一端与驱动晶体管T6的第二极例如源极相连，发光控制单元30包括第一晶体管T1和第二晶体管T2，第一晶体管T1的栅极与发光控制端EM相连，第一晶体管T1的第二极例如源极与第一预设电源VDD相连，第一晶体管T1的第一极例如漏极与驱动晶体管T6的第二极例如源极相连，第二晶体管T2的栅极与发光控制端EM相连，第二晶体管T2的第一极例如漏极与存储电容Cs的另一端相连，第二晶体管T2的第二极例如源极与驱动晶体管T6的栅极相连。
其中，驱动晶体管T6的第一极例如漏极与发光元件DO的阳极相连，发光元件DO的阴极与第三预设电源VSS相连，第一预设电源VDD可提供高电平，第三预设电源VSS可提供低电平。
根据本公开的一个实施例，如图4所示，重置单元10与发光控制单元30共用第一晶体管T1，重置单元10还包括第三晶体管T3，第三晶体管T3的栅极与第一扫描端S1相连，第三晶体管T3的第一极例如漏极与第二预设电源Vref相连，第三晶体管T3的第二极例如源极与存储电容Cs的一端相连，其中，第二预设电源Vref可提供参 考电平，参考电平可低于高电平。
根据本公开的一个实施例，如图4所示，写入补偿单元20包括第四晶体管T4和第五晶体管T5，第四晶体管T4的栅极与第二扫描端S2相连，第四晶体管T4的第一极例如漏极与第二预设电源Vref相连，第四晶体管T4的第二极例如源极与存储电容Cs的一端相连，第五晶体管T5的栅极与第二扫描端S2相连，第五晶体管T5的第一极例如漏极与数据输入端Vdata相连，第五晶体管T5的第二极例如源极与驱动晶体管T6的栅极相连。
其中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5均可为P型晶体管。并且，驱动晶体管T6也可为P型晶体管。更具体地，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和驱动晶体管T6均可TFT(Thin Film Transistor，薄膜晶体管)管。
根据本公开的一个实施例，第二预设电源Vref的电平值小于或等于数据输入端Vdata提供的数据信号的最小电平值。
如上所述，如图4的实施例，本公开实施例的像素驱动电路100包括6个晶体管和1个存储电容Cs，T1～T5均为开关管，用作电路开关，T6为驱动管，用于控制电流以驱动发光元件DO发光。并且，像素驱动电路100采用3路控制信号，即第一扫描信号、第二扫描信号和发光控制信号。
应当理解的是，本公开实施例的像素驱动电路100虽然引入了3路控制信号，但第一扫描信号实际为上一行扫描信号，实际输入显示装置内部的仍然只有2路控制信号，因此达到了电路控制信号的简化目的。
结合图4的实施例，本公开实施例的像素驱动电路100的工作阶段可依次包括如下的重置阶段、写入补偿阶段和发光驱动阶段。进一步地，在写入补偿阶段D2与发光驱动阶段D4之间还可包括如下的缓冲阶段D3。下面以第一扫描信号为上一行扫描信号S(n-1)、第二扫描信号为当前行扫描信号S(n)、发光控制信号为当前行发光控制信号EM(n)为例进行介绍。
如图5和图6所示，在重置阶段D1，第一扫描信号和发光控制信号为低电平且第二扫描信号为高电平，第一晶体管T1、第二晶体管T2和第三晶体管T3开启，第四晶体管T4和第五晶体管T5截止，第二预设电源Vref通过第三晶体管T3对存储电容Cs进行重置，同时第一预设电源VDD通过第一晶体管T1对存储电容Cs进行充电。
也就是说，在重置阶段D1，上一行扫描信号S(n-1)、当前行发光控制信号EM(n)为低电平，当前行扫描信号S(n)为高电平。
在此阶段，低电平的上一行扫描信号S(n-1)通过第一扫描端S1提供至第三晶体管T3的栅极，第三晶体管T3在低电平的驱动下开启，且低电平的当前行发光控制信号EM(n)通过发光控制端EM提供至第一晶体管T1和第二晶体管T2的栅极，第一晶体管T1和第二晶体管T2在低电平的驱动下开启，同时高电平的当前行扫描信号S(n)通过第二扫描端S2提供至第四晶体管T4和第五晶体管T5的栅极，第四晶体管T4和第五晶体管T5在高电平的驱动下截止。其中，等效电路图如图6所示。
由于第一晶体管T1、第二晶体管T2和第三晶体管T3开启，因此第二预设电源Vref的参考电平通过第三晶体管T3到达p点(即存储电容Cs的另一端)和g点(即驱动晶体管T6的栅极)，对上一阶段的数据进行清除和重置，同时第一预设电源VDD的高电平通过第一晶体管T1对存储电容Cs充电，在重置阶段D1结束时，存储电容Cs两端的电压差可为：VDD-Vref。
如图5和图7所示，在写入补偿阶段D2，第一扫描信号和发光控制信号为高电平，且第二扫描信号为低电平，第一晶体管T1、第二晶体管T2和第三晶体管T3截止，第四晶体管T4和第五晶体管T5开启，数据信号通过第五晶体管T5写入驱动晶体管T6的栅极，存储电容Cs通过驱动晶体管T6放电直至驱动晶体管T6截止。
也就是说，在写入补偿阶段D2，上一行扫描信号S(n-1)、当前行发光控制信号EM(n)为高电平，当前行扫描信号S(n)为低电平。
在此阶段，高电平的上一行扫描信号S(n-1)通过第一扫描端S1提供至第三晶体管T3的栅极，第三晶体管T3在高电平的驱动下截 止，且高电平的当前行发光控制信号EM(n)通过发光控制端EM提供至第一晶体管T1和第二晶体管T2的栅极，第一晶体管T1和第二晶体管T2在高电平的驱动下截止，同时低电平的当前行扫描信号S(n)通过第二扫描端S2提供至第四晶体管T4和第五晶体管T5的栅极，第四晶体管T4和第五晶体管T5在低电平的驱动下开启。其中，等效电路图如图7所示。
由于第四晶体管T4和第五晶体管T5，因此存储电容Cs的另一端仍与第二预设电源Vref连接，存储电容Cs的一端虽然已经与第一预设电源VDD断开，但电位仍为第一预设电源VDD的高电平，同时数据信号通过第五晶体管T5写入驱动晶体管T6的栅极即g点，由于数据电压Vdata小于第一预设电源VDD的高电平，因此驱动晶体管T6并未截止，从该阶段开始，存储电容Cs会通过驱动晶体管T6对第三预设电源VSS的低电位进行放电(但产生的电流不足以驱动发光元件DO发光)，存储电容Cs的一端即q点的电位开始持续下降，直到电位下降为数据信号的电压Vdata与阈值电压的绝对值之和，即Vdata+|Vthd|，其中，Vthd为驱动晶体管T6的阈值电压，此时驱动晶体管T6自动截止，在写入补偿阶段D2结束时，存储电容Cs两端的电压差为Vdata+|Vthd|-Vref。
其中，需要说明的是，在写入补偿阶段D2，第二扫描信号的下降沿与发光控制信号的上升沿同时提供至第二扫描端S2和发光控制端EM。也就是说，在外部控制信号给入时，当前行扫描信号S(n)的下降沿与当前行发光控制信号EM(n)的上升沿须对齐。
还需说明的是，第二扫描信号的下降沿与第一扫描信号的上升沿无需同时提供至第二扫描端S2和第一扫描端S1，也就是说，上一行扫描信号S(n-1)的上升沿不是必须与当前行扫描信号S(n)的下降沿对齐，即可以不用对齐。
如图5和图8所示，在缓冲阶段D3，第一扫描信号、第二扫描信号和发光控制信号均为高电平，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5均截止，以抑制干扰。
也就是说，在缓冲阶段D3，上一行扫描信号S(n-1)、当前行发光控制信号EM(n)和当前行扫描信号S(n)为高电平。
在此阶段，高电平的上一行扫描信号S(n-1)通过第一扫描端S1提供至第三晶体管T3的栅极，第三晶体管T3在高电平的驱动下截止，且高电平的当前行发光控制信号EM(n)通过发光控制端EM提供至第一晶体管T1和第二晶体管T2的栅极，第一晶体管T1和第二晶体管T2在高电平的驱动下截止，同时高电平的当前行扫描信号S(n)通过第二扫描端S2提供至第四晶体管T4和第五晶体管T5的栅极，第四晶体管T4和第五晶体管T5在高电平的驱动下截止，其中，等效电路图如图8所示。
第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5均截止，可避免不必要的杂讯。
如图5和图9所示，在发光驱动阶段D4，第一扫描信号和第二扫描信号均为高电平，且发光控制信号为低电平，第一晶体管T1、第二晶体管T2开启，第三晶体管T3、第四晶体管T4和第五晶体管T5截止，驱动晶体管T6在存储电容Cs的作用下生成发光电流。
也就是说，在发光驱动阶段D4，上一行扫描信号S(n-1)、当前行扫描信号S(n)都为高电平，当前行发光控制信号EM(n)为低电平。
在此阶段，高电平的上一行扫描信号S(n-1)通过第一扫描端S1提供至第三晶体管T3的栅极，第三晶体管T3在高电平的驱动下截止，且高电平的当前行扫描信号S(n)通过第二扫描端S2提供至第四晶体管T4和第五晶体管T5的栅极，第四晶体管T4和第五晶体管T5在高电平的驱动下截止。同时，低电平的当前行发光控制信号EM(n)通过发光控制端EM提供至第一晶体管T1和第二晶体管T2的栅极，第一晶体管T1和第二晶体管T2在低电平的驱动下开启。其中，等效电路图如图9所示。
由于第二晶体管T2开启，存储电容Cs的另一端相当于与驱动晶体管T6的栅极相连，驱动晶体管T6的栅极即g点悬空，因此驱动晶体管T6的源极和栅极之间的电压Vsg即为写入补偿阶段D2结束时存储电容Cs两端的电压差VCs，即VCs＝Vdata+|Vthd|-Vref。并 且，由于驱动晶体管T6的源极和漏极之间的电压Vsd大于驱动晶体管T6的源极和栅极之间的电压Vsg与驱动晶体管T6的阈值电压之差，即Vsd>Vsg-|Vthd|，驱动晶体管T6工作在饱和状态，因此，驱动晶体管T6产生的发光电流Ioled为：
Ioled＝K×(Vsg-|Vthd|)^2＝K×(VCs-|Vthd|)^2＝K×(Vdata+|Vthd|-Vref-|Vthd|)^2＝K×(Vdata-Vref)^2
其中，K为与工艺和设计有关的常数。
由上式可知，提供至发光元件DO例如有机发光二极管的发光电流Ioled只与数据信号的电压Vdata和第二预设电源的参考电压Vref有关，而与驱动晶体管T6的阈值电压Vthd无关，从而消除驱动晶体管T6的电压阈值对显示均匀性的影响。并且，本公开实施例的第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和驱动晶体管T6均P型晶体管，从而可保证工艺制程的简单化，同时实际输入的仍然只有2路控制信号，从而可同时维持电路控制信号的简单化。
综上，根据本公开实施例提出的像素驱动电路，重置单元根据第一扫描端提供的第一扫描信号开通，以对存储电容进行重置并对存储电容进行充电，写入补偿单元根据第二扫描端提供的第二扫描信号开通，以使数据输入端提供的数据信号写入驱动晶体管的栅极，并使储存电容通过写入补偿单元和驱动晶体管放电直至驱动晶体管截止，发光控制单元根据发光控制端提供的发光控制信号开通，以与储存电容共同驱动驱动晶体管生成发光电流以驱动像素中的发光元件发光，且第一扫描信号先于第二扫描信号输出，从而能够消除驱动晶体管的阈值电压不均对显示均匀性的影响，并且能保证工艺制程的简单化，同时尽量维持电路控制信号的简单化。
另外，本公开实施例还提出了一种显示面板，包括上述实施例的像素驱动电路。
根据本公开实施例提出的显示面板，能够消除驱动晶体管的阈值电压不均对显示均匀性的影响，并且能保证工艺制程的简单化，同时尽量维持电路控制信号的简单化。
最后，本公开实施例又提出了一种显示装置，包括上述实施例的显示面板。
根据本公开实施例提出的显示装置，能够消除驱动晶体管的阈值电压不均对显示均匀性的影响，并且能保证工艺制程的简单化，同时尽量维持电路控制信号的简单化。
在本公开的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”、“顺时针”、“逆时针”、“轴向”、“径向”、“周向”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本公开的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系，除非另有明确的限定。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
在本公开中，除非另有明确的规定和限定，第一特征在第二特征“上”或“下”可以是第一和第二特征直接接触，或第一和第二特征通过中间媒介间接接触。而且，第一特征在第二特征“之上”、“上方”和“上面”可是第一特征在第二特征正上方或斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之 下”、“下方”和“下面”可以是第一特征在第二特征正下方或斜下方，或仅仅表示第一特征水平高度小于第二特征。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
根据本公开实施例提出的显示装置，能够消除驱动晶体管的阈值电压不均对显示均匀性的影响，并且能保证工艺制程的简单化，同时尽量维持电路控制信号的简单化。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (13)

  1. 一种像素驱动电路，包括驱动晶体管、第一扫描端、第二扫描端、数据输入端、发光控制端、存储电容、重置单元、写入补偿单元和发光控制单元，其中，
    所述存储电容与所述驱动晶体管相连；
    所述重置单元与第一扫描端相连，所述重置单元根据所述第一扫描端提供的第一扫描信号开通，以对所述存储电容进行重置并对所述存储电容进行充电；
    所述写入补偿单元分别与第二扫描端和数据输入端相连，所述写入补偿单元根据所述第二扫描端提供的第二扫描信号开通，以使所述数据输入端提供的数据信号写入所述驱动晶体管的栅极，并使所述储存电容通过所述写入补偿单元和所述驱动晶体管放电直至所述驱动晶体管截止；
    所述发光控制单元与所述发光控制端相连，所述发光控制单元根据所述发光控制端提供的发光控制信号开通，以与所述储存电容共同驱动所述驱动晶体管生成所述发光电流以驱动像素中的发光元件发光；
    其中，所述第一扫描信号先于所述第二扫描信号输出。
  2. 根据权利要求1所述的像素驱动电路，其中，所述存储电容的一端与所述驱动晶体管的第二极相连，所述发光控制单元包括第一晶体管和第二晶体管，所述第一晶体管的栅极与所述发光控制端相连，所述第一晶体管的第二极与第一预设电源相连，所述第一晶体管的第一极与所述驱动晶体管的第二极相连，所述第二晶体管的栅极与所述发光控制端相连，所述第二晶体管的第一极与所述存储电容的另一端相连，所述第二晶体管的第二极与所述驱动晶体管的栅极相连。
  3. 根据权利要求2所述的像素驱动电路，其中，所述重置单元与所述发光控制单元共用所述第一晶体管，所述重置单元还包括第三晶体管，所述第三晶体管的栅极与所述第一扫描端相连，所述第三晶体管的第一极与第二预设电源相连，所述第三晶体管的第二极与所述存储电容的一端相连。
  4. 根据权利要求3所述的像素驱动电路，其中，所述写入补偿单元包括第四晶体管和第五晶体管，所述第四晶体管的栅极与所述第二扫描端相连，所述第四晶体管的第一极与所述第二预设电源相连，所述第四晶体管的第二极与所述存储电容的一端相连，所述第五晶体管的栅极与所述第二扫描端相连，所述第五晶体管的第一极与所述数据输入端相连，所述第五晶体管的第二极与所述驱动晶体管的栅极相连。
  5. 根据权利要求4所述的像素驱动电路，其中，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管和所述第五晶体管均为P型晶体管。
  6. 根据权利要求4所述的像素驱动电路，其中，所述像素驱动电路的工作阶段依次包括重置阶段、写入补偿阶段和发光驱动阶段，其中，
    在所述重置阶段，所述第一扫描信号和所述发光控制信号为低电平且所述第二扫描信号为高电平，所述第一晶体管、所述第二晶体管和所述第三晶体管开启，所述第四晶体管和所述第五晶体管截止，所述第二预设电源通过所述第三晶体管对所述存储电容进行重置，同时所述第一预设电源通过所述第一晶体管对所述存储电容进行充电；
    在所述写入补偿阶段，所述第一扫描信号和所述发光控制信号为高电平，且所述第二扫描信号为低电平，所述第一晶体管、所述第二晶体管和所述第三晶体管截止，所述第四晶体管和所述第五晶体管开启，所述数据信号通过所述第五晶体管写入所述驱动晶体管的栅极，所述存储电容通过所述驱动晶体管放电直至所述驱动晶体管截止；
    在所述发光驱动阶段，所述第一扫描信号和所述第二扫描信号均为高电平，且发光控制信号为低电平，所述第一晶体管、所述第二晶体管开启，所述第三晶体管、所述第四晶体管和所述第五晶体管截止，所述驱动晶体管在所述存储电容的作用下生成所述发光电流。
  7. 根据权利要求6所述的像素驱动电路，其中，在所述写入补偿阶段与所述发光驱动阶段之间还包括缓冲阶段，其中，
    在所述缓冲阶段，所述第一扫描信号、所述第二扫描信号和所述发光控制信号均为高电平，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管和所述第五晶体管均截止，以抑制干扰。
  8. 根据权利要求6所述的像素驱动电路，其中，其中，在所述写入补偿阶段，所述第二扫描信号的下降沿与所述发光控制信号的上升沿同时提供至第二扫描端和发光控制端。
  9. 一种显示面板，包括根据权利要求1-8中任一项所述的像素驱动电路。
  10. 一种显示装置，包括如权利要求9所述的显示面板。
  11. 一种利用权利要求4所述的像素驱动电路来驱动像素的方法，包括：
    重置阶段，所述第一扫描信号和所述发光控制信号为低电平且所述第二扫描信号为高电平，所述第一晶体管、所述第二晶体管和所述第三晶体管开启，所述第四晶体管和所述第五晶体管截止，所述第二预设电源通过所述第三晶体管对所述存储电容进行重置，同时所述第一预设电源通过所述第一晶体管对所述存储电容进行充电；
    写入补偿阶段，所述第一扫描信号和所述发光控制信号为高电平，且所述第二扫描信号为低电平，所述第一晶体管、所述第二晶体管和所述第三晶体管截止，所述第四晶体管和所述第五晶体管开启，所述数据信号通过所述第五晶体管写入所述驱动晶体管的栅极，所述存储电容通过所述驱动晶体管放电直至所述驱动晶体管截止；
    发光驱动阶段，所述第一扫描信号和所述第二扫描信号均为高电平，且发光控制信号为低电平，所述第一晶体管、所述第二晶体管开启，所述第三晶体管、所述第四晶体管和所述第五晶体管截止，所述驱动晶体管在所述存储电容的作用下生成所述发光电流。
  12. 根据权利要11所述的方法，其中，在所述写入补偿阶段与所述发光驱动阶段之间还包括缓冲阶段，其中，
    在所述缓冲阶段，所述第一扫描信号、所述第二扫描信号和所述发光控制信号均为高电平，所述第一晶体管、所述第二晶体管、所 述第三晶体管、所述第四晶体管和所述第五晶体管均截止，以抑制干扰。
  13. 根据权利要求11所述的方法，其中，其中，在所述写入补偿阶段，所述第二扫描信号的下降沿与所述发光控制信号的上升沿同时提供至第二扫描端和发光控制端。
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