WO2020062796A1 - 像素电路及其控制方法、显示面板、显示装置 - Google Patents

像素电路及其控制方法、显示面板、显示装置 Download PDF

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Publication number
WO2020062796A1
WO2020062796A1 PCT/CN2019/078044 CN2019078044W WO2020062796A1 WO 2020062796 A1 WO2020062796 A1 WO 2020062796A1 CN 2019078044 W CN2019078044 W CN 2019078044W WO 2020062796 A1 WO2020062796 A1 WO 2020062796A1
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Prior art keywords
transistor
pole
signal
pixel circuit
light
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PCT/CN2019/078044
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English (en)
French (fr)
Inventor
朱正勇
赵国华
朱晖
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昆山国显光电有限公司
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Publication of WO2020062796A1 publication Critical patent/WO2020062796A1/zh
Priority to US16/841,707 priority Critical patent/US20200234650A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present application relates to the field of display, for example, to a pixel circuit and a control method thereof, a display panel, and a display device.
  • Organic light-emitting display panels are more and more applied to the display field because of their advantages such as high contrast, low power consumption, wide viewing angle, and fast response speed.
  • an organic light emitting display panel includes pixel circuits arranged in an array.
  • the pixel circuit includes a light emitting diode D1 and a power source, and a current flowing through the light emitting diode D1 is related to a power source voltage.
  • the display panel since the distance between each light emitting diode and the power source is different, the voltage drop across the line during voltage transmission is also different. Therefore, the actual power voltage obtained by each light emitting diode D1 is different, and the current flowing through the light emitting diode D1 is different.
  • the brightness of the light-emitting diode D1 is also different, resulting in uneven brightness of the display panel.
  • the present application provides a pixel circuit and a control method thereof, a display panel, and a display device.
  • a pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a capacitor, and a light emitting diode;
  • the control terminal of the fourth transistor is used to input a first scanning signal, and the first pole of the fourth transistor is connected to the second pole of the third transistor, the control terminal of the first transistor, and the capacitor.
  • a first electrode plate, a second electrode of the fourth transistor being connected to a second electrode of the seventh transistor, and used to input a first reference voltage Vref1;
  • a control terminal of the seventh transistor is used to input the first scanning signal, and a first pole of the seventh transistor is respectively connected to an anode of the light emitting diode and a second pole of the sixth transistor, and the light emitting diode
  • the cathode is used to input the second power source
  • the control terminal of the sixth transistor is used to input a light-emitting control signal, and the first pole of the sixth transistor is connected to the second pole of the first transistor and the first pole of the third transistor, respectively.
  • a control terminal of the transistor is used to input a second scanning signal;
  • a control terminal of the second transistor is used to input the second scanning signal, a first pole of the second transistor is used to input a data signal, and a second pole of the second transistor is respectively connected to the first transistor.
  • a control terminal of the eighth transistor is used to input a third scanning signal, a first pole of the eighth transistor is used to input a second reference voltage Vref2, and a second pole of the eighth transistor is respectively connected to a first pole of the capacitor.
  • a bipolar plate and a second pole of the ninth transistor, and a control terminal of the ninth transistor is used to input the light emission control signal;
  • a control terminal of the fifth transistor is used to input the light emission control signal, and a first pole of the fifth transistor is used to input a first power source VDD.
  • a voltage value of the first reference voltage Vref1 is smaller than a voltage value of the second power source.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the The eighth transistor and the ninth transistor are all P-type transistors or both are N-type transistors.
  • the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the The ninth transistor is a switching transistor, and the first transistor is a driving transistor.
  • the capacitor is an energy storage capacitor
  • the light emitting diode is an organic light emitting diode
  • the first power source VDD is a positive voltage and the second power source is a negative voltage.
  • control terminal of each transistor is the gate of the transistor, the source of the first pole of each transistor, and the drain of the second pole of each transistor.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the The eighth transistor and the ninth transistor include any one of a low temperature polysilicon thin film transistor, an oxide semiconductor thin film transistor, and an amorphous silicon thin film transistor.
  • a display panel includes a plurality of pixel circuits arranged in an array, wherein the pixel circuits include the aforementioned pixel circuits.
  • the display panel further includes a data driver, a scan driver and a light emitting controller, a plurality of first scan signal lines, a plurality of second scan signal lines, a plurality of third scan signal lines, and a plurality of data.
  • each row of pixel circuits is respectively connected to the scan driver through corresponding first scan signal lines, second scan signal lines, and third scan signal lines; the scan drivers provide scan signals and pass the The scanning signal line transmits the scanning signal to the pixel circuit; each column of pixel circuits is connected to the data driver through a corresponding data signal line; the data driver provides a data signal, and the data signal is transmitted through the data signal line.
  • the data signal is transmitted to the pixel circuit; each row of pixel circuits is connected to the light-emitting controller through a corresponding light-emitting control signal line; the light-emitting controller provides a light-emitting control signal and transmits the light-emitting control signal through the light-emitting control signal line To the pixel circuit.
  • a display device includes the foregoing display panel.
  • the pixel circuit, the display panel, and the display device use the second reference voltage Vref2 to compensate the control terminal of the first transistor through a capacitor, so that the driving current flowing through the first transistor is related to the second reference voltage Vref2 and is related to the first power source.
  • VDD has nothing to do. Because the driving current flows through the power line, the current-resistance voltage drop on the power line has no effect on the driving current when the driving current is not related to the first power source VDD, thereby improving the uniformity of light emission of the screen.
  • a method for driving a pixel circuit as described above comprising:
  • the first scanning signal and the third scanning signal are both low-level signals
  • the second scanning signal and the light emission control signal are both high-level signals
  • the first reference voltage Vref1 and the second reference voltage Vref2 initialize the pixel circuit.
  • the second scan signal and the third scan signal are both low-level signals
  • the first scan signal and the light emission control signal are both high-level signals
  • the data signal is written Into the pixel circuit
  • the light-emitting control signal is a low-level signal
  • the first scanning signal, the second scanning signal, and the third scanning signal are all high-level signals
  • the light-emitting diode emits light.
  • the first scan signal controls the fourth transistor and the seventh transistor to be turned on
  • the first reference voltage Vref1 initializes the first electrode plate of the capacitor and the control terminal of the first transistor through the fourth transistor, and the first reference voltage Vref1 pairs the anode of the light emitting diode through the seventh transistor. Perform initialization.
  • the third scanning signal controls the eighth transistor to be turned on, and the second reference voltage Vref2 initializes the second plate of the capacitor.
  • the second scan signal controls the second transistor to be turned on, and the data signal is written into the first pole of the first transistor through the second transistor, so that The potential of the first pole of the first transistor is Vdata, and the potential of the control terminal of the first transistor is Vdata-
  • the third scan signal controls the eighth transistor to be turned on, and the second reference voltage Vref2 continues to initialize the second plate of the capacitor.
  • the light-emitting control signal controls the fifth transistor and the ninth transistor to be turned on, and a first power source VDD is written into a first pole of the first transistor and a first pole of the capacitor.
  • VDD the potential of the first pole of the first transistor
  • VDD-Vref2 the potential of the control terminal of the first transistor
  • the driving method of the pixel circuit provided in the present application compensates for the current-resistance voltage drop on the first power supply line by increasing the second reference voltage, and at the same time, also compensates for the influence of the threshold voltage on the light-emitting current, which improves the light-emitting effect of the screen. Uniformity.
  • FIG. 1 is a circuit diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 2 is a timing diagram of a pixel circuit driving method according to an embodiment of the present application.
  • an embodiment of the present application provides a pixel circuit including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor.
  • the pixel circuit further includes a first scan signal input terminal, which is connected to the control terminal of the fourth transistor T4 and the control terminal of the seventh transistor T7, respectively, for inputting the first scan signal SCAN1.
  • the second scanning signal input terminal is respectively connected to the control terminals of the second transistor T2 and the third transistor T3, and is used for inputting the second scanning signal SCAN2.
  • the third scanning signal input terminal is connected to the control terminal of the eighth transistor T8 and is used to input the third scanning signal SCAN3.
  • the light-emitting control signal input terminal is respectively connected to the control terminal of the fifth transistor T5, the control terminal of the sixth transistor T6, and the control terminal of the ninth transistor T9, and is used to input the light-emitting control signal EM.
  • the data signal input port is connected to the first pole of the second transistor T2 and is used to input a data signal Vdata.
  • the control terminal of the fourth transistor T4 is used to input the first scan signal SCAN1.
  • the first pole of the fourth transistor T4 is connected to the second pole of the third transistor T3, the control terminal of the first transistor T1, and the first of the capacitor C1. Polar plate.
  • the second pole of the fourth transistor T4 is connected to the second pole of the seventh transistor T7, and the second pole of the fourth transistor T4 and the second pole of the seventh transistor T7 are used to input the first reference voltage Vref1.
  • the control terminal of the seventh transistor T7 is used to input the first scan signal SCAN1.
  • the first pole of the seventh transistor T7 is connected to the anode of the light-emitting diode D1 and the second pole of the sixth transistor T6, and the cathode of the light-emitting diode D1 is connected to the second power source. VSS.
  • the control terminal of the sixth transistor T6 is used to input the light-emitting control signal EM.
  • the first pole of the sixth transistor T6 is connected to the second pole of the first transistor T1 and the first pole of the third transistor T3, and the control terminal of the third transistor T3. Used to input the second scan signal SCAN2.
  • the control terminal of the second transistor T2 is used to input the second scan signal SCAN2, the first pole of the second transistor T2 is used to input the data signal Vdata, and the second pole of the second transistor T2 is connected to the first pole of the first transistor T1, The first pole of the ninth transistor T9 and the second pole of the fifth transistor T5.
  • the control terminal of the eighth transistor T8 is used to input the third scan signal SCAN3, the first pole of the eighth transistor T8 is used to input the second reference voltage Vref2, and the second pole of the eighth transistor T8 is connected to the second plate of the capacitor C1, respectively.
  • the control terminal of the ninth transistor T9 is used to input a light emission control signal EM.
  • the control terminal of the fifth transistor T5 is used to input the light emission control signal EM, and the first pole of the fifth transistor T5 is used to input the first power source VDD.
  • the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are all switching transistors.
  • a transistor T1 is a driving transistor.
  • the capacitor C1 is an energy storage capacitor, and the light emitting diode D1 is an OLED (Organic Light-Emitting Diode).
  • the transistors in this embodiment are all P-type transistors.
  • the control terminal is the gate of the transistor, the source of the first electrode of the transistor, and the drain of the second electrode of the transistor. Applying a low level to the control terminal of the transistor can turn on the transistor.
  • the transistor may be an N-type transistor. When an N-type transistor is used as a transistor in a pixel circuit, a high-level signal is input to the control terminal of the transistor to make it conductive.
  • the first scan signal SCAN1 can control the fourth transistor T4 and the seventh transistor T7 to be turned on, so that the first reference voltage Vref1 initializes the gate of the first transistor T1 and the anode of the light emitting diode D1.
  • the second scan signal SCAN2 can control the second transistor T2 to be turned on, so that the data signal is written into the first pole of the first transistor T1 through the second transistor T2.
  • the third scan signal SCAN3 can control the eighth transistor T8 to be turned on, so that the second reference voltage Vref2 is written into the second plate of the capacitor C1.
  • the first power source VDD may be a positive voltage
  • the second power source VSS may be a negative voltage.
  • Driving the first transistor T1 can generate a current under the action of the first power source VDD, and the current flows through the light emitting diode D1 to cause the light emitting diode D1 to emit light.
  • the light emitting diode D1 emits light
  • a current flows from the light emitting diode D1 to the second power source VSS.
  • the pixel circuit provided in the above embodiment uses the second reference voltage Vref2 to compensate the control terminal of the first transistor T1 through the capacitor C1, so that the driving current flowing through the first transistor T1 is related to the second reference voltage Vref2 and is related to the first
  • the power supply VDD is irrelevant. Because the driving current flows through the power line, the current-resistance voltage drop on the power line has no effect on the driving current when the driving current is not related to the first power source VDD, thereby improving the uniformity of light emission of the screen.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 Any of a low temperature polysilicon thin film transistor, an oxide semiconductor thin film transistor, and an amorphous silicon thin film transistor may be included.
  • An embodiment of the present application provides a display panel including a plurality of the aforementioned pixel circuits arranged in an array.
  • the display panel also includes a data driver, a scan driver, and a light emitting controller.
  • the first scanning signal line, the second scanning signal line, and the third scanning signal line are connected to each row of pixel circuits at one end and connected to a scanning driver at the other end.
  • the scanning driver provides a scanning signal and transmits the scanning signal to the pixels through the scanning signal line.
  • One end of the plurality of data signal lines is connected to each column of pixel circuits, and the other end is connected to a data driver.
  • the data drivers provide data signals and transmit the data signals to the pixel circuits through the data signal lines.
  • One end of the plurality of light-emitting control signal lines is connected to each row of pixel circuits, and the other end is connected to a light-emitting controller.
  • the light-emitting controller provides light-emitting control signals, and transmits the light-emitting control signals to the pixel circuits through the light-emitting control signal lines. More specifically, each row of pixel circuits is connected to the scan driver through corresponding first scan signal lines, second scan signal lines, and third scan signal lines; each column of pixel circuits is connected to the scan driver through corresponding data signal lines.
  • the data driver is connected; each row of pixel circuits is respectively connected to the light-emitting controller through a corresponding light-emitting control signal line.
  • An embodiment of the present application provides a display device including the above display panel.
  • An embodiment of the present application further provides a driving method of the aforementioned pixel circuit.
  • FIG. 1 is a pixel circuit provided by an embodiment of the present application
  • FIG. 2 is a timing signal diagram for driving the pixel circuit shown in FIG. 1.
  • the driving method includes the following three stages:
  • the first scan signal SCAN1 and the third scan signal SCAN3 are both low-level signals
  • the second scan signal SCAN2 and the light emission control signal EM are high-level signals
  • the first reference voltage Vref1 and the second reference voltage Vref2 The pixel circuit is initialized.
  • the second scan signal SCAN2 and the third scan signal SCAN3 are both low-level signals
  • the first scan signal SCAN1 and the light emission control signal EM are both high-level signals
  • the data signals are written into the pixel circuit.
  • the light-emitting control signal EM is a low-level signal
  • the first scan signal SCAN1, the second scan signal SCAN2, and the third scan signal SCAN3 are all high-level signals
  • the light-emitting diode D1 emits light.
  • the first scan signal SCAN1 is a low-level signal, so the first scan signal SCAN1 controls the fourth transistor T4 and the seventh transistor T7 to be turned on, and the first reference voltage Vref1 is applied to the first plate of the capacitor C1.
  • the control terminal of the first transistor T1 and the anode of the light emitting diode D1 are initialized.
  • the third scan signal SCAN3 is a low-level signal, so the third scan signal SCAN3 controls the eighth transistor T8 to be turned on, and the second reference voltage Vref2 initializes the second plate of the capacitor C1.
  • both the first and second plates of the capacitor C1 are initialized during the initialization phase t1, so that the potentials of the first and second plates of the capacitor C1 are maintained at the first reference voltages, respectively.
  • the second scan signal SCAN2 is a low-level signal.
  • the second scan signal SCAN2 controls the second transistor T2 and the third transistor T3 to be turned on.
  • the data signal writes the data voltage Vdata to the first through the second transistor T2.
  • the first pole of the transistor T1 so that the potential of the first pole of the first transistor T1 is Vdata, and after the data voltage charges the first pole of the first transistor T1 for a period of time, the potential of the control terminal of the first transistor T1 remains at Vdata-
  • the third scan signal SCAN3 is also a low-level signal, so the third scan signal SCAN3 can control the eighth transistor T8 to be turned on, so that the second reference voltage Vref2 continues to carry out the second plate of the capacitor C1 before the data writing is completed. Initialization makes the screen body have better uniformity of light emission.
  • the light-emitting control signal EM is a low-level signal. Therefore, the light-emitting control signal EM controls the fifth transistor T5 and the ninth transistor T9 to be turned on. Dentsu C1's second plate. Therefore, the potential of the first electrode of the first transistor T1 is VDD. According to the coupling principle of the capacitor, when the voltage difference is constant, the potential of the second plate of the capacitor C1 changes, and the potential of the first plate also changes accordingly.
  • the potential change of the second plate of the capacitor C1 is VDD-Vref2, so the potential change of the first plate of the capacitor C1 is also VDD-Vref2, so the potential change of the control terminal of the first transistor T1 is VDD-Vref2, so the first The potential of the control terminal of the transistor T1 is Vdata-
  • the leakage current flowing through the first transistor T1 is the light emitting current flowing through the light emitting diode D1, so the light emitting current is not related to the first power source VDD, and the effect of the current-resistance voltage drop on the first power line on the current can be eliminated, and the current can be improved.
  • the uniformity of the light emitted by the screen is the uniformity of the light emitted by the screen.
  • the first scan signal SCAN1 and the third scan signal SCAN3 are both low-level signals, and the second scan signal SCAN2 and the light emission control signal EM are high-level signals.
  • the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned on, and the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are turned off.
  • the fourth transistor T4 is turned on, and the first reference voltage Vref1 initializes the control terminal of the first transistor T1 and the first plate of the capacitor C1.
  • the first reference voltage Vref1 may be a negative voltage, and the first reference voltage Vref1 acts on a control terminal of the first transistor T1 to make the first transistor T1 conductive.
  • the seventh transistor T7 is turned on, and the anode of the light emitting diode D1 is initialized by the first reference voltage Vref1.
  • the eighth transistor T8 is turned on, and the second reference voltage Vref2 initializes the second plate of the capacitor C1, so both the first plate and the second plate of the capacitor C1 are initialized.
  • the potential of the first plate of the capacitor C1 is Vref1
  • the potential of the second plate of the capacitor is Vref2.
  • the voltage value of the first reference voltage Vref1 is smaller than the voltage value of the second power source VSS to ensure that the light-emitting diode D1 does not emit light during initialization.
  • the initialization can eliminate the influence of the residual current of the previous light-emitting stage on the light-emitting stage, ensure that all pixel circuits are in the same initial state, and can improve the uniformity of light emission of the screen.
  • the second scan signal SCAN2 and the third scan signal SCAN3 are both low-level signals, and the first scan signal SCAN1 and the light emission control signal EM are high-level signals.
  • the second transistor T2, the third transistor T3, and the eighth transistor T8 are turned on.
  • the first transistor T1 is turned on.
  • the fourth transistor T4, the seventh transistor T7, the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are turned off.
  • the data signal Since the second transistor T2 is turned on, the data signal writes the data voltage Vdata to the first pole of the first transistor T1 through the second transistor T2. After the circuit state is stable, the potential of the first pole of the first transistor T1 is Vdata. The potential of the control terminal of the transistor T1 is Vdata-
  • the eighth transistor T8 remains on, so the second plate voltage of the capacitor C1 remains at the second reference voltage Vref2.
  • the light-emitting control signal EM is a low-level signal
  • the first scan signal SCAN1, the second scan signal SCAN2, and the third scan signal SCAN3 are high-level signals.
  • the fifth transistor T5, the ninth transistor T9, and the sixth The transistor T6 and the first transistor T1 are turned on, and the fourth transistor T4, the seventh transistor T7, the second transistor T2, the third transistor T3, and the eighth transistor T8 are turned off.
  • the fifth transistor T5 and the ninth transistor T9 are turned on, the power supply voltage of the first power source VDD is written into the first electrode of the first transistor T1 and the second electrode plate of the capacitor C1, so that the potential of the first electrode of the first transistor T1 is Is VDD, and the potential of the second plate of the capacitor C1 is VDD. Since the third transistor T3 and the fourth transistor T4 are turned off, and the capacity of the capacitor C1 is much larger than the parasitic capacitance of other transistors, the voltage difference between the capacitor C1 is unchanged. Since the potential of the second plate of the capacitor C1 is changed from Vref2 in the data writing stage t2 to VDD in the light emitting stage t3, the variation is VDD-Vref2.
  • the potential of the first plate of capacitor C1 when the voltage difference of capacitor C1 remains unchanged, the potential of the first plate of capacitor C1 also changes with the change of the second plate.
  • the potential of the first plate C1 of the capacitor is the first
  • the potential of the control terminal of a transistor T1 is then the potential of the control terminal of the first transistor T1 is Vdata-
  • Vgs of the first transistor T1 Vdata-
  • + VDD-Vref2-VDD Vdata-
  • ) 2 K * (Vdata-Vref2) 2
  • K 1/2 * ⁇ * Cox * W / L.
  • ⁇ is the electron mobility of the first transistor T1
  • Cox is the gate oxide capacitance per unit area of the first transistor T1
  • W is the channel width of the first transistor T1
  • L is the channel length of the first transistor T1.
  • the driving current flowing through the first transistor T1 is the light emitting current flowing through the light emitting diode D1. It can be seen from the above formula that the light-emitting current flowing through the light-emitting diode D1 has nothing to do with the voltage of the first power source VDD, and has no relation to the threshold voltage of the transistor. At the same time, the light-emitting current does not flow through the second reference voltage line.
  • the circuit structure and the driving method provided by the embodiments of the present application compensate for the current-resistance voltage drop on the first power line by adding a second reference voltage.
  • the circuit structure and the driving method of the present application also compensate for the threshold voltage. The effect on the luminous current improves the uniformity of the screen's luminescence.

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Abstract

像素电路及其控制方法、显示面板、显示装置，包括：第一晶体管（T1）、第二晶体管（T2）、第三晶体管（T3）、第四晶体管（T4）、第五晶体管（T5）、第六晶体管（T6）、第七晶体管（T7）、第八晶体管（T8）、第九晶体管（T9）、电容（C1）及发光二极管（D1）。像素电路利用第二参考电压（Vref2）通过电容（C1）对第一晶体管（T1）的控制端进行补偿，以使流过第一晶体管（T1）的驱动电流（I）与第二参考电压（Vref2）有关，而与第一电源（VDD）无关。由于驱动电流（I）流经电源线，在驱动电流（I）与第一电源（VDD）无关的情况下，电源线上的电流-电阻压降对驱动电流（I）无影响，进而可以提高屏体的发光均一性。

Description

像素电路及其控制方法、显示面板、显示装置 技术领域
本申请涉及显示领域，例如是涉及一种像素电路及其控制方法、显示面板、显示装置。
背景技术
有机发光显示面板因其具有对比度高、功耗低、视角广、反应速度快等优点，被越来越多地应用到显示领域。通常，有机发光显示面板中包含阵列排布的像素电路，像素电路包括发光二极管D1和电源，流经发光二极管D1的电流与电源电压有关。显示面板中，由于每个发光二极管与电源的距离不同，电压传输的过程中产生的线上压降也不同，因而每个发光二极管D1实际得到的电源电压不同，流过发光二极管D1的电流不同，发光二极管D1的亮度也不同，导致显示面板的发光亮度不均匀。
发明内容
本申请提供一种像素电路及其控制方法、显示面板、显示装置。
一种像素电路，包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、电容及发光二极管；
所述第四晶体管的控制端用于输入第一扫描信号，所述第四晶体管的第一极分别连接所述第三晶体管的第二极、所述第一晶体管的控制端和所述电容的第一 极板，所述第四晶体管的第二极连接所述第七晶体管的第二极，用于输入第一参考电压Vref1；
所述第七晶体管的控制端用于输入所述第一扫描信号，所述第七晶体管的第一极分别连接所述发光二极管的阳极和所述第六晶体管的第二极，所述发光二极管的阴极用于输入第二电源；
所述第六晶体管的控制端用于输入发光控制信号，所述第六晶体管的第一极分别连接所述第一晶体管的第二极和所述第三晶体管的第一极，所述第三晶体管的控制端用于输入第二扫描信号；
所述第二晶体管的控制端用于输入所述第二扫描信号，所述第二晶体管的第一极用于输入数据信号，所述第二晶体管的第二极分别连接所述第一晶体管的第一极、所述第九晶体管的第一极和所述第五晶体管的第二极；
所述第八晶体管的控制端用于输入第三扫描信号，所述第八晶体管的第一极用于输入第二参考电压Vref2，所述第八晶体管的第二极分别连接所述电容的第二极板和所述第九晶体管的第二极，所述第九晶体管的控制端用于输入所述发光控制信号；并且
所述第五晶体管的控制端用于输入所述发光控制信号，所述第五晶体管的第一极用于输入第一电源VDD。
在其中一个实施例中，所述第一参考电压Vref1的电压值小于所述第二电源的电压值。
在其中一个实施例中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管及所述第九晶体管均为P型晶体管或均为N型晶体管。
在其中一个实施例中，所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管、所述第九晶体管均为开关晶体管，所述第一晶体管为驱动晶体管。
在其中一个实施例中，所述电容为储能电容，所述发光二极管为有机发光二极管。
在其中一个实施例中，所述第一电源VDD是正电压，所述第二电源是负电压。
在其中一个实施例中，每个晶体管的控制端为晶体管的栅极，每个晶体管的第一极为晶体管的源极，每个晶体管的第二极为晶体管的漏极。
在其中一个实施例中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管及所述第九晶体管包括低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管以及非晶硅薄膜晶体管中的任一种。
一种显示面板，包括阵列排布的多个像素电路，其中，所述像素电路包括前述的像素电路。
在其中一个实施例中，所述显示面板还包括数据驱动器、扫描驱动器和发光控制器、多条第一扫描信号线、多条第二扫描信号线、多条第三扫描信号线、多条数据信号线和多条发光控制信号线。
在其中一个实施例中，每行像素电路分别通过对应的第一扫描信号线、第二扫描信号线和第三扫描信号线与所述扫描驱动器连接；所述扫描驱动器提供扫描信号，并通过所述扫描信号线将所述扫描信号传输至所述像素电路；每列像素电路分别通过对应的数据信号线与所述数据驱动器连接；所述数据驱动器提供数据 信号，并通过数据信号线将所述数据信号传输至像素电路；每行像素电路分别通过对应的发光控制信号线与所述发光控制器连接；所述发光控制器提供发光控制信号，并通过所述发光控制信号线将发光控制信号传输至像素电路。
一种显示装置，包括前述显示面板。
上述像素电路、显示面板及显示装置，利用第二参考电压Vref2通过电容对第一晶体管的控制端进行补偿，以使流过第一晶体管的驱动电流与第二参考电压Vref2有关而与第一电源VDD无关。由于驱动电流流经电源线，在驱动电流与第一电源VDD无关的情况下，电源线上的电流-电阻压降对驱动电流无影响，进而可以提高屏体的发光均一性。
一种如前所述的像素电路的驱动方法，包括：
初始化阶段，第一扫描信号及第三扫描信号均为低电平信号，第二扫描信号及发光控制信号均为高电平信号，第一参考电压Vref1和第二参考电压Vref2初始化所述像素电路；
数据写入阶段，所述第二扫描信号及所述第三扫描信号均为低电平信号，所述第一扫描信号及所述发光控制信号均为高电平信号，所述数据信号被写入所述像素电路；以及
发光阶段，所述发光控制信号为低电平信号，所述第一扫描信号、所述第二扫描信号及所述第三扫描信号均为高电平信号，发光二极管发光。
在其中一个实施例中，在所述初始化阶段，所述第一扫描信号控制第四晶体管和第七晶体管打开；并且
所述第一参考电压Vref1通过所述第四晶体管对电容的第一极板和第一晶体管的控制端进行初始化，所述第一参考电压Vref1通过所述第七晶体管对所述发 光二极管的阳极进行初始化。
在其中一个实施例中，所述第三扫描信号控制第八晶体管打开，所述第二参考电压Vref2对所述电容的第二极板进行初始化。
在其中一个实施例中，在所述数据写入阶段，所述第二扫描信号控制第二晶体管打开，所述数据信号通过所述第二晶体管写入所述第一晶体管的第一极，以使所述第一晶体管的第一极的电位为Vdata，所述第一晶体管的控制端的电位为Vdata-|Vth|，其中，Vth为第一晶体管的阈值电压。
在其中一个实施例中，所述第三扫描信号控制所述第八晶体管导通，所述第二参考电压Vref2持续对所述电容的第二极板进行初始化。
在其中一个实施例中，在所述发光阶段，所述发光控制信号控制第五晶体管和第九晶体管打开，第一电源VDD被写入所述第一晶体管的第一极和所述电容的第二极板，所述第一晶体管的第一极的电位为VDD，所述第一晶体管的控制端的电位为Vdata-|Vth|+VDD-Vref2。
本申请提供的像素电路的驱动方法通过增加第二参考电压的方式补偿了第一电源线上的电流-电阻压降，同时，也补偿了阈值电压对发光电流的影响，提高了屏体发光的均一性。
附图说明
图1为本申请的一个实施例提供的像素电路的电路图；
图2为本申请的一个实施例提供的像素电路驱动方法的时序图。
具体实施方式
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细地说明。在下面的描述中阐述了很多具体细节以便于充分理解本申请。但是本申请能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似改进，因此本申请不受下面公开的具体实施例的限制。
请参见图1，本申请的一个实施例提供一种像素电路，包括第一晶体管T1，第二晶体管T2，第三晶体管T3，第四晶体管T4，第五晶体管T5，第六晶体管T6，第七晶体管T7，第八晶体管T8，第九晶体管T9，电容C1及发光二极管D1。
像素电路还包括第一扫描信号输入端，分别连接第四晶体管T4的控制端和第七晶体管T7的控制端，用于输入第一扫描信号SCAN1。第二扫描信号输入端分别连接第二晶体管T2和第三晶体管T3的控制端，用于输入第二扫描信号SCAN2。第三扫描信号输入端连接第八晶体管T8的控制端，用于输入第三扫描信号SCAN3。发光控制信号输入端分别连接第五晶体管T5的控制端、第六晶体管T6的控制端和第九晶体管T9的控制端，用于输入发光控制信号EM。数据信号输入端口连接第二晶体管T2的第一极，用于输入数据信号Vdata。
其中，第四晶体管T4的控制端用于输入第一扫描信号SCAN1，第四晶体管T4的第一极分别连接第三晶体管T3的第二极、第一晶体管T1的控制端和电容C1的第一极板。第四晶体管T4的第二极连接第七晶体管T7的第二极，且第四晶体管T4的第二极和第七晶体管T7的第二极用于输入第一参考电压Vref1。第七晶体管T7的控制端用于输入第一扫描信号SCAN1，第七晶体管T7的第一极分别连接发光二极管D1的阳极和第六晶体管T6的第二极，发光二极管D1的阴极连接第二电源VSS。第六晶体管T6的控制端用于输入发光控制信号EM，第 六晶体管T6的第一极分别连接第一晶体管T1的第二极和第三晶体管T3的第一极，第三晶体管T3的控制端用于输入第二扫描信号SCAN2。第二晶体管T2的控制端用于输入第二扫描信号SCAN2，第二晶体管T2的第一极用于输入数据信号Vdata，第二晶体管T2的第二极分别连接第一晶体管T1的第一极、第九晶体管T9的第一极和第五晶体管T5的第二极。第八晶体管T8的控制端用于输入第三扫描信号SCAN3，第八晶体管T8的第一极用于输入第二参考电压Vref2，第八晶体管T8的第二极分别连接电容C1的第二极板和第九晶体管T9的第二极。第九晶体管T9的控制端用于输入发光控制信号EM。第五晶体管T5的控制端用于输入所述发光控制信号EM，第五晶体管T5的第一极用于输入第一电源VDD。
本实施例中，第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9均为开关晶体管，第一晶体管T1为驱动晶体管。电容C1为储能电容，发光二极管D1为OLED(Organic Light-Emitting Diode,有机发光二极管)。本实施例中的晶体管均采用P型晶体管。在一实施例中，控制端为晶体管的栅极，第一极为晶体管的源极，第二极为晶体管的漏极，对晶体管的控制端施加低电平可以使晶体管导通。在其他实施例中，晶体管也可以是N型晶体管。在采用N型晶体管作为像素电路中的晶体管时，对晶体管的控制端输入高电平信号可以使其导通。
第一扫描信号SCAN1可控制第四晶体管T4和第七晶体管T7导通，以使第一参考电压Vref1对第一晶体管T1的栅极和发光二极管D1的阳极进行初始化。第二扫描信号SCAN2可控制第二晶体管T2导通，以使数据信号通过第二晶体管T2写入第一晶体管T1的第一极。第三扫描信号SCAN3可以控制第八晶体管T8导通，以使第二参考电压Vref2写入电容C1的第二极板。
本实施例中，第一电源VDD可以是正电压，第二电源VSS可以是负电压。驱动第一晶体管T1可以在第一电源VDD的作用下产生电流，该电流流过发光二极管D1以使发光二极管D1发光。发光二极管D1发光时，电流从发光二极管D1流向第二电源VSS。
上述实施例提供的像素电路，利用第二参考电压Vref2通过电容C1对第一晶体管T1的控制端进行补偿，以使流过第一晶体管T1的驱动电流与第二参考电压Vref2有关而与第一电源VDD无关。由于驱动电流流经电源线，在驱动电流与第一电源VDD无关的情况下，电源线上的电流-电阻压降对驱动电流无影响，进而可以提高屏体的发光均一性。
在一个实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9可以包括低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管以及非晶硅薄膜晶体管中的任一种。
本申请的一个实施例提供一种显示面板，包括阵列排布的多个前述像素电路。显示面板还包括数据驱动器、扫描驱动器和发光控制器。多条第一扫描信号线、第二扫描信号线和第三扫描信号线一端分别连接每行像素电路，另一端连接扫描驱动器，扫描驱动器提供扫描信号，并通过扫描信号线将扫描信号传输至像素电路中。多条数据信号线一端连接每列像素电路，另一端连接数据驱动器，数据驱动器提供数据信号，并通过数据信号线将数据信号传输至像素电路。多条发光控制信号线一端连接每行像素电路，另一端连接发光控制器，发光控制器提供发光控制信号，并通过发光控制信号线将发光控制信号传输至像素电路。更具体地，每行像素电路分别通过对应的第一扫描信号线、第二扫描信号线和第三扫描信号 线与所述扫描驱动器连接；每列像素电路分别通过对应的数据信号线与所述数据驱动器连接；每行像素电路分别通过对应的发光控制信号线与所述发光控制器连接。
本申请的一个实施例提供一种显示装置，包括上述显示面板。
本申请的一个实施例还提供一种前述像素电路的驱动方法。
请参见图1与图2，图1为本申请的一个实施例提供的一种像素电路，图2为驱动图1所示的像素电路的时序信号图。所述驱动方法包括以下三个阶段：
初始化阶段t1，第一扫描信号SCAN1和第三扫描信号SCAN3均为低电平信号，第二扫描信号SCAN2和发光控制信号EM均为高电平信号，第一参考电压Vref1和第二参考电压Vref2初始化所述像素电路。
数据写入阶段t2，第二扫描信号SCAN2和第三扫描信号SCAN3均为低电平信号，第一扫描信号SCAN1和发光控制信号EM均为高电平信号,数据信号被写入像素电路。
发光阶段t3，发光控制信号EM为低电平信号，第一扫描信号SCAN1、第二扫描信号SCAN2和第三扫描信号SCAN3均为高电平信号，发光二极管D1发光。
具体的，在初始化阶段t1，第一扫描信号SCAN1为低电平信号，故第一扫描信号SCAN1控制第四晶体管T4和第七晶体管T7打开，第一参考电压Vref1对电容C1的第一极板、第一晶体管T1的控制端和发光二极管D1的阳极进行初始化。第三扫描信号SCAN3为低电平信号，故第三扫描信号SCAN3控制第八晶体管T8打开，第二参考电压Vref2对电容C1的第二极板进行初始化。本实施例中，在初始化阶段t1对电容C1的第一极板和第二极板均进行了初始化，以使电 容C1的第一极板和第二极板的电位分别保持为第一参考电压Vref1和第二参考电压Vref2。由于发光电流经第一电源VDD、第五晶体管T5、第一晶体管T1、第六晶体管T6和发光二极管D1流向第二电源VSS，发光电流不流经提供第一参考电压Vref1的第一参考电压线和提供第二参考电压Vref2的第二参考电压线。因此第一参考电压线和第二参考电压线上不存在电流-电阻压降，故每个像素电路的初始化状态均相同，进而可以更好地保证屏体发光的均一性。
在数据写入阶段t2，第二扫描信号SCAN2为低电平信号，第二扫描信号SCAN2控制第二晶体管T2和第三晶体管T3打开，数据信号通过第二晶体管T2将数据电压Vdata写入第一晶体管T1的第一极，以使第一晶体管T1的第一极电位为Vdata，数据电压对第一晶体管T1的第一极充电一段时间后，第一晶体管T1的控制端电位保持为Vdata-|Vth|，其中，Vth为第一晶体管T1的阈值电压，实现了对第一晶体管T1的阈值电压的补偿。第三扫描信号SCAN3也为低电平信号，故第三扫描信号SCAN3可控制第八晶体管T8导通，以在数据写入结束之前，第二参考电压Vref2持续对电容C1的第二极板进行初始化，使得屏体具有更好的发光均一性。
在发光阶段t3，发光控制信号EM为低电平信号，故发光控制信号EM控制第五晶体管T5和第九晶体管T9打开，第一电源VDD将电源电压写入第一晶体管T1的第一极和电通C1的第二极板。故第一晶体管T1的第一极的电位为VDD。根据电容的耦合原理，在电压差不变的情况下，电容C1的第二极板电位发生变化，第一极板的电位也会随之发生变化。电容C1第二极板的电位变化量为VDD-Vref2，故电容C1第一极板的电位变化量也为VDD-Vref2，因此第一晶体管T1控制端的电位变化量为VDD-Vref2，故第一晶体管T1的控制端的电位为Vdata- |Vth|+VDD-Vref2。根据第一晶体管T1的漏电流公式可知，流过第一晶体管T1的漏电流与第一电源VDD无关。流过第一晶体管T1的漏电流即为流过发光二极管D1的发光电流，故发光电流与第一电源VDD无关，进而可以消除第一电源线上的电流-电阻压降对电流的影响，提高屏体的发光均一性。
基于图1和图2的像素电路的工作原理如下：
在初始化阶段t1，第一扫描信号SCAN1、第三扫描信号SCAN3均为低电平信号，第二扫描信号SCAN2和发光控制信号EM均为高电平信号。第四晶体管T4、第七晶体管T7和第八晶体管T8导通，第二晶体管T2、第三晶体管T3、第五晶体管T5、第六晶体管T6、第九晶体管T9截止。
第四晶体管T4导通，第一参考电压Vref1对第一晶体管T1的控制端和电容C1的第一极板进行初始化。第一参考电压Vref1可以是负电压，第一参考电压Vref1作用于第一晶体管T1的控制端可以使第一晶体管T1导通。第七晶体管T7导通，第一参考电压Vref1对发光二极管D1的阳极进行初始化。第八晶体管T8导通，第二参考电压Vref2对电容C1的第二极板进行初始化，故电容C1的第一极板和第二极板均被初始化。初始化阶段后，电容C1的第一极板的电位为Vref1，电容第二极板的电位为Vref2。
在一实施例中，第一参考电压Vref1的电压值小于第二电源VSS的电压值，以保证在初始化时发光二极管D1不发光。初始化可消除上一发光阶段的残留电流对本发光阶段的影响，保证所有像素电路均处于同一初始状态，可提高屏体的发光均一性。
在数据写入阶段t2，第二扫描信号SCAN2和第三扫描信号SCAN3均为低电平信号，第一扫描信号SCAN1和发光控制信号EM为高电平信号。第二晶体 管T2、第三晶体管T3和第八晶体管T8导通，在初始化阶段，第一晶体管T1已导通。第四晶体管T4、第七晶体管T7、第五晶体管T5、第六晶体管T6、第九晶体管T9截止。
由于第二晶体管T2导通，数据信号通过第二晶体管T2将数据电压Vdata写入第一晶体管T1的第一极，当电路状态稳定后，第一晶体管T1的第一极电位为Vdata，第一晶体管T1的控制端电位为Vdata-|Vth|，实现了对第一晶体管T1的阈值电压的补偿。第八晶体管T8保持导通状态，故电容C1的第二极板电压保持为第二参考电压Vref2。
在发光阶段t3，发光控制信号EM为低电平信号，第一扫描信号SCAN1、第二扫描信号SCAN2、第三扫描信号SCAN3为高电平信号，第五晶体管T5、第九晶体管T9、第六晶体管T6和第一晶体管T1导通，第四晶体管T4、第七晶体管T7、第二晶体管T2、第三晶体管T3、第八晶体管T8截止。
由于第五晶体管T5和第九晶体管T9导通，故第一电源VDD的电源电压写入第一晶体管T1的第一极和电容C1的第二极板，使得第一晶体管T1的第一极电位为VDD，电容C1的第二极板的电位为VDD。由于第三晶体管T3和第四晶体管T4截止，且电容C1的容量远大于其他晶体管的寄生电容，故电容C1的电压差不变。由于电容C1的第二极板电位由数据写入阶段t2的Vref2变为发光阶段t3的VDD，变化量为VDD-Vref2。根据电容耦合原理，在电容C1的电压差保持不变的情况下，电容C1的第一极板的电位也会随第二极板的变化而变化，电容第一极板C1的电位即为第一晶体管T1控制端的电位，则第一晶体管T1的控制端的电位为Vdata-|Vth|+VDD-Vref2。因此第一晶体管T1的Vgs＝Vdata-|Vth|+VDD-Vref2-VDD＝Vdata-|Vth|-Vref2，流过第一晶体管T1的驱动电流为： I＝K*(Vgs-Vth) 2＝K*(Vdata-|Vth|-Vref2+|Vth|) 2＝K*(Vdata-Vref2) 2
其中，K＝1/2*μ*Cox*W/L。μ是第一晶体管T1的电子迁移率，Cox是第一晶体管T1单位面积的栅氧化层电容，W是第一晶体管T1的沟道宽度，L是第一晶体管T1的沟道长度。流过第一晶体管T1的驱动电流即为流过发光二极管D1的发光电流。由上述公式可以看出，流过发光二极管D1的发光电流与第一电源VDD的电压无关，与晶体管的阈值电压也无关，同时，发光电流不流经第二参考电压线。因此本申请的实施例提供的电路结构及其驱动方法通过增加第二参考电压补偿了第一电源线上的电流-电阻压降，同时，本申请的电路结构及其驱动方法也补偿了阈值电压对发光电流的影响，提高了屏体发光的均一性。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。本领域的普通技术人员来说，在不脱离本申请构思的前提下做出的若干变形和改进，都属于本申请的保护范围。本申请专利的保护范围应以所附权利要求为准。

Claims (18)

  1. 一种像素电路，包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、电容及发光二极管；
    所述第四晶体管的控制端用于输入第一扫描信号，所述第四晶体管的第一极分别连接所述第三晶体管的第二极、所述第一晶体管的控制端和所述电容的第一极板，所述第四晶体管的第二极连接所述第七晶体管的第二极，用于输入第一参考电压Vref1；
    所述第七晶体管的控制端用于输入所述第一扫描信号，所述第七晶体管的第一极分别连接所述发光二极管的阳极和所述第六晶体管的第二极，所述发光二极管的阴极用于输入第二电源；
    所述第六晶体管的控制端用于输入发光控制信号，所述第六晶体管的第一极分别连接所述第一晶体管的第二极和所述第三晶体管的第一极，所述第三晶体管的控制端用于输入第二扫描信号；
    所述第二晶体管的控制端用于输入所述第二扫描信号，所述第二晶体管的第一极用于输入数据信号，所述第二晶体管的第二极分别连接所述第一晶体管的第一极、所述第九晶体管的第一极和所述第五晶体管的第二极；
    所述第八晶体管的控制端用于输入第三扫描信号，所述第八晶体管的第一极用于输入第二参考电压Vref2，所述第八晶体管的第二极分别连接所述电容的第二极板和所述第九晶体管的第二极，所述第九晶体管的控制端用于输入所述发光控制信号；并且
    所述第五晶体管的控制端用于输入所述发光控制信号，所述第五晶体管的第 一极用于输入第一电源VDD。
  2. 根据权利要求1所述的像素电路，其中，所述第一参考电压Vref1的电压值小于所述第二电源的电压值。
  3. 根据权利要求1所述的像素电路，其中，所述第一晶体管至所述第九晶体管均为P型晶体管或均为N型晶体管。
  4. 根据权利要求1所述的像素电路，其中，所述第二晶体管至所述第九晶体管均为开关晶体管，所述第一晶体管为驱动晶体管。
  5. 根据权利要求1所述的像素电路，其中，所述电容为储能电容，所述发光二极管为有机发光二极管。
  6. 根据权利要求1所述的像素电路，其中，所述第一电源VDD是正电压，所述第二电源是负电压。
  7. 根据权利要求1所述的像素电路，其中，每个晶体管的控制端为晶体管的栅极，每个晶体管的第一极为晶体管的源极，每个晶体管的第二极为晶体管的漏极。
  8. 根据权利要求1所述的像素电路，其中，所述第一晶体管至所述第九晶体管包括低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管以及非晶硅薄膜晶体管中的任一种。
  9. 一种显示面板，包括阵列排布的多个像素电路，其中，所述像素电路包括如权利要求1-8中任一项所述的像素电路。
  10. 根据权利要求9所述的显示面板，还包括数据驱动器、扫描驱动器和发光控制器、多条第一扫描信号线、多条第二扫描信号线、多条第三扫描信号线、多条数据信号线和多条发光控制信号线。
  11. 根据权利要求10所述的显示面板，其中，
    每行像素电路分别通过对应的第一扫描信号线、第二扫描信号线和第三扫描信号线与所述扫描驱动器连接；所述扫描驱动器提供扫描信号，并通过所述扫描信号线将所述扫描信号传输至所述像素电路；
    每列像素电路分别通过对应的数据信号线与所述数据驱动器连接；所述数据驱动器提供数据信号，并通过数据信号线将所述数据信号传输至像素电路；
    每行像素电路分别通过对应的发光控制信号线与所述发光控制器连接；所述发光控制器提供发光控制信号，并通过所述发光控制信号线将所述发光控制信号传输至像素电路。
  12. 一种显示装置，包括如权利要求9-11中任一项所述的显示面板。
  13. 一种如权利要求1-8中任一项所述的像素电路的驱动方法，包括：
    初始化阶段，第一扫描信号及第三扫描信号均为低电平信号，第二扫描信号及发光控制信号均为高电平信号，第一参考电压Vref1和第二参考电压Vref2初始化所述像素电路；
    数据写入阶段，所述第二扫描信号及所述第三扫描信号均为低电平信号，所述第一扫描信号及所述发光控制信号均为高电平信号，数据信号被写入所述像素电路；和
    发光阶段，所述发光控制信号为低电平信号，所述第一扫描信号、所述第二扫描信号及所述第三扫描信号均为高电平信号，发光二极管发光。
  14. 根据权利要求13所述的像素电路的驱动方法，其中，在所述初始化阶段，所述第一扫描信号控制第四晶体管和第七晶体管打开；并且
    所述第一参考电压Vref1通过所述第四晶体管对电容的第一极板和第一晶体 管的控制端进行初始化，所述第一参考电压Vref1通过所述第七晶体管对所述发光二极管的阳极进行初始化。
  15. 根据权利要求14所述的像素电路的驱动方法，其中，所述第三扫描信号控制第八晶体管打开，所述第二参考电压Vref2对所述电容的第二极板进行初始化。
  16. 根据权利要求15所述的像素电路的驱动方法，其中，在所述数据写入阶段，所述第二扫描信号控制第二晶体管打开，所述数据信号通过所述第二晶体管写入所述第一晶体管的第一极，以使所述第一晶体管的第一极的电位为Vdata，所述第一晶体管的控制端的电位为Vdata-|Vth|，其中，Vth为第一晶体管的阈值电压。
  17. 根据权利要求16所述的像素电路的驱动方法，其中，所述第三扫描信号控制所述第八晶体管导通，所述第二参考电压Vref2持续对所述电容的第二极板进行初始化。
  18. 根据权利要求17所述的像素电路的驱动方法，其中，在所述发光阶段，所述发光控制信号控制第五晶体管和第九晶体管打开，第一电源VDD被写入所述第一晶体管的第一极和所述电容的第二极板，所述第一晶体管的第一极的电位为VDD，所述第一晶体管的控制端的电位为Vdata-|Vth|+VDD-Vref2。
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