WO2023197361A1 - 像素驱动电路及其驱动方法、显示面板 - Google Patents

像素驱动电路及其驱动方法、显示面板 Download PDF

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Publication number
WO2023197361A1
WO2023197361A1 PCT/CN2022/088521 CN2022088521W WO2023197361A1 WO 2023197361 A1 WO2023197361 A1 WO 2023197361A1 CN 2022088521 W CN2022088521 W CN 2022088521W WO 2023197361 A1 WO2023197361 A1 WO 2023197361A1
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WIPO (PCT)
Prior art keywords
transistor
electrically connected
node
drain
gate
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Application number
PCT/CN2022/088521
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English (en)
French (fr)
Inventor
刘斌
Original Assignee
惠州华星光电显示有限公司
Tcl华星光电技术有限公司
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Publication of WO2023197361A1 publication Critical patent/WO2023197361A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present application relates to the field of display technology, and in particular to a pixel driving circuit and a driving method thereof, and a display panel.
  • the transistor that drives the light-emitting device to emit light will have a threshold voltage shift under long-term bias, causing the current to flow.
  • the current passing through the light-emitting device is attenuated; in addition, due to the loss of the signal during the transmission process (such as the voltage drop during the signal transmission process), the current driving the light-emitting devices everywhere in the panel is also different, causing the display panel to display uneven problem.
  • Embodiments of the present application provide a pixel driving circuit, a driving method thereof, and a display panel, which can compensate for current attenuation caused by threshold voltage shifts and voltage drops during signal transmission, and improve the problem of uneven display on the display panel.
  • An embodiment of the present application provides a pixel driving circuit, which includes a first transistor, a second transistor, a fifth transistor, a first capacitor, a second capacitor, and a light-emitting device.
  • the gate electrode of the first transistor is electrically connected to the first node, one of the source electrode or the drain electrode of the first transistor is electrically connected to the second node, and one of the source electrode or the drain electrode of the first transistor is electrically connected to the second node. The other one is electrically connected to the third node.
  • the source and drain of the second transistor are electrically connected between the first node and the third node, the gate of the second transistor is electrically connected to the second scan line, and the second The transistor is used to detect the threshold voltage of the first transistor according to the second scan signal.
  • the first capacitor is connected in series between the first node and the second node; the second capacitor is connected in series between the first node and the first voltage terminal; the light-emitting device is electrically connected to the between the first voltage terminal and the third node.
  • the source and drain of the fifth transistor are electrically connected between the second voltage terminal and the second node, the gate of the fifth transistor is electrically connected to the fourth scan line, and the fifth transistor Used to compensate the second voltage signal according to the fourth scan signal.
  • the pixel driving circuit further includes a third transistor, the source and drain of the third transistor are electrically connected between the data line and the second node, The gate of the third transistor is electrically connected to the first scan line and used to transmit data signals to the second node according to the first scan signal.
  • the pixel driving circuit further includes: a fourth transistor, the source and drain of the fourth transistor are electrically connected to the second capacitor and the first Between the voltage terminals, the gate of the fourth transistor is electrically connected to the first scan line for disconnecting the first voltage terminal and the first scan line when the fifth transistor compensates for the second voltage signal.
  • the electrical connection of the second capacitor is not limited to: a fourth transistor, the source and drain of the fourth transistor are electrically connected to the second capacitor and the first Between the voltage terminals, the gate of the fourth transistor is electrically connected to the first scan line for disconnecting the first voltage terminal and the first scan line when the fifth transistor compensates for the second voltage signal.
  • the pixel driving circuit further includes: a sixth transistor, the source and drain of the sixth transistor are electrically connected to the first voltage terminal and the third voltage terminal. Between one node, the gate of the sixth transistor is electrically connected to the third scan line for initializing the potential of the first node according to the third scan signal.
  • the pixel driving circuit further includes: a seventh transistor, the source and drain of the seventh transistor are electrically connected to the light-emitting device and the third node.
  • the gate of the seventh transistor is electrically connected to the emission line.
  • the pixel driving circuit further includes: an eighth transistor, the source and drain of the eighth transistor are electrically connected to the second voltage terminal and the second node.
  • the gate of the eighth transistor is electrically connected to the emission line.
  • the capacitance of the first capacitor is less than or equal to the capacitance of the second capacitor.
  • the light-emitting device includes an organic light-emitting diode, a sub-millimeter light-emitting diode or a micro light-emitting diode.
  • the third transistor and the fourth transistor are both P-type transistors or both are N-type transistors.
  • Embodiments of the present application also provide a driving method of a pixel driving circuit for driving any of the above-mentioned pixel driving circuits.
  • the driving method includes:
  • Threshold voltage detection and data writing stage the second transistor is turned on in response to the second scan signal, so that the first transistor is connected in a diode manner.
  • Power voltage writing stage the fifth transistor is turned on in response to the fourth scan signal, and the second voltage signal provided by the second voltage terminal is transmitted to the second node.
  • An embodiment of the present application further provides a display panel, which includes any one of the above-mentioned pixel driving circuits and a power supply, and the power supply is electrically connected to the first voltage terminal of the pixel driving circuit.
  • the display panel further includes a gate driver chip, and the gate driver chip is electrically connected to the gate of the second transistor through the second scan line, The fourth scan line is electrically connected to the gate of the fifth transistor.
  • the pixel driving circuit includes a first transistor, a second transistor, a fifth transistor, a first capacitor, a second capacitor, and a pixel driving circuit.
  • Light emitting device a first transistor, a second transistor, a fifth transistor, a first capacitor, a second capacitor, and a pixel driving circuit.
  • the first capacitor is connected in series between the gate of the first transistor and one of the source or the drain
  • the second capacitor is connected in series between the gate of the first transistor and the first voltage terminal
  • the second transistor is electrically connected to the first between the gate of the transistor and the other of the source or the drain
  • the fifth transistor is electrically connected between the second voltage terminal and the one of the source or the drain of the first transistor that is electrically connected to the first capacitor
  • the light-emitting device is connected in series between the first voltage terminal and the other one of the source electrode or the drain electrode of the first transistor.
  • the scanning signal makes the voltage difference between the first node and the second node irrelevant to the second voltage signal to achieve compensation of the second voltage signal, thereby improving the current attenuation problem caused by the voltage drop occurring during signal transmission and improving
  • the display panel has uneven display issues.
  • FIG. 1A to 1B are schematic structural diagrams of a pixel driving circuit provided by embodiments of the present application.
  • FIG. 2A is a timing diagram corresponding to the pixel driving circuit shown in FIG. 1A provided by an embodiment of the present application;
  • FIG. 2B is a timing diagram corresponding to the pixel driving circuit shown in FIG. 1B provided by an embodiment of the present application;
  • Figure 3 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • 4A to 4B are schematic structural diagrams of a pixel driving circuit provided by embodiments of the present application.
  • FIG. 1A to FIG. 1B are schematic structural diagrams of a pixel driving circuit provided by embodiments of the present application.
  • Embodiments of the present application provide a pixel driving circuit, which includes at least one light-emitting device D, a first transistor T1, a second transistor T2, a first capacitor C1 and a second capacitor C2.
  • the light-emitting device D includes at least one of an organic light-emitting diode, a sub-millimeter light-emitting diode or a micro light-emitting diode.
  • the pixel driving circuit may include one light-emitting device D, or may include multiple light-emitting devices D.
  • the pixel driving circuit may include a plurality of the light-emitting devices D, the plurality of the light-emitting devices D may be connected in series, or the plurality of the light-emitting devices D may be connected in parallel.
  • the first transistor T1 and the light-emitting device D are electrically connected between the first voltage terminal VDD and the second voltage terminal VSS.
  • the first transistor T1 is used to generate a driving current Ids that drives the light-emitting device D to emit light. .
  • the light-emitting device D is connected in series between the first voltage terminal VDD and one of the source or drain of the first transistor T1; or, the light-emitting device D is connected in series to the second between the voltage terminal VSS and the other one of the source electrode or the drain electrode of the first transistor T1.
  • the light-emitting device D is connected in series between the first voltage terminal VDD and one of the source or drain of the first transistor T1 for description.
  • the gate of the first transistor T1 is electrically connected to the first node A, and one of the source or drain of the first transistor T1 is electrically connected to the second node B.
  • the first transistor The other one of the source or the drain of T1 is electrically connected to the third node C, the anode of the light-emitting device D is electrically connected to the first voltage terminal VDD, and the cathode of the light-emitting device D is electrically connected to the third node C.
  • the three nodes C are electrically connected.
  • the light-emitting device D is closer to the first voltage terminal VDD, which is conducive to reducing the voltage amplitude corresponding to each transistor in the pixel driving circuit, and is further conducive to reducing power consumption.
  • the first capacitor C1 is connected in series between the first node A and the second node B.
  • the second capacitor C2 is connected in series between the first node A and the first voltage terminal VDD.
  • the capacitance of the first capacitor C1 is less than or equal to the capacitance of the second capacitor C2, so that the second capacitor C2 can better stabilize the gate potential of the first transistor T1. pressure effect.
  • the source and drain of the second transistor T2 are electrically connected between the first node A and the third node C, and the gate of the second transistor T2 is electrically connected to the second scan line SL2 , the second transistor T2 is used to detect the threshold voltage of the first transistor T1 according to the second scan signal Scan2 transmitted by the second scan line SL2.
  • one of the source or drain of the second transistor T2 is electrically connected to the gate of the first transistor T1
  • the other of the source or drain of the second transistor T2 is electrically connected to the gate of the first transistor T1.
  • One of the source electrode or the drain electrode of the first transistor T1 is electrically connected to the light-emitting device D.
  • the second transistor T2 makes the first transistor T1 diode-connected according to the second scan signal Scan2 transmitted by the second scan line SL2, thereby storing the threshold voltage of the first transistor T1 to the first transistor T1.
  • the capacitor C1 stores the data signal Data in the second capacitor C2 to compensate for the impact of the threshold voltage on the driving current Ids when the first transistor T1 drives the light-emitting device D to emit light, thereby improving the
  • the threshold voltage shift of the first transistor T1 causes the problem of attenuation of the driving current Ids flowing through the light-emitting device D.
  • the pixel driving circuit also includes a third transistor T3.
  • the source and drain of the third transistor T3 are electrically connected between the data line DL and the second node B.
  • the gate of the third transistor T3 is electrically connected to the first scan line SL1.
  • the third transistor T3 is used to transmit the first scan signal Scan1 transmitted by the first scan line SL1 to the second node B.
  • the data signal Data Specifically, one of the source or drain of the third transistor T3 is electrically connected to the data line DL, and the other of the source or drain of the third transistor T3 is electrically connected to the first transistor.
  • One of the source electrode or the drain electrode of T1 is electrically connected to the second voltage terminal VSS.
  • the third transistor T3 transmits the data signal Data transmitted by the data line DL to the second node B according to the first scan signal Scan1 transmitted by the first scan line SL1.
  • the pixel driving circuit also includes a fourth transistor T4.
  • the source and drain of the fourth transistor T4 are electrically connected to the second capacitor C2 and the first voltage terminal. Between VDD, the gate of the fourth transistor T4 is electrically connected to the first scan line SL1. Specifically, one of the source or drain of the fourth transistor T4 is electrically connected to the second capacitor C2, and the other of the source or drain of the fourth transistor T4 is electrically connected to the first capacitor C2.
  • the voltage terminal VDD is electrically connected.
  • the fourth transistor T4 is electrically connected to the first voltage terminal VDD and the second capacitor C2 according to the first scan signal Scan1 transmitted by the first scan line SL1.
  • the pixel The driving circuit also includes a fifth transistor T5.
  • the source and drain of the fifth transistor T5 are electrically connected between the second voltage terminal VSS and the second node B.
  • the gate of the fifth transistor T5 The fifth transistor T5 is electrically connected to the fourth scan line SL4, and the fifth transistor T5 is used to compensate the second voltage signal according to the fourth scan signal Scan4 transmitted by the fourth scan line SL4. Specifically, please continue to refer to FIGS. 1A to 1B .
  • One of the source or drain of the fifth transistor T5 is electrically connected to the second voltage terminal VSS.
  • the source or drain of the fifth transistor T5 is electrically connected to the second voltage terminal VSS.
  • the other of the electrodes is electrically connected to one of the source electrode or the drain electrode of the first transistor T1 and the first capacitor C1.
  • the fifth transistor T5 transmits according to the fourth scan line SL4.
  • the fourth scan signal Scan4 transmits the second voltage signal provided by the second voltage terminal VSS to the second node B, so that the potential at the first node A changes due to capacitive coupling, thereby causing the third
  • the voltage difference between a node A and the second node B is not related to the second voltage signal, thereby realizing compensation for the second voltage signal, and then realizing compensation for the impact of the voltage drop on the driving current Ids.
  • the fourth transistor T4 may also be used to disconnect the electrical connection between the first voltage terminal VDD and the second capacitor C2 when the fifth transistor T5 compensates the second voltage signal. That is, the fourth transistor T4 is turned off when the fifth transistor T5 compensates for the second voltage signal, so that the second voltage signal provided by the second voltage terminal VSS can directly pass through the fifth transistor T5 be compensated, reducing the complexity of the pixel driving circuit.
  • the pixel driving circuit further includes a sixth transistor T6 .
  • the source and drain of the sixth transistor T6 are electrically connected between the first voltage terminal VDD and the first node A, and the gate of the sixth transistor T6 is electrically connected to the third scan line SL3. connect.
  • one of the source or drain of the sixth transistor T6 is electrically connected to the first voltage terminal VDD, and the other of the source or drain of the sixth transistor T6 is electrically connected to the first voltage terminal VDD.
  • the gate of a transistor T1 is electrically connected, and the sixth transistor T6 is used to transmit the first voltage signal provided by the first voltage terminal VDD to the third scan signal Scan3 transmitted by the third scan line SL3.
  • the first node A is used to initialize the gate voltage of the first transistor T1 through the sixth transistor T6 and the first voltage signal.
  • the pixel driving circuit also includes a seventh transistor T7.
  • the source and drain of the seventh transistor T7 are electrically connected between the light-emitting device D and the third node C.
  • the gate of the seventh transistor T7 is electrically connected to the emission line EML.
  • one of the source or drain of the seventh transistor T7 is electrically connected to the cathode of the light-emitting device D, and the other of the source or drain of the seventh transistor T7 is connected to the cathode of the light-emitting device D.
  • One of the source or drain of a transistor T1 is electrically connected.
  • the seventh transistor T7 switches between the on state and the off state according to the emission control signal EM transmitted by the emission line EML.
  • the seventh transistor T7 Turning on causes the first transistor T1 to generate a driving current Ids that drives the light-emitting device D to emit light under the action of the first voltage terminal VDD, the second voltage terminal VSS, and the data signal Data.
  • the pixel circuit further includes an eighth transistor T8.
  • the source and drain of the eighth transistor T8 are electrically connected to the second voltage terminal VSS and the second node. B, the gate of the eighth transistor T8 is electrically connected to the emission line EML.
  • one of the source or drain of the eighth transistor T8 is electrically connected to the other of the source or drain of the first transistor T1
  • the source or drain of the eighth transistor T8 is electrically connected to the source or drain of the first transistor T1.
  • the other one of the poles is electrically connected to the second voltage terminal VSS, and the eighth transistor T8 and the seventh transistor T7 are used to achieve on-state and off-state according to the emission control signal EM transmitted by the emission line EML.
  • the seventh transistor T7 and the eighth transistor T8 are turned on so that the first transistor T1 acts on the first voltage terminal VDD, the second voltage terminal VSS, and the data signal Data.
  • a driving current is generated to drive the light-emitting device D to emit light.
  • the first transistor T1 to the eighth transistor T8 may include at least one of a P-type transistor or an N-type transistor; the active layer of the first transistor T1 to the eighth transistor T8 may be Includes at least one of a silicon semiconductor layer or an oxide semiconductor layer.
  • the silicon semiconductor layer includes single crystal silicon, polycrystalline silicon, amorphous silicon and other materials
  • the oxide semiconductor layer includes zinc oxide, zinc tin oxide, zinc indium oxide, indium oxide, titanium oxide, indium gallium zinc oxide , at least one of indium zinc tin oxide and other materials.
  • FIG. 2A is a timing diagram corresponding to the pixel driving circuit shown in FIG. 1A provided by an embodiment of the present application
  • FIG. 2B is a timing diagram corresponding to the pixel driving circuit shown in FIG. 1B provided by an embodiment of the present application.
  • the first transistor T1 to the eighth transistor T8 as N-type transistors as an example, the driving method of the pixel driving circuit will be described.
  • the driving method of the pixel driving circuit includes an initialization phase t1, a threshold voltage detection and data writing phase t2, a transition phase t3, a power supply voltage writing phase t4 and a light emitting phase t5.
  • Initialization stage t1 the emission control signal EM transmitted by the emission line EML is low level, the data signal Data transmitted by the data line DL is Data_L, and the first scanning signal transmitted by the first scanning line SL1 Scan1 is high level, the second scan signal Scan2 transmitted by the second scan line SL2 is low level, the third scan signal Scan3 transmitted by the third scan line SL3 is high level, and the The fourth scan signal Scan4 transmitted by the fourth scan line SL4 is low level.
  • the second transistor T2 is turned off in response to the second scan signal Scan2
  • the fifth transistor T5 is turned off in response to the fourth scan signal Scan4, and the seventh transistor T7 (as shown in FIG. 1A and FIG.
  • the seventh transistor T7 and the eighth transistor T8 are turned off in response to the emission control signal EM.
  • the third transistor T3 and the fourth transistor T4 are turned on in response to the first scan signal Scan1, and the sixth transistor T6 is turned on in response to the third scan signal Scan3.
  • the third transistor T3 and the fourth transistor T4 are turned on so that the data signal Data_L is transmitted to the second node B, and the potential at the second node B becomes Data_L; the sixth transistor T6
  • the conduction causes the first voltage signal provided by the first voltage terminal VDD to be transmitted to the first node A, and the potential at the first node A becomes the voltage value Vdd corresponding to the first voltage signal; that is, The first voltage signal provided by the first voltage terminal VDD is used to initialize the gate potential of the first transistor T1 through the sixth transistor T6.
  • the voltage difference across the first capacitor C1 is Vdd-Data_L; since the sixth transistor T6 is turned on, the two ends of the second capacitor C2 are short-circuited, and the voltage difference across the second capacitor C2 is zero.
  • Threshold voltage detection and data writing stage t2 The emission control signal EM transmitted by the emission line EML is low level, the data signal Data transmitted by the data line DL is Data_H, and the first scan line SL1 transmits The first scan signal Scan1 is high level, the second scan signal Scan2 transmitted by the second scan line SL2 is high level, and the third scan signal Scan3 transmitted by the third scan line SL3 is low level, and the fourth scanning signal Scan4 transmitted by the fourth scanning line SL4 is low level.
  • the fifth transistor T5 is turned off in response to the fourth scan signal Scan4, the sixth transistor T6 is turned off in response to the third scan signal Scan3, the seventh transistor T7 (as shown in FIG. 1A and FIG.
  • the seventh transistor T7 and the eighth transistor T8 are turned off in response to the emission control signal EM.
  • the second transistor T2 is turned on in response to the second scan signal Scan2, and the third transistor T3 and the fourth transistor T4 are turned on in response to the first scan signal Scan1.
  • the third transistor T3 and the fourth transistor T4 are turned on so that the data signal Data_H is transmitted to the second node B, and the potential Data_L at the second node B changes from Data_H to Data_H; the second The transistor T2 is turned on so that the first transistor T1 is connected in a diode manner, and the potential at the first node A changes from Vdd to Data_H+Vth, that is, the gate potential of the first transistor T1 changes from Vdd to Data_H+ Vth.
  • the voltage difference across the second capacitor C2 is Vdd-Data_H-Vth; that is, the threshold voltage of the first transistor T1 is stored in In the first capacitor C1, the data signal Data_H is stored in the second capacitor C2.
  • Vth represents the threshold voltage of the first transistor T1.
  • Transition stage t3 the emission control signal EM transmitted by the emission line EML is low level, the data signal Data transmitted by the data line DL is Data_L, and the first scanning signal transmitted by the first scanning line SL1 Scan1 is high level, the second scan signal Scan2 transmitted by the second scan line SL2 is low level, the third scan signal Scan3 transmitted by the third scan line SL3 is low level, the The fourth scan signal Scan4 transmitted by the fourth scan line SL4 is low level.
  • the second transistor T2 is turned off in response to the second scan signal Scan2
  • the fifth transistor T5 is turned off in response to the fourth scan signal Scan4
  • the sixth transistor T6 is turned off in response to the third scan signal Scan3.
  • the seventh transistor T7 (shown in FIGS.
  • the seventh transistor T7 and the eighth transistor T8 (shown in FIGS. 1B and 2B ) is turned off in response to the emission control signal EM.
  • the third transistor T3 and the fourth transistor T4 are turned on in response to the first scan signal Scan1, and the third transistor T3 and the fourth transistor T4 are turned on so that the data signal Data_L is transmitted to the Second node B, the potential at the second node B changes from Data_H to Data_L. Due to the existence of the first capacitor C1, the potential at the first node A changes from Data_H+Vth to Data_H due to capacitive coupling.
  • V0 (Data_H-Data_L)*C1/(C1+C2).
  • Power supply voltage writing stage t4 the emission control signal EM transmitted by the emission line EML is low level, the data signal Data transmitted by the data line DL is Data_L, and the first scanning line SL1 transmits the A scan signal Scan1 is low level, the second scan signal Scan2 transmitted by the second scan line SL2 is low level, and the third scan signal Scan3 transmitted by the third scan line SL3 is low level.
  • the fourth scan signal Scan4 transmitted by the fourth scan line SL4 is high level.
  • the second transistor T2 is turned off in response to the second scan signal Scan2
  • the third transistor T3 and the fourth transistor T4 are turned off in response to the first scan signal Scan1
  • the sixth transistor T6 is turned off in response to the third scan signal Scan1.
  • the scan signal Scan3 is turned off, and the seventh transistor T7 (shown in FIGS. 1A and 2A) or the seventh transistor T7 and the eighth transistor T8 (shown in FIGS. 1B and 2B) responds to the emission control.
  • Signal EM is cut off.
  • the fifth transistor T5 is turned on in response to the fourth scan signal Scan4, the second voltage signal provided by the second voltage terminal VSS is transmitted to the second node B, and the potential at the second node B is Data_L becomes the voltage value Vss corresponding to the second voltage signal.
  • the potential at the first node A changes from Data_H+Vth+V0 to Data_H+Vth+V0+Vss-Data_L due to capacitive coupling; that is, the gate of the first transistor T1
  • the pole potential changes from Data_H+Vth+V0 to Data_H+Vth+V0+Vss-Data_L.
  • the voltage difference between the first node A and the second node B has no correlation with the second voltage signal.
  • Light-emitting stage t5 the emission control signal EM transmitted by the emission line EML is high level, the data signal Data transmitted by the data line DL is Data_L, and the first scanning signal transmitted by the first scanning line SL1 Scan1 is low level, the second scan signal Scan2 transmitted by the second scan line SL2 is low level, the third scan signal Scan3 transmitted by the third scan line SL3 is low level, the The second transistor T2 turns off in response to the second scan signal Scan2, the third transistor T3 and the fourth transistor T4 turn off in response to the first scan signal Scan1, and the sixth transistor T6 responds to the third scan signal. Scan3 ends. When the fourth scan signal Scan4 transmitted by the fourth scan line SL4 is high level (as shown in FIG.
  • the fifth transistor T5 is turned on in response to the fourth scan signal Scan4, so The seventh transistor T7 is turned on in response to the emission control signal EM, and the first transistor T1 generates the driving current Ids for driving the light-emitting device D to emit light.
  • the fourth scan signal Scan4 transmitted by the fourth scan line SL4 is low level (as shown in FIG. 1B and FIG. 2B )
  • the fifth transistor T5 is turned off in response to the fourth scan signal Scan4.
  • the seventh transistor T7 and the eighth transistor T8 are turned on in response to the emission control signal EM, and the first transistor T1 generates the driving current Ids for driving the light-emitting device D to emit light.
  • the pixel driving circuit shown in FIG. 1A uses fewer transistors, which is beneficial to saving layout space and manufacturing costs.
  • An embodiment of the present application also provides a display panel, which includes any of the above-mentioned pixel driving circuits.
  • FIG. 3 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • An embodiment of the present application also provides a display panel, where the display panel includes a driving circuit.
  • the display panel includes a passive luminous display panel and a self-luminous display panel;
  • the driving circuit includes a backlight driving circuit and a pixel driving circuit.
  • the driving circuit is a pixel driving circuit as an example for description.
  • the display panel includes a display area 100a and a non-display area 100b.
  • the display panel implements a display function in the display area 100a.
  • the non-display area 100b is located at the periphery of the display area 100a.
  • the display panel may further include a sensing area, and the sensing area may be located in the display area 100a or the non-display area 100b.
  • the display panel includes sensing elements arranged corresponding to the sensing area.
  • the sensing element includes a camera, a fingerprint sensor, a distance sensor, etc.
  • the display panel includes a plurality of scanning lines SL, a plurality of data lines DL, a plurality of emission lines EML and a plurality of the pixel driving circuits.
  • the plurality of data lines DL transmit a plurality of data signals.
  • a plurality of the data lines DL are arranged along the first direction x and extend along the second direction y in the display area 100a. Wherein, the first direction x and the second direction y intersect.
  • the plurality of scan lines SL transmit a plurality of scan signals.
  • a plurality of the scan lines SL are arranged along the second direction y and extend along the first direction x in the display area 100a.
  • a plurality of the emission lines EML transmit a plurality of emission control signals.
  • a plurality of the emission lines EML are arranged along the second direction y and extend along the first direction x in the display area 100a.
  • a plurality of the pixel driving circuits are electrically connected to a plurality of the scanning lines SL, a plurality of the data lines DL and a plurality of the emission lines EML, for controlling the corresponding scanning signals and data signals. and the emission control signal causes the display panel to display.
  • a plurality of the pixel driving circuits are located in the display area 100a.
  • the display panel further includes a driving module electrically connected to the pixel driving circuit.
  • the driving module includes a power supply electrically connected to the first voltage terminal VDD of the pixel driving circuit.
  • the driving module further includes a gate driving chip and a source driving chip.
  • the gate driving chip is electrically connected to a plurality of the scanning lines SL to provide scanning signals for a plurality of the scanning lines SL.
  • the source driver chip is electrically connected to the plurality of data lines DL, so as to transmit data signals to the plurality of data lines DL.
  • the driving module further includes an emission control chip, and the emission control chip is electrically connected to the plurality of emission lines EML, so as to provide emission control signals for the plurality of emission lines EML.
  • each pixel driving circuit at least includes a first transistor T1 and a light-emitting device D.
  • the first transistor T1 is used to generate a driving current for driving the light-emitting device D to emit light according to the data signal, so that the light-emitting device D emits light.
  • the light-emitting device D is connected in series between the first voltage terminal VDD and one of the source or drain of the first transistor T1; or, the light-emitting device D is connected in series to the second between the voltage terminal VSS and the other one of the source electrode or the drain electrode of the first transistor T1.
  • the light-emitting device D is connected in series between the first voltage terminal VDD and one of the source or drain of the first transistor T1, so that the The light-emitting device D is closer to the first voltage terminal VDD, which is beneficial to reducing the voltage amplitude corresponding to each transistor in the pixel driving circuit.
  • the light-emitting device D includes an organic light-emitting diode, a sub-millimeter light-emitting diode, a micro light-emitting diode, etc.
  • the light-emitting layer of the light-emitting device may include perovskite materials, fluorescent materials, quantum dot materials, etc.
  • the pixel driving circuit further includes a second transistor T2 , a first capacitor C1 and a second capacitor C2 .
  • the first capacitor C1 is connected in series between the gate of the first transistor T1 and one of the source or drain of the first transistor T1 that is electrically connected to the second voltage terminal VSS;
  • Two capacitors C2 are connected in series between the gate of the first transistor T1 and the first voltage terminal VDD.
  • the source and drain of the second transistor T2 are electrically connected to the gate of the first transistor T1 and the source or drain of the first transistor T1 and are electrically connected to the light-emitting device D. Between one of the two electrical connections, the gate of the second transistor T2 is electrically connected to the corresponding scan line SL. Specifically, the gate of the second transistor T2 is electrically connected to the second scan line SL2, and one of the source or drain of the second transistor T2 is electrically connected to the gate of the first transistor T1. , the other one of the source electrode or the drain electrode of the second transistor T2 is electrically connected to the one of the source electrode or the drain electrode of the first transistor T1 that is electrically connected to the light-emitting device D.
  • the second transistor T2 is used to store the threshold voltage of the first transistor T1 to the first capacitor C1 according to the second scan signal transmitted by the second scan line SL2, and to store the data signal to the second capacitor C1.
  • the capacitor C2 is used to compensate the influence of the threshold voltage on the driving current when the first transistor T1 drives the light-emitting device D to emit light, thereby improving the flow through the first transistor T1 due to the threshold voltage shift of the first transistor T1.
  • the driving current of the light-emitting device D is attenuated, thereby improving the display effect of the display panel.
  • the pixel driving circuit further includes a third transistor T3.
  • the gate of the third transistor T3 is electrically connected to the corresponding scan line SL.
  • the gate of the third transistor T3 The source electrode and the drain electrode are electrically connected between the corresponding data line DL and one of the source electrode or the drain electrode of the first transistor T1 that is electrically connected to the first capacitor C1.
  • the gate of the third transistor T3 is electrically connected to the first scan line SL1.
  • One of the source or drain of the third transistor T3 is electrically connected to the corresponding data line DL, and the other of the source or drain of the third transistor is connected to the first transistor T1
  • One of the source electrode or the drain electrode is electrically connected to the first capacitor C1.
  • the third transistor T3 is used to transmit the data signal Data transmitted by the data line DL to the source or drain of the first transistor T1 according to the first scan signal transmitted by the first scan line SL1 One electrically connected to the first capacitor C1.
  • the pixel driving circuit further includes a fourth transistor T4, the gate of the fourth transistor T4 is corresponding to The scan line SL is electrically connected, and the source and drain of the fourth transistor T4 are electrically connected between the second capacitor C2 and the first voltage terminal VDD.
  • the gates of the third transistor T3 and the fourth transistor T4 are electrically connected to the same scan line SL, and both the third transistor T3 and the fourth transistor T4 are P-type transistors or Both are N-type transistors, so that when the third transistor T3 is turned on, the fourth transistor T4 is also turned on, ensuring effective writing of the data signal and effective detection of the threshold voltage of the first transistor T1.
  • the gate of the fourth transistor T4 is electrically connected to the first scan line SL1, and one of the source or drain of the fourth transistor T4 is electrically connected to the second capacitor C2. The other one of the source electrode or the drain electrode of the fourth transistor T4 is electrically connected to the first voltage terminal VDD.
  • the pixel driving circuit also includes a fifth transistor T5.
  • the gate of the fifth transistor T5 is electrically connected to the corresponding scan line SL.
  • the source and drain of the fifth transistor T5 are electrically connected to the scan line SL. between the second voltage terminal VSS and one of the source or the drain of the first transistor T1 that is electrically connected to the first capacitor C1.
  • the gate electrode of the fifth transistor T5 is electrically connected to the fourth scan line SL4, and one of the source electrode or the drain electrode of the fifth transistor T5 is electrically connected to the second voltage terminal VSS, so The other one of the source or the drain of the fifth transistor T5 is electrically connected to the one of the source or the drain of the first transistor T1 that is electrically connected to the first capacitor C1.
  • the fifth transistor T5 is used to transmit the second voltage signal provided by the second voltage terminal VSS to the source or drain of the first transistor T1 according to the fourth scan signal transmitted by the fourth scan line SL4 and neutralize the second voltage signal provided by the second voltage terminal VSS.
  • a capacitor C1 is electrically connected to one of the capacitors to compensate the influence of the voltage drop on the driving current through the second voltage signal.
  • the pixel driving circuit also includes a sixth transistor T6, the gate of the sixth transistor T6 is connected to the corresponding The scan line SL is electrically connected, and the source and drain of the sixth transistor T6 are electrically connected between the first voltage terminal VDD and the gate of the first transistor T1.
  • the gate electrode of the sixth transistor T6 is electrically connected to the third scan line SL3, and one of the source electrode or the drain electrode of the sixth transistor T6 is electrically connected to the first voltage terminal VDD, so The other one of the source or the drain of the sixth transistor T6 is electrically connected to the gate of the first transistor T1.
  • the sixth transistor T6 is used for the third scan transmitted according to the third scan line SL3.
  • the signal transmits the first voltage signal provided by the first voltage terminal VDD to the gate of the first transistor T1 to initialize the gate voltage of the first transistor T1 through the first voltage signal.
  • the pixel driving circuit also includes a seventh transistor T7.
  • the gate of the seventh transistor T7 is electrically connected to the corresponding emission line EML.
  • the seventh transistor T7 The source electrode and the drain electrode of T7 are electrically connected between the light emitting device D and one of the source electrode or the drain electrode of the first transistor T1. Specifically, one of the source or drain of the seventh transistor T7 is electrically connected to the cathode of the light-emitting device D, and the other of the source or drain of the seventh transistor T7 is connected to the cathode of the light-emitting device D.
  • One of the source or drain of a transistor T1 is electrically connected, and the seventh transistor T7 is used to cause the first transistor T1 to generate and drive the light-emitting device D to emit light according to the emission control signal transmitted by the emission line EML. of driving current.
  • the fifth transistor T5 can be turned on when the seventh transistor T7 responds to the emission control signal, so that the first transistor T1 switches between the first voltage terminal VDD and the second voltage.
  • a driving current is generated between the terminals VSS to drive the light-emitting device D to emit light.
  • the pixel driving circuit further includes an eighth transistor T8.
  • the gate of the eighth transistor T8 is electrically connected to the emission line EML.
  • the source and drain of the eighth transistor are electrically connected to between the second voltage terminal VSS and the other one of the source electrode or the drain electrode of the first transistor T1.
  • one of the source or drain of the eighth transistor T8 is electrically connected to the other of the source or drain of the first transistor T1
  • the source or drain of the eighth transistor T8 is electrically connected to the source or drain of the first transistor T1.
  • the other one of the two terminals is electrically connected to the second voltage terminal VSS.
  • the eighth transistor T8 and the seventh transistor T7 are used to enable the first transistor T1 according to the emission control signal transmitted by the emission line EML.
  • a driving current for driving the light-emitting device D to emit light is generated between the first voltage terminal VDD and the second voltage terminal VSS.
  • the driving method of the pixel driving circuit includes: an initialization stage, a threshold voltage detection and data writing stage, a transition stage, a power supply voltage writing stage and a light emitting stage.
  • the emission control signal transmitted by the emission line EML is low level
  • the data signal Data transmitted by the data line DL is Data_L
  • the first scan transmitted by the first scan line SL1 The signal is at a high level
  • the second scanning signal transmitted by the second scanning line SL2 is at a low level
  • the third scanning signal transmitted by the third scanning line SL3 is at a high level
  • the fourth scanning signal is at a high level.
  • the fourth scan signal transmitted by scan line SL4 is low level.
  • the second transistor T2, the fifth transistor T5, the seventh transistor T7 (as shown in FIG. 4A) or the seventh transistor T7 and the eighth transistor T8 (as shown in FIG. 4B) are turned off.
  • the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are turned on.
  • the data signal Data_L is transmitted to one of the source or drain of the first transistor T1 that is electrically connected to the first capacitor C1, and the first voltage signal provided by the first voltage terminal VDD is transmitted to The gate of the first transistor T1 realizes the initialization of the gate potential of the first transistor T1.
  • the data signal Data transmitted by the data line DL is Data_H
  • the first scan signal and the second scan signal are high level
  • the third The scanning signal, the fourth scanning signal and the emission control signal are low level.
  • the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 (as shown in FIG. 4A) or the seventh transistor T7 and the eighth transistor T8 (as shown in FIG. 4B) are turned off.
  • the second transistor T2, the third transistor T3 and the fourth transistor T4 are turned on.
  • the data signal Data_H is transmitted to one of the source or drain of the first transistor T1 that is electrically connected to the first capacitor C1; the second transistor T2 is turned on so that the first transistor T1 is in the state of Diode connection, the gate potential of the first transistor T1 changes from Vdd to Data_H+Vth, the threshold voltage of the first transistor T1 is stored in the first capacitor C1, and the data signal Data_H is stored in in the second capacitor C2.
  • Vth represents the threshold voltage of the first transistor T1.
  • the data signal Data transmitted by the data line DL is Data_L
  • the first scan signal is high level
  • the second scan signal is high level
  • the second scan signal is high level
  • the second scan signal is high level
  • the third scan signal the fourth scan signal
  • the scanning signal and the emission control signal are low level.
  • the second transistor, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 (as shown in Figure 4A) or the seventh transistor T7 and the eighth transistor T8 (as shown in Figure 4A shown in 4B) ends.
  • the third transistor T3 and the fourth transistor T4 are turned on, and the data signal Data_L is transmitted to one of the source electrode or the drain electrode of the first transistor T1 that is electrically connected to the first capacitor C1.
  • the data signal Data transmitted by the data line DL is Data_L
  • the first scanning signal, the second scanning signal, the third scanning signal and the emission control signal is low level
  • the fourth scanning signal is high level.
  • the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7 (as shown in FIG. 4A) or the seventh transistor T7 and the The eighth transistor T8 (shown in FIG. 4B) is turned off.
  • the fifth transistor T5 is turned on, and the second voltage signal provided by the second voltage terminal VSS is transmitted to the source or drain of the first transistor T1 which is electrically connected to the first capacitor C1 , the gate potential of the first transistor T1 changes from Data_H+Vth+V0 to Data_H+Vth+V0+Vss-Data_L due to capacitive coupling.
  • the data signal Data transmitted by the data line DL is Data_L
  • the emission control signal is high level
  • the signal is low level
  • the second transistor T2, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are turned off.
  • the fourth scan signal is high level (as shown in FIG. 4A)
  • the fifth transistor T5 is turned on
  • the seventh transistor T7 is turned on in response to the emission control signal
  • the first transistor T1 generates
  • the driving current drives the light-emitting device D to emit light.
  • the fourth scan signal is low level (as shown in FIG. 4B)
  • the fifth transistor T5 is turned off, the seventh transistor T7 and the eighth transistor T8 are turned on, and the first transistor T1 generates
  • the driving current drives the light-emitting device D to emit light.
  • This application also provides a display device, which includes any one of the above-mentioned driving circuits or any one of the above-mentioned display panels.
  • the display device includes a movable display device (such as a laptop computer, a mobile phone, etc.), a fixed terminal (such as a desktop computer, a television, etc.), a measuring device (such as a sports bracelet, a thermometer, etc.), etc.
  • a movable display device such as a laptop computer, a mobile phone, etc.
  • a fixed terminal such as a desktop computer, a television, etc.
  • a measuring device such as a sports bracelet, a thermometer, etc.

Abstract

一种像素驱动电路及其驱动方法、显示面板，通过使第二晶体管（T2）根据第二扫描信号（Scan2）将第一晶体管（T1）的阈值电压存储至第一电容（C1），以补偿阈值电压对驱动电流的影响；通过使第五晶体管（T5）根据第四扫描信号（Scan4）使第一节点（A）和第二节点（B）之间的电压差与第二电压信号不相关，改善因信号传输过程中出现的电压降引起的电流衰减问题。

Description

像素驱动电路及其驱动方法、显示面板 技术领域
本申请涉及显示技术领域，特别涉及一种像素驱动电路及其驱动方法、一种显示面板。
 背景技术
采用有源矩阵驱动方式配合行扫描技术实现显示面板的显示虽然可以改善瞬态大电流问题，但由于驱动发光器件发光的晶体管在长时间的偏置作用下会出现阈值电压的偏移，使得流经发光器件的电流出现衰减；加之由于信号在传输过程中会存在损耗（如信号传输过程中存在电压降），使得面板内驱动各处的发光器件发光的电流也存在差异，致使显示面板出现显示不均的问题。
 技术问题
本申请实施例提供一种像素驱动电路及其驱动方法、显示面板，可以补偿因阈值电压偏移及信号传输过程中出现的电压降引起的电流衰减，改善显示面板出现显示不均的问题。
 技术解决方案
本申请实施例提供一种像素驱动电路，所述像素驱动电路包括第一晶体管、第二晶体管、第五晶体管、第一电容、第二电容以及发光器件。
所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极或漏极中的一个电性连接于第二节点，所述第一晶体管的源极或漏极中的另一个电性连接于第三节点。
所述第二晶体管的源极和漏极电性连接于所述第一节点和所述第三节点之间，所述第二晶体管的栅极电性连接于第二扫描线，所述第二晶体管用于根据第二扫描信号侦测所述第一晶体管的阈值电压。
所述第一电容串联于所述第一节点和所述第二节点之间；所述第二电容串联于所述第一节点和第一电压端之间；所述发光器件电性连接于所述第一电压端和所述第三节点之间。
所述第五晶体管的源极和漏极电性连接于第二电压端和所述第二节点之间，所述第五晶体管的栅极电性连接于第四扫描线，所述第五晶体管用于根据第四扫描信号补偿第二电压信号。
可选地，在本申请的一些实施例中，所述像素驱动电路还包括第三晶体管，所述第三晶体管的源极和漏极电性连接于数据线和所述第二节点之间，所述第三晶体管的栅极电性连接于第一扫描线，用于根据第一扫描信号向所述第二节点传输数据信号。
可选地，在本申请的一些实施例中，所述像素驱动电路还包括：第四晶体管，所述第四晶体管的源极和漏极电性连接于所述第二电容和所述第一电压端之间，所述第四晶体管的栅极电性连接于所述第一扫描线，用于在所述第五晶体管补偿所述第二电压信号时断开所述第一电压端和所述第二电容的电性连接。
可选地，在本申请的一些实施例中，所述像素驱动电路还包括：第六晶体管，所述第六晶体管的源极和漏极电性连接于所述第一电压端和所述第一节点之间，所述第六晶体管的栅极电性连接于所述第三扫描线，用于根据第三扫描信号初始化所述第一节点的电位。
可选地，在本申请的一些实施例中，所述像素驱动电路还包括：第七晶体管，所述第七晶体管的源极和漏极电性连接于所述发光器件和所述第三节点之间，所述第七晶体管的栅极电性连接于发射线。
可选地，在本申请的一些实施例中，所述像素驱动电路还包括：第八晶体管，所述第八晶体管的源极和漏极电性连接于第二电压端和所述第二节点之间，所述第八晶体管的栅极电性连接于所述发射线。
可选地，在本申请的一些实施例中，所述第一电容的电容量小于或等于所述第二电容的电容量。
可选地，在本申请的一些实施例中，所述发光器件包括有机发光二极管、次毫米发光二极管或微型发光二极管。
可选地，在本申请的一些实施例中，所述第三晶体管和所述第四晶体管均为P型晶体管或均为N型晶体管。
本申请的实施例还提供一种像素驱动电路的驱动方法，用于驱动任一上述的像素驱动电路，所述驱动方法包括：
阈值电压侦测及数据写入阶段：所述第二晶体管响应所述第二扫描信号导通，使得所述第一晶体管呈二极管式连接。
电源电压写入阶段：所述第五晶体管响应所述第四扫描信号导通，所述第二电压端提供的所述第二电压信号被传输至所述第二节点。
本申请的实施例还提供一种显示面板，所述显示面板包括任一上述的像素驱动电路和电源，所述电源与所述像素驱动电路的所述第一电压端电性连接。
可选地，在本申请的一些实施例中，所述显示面板还包括栅极驱动芯片，所述栅极驱动芯片通过所述第二扫描线与所述第二晶体管的栅极电性连接，通过所述第四扫描线与所述第五晶体管的栅极电性连接。
 有益效果
相较于现有技术，本申请的实施例提供一种像素驱动电路及其驱动方法、显示面板，像素驱动电路包括第一晶体管、第二晶体管、第五晶体管、第一电容、第二电容以及发光器件。第一电容串联于第一晶体管的栅极和源极或漏极中的一个之间，第二电容串联于第一晶体管的栅极和第一电压端之间，第二晶体管电性连接第一晶体管的栅极和源极或漏极中的另一个之间，第五晶体管电性连接于第二电压端和第一晶体管的源极或漏极中与第一电容电性连接的一个之间，发光器件串联于第一电压端和第一晶体管的源极或漏极中的另一个之间。通过使第二晶体管根据第二扫描信号将第一晶体管的阈值电压存储至第一电容，以在第一晶体管驱动发光器件发光时补偿阈值电压对驱动电流的影响，通过使第五晶体管根据第四扫描信号使第一节点和第二节点之间的电压差与第二电压信号不相关，以实现第二电压信号的补偿，从而改善因信号传输过程中出现的电压降引起的电流衰减问题，改善显示面板出现显示不均的问题。
 附图说明
图1A~图1B是本申请实施例提供的像素驱动电路的结构示意图；
图2A是本申请实施例提供的对应图1A所示的像素驱动电路的时序图；
图2B是本申请实施例提供的对应图1B所示的像素驱动电路的时序图；
图3是本申请实施例提供的显示面板的结构示意图；
图4A~图4B是本申请实施例提供的像素驱动电路的结构示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
具体地，如图1A~图1B是本申请实施例提供的像素驱动电路的结构示意图。本申请的实施例提供一种像素驱动电路，所述像素驱动电路包括至少一发光器件D、第一晶体管T1、第二晶体管T2、第一电容C1及第二电容C2。
可选地，所述发光器件D包括有机发光二极管、次毫米发光二极管或微型发光二极管中的至少一种。
可选地，所述像素驱动电路可包括一所述发光器件D，也可包括多个所述发光器件D。可选地，在所述像素驱动电路包括多个所述发光器件D时，多个所述发光器件D可以串联，多个所述发光器件D也可以并联。
所述第一晶体管T1与所述发光器件D电性连接于第一电压端VDD和第二电压端VSS之间，所述第一晶体管T1用于产生驱动所述发光器件D发光的驱动电流Ids。
可选地，所述发光器件D串联于所述第一电压端VDD和所述第一晶体管T1的源极或漏极中的一个之间；或，所述发光器件D串联于所述第二电压端VSS和所述第一晶体管T1的源极或漏极中的另一个之间。在本申请中，以所述发光器件D串联于所述第一电压端VDD和所述第一晶体管T1的源极或漏极中的一个之间为例进行说明。
具体地，所述第一晶体管T1的栅极电性连接于第一节点A，所述第一晶体管T1的源极或漏极中的一个电性连接于第二节点B，所述第一晶体管T1的源极或漏极中的另一个电性连接于第三节点C，所述发光器件D的阳极与所述第一电压端VDD电性连接，所述发光器件D的阴极与所述第三节点C电性连接。所述发光器件D更靠近所述第一电压端VDD，有利于像素驱动电路中各晶体管对应的电压幅值的降低，更利于降低功耗。
所述第一电容C1串联于所述第一节点A和所述第二节点B之间。
所述第二电容C2串联于所述第一节点A和所述第一电压端VDD之间。
可选地，所述第一电容C1的电容量小于或等于所述第二电容C2的电容量，以使所述第二电容C2对所述第一晶体管T1的栅极电位实现更好的稳压效果。
所述第二晶体管T2的源极和漏极电性连接于所述第一节点A和所述第三节点C之间，所述第二晶体管T2的栅极与第二扫描线SL2电性连接，所述第二晶体管T2用于根据所述第二扫描线SL2传输的第二扫描信号Scan2侦测所述第一晶体管T1的阈值电压。具体地，所述第二晶体管T2的源极或漏极中的一个与所述第一晶体管T1的栅极电性连接，所述第二晶体管T2的源极或漏极中的另一个与所述第一晶体管T1的源极或漏极中与所述发光器件D电性连接的一个电性连接。所述第二晶体管T2根据所述第二扫描线SL2传输的第二扫描信号Scan2使得所述第一晶体管T1呈二极管式连接，从而将所述第一晶体管T1的阈值电压存储至所述第一电容C1，将数据信号Data存储至所述第二电容C2，以在所述第一晶体管T1驱动所述发光器件D发光时，补偿阈值电压对所述驱动电流Ids的影响，从而改善因所述第一晶体管T1的阈值电压偏移导致流经所述发光器件D的所述驱动电流Ids衰减的问题。
请继续参阅图1A~图1B，所述像素驱动电路还包括第三晶体管T3，所述第三晶体管T3的源极和漏极电性连接于数据线DL和所述第二节点B之间，所述第三晶体管T3的栅极与第一扫描线SL1电性连接，所述第三晶体管T3用于根据所述第一扫描线SL1传输的第一扫描信号Scan1向所述第二节点B传输所述数据信号Data。具体地，所述第三晶体管T3的源极或漏极中的一个与所述数据线DL电性连接，所述第三晶体管T3的源极或漏极中的另一个与所述第一晶体管T1的源极或漏极中和所述第二电压端VSS电性连接的一个电性连接。所述第三晶体管T3根据所述第一扫描线SL1传输的第一扫描信号Scan1将所述数据线DL传输的所述数据信号Data传输至所述第二节点B。
请继续参阅图1A~图1B，所述像素驱动电路还包括第四晶体管T4，所述第四晶体管T4的源极和漏极电性连接于所述第二电容C2和所述第一电压端VDD之间，所述第四晶体管T4的栅极与所述第一扫描线SL1电性连接。具体地，所述第四晶体管T4的源极或漏极中的一个与所述第二电容C2电性连接，所述第四晶体管T4的源极或漏极中的另一个与所述第一电压端VDD电性连接。所述第四晶体管T4根据所述第一扫描线SL1传输的第一扫描信号Scan1电性连接所述第一电压端VDD和所述第二电容C2。
由于信号在传输过程中会存在不同程度的损耗（如信号传输过程中存在电压降），影响所述驱动电流Ids，因此，为补偿因电压降导致的所述驱动电流Ids的衰减，所述像素驱动电路还包括第五晶体管T5，所述第五晶体管T5的源极和漏极电性连接于所述第二电压端VSS和所述第二节点B之间，所述第五晶体管T5的栅极与第四扫描线SL4电性连接，所述第五晶体管T5用于根据所述第四扫描线SL4传输的第四扫描信号Scan4补偿第二电压信号。具体地，请继续参阅图1A~图1B，所述第五晶体管T5的源极或漏极中的一个与所述第二电压端VSS电性连接，所述第五晶体管T5的源极或漏极中的另一个与所述第一晶体管T1的源极或漏极中和所述第一电容C1电性连接的一个电性连接，所述第五晶体管T5根据所述第四扫描线SL4传输的第四扫描信号Scan4将所述第二电压端VSS提供的第二电压信号传输至所述第二节点B，使得所述第一节点A处的电位因电容耦合作用变化，从而使所述第一节点A和所述第二节点B之间的电压差与所述第二电压信号不相关，实现对所述第二电压信号的补偿，继而实现补偿电压降对所述驱动电流Ids的影响。
可选地，所述第四晶体管T4还可用于在所述第五晶体管T5补偿所述第二电压信号时断开所述第一电压端VDD和所述第二电容C2的电性连接。即所述第四晶体管T4在所述第五晶体管T5补偿所述第二电压信号时截止，以使所述第二电压端VSS提供的所述第二电压信号可直接经所述第五晶体管T5被补偿，降低所述像素驱动电路的复杂度。
请继续参阅图1A~图1B，所述像素驱动电路还包括第六晶体管T6。所述第六晶体管T6的源极和漏极电性连接于所述第一电压端VDD和所述第一节点A之间，所述第六晶体管T6的栅极与第三扫描线SL3电性连接。具体地，所述第六晶体管T6的源极或漏极中的一个与所述第一电压端VDD电性连接，所述第六晶体管T6的源极或漏极中的另一个与所述第一晶体管T1的栅极电性连接，所述第六晶体管T6用于根据所述第三扫描线SL3传输的第三扫描信号Scan3将所述第一电压端VDD提供的第一电压信号传输至所述第一节点A，以通过所述第六晶体管T6及所述第一电压信号对所述第一晶体管T1的栅极电压进行初始化。
请继续参阅图1A~图1B，所述像素驱动电路还包括第七晶体管T7，所述第七晶体管T7的源极和漏极电性连接于所述发光器件D和所述第三节点C之间，所述第七晶体管T7的栅极与发射线EML电性连接。具体地，所述第七晶体管T7的源极或漏极中的一个与所述发光器件D的阴极电性连接，所述第七晶体管T7的源极或漏极中的另一个与所述第一晶体管T1的源极或漏极中的一个电性连接，所述第七晶体管T7根据所述发射线EML传输的发射控制信号EM实现导通状态与截止状态的切换，所述第七晶体管T7导通使得所述第一晶体管T1在所述第一电压端VDD、所述第二电压端VSS、所述数据信号Data的作用下产生驱动所述发光器件D发光的驱动电流Ids。
可选地，请继续参阅图1B，所述像素电路还包括第八晶体管T8，所述第八晶体管T8的源极和漏极电性连接于所述第二电压端VSS和所述第二节点B之间，所述第八晶体管T8的栅极与所述发射线EML电性连接。具体地，所述第八晶体管T8的源极或漏极中的一个与所述第一晶体管T1的源极或漏极中的另一个电性连接，所述第八晶体管T8的源极或漏极中的另一个与所述第二电压端VSS电性连接，所述第八晶体管T8和所述第七晶体管T7用于根据所述发射线EML传输的发射控制信号EM实现导通状态与截止状态的切换，所述第七晶体管T7和所述第八晶体管T8导通使得所述第一晶体管T1在所述第一电压端VDD、所述第二电压端VSS、所述数据信号Data的作用下产生驱动所述发光器件D发光的驱动电流。
可以理解的，所述第一晶体管T1~所述第八晶体管T8可包括P型晶体管或N型晶体管中的至少一种；所述第一晶体管T1~所述第八晶体管T8的有源层可包括硅半导体层或氧化物半导体层中的至少一种。可选地，所述硅半导体层包括单晶硅、多晶硅、非晶硅等材料，所述氧化物半导体层包括氧化锌、氧化锌锡、氧化锌铟、氧化铟、氧化钛、氧化铟镓锌、氧化铟锌锡等材料中的至少一种。
本申请还提供一种像素驱动电路的驱动方法，用于驱动任一上述的像素驱动电路。具体地，如图2A是本申请实施例提供的对应图1A所示的像素驱动电路的时序图，图2B是本申请实施例提供的对应图1B所示的像素驱动电路的时序图。以所述第一晶体管T1~所述第八晶体管T8均为N型晶体管为例，对所述像素驱动电路的驱动方法进行说明。
所述像素驱动电路的驱动方法包括初始化阶段t1、阈值电压侦测及数据写入阶段t2、过渡阶段t3、电源电压写入阶段t4及发光阶段t5。
初始化阶段t1：所述发射线EML传输的发射控制信号EM为低电平，所述数据线DL传输的所述数据信号Data为Data_L，所述第一扫描线SL1传输的所述第一扫描信号Scan1为高电平，所述第二扫描线SL2传输的所述第二扫描信号Scan2为低电平，所述第三扫描线SL3传输的所述第三扫描信号Scan3为高电平，所述第四扫描线SL4传输的所述第四扫描信号Scan4为低电平。所述第二晶体管T2响应所述第二扫描信号Scan2截止，所述第五晶体管T5响应所述第四扫描信号Scan4截止，所述第七晶体管T7(如图1A和图2A所示)或所述第七晶体管T7和所述第八晶体管T8(如图1B和图2B所示)响应所述发射控制信号EM截止。所述第三晶体管T3和所述第四晶体管T4响应所述第一扫描信号Scan1导通，所述第六晶体管T6响应所述第三扫描信号Scan3导通。所述第三晶体管T3和所述第四晶体管T4导通使得所述数据信号Data_L被传输至所述第二节点B，所述第二节点B处的电位变为Data_L；所述第六晶体管T6导通使得所述第一电压端VDD提供的第一电压信号被传输至所述第一节点A，所述第一节点A处的电位变为所述第一电压信号对应的电压值Vdd；即利用所述第一电压端VDD提供的第一电压信号经所述第六晶体管T6对所述第一晶体管T1的栅极电位进行初始化。所述第一电容C1两端的电压差为Vdd-Data_L；由于所述第六晶体管T6导通，所述第二电容C2两端被短接，所述第二电容C2两端的电压差为零。
阈值电压侦测及数据写入阶段t2：所述发射线EML传输的发射控制信号EM为低电平，所述数据线DL传输的所述数据信号Data为Data_H，所述第一扫描线SL1传输的所述第一扫描信号Scan1为高电平，所述第二扫描线SL2传输的所述第二扫描信号Scan2为高电平，所述第三扫描线SL3传输的所述第三扫描信号Scan3为低电平，所述第四扫描线SL4传输的所述第四扫描信号Scan4为低电平。所述第五晶体管T5响应所述第四扫描信号Scan4截止，所述第六晶体管T6响应所述第三扫描信号Scan3截止，所述第七晶体管T7(如图1A和图2A所示)或所述第七晶体管T7和所述第八晶体管T8(如图1B和图2B所示)响应所述发射控制信号EM截止。所述第二晶体管T2响应所述第二扫描信号Scan2导通，所述第三晶体管T3和所述第四晶体管T4响应所述第一扫描信号Scan1导通。所述第三晶体管T3和所述第四晶体管T4导通使得所述数据信号Data_H被传输至所述第二节点B，所述第二节点B处的电位Data_L由变为Data_H；所述第二晶体管T2导通使得所述第一晶体管T1呈二极管式连接，所述第一节点A处的电位由Vdd变为Data_H+Vth，即所述第一晶体管T1的栅极电位由Vdd变为Data_H+Vth。所述第一电容C1两端的电压差为Data_H-Data_H+Vth=Vth，所述第二电容C2两端的电压差为Vdd-Data_H-Vth；即所述第一晶体管T1的阈值电压被存储至所述第一电容C1中，所述数据信号Data_H被存储至所述第二电容C2中。其中，Vth表示所述第一晶体管T1的阈值电压。
过渡阶段t3：所述发射线EML传输的发射控制信号EM为低电平，所述数据线DL传输的所述数据信号Data为Data_L，所述第一扫描线SL1传输的所述第一扫描信号Scan1为高电平，所述第二扫描线SL2传输的所述第二扫描信号Scan2为低电平，所述第三扫描线SL3传输的所述第三扫描信号Scan3为低电平，所述第四扫描线SL4传输的所述第四扫描信号Scan4为低电平。所述第二晶体管T2响应所述第二扫描信号Scan2截止，所述第五晶体管T5响应所述第四扫描信号Scan4截止，所述第六晶体管T6响应所述第三扫描信号Scan3截止，所述第七晶体管T7(如图1A和图2A所示)或所述第七晶体管T7和所述第八晶体管T8(如图1B和图2B所示)响应所述发射控制信号EM截止。所述第三晶体管T3和所述第四晶体管T4响应所述第一扫描信号Scan1导通，所述第三晶体管T3和所述第四晶体管T4导通使得所述数据信号Data_L被传输至所述第二节点B，所述第二节点B处的电位由Data_H变为Data_L，由于所述第一电容C1的存在，所述第一节点A处的电位因电容耦合作用由Data_H+Vth变为Data_H+Vth+V0；即所述第一晶体管T1的栅极电位由Data_H+Vth变为Data_H+Vth+V0。所述第一电容C1两端的电压差为Data_H+Vth+V0-Data_L，所述第二电容C2两端的电压差为Vdd- Data_H-Vth-V0。其中，V0=（Data_H-Data_L）*C1/(C1+C2)。
电源电压写入阶段t4：所述发射线EML传输的发射控制信号EM为低电平，所述数据线DL传输的所述数据信号Data为Data_L，所述第一扫描线SL1传输的所述第一扫描信号Scan1为低电平，所述第二扫描线SL2传输的所述第二扫描信号Scan2为低电平，所述第三扫描线SL3传输的所述第三扫描信号Scan3为低电平，所述第四扫描线SL4传输的所述第四扫描信号Scan4为高电平。所述第二晶体管T2响应所述第二扫描信号Scan2截止，所述第三晶体管T3和所述第四晶体管T4响应所述第一扫描信号Scan1截止，所述第六晶体管T6响应所述第三扫描信号Scan3截止，所述第七晶体管T7(如图1A和图2A所示)或所述第七晶体管T7和所述第八晶体管T8(如图1B和图2B所示)响应所述发射控制信号EM截止。所述第五晶体管T5响应所述第四扫描信号Scan4导通，所述第二电压端VSS提供的第二电压信号被传输至所述第二节点B，所述第二节点B处的电位由Data_L变为所述第二电压信号对应的电压值Vss。由于所述第一电容C1的存在，所述第一节点A处的电位因电容耦合作用由Data_H+Vth+V0变为Data_H+Vth+V0+Vss-Data_L；即所述第一晶体管T1的栅极电位由Data_H+Vth+V0变为Data_H+Vth+V0+Vss-Data_L，所述第一电容C1两端的电压差为Data_H+Vth+V0+Vss-Data_L-Vss=Data_H+Vth+V0-Data_L，所述第一节点A和所述第二节点B之间的电压差与所述第二电压信号不相关。
发光阶段t5：所述发射线EML传输的发射控制信号EM为高电平，所述数据线DL传输的所述数据信号Data为Data_L，所述第一扫描线SL1传输的所述第一扫描信号Scan1为低电平，所述第二扫描线SL2传输的所述第二扫描信号Scan2为低电平，所述第三扫描线SL3传输的所述第三扫描信号Scan3为低电平，所述第二晶体管T2响应所述第二扫描信号Scan2截止，所述第三晶体管T3和所述第四晶体管T4响应所述第一扫描信号Scan1截止，所述第六晶体管T6响应所述第三扫描信号Scan3截止。在所述第四扫描线SL4传输的所述第四扫描信号Scan4为高电平时（如图1A和图2A所示），所述第五晶体管T5响应所述第四扫描信号Scan4导通，所述第七晶体管T7响应所述发射控制信号EM导通，所述第一晶体管T1产生驱动所述发光器件D发光的所述驱动电流Ids。在所述第四扫描线SL4传输的所述第四扫描信号Scan4为低电平时（如图1B和图2B所示），所述第五晶体管T5响应所述第四扫描信号Scan4截止，所述第七晶体管T7和所述第八晶体管T8响应所述发射控制信号EM导通，所述第一晶体管T1产生驱动所述发光器件D发光的所述驱动电流Ids。
由于Vgs=Data_H+Vth+V0+Vss-Data_L-Vss=Data_H+Vth+V0-Data_L，所述驱动电流Ids=(C oxμ mW/L)*(Vgs-Vth) 2/2；其中，C ox、μ m、W、L分别为晶体管的单位面积沟道电容、沟道迁移率、沟道宽和沟道长；则所述驱动电流Ids=(C oxμ mW/L)*(Vgs-Vth) 2/2=(C oxμ mW/L)*(Data_H+V0-Data_L) 2/2。因此，所述驱动电流Ids不受所述第一晶体管T1的阈值电压及所述第二电压端VSS传输的第二电压信号的变化影响，保证所述发光器件D发光的稳定性。
相较于图1B所示的像素驱动电路，图1A所示的像素驱动电路采用的晶体管的数量更少，有利于节省布局空间及制造成本。
本申请的实施例还提供一种显示面板，所述显示面板包括任一上述的像素驱动电路。
如图3是本申请实施例提供的显示面板的结构示意图，本申请的实施例还提供一种显示面板，所述显示面板包括驱动电路。可选地，所述显示面板包括被动式发光显示面板和自发光显示面板；所述驱动电路包括背光驱动电路和像素驱动电路。在本申请中，以所述驱动电路为像素驱动电路为例进行说明。
所述显示面板包括显示区100a和非显示区100b。所述显示面板在所述显示区100a实现显示功能。可选地，所述非显示区100b位于所述显示区100a外围。可选地，所述显示面板还可包括感测区，所述感测区可位于所述显示区100a内，也可位于所述非显示区100b内。所述显示面板包括对应所述感测区设置的感测元件。可选地，所述感测元件包括摄像头、指纹传感器、距离传感器等。
所述显示面板包括多条扫描线SL、多条数据线DL、多条发射线EML及多个所述像素驱动电路。
多条所述数据线DL传输多个数据信号。可选地，多条所述数据线DL在所述显示区100a内沿第一方向x排列且沿第二方向y延伸。其中，所述第一方向x和所述第二方向y相交。
多条所述扫描线SL传输多个扫描信号。可选地，多条所述扫描线SL在所述显示区100a内沿所述第二方向y排列且沿所述第一方向x延伸。
多条所述发射线EML传输多个发射控制信号。可选地，多条所述发射线EML在所述显示区100a内沿所述第二方向y排列且沿所述第一方向x延伸。
多个所述像素驱动电路与多条所述扫描线SL、多条所述数据线DL及多条所述发射线EML电性连接，以用于根据对应的所述扫描信号、所述数据信号及所述发射控制信号使所述显示面板实现显示。可选地，多个所述像素驱动电路位于所述显示区100a内。
所述显示面板还包括驱动模块，所述驱动模块与所述像素驱动电路电性连接。可选地，所述驱动模块包括与所述像素驱动电路的所述第一电压端VDD电性连接的电源。可选地，所述驱动模块还包括栅极驱动芯片和源极驱动芯片，所述栅极驱动芯片与多条所述扫描线SL电性连接，以便为多条所述扫描线SL提供扫描信号；所述源极驱动芯片与多条所述数据线DL电性连接，以便为多条所述数据线DL传输数据信号。可选地，所述驱动模块还包括发射控制芯片，所述发射控制芯片与多条所述发射线EML电性连接，以便为多条所述发射线EML提供发射控制信号。
如图4A~图4B是本申请实施例提供的像素驱动电路的结构示意图，为实现所述显示面板的显示功能，每一所述像素驱动电路至少包括第一晶体管T1和发光器件D。所述第一晶体管T1用于根据所述数据信号产生驱动所述发光器件D发光的驱动电流，以使所述发光器件D发光。
可选地，所述发光器件D串联于所述第一电压端VDD和所述第一晶体管T1的源极或漏极中的一个之间；或，所述发光器件D串联于所述第二电压端VSS和所述第一晶体管T1的源极或漏极中的另一个之间。
可选地，为降低所述显示面板的功耗，所述发光器件D串联于所述第一电压端VDD和所述第一晶体管T1的源极或漏极中的一个之间，使所述发光器件D更靠近所述第一电压端VDD，有利于像素驱动电路中各晶体管对应的电压幅值的降低。
可选地，所述发光器件D包括有机发光二极管、次毫米发光二极管、微型发光二极管等。可选地，所述发光器件的发光层可包括钙钛矿材料、荧光材料或量子点材料等。
请继续参阅图4A~图4B，所述像素驱动电路还包括第二晶体管T2、第一电容C1及第二电容C2。
所述第一电容C1串联于所述第一晶体管T1的所述栅极和所述第一晶体管T1的源极或漏极中与第二电压端VSS电性连接的一个之间；所述第二电容C2串联于所述第一晶体管T1的所述栅极和所述第一电压端VDD之间。
所述第二晶体管T2的源极和漏极电性连接于所述第一晶体管T1的栅极和所述第一晶体管T1的所述源极或所述漏极中与所述发光器件D电性连接的一个之间，所述第二晶体管T2的栅极与对应的所述扫描线SL电性连接。具体地，所述第二晶体管T2的栅极与第二扫描线SL2电性连接，所述第二晶体管T2的源极或漏极中的一个与所述第一晶体管T1的栅极电性连接，所述第二晶体管T2的源极或漏极中的另一个与所述第一晶体管T1的源极或漏极中与所述发光器件D电性连接的一个电性连接。所述第二晶体管T2用于根据所述第二扫描线SL2传输的第二扫描信号将所述第一晶体管T1的阈值电压存储至所述第一电容C1，将数据信号存储至所述第二电容C2，以在所述第一晶体管T1驱动所述发光器件D发光时，补偿阈值电压对所述驱动电流的影响，从而改善因所述第一晶体管T1的阈值电压偏移导致流经所述发光器件D的驱动电流衰减，改善所述显示面板的显示效果。
为实现所述数据信号的写入，所述像素驱动电路还包括第三晶体管T3，所述第三晶体管T3的栅极与对应的所述扫描线SL电性连接，所述第三晶体管T3的源极和漏极电性连接于对应的所述数据线DL和所述第一晶体管T1的源极或漏极中与所述第一电容C1电性连接的一个之间。具体地，所述第三晶体管T3的栅极与第一扫描线SL1电性连接。所述第三晶体管T3的源极或漏极中的一个与对应的所述数据线DL电性连接，所述第三晶体管的源极或漏极中的另一个与所述第一晶体管T1的源极或漏极中和所述第一电容C1电性连接的一个电性连接。所述第三晶体管T3用于根据所述第一扫描线SL1传输的第一扫描信号将所述数据线DL传输的所述数据信号Data传输至所述第一晶体管T1的源极或漏极中和所述第一电容C1电性连接的一个。
可选地，为实现所述第二电容C2与所述第一电压端VDD电性连接的可控，所述像素驱动电路还包括第四晶体管T4，所述第四晶体管T4的栅极与对应的所述扫描线SL电性连接，所述第四晶体管T4的源极和漏极电性连接于所述第二电容C2和所述第一电压端VDD之间。可选地，所述第三晶体管T3和所述第四晶体管T4的栅极与同一所述扫描线SL电性连接，所述第三晶体管T3和所述第四晶体管T4均为P型晶体管或均为N型晶体管，以使所述第三晶体管T3导通时，所述第四晶体管T4也导通，保证所述数据信号的有效写入及所述第一晶体管T1的阈值电压的有效侦测。具体地，所述第四晶体管T4的栅极与第一扫描线SL1电性连接，所述第四晶体管T4的源极或漏极中的一个与所述第二电容C2电性连接，所述第四晶体管T4的源极或漏极中的另一个与所述第一电压端VDD电性连接。
由于在信号在传输过程中会出现损耗(如信号传输过程中存在电压降)，使所述显示面板内驱动各处所述发光器件D发光的驱动电流存在差异，导致所述显示面板出现显示不均的问题。所述像素驱动电路还包括第五晶体管T5，所示第五晶体管T5的栅极与对应的所述扫描线SL电性连接，所述第五晶体管T5的源极和漏极电性连接于所述第二电压端VSS与所述第一晶体管T1的所述源极或所述漏极中和所述第一电容C1电性连接的一个之间。具体地，所述第五晶体管T5的栅极与第四扫描线SL4电性连接，所述第五晶体管T5的源极或漏极中的一个与所述第二电压端VSS电性连接，所述第五晶体管T5的源极或漏极中的另一个与所述第一晶体管T1的源极或漏极中和所述第一电容C1电性连接的一个电性连接，所述第五晶体管T5用于根据所述第四扫描线SL4传输的第四扫描信号将所述第二电压端VSS提供的第二电压信号传输至所述第一晶体管T1的源极或漏极中和所述第一电容C1电性连接的一个，以通过所述第二电压信号补偿电压降对所述驱动电流的影响。
为保证所述发光器件D每次发光时，所述第一晶体管T1均能产生准确的驱动电流，所述像素驱动电路还包括第六晶体管T6，所述第六晶体管T6的栅极与对应的所述扫描线SL电性连接，所述第六晶体管T6的源极和漏极电性连接于所述第一电压端VDD和所述第一晶体管T1的栅极之间。具体地，所述第六晶体管T6的栅极与第三扫描线SL3电性连接，所述第六晶体管T6的源极或漏极中的一个与所述第一电压端VDD电性连接，所述第六晶体管T6的源极或漏极中的另一个与所述第一晶体管T1的栅极电性连接，所述第六晶体管T6用于根据所述第三扫描线SL3传输的第三扫描信号将所述第一电压端VDD提供的第一电压信号传输至所述第一晶体管T1的栅极，以通过所述第一电压信号对所述第一晶体管T1的栅极电压进行初始化。
为实现所述发光器件D的发光阶段的可控，所述像素驱动电路还包括第七晶体管T7，所述第七晶体管T7的栅极与对应的发射线EML电性连接，所述第七晶体管T7的源极和漏极电性连接于所述发光器件D和所述第一晶体管T1的所述源极或所述漏极中的一个之间。具体地，所述第七晶体管T7的源极或漏极中的一个与所述发光器件D的阴极电性连接，所述第七晶体管T7的源极或漏极中的另一个与所述第一晶体管T1的源极或漏极中的一个电性连接，所述第七晶体管T7用于根据所述发射线EML传输的发射控制信号使所述第一晶体管T1产生驱动所述发光器件D发光的驱动电流。
可选地，所述第五晶体管T5在所述第七晶体管T7响应所述发射控制信号时可导通，以使所述第一晶体管T1在所述第一电压端VDD和所述第二电压端VSS之间产生驱动所述发光器件D发光的驱动电流。
可选地，所述像素驱动电路还包括第八晶体管T8，所述第八晶体管T8的栅极与所述发射线EML电性连接，所述第八晶体管的源极和漏极电性连接于第二电压端VSS和所述第一晶体管T1的所述源极或所述漏极中的另一个之间。具体地，所述第八晶体管T8的源极或漏极中的一个与所述第一晶体管T1的源极或漏极中的另一个电性连接，所述第八晶体管T8的源极或漏极中的另一个与所述第二电压端VSS电性连接，所述第八晶体管T8和所述第七晶体管T7用于根据所述发射线EML传输的发射控制信号使所述第一晶体管T1在所述第一电压端VDD和所述第二电压端VSS之间产生驱动所述发光器件D发光的驱动电流。
在第N帧周期内，所述像素驱动电路的驱动方法包括：初始化阶段、阈值电压侦测及数据写入阶段、过渡阶段、电源电压写入阶段及发光阶段。
在所述初始化阶段，所述发射线EML传输的发射控制信号为低电平，所述数据线DL传输的所述数据信号Data为Data_L，所述第一扫描线SL1传输的所述第一扫描信号为高电平，所述第二扫描线SL2传输的所述第二扫描信号为低电平，所述第三扫描线SL3传输的所述第三扫描信号为高电平，所述第四扫描线SL4传输的所述第四扫描信号为低电平。所述第二晶体管T2、所述第五晶体管T5、所述第七晶体管T7(如图4A所示)或所述第七晶体管T7和所述第八晶体管T8(如图4B所示)截止。所述第三晶体管T3、所述第四晶体管T4和所述第六晶体管T6导通。所述数据信号Data_L被传输至所述第一晶体管T1的源极或漏极中与所述第一电容C1电性连接的一个，所述第一电压端VDD提供的第一电压信号被传输至所述第一晶体管T1的栅极，实现所述第一晶体管T1栅极电位的初始化。
在所述阈值电压侦测及数据写入阶段，所述数据线DL传输的所述数据信号Data为Data_H，所述第一扫描信号和所述第二扫描信号为高电平，所述第三扫描信号、所述第四扫描信号和所述发射控制信号为低电平。所述第五晶体管T5、所述第六晶体管T6、所述第七晶体管T7(如图4A所示)或所述第七晶体管T7和所述第八晶体管T8(如图4B所示)截止。所述第二晶体管T2、所述第三晶体管T3和所述第四晶体管T4导通。所述数据信号Data_H被传输至所述第一晶体管T1的源极或漏极中与所述第一电容C1电性连接的一个；所述第二晶体管T2导通使得所述第一晶体管T1呈二极管式连接，所述第一晶体管T1的栅极电位由Vdd变为Data_H+Vth，所述第一晶体管T1的阈值电压被存储至所述第一电容C1中，所述数据信号Data_H被存储至所述第二电容C2中。其中，Vth表示所述第一晶体管T1的阈值电压。
在所述过渡阶段，所述数据线DL传输的所述数据信号Data为Data_L，所述第一扫描信号为高电平，所述第二扫描信号、所述第三扫描信号、所述第四扫描信号及所述发射控制信号为低电平。所述第二晶体管、所述第五晶体管T5、所述第六晶体管T6、所述第七晶体管T7(如图4A所示)或所述第七晶体管T7和所述第八晶体管T8(如图4B所示)截止。所述第三晶体管T3和所述第四晶体管T4导通，所述数据信号Data_L被传输至所述第一晶体管T1的源极或漏极中与所述第一电容C1电性连接的一个。所述第一晶体管T1的栅极电位因电容耦合作用由Data_H+Vth变为Data_H+Vth+V0。其中，V0=（Data_H-Data_L）*C1/(C1+C2)。
在所述电源电压写入阶段，所述数据线DL传输的所述数据信号Data为Data_L，所述第一扫描信号、所述第二扫描信号、所述第三扫描信号及所述发射控制信号为低电平，所述第四扫描信号为高电平。所述第二晶体管T2、所述第三晶体管T3、所述第四晶体管T4、所述第六晶体管T6、所述第七晶体管T7(如图4A所示)或所述第七晶体管T7和所述第八晶体管T8(如图4B所示)截止。所述第五晶体管T5导通，所述第二电压端VSS提供的第二电压信号被传输至所述第一晶体管T1的源极或漏极中与所述第一电容C1电性连接的一个，所述第一晶体管T1的栅极电位因电容耦合作用由Data_H+Vth+V0变为Data_H+Vth+V0+Vss-Data_L。
在所述发光阶段，所述数据线DL传输的所述数据信号Data为Data_L，所述发射控制信号为高电平，所述第一扫描信号、所述第二扫描信号、所述第三扫描信号为低电平；所述第二晶体管T2、所述第三晶体管T3、所述第四晶体管T4及所述第六晶体管T6截止。若所述第四扫描信号为高电平（如图4A所示），所述第五晶体管T5导通，所述第七晶体管T7响应所述发射控制信号导通，所述第一晶体管T1产生驱动所述发光器件D发光的所述驱动电流。若所述第四扫描信号为低电平时（如图4B所示），所述第五晶体管T5截止，所述第七晶体管T7和所述第八晶体管T8导通，所述第一晶体管T1产生驱动所述发光器件D发光的所述驱动电流。
本申请还提供一种显示装置，所述显示装置包括任一上述的驱动电路或任一上述的显示面板。
可以理解地，所述显示装置包括可移动显示装置（如笔记本电脑、手机等）、固定终端（如台式电脑、电视等）、测量装置（如运动手环、测温仪等）等。
本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种像素驱动电路，其中，包括：
    第一晶体管，所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极或漏极中的一个电性连接于第二节点，所述第一晶体管的源极或漏极中的另一个电性连接于第三节点；
    第二晶体管，所述第二晶体管的源极和漏极电性连接于所述第一节点和所述第三节点之间，所述第二晶体管的栅极电性连接于第二扫描线，用于根据第二扫描信号侦测所述第一晶体管的阈值电压；
    第一电容，串联于所述第一节点和所述第二节点之间；
    第二电容，串联于所述第一节点和第一电压端之间；
    发光器件，电性连接于所述第一电压端和所述第三节点之间；以及
    第五晶体管，所述第五晶体管的源极和漏极电性连接于第二电压端和所述第二节点之间，所述第五晶体管的栅极电性连接于第四扫描线，用于根据第四扫描信号补偿第二电压信号。
  2. 根据权利要求1所述的像素驱动电路，其中，还包括：
    第三晶体管，所述第三晶体管的源极和漏极电性连接于数据线和所述第二节点之间，所述第三晶体管的栅极电性连接于第一扫描线，用于根据第一扫描信号向所述第二节点传输数据信号。
  3. 根据权利要求2所述的像素驱动电路，其中，还包括：
    第四晶体管，所述第四晶体管的源极和漏极电性连接于所述第二电容和所述第一电压端之间，所述第四晶体管的栅极电性连接于所述第一扫描线，用于在所述第五晶体管补偿所述第二电压信号时断开所述第一电压端和所述第二电容的电性连接。
  4. 根据权利要求1所述的像素驱动电路，其中，还包括：
    第六晶体管，所述第六晶体管的源极和漏极电性连接于所述第一电压端和所述第一节点之间，所述第六晶体管的栅极电性连接于第三扫描线，用于根据第三扫描信号初始化所述第一节点的电位。
  5. 根据权利要求1所述的像素驱动电路，其中，还包括：
    第七晶体管，所述第七晶体管的源极和漏极电性连接于所述发光器件和所述第三节点之间，所述第七晶体管的栅极电性连接于发射线。
  6. 根据权利要求5所述的像素驱动电路，其中，还包括：
    第八晶体管，所述第八晶体管的源极和漏极电性连接于第二电压端和所述第二节点之间，所述第八晶体管的栅极电性连接于所述发射线。
  7. 根据权利要求1所述的像素驱动电路，其中，所述第一电容的电容量小于或等于所述第二电容的电容量。
  8. 根据权利要求1所述的像素驱动电路，其中，所述发光器件包括有机发光二极管、次毫米发光二极管或微型发光二极管。
  9. 根据权利要求3所述的像素驱动电路，所述第三晶体管和所述第四晶体管均为P型晶体管或均为N型晶体管。
  10. 一种像素驱动电路的驱动方法，其中，用于驱动如权利要求1所述的像素驱动电路，所述驱动方法包括：
    阈值电压侦测及数据写入阶段：所述第二晶体管响应所述第二扫描信号导通，使得所述第一晶体管呈二极管式连接；
    电源电压写入阶段：所述第五晶体管响应所述第四扫描信号导通，所述第二电压端提供的所述第二电压信号被传输至所述第二节点。
  11. 一种显示面板，其中，包括电源和像素驱动电路，所述像素驱动电路包括：
    第一晶体管，所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极或漏极中的一个电性连接于第二节点，所述第一晶体管的源极或漏极中的另一个电性连接于第三节点；
    第二晶体管，所述第二晶体管的源极和漏极电性连接于所述第一节点和所述第三节点之间，所述第二晶体管的栅极电性连接于第二扫描线；
    第一电容，串联于所述第一节点和所述第二节点之间；
    第二电容，串联于所述第一节点和第一电压端之间；
    发光器件，电性连接于所述第一电压端和所述第三节点之间；以及
    第五晶体管，所述第五晶体管的源极和漏极电性连接于第二电压端和所述第二节点之间，所述第五晶体管的栅极电性连接于第四扫描线；
    所述电源与所述像素驱动电路的所述第一电压端电性连接。
  12. 根据权利要求11所述的显示面板，其中，所述像素驱动电路还包括：
    第三晶体管，所述第三晶体管的源极和漏极电性连接于数据线和所述第二节点之间，所述第三晶体管的栅极电性连接于第一扫描线。
  13. 根据权利要求12所述的显示面板，其中，所述像素驱动电路还包括：
    第四晶体管，所述第四晶体管的源极和漏极电性连接于所述第二电容和所述第一电压端之间，所述第四晶体管的栅极电性连接于所述第一扫描线。
  14. 根据权利要求11所述的显示面板，其中，所述像素驱动电路还包括：
    第六晶体管，所述第六晶体管的源极和漏极电性连接于所述第一电压端和所述第一节点之间，所述第六晶体管的栅极电性连接于第三扫描线。
  15. 根据权利要求11所述的显示面板，其中，所述像素驱动电路还包括：
    第七晶体管，所述第七晶体管的源极和漏极电性连接于所述发光器件和所述第三节点之间，所述第七晶体管的栅极电性连接于发射线。
  16. 根据权利要求15所述的显示面板，其中，所述像素驱动电路还包括：
    第八晶体管，所述第八晶体管的源极和漏极电性连接于第二电压端和所述第二节点之间，所述第八晶体管的栅极电性连接于所述发射线。
  17. 根据权利要求11所述的显示面板，其中，所述第一电容的电容量小于或等于所述第二电容的电容量。
  18. 根据权利要求11所述的显示面板，其中，所述发光器件包括有机发光二极管、次毫米发光二极管或微型发光二极管。
  19. 根据权利要求13所述的显示面板，其中，所述第三晶体管和所述第四晶体管均为P型晶体管或均为N型晶体管。
  20. 根据权利要求11所述的显示面板，其中，所述显示面板还包括栅极驱动芯片，所述栅极驱动芯片通过所述第二扫描线与所述第二晶体管的栅极电性连接，通过所述第四扫描线与所述第五晶体管的栅极电性连接。
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Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040009285A (ko) * 2002-07-23 2004-01-31 삼성에스디아이 주식회사 유기 전계발광 표시장치 및 그의 구동방법
CN106448526A (zh) * 2015-08-13 2017-02-22 群创光电股份有限公司 驱动电路
CN106887207A (zh) * 2015-12-15 2017-06-23 昆山工研院新型平板显示技术中心有限公司 像素电路及其驱动方法和有机发光显示器
CN107230451A (zh) * 2017-07-11 2017-10-03 深圳市华星光电半导体显示技术有限公司 一种amoled像素驱动电路及像素驱动方法
CN108257549A (zh) * 2016-12-29 2018-07-06 乐金显示有限公司 电致发光显示器
CN109243368A (zh) * 2018-11-13 2019-01-18 京东方科技集团股份有限公司 像素电路及其驱动方法、阵列基板
CN112071275A (zh) * 2020-09-28 2020-12-11 成都中电熊猫显示科技有限公司 像素驱动电路及方法、显示面板

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040009285A (ko) * 2002-07-23 2004-01-31 삼성에스디아이 주식회사 유기 전계발광 표시장치 및 그의 구동방법
CN106448526A (zh) * 2015-08-13 2017-02-22 群创光电股份有限公司 驱动电路
CN106887207A (zh) * 2015-12-15 2017-06-23 昆山工研院新型平板显示技术中心有限公司 像素电路及其驱动方法和有机发光显示器
CN108257549A (zh) * 2016-12-29 2018-07-06 乐金显示有限公司 电致发光显示器
CN107230451A (zh) * 2017-07-11 2017-10-03 深圳市华星光电半导体显示技术有限公司 一种amoled像素驱动电路及像素驱动方法
CN109243368A (zh) * 2018-11-13 2019-01-18 京东方科技集团股份有限公司 像素电路及其驱动方法、阵列基板
CN112071275A (zh) * 2020-09-28 2020-12-11 成都中电熊猫显示科技有限公司 像素驱动电路及方法、显示面板

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