WO2024021465A1 - 像素驱动电路和显示面板 - Google Patents

像素驱动电路和显示面板 Download PDF

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Publication number
WO2024021465A1
WO2024021465A1 PCT/CN2022/141297 CN2022141297W WO2024021465A1 WO 2024021465 A1 WO2024021465 A1 WO 2024021465A1 CN 2022141297 W CN2022141297 W CN 2022141297W WO 2024021465 A1 WO2024021465 A1 WO 2024021465A1
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Prior art keywords
voltage
switch tube
light
reset
energy storage
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PCT/CN2022/141297
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English (en)
French (fr)
Inventor
周仁杰
李荣荣
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惠科股份有限公司
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Application filed by 惠科股份有限公司 filed Critical 惠科股份有限公司
Priority to EP22925233.3A priority Critical patent/EP4336486A4/en
Priority to KR1020237031780A priority patent/KR20240016940A/ko
Publication of WO2024021465A1 publication Critical patent/WO2024021465A1/zh

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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G2300/0408—Integration of the drivers onto the display substrate
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    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
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    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
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    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
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    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
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    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Definitions

  • the present application relates to the field of display technology, and in particular, to a pixel driving circuit and a display panel.
  • each OLED has a corresponding pixel driving circuit.
  • the pixel driving circuit is usually composed of multiple thin film transistors (TFTs).
  • the threshold voltage Vth that is, the gate-to-source bias voltage that puts the TFT in a critical off or critical on state
  • mobility etc.
  • mura unevenness
  • pixel driving circuits with compensation are usually designed, such as 6T1C, 7T1C, 8T1C and other pixel driving circuits, and let the pixels
  • the driving circuit works in the reset phase, data writing phase, and light-emitting phase in sequence.
  • the display brightness of the OLED is related to the data voltage Vdata and the driving voltage VDD, and has nothing to do with the threshold voltage Vth of the TFT.
  • the pixel driving circuits with different distances from the power chip receive different driving voltages VDD. This causes differences in the display brightness of OLEDs with different distances from the power chip. , so that the mura phenomenon cannot be completely solved, and as the size of the OLED display increases, the mura phenomenon becomes more obvious, seriously affecting the user's visual experience.
  • the present application provides a pixel driving circuit.
  • the pixel driving circuit is configured to drive a light-emitting element to emit light.
  • the first end of the light-emitting element is configured to receive a reference voltage.
  • the pixel driving circuit sequentially works in reset during a frame display period.
  • stage, data writing stage and light emitting stage the pixel driving circuit includes a driving transistor, an energy storage capacitor, an energy storage capacitor reset circuit, a bootstrap capacitor, a precharge circuit, a data writing circuit and a light emitting circuit.
  • the driving transistor includes a control terminal, a first connection terminal and a second connection terminal, the first connection terminal is configured to receive a driving voltage, and the second connection terminal is electrically connected to the second terminal of the light emitting element.
  • the first end of the energy storage capacitor is electrically connected to the control end of the driving transistor, and the second end of the energy storage capacitor is configured to receive a first voltage with a constant voltage value.
  • the energy storage capacitor reset loop is configured to be turned on during the reset phase, and receives a first reset voltage to reset the voltage at the first end of the energy storage capacitor to the first reset voltage.
  • the first end of the bootstrap capacitor is electrically connected to the first connection end of the drive transistor, the second end of the bootstrap capacitor receives zero potential voltage during the reset phase, and the second end of the bootstrap capacitor Receives the data voltage during the data writing phase.
  • the precharge loop is configured to be turned on during the reset phase, and receive the driving voltage to charge the bootstrap capacitor to adjust the voltage at the first end of the bootstrap capacitor to the driving voltage, And the voltage of the second terminal of the bootstrap capacitor is reset to zero potential, so that the voltage difference between the first terminal and the second terminal of the bootstrap capacitor reaches the driving voltage.
  • the data writing loop includes the bootstrap capacitor, the driving transistor and the energy storage capacitor connected in series. The data writing loop is configured to be turned on during the data writing phase to receive the data voltage through the second end of the bootstrap capacitor and perform operation on the energy storage capacitor based on the bootstrap effect of the bootstrap capacitor.
  • the light-emitting circuit includes the driving transistor and the light-emitting element connected in series.
  • the light-emitting loop is configured to be turned on during the light-emitting phase, so that the first connection end of the driving transistor receives the driving voltage to drive the light-emitting element to emit light.
  • the pixel driving circuit charges the voltage of the first terminal of the bootstrap capacitor to the driving voltage through the precharge loop during the reset phase, and receives the data voltage through the second terminal of the bootstrap capacitor during the data writing phase and performs the operation based on the self-starting voltage.
  • the bootstrap effect of the lifting capacitor charges the energy storage capacitor to adjust the voltage at the control terminal of the driving transistor to a second voltage whose voltage value is equal to the sum of the driving voltage, the data voltage and the threshold voltage of the driving transistor, and during the light-emitting phase, the driving The transistor drives the light-emitting element to emit light based on the second voltage received by its control terminal and the driving voltage received by its first connection terminal, so that the current flowing through the light-emitting element has nothing to do with the driving voltage and the threshold voltage of the driving transistor, which not only eliminates
  • the uneven display brightness of the display panel caused by the different threshold voltages of the driving transistors in different pixel driving circuits can also eliminate the uneven display brightness of the display panel caused by the inconsistent driving voltages received by different pixel driving circuits. Phenomenon.
  • This application also provides a display panel, which includes a substrate and a plurality of the above-mentioned pixel driving circuits.
  • the substrate includes a display area, and the plurality of pixel driving circuit arrays are arranged in the display area of the substrate.
  • the pixel driving circuit is configured to drive the light-emitting element to emit light, and the first end of the light-emitting element is configured to receive a reference voltage.
  • the pixel driving circuit sequentially works in the reset phase, the data writing phase and the data writing phase in a frame display period.
  • the pixel driving circuit includes a driving transistor, an energy storage capacitor, an energy storage capacitor reset circuit, a bootstrap capacitor, a precharge circuit, a data writing circuit, and a light-emitting circuit.
  • the driving transistor includes a control terminal, a first connection terminal and a second connection terminal, the first connection terminal is configured to receive a driving voltage, and the second connection terminal is electrically connected to the second terminal of the light emitting element.
  • the first end of the energy storage capacitor is electrically connected to the control end of the driving transistor, and the second end of the energy storage capacitor is configured to receive a first voltage with a constant voltage value.
  • the energy storage capacitor reset loop is configured to be turned on during the reset phase, and receives a first reset voltage to reset the voltage at the first end of the energy storage capacitor to the first reset voltage.
  • the first end of the bootstrap capacitor is electrically connected to the first connection end of the drive transistor, the second end of the bootstrap capacitor receives zero potential voltage during the reset phase, and the second end of the bootstrap capacitor Receives the data voltage during the data writing phase.
  • the precharge loop is configured to be turned on during the reset phase, and receive the driving voltage to charge the bootstrap capacitor to adjust the voltage at the first end of the bootstrap capacitor to the driving voltage, And the voltage of the second terminal of the bootstrap capacitor is reset to zero potential, so that the voltage difference between the first terminal and the second terminal of the bootstrap capacitor reaches the driving voltage.
  • the data writing loop includes the bootstrap capacitor, the driving transistor and the energy storage capacitor connected in series.
  • the data writing loop is configured to be turned on during the data writing phase to receive the data voltage through the second end of the bootstrap capacitor and perform operation on the energy storage capacitor based on the bootstrap effect of the bootstrap capacitor.
  • the light-emitting circuit includes the driving transistor and the light-emitting element connected in series. The light-emitting loop is configured to be turned on during the light-emitting phase, so that the first connection end of the driving transistor receives the driving voltage to drive the light-emitting element to emit light.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a conventional pixel driving circuit.
  • FIG. 3 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present application.
  • FIG. 4 is an operation timing diagram of the pixel driving circuit shown in FIG. 3 .
  • Figure 5a is a circuit schematic diagram of the pixel driving circuit shown in Figure 3 in stage A.
  • Figure 5b is a circuit schematic diagram of the pixel driving circuit shown in Figure 3 in stage B.
  • Figure 5c is a circuit schematic diagram of the pixel driving circuit shown in Figure 3 in stage C.
  • the present application provides a display panel 1 .
  • the display panel 1 includes a substrate 1000 and a main drive circuit 2000 that are electrically connected to each other.
  • the substrate 1000 includes a display area 1001 and a non-display area 1002 .
  • a plurality of pixel driving circuits 100 arranged in an array are provided in the display area 1001.
  • the main driving circuit 2000 includes a scanning signal generating module 110 , a data voltage generating module 120 and a driving voltage generating module 130 .
  • the scanning signal generation module 110 is electrically connected to multiple rows of the pixel driving circuits 100 through a plurality of scanning lines 111, and the scanning signal generation module 110 is used to generate a plurality of corresponding pixel driving circuits 100 for each row.
  • the data voltage generation module 120 is electrically connected to multiple columns of the pixel driving circuits 100 through a plurality of data lines 121.
  • the data voltage generation module 120 is used to generate a corresponding data voltage Vdata for each column of the pixel driving circuits 100.
  • the driving voltage generation module 130 is electrically connected to multiple rows of the pixel driving circuits 100 through a plurality of power supply voltage lines 131 .
  • the driving voltage generating module 130 is used to generate a driving voltage VDD for each row of the pixel driving circuits 100 .
  • FIG. 2 shows an existing pixel driving circuit 100' with a 2T1C structure.
  • the pixel driving circuit 100' includes a scanning transistor T0, a driving transistor M, an energy storage capacitor C and a light-emitting element.
  • the pixel driving circuit 100' is used to drive the light-emitting element to emit light.
  • the light-emitting element is an OLED, and the first end and the second end of the light-emitting element correspond to the cathode and anode of the OLED.
  • the light-emitting element may also be LED (Light-Emitting Diode, light-emitting diode), MicroLED (Micro Light-Emitting Diode, micro-light-emitting diode) or MiniLED (Mini Light-Emitting Diode, sub-millimeter led).
  • the cathode of the light-emitting element OLED is electrically connected to the reference voltage terminal to receive the reference voltage signal Vss.
  • the source of the driving transistor M is electrically connected to the power supply voltage line 131 to receive the driving voltage VDD.
  • the driving transistor M The drain is electrically connected to the anode of the light-emitting element OLED, the gate of the driving transistor M is electrically connected to the drain of the scanning transistor T0, and the source of the scanning transistor T0 is electrically connected to the data line 121 to receive The data voltage Vdata, the gate of the scan transistor T0 is electrically connected to the scan line 111 to receive the scan signal.
  • the first end of the energy storage capacitor C is electrically connected to the gate of the driving transistor M, and the second end of the energy storage capacitor C is electrically connected to the cathode of the light emitting element OLED.
  • the scan signal is a turn-on signal
  • the scan transistor T0 is turned on, and the data voltage Vdata on the data line 121 charges the energy storage capacitor C through the scan transistor T0 to charge the energy storage capacitor C.
  • the voltage at the first end of the energy storage capacitor C is adjusted to the data voltage Vdata, and the driving transistor M is driven based on the data voltage Vdata received by its gate and the driving voltage VDD received by its source.
  • the light-emitting element is an OLED that emits light.
  • the pole voltage Vgs has the following relationship:
  • K Cox ⁇ W/L
  • Cox is the gate capacitance per unit area
  • ⁇ is the mobility of channel electron movement
  • W/L is the width-to-length ratio of the channel of the driving transistor M
  • the existing display panel designs the pixel driving circuit 100' as a driving circuit with a threshold compensation function (not shown in the figure). ), allowing the drive circuit to work in the reset phase, data writing phase, and light-emitting phase in sequence.
  • the energy storage capacitor C is charged to adjust the voltage at its first end to (Vdata+Vth).
  • the brightness of the light-emitting element OLED is related to the data voltage Vdata and the driving voltage VDD, but has nothing to do with the threshold voltage Vth of the driving transistor M. In this way, the differences caused by different driving transistors M can be eliminated.
  • the difference in threshold voltage Vth causes uneven display brightness of the display panel 1 .
  • the power supply voltage line 131 used to transmit the driving voltage VDD itself has a line impedance
  • the pixel driving circuit 100 at a different distance from the driving voltage generating module 130 receives a different driving voltage VDD. This causes the difference between the driving voltage VDD and the driving voltage VDD.
  • the present application provides a new type of pixel driving circuit 100.
  • the circuit 100 is used to drive the light emitting element OLED to emit light.
  • the pixel driving circuit 100 includes an energy storage capacitor C1, a bootstrap capacitor C2, a driving transistor M, a first switching tube T1, a second switching tube T2, a third switching tube T3, a fourth switching tube T4, and a fifth switching tube T5. and the sixth switching transistor T6.
  • the control terminals of the switch tubes T1 to T6 are electrically connected to the scanning signal generation module 110.
  • the switch tubes T1 to T6 can be at least one of a triode or a MOS tube.
  • the switch transistors T1 to T6 and the driving transistor M are all low-level conducting transistors, such as PMOS transistors.
  • the switch transistors T1 to T6 and the driving transistor M are high-level conduction transistors, such as NMOS transistors.
  • the switch transistors T1 to T6 may be the same type of transistor, which are conducive to simplifying the manufacturing process of the substrate 1000 and is conducive to reducing processing difficulty and production cost.
  • the switch transistors T1 to T6 and the driving transistor M may also use different types of transistors, which are not limited here.
  • the switch transistors T1 to T6 and the driving transistor M in this application can use amorphous silicon thin film transistors (a-Si TFT), or use low-temperature polysilicon thin film transistors (LTPS TFT), or use oxide Semiconductor thin film transistor (Oxide TFT).
  • the active layer of the oxide semiconductor thin film transistor uses oxide semiconductor (Oxide), such as Indium Gallium Zinc Oxide (IGZO).
  • oxide semiconductor such as Indium Gallium Zinc Oxide (IGZO).
  • the switch transistors T1 to T6 use oxide semiconductor thin film transistors
  • the driving transistor M uses a low-temperature polysilicon transistor. Since the mobility of the low-temperature polysilicon transistor is relatively high, the mobility of the driving transistor M can be improved. The conduction speed can further increase the response speed of the pixel driving circuit 100, thereby improving the display effect of the display panel 1.
  • the pixel driving circuit 100 sequentially operates in a reset phase (A phase), a data writing phase (B phase), and a light emitting phase (C phase) in one frame display period.
  • the pixel driving circuit 100 includes a precharge circuit L1 and a capacitor reset circuit L2.
  • the capacitor reset loop L2 includes the first switch tube T1, the bootstrap capacitor C2 and the second switch tube T2 which are connected in series in sequence.
  • the first connection end of the first switch tube T1 is used to receive The driving voltage VDD, the second connection end of the first switching transistor T1 and the first end of the bootstrap capacitor C2 are electrically connected.
  • the first connection end of the second switch transistor T2 is electrically connected to the ground end to receive zero potential voltage, and the second connection end of the second switch transistor T2 is electrically connected to the second end of the bootstrap capacitor C2.
  • the precharge circuit L1 is used to be turned on during the reset phase (that is, both the first switching tube T1 and the second switching tube T2 are turned on), and receive the driving voltage VDD to charge the bootstrap capacitor.
  • C2 charges to adjust the voltage of the first terminal of the bootstrap capacitor C2 to the driving voltage VDD, and resets the voltage of the second terminal of the bootstrap capacitor C2 to zero potential, so that the bootstrap capacitor C2 The voltage difference between the first terminal and the second terminal of the capacitor C2 reaches the driving voltage VDD.
  • the bootstrap capacitor C2 can release the residual charge in the previous frame display period to the ground terminal through the second switch transistor T2, thereby switching the second terminal of the bootstrap capacitor C2 to the first
  • the voltage at the connection end is reset to zero potential to ensure the uniformity of the display effect of the display panel 1 .
  • the capacitor reset circuit L2 includes the energy storage capacitor C1 and the sixth switch T6 connected in series, wherein the first connection end of the sixth switch T6 is used to receive the first reset voltage, and the sixth switch T6
  • the second connection end of the switching tube T6 is electrically connected to the first end of the energy storage capacitor C1, and the first end of the energy storage capacitor C1 is also electrically connected to the control end (i.e., the gate g) of the driving transistor M.
  • the second end of the energy storage capacitor C1 is used to receive the first voltage V1 with a constant voltage value.
  • the capacitor reset loop L2 is configured to be turned on during the reset phase (that is, the sixth switch T6 is turned on), and receive the first reset voltage to conduct voltage on the first end of the energy storage capacitor C1
  • Resetting means charging the energy storage capacitor C1 and resetting the voltage at its first end to the first reset voltage.
  • the initial voltage values are all equal, which is the first reset voltage, to ensure the uniformity of the display effect of the display panel 1 .
  • the first voltage V1 received by the second end of the energy storage capacitor C1 is a zero potential voltage.
  • the first voltage V1 may also be the driving voltage VDD. .
  • the first end of the light-emitting element OLED is used to receive the reference voltage VSS, and the second end of the light-emitting element OLED is electrically connected to the second connection end (ie, the drain d) of the driving transistor M.
  • the pixel driving circuit 100 further includes a light-emitting element reset circuit L3.
  • the light-emitting element reset circuit L3 includes a seventh switch tube T7 and the light-emitting element OLED connected in series, wherein the seventh switch tube T7 The first connection end is used to receive the second reset voltage, and the first connection end of the seventh switch tube T7 is electrically connected to the second end of the light-emitting element OLED.
  • the light-emitting element reset circuit L3 is configured to be turned on during the reset stage (that is, the seventh switch transistor T7 is turned on) to reset the voltage at the second end of the light-emitting element OLED to the second reset voltage.
  • the voltage of the second terminal of the light-emitting element OLED in the light-emitting phase of the previous frame display period, the voltage of the second terminal of the light-emitting element OLED
  • the initial voltage values are all equal, which is the second reset voltage, so as to further improve the uniformity of the display effect of the display panel 1 .
  • the voltage value of the first reset voltage and the voltage value of the second reset voltage are both equal to the reset voltage Vint, where Vint ⁇ VSS. In this way, during the reset phase, the second reset voltage will not This causes the OLED, the light-emitting element, to emit light incorrectly.
  • the voltage value of the first reset voltage and the voltage value of the second reset voltage may not be equal.
  • the pixel driving circuit 100 further includes a data writing circuit L4.
  • the data writing circuit L4 includes the third switching transistor T3, the bootstrap capacitor C2, and the driving transistor connected in series. M the fourth switching transistor T4 and the energy storage capacitor C1.
  • the first connection end of the third switching transistor T3 is used to receive the data voltage Vdata
  • the second connection end of the third switching transistor T3 is electrically connected to the second end of the bootstrap capacitor C2
  • the first terminal of the bootstrap capacitor C2 is also electrically connected to the first connection terminal of the driving transistor M (ie, the source s).
  • the fourth switching transistor T4 is electrically connected between the second connection terminal of the driving transistor M and the first terminal of the energy storage capacitor C1.
  • the data writing circuit L4 is configured to be turned on during the data writing phase to receive the data voltage Vdata through the first connection end of the third switching transistor T3 and based on the bootstrap of the bootstrap capacitor C2
  • the energy storage capacitor C1 is charged to adjust the voltage at the control terminal of the driving transistor M from the first reset voltage to the second voltage, wherein the voltage at the control terminal of the driving transistor M is equal to the
  • the critical conduction state is entered at the second voltage, and the voltage value of the second voltage is equal to the sum of the driving voltage VDD, the data voltage and the threshold voltage of the driving transistor M.
  • the third switching transistor T3 can release the residual charge in the previous frame display period to the ground terminal through the second switching transistor T2, thereby avoiding the upper voltage.
  • the voltage difference between the first terminal and the second terminal of the bootstrap capacitor C2 is the driving voltage VDD.
  • the bootstrap capacitor C2 receives the data voltage Vdata, it The second terminal changes from zero potential to Vdata, that is, the potential of the second terminal of the bootstrap capacitor C2 changes by Vdata. Due to the bootstrap effect of the bootstrap capacitor C2, the first terminal of the bootstrap capacitor C2 (i.e. The potential of the source voltage Vs of the driving transistor M also changes to (Vdata+VDD).
  • Vth is the threshold voltage of the driving transistor M.
  • Vgs ⁇ Vth the driving transistor M is turned on.
  • Vgs>Vth the driving transistor M is turned off.
  • the source voltage Vs charges the energy storage capacitor C1 through the turned-on data writing circuit L4, so that the voltage at the first end of the energy storage capacitor C1 continues to rise.
  • the driving transistor M Entering the critical conduction state, the voltage at the first end of the energy storage capacitor C1 no longer rises, where the voltage value of the second voltage is equal to (Vdata+VDD+Vth).
  • the bootstrap effect of the bootstrap capacitor C2 causes the data voltage Vdata to be transmitted to the energy storage capacitor C1 faster, thereby reducing the duration of the data writing phase and reducing the display time of one frame.
  • the length of the cycle is beneficial to increasing the refresh frequency of the display panel 1 .
  • the pixel driving circuit 100 further includes a light-emitting circuit L5.
  • the light-emitting circuit L5 includes the first switching tube T1, the driving transistor M, the fifth switching tube T5 and the The light-emitting element OLED.
  • the fifth switching transistor T5 is electrically connected between the second connection end of the driving transistor M and the second end of the light emitting element OLED.
  • the light-emitting circuit L5 is used to be turned on during the light-emitting phase, so that the first connection end of the driving transistor M receives the driving voltage VDD to drive the light-emitting element OLED to emit light.
  • the driving transistor M during the light-emitting phase, the driving transistor M continues to be turned on. Since the first switching tube T1 and the fifth switching tube T5 both operate in the linear region, The driving transistor M operates in a saturation region, so the size of the current flowing through the light-emitting element OLED mainly depends on the current Ids between the source and drain of the driving transistor M. According to the operating characteristics of the switching tube, it can be seen that the following equation relationship is satisfied between the current Ids and the gate-source voltage Vgs:
  • K Cox ⁇ W/L
  • Cox is the gate capacitance per unit area
  • ⁇ is the mobility of electron movement in the channel
  • W/L is the width-to-length ratio of the channel of the driving transistor M.
  • the data writing circuit L3 can provide a compensation voltage to the driving transistor M, so that the current Ids flowing through the light-emitting element OLED is consistent with the threshold voltage Vth of the driving transistor M and the driving voltage VDD. It is irrelevant, that is to say, as long as the writing accuracy of the data voltage Vdata is ensured, the luminous brightness of the light-emitting element OLED can be accurately controlled. Therefore, the pixel driving circuit 100 provided by the present application can not only eliminate the phenomenon of uneven display brightness of the display panel 1 caused by the different threshold voltages of the driving transistors M in different pixel driving circuits 100, but also eliminate the uneven display brightness caused by the different threshold voltages of the driving transistors M in different pixel driving circuits 100.
  • Different pixel driving circuits 100 receive different driving voltages VDD, which causes uneven display brightness of the display panel 1 .
  • the current Ids flowing through the light-emitting element OLED has nothing to do with the driving voltage VDD, according to the characteristic that the voltage difference between the first terminal and the first terminal of the light-emitting element OLED remains unchanged and its luminous brightness remains unchanged, it can be appropriately reduced.
  • the voltage value of the driving voltage VDD is used to reduce the power consumption of the pixel driving circuit 100 .
  • the switch transistors T1 to T7 and the driving transistor M are all transistors conducting at a low level.
  • the following is a detailed introduction to the working flow of the pixel driving circuit 100 provided by the present application within a frame scanning period with reference to Figures 3 to 5c:
  • the scan signal received by the control end of the first switch T1 is the first scan signal SCAN1, and the second switch T2, the sixth switch T6 and the seventh switch
  • the scanning signals received by the control terminal of the tube T7 are all the second scanning signal SCAN2
  • the scanning signals received by the control terminals of the third switching tube T3 and the fourth switching tube T4 are both the third scanning signal SCAN3, so
  • the scanning signal received by the control terminal of the fifth switching transistor T5 is the fourth scanning signal SCAN4.
  • Switch transistors with the same conduction timing can be controlled by the same scan signal, thus simplifying the wiring structure of the substrate 1000 .
  • each switching tube can also be controlled by setting a separate scanning signal, which is not limited here.
  • the first scan signal SCAN1 and the second scan signal SCAN2 are both low level, and the third scan signal SCAN3 and the fourth scan signal SCAN4 are both high level. flat. Therefore, the switching tubes T1, T2, T6, and T7 are all turned on, and the switching tubes T3 to T5 are all turned off, so that the precharge circuit L1 is turned on to charge the first terminal of the bootstrap capacitor C2.
  • the voltage of the energy storage capacitor C2 is adjusted to the driving voltage VDD and the voltage of the second terminal of the bootstrap capacitor C2 is reset to zero potential, and the energy storage capacitor reset loop L2 is turned on to reset the first voltage of the energy storage capacitor C1.
  • the voltage of the second terminal of the light-emitting element OLED is reset to the first reset voltage, and the light-emitting element reset loop L3 is turned on.
  • the voltage of the second terminal of the light-emitting element OLED is reset to the second reset voltage, and the data is written.
  • the input circuit L4 and the light-emitting circuit L5 are disconnected.
  • the third scanning signal SCAN3 is low level, and the first scanning signal SCAN1, the second scanning signal SCAN2 and the fourth scanning signal SCAN4 are all high. level. Therefore, the switching transistors T3 and T4 and the driving transistor M are all turned on, and the switching transistors T1, T2, T5, T6, and T7 are all turned off, so that the data writing circuit L4 is turned on to write all the data.
  • the voltage at the control terminal of the driving transistor M is adjusted from the first reset voltage to the second voltage, and causes the precharge circuit L1, the energy storage capacitor reset circuit L2, the light emitting element reset circuit L3 and the The above-mentioned light-emitting circuits L5 are all disconnected.
  • the first scan signal SCAN1 and the fourth scan signal SCAN4 are both low level, and the second scan signal SCAN2 and the third scan signal SCAN3 are both high level. flat. Therefore, the switching tubes T1 and T5 and the driving transistor M are all turned on, and the switching tubes T2, T3, T4, T6, and T7 are all turned off, so that the light-emitting circuit L5 is turned on to receive the driving
  • the voltage VDD drives the light-emitting element OLED to emit light, and causes the precharge circuit L1, the energy storage capacitor reset circuit L2, the light-emitting element reset circuit L3 and the data writing circuit L4 to all be disconnected.
  • the pixel driving circuit 100 provided by this application charges the voltage of the first terminal of the bootstrap capacitor C2 to the driving voltage VDD through the precharge loop L1 during the reset phase, and receives the voltage through the second terminal of the bootstrap capacitor C2 during the data writing phase.
  • the data voltage Vdata charges the energy storage capacitor C1 based on the bootstrap effect of the bootstrap capacitor C2 to adjust the voltage at the control terminal of the drive transistor M to a voltage value equal to the drive voltage VDD, the data voltage Vdata, and the threshold voltage Vth of the drive transistor M.
  • the driving transistor M drives the light-emitting element OLED to emit light based on the second voltage received by its control terminal and the driving voltage VDD received by its first connection terminal, thereby causing the light-emitting element OLED to flow through
  • the current has nothing to do with the driving voltage VDD and the threshold voltage Vth of the driving transistor M. It can not only eliminate the uneven display brightness of the display panel 1 caused by the different threshold voltages of the driving transistor M in different pixel driving circuits 100, but also can This eliminates the phenomenon of uneven display brightness of the display panel 1 caused by inconsistent driving voltages VDD received by different pixel driving circuits 100 .

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Abstract

一种像素驱动电路（100）和显示面板，该像素驱动电路(100)在复位阶段通过预充电回路(L1)将自举电容(C2)的第一端的电压充电至驱动电压（VDD），在数据写入阶段通过自举电容(C2)接收数据电压（Vdata）并通过自举电容(C2)对储能电容(C1)充电，将驱动晶体管(M)的控制端的电压调节至第二电压，以及在发光阶段使得驱动晶体管(M)基于第二电压和驱动电压（VDD）驱动发光元件(OLED)发光，可以消除显示亮度不均的现象。

Description

像素驱动电路和显示面板
本申请要求于2022年07月28日提交中国专利局、申请号为202210898918.7，申请名称为“像素驱动电路和显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种像素驱动电路和显示面板。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然构成现有技术。由于OLED(Organic Light-Emitting Diode，有机发光半导体)显示器具有功耗低、响应速度快、显示视角宽等优点，因此，OLED显示器的应用越来越广泛。在OLED显示器的OLED阵列中，每个OLED都具有相应的像素驱动电路，像素驱动电路通常由多个薄膜晶体管(thin filmtransistor，TFT)组成，然而，不同像素驱动电路的TFT的参数存在差异，例如阈值电压Vth(即，使得TFT处于临界截止或临界导通状态的栅极对源极的偏置电压)、迁移率等，如此，将导致不同OLED发出光线的亮度的差异，并被人眼所感知，这称现象称为mura(不均)现象，mura现象降低了显示装置的显示性能。
在现有技术中，为改善不同像素驱动电路的TFT的阈值电压不同引起的显示亮度不均，通常设计具有补偿作用的像素驱动电路，例如，6T1C、7T1C、8T1C等像素驱动电路，并让像素驱动电路依次工作于复位阶段、数据写入阶段、发光阶段。现有的像素驱动电路在数据写入阶段对TFT的阈值电压Vth进行补偿后，使得OLED的显示亮度与数据电压Vdata以及驱动电压VDD有关，而与TFT的阈值电压Vth无关。然而，由于用于传输驱动电压VDD的电源线本身存在阻抗，使得与电源芯片距离不同的像素驱动电路接收到的驱动电压VDD不同，如此，就引起与电源芯片距离不同的OLED的显示亮度存在差异，从而使得mura现象无法得到彻底地解决，并且随着OLED显示器的尺寸的增大，mura现象越明显，严重影响用户的视觉体验。
申请内容
本申请提供一种像素驱动电路，所述像素驱动电路设置为驱动发光元件发光，所述发光元件的第一端设置为接收参考电压，所述像素驱动电路在一帧显示周期中依次工作于复位阶段、数据写入阶段以及发光阶段，所述像素驱动电路包括驱动晶体管、储能电容、储能电容复位回路、自举电容、预充电回路、数据写入回路以及发光回路。所述驱动晶体管包括控制端、第一连接端和第二连接端，所述第一连接端设置为接收驱动电压，所述第二连接端与所述发光元件的第二端电连接。所述储能电容的第一端与所述驱动晶体管的控制端电连接，所述储能电容的第二端设置为接收电压值恒定的第一电压。所述储能电容复位回路设置为在复位阶段导通，并接收第一复位电压将所述储能电容的第一端的电压复位至所述第一复位电压。所述自举电容的第一端与所述驱动晶体管的第一连接端电连接，所述自举电容的第二端在所述复位阶段接收零电位电压，所述自举电容的第二端在数据写入阶段接收数据电压。所述预充电回路设置为在所述复位阶段导通，并接收所述驱动电压对所述自举电容进行充电，以将所述自举电容的第一端的电压调节至所述驱动电压，并将所述自举电容的第二端的电压复位 至零电位，从而使得所述自举电容的第一端和第二端之间的电压差值达到所述驱动电压。所述数据写入回路包括串联的所述自举电容、所述驱动晶体管以及所述储能电容。所述数据写入回路设置为在数据写入阶段导通，以通过所述自举电容的第二端接收所述数据电压并基于所述自举电容的自举效应对所述储能电容进行充电，以将所述驱动晶体管的控制端的电压从所述第一复位电压调节至第二电压，其中，所述驱动晶体管在其控制端的电压等于所述第二电压时进入临界导通状态，所述第二电压等于所述驱动电压、所述数据电压以及所述驱动晶体管的阈值电压之和。所述发光回路包括串联的所述驱动晶体管和所述发光元件。所述发光回路设置为在发光阶段导通，使得所述驱动晶体管的第一连接端接收到所述驱动电压，以驱动所述发光元件发光。
本申请提供的像素驱动电路，在复位阶段通过预充电回路将自举电容的第一端的电压充电至驱动电压，并在数据写入阶段通过自举电容的第二端接收数据电压并基于自举电容的自举效应对储能电容进行充电，以将驱动晶体管的控制端的电压调节至电压值等于驱动电压、数据电压以及驱动晶体管的阈值电压之和的第二电压，以及在发光阶段使得驱动晶体管基于其控制端接收到的第二电压及其第一连接端接收到的驱动电压驱动发光元件发光，从而使得流过发光元件的电流与驱动电压以及驱动晶体管的阈值电压均无关，不仅可以消除由于不同的像素驱动电路中驱动晶体管的阈值电压不同而引起显示面板的显示亮度不均的现象，还可以消除由于不同的像素驱动电路接收到的驱动电压不一致而引起显示面板的显示亮度不均的现象。
本申请还提供一种显示面板，所述显示面板包括基板和若干个上述的像素驱动电路，所述基板包括显示区，所述若干个像素驱动电路阵列排布在所述基板的显示区内。其中，所述像素驱动电路设置为驱动发光元件发光，所述发光元件的第一端设置为接收参考电压，所述像素驱动电路在一帧显示周期中依次工作于复位阶段、数据写入阶段以及发光阶段，所述像素驱动电路包括驱动晶体管、储能电容、储能电容复位回路、自举电容、预充电回路、数据写入回路以及发光回路。所述驱动晶体管包括控制端、第一连接端和第二连接端，所述第一连接端设置为接收驱动电压，所述第二连接端与所述发光元件的第二端电连接。所述储能电容的第一端与所述驱动晶体管的控制端电连接，所述储能电容的第二端设置为接收电压值恒定的第一电压。所述储能电容复位回路设置为在复位阶段导通，并接收第一复位电压将所述储能电容的第一端的电压复位至所述第一复位电压。所述自举电容的第一端与所述驱动晶体管的第一连接端电连接，所述自举电容的第二端在所述复位阶段接收零电位电压，所述自举电容的第二端在数据写入阶段接收数据电压。所述预充电回路设置为在所述复位阶段导通，并接收所述驱动电压对所述自举电容进行充电，以将所述自举电容的第一端的电压调节至所述驱动电压，并将所述自举电容的第二端的电压复位至零电位，从而使得所述自举电容的第一端和第二端之间的电压差值达到所述驱动电压。所述数据写入回路包括串联的所述自举电容、所述驱动晶体管以及所述储能电容。所述数据写入回路设置为在数据写入阶段导通，以通过所述自举电容的第二端接收所述数据电压并基于所述自举电容的自举效应对所述储能电容进行充电，以将所述驱动晶体管的控制端的电压从所述第一复位电压调节至第二电压，其中，所述驱动晶体管在其控制端的电压等于所述第二电压时进入临界导通状态，所述第二电压等于所述驱动电压、所述数据电压以及所述驱动晶体管的阈值电压之和。所述发光回路包括串联的所述驱动晶体管和所述发光元件。所述发光回路设置为在发光阶段导通，使得所述驱动晶体管的第一连接端接收到所述驱动电压，以驱动所述发光元件发光。
本申请的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本申请的实践了解到。
附图说明
图1是本申请实施例提供的显示面板的结构示意图。
图2是现有的像素驱动电路的结构示意图。
图3是本申请实施例提供的像素驱动电路的结构示意图。
图4是图3所示的像素驱动电路的工作时序图。
图5a是图3所示的像素驱动电路在A阶段的电路示意图。
图5b是图3所示的像素驱动电路在B阶段的电路示意图。
图5c是图3所示的像素驱动电路在C阶段的电路示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有付出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要说明的是，术语“上”、“下”、“左”、“右”等指示的方位或者位置关系为基于附图所示的方位或者位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性。
请参阅图1，本申请提供一种显示面板1，所述显示面板1包括相互电连接的基板1000和主驱动电路2000，所述基板1000包括显示区1001和非显示区1002。其中，所述显示区1001内设置阵列排布的若干个像素驱动电路100。所述主驱动电路2000包括扫描信号生成模块110、数据电压生成模块120以及驱动电压生成模块130。其中，所述扫描信号生成模块110通过多条扫描线111与多行所述像素驱动电路100分别电连接，所述扫描信号生成模块110用于为每一行所述像素驱动电路100生成相应的若干个扫描信号。所述数据电压生成模块120通过多条数据线121与多列所述像素驱动电路100分别电连接，所述数据电压生成模块120用于为每一列所述像素驱动电路100生成相应的数据电压Vdata。所述驱动电压生成模块130通过多条电源电压线131与多行所述像素驱动电路100分别电连接，所述驱动电压生成模块130用于为每一行所述像素驱动电路100生成驱动电压VDD。
请参阅图2，图2是现有的一种2T1C结构的像素驱动电路100'，所述像素驱动电路100'包括扫描晶体管T0、驱动晶体管M、储能电容C以及发光元件。
其中，所述像素驱动电路100'用于驱动所述发光元件发光。在本申请实施例中，所述发光元件为OLED，所述发光元件的第一端、第二端一一对应于OLED的阴极、阳极。在其他实施例中，所述发光元件还可以是LED(Light-Emitting Diode，发光二极管)、也可以是MicroLED(Micro Light-Emitting Diode，微发光二极管)或MiniLED(Mini Light-Emitting Diode，次毫米发光二极管)。所述发光元件OLED的阴极与参考电压端电连接以接收参考电压信号Vss，所述驱动晶体管M的源极与所述电源电压线131电连接以接收所述驱动电压VDD，所述驱动晶体管M的漏极与所述发光元件OLED的阳极电连接，所述驱动晶体管M的栅极与 扫描晶体管T0的漏极电连接，所述扫描晶体管T0的源极与所述数据线121电连接以接收所述数据电压Vdata，所述扫描晶体管T0的栅极与所述扫描线111电连接以接收所述扫描信号。所述储能电容C的第一端电连接于所述驱动晶体管M的栅极，所述储能电容C的第二端电连接于所述发光元件OLED的阴极。示例性地，当所述扫描信号为开启信号时，所述扫描晶体管T0导通，所述数据线121上的数据电压Vdata通过所述扫描晶体管T0对所述储能电容C进行充电，以将所述储能电容C的第一端的电压调节至所述数据电压Vdata，所述驱动晶体管M基于其栅极接收到的所述数据电压Vdata以及其源极接收到的所述驱动电压VDD驱动所述发光元件为OLED发光，此时，所述驱动晶体管M的栅源极电压Vgs＝Vg-Vs＝Vdata-VDD，流过所述发光元件OLED的电流Ids与所述驱动晶体管M的栅源极电压Vgs存在如下关系：
Ids＝(K/2)(Vgs-Vth) 2＝(K/2)(Vdata-VDD-Vth) 2
其中，K＝Cox×μ×W/L，Cox为单位面积栅极电容；μ为沟道电子运动的迁移率；W/L为所述驱动晶体管M的沟道的宽长比；Vth为所述驱动晶体管M的阈值电压。
由于所述发光元件OLED的亮度与流过其的电流Ids成正比关系，即与所述数据电压Vdata、所述驱动电压VDD以及所述驱动晶体管M的阈值电压Vth均相关。为了避免因不同的驱动晶体管M的阈值电压Vth的差异造成显示面板的显示亮度不均匀，现有的显示面板将所述像素驱动电路100'设计成具有阈值补偿功能的驱动电路(图中未示)，让驱动电路依次工作于复位阶段、数据写入阶段、发光阶段，在数据写入阶段对所述储能电容C充电将其第一端的电压调节至(Vdata+Vth)，此时，所述驱动晶体管M的栅源极电压Vgs＝Vg-Vs＝(Vdata+Vth)-VDD，那么，流过所述发光元件OLED的电流Ids与所述驱动晶体管M的栅源极电压Vgs之间满足如下等式关系：
Ids＝(K/2)(Vgs-Vth) 2＝(K/2)(Vdata-VDD) 2
由上述等式可知，所述发光元件OLED的亮度与所述数据电压Vdata、所述驱动电压VDD相关，而与所述驱动晶体管M的阈值电压Vth无关，如此，可以消除因不同的驱动晶体管M的阈值电压Vth的差异造成显示面板1的显示亮度不均匀的问题。然而，由于用于传输驱动电压VDD的电源电压线131本身存在线路阻抗，使得与所述驱动电压生成模块130距离不同的像素驱动电路100接收到的驱动电压VDD不同，如此，就引起与所述驱动电压生成模块130距离不同的发光元件OLED之间存在显示亮度差异，从而使得mura现象无法得到彻底地解决，并且随着显示面板1的尺寸的增大，mura现象越明显，严重影响用户的视觉体验。
请参阅图3，为了解决现有的像素驱动电路中因电源电压线131的线路阻抗造成显示面板1的显示亮度不均匀的问题，本申请提供一种新型的像素驱动电路100，所述像素驱动电路100用于驱动发光元件OLED发光。
所述像素驱动电路100包括储能电容C1、自举电容C2、驱动晶体管M、第一开关管T1、第二开关管T2、第三开关管T3、第四开关管T4、第五开关管T5以及第六开关管T6。其中，所述开关管T1～T6的控制端均与所述扫描信号生成模块110电连接，所述开关管T1～T6可以采用三极管或MOS管当中的至少一种。在本实施例中，所述开关管T1～T6和所述驱动晶体管M均为低电平导通的晶体管，例如PMOS管。在另一种实施例中，所述开关管T1～T6和所述驱动晶体管M均为高电平导通晶体管，例如NMOS管。可以理解的是，将所述开关管T1～T6均设计成同一类型的晶体管，有利于简化所述基板1000的制程，有利于降低加工难度、降低生产成本。当然，在其他实施例中，所述开关管T1～T6和所述驱动晶体管M也可以采用 不同类型的晶体管，此处不作限定。需要说明的是，本申请中的开关管T1～T6和所述驱动晶体管M可以采用非晶硅薄膜晶体管(a-Si TFT)，或者采用低温多晶硅薄膜晶体管(LTPS TFT)，又或者采用氧化物半导体薄膜晶体管(Oxide TFT)。其中，氧化物半导体薄膜晶体管的有源层采用氧化物半导体(Oxide)，比如铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)。示例性地，所述开关管T1～T6采用氧化物半导体薄膜晶体管，所述驱动晶体管M采用低温多晶硅型晶体管，由于低温多晶硅晶体管的迁移率较高，由此，可以提高所述驱动晶体管M的导通速度，进而能够提高像素驱动电路100的反应速度，从而提高所述显示面板1的显示效果。
为了更加清楚地介绍所述像素驱动电路100的电路结构及其工作原理，请一同参阅图4、图5a-图5c。
如图4所示，所述像素驱动电路100在一帧显示周期中依次工作于复位阶段(A阶段)、数据写入阶段(B阶段)以及发光阶段(C阶段)。
如图5a所示，所述像素驱动电路100包括预充电回路L1和电容复位回路L2。其中，所述电容复位回路L2包括依次串联的所述第一开关管T1、所述自举电容C2以及所述第二开关管T2，所述第一开关管T1的第一连接端用于接收所述驱动电压VDD，所述第一开关管T1的第二连接端与所述自举电容C2的第一端电连接。所述第二开关管T2的第一连接端与接地端电连接以接收零电位电压，所述第二开关管T2的第二连接端与所述自举电容C2的第二端电连接。所述预充电回路L1用于在所述复位阶段导通(即所述第一开关管T1、所述第二开关管T2均导通)，并接收所述驱动电压VDD对所述自举电容C2进行充电，以将所述自举电容C2的第一端的电压调节至所述驱动电压VDD，并将所述自举电容C2的第二端的电压复位至零电位，从而使得所述自举电容C2的第一端和第二端之间的电压差值达到所述驱动电压VDD。如此，所述自举电容C2可以通过所述第二开关管T2将上一帧显示周期中的残留的电荷释放到所述接地端，从而将所述自举电容C2的第二端第第一连接端的电压复位至零电位，以确保所述显示面板1显示效果的均匀性。
所述电容复位回路L2包括串联的所述储能电容C1和所述第六开关管T6，其中，所述第六开关管T6的第一连接端用于接收第一复位电压，所述第六开关管T6的第二连接端与所述储能电容C1的第一端电连接，所述储能电容C1的第一端还与所述驱动晶体管M的控制端(即栅极g)电连接，所述储能电容C1的第二端用于接收电压值恒定的第一电压V1。所述电容复位回路L2用于在所述复位阶段导通(即所述第六开关管T6导通)，并接收所述第一复位电压对所述储能电容C1的第一端的电压进行复位，即对所述储能电容C1进行充电，将其第一端的电压复位至所述第一复位电压。如此，可以消除上一帧显示周期的发光阶段残留的电荷对所述储能电容C1电压的影响，使得在每一帧显示周期中的数据写入阶段，所述储能电容C1的第一端的电压初始值均相等，即为所述第一复位电压，以确保所述显示面板1显示效果的均匀性。在本实施例中，所述储能电容C1的第二端接收到的所述第一电压V1为零电位电压，在其他实施例中，所述第一电压V1也可以是所述驱动电压VDD。
进一步地，所述发光元件OLED的第一端用于接收参考电压VSS，所述发光元件OLED的第二端与所述驱动晶体管M的第二连接端(即漏极d)电连接。
可选地，所述像素驱动电路100还包括发光元件复位回路L3，所述发光元件复位回路L3包括串联的第七开关管T7和所述发光元件OLED，其中，所述第七开关管T7的第一连接端用于接收第二复位电压，所述第七开关管T7的第一连接端与所述发光元件OLED的第二端电连接。所述发光元件复位回路L3用于在所述复位阶段导通(即所述第七开关管T7导通)， 将所述发光元件OLED的第二端的电压复位至所述第二复位电压。如此，可以消除上一帧显示周期的发光阶段残留的电荷对所述发光元件OLED的第二端的电压的影响，使得在每一帧显示周期中的发光阶段，所述发光元件OLED的第二端的电压初始值均相等，即为所述第二复位电压，以进一步提升所述显示面板1显示效果的均匀性。示例性地，所述第一复位电压的电压值和第二复位电压的电压值均等于复位电压Vint，其中，Vint<VSS，如此，在所述复位阶段中，所述第二复位电压不会引起所述发光元件OLED误发光。当然，在其他实施例中，所述第一复位电压的电压值和所述第二复位电压的电压值也可以不相等。
如图5b所示，所述像素驱动电路100还包括数据写入电路L4，所述数据写入回路L4包括依次串联的所述第三开关管T3、所述自举电容C2、所述驱动晶体管M所述第四开关管T4以及所述储能电容C1。具体地，所述第三开关管T3的第一连接端用于接收所述数据电压Vdata，所述第三开关管T3的第二连接端与所述自举电容C2的第二端电连接，所述自举电容C2的第一端还与所述驱动晶体管M的第一连接端(即源极s)电连接。所述第四开关管T4电连接于所述驱动晶体管M的第二连接端和所述储能电容C1的第一端之间。所述数据写入电路L4用于在所述数据写入阶段导通，以通过所述第三开关管T3的第一连接端接收所述数据电压Vdata并基于所述自举电容C2的自举效应对所述储能电容C1进行充电，以将所述驱动晶体管M的控制端的电压从所述第一复位电压调节至第二电压，其中，所述驱动晶体管M在其控制端的电压等于所述第二电压时进入临界导通状态，所述第二电压的电压值等于所述驱动电压VDD、所述数据电压以及所述驱动晶体管M的阈值电压之和。需要说明的是，在所述复位阶段，所述第三开关管T3可以通过所述第二开关管T2将上一帧显示周期中的残留的电荷释放到所述接地端，从而可以避免受到上一帧显示周期残余电荷的影响。
具体地，如前文所述，所述自举电容C2的第一端和第二端之间的电压差值为所述驱动电压VDD，所述自举电容C2接收到所述数据电压Vdata时其第二端从零电位变为Vdata，即所述自举电容C2的第二端的电位变化了Vdata，由于所述自举电容C2的自举效应，所述自举电容C2的第一端(即所述驱动晶体管M的源极电压Vs)的电位也随之变化至(Vdata+VDD)。在所述数据写入阶段中，对于所述驱动晶体管M而言，在对所述储能电容C1充电的起始时刻，所述驱动晶体管M的栅极电压Vg＝Vint，源极电压Vs＝Vdata+VDD，此时，其栅源极电压Vgs＝Vg-Vs＝Vint-Vdata<Vth，因此，所述驱动晶体管M导通。其中，Vth为所述驱动晶体管M的阈值电压，当Vgs<Vth时，所述驱动晶体管M导通，当Vgs>Vth时，所述驱动晶体管M截止。所述源极电压Vs通过导通的所述数据写入回路L4为所述储能电容C1充电，使得所述储能电容C1的第一端的电压不断上升。当所述储能电容C1的第一端的电压上升至Vg＝Vdata+VDD+Vth时，此时，Vgs＝(Vdata+VDD+Vth)-(Vdata+VDD)＝Vth，所述驱动晶体管M进入临界导通状态，所述储能电容C1的第一端的电压不再上升，其中，所述第二电压的电压值即等于(Vdata+VDD+Vth)。需要说明的是，所述自举电容C2的自举效应使得所述数据电压Vdata传输至所述储能电容C1的速度较快，进而可以缩减所述数据写入阶段的时长，降低一帧显示周期的时长，有利于提高所述显示面板1的刷新频率。
如图5c所示，所述像素驱动电路100还包括发光回路L5，所述发光回路L5包括依次串联的所述第一开关管T1、所述驱动晶体管M、所述第五开关管T5以及所述发光元件OLED。其中，所述第五开关管T5电连接于所述驱动晶体管M的第二连接端和所述发光元件OLED的第二端之间。所述发光回路L5用于在发光阶段导通，使得所述驱动晶体管M的第一连接端接收到所述驱动电压VDD，以驱动所述发光元件OLED发光。
具体地，对于所述驱动晶体管M而言，在所述发光阶段中，所述驱动晶体管M持续导通，由于所述第一开关管T1和所述第五开关管T5均工作在线性区，而所述驱动晶体管M工作在饱和区，因此流过所述发光元件OLED的电流的大小主要取决于所述驱动晶体管M的源极与漏极之间的电流Ids。根据开关管的工作特性，可知电流Ids与栅源极电压Vgs之间满足如下等式关系：
Ids＝(K/2)(Vgs-Vth) 2＝(K/2)(Vdata) 2
其中，K＝Cox×μ×W/L，Cox为单位面积栅极电容；μ为沟道电子运动的迁移率；W/L为所述驱动晶体管M的沟道的宽长比。
由上述公式可知，所述数据写入回路L3可以向所述驱动晶体管M提供补偿电压，使得流过所述发光元件OLED的电流Ids与所述驱动晶体管M的阈值电压Vth以及所述驱动电压VDD均无关，也就是说，只要保证所述数据电压Vdata的写入精度，即可精准地控制所述发光元件OLED的发光亮度。因此，本申请提供的所述像素驱动电路100不仅可以消除由于不同的像素驱动电路100中的驱动晶体管M的阈值电压不同而引起所述显示面板1的显示亮度不均的现象，还可以消除由于不同的像素驱动电路100接收到的驱动电压VDD不同而引起所述显示面板1的显示亮度不均的现象。此外，由于流经发光元件OLED的电流Ids与所述驱动电压VDD无关，根据发光元件OLED的第一端和第一端之间的电压差不变，其发光亮度不变的特性，可以适量降低所述驱动电压VDD的电压值，以降低所述像素驱动电路100的功耗。
如前文所述，在本实施例中，所述开关管T1～T7和所述驱动晶体管M均为低电平导通的晶体管。下面结合图3～图5c，对本申请提供的所述像素驱动电路100在一帧扫描周期内的工作流程进行详细介绍：
在本申请实施例中，所述第一开关管T1的控制端接收到的扫描信号为第一扫描信号SCAN1，所述第二开关管T2、所述第六开关管T6以及所述第七开关管T7的控制端接收到的扫描信号均为第二扫描信号SCAN2，所述第三开关管T3和所述第四开关管T4的控制端接收到的扫描信号均为第三扫描信号SCAN3，所述第五开关管T5的控制端接收到的扫描信号为第四扫描信号SCAN4。具有相同导通时序的开关管可以通过同一个扫描信号来控制，如此，可以简化所述基板1000的布线结构。当然，在其他实施例中，也可以为每一个开关管单独设置一个扫描信号来控制，此处不做限定。
在所述复位阶段(A阶段)，所述第一扫描信号SCAN1、所述第二扫描信号SCAN2均为低电平，所述第三扫描信号SCAN3、所述第四扫描信号SCAN4均为高电平。因此，所述开关管T1、T2、T6、T7均导通，所述开关管T3～T5均断开，从而使得所述预充电回路L1导通以将所述自举电容C2的第一端的电压调节至所述驱动电压VDD并将所述自举电容C2的第二端的电压复位至零电位，并使得所述储能电容复位回路L2导通以将所述储能电容C1的第一端的电压复位至所述第一复位电压，以及使得所述发光元件复位回路L3均导通将所述发光元件OLED的第二端的电压复位至所述第二复位电压，以及使得所述数据写入回路L4和所述发光回路L5断开。
在所述数据写入阶段(B阶段)，所述第三扫描信号SCAN3为低电平，所述第一扫描信号SCAN1、所述第二扫描信号SCAN2以及所述第四扫描信号SCAN4均为高电平。因此，所述开关管T3、T4以及所述驱动晶体管M均导通，所述开关管T1、T2、T5、T6、T7均断开，从而使得所述数据写入回路L4导通以将所述驱动晶体管M的控制端的电压从所述第一 复位电压调节至所述第二电压，并使得所述预充电回路L1、所述储能电容复位回路L2、所述发光元件复位回路L3以及所述发光回路L5均断开。
在所述发光阶段(C阶段)，所述第一扫描信号SCAN1、所述第四扫描信号SCAN4均为低电平，所述第二扫描信号SCAN2、所述第三扫描信号SCAN3均为高电平。因此，所述开关管T1、T5以及所述驱动晶体管M均导通，所述开关管T2、T3、T4、T6、T7均断开，从而使得所述发光回路L5导通以接收所述驱动电压VDD驱动所述发光元件OLED发光，并使得所述预充电回路L1、所述储能电容复位回路L2、所述发光元件复位回路L3以及所述数据写入回路L4均断开。
本申请提供的像素驱动电路100，在复位阶段通过预充电回路L1将自举电容C2的第一端的电压充电至驱动电压VDD，并在数据写入阶段通过自举电容C2的第二端接收数据电压Vdata并基于自举电容C2的自举效应对储能电容C1进行充电，以将驱动晶体管M的控制端的电压调节至电压值等于驱动电压VDD、数据电压Vdata以及驱动晶体管M的阈值电压Vth之和的第二电压，以及在发光阶段使得驱动晶体管M基于其控制端接收到的第二电压及其第一连接端接收到的驱动电压VDD驱动发光元件OLED发光，从而使得流过发光元件OLED的电流与驱动电压VDD以及驱动晶体管M的阈值电压Vth均无关，不仅可以消除由于不同的像素驱动电路100中驱动晶体管M的阈值电压不同而引起显示面板1的显示亮度不均的现象，还可以消除由于不同的像素驱动电路100接收到的驱动电压VDD不一致而引起显示面板1的显示亮度不均的现象。
尽管已经示出和描述了本申请的实施例，本领域的普通技术人员可以理解：在不脱离本申请的原理和宗旨的情况下可以对这些实施例进行多种变化、修改、替换和变型，本申请的范围由权利要求及其等同物限定。

Claims (16)

  1. 一种像素驱动电路，设置为驱动发光元件发光，所述发光元件的第一端设置为接收参考电压，所述像素驱动电路在一帧显示周期中依次工作于复位阶段、数据写入阶段以及发光阶段，其中，所述像素驱动电路包括：
    驱动晶体管，包括控制端、第一连接端和第二连接端，所述第一连接端设置为接收驱动电压，所述第二连接端与所述发光元件的第二端电连接；
    储能电容，所述储能电容的第一端与所述驱动晶体管的控制端电连接，所述储能电容的第二端设置为接收电压值恒定的第一电压；
    储能电容复位回路，设置为在复位阶段导通，并接收第一复位电压将所述储能电容的第一端的电压复位至所述第一复位电压；
    自举电容，所述自举电容的第一端与所述驱动晶体管的第一连接端电连接，所述自举电容的第二端在所述复位阶段接收零电位电压，所述自举电容的第二端在数据写入阶段接收数据电压；
    预充电回路，设置为在所述复位阶段导通，并接收所述驱动电压对所述自举电容进行充电，以将所述自举电容的第一端的电压调节至所述驱动电压，并将所述自举电容的第二端的电压复位至零电位，从而使得所述自举电容的第一端和第二端之间的电压差值达到所述驱动电压；
    数据写入回路，包括串联的所述自举电容、所述驱动晶体管以及所述储能电容；所述数据写入回路设置为在数据写入阶段导通，以通过所述自举电容的第二端接收所述数据电压并基于所述自举电容的自举效应对所述储能电容进行充电，以将所述驱动晶体管的控制端的电压从所述第一复位电压调节至第二电压，其中，所述驱动晶体管在其控制端的电压等于所述第二电压时进入临界导通状态，所述第二电压等于所述驱动电压、所述数据电压以及所述驱动晶体管的阈值电压之和；以及
    发光回路，包括串联的所述驱动晶体管和所述发光元件；所述发光回路设置为在发光阶段导通，使得所述驱动晶体管的第一连接端接收到所述驱动电压，以驱动所述发光元件发光。
  2. 如权利要求1所述的像素驱动电路，其中，所述预充电回路包括串联的第一开关管、所述自举电容以及第二开关管，其中：
    所述第一开关管的第一连接端设置为接收所述驱动电压，所述第一开关管的第二连接端与所述自举电容的第一端电连接；
    所述第二开关管的第一连接端与接地端电连接以接收所述零电位电压，所述第二开关管的第二连接端与所述自举电容的第二端电连接；
    在所述复位阶段，所述第一开关管基于其控制端接收到的扫描信号而导通，所述第二开关管基于其控制端接收到的扫描信号而导通，从而使得所述预充电回路导通。
  3. 如权利要求2所述的像素驱动电路，其中，所述数据写入回路包括串联的第三开关管、所述自举电容、所述驱动晶体管、第四开关管以及所述储能电容，其中：
    所述第三开关管的第一连接端设置为接收所述数据电压，所述第三开关管的第二连接端与所述自举电容的第二端电连接；
    所述第四开关管电连接于所述驱动晶体管的第二连接端和所述储能电容的第一端之间；
    在所述数据写入阶段，所述第三开关管和所述第四开关管均响应于各自控制端接收到的 扫描信号而导通，从而导通所述数据写入回路。
  4. 如权利要求3所述的像素驱动电路，其中，所述发光回路包括串联的所述第一开关管、所述驱动晶体管、第五开关管以及所述发光元件，其中：
    所述第一开关管的第二连接端与所述驱动晶体管的第一连接端电连接；
    所述第五开关管电连接于所述驱动晶体管的第二连接端和所述发光元件的第二端之间；
    在发光阶段，所述第一开关管基于其控制端接收到的扫描信号而导通，所述第五开关管基于其控制端接收到的扫描信号而导通，从而使得所述发光回路导通。
  5. 如权利要求4所述的像素驱动电路，其中，所述储能电容复位回路包括串联的储能电容和第六开关管，其中，所述第六开关管的第一连接端设置为接收所述第一复位电压，所述第六开关管的第二连接端与所述储能电容的第一端电连接；
    在所述复位阶段，所述第六开关管基于其控制端接收到的扫描信号而导通，从而使得所述储能电容复位回路导通。
  6. 如权利要求5所述的像素驱动电路，其中，所述像素驱动电路还包括发光元件复位回路，所述发光元件复位回路包括串联的第七开关管和所述发光元件，其中，所述第七开关管的第一连接端设置为接收第二复位电压，所述第七开关管的第一连接端与所述发光元件的第二端电连接；
    在所述复位阶段，所述第七开关管基于其控制端接收到的扫描信号而导通，从而使得所述发光元件复位回路导通，并将所述发光元件的第二端的电压复位至所述第二复位电压。
  7. 如权利要求6所述的像素驱动电路，其中，所述第一开关管、所述第二开关管、所述第三开关管、所述第四开关管、所述第五开关管、所述第六开关管、所述第七开关管以及所述驱动晶体管均为低电平导通的晶体管。
  8. 如权利要求7所述的像素驱动电路，其中，所述驱动晶体管为低温多晶硅薄膜晶体管；
    所述第一开关管、所述第二开关管、所述第三开关管、所述第四开关管、所述第五开关管、所述第六开关管、所述第七开关管均为氧化物半导体薄膜晶体管。
  9. 如权利要求1所述的像素驱动电路，其中，所述储能电容的第二端接收到的所述第一电压包括所述驱动电压或所述零电位电压。
  10. 一种显示面板，包括基板和若干个像素驱动电路，所述基板包括显示区，所述若干个像素驱动电路阵列排布在所述基板的显示区内；
    其中，所述像素驱动电路设置为驱动发光元件发光，所述发光元件的第一端设置为接收参考电压，所述像素驱动电路在一帧显示周期中依次工作于复位阶段、数据写入阶段以及发光阶段，所述像素驱动电路包括：
    驱动晶体管，包括控制端、第一连接端和第二连接端，所述第一连接端设置为接收驱动电压，所述第二连接端与所述发光元件的第二端电连接；
    储能电容，所述储能电容的第一端与所述驱动晶体管的控制端电连接，所述储能电容的第二端设置为接收电压值恒定的第一电压；
    储能电容复位回路，设置为在复位阶段导通，并接收第一复位电压将所述储能电容的第一端的电压复位至所述第一复位电压；
    自举电容，所述自举电容的第一端与所述驱动晶体管的第一连接端电连接，所述自举电容的第二端在所述复位阶段接收零电位电压，所述自举电容的第二端在数据写入阶段接收数据电压；
    预充电回路，设置为在所述复位阶段导通，并接收所述驱动电压对所述自举电容进行充电，以将所述自举电容的第一端的电压调节至所述驱动电压，并将所述自举电容的第二端的电压复位至零电位，从而使得所述自举电容的第一端和第二端之间的电压差值达到所述驱动电压；
    数据写入回路，包括串联的所述自举电容、所述驱动晶体管以及所述储能电容；所述数据写入回路设置为在数据写入阶段导通，以通过所述自举电容的第二端接收所述数据电压并基于所述自举电容的自举效应对所述储能电容进行充电，以将所述驱动晶体管的控制端的电压从所述第一复位电压调节至第二电压，其中，所述驱动晶体管在其控制端的电压等于所述第二电压时进入临界导通状态，所述第二电压等于所述驱动电压、所述数据电压以及所述驱动晶体管的阈值电压之和；以及
    发光回路，包括串联的所述驱动晶体管和所述发光元件；所述发光回路设置为在发光阶段导通，使得所述驱动晶体管的第一连接端接收到所述驱动电压，以驱动所述发光元件发光。
  11. 如权利要求10所述的显示面板，其中，所述预充电回路包括串联的第一开关管、所述自举电容以及第二开关管，其中：
    所述第一开关管的第一连接端设置为接收所述驱动电压，所述第一开关管的第二连接端与所述自举电容的第一端电连接；
    所述第二开关管的第一连接端与接地端电连接以接收所述零电位电压，所述第二开关管的第二连接端与所述自举电容的第二端电连接；
    在所述复位阶段，所述第一开关管基于其控制端接收到的扫描信号而导通，所述第二开关管基于其控制端接收到的扫描信号而导通，从而使得所述预充电回路导通。
  12. 如权利要求11所述的显示面板，其中，所述数据写入回路包括串联的第三开关管、所述自举电容、所述驱动晶体管、第四开关管以及所述储能电容，其中：
    所述第三开关管的第一连接端设置为接收所述数据电压，所述第三开关管的第二连接端与所述自举电容的第二端电连接；
    所述第四开关管电连接于所述驱动晶体管的第二连接端和所述储能电容的第一端之间；
    在所述数据写入阶段，所述第三开关管和所述第四开关管均响应于各自控制端接收到的扫描信号而导通，从而导通所述数据写入回路。
  13. 如权利要求12所述的显示面板，其中，所述发光回路包括串联的所述第一开关管、所述驱动晶体管、第五开关管以及所述发光元件，其中：
    所述第一开关管的第二连接端与所述驱动晶体管的第一连接端电连接；
    所述第五开关管电连接于所述驱动晶体管的第二连接端和所述发光元件的第二端之间；
    在发光阶段，所述第一开关管基于其控制端接收到的扫描信号而导通，所述第五开关管基于其控制端接收到的扫描信号而导通，从而使得所述发光回路导通。
  14. 如权利要求13所述的显示面板，其中，所述储能电容复位回路包括串联的储能电容和第六开关管，其中，所述第六开关管的第一连接端设置为接收所述第一复位电压，所述第六开关管的第二连接端与所述储能电容的第一端电连接；
    在所述复位阶段，所述第六开关管基于其控制端接收到的扫描信号而导通，从而使得所述储能电容复位回路导通。
  15. 如权利要求14所述的显示面板，其中，所述像素驱动电路还包括发光元件复位回路，所述发光元件复位回路包括串联的第七开关管和所述发光元件，其中，所述第七开关管的第 一连接端设置为接收第二复位电压，所述第七开关管的第一连接端与所述发光元件的第二端电连接；
    在所述复位阶段，所述第七开关管基于其控制端接收到的扫描信号而导通，从而使得所述发光元件复位回路导通，并将所述发光元件的第二端的电压复位至所述第二复位电压。
  16. 如权利要求15所述的显示面板，其中，所述第一开关管、所述第二开关管、所述第三开关管、所述第四开关管、所述第五开关管、所述第六开关管、所述第七开关管以及所述驱动晶体管均为低电平导通的晶体管。
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