WO2021203497A1 - 像素驱动电路和显示面板 - Google Patents

像素驱动电路和显示面板 Download PDF

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Publication number
WO2021203497A1
WO2021203497A1 PCT/CN2020/087697 CN2020087697W WO2021203497A1 WO 2021203497 A1 WO2021203497 A1 WO 2021203497A1 CN 2020087697 W CN2020087697 W CN 2020087697W WO 2021203497 A1 WO2021203497 A1 WO 2021203497A1
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Prior art keywords
thin film
film transistor
gate
switching thin
double
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PCT/CN2020/087697
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English (en)
French (fr)
Inventor
张晓东
宋尚哲
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Priority to US16/766,742 priority Critical patent/US11455960B2/en
Publication of WO2021203497A1 publication Critical patent/WO2021203497A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • This application relates to the field of display technology, and in particular to a pixel drive circuit and a display panel.
  • OLED Organic Light Emitting Diode
  • LCD Liquid Crystal Display
  • OLED Organic Light Emitting Diode
  • LCD Liquid Crystal Display
  • Micro-LED of inorganic materials has attracted wide attention due to its advantages such as high contrast and high stability of inorganic materials. It is considered to be a new display technology comparable to OLED in the future.
  • FIG. 1(a) shows the traditional Diode-Connect (diode structure) type internal compensation circuit structure, in which the T1 thin film transistor is a driving thin film transistor, the T1 thin film transistor is an N-type thin film transistor (NTFT), and the T2 thin film transistor is a switching film Transistor: The source and drain of the T2 thin film transistor are respectively connected to the gate terminal (G) and the drain terminal (D) of the T1 thin film transistor. When the T2 thin film transistor is turned on, the T1 thin film transistor forms a diode structure.
  • NTFT N-type thin film transistor
  • the present application provides a pixel driving circuit and a display panel, combining the gate control principle of the double-gate device and the threshold voltage detection principle of the diode structure, which can realize compensation when the threshold voltage of the driving thin film transistor is positive and negative.
  • the traditional Diode-Connect type internal compensation circuit can only compensate for the single direction threshold voltage drift, which improves the accuracy and uniformity of the screen display.
  • the present application provides a pixel driving circuit, including a light emitting module and a compensation driving module:
  • the light-emitting module is used to connect to a low-potential first power supply voltage in the initialization phase, a threshold voltage compensation phase, and a data writing phase; and to connect to a high-potential first power supply voltage in the light-emitting phase;
  • the compensation driving module is electrically connected to the light-emitting module, and includes a dual gate driving thin film transistor, which is used to connect a high potential signal during the initialization phase to turn on the dual gate driving thin film transistor and connect the high Potential of the second power supply voltage to charge the bottom gate of the double-gate driving thin film transistor to adjust the threshold voltage of the double-gate driving thin film transistor to the initial value; in the threshold voltage compensation stage, connect A reference voltage is input to turn on the double-gate driving thin film transistor, and a second power supply voltage with a low potential is connected to discharge the bottom gate of the double-gate driving thin film transistor to turn on the double-gate driving thin film transistor.
  • the threshold voltage of the driving thin film transistor is compensated to be equal to the voltage difference between the reference voltage and the low-level second power supply voltage; in the data writing phase, a data signal and a low-level second power supply voltage are connected ; In the light-emitting stage, the double-gate drive thin film transistor is turned on, and a low-potential second power supply voltage is connected to control the light-emitting module to emit light.
  • the compensation driving module further includes a first switching thin film transistor and a second switching thin film transistor;
  • the compensation driving module is also used to turn on the first switching thin film transistor in the initialization phase to access the high-potential signal, and turn on the second switching thin film transistor to make the high-potential
  • the second power supply voltage charges the bottom gate of the dual-gate driving thin film transistor; during the threshold voltage compensation stage, the first switching thin film transistor is turned on to access the reference voltage and turn on the The second switching thin film transistor to discharge the bottom gate of the double-gate driving thin film transistor; the first switching thin film transistor and the second switching thin film transistor are turned off during the data writing phase to connect Input the data signal; turn off the first switching thin film transistor and the second switching thin film transistor during the light-emitting phase to drive the light-emitting module to emit light.
  • the source of the double-gate driving thin film transistor is connected to the second power supply voltage, and the drain is electrically connected to the light-emitting module;
  • the gate of the first switching thin film transistor is connected to a first control signal, its source is connected to the high potential signal during the initialization phase, and the reference voltage is connected during the threshold voltage compensation phase, and its drain
  • the electrode is electrically connected to the top gate of the dual-gate driving thin film transistor
  • the gate of the second switching thin film transistor is connected to the first control signal, its source is electrically connected to the drain of the dual gate driving thin film transistor, and its drain is connected to the dual gate driving thin film transistor.
  • the bottom gate is electrically connected.
  • the compensation driving module further includes a first capacitor and a second capacitor;
  • One end of the first capacitor is electrically connected to the top gate of the dual gate driving thin film transistor, and the other end is electrically connected to the source of the dual gate driving thin film transistor for storing the dual gate driving thin film The potential of the top gate of the transistor;
  • One end of the second capacitor is electrically connected to the bottom gate of the double-gate driving thin film transistor, and the other end is grounded to store the potential of the bottom gate of the double-gate driving thin film transistor.
  • the reference voltage is a positive voltage or a negative voltage.
  • the double-gate driving thin film transistor includes any of an N-type oxide thin film transistor, an N-type low-temperature polysilicon thin film transistor, an N-type amorphous silicon thin film transistor, and an N-type organic thin film transistor. A sort of.
  • the pixel driving circuit further includes a data writing module electrically connected to the compensation driving module;
  • the data writing module is used for acquiring the data signal in the data writing stage, and outputting the data signal to the compensation driving module.
  • the data writing module includes a third switching thin film transistor; the gate of the third switching thin film transistor is connected to the second control signal, and the source of the third switching thin film transistor is connected to the data signal , Its drain is electrically connected to the top gate of the double-gate driving thin film transistor.
  • the first switching thin film transistor, the second switching thin film transistor, and the third switching thin film transistor include any one of an N-type thin film transistor and a P-type thin film transistor.
  • the pixel driving circuit further includes a data writing module electrically connected to the compensation driving module;
  • the data writing module is used for outputting a pre-stored data signal to the compensation driving module in the data writing stage, and acquiring and storing the data signal required for the next frame in the light emitting stage.
  • the data writing module includes a third switching thin film transistor, a fourth switching thin film transistor, and a third capacitor;
  • the data writing module is used for turning off the third switching thin film transistor, turning on the fourth switching thin film transistor during the data writing phase, and outputting the data signal pre-stored in the third capacitor to The top gate of the double-gate driving thin film transistor; in the light-emitting phase, the fourth switching thin film transistor is turned off, and the third switching thin film transistor is turned on to obtain the data signal of the next frame and store it in The third capacitor.
  • the gate of the third switching thin film transistor is connected to the second control signal, the source is connected to the data signal, and the drain is connected to the fourth switching thin film transistor.
  • the source is electrically connected;
  • the gate of the fourth switching thin film transistor is connected to a third control signal, and the drain is electrically connected to the top gate of the double-gate driving thin film transistor;
  • One end of the third capacitor is electrically connected to the source of the fourth switch thin film transistor, and the other end is grounded.
  • the first switching thin film transistor, the second switching thin film transistor, the third switching thin film transistor, and the fourth switching thin film transistor include an N-type thin film transistor and a P-type thin film transistor. Any of thin film transistors.
  • the light-emitting module includes an OLED light-emitting device or a Micro-LED light-emitting device.
  • the present application also provides a display panel, including a signal control unit and a plurality of pixel units, each pixel unit includes the above-mentioned pixel drive circuit; the signal control unit is electrically connected to each of the pixel drive circuits , To provide a control signal for the pixel drive circuit.
  • the compensation driving module further includes a first switching thin film transistor and a second switching thin film transistor;
  • the compensation driving module is also used to turn on the first switching thin film transistor in the initialization phase to access the high-potential signal, and turn on the second switching thin film transistor to make the high-potential
  • the second power supply voltage charges the bottom gate of the dual-gate driving thin film transistor; during the threshold voltage compensation stage, the first switching thin film transistor is turned on to access the reference voltage and turn on the The second switching thin film transistor to discharge the bottom gate of the double-gate driving thin film transistor; the first switching thin film transistor and the second switching thin film transistor are turned off during the data writing phase to connect Input the data signal; turn off the first switching thin film transistor and the second switching thin film transistor during the light-emitting phase to drive the light-emitting module to emit light.
  • the source of the dual gate driving thin film transistor is connected to the second power supply voltage, and the drain is electrically connected to the light-emitting module;
  • the gate of the first switching thin film transistor is connected to a first control signal, its source is connected to the high potential signal during the initialization phase, and the reference voltage is connected during the threshold voltage compensation phase, and its drain
  • the electrode is electrically connected to the top gate of the dual-gate driving thin film transistor
  • the gate of the second switching thin film transistor is connected to the first control signal, its source is electrically connected to the drain of the dual gate driving thin film transistor, and its drain is connected to the dual gate driving thin film transistor.
  • the bottom gate is electrically connected.
  • the compensation driving module further includes a first capacitor and a second capacitor
  • One end of the first capacitor is electrically connected to the top gate of the dual gate driving thin film transistor, and the other end is electrically connected to the source of the dual gate driving thin film transistor for storing the dual gate driving thin film The potential of the top gate of the transistor;
  • One end of the second capacitor is electrically connected to the bottom gate of the double-gate driving thin film transistor, and the other end is grounded to store the potential of the bottom gate of the double-gate driving thin film transistor.
  • the pixel driving circuit further includes a data writing module electrically connected to the compensation driving module;
  • the data writing module is used to obtain the data signal in the data writing stage and output the data signal to the compensation driving module; or, output to the compensation driving module in the data writing stage Pre-stored data signals, and acquire and store the data signals needed for the next frame in the light-emitting stage.
  • the reference voltage is a positive voltage or a negative voltage.
  • the driving thin film crystal in the compensation driving module adopts a double-gate structure, that is, a double-gate driving thin film transistor.
  • the double-gate driving thin film The potential of the bottom gate of the transistor can dynamically adjust its threshold voltage.
  • the bottom gate of the double-gate drive thin film transistor is charged to a high potential to adjust its threshold voltage to a lower initial value; then, the diode structure is combined
  • the threshold voltage compensation stage the bottom gate and drain of the double-gate driving thin film transistor are short-circuited to form a diode structure, so that the high potential of the bottom gate gradually decreases until the double-gate driving thin film transistor is turned off.
  • Make the threshold voltage equal to the voltage difference between the top gate and the source. Since the potential of the top gate is equal to the reference voltage at this stage and the potential of the source is equal to the second power supply voltage, the compensated threshold voltage is equal to the reference voltage of the compensation stage.
  • Fig. 1(a) is a schematic diagram of an exemplary internal compensation circuit with a diode structure.
  • Fig. 1(b) is a schematic diagram of the change of the voltage difference between the gate terminal and the source terminal of the T1 thin film transistor when the internal compensation circuit structure in Fig. 1(a) is used to detect the positive threshold voltage.
  • Fig. 1(c) is a schematic diagram of the change of the voltage difference between the gate terminal and the source terminal of the T1 thin film transistor when the internal compensation circuit structure in Fig. 1(a) is used to detect the negative threshold voltage.
  • FIG. 2 is a schematic block diagram of the structure of a pixel driving circuit provided by an embodiment of the application.
  • FIG. 3 is a circuit diagram of a pixel driving circuit with a 4T2C architecture provided by an embodiment of the application.
  • FIG. 4 is a driving timing diagram of the pixel driving circuit provided in FIG. 3.
  • FIG. 5 is a circuit diagram of a pixel driving circuit with a 5T3C architecture provided by an embodiment of the application.
  • FIG. 6 is a driving timing diagram of the pixel driving circuit provided in FIG. 5.
  • FIG. 7 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • an embodiment of the present application provides a pixel driving circuit 1 with a 4T2C architecture.
  • the pixel driving circuit 1 includes a light emitting module 2, a compensation driving module 3, and a data writing module 4, and the pixel driving circuit 1
  • the driving sequence includes an initialization phase, a threshold voltage compensation phase, a data writing phase, and a light-emitting phase in sequence.
  • the light-emitting module 2 is used to connect to the low-level first power supply voltage EVDD during the initialization phase, the threshold voltage compensation phase, and the data writing phase to maintain the non-lighting state; and, during the light-emitting phase, connect to the high-level first power supply voltage EVDD , In order to achieve luminescence.
  • the light-emitting module 2 includes an OLED light-emitting device or a Micro-LED light-emitting device, and the anode terminal of the light-emitting device is connected to the first power supply voltage EVDD, and the cathode terminal is electrically connected with the compensation driving module 3.
  • the data writing module 4 is electrically connected to the compensation driving module 3 for obtaining the data signal Data during the data writing stage, and outputting the data signal Data to the compensation driving module 3.
  • the compensation driving module 3 is also electrically connected to the light emitting module 2.
  • the compensation driving module 3 includes a double gate driving thin film transistor T10, which is used to connect a high potential signal during the initialization phase to turn on the double gate driving thin film transistor T10, and is connected to The second power supply voltage VSS with a high potential is input to charge the bottom gate bg of the double-gate driving thin film transistor T10, and adjust the threshold voltage Vth of the double-gate driving thin film transistor T10 to the initial value; in the threshold voltage compensation stage, Connect the reference voltage Vref (greater than the aforementioned initial value and less than the aforementioned high-potential signal) to turn on the double-gate driving thin film transistor T10, and connect to the low-potential second power supply voltage VSS to connect the double-gate driving thin film transistor
  • the bottom gate bg of T10 is discharged, and the threshold voltage Vth of the double-gate driving thin film transistor T10 is compensated to be equal to the voltage difference (Vref-VSS) between the reference voltage
  • the top gate tg of the dual-gate driving thin film transistor T10 is connected to a high potential signal during the initialization phase, and is connected to the reference voltage Vref during the threshold voltage compensation phase, its source is connected to the second power supply voltage VSS, and its drain is connected to the second power supply voltage VSS. It is electrically connected to the cathode of the light-emitting device in the light-emitting module 2.
  • the double gate driving thin film transistor T10 includes any one of an N-type oxide thin film transistor, an N-type low-temperature polysilicon thin film transistor, an N-type amorphous silicon thin film transistor, and an N-type organic thin film transistor.
  • the dual gate driving thin film transistor T10 since the dual gate driving thin film transistor T10 has a dual gate structure, its threshold voltage Vth is not a fixed value, and the threshold voltage Vth has a negative linear relationship with the potential of the bottom gate bg. Specifically, the dual gate driving thin film The threshold voltage Vth of the transistor T10 decreases linearly as the potential difference (Vbgs) between the bottom gate bg and its source increases, and for dual-gate drive thin film transistors T10 of different sizes, the threshold voltage Vth and Vbgs The slope of the linear relationship between the two is the same, that is, the dual gate driving thin film transistors T10 of different sizes are all within the protection scope of the present application.
  • the bottom gate bg of the double gate driving thin film transistor T10 is charged to a high potential, so that the threshold voltage Vth drops to a lower initial value; in the threshold voltage compensation phase, the double gate driving thin film transistor T10 The bottom gate bg is discharged. As the high potential of the bottom gate bg gradually decreases, the threshold voltage Vth gradually increases until it is equal to the voltage difference between the top gate tg and the source of the double gate driving thin film transistor T10 Vtgs, at this time, the dual-gate driving thin film transistor T10 is turned off, thereby completing the threshold voltage compensation.
  • the threshold voltage after compensation is obtained by setting the reference voltage Vref.
  • the reference voltage Vref is a positive voltage or a negative voltage. It should be noted that the selection of the reference voltage Vref value depends on the Vth distribution before the display panel is not initialized, and is not a fixed value. Generally, the threshold voltage Vth of the oxide TFT is about 0V before being initialized. Since Vth will drift between positive and negative, for the oxide TFT, the reference voltage Vref selected in the threshold voltage compensation stage is a negative value. Of course, for TFTs whose threshold voltage Vth is greater than 0V before being initialized, the reference voltage Vref can be set to a positive value. Therefore, the pixel driving circuit 1 provided by the embodiment of the present application can compensate for the case where the threshold voltage Vth is a positive value, and can also compensate for the case where the threshold voltage Vth is a negative value.
  • the compensation driving module 3 further includes a first switching thin film transistor T11, a second switching thin film transistor T12, a first capacitor C1, and a second capacitor C2.
  • the gate of the first switching thin film transistor T11 is connected to the first control signal Sense, its source is connected to a high potential signal during the initialization phase, and the reference voltage Vref is connected to the threshold voltage Vth compensation phase, and its drain is driven by a double gate.
  • the top gate tg of the thin film transistor T10 is electrically connected. It should be noted that the reference voltage Vref shown in FIG. 2 and FIG. 3 can also be replaced with the above-mentioned high potential signal.
  • the gate of the second switching thin film transistor T12 is also connected to the first control signal Sense, its source is electrically connected to the drain of the dual gate driving thin film transistor T10, and its drain is connected to the bottom gate of the dual gate driving thin film transistor T10 bg electrical connection.
  • One end of the first capacitor C1 is electrically connected to the top gate tg of the double-gate driving thin film transistor T10, and the other end is electrically connected to the source of the double-gate driving thin film transistor T10 to store the top of the double-gate driving thin film transistor T10.
  • the potential of the gate tg; one end of the second capacitor C2 is electrically connected to the bottom gate bg of the double gate driving thin film transistor T10, and the other end is grounded to store the potential of the bottom gate bg of the double gate driving thin film transistor T10.
  • the compensation driving module 3 is also used to turn on the first switching thin film transistor T11 through the first control signal Sense in the initialization phase, so that the top gate tg of the double gate driving thin film transistor T10 is connected to a high potential signal and turned on.
  • the second switching thin film transistor T12 is turned on by the first control signal Sense, so that the bottom gate bg and the drain of the double-gate driving thin film transistor T10 are short-circuited to form a diode structure, so that the high-potential second power supply voltage VSS is sequentially
  • the bottom gate bg of the double gate driving thin film transistor T10 is charged through the double gate driving thin film transistor T10 and the second switching thin film transistor T12 to realize the initialization of the threshold voltage of the double gate driving thin film transistor T10; and, In the threshold voltage compensation stage, the first switching thin film transistor T11 is turned on by the first control signal Sense, so that the top gate tg of the dual-gate driving thin film transistor T10 is connected to the reference voltage Vref, and the second control signal Sense is turned on.
  • the switching thin film transistor T12 keeps the bottom gate bg and drain of the double gate driving thin film transistor T10 in a short-circuited state.
  • the source of the double gate driving thin film transistor T10 is connected to the low-potential second power supply voltage VSS, so that The bottom gate bg of the double gate driving thin film transistor T10 is discharged to realize the compensation of the threshold voltage of the double gate driving thin film transistor T10;
  • the first switching thin film transistor T11 is turned off by the first control signal Sense during the data writing phase
  • the second switching thin film transistor T12 to access the data signal (Data) and store it in the first capacitor C1; and, during the light-emitting phase, the first switching thin film transistor T11 and the second switching thin film transistor T12 are turned off by the first control signal Sense ,
  • the data signal (Data) stored by the first capacitor C1 turns on the double-gate driving thin film transistor T10 to drive the light-emitting module 2 to emit light.
  • the data writing module 4 includes a third switching thin film transistor T13; the gate of the third switching thin film transistor T13 is connected to the second control signal Scan, its source is connected to the data signal Data, and its drain is driven by a double gate.
  • the top gate tg of the thin film transistor T10 is electrically connected.
  • the data writing module 4 is specifically configured to turn off the third switching thin film transistor T13 through the second control signal Scan during the initialization phase, the threshold voltage compensation phase, and the light emitting phase; and during the data writing phase, turn on the third switching thin film transistor T13 through the second control signal Scan.
  • the thin film transistor T13 is switched third to obtain the data signal Data and input the data signal Data to the top gate tg of the double gate driving thin film transistor T10.
  • the first switching thin film transistor T11, the second switching thin film transistor T12, and the third switching thin film transistor T13 may be either N-type thin film transistors or P-type thin film transistors; according to the different material types, the first switching thin film transistors T11, the second switching thin film transistor T12 and the third switching thin film transistor T13 include any one of an oxide thin film transistor, a low temperature polysilicon thin film transistor, an amorphous silicon thin film transistor, and an organic thin film transistor; and the first switching thin film transistor T11, the first switching thin film transistor The two-switch thin-film transistor T12 and the third-switch thin-film transistor T13 may have a single-gate structure or a double-gate structure, which is not limited here.
  • the first switching thin film transistor T11, the second switching thin film transistor T12, and the third switching thin film transistor T13 are N-type thin film transistors, they are turned on by a high-potential control signal, and turned off by a low-potential control signal.
  • the first switching thin film transistor T11, the second switching thin film transistor T12, and the third switching thin film transistor T13 are P-type thin film transistors, the first switching thin film transistor T11, the second switching thin film transistor T12, and the third switching thin film transistor T13 are They are respectively turned on by a low-level control signal, and turned off by a high-level control signal.
  • the driving timing of the pixel driving circuit 1 is shown in FIG. 4, and the driving timing of the pixel driving circuit 1 includes an initialization phase 1, a threshold voltage compensation phase 2, a data writing phase 3, and a light-emitting phase 4;
  • the high potential signal in the initialization stage 1 and the reference voltage Vref in the threshold compensation stage 2 are both connected from the source of the first switching thin film transistor T11, in the timing diagram, the high potential signal and the reference voltage Vref adopt the same
  • a potential line Vref indicates that the high voltage signal can also be considered as the initial reference voltage, and the reference voltage Vref is the specific reference voltage in the compensation phase.
  • the driving steps of the pixel driving circuit 1 are as follows:
  • the first power supply voltage EVDD is at a low potential
  • the second power supply voltage VSS is at a high potential
  • the first control signal Sense is at a high potential
  • the first switching thin film transistor T11 and the second switching thin film transistor T12 are turned on
  • the second control signal Scan is at a low potential
  • the third switching thin film transistor T13 is turned off
  • the top gate tg of the double gate driving thin film transistor T10 is connected to a high potential signal, so that the double gate driving thin film transistor T10 is turned on, and the bottom gate bg is connected to the drain
  • the poles are short-connected to form a diode structure
  • the high-potential second power supply voltage VSS charges the bottom gate bg of the double-gate driving thin film transistor T10 to a high potential.
  • the threshold voltage Vth Adjusted to a smaller initial value the second capacitor C2 stores the high potential of the bottom gate bg.
  • Data writing stage 3 The first power supply voltage EVDD is at a low potential, and the second power supply voltage VSS is at a low potential; the first control signal Sense is at a low potential, and the first switching thin film transistor T11 and the second switching thin film transistor T12 are disconnected; The second control signal Scan is at high potential (Scan is turned on row by row), the third switching thin film transistor T13 is turned on, and the data signal Data is written from the data line and output to the top of the double gate driving thin film transistor T10 through the third switching thin film transistor T13.
  • the gate tg is stored in the first capacitor C1.
  • Light-emitting stage 4 the first power supply voltage EVDD is at a high potential, the second power supply voltage VSS is at a low potential; the first control signal Sense is at a low potential, the first switching thin film transistor T11 and the second switching thin film transistor T12 are disconnected; the second control The signal Scan is at a low potential, the third switching thin film transistor T13 is turned off, and the data signal Data stored in the first capacitor C1 controls the double gate driving thin film transistor T10 to turn on to drive the light emitting module 2 to emit light.
  • the formula for the current flowing through the light-emitting device during the light-emitting stage is:
  • K is a constant value coefficient related to the characteristics of the dual gate driving thin film transistor T10
  • ⁇ is the efficiency of data signal Data transmission to the top gate tg of the dual gate driving thin film transistor T10
  • Vref is the reference for the threshold voltage compensation stage Voltage.
  • the current value flowing through the dual gate driving thin film transistor T10 and the light emitting module 2 has nothing to do with the threshold voltage Vth of the dual gate driving thin film transistor T10, which compensates for the threshold voltage drift of the dual gate driving thin film transistor T10. Conducive to the uniformity and accuracy of the display panel.
  • the high potential of the top gate tg terminal of the double-gate driving thin film transistor T10 The signal drops earlier than the second power supply voltage VSS to turn off the dual-gate driving thin film transistor T10 and maintain the initialization effect; and, to ensure that the compensated threshold voltage is not affected, the reference voltage Vref is delayed until the data writing stage 3 rises to high The potential signal is prevented from changing simultaneously with the first control signal Sense at time t2.
  • the driving thin film crystal in the compensation driving module 3 adopts a double-gate structure, that is, the double-gate driving thin-film transistor T10.
  • the potential of the bottom gate bg of the double-gate driving thin-film transistor T10 is The threshold voltage can be adjusted linearly and dynamically.
  • the threshold voltage Vth is adjusted to a lower initial value; then, combined with the threshold voltage detection of the diode structure.
  • the principle is that in the threshold voltage compensation stage, the bottom gate bg and drain of the dual-gate driving thin film transistor T10 are short-circuited to form a diode structure, so that the high potential of the bottom gate bg gradually decreases until the dual-gate driving thin film transistor T10 is turned off.
  • the threshold voltage Vth is equal to the voltage difference between the top gate tg and the source.
  • the compensated threshold voltage is equal to The difference between the reference voltage Vref and the second power supply voltage VSS in the compensation stage, so as to realize the compensation of the threshold voltage of the dual-gate driving thin film transistor T10; in addition, regardless of whether the threshold voltage Vth of the dual-gate driving thin film transistor T10 is positive before initialization Whether the value is negative or negative, the threshold voltage Vth of the dual-gate driving thin film transistor T10 can be adjusted to the initial value by increasing the potential of the bottom gate bg of the double-gate driving thin film transistor T10, and then the compensation is performed; therefore, the pixel driving circuit 1 provided by the present application It can realize the compensation of the threshold voltage Vth in positive and negative conditions, effectively broaden the compensation range of the threshold voltage Vth, and solve the problem that the traditional diode structure internal compensation circuit can only compensate for the threshold voltage drift in a single direction, which is beneficial to
  • the embodiment of the present application also provides a pixel driving circuit 1 with a 5T3C architecture.
  • the difference from the above-mentioned embodiment is that the data writing module 4 is used to send data to the compensation driving module during the data writing stage.
  • the data writing module 4 includes a third switch thin film transistor T13 and a fourth switch thin film transistor T14 And the third capacitor C3;
  • the gate of the third switching thin film transistor T13 is connected to the second control signal Scan, its source is connected to the data signal Data, and its drain is electrically connected to the source of the fourth switching thin film transistor T14;
  • fourth The gate of the switching thin film transistor T14 is connected to the third control signal Merge, and its drain is electrically connected to the top gate tg of the double-gate driving thin film transistor T10; one end of the third capacitor C3 is connected to the source of the fourth switching thin film transistor T14 It is electrically connected, and the other end is grounded for pre-storing the data signal Data in the previous frame.
  • the data writing module 4 is specifically used to turn off the third switching thin film transistor T13 and the fourth switching thin film transistor T14 during the initialization phase and the threshold voltage compensation phase; during the data writing phase, the third switching thin film transistor T13 is turned off and turned on
  • the fourth switching thin film transistor T14 outputs the data signal Data pre-stored in the third capacitor C3 to the top gate tg of the double-gate driving thin film transistor T10; in the light-emitting phase, the fourth switching thin film transistor T14 is turned off, and the fourth switching thin film transistor T14 is turned on.
  • the thin film transistor T13 is three-switched to obtain the data signal Data of the next frame and store it in the third capacitor C3.
  • the first switching thin film transistor T11, the second switching thin film transistor T12, the third switching thin film transistor T13, and the fourth switching thin film transistor T14 can be either N-type thin film transistors or P-type thin film transistors; Different, the first switching thin film transistor T11, the second switching thin film transistor T12, the third switching thin film transistor T13, and the fourth switching thin film transistor T14 include oxide thin film transistors, low temperature polysilicon thin film transistors, amorphous silicon thin film transistors, and organic thin film transistors. In addition, the first switching thin film transistor T11, the second switching thin film transistor T12, the third switching thin film transistor T13, and the fourth switching thin film transistor T14 may have a single-gate structure or a double-gate structure, where No restrictions.
  • the source position of the first switching thin film transistor T11 in FIG. 5 shows the reference voltage Vref, which can also be replaced by the above-mentioned high potential signal.
  • the driving timing of the pixel driving circuit 1 is shown in FIG. 6, and the driving timing of the pixel driving circuit 1 includes an initialization phase 1, a threshold voltage compensation phase 2, a data writing phase 3, and a light-emitting phase 4;
  • the high potential signal in the initialization stage 1 and the reference voltage Vref in the threshold compensation stage 2 are both connected from the source of the first switching thin film transistor T11, in the timing diagram, the high potential signal and the reference voltage Vref adopt the same
  • a potential line Vref indicates that the high voltage signal can also be considered as the initial reference voltage, and the reference voltage Vref is the specific reference voltage in the compensation phase.
  • the driving method of the pixel driving circuit 1 is as follows:
  • the first power supply voltage EVDD is at a low potential
  • the second power supply voltage VSS is at a high potential
  • the first control signal Sense is at a high potential
  • the first switching thin film transistor T11 and the second switching thin film transistor T12 are turned on
  • the second control signal Scan is a low potential
  • the third switching thin film transistor T13 is turned off
  • the third control signal Merge is a low potential
  • the fourth switching thin film transistor T14 is turned off
  • the top gate tg of the double-gate driving thin film transistor T10 is connected to a high potential signal
  • the double-gate driving thin film transistor T10 is turned on, and the bottom gate bg and the drain are short-circuited to form a diode structure
  • the high-potential second power supply voltage VSS charges the bottom gate bg of the double-gate driving thin film transistor T10 to a high potential
  • the threshold voltage Vth is adjusted to a smaller initial value
  • Threshold voltage compensation stage 2 the first power supply voltage EVDD is at a low potential, and the second power supply voltage VSS is at a low potential; the first control signal Sense is at a high potential, and the first switching thin film transistor T11 and the second switching thin film transistor T12 are turned on; The second control signal Scan is at a low level, and the third switching thin film transistor T13 is turned off; the third control signal Merge is at a low potential, and the fourth switching thin film transistor T14 is turned off; the top gate tg of the double-gate driving thin film transistor T10 is connected to the reference The voltage Vref turns on the dual gate driving thin film transistor T10, and the bottom gate bg and drain of the dual gate driving thin film transistor T10 are short-circuited to form a diode structure; the bottom gate bg of the dual gate driving thin film transistor T10 is high The potential gradually drops until the double-gate driving thin film transistor T10 is turned off (turned off), and the compensation of the threshold voltage Vth is completed, and the compensated
  • Data writing stage 3 The first power supply voltage EVDD is at a low potential, and the second power supply voltage VSS is at a low potential; the first control signal Sense is at a low potential, and the first switching thin film transistor T11 and the second switching thin film transistor T12 are disconnected; The second control signal Scan is at a low level, the third switch thin film transistor T13 is turned off; the third control signal Merge is at a high potential, the fourth switch thin film transistor T14 is turned on, and the data signal Data pre-stored by the third capacitor C3 passes through the fourth switch film The transistor T14 is output to the top gate tg of the double-gate driving thin film transistor T10 and stored in the first capacitor C1.
  • Light-emitting stage 4 the first power supply voltage EVDD is at a high potential, the second power supply voltage VSS is at a low potential; the first control signal Sense is at a low potential, the first switching thin film transistor T11 and the second switching thin film transistor T12 are disconnected; the second control The signal Scan is at a high potential, the third switching thin film transistor T13 is turned on; the third control signal Merge is at a low potential, and the fourth switching thin film transistor T14 is turned off; the data signal Data stored in the first capacitor C1 controls the double gate driving thin film transistor T10 Turn on to drive the light emitting module 2 to emit light.
  • the second control signal Scan turns on the third switching thin film transistor T13 row by row to write and store the data signal Data of the next frame from the data line into the third capacitor C3.
  • the formula for the current flowing through the light-emitting device during the light-emitting stage is:
  • K is a constant value coefficient related to the characteristics of the dual gate driving thin film transistor T10
  • ⁇ is the efficiency of data signal Data transmission to the top gate tg of the dual gate driving thin film transistor T10
  • Vref is the reference for the threshold voltage compensation stage Voltage.
  • the current value flowing through the dual gate driving thin film transistor T10 and the light emitting module 2 has nothing to do with the threshold voltage Vth of the dual gate driving thin film transistor T10, which compensates for the threshold voltage drift of the dual gate driving thin film transistor T10. It is beneficial to improve the uniformity and accuracy of the display of the display panel.
  • the high potential of the top gate tg terminal of the double-gate driving thin film transistor T10 The signal drops earlier than the second power supply voltage VSS to turn off the dual-gate driving thin film transistor T10 and maintain the initialization effect; and, to ensure that the compensated threshold voltage is not affected, the reference voltage Vref is delayed until the data writing stage 3 rises to high The potential signal does not change together with the first control signal Sense at the t2 time point.
  • the pixel driving circuit 1 of the 5T3C architecture can realize the compensation of the threshold voltage Vth in positive and negative conditions, effectively widening the compensation range of the threshold voltage Vth, and solving the traditional internal compensation of the diode structure.
  • the circuit can only compensate for the problem of threshold voltage drift in a single direction, which is beneficial to improve the uniformity and accuracy of the panel display and improve the life of the panel; on the other hand, the data writing module 4 in this embodiment has the function of pre-storing the data signal Data That is, in the light-emitting stage, the light-emitting device can also write and store the next frame of data signals while emitting light, which can effectively reduce the time (t3-t2) required for the data writing stage 3, thereby increasing the light-emitting stage 4
  • the duty cycle (the time required for the light-emitting phase/the sum of the time required for the data writing phase and the light-emitting phase), at the same time, it also increases the data signal writing time and improves the charging time of the high-resolution display panel. It is beneficial to improve the display effect of the high-resolution display panel.
  • the functions of the source and drain mentioned in all the above embodiments are the same, and the names of the two can be interchanged. That is to say, when the thin film transistor is turned on, the current can flow from the source to the drain, or From the drain to the source, the direction of current flow is only determined by the magnitude of the voltage connected to the source and drain.
  • an embodiment of the present application also provides a display panel 5.
  • the display panel 5 includes a signal control unit 6 and a plurality of pixel units 7.
  • Each pixel unit 7 includes any one of the pixel driving circuits in the above embodiments. 1;
  • the signal control unit 6 is electrically connected to each pixel drive circuit 1, and provides control signals for the pixel drive circuit 1.
  • the display panel 5 includes any one of an LTPS (Low Temperature Poly-Silicon) display panel and an IGZO (Indium Gallium Zinc Oxide, indium gallium zinc oxide) display panel.
  • LTPS Low Temperature Poly-Silicon
  • IGZO Indium Gallium Zinc Oxide, indium gallium zinc oxide
  • the display in this embodiment The type of panel 5 is not limited to this.
  • LTPS cannot be used in the mass production of large-size OLED panels due to its disadvantages such as poor uniformity of large-size preparation and high cost.
  • the oxide semiconductor based on IGZO is suitable for mass production of large-size OLED panels due to its high mobility, good uniformity in large-size preparation, and flexibility and transparency.
  • oxide TFTs face reliability problems. As driving transistors, TFTs need to work under voltage/current stress, and changes in their threshold voltage Vth will affect the accuracy of screen display.
  • the pixel driving circuit 1 provided by the embodiment of the present application is suitable for an OLED/Micro-LED display panel 5 based on oxide TFT backplane technology.
  • the threshold voltage Vth is compensated by an N-type driving TFT with a double gate structure, which can improve the display performance of the panel. Uniformity, and the ability to compensate the threshold voltage Vth when the threshold voltage Vth is positive and negative can be achieved.
  • the pixel driving circuit 1 can realize the compensation of the threshold voltage in the positive and negative conditions, which effectively widens the compensation range of the threshold voltage, and solves the problem that the traditional diode structure type internal compensation circuit can only compensate the threshold voltage in a single direction.
  • the problem of drift is conducive to improving the uniformity and accuracy of the panel display and improving the life of the panel.
  • the first control signal Sense (signal transmitted by the Sense line) and the third control signal Merge (signal transmitted by the Merge line) are global signals. That is, the Sense lines of all the pixel units 7 on the display panel 5 are connected together through the peripheral shorting bar, and the signal is provided by the external IC chip, and the Merge lines of all the pixel units 7 on the display panel 5 also pass through the peripheral shorting bar. Connected together, the signal is provided by an external IC chip.
  • the Sense lines on the display panel 5 are also connected together by the peripheral short-circuit bar, and the signal is provided by the external IC chip. Therefore, only the second control signal Scan is generated row by row, which is generated by the gate signal driving IC or GOA. If the second control signal Scan is generated by the gate signal driver IC, it is beneficial to reduce the number of signal channels, thereby reducing costs; if only the second control signal Scan is generated by GOA, the complexity of GOA design can be reduced, and GOA only outputs the Scan signal. , Which is beneficial to improve the product yield, and at the same time reduces the side width of the display panel 5, which is beneficial to enhance the product competitiveness.

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Abstract

一种像素驱动电路（1）和显示面板（5），像素驱动电路（1）包括电连接的发光模块（2）和补偿驱动模块（3）；补偿驱动模块（3）包括双栅极驱动薄膜晶体管（T10），用于在初始化阶段，对双栅极驱动薄膜晶体管（10）的底栅极（bg）进行充电，将阈值电压（Vth）调节至初始值；且在阈值电压补偿阶段，接入参考电压（Vref），对双栅极驱动薄膜晶体管（T10）的底栅极（bg）进行放电，实现对阈值电压（Vth）的补偿。

Description

像素驱动电路和显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种像素驱动电路和显示面板。
背景技术
相较于传统的LCD(Liquid Crystal Display，液晶显示器)技术，OLED(Organic Light Emitting Diode，有机发光二极管)具有更高对比度、更快反应速度和广视角等优势，被广泛应用在智能手机领域和智能电视以及可穿戴设备领域。然而OLED作为有机材料，对于水氧等比较敏感，影响材料的稳定性及显示器寿命。近年来无机材料的Micro-LED以其高对比度、无机材料高稳定性等优势引起广泛关注，被认为是未来能与OLED媲美的新型显示技术。
传统的LCD属于电压驱动型器件；而Micro-LED与OLED属于电流驱动型器件，对薄膜晶体管(TFT)的电性变异比较敏感，因此，Micro-LED与OLED显示面板的薄膜晶体管的阈值电压Vth的均匀性以及在电学压力(Stress)下阈值电压Vth的正向或负向漂移均会影响画面显示的准确性和均匀性。为解决阈值电压Vth的漂移问题，通常引入补偿电路设计。
图1(a)为传统的Diode-Connect(二极管结构)型内部补偿电路结构，其中，T1薄膜晶体管是驱动薄膜晶体管，且T1薄膜晶体管为N型薄膜晶体管(NTFT)，T2薄膜晶体管为开关薄膜晶体管；T2薄膜晶体管的源极和漏极分别连接T1薄膜晶体管的栅极端(G)和漏极端(D)，当T2薄膜晶体管导通时，T1薄膜晶体管形成二极管结构。如图1(b)所示，若T1薄膜晶体管的阈值电压Vth>0V，此时，T1薄膜晶体管的栅极端(G)电压会通过二极管释放，直至其栅极端(G)与源极端(S)的电压差Vgs＝Vth时，二极管截止，从而探测到T1薄膜晶体管的阈值电压Vth信息，用于进一步对阈值电压Vth进行补偿。但是，如图1(c)所示，若T1薄膜晶体管的阈值电压Vth<0V，此时T1薄膜晶体管一直处于开启状态，且最终T1薄膜晶体管的栅极端(G)和源极端(S)电位相等，即Vgs＝0V，此时栅极端(G)不能全部探测到Vth信息，无法进一步对阈值电压Vth进行补偿。因此，对于N型薄膜晶体管来 说，传统的Diode-Connect型补偿电路无法补偿Vth为负值的情况，不利于提高面板显示的均匀性，使得面板寿命减小。
因此，需要开发一种新的像素驱动电路，实现对阈值电压Vth为正值和负值情况下的补偿，从而提高画面显示的准确性和均匀性。
技术问题
本申请提供一种像素驱动电路和显示面板，结合双栅器件栅极调控原理和二极管结构的阈值电压探测原理，可以实现对驱动薄膜晶体管的阈值电压为正值和负值情况下的补偿，解决了传统的Diode-Connect型内部补偿电路只能补偿单一方向阈值电压漂移的问题，提高了画面显示的准确性和均匀性。
技术解决方案
第一方面，本申请提供一种像素驱动电路，包括发光模块和补偿驱动模块：
所述发光模块，用于在初始化阶段、阈值电压补偿阶段和数据写入阶段接入低电位的第一电源电压；在发光阶段，接入高电位的第一电源电压；
所述补偿驱动模块，与所述发光模块电连接，包括双栅极驱动薄膜晶体管，用于在所述初始化阶段，接入高电位信号，以导通双栅极驱动薄膜晶体管，且接入高电位的第二电源电压，以对所述双栅极驱动薄膜晶体管的底栅极进行充电，将所述双栅极驱动薄膜晶体管的阈值电压调节至初始值；在所述阈值电压补偿阶段，接入参考电压，以导通所述双栅极驱动薄膜晶体管，且接入低电位的第二电源电压，以对所述双栅极驱动薄膜晶体管的底栅极进行放电，将所述双栅极驱动薄膜晶体管的阈值电压补偿至等于所述参考电压与所述低电位的第二电源电压之间的电压差值；在所述数据写入阶段，接入数据信号和低电位的第二电源电压；在所述发光阶段，导通所述双栅极驱动薄膜晶体管，且接入低电位的第二电源电压，以控制所述发光模块发光。
在本申请所提供的像素驱动电路中，所述补偿驱动模块还包括第一开关薄膜晶体管和第二开关薄膜晶体管；
所述补偿驱动模块还用于在所述初始化阶段导通所述第一开关薄膜晶体管，以接入所述高电位信号，且导通所述第二开关薄膜晶体管，以使所述高电位的第二电源电压对所述双栅极驱动薄膜晶体管的底栅极进行充电；在所述阈 值电压补偿阶段导通所述第一开关薄膜晶体管，以接入所述参考电压，且导通所述第二开关薄膜晶体管，以使所述双栅极驱动薄膜晶体管的底栅极进行放电；在所述数据写入阶段断开所述第一开关薄膜晶体管和所述第二开关薄膜晶体管，以接入所述数据信号；在所述发光阶段断开所述第一开关薄膜晶体管和所述第二开关薄膜晶体管，以驱动所述发光模块发光。
在本申请所提供的像素驱动电路中，所述双栅极驱动薄膜晶体管的源极接入所述第二电源电压，其漏极与所述发光模块电连接；
所述第一开关薄膜晶体管的栅极接入第一控制信号，其源极在所述初始化阶段接入所述高电位信号，且在所述阈值电压补偿阶段接入所述参考电压，其漏极与所述双栅极驱动薄膜晶体管的顶栅极电连接；
所述第二开关薄膜晶体管的栅极接入所述第一控制信号，其源极与所述双栅极驱动薄膜晶体管的漏极电连接，其漏极与所述双栅极驱动薄膜晶体管的底栅极电连接。
在本申请所提供的像素驱动电路中，所述补偿驱动模块还包括第一电容和第二电容；
所述第一电容的一端与所述双栅极驱动薄膜晶体管的顶栅极电连接，另一端与所述双栅极驱动薄膜晶体管的源极电连接，用以存储所述双栅极驱动薄膜晶体管的顶栅极的电位；
所述第二电容的一端与所述双栅极驱动薄膜晶体管的底栅极电连接，另一端接地，用以存储所述双栅极驱动薄膜晶体管的底栅极的电位。
在本申请所提供的像素驱动电路中，所述参考电压为正电压或者负电压。
在本申请所提供的像素驱动电路中，所述双栅极驱动薄膜晶体管包括N型氧化物薄膜晶体管、N型低温多晶硅薄膜晶体管、N型非晶硅薄膜晶体管和N型有机薄膜晶体管中的任意一种。
在本申请所提供的像素驱动电路中，所述像素驱动电路还包括与所述补偿驱动模块电连接的数据写入模块；
所述数据写入模块用于在所述数据写入阶段获取所述数据信号，并向所述补偿驱动模块输出所述数据信号。
在本申请所提供的像素驱动电路中，所述数据写入模块包括第三开关薄膜 晶体管；所述第三开关薄膜晶体管的栅极接入第二控制信号，其源极接入所述数据信号，其漏极与所述双栅极驱动薄膜晶体管的顶栅极电连接。
在本申请所提供的像素驱动电路中，所述第一开关薄膜晶体管、所述第二开关薄膜晶体管和所述第三开关薄膜晶体管包括N型薄膜晶体管和P型薄膜晶体管中的任意一种。
在本申请所提供的像素驱动电路中，所述像素驱动电路还包括与所述补偿驱动模块电连接的数据写入模块；
所述数据写入模块用于在所述数据写入阶段向所述补偿驱动模块输出预存储的数据信号，且在所述发光阶段获取并存储下一帧所需的数据信号。
在本申请所提供的像素驱动电路中，所述数据写入模块包括第三开关薄膜晶体管、第四开关薄膜晶体管和第三电容；
所述数据写入模块用于在所述数据写入阶段，断开所述第三开关薄膜晶体管，导通所述第四开关薄膜晶体管，将所述第三电容中预存储的数据信号输出至所述双栅极驱动薄膜晶体管的顶栅极；在所述发光阶段，断开所述第四开关薄膜晶体管，导通所述第三开关薄膜晶体管，以获取下一帧的数据信号并存储至所述第三电容。
在本申请所提供的像素驱动电路中，所述第三开关薄膜晶体管的栅极接入第二控制信号，其源极接入所述数据信号，其漏极与所述第四开关薄膜晶体管的源极电连接；所述第四开关薄膜晶体管的栅极接入第三控制信号，其漏极与所述双栅极驱动薄膜晶体管的顶栅极电连接；
所述第三电容的一端与所述第四开关薄膜晶体管的源极电连接，另一端接地。
在本申请所提供的像素驱动电路中，所述第一开关薄膜晶体管、所述第二开关薄膜晶体管、所述第三开关薄膜晶体管和所述第四开关薄膜晶体管包括N型薄膜晶体管和P型薄膜晶体管中的任意一种。
在本申请所提供的像素驱动电路中，所述发光模块包括OLED发光器件或者Micro-LED发光器件。
第二方面，本申请还提供了一种显示面板，包括信号控制单元和多个像素 单元，每个像素单元包括上述的像素驱动电路；所述信号控制单元与每个所述像素驱动电路电连接，为所述像素驱动电路提供控制信号。
在本申请所提供的显示面板中，所述补偿驱动模块还包括第一开关薄膜晶体管和第二开关薄膜晶体管；
所述补偿驱动模块还用于在所述初始化阶段导通所述第一开关薄膜晶体管，以接入所述高电位信号，且导通所述第二开关薄膜晶体管，以使所述高电位的第二电源电压对所述双栅极驱动薄膜晶体管的底栅极进行充电；在所述阈值电压补偿阶段导通所述第一开关薄膜晶体管，以接入所述参考电压，且导通所述第二开关薄膜晶体管，以使所述双栅极驱动薄膜晶体管的底栅极进行放电；在所述数据写入阶段断开所述第一开关薄膜晶体管和所述第二开关薄膜晶体管，以接入所述数据信号；在所述发光阶段断开所述第一开关薄膜晶体管和所述第二开关薄膜晶体管，以驱动所述发光模块发光。
在本申请所提供的显示面板中，所述双栅极驱动薄膜晶体管的源极接入所述第二电源电压，其漏极与所述发光模块电连接；
所述第一开关薄膜晶体管的栅极接入第一控制信号，其源极在所述初始化阶段接入所述高电位信号，且在所述阈值电压补偿阶段接入所述参考电压，其漏极与所述双栅极驱动薄膜晶体管的顶栅极电连接；
所述第二开关薄膜晶体管的栅极接入所述第一控制信号，其源极与所述双栅极驱动薄膜晶体管的漏极电连接，其漏极与所述双栅极驱动薄膜晶体管的底栅极电连接。
在本申请所提供的显示面板中，所述补偿驱动模块还包括第一电容和第二电容；
所述第一电容的一端与所述双栅极驱动薄膜晶体管的顶栅极电连接，另一端与所述双栅极驱动薄膜晶体管的源极电连接，用以存储所述双栅极驱动薄膜晶体管的顶栅极的电位；
所述第二电容的一端与所述双栅极驱动薄膜晶体管的底栅极电连接，另一端接地，用以存储所述双栅极驱动薄膜晶体管的底栅极的电位。
在本申请所提供的显示面板中，所述像素驱动电路还包括与所述补偿驱动模块电连接的数据写入模块；
所述数据写入模块用于在所述数据写入阶段获取所述数据信号，并向所述补偿驱动模块输出所述数据信号；或者，在所述数据写入阶段向所述补偿驱动模块输出预存储的数据信号，且在所述发光阶段获取并存储下一帧所需的数据信号。
在本申请所提供的显示面板中，所述参考电压为正电压或者负电压。
有益效果
相较于现有技术，本申请提供的像素驱动电路中，补偿驱动模块中的驱动薄膜晶体采用双栅结构，即双栅驱动薄膜晶体管，根据双栅器件的栅极调控原理，双栅驱动薄膜晶体管的底栅极的电位能够线性动态调节其阈值电压，在初始化阶段，通过对双栅驱动薄膜晶体管的底栅极充电至高电位，调节其阈值电压至较低的初始值；然后，结合二极管结构的阈值电压探测原理，在阈值电压补偿阶段，将双栅驱动薄膜晶体管的底栅极与漏极短接形成二极管结构，从而使底栅极的高电位逐渐下降，直至双栅驱动薄膜晶体管截止，使得其阈值电压等于其顶栅极与源极的电压差，由于该阶段顶栅极的电位等于参考电压，源极的电位等于第二电源电压，故补偿后的阈值电压等于补偿阶段的参考电压与第二电源电压之间的差值，从而实现对双栅驱动薄膜晶体管的阈值电压的补偿；另外，不管初始化之前双栅驱动薄膜晶体管的阈值电压为正值还是负值，都可以在补偿阶段通过增大双栅驱动薄膜晶体管的底栅极的电位来调节其阈值电压至初始值，然后进行补偿；因此，本发明的像素驱动电路能够实现阈值电压在正值和负值情况下的补偿，有效拓宽了阈值电压的补偿范围，解决了传统的二极管结构型内部补偿电路只能补偿单一方向阈值电压漂移的问题，有利于提高显示面板显示的均匀性和准确性，改善显示面板寿命。
附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1(a)为示例性的二极管结构型内部补偿电路结构示意图。
图1(b)为采用图1(a)中的内部补偿电路结构对正值阈值电压探测时T1薄膜晶体管的栅极端与源极端的电压差的变化示意图。
图1(c)为采用图1(a)中的内部补偿电路结构对负值阈值电压探测时T1薄膜晶体管的栅极端与源极端的电压差的变化示意图。
图2为本申请实施例提供的像素驱动电路的结构示意框图。
图3为本申请实施例提供的一种4T2C架构的像素驱动电路的电路图。
图4为图3提供的像素驱动电路的驱动时序图。
图5为本申请实施例提供的一种5T3C架构的像素驱动电路的电路图。
图6为图5提供的像素驱动电路的驱动时序图。
图7为本申请实施例提供的一种显示面板的结构示意图。
本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
如图2和图3所示，本申请实施例提供了一种4T2C架构的像素驱动电路1，像素驱动电路1包括发光模块2、补偿驱动模块3和数据写入模块4，且像素驱动电路1的驱动时序依次包括初始化阶段、阈值电压补偿阶段、数据写入阶段和发光阶段。
发光模块2用于在初始化阶段、阈值电压补偿阶段和数据写入阶段接入低电位的第一电源电压EVDD，保持不发光状态；并且，在发光阶段，接入高电位的第一电源电压EVDD，以实现发光。具体的，发光模块2包括OLED发光器件或Micro-LED发光器件，且发光器件的阳极端接入第一电源电压 EVDD，其阴极端与补偿驱动模块3电连接。
数据写入模块4与补偿驱动模块3电连接，用于在数据写入阶段获取数据信号Data，并向补偿驱动模块3输出数据信号Data。
补偿驱动模块3还与发光模块2电连接，补偿驱动模块3包括双栅极驱动薄膜晶体管T10，用于在初始化阶段，接入高电位信号，以导通双栅极驱动薄膜晶体管T10，且接入高电位的第二电源电压VSS，以对双栅极驱动薄膜晶体管T10的底栅极bg进行充电，将双栅极驱动薄膜晶体管T10的阈值电压Vth调节至初始值；在阈值电压补偿阶段，接入参考电压Vref(大于上述初始值，且小于上述高电位信号)，以导通双栅极驱动薄膜晶体管T10，且接入低电位的第二电源电压VSS，以对双栅极驱动薄膜晶体管T10的底栅极bg进行放电，将双栅极驱动薄膜晶体管T10的阈值电压Vth补偿至等于参考电压Vref与低电位的第二电源电压VSS之间的电压差值(Vref-VSS)；在数据写入阶段，接入数据写入模块4提供的数据信号Data；在发光阶段，通过数据信号Data导通双栅极驱动薄膜晶体管T10，且接入低电位的第二电源电压VSS，以控制发光模块2发光。
具体的，双栅极驱动薄膜晶体管T10的顶栅极tg在初始化阶段接入高电位信号，且在阈值电压补偿阶段接入参考电压Vref，其源极接入第二电源电压VSS，其漏极与发光模块2中发光器件的阴极电连接。双栅极驱动薄膜晶体管T10包括N型氧化物薄膜晶体管、N型低温多晶硅薄膜晶体管、N型非晶硅薄膜晶体管和N型有机薄膜晶体管中的任意一种。
需要说明的是，由于双栅极驱动薄膜晶体管T10是双栅结构，其阈值电压Vth不是固定值，阈值电压Vth与底栅极bg的电位呈负向线性关系，具体的，双栅极驱动薄膜晶体管T10的阈值电压Vth随底栅极bg与其源极之间的电位差(Vbgs)增大而线性减小，并且，对于不同尺寸的双栅极驱动薄膜晶体管T10，其阈值电压Vth与Vbgs之间的线性关系式的斜率相同，即不同尺寸的双栅极驱动薄膜晶体管T10均在本申请的保护范围内。
具体的，在初始化阶段，双栅极驱动薄膜晶体管T10的底栅极bg被充电至高电位，使得阈值电压Vth下降至较低的初始值；在阈值电压补偿阶段，双栅极驱动薄膜晶体管T10的底栅极bg被放电，在底栅极bg的高电位逐渐下降 的过程中，阈值电压Vth逐渐增大，直至等于双栅极驱动薄膜晶体管T10的顶栅极tg与源极之间的电压差Vtgs，此时双栅极驱动薄膜晶体管T10截止，从而完成了阈值电压补偿。由于在阈值电压补偿过程中，双栅极驱动薄膜晶体管T10的顶栅极tg接入参考电压Vref，漏极接入低电位的第二电源电压VSS，故补偿后的Vth＝Vtgs＝Vref-VSS，而低电位的第二电源电压VSS可以设为0V，因此，补偿后的Vth＝Vref。通过设定参考电压Vref得到补偿后的阈值电压。
具体的，参考电压Vref为正电压或者负电压。需要说明的是，参考电压Vref值的选取取决于显示面板未初始化之前的Vth分布，并非固定值。一般氧化物TFT的阈值电压Vth在未初始化之前约为0V，由于Vth会正负漂移，对于氧化物TFT，阈值电压补偿阶段选取的参考电压Vref为负值。当然，对于在未初始化之前阈值电压Vth大于0V的TFT，参考电压Vref可以设为正值。因此，本申请实施例提供的像素驱动电路1可以补偿阈值电压Vth为正值的情况，也可以补偿阈值电压Vth为负值的情况。
具体的，补偿驱动模块3还包括第一开关薄膜晶体管T11、第二开关薄膜晶体管T12、第一电容C1和第二电容C2。
第一开关薄膜晶体管T11的栅极接入第一控制信号Sense，其源极在初始化阶段接入高电位信号，且在阈值电压Vth补偿阶段接入参考电压Vref，其漏极与双栅极驱动薄膜晶体管T10的顶栅极tg电连接。需要说明的是，图2和图3中示出的参考电压Vref，还可以替换为上述高电位信号。
第二开关薄膜晶体管T12的栅极也接入第一控制信号Sense，其源极与双栅极驱动薄膜晶体管T10的漏极电连接，其漏极与双栅极驱动薄膜晶体管T10的底栅极bg电连接。
第一电容C1的一端与双栅极驱动薄膜晶体管T10的顶栅极tg电连接，另一端与双栅极驱动薄膜晶体管T10的源极电连接，用以存储双栅极驱动薄膜晶体管T10的顶栅极tg的电位；第二电容C2的一端与双栅极驱动薄膜晶体管T10的底栅极bg电连接，另一端接地，用以存储双栅极驱动薄膜晶体管T10的底栅极bg的电位。
具体的，补偿驱动模块3还用于在初始化阶段通过第一控制信号Sense导通第一开关薄膜晶体管T11，以使双栅极驱动薄膜晶体管T10的顶栅极tg接 入高电位信号而导通，且通过第一控制信号Sense导通第二开关薄膜晶体管T12，以使双栅极驱动薄膜晶体管T10的底栅极bg和漏极短接形成二极管结构，使高电位的第二电源电压VSS依次通过双栅极驱动薄膜晶体管T10和第二开关薄膜晶体管T12对双栅极驱动薄膜晶体管T10的底栅极bg进行充电，以实现对双栅极驱动薄膜晶体管T10的阈值电压的初始化；并且，在阈值电压补偿阶段通过第一控制信号Sense导通第一开关薄膜晶体管T11，以使双栅极驱动薄膜晶体管T10的顶栅极tg接入参考电压Vref，且通过第一控制信号Sense导通第二开关薄膜晶体管T12，使双栅极驱动薄膜晶体管T10的底栅极bg和漏极保持短接状态，此时双栅极驱动薄膜晶体管T10的源极接入低电位的第二电源电压VSS，使双栅极驱动薄膜晶体管T10的底栅极bg进行放电，以实现对双栅极驱动薄膜晶体管T10的阈值电压的补偿；在数据写入阶段通过第一控制信号Sense断开第一开关薄膜晶体管T11和第二开关薄膜晶体管T12，以接入数据信号(Data)并存储至第一电容C1；以及，在发光阶段通过第一控制信号Sense断开第一开关薄膜晶体管T11和第二开关薄膜晶体管T12，且通过第一电容C1存储的数据信号(Data)导通双栅极驱动薄膜晶体管T10，以驱动发光模块2发光。
具体的，数据写入模块4包括第三开关薄膜晶体管T13；第三开关薄膜晶体管T13的栅极接入第二控制信号Scan，其源极接入数据信号Data，其漏极与双栅极驱动薄膜晶体管T10的顶栅极tg电连接。数据写入模块4具体用于在初始化阶段、阈值电压补偿阶段和发光阶段，通过第二控制信号Scan断开第三开关薄膜晶体管T13；并且在数据写入阶段，通过第二控制信号Scan导通第三开关薄膜晶体管T13，以获取数据信号Data并将数据信号Data输入到双栅极驱动薄膜晶体管T10的顶栅极tg。
具体的，第一开关薄膜晶体管T11、第二开关薄膜晶体管T12和第三开关薄膜晶体管T13既可以是N型薄膜晶体管，也可以是P型薄膜晶体管；根据材料类型的不同，第一开关薄膜晶体管T11、第二开关薄膜晶体管T12和第三开关薄膜晶体管T13包括氧化物薄膜晶体管、低温多晶硅薄膜晶体管、非晶硅薄膜晶体管和有机薄膜晶体管中的任意一种；并且第一开关薄膜晶体管T11、第二开关薄膜晶体管T12和第三开关薄膜晶体管T13既可以是单栅结构，也 可以是双栅结构，此处不做限制。
具体的，当第一开关薄膜晶体管T11、第二开关薄膜晶体管T12和第三开关薄膜晶体管T13为N型薄膜晶体管时，分别通过高电位的控制信号导通，且通过低电位的控制信号断开。当第一开关薄膜晶体管T11、第二开关薄膜晶体管T12和第三开关薄膜晶体管T13为P型薄膜晶体管时，第一开关薄膜晶体管T11、第二开关薄膜晶体管T12和第三开关薄膜晶体管T13则是分别通过低电位的控制信号导通，通过高电位的控制信号断开。
在一实施例中，像素驱动电路1的驱动时序如图4所示，像素驱动电路1的驱动时序依次包括初始化阶段①、阈值电压补偿阶段②、数据写入阶段③和发光阶段④；需要说明的是，由于初始化阶段①的高电位信号和阈值补偿阶段②的参考电压Vref均从第一开关薄膜晶体管T11的源极接入，因此，在时序图中，高电位信号和参考电压Vref采用同一条电位线Vref表示，也可以认为高电压信号为初始参考电压，参考电压Vref为补偿阶段的特定参考电压。结合图3和图4，像素驱动电路1的驱动步骤如下：
初始化阶段：第一电源电压EVDD为低电位，第二电源电压VSS为高电位；第一控制信号Sense为高电位，第一开关薄膜晶体管T11和第二开关薄膜晶体管T12导通；第二控制信号Scan为低电位，第三开关薄膜晶体管T13断开；双栅极驱动薄膜晶体管T10的顶栅极tg接入高电位信号，使双栅极驱动薄膜晶体管T10导通，且底栅极bg与漏极短接形成二极管结构；高电位的第二电源电压VSS对双栅极驱动薄膜晶体管T10的底栅极bg充电至高电位，当第二电源电压VSS从高电位降至低电位时，阈值电压Vth被调节至较小的初始值，第二电容C2存储底栅极bg的高电位。
阈值电压补偿阶段②：第一电源电压EVDD为低电位，第二电源电压VSS为低电位；第一控制信号Sense为高电位，第一开关薄膜晶体管T11和第二开关薄膜晶体管T12导通；第二控制信号Scan为低电位，第三开关薄膜晶体管T13断开；双栅极驱动薄膜晶体管T10的顶栅极tg接入参考电压Vref，使双栅极驱动薄膜晶体管T10导通，且底栅极bg与漏极短接形成二极管结构；双栅极驱动薄膜晶体管T10的底栅极bg的高电位逐渐下降，直至双栅极驱动薄膜晶体管T10断开(截止)，完成阈值电压Vth的补偿，且补偿后的阈值电压 Vth＝Vref-VSS＝Vref-0V＝Vref，第二电容C2存储底栅极bg的低电位，以维持阈值电压Vth为补偿值。
数据写入阶段③：第一电源电压EVDD为低电位，第二电源电压VSS为低电位；第一控制信号Sense为低电位，第一开关薄膜晶体管T11和第二开关薄膜晶体管T12断开；第二控制信号Scan为高电位(Scan逐行打开)，第三开关薄膜晶体管T13导通，数据信号Data从数据线写入并通过第三开关薄膜晶体管T13输出至双栅极驱动薄膜晶体管T10的顶栅极tg，且存储至第一电容C1。
发光阶段④：第一电源电压EVDD为高电位，第二电源电压VSS为低电位；第一控制信号Sense为低电位，第一开关薄膜晶体管T11和第二开关薄膜晶体管T12断开；第二控制信号Scan为低电位，第三开关薄膜晶体管T13断开，第一电容C1存储的数据信号Data控制双栅极驱动薄膜晶体管T10导通，以驱动发光模块2发光。
具体的，发光阶段，流过发光器件的电流公式为：
I＝K(αV Data-Vth) 2
＝K(αV Data-Vref) 2
其中，K为一与双栅极驱动薄膜晶体管T10特性有关的常值系数，α为数据信号Data传输到双栅极驱动薄膜晶体管T10的顶栅极tg的效率，Vref为阈值电压补偿阶段的参考电压。
由上述电流公式可知，流过双栅极驱动薄膜晶体管T10和发光模块2的电流值与双栅极驱动薄膜晶体管T10的阈值电压Vth无关，补偿了双栅极驱动薄膜晶体管T10的阈值电压漂移，有利于显示面板显示的均匀性和准确性。
需要说明的是，为了避免在t1时间点第二电源电压VSS由高电位降至低电位而导致第二电容C2中的高电位下降，双栅极驱动薄膜晶体管T10的顶栅极tg端的高电位信号较第二电源电压VSS提前下降，以断开双栅极驱动薄膜晶体管T10，维持初始化效果；并且，为了保证补偿的阈值电压不受影响，参考电压Vref延迟至数据写入阶段③升高至高电位信号，而避免在t2时间点与第一控制信号Sense同时改变。
本实施例中，补偿驱动模块3中的驱动薄膜晶体采用双栅结构，即双栅驱 动薄膜晶体管T10，根据双栅器件的栅极调控原理，双栅驱动薄膜晶体管T10的底栅极bg的电位能够线性动态调节其阈值电压，在初始化阶段，通过对双栅驱动薄膜晶体管T10的底栅极bg充电至高电位，调节其阈值电压Vth至较低的初始值；然后，结合二极管结构的阈值电压探测原理，在阈值电压补偿阶段，将双栅驱动薄膜晶体管T10的底栅极bg与漏极短接形成二极管结构，从而使底栅极bg的高电位逐渐下降，直至双栅驱动薄膜晶体管T10截止，使得其阈值电压Vth等于其顶栅极tg与源极的电压差，由于该阶段顶栅极tg的电位等于参考电压Vref，源极的电位等于第二电源电压VSS，故补偿后的阈值电压等于补偿阶段的参考电压Vref与第二电源电压VSS之间的差值，从而实现对双栅驱动薄膜晶体管T10的阈值电压的补偿；另外，不管初始化之前双栅驱动薄膜晶体管T10的阈值电压Vth为正值还是负值，都可以在补偿阶段通过增大双栅驱动薄膜晶体管T10的底栅极bg的电位来调节其阈值电压Vth至初始值，然后进行补偿；因此，本申请提供的像素驱动电路1能够实现阈值电压Vth在正值和负值情况下的补偿，有效拓宽了阈值电压Vth的补偿范围，解决了传统的二极管结构型内部补偿电路只能补偿单一方向阈值电压漂移的问题，有利于提高显示面板显示的均匀性和准确性，改善显示面板寿命。
如图2和图5所示，本申请实施例还提供了一种5T3C架构的像素驱动电路1，与上述实施例不同的在于，数据写入模块4用于在数据写入阶段向补偿驱动模块3输出预存储的数据信号(Data)，且在发光模块2获取并存储下一帧所需的数据信号；具体的，数据写入模块4包括第三开关薄膜晶体管T13、第四开关薄膜晶体管T14和第三电容C3；第三开关薄膜晶体管T13的栅极接入第二控制信号Scan，其源极接入数据信号Data，其漏极与第四开关薄膜晶体管T14的源极电连接；第四开关薄膜晶体管T14的栅极接入第三控制信号Merge，其漏极与双栅极驱动薄膜晶体管T10的顶栅极tg电连接；第三电容C3的一端与第四开关薄膜晶体管T14的源极电连接，另一端接地，用于在上一帧预存储数据信号Data。
数据写入模块4具体用于在初始化阶段和阈值电压补偿阶段，断开第三开关薄膜晶体管T13和第四开关薄膜晶体管T14；在数据写入阶段，断开第三开关薄膜晶体管T13，导通第四开关薄膜晶体管T14，将第三电容C3中预存储 的数据信号Data输出至双栅极驱动薄膜晶体管T10的顶栅极tg；在发光阶段，断开第四开关薄膜晶体管T14，导通第三开关薄膜晶体管T13，以获取下一帧的数据信号Data并存储至第三电容C3。
具体的，第一开关薄膜晶体管T11、第二开关薄膜晶体管T12、第三开关薄膜晶体管T13和第四开关薄膜晶体管T14既可以是N型薄膜晶体管，也可以是P型薄膜晶体管；根据材料类型的不同，第一开关薄膜晶体管T11、第二开关薄膜晶体管T12、第三开关薄膜晶体管T13和第四开关薄膜晶体管T14包括氧化物薄膜晶体管、低温多晶硅薄膜晶体管、非晶硅薄膜晶体管和有机薄膜晶体管中的任意一种；并且，第一开关薄膜晶体管T11、第二开关薄膜晶体管T12、第三开关薄膜晶体管T13和第四开关薄膜晶体管T14既可以是单栅结构，也可以是双栅结构，此处不做限制。
需要说明的是，图5中第一开关薄膜晶体管T11的源极位置示出的是参考电压Vref，还可以替换为上述高电位信号。
在一实施例中，像素驱动电路1的驱动时序如图6所示，像素驱动电路1的驱动时序依次包括初始化阶段①、阈值电压补偿阶段②、数据写入阶段③和发光阶段④；需要说明的是，由于初始化阶段①的高电位信号和阈值补偿阶段②的参考电压Vref均从第一开关薄膜晶体管T11的源极接入，因此，在时序图中，高电位信号和参考电压Vref采用同一条电位线Vref表示，也可以认为高电压信号为初始参考电压，参考电压Vref为补偿阶段的特定参考电压。结合图5和图6，像素驱动电路1的驱动方法如下：
初始化阶段；第一电源电压EVDD为低电位，第二电源电压VSS为高电位；第一控制信号Sense为高电位，第一开关薄膜晶体管T11和第二开关薄膜晶体管T12导通；第二控制信号Scan为低电位，第三开关薄膜晶体管T13断开；第三控制信号Merge为低电位，第四开关薄膜晶体管T14断开；双栅极驱动薄膜晶体管T10的顶栅极tg接入高电位信号，使双栅极驱动薄膜晶体管T10导通，且底栅极bg与漏极短接形成二极管结构；高电位的第二电源电压VSS对双栅极驱动薄膜晶体管T10的底栅极bg充电至高电位，当第二电源电压VSS从高电位降至低电位时，阈值电压Vth被调节至较小的初始值，第二电容C2存储底栅极bg的高电位。
阈值电压补偿阶段②：第一电源电压EVDD为低电位，第二电源电压VSS为低电位；第一控制信号Sense为高电位，第一开关薄膜晶体管T11和第二开关薄膜晶体管T12导通；第二控制信号Scan为低电位，第三开关薄膜晶体管T13断开；第三控制信号Merge为低电位，第四开关薄膜晶体管T14断开；双栅极驱动薄膜晶体管T10的顶栅极tg接入参考电压Vref，使双栅极驱动薄膜晶体管T10导通，且双栅极驱动薄膜晶体管T10的底栅极bg与漏极短接形成二极管结构；双栅极驱动薄膜晶体管T10的底栅极bg的高电位逐渐下降，直至双栅极驱动薄膜晶体管T10断开(截止)，完成阈值电压Vth的补偿，且补偿后的阈值电压Vth＝Vref-VSS＝Vref-0V＝Vref，第二电容C2存储底栅极bg的低电位，以维持阈值电压Vth为补偿值。
数据写入阶段③：第一电源电压EVDD为低电位，第二电源电压VSS为低电位；第一控制信号Sense为低电位，第一开关薄膜晶体管T11和第二开关薄膜晶体管T12断开；第二控制信号Scan为低电位，第三开关薄膜晶体管T13断开；第三控制信号Merge为高电位，第四开关薄膜晶体管T14导通，第三电容C3预存储的数据信号Data通过第四开关薄膜晶体管T14输出至双栅极驱动薄膜晶体管T10的顶栅极tg，且存储至第一电容C1。
发光阶段④：第一电源电压EVDD为高电位，第二电源电压VSS为低电位；第一控制信号Sense为低电位，第一开关薄膜晶体管T11和第二开关薄膜晶体管T12断开；第二控制信号Scan为高电位，第三开关薄膜晶体管T13导通；第三控制信号Merge为低电位，第四开关薄膜晶体管T14断开；第一电容C1存储的数据信号Data控制双栅极驱动薄膜晶体管T10导通，以驱动发光模块2发光，同时，第二控制信号Scan逐行打开第三开关薄膜晶体管T13，以将下一帧的数据信号Data从数据线写入并存储至第三电容C3中。
具体的，发光阶段，流过发光器件的电流公式为：
I＝K(αV Data-Vth) 2
＝K(αV Data-Vref) 2
其中，K为一与双栅极驱动薄膜晶体管T10特性有关的常值系数，α为数据信号Data传输到双栅极驱动薄膜晶体管T10的顶栅极tg的效率，Vref为阈值电压补偿阶段的参考电压。
由上述电流公式可知，流过双栅极驱动薄膜晶体管T10和发光模块2的电流值与双栅极驱动薄膜晶体管T10的阈值电压Vth无关，补偿了双栅极驱动薄膜晶体管T10的阈值电压漂移，有利于提高显示面板显示的均匀性和准确性。
需要说明的是，为了避免在t1时间点第二电源电压VSS由高电位降至低电位而导致第二电容C2中的高电位下降，双栅极驱动薄膜晶体管T10的顶栅极tg端的高电位信号较第二电源电压VSS提前下降，以断开双栅极驱动薄膜晶体管T10，维持初始化效果；并且，为了保证补偿的阈值电压不受影响，参考电压Vref延迟至数据写入阶段③升高至高电位信号，而不是在t2时间点与第一控制信号Sense一起改变。
本实施例中，一方面，5T3C架构的像素驱动电路1能够实现阈值电压Vth在正值和负值情况下的补偿，有效拓宽了阈值电压Vth的补偿范围，解决了传统的二极管结构型内部补偿电路只能补偿单一方向阈值电压漂移的问题，有利于提高面板显示的均匀性和准确性，改善面板寿命；另一方面，本实施例中的数据写入模块4具有预存储数据信号Data的功能，即在发光阶段，发光器件发光的同时还能进行下一帧数据信号的写入和存储，可以有效的减小数据写入阶段③所需的时间(t3-t2)，从而增大发光阶段④的占空比(发光阶段所需时间/数据写入阶段和发光阶段所属需时间总和)，同时，也增大了数据信号写入的时间，改善了高分辨率显示面板的充电时间，有利于提高高分辨率显示面板的显示效果。
需要说明的是，以上所有实施例中提到的源极和漏极的功能相同，二者名称可以互换，也就是说当薄膜晶体管导通时，电流可以从源极流向漏极，也可以从漏极流向源极，电流流向仅由源极和漏极接入的电压的大小决定。
如图7所示，本申请实施例还提供了一种显示面板5，显示面板5包括信号控制单元6和多个像素单元7，每个像素单元7包括上述实施例中的任意一个像素驱动电路1；信号控制单元6与每个像素驱动电路1电连接，为像素驱动电路1提供控制信号。
具体的，显示面板5包括LTPS(Low Temperature Poly-Silicon，低温多晶硅)显示面板和IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)显示面板中的任意一种，当然，本实施例中的显示面板5的种类不限于此。
具体的，LTPS以其大尺寸制备均匀性差、成本高等缺点，无法应用在大尺寸OLED面板量产中。而以IGZO为主的氧化物半导体以其迁移率高、大尺寸制备均匀性好、并且具备柔性透明等优点，适合大尺寸OLED面板量产。然而氧化物TFT面临信赖性问题，作为驱动晶体管，TFT需要工作在电压/电流应力下，其阈值电压Vth的变化会影响画面显示的准确性。本申请实施例提供的像素驱动电路1适用于基于氧化物TFT背板技术的OLED/Micro-LED显示面板5，通过双栅结构的N型驱动TFT实现阈值电压Vth的补偿，可以改善面板显示的均匀性，并且可以实现阈值电压Vth为正值和负值的情况下阈值电压Vth的补偿能力。
本实施例中，像素驱动电路1能够实现阈值电压在正值和负值情况下的补偿，有效拓宽了阈值电压的补偿范围，解决了传统的二极管结构型内部补偿电路只能补偿单一方向阈值电压漂移的问题，有利于提高面板显示的均匀性和准确性，改善面板寿命。
需要说明的是，对于本申请实施例中提供的5T3C架构的像素驱动电路1，第一控制信号Sense(由Sense线传输信号)和第三控制信号Merge(由Merge线传输信号)为全局信号，即显示面板5上所有像素单元7的Sense线通过外围的短路条(shorting bar)连接在一起，由外部IC芯片提供讯号，且显示面板5上所有像素单元7的Merge线也通过外围的短路条连接在一起，由外部IC芯片提供讯号。对于本申请实施例中提供的4T2C架构的像素驱动电路1，显示面板5上所有的Sense线也通过外围的短路条连接在一起，由外部IC芯片提供讯号。因此，仅有第二控制信号Scan是逐行产生的，由栅极信号驱动IC或GOA产生。若第二控制信号Scan由栅极信号驱动IC产生，有利于减少信号通道数，从而降低成本；若仅第二控制信号Scan由GOA产生，能够降低GOA设计复杂度，GOA仅输出Scan信号即可，有利于提高产品良率，同时减小显示面板5的边宽，有利于提升产品竞争力。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种像素驱动电路和显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实 施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种像素驱动电路，包括发光模块和补偿驱动模块：
    所述发光模块，用于在初始化阶段、阈值电压补偿阶段和数据写入阶段接入低电位的第一电源电压(EVDD)；在发光阶段，接入高电位的第一电源电压(EVDD)；
    所述补偿驱动模块，与所述发光模块电连接，包括双栅极驱动薄膜晶体管(T10)，用于在所述初始化阶段，接入高电位信号，以导通双栅极驱动薄膜晶体管(T10)，且接入高电位的第二电源电压(VSS)，以对所述双栅极驱动薄膜晶体管(T10)的底栅极进行充电，将所述双栅极驱动薄膜晶体管(T10)的阈值电压(Vth)调节至初始值；在所述阈值电压补偿阶段，接入参考电压(Vref)，以导通所述双栅极驱动薄膜晶体管(T10)，且接入低电位的第二电源电压(VSS)，以对所述双栅极驱动薄膜晶体管(T10)的底栅极进行放电，将所述双栅极驱动薄膜晶体管(T10)的阈值电压(Vth)补偿至等于所述参考电压(Vref)与所述低电位的第二电源电压(VSS)之间的电压差值；在所述数据写入阶段，接入数据信号(Data)和低电位的第二电源电压(VSS)；在所述发光阶段，导通所述双栅极驱动薄膜晶体管(T10)，且接入低电位的第二电源电压(VSS)，以控制所述发光模块发光。
  2. 如权利要求1所述的像素驱动电路，其中，所述补偿驱动模块还包括第一开关薄膜晶体管(T11)和第二开关薄膜晶体管(T12)；
    所述补偿驱动模块还用于在所述初始化阶段导通所述第一开关薄膜晶体管(T11)，以接入所述高电位信号，且导通所述第二开关薄膜晶体管(T12)，以使所述高电位的第二电源电压(VSS)对所述双栅极驱动薄膜晶体管(T10)的底栅极进行充电；在所述阈值电压补偿阶段导通所述第一开关薄膜晶体管(T11)，以接入所述参考电压，且导通所述第二开关薄膜晶体管(T12)，以使所述双栅极驱动薄膜晶体管(T10)的底栅极进行放电；在所述数据写入阶段断开所述第一开关薄膜晶体管(T11)和所述第二开关薄膜晶体管(T12)，以接入所述数据信号(Data)；在所述发光阶段断开所述第一开关薄膜晶体管(T11)和所述第二开关薄膜晶体管(T12)，以驱动所述发光模块发光。
  3. 如权利要求2所述的像素驱动电路，其中，所述双栅极驱动薄膜晶体 管(T10)的源极接入所述第二电源电压(VSS)，其漏极与所述发光模块电连接；
    所述第一开关薄膜晶体管(T11)的栅极接入第一控制信号，其源极在所述初始化阶段接入所述高电位信号，且在所述阈值电压补偿阶段接入所述参考电压(Vref)，其漏极与所述双栅极驱动薄膜晶体管(T10)的顶栅极电连接；
    所述第二开关薄膜晶体管(T12)的栅极接入所述第一控制信号，其源极与所述双栅极驱动薄膜晶体管(T10)的漏极电连接，其漏极与所述双栅极驱动薄膜晶体管(T10)的底栅极电连接。
  4. 如权利要求3所述的像素驱动电路，其中，所述补偿驱动模块还包括第一电容(C1)和第二电容(C2)；
    所述第一电容(C1)的一端与所述双栅极驱动薄膜晶体管(T10)的顶栅极电连接，另一端与所述双栅极驱动薄膜晶体管(T10)的源极电连接，用以存储所述双栅极驱动薄膜晶体管(T10)的顶栅极的电位；
    所述第二电容(C2)的一端与所述双栅极驱动薄膜晶体管(T10)的底栅极电连接，另一端接地，用以存储所述双栅极驱动薄膜晶体管(T10)的底栅极的电位。
  5. 如权利要求1所述的像素驱动电路，其中，所述参考电压(Vref)为正电压或者负电压。
  6. 如权利要求1所述的像素驱动电路，其中，所述双栅极驱动薄膜晶体管(T10)包括N型氧化物薄膜晶体管、N型低温多晶硅薄膜晶体管、N型非晶硅薄膜晶体管和N型有机薄膜晶体管中的任意一种。
  7. 如权利要求1所述的像素驱动电路，其中，所述像素驱动电路还包括与所述补偿驱动模块电连接的数据写入模块；
    所述数据写入模块用于在所述数据写入阶段获取所述数据信号(Data)，并向所述补偿驱动模块输出所述数据信号(Data)。
  8. 如权利要求7所述的像素驱动电路，其中，所述数据写入模块包括第三开关薄膜晶体管(T13)；所述第三开关薄膜晶体管(T13)的栅极接入第二控制信号，其源极接入所述数据信号(Data)，其漏极与所述双栅极驱动薄膜晶体管(T10)的顶栅极电连接。
  9. 如权利要求8所述的像素驱动电路，其中，所述第一开关薄膜晶体管(T11)、所述第二开关薄膜晶体管(T12)和所述第三开关薄膜晶体管(T13)包括N型薄膜晶体管和P型薄膜晶体管中的任意一种。
  10. 如权利要求1所述的像素驱动电路，其中，所述像素驱动电路还包括与所述补偿驱动模块电连接的数据写入模块；
    所述数据写入模块用于在所述数据写入阶段向所述补偿驱动模块输出预存储的数据信号(Data)，且在所述发光阶段获取并存储下一帧所需的数据信号。
  11. 如权利要求10所述的像素驱动电路，其中，所述数据写入模块包括第三开关薄膜晶体管(T13)、第四开关薄膜晶体管(T14)和第三电容(C3)；
    所述数据写入模块用于在所述数据写入阶段，断开所述第三开关薄膜晶体管(T13)，导通所述第四开关薄膜晶体管(T14)，将所述第三电容(C3)中预存储的数据信号(Data)输出至所述双栅极驱动薄膜晶体管(T10)的顶栅极；在所述发光阶段，断开所述第四开关薄膜晶体管(T14)，导通所述第三开关薄膜晶体管(T13)，以获取下一帧的数据信号(Data)并存储至所述第三电容(C3)。
  12. 如权利要求11所述的像素驱动电路，其中，所述第三开关薄膜晶体管(T13)的栅极接入第二控制信号，其源极接入所述数据信号(Data)，其漏极与所述第四开关薄膜晶体管(T14)的源极电连接；所述第四开关薄膜晶体管(T14)的栅极接入第三控制信号，其漏极与所述双栅极驱动薄膜晶体管(T10)的顶栅极电连接；
    所述第三电容(C3)的一端与所述第四开关薄膜晶体管(T14)的源极电连接，另一端接地。
  13. 如权利要求12所述的像素驱动电路，其中，所述第一开关薄膜晶体管(T11)、所述第二开关薄膜晶体管(T12)、所述第三开关薄膜晶体管(T13)和所述第四开关薄膜晶体管(T14)包括N型薄膜晶体管和P型薄膜晶体管中的任意一种。
  14. 如权利要求1所述的像素驱动电路，其中，所述发光模块包括OLED发光器件或者Micro-LED发光器件。
  15. 一种显示面板，包括信号控制单元和多个像素单元，每个像素单元包括如权利要求1所述的像素驱动电路；所述信号控制单元与每个所述像素驱动电路电连接，为所述像素驱动电路提供控制信号。
  16. 如权利要求15所述的显示面板，其中，所述补偿驱动模块还包括第一开关薄膜晶体管(T11)和第二开关薄膜晶体管(T12)；
    所述补偿驱动模块还用于在所述初始化阶段导通所述第一开关薄膜晶体管(T11)，以接入所述高电位信号，且导通所述第二开关薄膜晶体管(T12)，以使所述高电位的第二电源电压(VSS)对所述双栅极驱动薄膜晶体管(T10)的底栅极进行充电；在所述阈值电压补偿阶段导通所述第一开关薄膜晶体管(T11)，以接入所述参考电压，且导通所述第二开关薄膜晶体管(T12)，以使所述双栅极驱动薄膜晶体管(T10)的底栅极进行放电；在所述数据写入阶段断开所述第一开关薄膜晶体管(T11)和所述第二开关薄膜晶体管(T12)，以接入所述数据信号(Data)；在所述发光阶段断开所述第一开关薄膜晶体管(T11)和所述第二开关薄膜晶体管(T12)，以驱动所述发光模块发光。
  17. 如权利要求16所述的显示面板，其中，所述双栅极驱动薄膜晶体管(T10)的源极接入所述第二电源电压(VSS)，其漏极与所述发光模块电连接；
    所述第一开关薄膜晶体管(T11)的栅极接入第一控制信号，其源极在所述初始化阶段接入所述高电位信号，且在所述阈值电压补偿阶段接入所述参考电压(Vref)，其漏极与所述双栅极驱动薄膜晶体管(T10)的顶栅极电连接；
    所述第二开关薄膜晶体管(T12)的栅极接入所述第一控制信号，其源极与所述双栅极驱动薄膜晶体管(T10)的漏极电连接，其漏极与所述双栅极驱动薄膜晶体管(T10)的底栅极电连接。
  18. 如权利要求17所述的显示面板，其中，所述补偿驱动模块还包括第一电容(C1)和第二电容(C2)；
    所述第一电容(C1)的一端与所述双栅极驱动薄膜晶体管(T10)的顶栅极电连接，另一端与所述双栅极驱动薄膜晶体管(T10)的源极电连接，用以存储所述双栅极驱动薄膜晶体管(T10)的顶栅极的电位；
    所述第二电容(C2)的一端与所述双栅极驱动薄膜晶体管(T10)的底栅极电连接，另一端接地，用以存储所述双栅极驱动薄膜晶体管(T10)的底栅 极的电位。
  19. 如权利要求15所述的显示面板，其中，所述像素驱动电路还包括与所述补偿驱动模块电连接的数据写入模块；
    所述数据写入模块用于在所述数据写入阶段获取所述数据信号(Data)，并向所述补偿驱动模块输出所述数据信号(Data)；或者，在所述数据写入阶段向所述补偿驱动模块输出预存储的数据信号(Data)，且在所述发光阶段获取并存储下一帧所需的数据信号。
  20. 如权利要求15所述的显示面板，其中，所述参考电压(Vref)为正电压或者负电压。
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