WO2019184916A1 - 像素电路及其驱动方法、显示装置 - Google Patents

像素电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2019184916A1
WO2019184916A1 PCT/CN2019/079714 CN2019079714W WO2019184916A1 WO 2019184916 A1 WO2019184916 A1 WO 2019184916A1 CN 2019079714 W CN2019079714 W CN 2019079714W WO 2019184916 A1 WO2019184916 A1 WO 2019184916A1
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Prior art keywords
circuit
transistor
sub
electrically connected
driving
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PCT/CN2019/079714
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English (en)
French (fr)
Inventor
吴忠山
蒲巡
毕鑫
郭建东
吴君辉
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京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Priority to US16/609,278 priority Critical patent/US11056063B2/en
Publication of WO2019184916A1 publication Critical patent/WO2019184916A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0238—Improving the black level

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, and a display device.
  • OLED displays are hotspots in the field of display. Compared with liquid crystal displays (LCDs), OLED displays have low energy consumption, self-illumination, wide viewing angle and fast response. advantage. Among them, the design of the pixel circuit is the core technical content of the OLED display, which has important research significance.
  • a pixel circuit including: a data write and compensation sub-circuit, a drive sub-circuit, an illumination control sub-circuit, and an illumination sub-circuit.
  • the data writing and compensating sub-circuit is electrically connected to the driving sub-circuit, the first control signal end, and the data voltage end, and configured to input the data signal outputted by the data voltage end to the driving under the control of the first control signal end.
  • the sub-circuit compensates for the threshold voltage of the driving sub-circuit.
  • the illumination control sub-circuit is electrically connected to the driving sub-circuit, the data writing and compensating sub-circuit, the second control signal end, the first voltage end and the second voltage end, and is configured to be controlled under the control of the second control signal end
  • the first voltage signal outputted by the voltage terminal is input to the driving sub-circuit and the data writing and compensating sub-circuit
  • the second voltage signal outputted by the second voltage terminal is input to the driving sub-circuit.
  • the driving sub-circuit is further electrically connected to the illuminating sub-circuit and configured to input a signal output from the illuminating control sub-circuit to the illuminating sub-circuit.
  • the illuminating sub-circuit is further electrically connected to the third voltage terminal and configured to emit light under the driving of the signal input by the driving sub-circuit and the third voltage signal outputted by the third voltage terminal.
  • the data writing and compensating sub-circuit includes: a first transistor, a gate of the first transistor is electrically connected to the first control signal terminal, and a first pole of the first transistor is electrically connected to the data voltage terminal, the first transistor The second pole is electrically connected to the driving sub-circuit; the second transistor, the gate of the second transistor is electrically connected to the first control signal end, the first pole of the second transistor is electrically connected to the light-emitting control sub-circuit, and the second pole of the second transistor The drive subcircuit is electrically connected.
  • the data write and compensation sub-circuit is further electrically coupled to the illuminating sub-circuit, configured to equalize the voltage across the illuminating sub-circuit under control of the first control signal terminal.
  • the data writing and compensating sub-circuit includes: a first transistor, a gate of the first transistor is electrically connected to the first control signal terminal, and a first pole of the first transistor is electrically connected to the data voltage terminal, the first transistor The second pole is electrically connected to the driving sub-circuit; the second transistor, the gate of the second transistor is electrically connected to the first control signal end, the first pole of the second transistor is electrically connected to the light-emitting control sub-circuit, and the second pole of the second transistor is electrically connected Driving a sub-circuit; a third transistor, a gate of the third transistor is electrically connected to the first control signal end, a first electrode of the third transistor is electrically connected to the driving sub-circuit, and a second electrode of the third transistor is electrically connected to the illuminating sub-circuit and the third Voltage terminal.
  • the driving sub-circuit includes: a storage capacitor, the first end of the storage capacitor electrically connects the data writing and compensating sub-circuit and the lighting control sub-circuit; the driving transistor, the gate of the driving transistor is electrically connected to the second of the storage capacitor And the data writing and compensating sub-circuit, the first pole of the driving transistor is electrically connected to the data writing and compensating sub-circuit and the lighting control sub-circuit, and the second pole of the driving transistor is electrically connected to the illuminating sub-circuit.
  • the illumination control sub-circuit includes: a fourth transistor, the gate of the fourth transistor is electrically connected to the second control signal terminal, the first pole of the fourth transistor is electrically connected to the first voltage terminal, and the second transistor is second The pole electrical connection data is written into the compensation sub-circuit and the driving sub-circuit; the fifth transistor, the fifth transistor has a gate electrically connected to the second control signal terminal, and the first electrode of the fifth transistor is electrically connected to the data writing and compensating sub-circuit and Driving the subcircuit, the second pole of the fifth transistor is electrically connected to the second voltage terminal.
  • the data writing and compensating sub-circuit includes: a first transistor, a gate of the first transistor is electrically connected to the first control signal terminal, a first pole of the first transistor is electrically connected to the data voltage terminal; and a second transistor is The gate of the second transistor is electrically connected to the first control signal terminal.
  • the driving sub-circuit includes: a storage capacitor, the first end of the storage capacitor is electrically connected to the second pole of the first transistor, the second end of the storage capacitor is electrically connected to the first pole of the second transistor; the driving transistor, the gate of the driving transistor is electrically connected The first pole of the second transistor and the second end of the storage capacitor, the first pole of the driving transistor is electrically connected to the second pole of the second transistor.
  • the illumination control sub-circuit includes: a fourth transistor, a gate of the fourth transistor is electrically connected to the second control signal terminal, a first electrode of the fourth transistor is electrically connected to the first voltage terminal, and a second electrode of the fourth transistor is electrically connected to the second transistor The second pole and the first pole of the driving transistor; the fifth transistor, the gate of the fifth transistor is electrically connected to the second control signal terminal, and the first pole of the fifth transistor is electrically connected to the second pole of the first transistor and the storage capacitor At the first end, the second pole of the fifth transistor is electrically connected to the second voltage terminal.
  • the data writing and compensating sub-circuit further includes: a third transistor, a gate of the third transistor is electrically connected to the first control signal end, and a first electrode of the third transistor is electrically connected to the second electrode of the driving transistor, The second pole of the third transistor is electrically connected to the third voltage terminal.
  • the transistors in the data write and compensation subcircuit are P-type transistors, and the transistors in the illumination control sub-circuit are N-type transistors.
  • the transistors in the data write and compensation sub-circuit are N-type transistors, and the transistors in the light-emitting control sub-circuit are P-type transistors.
  • a display device comprising a plurality of pixel circuits as described in the above technical solution.
  • a driving method of a pixel circuit is provided, which is configured to drive a pixel circuit as described in any one of the above aspects, wherein the driving method comprises: a time period of a frame of pictures including a pre-charging phase, a compensation phase, and Luminous stage.
  • the pre-charging phase the data writing and compensating sub-circuit is turned on under the control of the first control signal end, and the data signal outputted by the data voltage terminal is transmitted to the driving sub-circuit, and the lighting control sub-circuit is turned on under the control of the second control signal end. And transmitting the signal of the first voltage terminal to the driving sub-circuit to pre-charge the driving sub-circuit.
  • the data writing and compensation sub-circuit is turned on under the control of the first control signal terminal, and the threshold voltage is compensated for the driving sub-circuit.
  • the illuminating control sub-circuit is turned on under the control of the second control signal end, and the first voltage signal outputted by the first voltage terminal and the second voltage signal outputted by the second voltage terminal are input to the driving sub-circuit, the illuminator The circuit emits light under the driving of the driving signal outputted by the driving sub-circuit and the third voltage signal outputted by the third voltage terminal.
  • a voltage stabilization phase is also included between the compensation phase and the illumination phase.
  • the data writing and compensating sub-circuit is turned off under the control of the first control signal end, and the lighting control sub-circuit is turned off under the control of the second control signal end, and the signal in the driving sub-circuit remains unchanged.
  • the data writing and compensating sub-circuit is further electrically connected to the illuminating sub-circuit, the driving method comprising: in the pre-charging stage, the data writing and compensating sub-circuit is turned on under the control of the first control signal end, While the driver sub-circuit is pre-charging, the voltages at both ends of the control sub-circuit are controlled to be equal.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to the related art
  • FIG. 2 is a first schematic diagram of a pixel circuit in accordance with some embodiments of the present disclosure
  • FIG. 3 is a second schematic structural diagram of a pixel circuit in accordance with some embodiments of the present disclosure.
  • FIG. 4 is a first structural diagram of each sub-circuit of a pixel circuit, in accordance with some embodiments of the present disclosure
  • 5a is a second structural schematic diagram of each sub-circuit of a pixel circuit, in accordance with some embodiments of the present disclosure.
  • 5b is a third structural schematic diagram of each sub-circuit of a pixel circuit, in accordance with some embodiments of the present disclosure.
  • 6a is a first driving timing diagram of a pixel circuit in accordance with some embodiments of the present disclosure.
  • 6b is a second driving timing diagram of a pixel circuit in accordance with some embodiments of the present disclosure.
  • FIGS. 7-10 are schematic diagrams of stages in a driving process of a pixel circuit, in accordance with some embodiments of the present disclosure.
  • FIG. 11 is a flowchart of a method of driving a pixel circuit, in accordance with some embodiments of the present disclosure.
  • FIG. 12 is a schematic plan view of a display device in accordance with some embodiments of the present disclosure.
  • the pixel circuit in the OLED display is a 2T1C structure, that is, the pixel circuit includes two transistors T1 and Td, and one storage capacitor C, and the pixel circuit is driven by the 2T1C structure to drive the light emitting device.
  • D ie, OLED
  • the pixel circuit emits light to realize display of corresponding pixels.
  • the driving current I oled when the light emission luminance of the light emitting device D (i.e. OLED) flows depends on its own drive current I oled, i.e., the driving current I oled current flowing through the driving transistor Td, the driving current I oled may be expressed as: Wherein C OX is a dielectric constant of a channel insulating layer of the driving transistor Td, and ⁇ is a channel carrier mobility of the driving transistor Td, To drive the width to length ratio of the transistor Td, V GS is the gate-source voltage difference of the driving transistor Td, and V th is the threshold voltage of the driving transistor Td.
  • the drive current I oled is affected by four variables of W, L, V GS , and V th . Since W and L of the driving transistor Td of the pixel circuit of each pixel in the same display are identical, the luminance of the OLED is controlled by V GS and V th .
  • the OLED display substrate in the OLED display is large, it is difficult to ensure that the thickness of the semiconductor layer is uniform, which may result in different switching characteristics of transistors at different positions, that is, Vth of each transistor may be inconsistent, resulting in the same V GS .
  • the driving current I oled of each pixel is different, so that the brightness of each pixel is not uniform, which seriously affects the display effect.
  • Some embodiments of the present disclosure provide a pixel circuit 100 that includes a data write and compensation sub-circuit 10, an illumination control sub-circuit 20, a drive sub-circuit 30, and a illuminating sub-circuit 40, as shown in FIG.
  • the data writing and compensating sub-circuit 10, the electrical connection driving sub-circuit 30, the first control signal terminal S1 and the data voltage terminal Vdata are configured to be connected to the data voltage terminal Vdata under the control of the first control signal terminal S1.
  • the output data signal is input to the drive sub-circuit 30, and the drive sub-circuit 30 is compensated for the threshold voltage Vth.
  • the illumination control sub-circuit 20, the electrical connection driving sub-circuit 30, the data writing and compensating sub-circuit 10, the second control signal terminal S2, the first voltage terminal V1 and the second voltage terminal V2 are configured to be at the second control signal end. Under the control of S2, the first voltage signal outputted by the first voltage terminal V1 is input to the driving sub-circuit 30 and the data writing and compensating sub-circuit 10, and the second voltage signal outputted by the second voltage terminal V2 is input to the driving. Subcircuit 30.
  • the driving sub-circuit 30 is electrically connected to the illuminating sub-circuit 40 in addition to being electrically connected to the data writing and compensating sub-circuit 10 and the illuminating sub-circuit 20, and is configured to input a signal output from the illuminating control sub-circuit 20 to the illuminating light. Subcircuit 40.
  • the illuminating sub-circuit 40 is electrically connected to the third voltage terminal V3 in addition to the driving sub-circuit 30, and is configured to be a signal input by the driving sub-circuit 30 and a third voltage signal outputted by the third voltage terminal V3.
  • the drive is illuminated.
  • the illuminating sub-circuit 40 comprises a light emitting device, such as an OLED.
  • the pixel circuit 100 performs the compensation of the threshold voltage Vth on the driving sub-circuit 30 under the action of the data writing and compensating sub-circuit 10 and the lighting control sub-circuit 20, thereby eliminating the threshold voltage Vth and the driving current Ioled .
  • the effect is that the service life of the transistors in each of the driving sub-circuits 30 in the display panel is improved, and the problem that the display brightness of each pixel in the display panel is different due to the difference in the amount of drift of the threshold voltage Vth of different transistors can be avoided. Improves the uniformity of brightness between pixels and pixels.
  • the data write and compensation sub-circuit 10 is not electrically coupled to the illuminating sub-circuit 40.
  • the signal input from the first voltage terminal V1 is used to control the driving sub-circuit 30 to be turned off, so that the light-emitting sub-circuit 40 does not emit light.
  • the data write and compensation sub-circuit 10 includes a first transistor T1 and a second transistor T2.
  • the gate g 1 of the first transistor T1 is electrically connected to the first control signal terminal S1, the first pole a 1 of the first transistor T1 is electrically connected to the data voltage terminal Vdata, and the second pole b 1 of the first transistor T1 is electrically connected to be driven. Subcircuit 30.
  • the gate g 2 of the second transistor T2 is electrically connected to the first control signal terminal S1, the first pole a 2 of the second transistor T2 is electrically connected to the illumination control sub-circuit 20, and the second pole b 2 of the second transistor T2 is electrically connected to the driver. Circuit 30.
  • the data write and compensation sub-circuit 10 may also include a plurality of switching transistors in parallel with the first transistor T1, and/or a plurality of switching transistors in parallel with the second transistor T2.
  • the above is only an example of the specific structure of the data writing and compensating sub-circuit 10.
  • Other structures having the same function as the data writing and compensating sub-circuit 10 will not be further described herein, but all should belong to the protection of the present disclosure. range.
  • the data writing and compensating sub-circuit 10 is also electrically connected to the illuminating sub-circuit 40, and is configured to make the voltages at both ends of the illuminating sub-circuit 40 equal under the control of the first control signal terminal S1.
  • the illuminating sub-circuit 40 can emit light based on the electric field formed by the pressure difference across the illuminating sub-circuit 40.
  • the data writing and compensating sub-circuit 10 is connected to both ends of the illuminating sub-circuit 40 in the pre-charging phase of one frame, so that the voltages across the illuminating sub-circuit 40 are equal, and no electric field is generated, thereby generating illuminators. Circuit 40 does not illuminate.
  • the data writing and compensating sub-circuit 10 in the case where the data writing and compensating sub-circuit 10 is also electrically connected to the illuminating sub-circuit 40, the data writing and compensating sub-circuit 10 includes the first transistor T1 and the second transistor T2. In addition, a third transistor T3 is also included.
  • the third gate transistor T3 g 3 is electrically connected to a first terminal of a control signal Sl, a first electrode of the third transistor T3 is electrically connected to a 3 sub-driving circuit 30, a second electrode of the third transistor T3 is electrically connected to the light emitting sub b 3 Circuit 40 and third voltage terminal V3.
  • the connection relationship between the first transistor T1 and the second transistor T2 is described above with respect to the connection relationship of the first transistor T1 and the second transistor T2.
  • the data write and compensation sub-circuit 10 may also include a plurality of switching transistors in parallel with the third transistor T3.
  • the foregoing is only an example of the data writing and compensating sub-circuit 10.
  • the other structures having the same functions as the data writing and compensating sub-circuit 10 are not described herein again, but all should fall within the protection scope of the present disclosure.
  • the driving sub-circuit 30 includes a storage capacitor C and a driving transistor Td.
  • the first end c 1 of the storage capacitor C is electrically connected to the data writing and compensating sub-circuit 10 and the lighting control sub-circuit 20.
  • the gate g d of the driving transistor Td is electrically connected to the second terminal c 2 of the storage capacitor C and the data writing and compensating sub-circuit 10, and the first pole a d of the driving transistor Td is electrically connected to the data writing and compensating sub-circuit 10 and the light emitting the control sub-circuit 20, a second electrode of the driving transistor Td b d is electrically connected to the light emitting sub-circuit 40.
  • the driving sub-circuit 30 further includes a plurality of transistors in parallel with the driving transistor Td.
  • the above is only an example of the driving sub-circuit 30.
  • Other structures having the same function as the driving sub-circuit 30 will not be further described herein, but all should fall within the protection scope of the present disclosure.
  • the illumination control sub-circuit 20 includes a fourth transistor T4 and a fifth transistor T5.
  • the gate g 4 of the fourth transistor T4 is electrically connected to the second control signal terminal S2, the first pole a 4 of the fourth transistor T4 is electrically connected to the first voltage terminal V1, and the second pole b 4 of the fourth transistor T4 is electrically connected.
  • the data is written and compensated for the sub-circuit 10 and the drive sub-circuit 30.
  • the gate g 5 of the fifth transistor T5 is electrically connected to the second control signal terminal S2, and the first pole a 5 of the fifth transistor T5 is electrically connected to the data writing and compensating sub-circuit 10 and the driving sub-circuit 30, and the fifth transistor T5
  • the diode b 5 is electrically connected to the second voltage terminal V2.
  • the illumination control sub-circuit 20 may further include a plurality of switching transistors in parallel with the fourth transistor T4, and/or a plurality of switching transistors in parallel with the fifth transistor T5.
  • the foregoing is merely an illustration of the illumination control sub-circuit 20.
  • Other structures having the same functions as those of the illumination control sub-circuit 20 are not described herein again, but are all within the scope of the present disclosure.
  • the illuminating sub-circuit 40 includes a light emitting device D.
  • the anode d 1 of the light-emitting device D is electrically connected to the driving sub-circuit 30, and the cathode d 2 of the light-emitting device D is electrically connected to the third voltage terminal V3.
  • the light emitting device D is, for example, an OLED.
  • the illuminating sub-circuit 40 includes a light emitting device D.
  • the anode d 1 of the light-emitting device D is electrically connected to the driving sub-circuit 30 and the data writing and compensating sub-circuit 10, and the cathode d 2 of the light-emitting device D is electrically connected to the third voltage terminal V3.
  • the light emitting device D is, for example, an OLED.
  • a pixel circuit 100 data is written to the compensation circuit 10 again comprises: a first transistor T1, the gate g of the first transistor T1 is electrically connected to one end of a first control signal S1, the The first pole a 1 of the transistor T1 is electrically connected to the data voltage terminal Vdata; the second transistor T2, the gate g 2 of the second transistor T2 is electrically connected to the first control signal terminal S1.
  • the driving sub-circuit 30 includes a storage capacitor C.
  • the first end c 1 of the storage capacitor C is electrically connected to the second pole b 1 of the first transistor T1
  • the second end c 2 of the storage capacitor C is electrically connected to the first end of the second transistor T2 .
  • a 2 pole; driving transistor Td, the gate of the driving transistor Td g d is electrically connected to a first electrode of the second transistor T2, a 2 and a second terminal of the storage capacitor C c 2, a first electrode of the driving transistor Td is electrically connected to a d
  • the illumination control sub-circuit 20 includes: a fourth transistor T4, the gate g 4 of the fourth transistor T4 is electrically connected to the second control signal terminal V2, and the first pole a 4 of the fourth transistor T4 is electrically connected to the first voltage terminal V1, fourth The second pole b 4 of the transistor T4 is electrically connected to the second pole b 2 of the second transistor T2 and the first pole a d of the driving transistor Td; the fifth transistor T5, the gate g 5 of the fifth transistor T5 is electrically connected to the second control The signal terminal V2, the first pole a 5 of the fifth transistor T5 is electrically connected to the second pole b 1 of the first transistor T1 and the first terminal c 1 of the storage capacitor C, and the second pole b 5 of the fifth transistor T5 is electrically connected. Two voltage terminals V2.
  • the illuminating sub-circuit 40 includes a illuminating device D.
  • the anode d 1 of the illuminating device D is electrically connected to the second pole b d of the driving transistor Td, and the cathode d 2 of the illuminating device D is electrically connected to the third voltage terminal V3.
  • the pixel circuit 100 includes, in addition to the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the driving transistor Td, the storage capacitor C, and the light emitting device D. In addition to the third transistor T3.
  • the gate g 3 of the third transistor T3 is electrically connected to the first control signal terminal S1, and the first pole a 3 of the third transistor T3 is electrically connected to the second pole b d of the driving transistor Td and the anode d 1 of the light emitting device D,
  • the second pole b 3 of the third transistor T3 is electrically connected to the third voltage terminal V3 and the cathode d 2 of the light emitting device D.
  • the gate of the first transistor T1 is g 1 in FIG. 5a is electrically connected to the first control signal terminal S1, a first electrode electrically connected to a 1 terminal of the data voltage Vdata of the first transistor T1, the first transistor The second pole b 1 of T1 is electrically connected to the first point O.
  • the gate g 2 of the second transistor T2 is electrically connected to the first control signal terminal S1, the first pole a 2 of the second transistor T2 is electrically connected to the second point P, and the second pole b 2 of the second transistor T2 is electrically connected to the third point. Q.
  • the gate g 3 of the third transistor T3 is electrically connected to the first control signal terminal S1, the first pole a 3 of the third transistor T3 is electrically connected to the fourth point W, and the second pole b 3 of the third transistor T3 is electrically connected to the third voltage. End V3.
  • the first end c 1 of the storage capacitor C is electrically connected to the first point O, and the second end c 2 of the storage capacitor C is electrically connected to the third point Q.
  • a gate driving transistor Td is electrically connected to a third point Q
  • a first driving transistor Td is electrically connected to the second point of a d P
  • the second electrode of the driving transistor Td b d is electrically connected to a fourth point W.
  • the gate g 4 of the fourth transistor T4 is electrically connected to the second control signal terminal S2, the first pole a 4 of the fourth transistor T4 is electrically connected to the first voltage terminal V1, and the second pole b 4 of the fourth transistor T4 is electrically connected to the second Point P.
  • the gate g 5 of the fifth transistor T5 is electrically connected to the second control signal terminal S2, the first pole a 5 of the fifth transistor T5 is electrically connected to the first point O, and the second pole b 5 of the fifth transistor T5 is electrically connected to the second voltage End V2.
  • the anode d 1 of the light-emitting device D is electrically connected to the fourth point W, and the cathode d 2 of the light-emitting device D is electrically connected to the third voltage terminal V3.
  • the anode d 1 and the cathode d 2 of the light-emitting device D are electrically connected to the first pole a 3 and the second pole b 3 of the third transistor T3, respectively.
  • the pixel circuit 100 shown in FIG. 5a includes six transistors (T1 to T5, and Td) and one capacitor (C), that is, the pixel circuit 100 adopts a circuit structure of 6T1C.
  • the influence of the threshold voltage Vth on the driving current Ioled is directly eliminated, which not only stabilizes the signal in the pixel circuit 100, but also greatly improves the operating life of the transistor.
  • the 6T1C pixel circuit provided by the embodiments of the present disclosure has a simple structure, low cost, and no need for a new process, which can greatly improve the stability of the OLED driving circuit. Sex.
  • the transistors in the data write and compensation sub-circuit 10 of the pixel circuit 100 are P-type transistors, and the transistors in the illumination control sub-circuit 20 are N-type transistors.
  • the first transistor T1 and the second transistor T2 in the data writing and compensating sub-circuit 10 are both P-type transistors; as shown in FIG. 5a, the data writing and compensating sub-circuit 10
  • the first transistor T1, the second transistor T2, and the third transistor T3 are all P-type transistors.
  • the fourth transistor T4 and the fifth transistor T5 in the light emission control sub-circuit 20 are both N-type transistors.
  • the transistors in the data writing and compensating sub-circuit 10 of the pixel circuit 100 are N-type transistors, and the transistors in the light-emitting control sub-circuit 20 are all P-type transistors.
  • the pixel circuit 100 includes a plurality of N-type transistors and a plurality of P-type transistors, that is, the pixel circuit 100 has a hybrid structure, that is, the pixel circuit 100 adopts a CMOS (Complementary Metal Oxide Semiconductor) structure.
  • CMOS Complementary Metal Oxide Semiconductor
  • the OLED driver circuit design eliminates the influence of the threshold voltage Vth drift, and eliminates the problem of signal instability caused by the problem, so that the driving circuit design of the OLED is more stable, and the driving circuit design of the OLED in the related art is solved.
  • a single type (P-type or N-type only) transistor brings poor pixel circuit stability and poor uniformity.
  • the first embodiment of the present disclosure does not limit the types of transistors in the respective sub-circuits of the pixel circuit 100, that is, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor.
  • T4, the fifth transistor T5, and the driving transistor Td may be an N-type transistor or a P-type transistor.
  • the transistors in the data write and compensation sub-circuit 10 of the pixel circuit 100 are N-type transistors
  • the illumination control sub-circuit 20 The transistors (ie, the fourth transistor T4 and the fifth transistor T5) are P-type transistors; alternatively, the transistors in the data write and compensation sub-circuit 10 are P-type transistors, and the transistors in the light-emitting control sub-circuit 20 are N-type transistors.
  • the transistors in the data writing and compensating sub-circuit 10 are all P-type transistors
  • the transistors in the light-emission control sub-circuit 20 are all N-type transistors as an example.
  • the first pole a of the transistor in the pixel circuit 100 is the drain d and the second pole b is the source s; or the first pole a is the source s and the second pole b is the drain d.
  • the embodiments of the present disclosure do not limit this.
  • the transistors in the pixel circuit 100 described above are classified into an enhancement transistor and a depletion transistor depending on the manner in which the transistors are electrically conductive.
  • the embodiments of the present disclosure do not limit this.
  • the first voltage signal outputted by the first voltage terminal V1 is a high level VDD
  • the second voltage signal outputted by the second voltage terminal V2 is a low level
  • the third voltage signal outputted by the third voltage terminal V3 is at a low level.
  • the second voltage signal outputted by the second voltage terminal V2 and the third voltage signal output by the third voltage terminal V3 are at the same low level VSS, for example, the second voltage terminal V2 and the The three voltage terminals V3 are both grounded such that the second voltage signal and the third voltage signal are both ground signals.
  • the above-mentioned “high level” and “low level” only indicate the relative magnitude relationship between the input voltages.
  • the first voltage signal outputted by the first voltage terminal V1 is a low level
  • the second voltage signal outputted by the second voltage terminal V2 is a high level VDD.
  • the first voltage signal outputted by the first voltage terminal V1 is at a high level VDD, and the second voltage terminal V2 and the third voltage terminal V3 are both grounded, and the voltage signals of the two are VSS as an example.
  • the time of one frame of the pixel circuit 100 is divided into a precharge phase P1, a compensation phase P2, and an illumination phase P3.
  • the first control signal terminal S1 inputs a low level on signal
  • the second control signal terminal S2 inputs a high level on signal.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the driving transistor Td of the pixel circuit 100 are all turned on.
  • the first control signal terminal S1 inputs a low-level on signal, and controls the first transistor T1, the second transistor T2, and the third transistor T3 to be turned on, and the signal of the data voltage terminal Vdata is input to the first point O through the first transistor T1.
  • the second control signal terminal S2 inputs a high-level on signal, and controls the fourth transistor T4 and the fifth transistor T5 to be turned on, and the first voltage signal VDD outputted by the first voltage terminal V1 is input to the fourth transistor T4 and the second transistor T2.
  • the third point is Q.
  • the driving transistor Td is turned on under the control of the third point Q (of course, the driving transistor Td can also be turned off under the control of the third point Q).
  • the third transistor T3 is in an on state, since the first pole a 3 of the third transistor T3 is electrically connected to the anode d 1 of the light emitting device D, and the second pole b 3 of the third transistor T3 is electrically connected to the cathode d 2 of the light emitting device D, The voltages of the cathode d 2 and the anode d 1 of the light-emitting device D are equal, and the light-emitting device D does not emit light.
  • the pixel circuit 100 does not include the third transistor T3, the first voltage signal outputted by the first voltage terminal V1 is changed to a low level, so that the potential of the third point Q is a low level. Thereby, under the control of the third point Q, the driving transistor Td is turned off, ensuring that the light-emitting device D does not emit light in the pre-charging phase P1.
  • VDD is the supply voltage provided by a system external to pixel circuit 100.
  • the first control signal terminal S1 inputs a low level on signal
  • the second control signal terminal S2 inputs a low level off signal.
  • the equivalent circuit diagram of the pixel circuit 100 shown in FIG. 5a and FIG. 5b is as shown in FIG. 8.
  • the first transistor T1 is turned on
  • the second transistor T2 is turned on
  • the third transistor T3 is turned on
  • the driving transistor Td is turned on
  • the fourth transistor is turned on
  • T4 is turned off
  • the fifth transistor T5 is turned off (the transistor in the off state is indicated by "x").
  • the first control signal terminal S1 inputs a low-level turn-on signal, and controls the first transistor T1, the second transistor T2, and the third transistor T3 to be turned on, and the signal of the data voltage terminal Vdata is input to the first point O through the first transistor T1.
  • the second transistor T2 is turned on the gate of the driving transistor Td and a g d a d is electrically connected to a first electrode, i.e. the second point and the third point P Q electrically connected.
  • V W of the fourth point W is released, so that the voltage V W of the fourth point W is VSS + Voled.
  • Voled is the voltage at which the light-emitting device D does not emit light
  • Vth is the threshold voltage of the driving transistor Td.
  • VSS is the power supply voltage of the system external to the pixel circuit 100.
  • the first control signal terminal S1 inputs a high-level off signal
  • the second control signal terminal S2 inputs a high-level on signal.
  • the equivalent circuit diagram of the pixel circuit 100 shown in FIG. 5a and FIG. 5b is as shown in FIG. 10, the first transistor T1 is turned off, the second transistor T2 is turned off, the third transistor T3 is turned off, and the fourth transistor T4 is turned on, fifth.
  • the transistor T5 is turned on and the driving transistor Td is turned on.
  • the second control signal terminal S2 inputs a high-level on signal, controls the fifth transistor T5 to be turned on, and the second voltage signal outputted by the second voltage terminal V2 is output to the first point O through the fifth transistor T5.
  • point voltage O V O 0 transition, hopping ⁇ Vdata.
  • the voltage V Q of the third point Q also changes, V Q becomes Vth + VSS + Voled + Vdata, and the voltage V Q of the third point Q controls the driving transistor Td to be turned on.
  • the second control signal terminal S2 inputs a high-level turn-on signal, and simultaneously controls the fourth transistor T4 to be turned on, and the first voltage signal voltage (VDD) outputted by the first voltage terminal V1 is input to the driving transistor Td through the fourth transistor T4, and the light emitting device D emits light under the driving of the driving signal output from the driving transistor Td and the third voltage signal (VSS) outputted from the third voltage terminal V3.
  • VDD voltage signal voltage
  • VSS third voltage signal
  • the driving transistor Td is an N-type transistor
  • the N-type transistor is in a saturated conduction state when Vgs-Vth ⁇ Vds, so when the driving transistor Td, that is, Vgs-Vth ⁇ Vds, the driving transistor Td can be in a saturated on state.
  • Vgs is the gate-to-source voltage difference of the driving transistor Td
  • Vds is the drain-source voltage difference of the driving transistor Td.
  • C OX is a dielectric constant of a channel insulating layer of the driving transistor Td
  • ⁇ is a channel carrier mobility of the driving transistor Td
  • the driving current I oled only has its own structure with the driving transistor Td (the structure itself determines C OX , ⁇ , And the data signal outputted by the data voltage terminal Vdata is related to the threshold voltage Vth of the driving transistor Td, thereby eliminating the influence of the threshold voltage Vth of the driving transistor Td on the luminance of the light emitting device D, and improving the brightness of the light emitting device D. Uniformity.
  • VSS term is not included in the drive current Ioled of the drive transistor Td, the problem of display unevenness due to the voltage drop on the VSS signal line can be solved.
  • a voltage stabilization phase P2' is also included between the compensation phase P2 and the illumination phase P3.
  • the first control signal terminal S1 inputs a high-level off signal
  • the second control signal terminal S2 inputs a low-level off signal.
  • the equivalent circuit diagram of the pixel circuit 100 shown in FIGS. 5a and 5b is as shown in FIG. 9, the first transistor T1 is turned off, the second transistor T2 is turned off, the third transistor T3 is turned off, the fourth transistor T4 is turned off, and the fifth transistor Transistor T5 is turned off.
  • the signal of the data signal terminal Vdata is, for example, a high level signal as shown in Fig. 6a or, for example, a low level signal as shown in Fig. 6b.
  • the first control signal terminal S1 inputs a high-level off signal, and controls the first transistor T1 to be turned off, the second transistor T2 to be turned off, and the third transistor T3 to be turned off.
  • the second control signal terminal S2 inputs a low-level cutoff signal, and controls the fourth transistor T4 and the fifth transistor T5 to be turned off.
  • the voltage V O of the first point O is maintained at Vdata
  • the voltage V Q of the third point Q is maintained at Vth + VSS + Voled.
  • the voltage V O of the first point O is Vdata
  • the third transistor T3 is not included in the pixel circuit 100, and the other transistors in the pixel circuit 100 (ie, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the driving transistor Td)
  • the other transistors in the pixel circuit 100 ie, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the driving transistor Td
  • Some embodiments of the present disclosure provide a display device that includes a plurality of pixel circuits 100 as shown in FIG.
  • the display device 200 is specifically a product or component having any display function, such as an OLED display, a digital photo frame, a mobile phone, a tablet computer, and a navigator.
  • any display function such as an OLED display, a digital photo frame, a mobile phone, a tablet computer, and a navigator.
  • the display device 200 provided by the embodiment of the present disclosure includes a plurality of pixels Pixel, the plurality of pixels Pixel are arranged in an array, and each of the plurality of pixels Pixel includes any one of the above embodiments.
  • the display device 200 provided by the embodiment of the present disclosure has the same advantageous effects as the pixel circuit 100 provided by the foregoing embodiments of the present disclosure. Since the pixel circuit 100 has been described in detail in the foregoing embodiments, details are not described herein again.
  • An embodiment of the present disclosure provides a driving method of the pixel circuit 100.
  • the timing of a frame of a picture sequentially includes a pre-charging phase P1, a compensation phase P2, and an illumination phase P3.
  • the driving method includes the following steps:
  • the data writing and compensating sub-circuit 10 in a pre-charging phase P1 of a frame, the data writing and compensating sub-circuit 10 is turned on under the control of the first control signal terminal S1, and the data signal outputted by the data voltage terminal Vdata is transmitted to the driving sub-circuit 30, and the illumination control is performed.
  • the sub-circuit 20 is turned on under the control of the second control signal terminal S2, and transmits the first voltage signal outputted from the first voltage terminal V1 to the driving sub-circuit 30 to pre-charge the driving sub-circuit 30.
  • the first control signal terminal S1 inputs a low-level on signal, and controls the first transistor T1 to be turned on and the second transistor T2 to be turned on.
  • the second control signal terminal S2 inputs a high-level on signal, controls the fourth transistor T4 to be turned on, and the fifth transistor T5 is turned on to pre-charge both ends of the storage capacitor C (ie, the first point O and the third point Q).
  • the data write and compensation sub-circuit 10 is also electrically coupled to the illuminating sub-circuit 40.
  • the data writing and compensating sub-circuit 10 is turned on under the control of the first control signal terminal S1, and while the driving sub-circuit 30 is precharged, two of the illuminating sub-circuits 40 can be controlled.
  • the voltages at the terminals are equal so that the illuminating sub-circuit 40 does not illuminate at this stage.
  • the data writing and compensating sub-circuit 10 includes a first transistor T1 and a second transistor T2, and further includes a third transistor T3.
  • the first control signal terminal S1 inputs a low-level turn-on signal, controls the first transistor T1 to be turned on, and charges the first point O; and simultaneously controls the third transistor T3 to turn on, so that the voltages of the two electrodes of the light-emitting device D are equal, thereby avoiding the light-emitting device D. Glowing.
  • the data writing and compensating sub-circuit 10 is turned on under the control of the first control signal terminal S1, and the driving sub-circuit 30 is compensated for the threshold voltage Vth.
  • the first control signal terminal S1 inputs a low-level on signal, and controls the first transistor T1, the second transistor T2, and the third transistor T3 to be turned on, and the signal of the data voltage terminal Vdata passes through A transistor T1 is input to the first point O, and the second transistor T2 is turned on to electrically connect the gate g d of the driving transistor Td and the first pole a d , thereby releasing the voltages of the third point Q and the fourth point W, thereby realizing The compensation of the threshold voltage Vth of the sub-circuit 30 is driven.
  • the light-emitting control sub-circuit 20 in the light-emitting phase P3 of one frame, the light-emitting control sub-circuit 20 is turned on under the control of the second control signal terminal S2, and the first voltage signal outputted by the first voltage terminal V1 and the second voltage terminal V2 are output.
  • the two voltage signals are input to the driving sub-circuit 30, and the light-emitting sub-circuit 40 emits light under the driving of the driving signal output from the driving sub-circuit 30 and the third voltage signal outputted from the third voltage terminal V3.
  • the second control signal terminal S2 inputs a high-level on signal, and controls the fourth transistor T4 and the fifth transistor T5 to be turned on, and the second voltage signal outputted by the second voltage terminal V2 is
  • the fifth transistor T5 is transmitted to the first point O, and the bootstrap action of the storage capacitor C causes the third electrically controlled driving transistor Td to be turned on.
  • the second voltage signal outputted by the first voltage terminal V1 is transmitted to the driving transistor Td via the fourth transistor T4, and is transmitted to the anode d 1 of the light emitting device D via the driving transistor Td, and the third voltage signal outputted by the third voltage terminal V3. It is transmitted to the cathode d 2 of the light-emitting device D to drive the light-emitting device D to emit light.
  • the voltage stabilization phase P2' is further included, and the driving method of the pixel circuit 100 further includes the following steps:
  • the data writing and compensating sub-circuit 10 is turned off under the control of the first control signal terminal V1, and the lighting control sub-circuit 20 is also turned off under the control of the second control signal V2. Therefore, the signal in the drive sub-circuit 30 remains unchanged.
  • the first control signal terminal S1 inputs a high-level cut-off signal
  • the second control signal terminal S2 inputs a low-level cut-off signal
  • the four transistors T4 are turned off and the fifth transistor T5 is turned off, so that the voltage across the storage capacitor C remains unchanged, that is, the voltages at the first point O and the third point Q are the same as those at the compensation phase P2.

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Abstract

一种像素电路，包括数据写入与补偿子电路、驱动子电路、发光控制子电路及发光子电路。数据写入与补偿子电路分别连接驱动子电路、第一控制信号端及数据电压端，被配置为将数据电压端所输出的数据信号输入至驱动子电路，并对驱动子电路进行阈值电压的补偿；发光控制子电路连接驱动子电路、数据写入与补偿子电路、第二控制信号端、第一电压端及第二电压端，被配置为将第一电压端所输出的第一电压信号输入至驱动子电路和数据写入与补偿子电路，将第二电压端所输出的第二电压信号输入至驱动子电路；驱动子电路还连接发光子电路，被配置为将发光控制子电路输出的信号输入至发光子电路；发光子电路还与第三电压端电连接，被配置为进行发光。

Description

像素电路及其驱动方法、显示装置
本申请要求于2018年03月28日提交中国专利局、申请号为201810264933.X、申请名称为“一种像素电路及其驱动方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路及其驱动方法、显示装置。
背景技术
有机电致发光二极管(Organic Light Emitting Diode，OLED)显示器是目前显示领域的热点，与液晶显示器(Liquid Crystal Display，LCD)相比，OLED显示器具有低能耗、自发光、宽视角及响应速度快等优点。其中，像素电路的设计是OLED显示器的核心技术内容，具有重要的研究意义。
发明内容
一方面，提供一种像素电路，包括：数据写入与补偿子电路、驱动子电路、发光控制子电路、以及发光子电路。数据写入与补偿子电路，与驱动子电路、第一控制信号端、以及数据电压端电连接，被配置为在第一控制信号端的控制下，将数据电压端所输出的数据信号输入至驱动子电路，并对驱动子电路进行阈值电压的补偿。发光控制子电路，与驱动子电路、数据写入与补偿子电路、第二控制信号端、第一电压端以及第二电压端电连接，被配置为在第二控制信号端的控制下，将第一电压端所输出的第一电压信号输入至驱动子电路和数据写入与补偿子电路，将第二电压端所输出的第二电压信号输入至驱动子电路。驱动子电路，还与发光子电路电连接，被配置为将发光控制子电路所输出的信号输入至发光子电路。发光子电路，还与第三电压端电连接，被配置为在驱动子电路所输入的信号和第三电压端所输出的第三电压信号的驱动下进行发光。
在一些实施例中，数据写入与补偿子电路包括：第一晶体管，第一晶体管的栅极电连接第一控制信号端，第一晶体管的第一极电连接数据电压端，第一晶体管的第二极电连接所述驱动子电路；第二晶体管，第二晶体 管的栅极电连接第一控制信号端，第二晶体管的第一极电连接发光控制子电路，第二晶体管的第二极电连接所述驱动子电路。
在一些实施例中，数据写入与补偿子电路还与发光子电路电连接，被配置为在第一控制信号端的控制下，使发光子电路的两端的电压相等。
在一些实施例中，数据写入与补偿子电路包括：第一晶体管，第一晶体管的栅极电连接第一控制信号端，第一晶体管的第一极电连接数据电压端，第一晶体管的第二极电连接驱动子电路；第二晶体管，第二晶体管的栅极电连接第一控制信号端，第二晶体管的第一极电连接发光控制子电路，第二晶体管的第二极电连接驱动子电路；第三晶体管，第三晶体管的栅极电连接第一控制信号端，第三晶体管的第一极电连接驱动子电路，第三晶体管的第二极电连接发光子电路和第三电压端。
在一些实施例中，驱动子电路包括：存储电容，存储电容的第一端电连接数据写入与补偿子电路和发光控制子电路；驱动晶体管，驱动晶体管的栅极电连接存储电容的第二端和数据写入与补偿子电路，驱动晶体管的第一极电连接数据写入与补偿子电路和发光控制子电路，驱动晶体管的第二极电连接发光子电路。
在一些实施例中，发光控制子电路包括：第四晶体管，第四晶体管的栅极电连接第二控制信号端，第四晶体管的第一极电连接第一电压端，第四晶体管的第二极电连接数据写入与补偿子电路和驱动子电路；第五晶体管，第五晶体管的栅极电连接第二控制信号端，第五晶体管的第一极电连接数据写入与补偿子电路和驱动子电路，第五晶体管的第二极电连接第二电压端。
在一些实施例中，数据写入与补偿子电路包括：第一晶体管，第一晶体管的栅极电连接第一控制信号端，第一晶体管的第一极电连接数据电压端；第二晶体管，第二晶体管的栅极电连接第一控制信号端。
驱动子电路包括：存储电容，存储电容的第一端电连接第一晶体管的第二极，存储电容的第二端电连接第二晶体管的第一极；驱动晶体管，驱动晶体管的栅极电连接第二晶体管的第一极和存储电容的第二端，驱动晶体管的第一极电连接第二晶体管的第二极。
发光控制子电路包括：第四晶体管，第四晶体管的栅极电连接第二控制信号端，第四晶体管的第一极电连接第一电压端，第四晶体管的第二极电连接第二晶体管的第二极和驱动晶体管的第一极；第五晶体管，第五晶 体管的栅极电连接第二控制信号端，第五晶体管的第一极电连接第一晶体管的第二极和存储电容的第一端，第五晶体管的第二极电连接第二电压端。
在一些实施例中，数据写入与补偿子电路还包括：第三晶体管，第三晶体管的栅极电连接第一控制信号端，第三晶体管的第一极电连接驱动晶体管的第二极，第三晶体管的第二极电连接第三电压端。
在一些实施例中，数据写入与补偿子电路中的晶体管为P型晶体管，发光控制子电路中的晶体管为N型晶体管。或者，数据写入与补偿子电路中的晶体管为N型晶体管，发光控制子电路中的晶体管为P型晶体管。
第二方面，提供一种显示装置，包括多个如上述技术方案中所述的像素电路。
第三方面，提供一种像素电路的驱动方法，被配置为驱动如上述任一技术方案中所述的像素电路，所述驱动方法包括：一帧画面的时间依次包括预充电阶段、补偿阶段和发光阶段。在预充电阶段，数据写入与补偿子电路在第一控制信号端的控制下开启，将数据电压端所输出的数据信号传输至驱动子电路，发光控制子电路在第二控制信号端的控制下开启，将第一电压端的信号传输至驱动子电路，对驱动子电路进行预充电。在补偿阶段，数据写入与补偿子电路在第一控制信号端的控制下开启，对驱动子电路进行阈值电压的补偿。在发光阶段，发光控制子电路在第二控制信号端的控制下开启，将第一电压端所输出的第一电压信号和第二电压端所输出的第二电压信号输入至驱动子电路，发光子电路在驱动子电路所输出的驱动信号和第三电压端所输出的第三电压信号的驱动下发光。
在一些实施例中，在补偿阶段和发光阶段之间，还包括稳压阶段。在稳压阶段，数据写入与补偿子电路在第一控制信号端的控制下关闭，发光控制子电路在第二控制信号端的控制下关闭，驱动子电路中的信号保持不变。
在一些实施例中，数据写入与补偿子电路还与发光子电路电连接，所述驱动方法包括：在预充电阶段，数据写入与补偿子电路在第一控制信号端的控制下开启，对驱动子电路进行预充电的同时，控制发光子电路的两端的电压相等。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅 是本公开的一些实施例，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。
图1为根据相关技术的一种像素电路的结构示意图；
图2为根据本公开的一些实施例的像素电路的第一种结构示意图；
图3为根据本公开的一些实施例的像素电路的第二种结构示意图；
图4为根据本公开的一些实施例的像素电路的各子电路的第一种结构示意图；
图5a为根据本公开的一些实施例的像素电路的各子电路的第二种结构示意图；
图5b为根据本公开的一些实施例的像素电路的各子电路的第三种结构示意图；
图6a为根据本公开的一些实施例的像素电路的第一种驱动时序图；
图6b为根据本公开的一些实施例的像素电路的第二种驱动时序图；
图7～图10为根据本公开的一些实施例的像素电路的驱动过程中各阶段的示意图；
图11为根据本公开的一些实施例的像素电路的驱动方法的流程图；
图12为根据本公开的一些实施例的显示装置的平面示意图。
具体实施方式
下面将结合附图，对本公开的一些实施例进行描述。显然，所描述的实施例仅仅是本公开的一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
如图1所示，在相关技术中，OLED显示器中的像素电路为2T1C的结构，即像素电路包括两个晶体管T1和Td，及1个存储电容C，利用该2T1C结构的像素电路驱动发光器件D(即OLED)进行发光，进而实现相应像素的显示。
其中，发光器件D(即OLED)发光时的亮度取决于流过其自身的驱动电流I oled，驱动电流I oled也即流过驱动晶体管Td的电流，驱动电流I oled可表示为：
Figure PCTCN2019079714-appb-000001
其中，C OX为驱动晶体管Td的沟道绝缘层的介电常数，μ为驱动晶体管Td的沟道载流子迁移率，
Figure PCTCN2019079714-appb-000002
为驱动晶体管Td的宽长比，V GS为驱动晶体管Td的栅极与源极的压差，V th为驱动晶体管Td的阈值电压。由于C OX和μ为常数，因此驱动电流I oled会受到W、 L、V GS、V th四个变量的影响。由于同一显示器中各像素的像素电路的驱动晶体管Td的W和L是一致的，因此OLED的发光亮度由V GS和V th控制。
由于OLED显示器中OLED显示基板较大，工艺很难保证半导体层厚度一致，这会导致不同位置的晶体管的开关特性不同，即各个晶体管的V th会不一致，从而导致在相同V GS的情况下，各像素的驱动电流I oled不一样，使得各像素的亮度不均一，严重影响显示效果。
本公开的一些实施例提供一种像素电路100，如图2所示，该像素电路100包括数据写入与补偿子电路10、发光控制子电路20、驱动子电路30以及发光子电路40。
其中，数据写入与补偿子电路10，电连接驱动子电路30、第一控制信号端S1以及数据电压端Vdata，被配置为在第一控制信号端S1的控制下，将数据电压端Vdata所输出的数据信号输入至驱动子电路30，并对驱动子电路30进行阈值电压Vth的补偿。
发光控制子电路20，电连接驱动子电路30、数据写入与补偿子电路10、第二控制信号端S2、第一电压端V1以及第二电压端V2，被配置为在第二控制信号端S2的控制下，将第一电压端V1所输出的第一电压信号输入至驱动子电路30和数据写入与补偿子电路10，将第二电压端V2所输出的第二电压信号输入至驱动子电路30。
驱动子电路30，除与数据写入与补偿子电路10及发光控制子电路20电连接外，还与发光子电路40电连接，被配置为将发光控制子电路20所输出的信号输入至发光子电路40。
发光子电路40，除与驱动子电路30电连接外，还与第三电压端V3电连接，被配置为在驱动子电路30所输入的信号和第三电压端V3所输出的第三电压信号的驱动下进行发光。示例性的，发光子电路40包括发光器件，发光器件例如为OLED。
上述像素电路100，在数据写入与补偿子电路10和发光控制子电路20共同的作用下，对驱动子电路30进行了阈值电压Vth的补偿，从而消除了阈值电压Vth对驱动电流I oled的影响，提高了显示面板中各驱动子电路30中的晶体管的使用寿命，并且可以避免因不同晶体管的阈值电压Vth的漂移量不同，而造成的显示面板中各像素的显示亮度存在差异的问题，提高了像素和像素之间亮度的均匀性。
在一些实施例中，请再次参见图2，数据写入与补偿子电路10不与 发光子电路40电连接。在像素电路100的驱动过程中，在一帧的预充电阶段，为避免发光子电路40发光，利用第一电压端V1输入的信号控制驱动子电路30关闭，从而使发光子电路40不发光。
在一些实施例中，如图4所示，数据写入与补偿子电路10包括第一晶体管T1和第二晶体管T2。
其中，第一晶体管T1的栅极g 1电连接第一控制信号端S1，第一晶体管T1的第一极a 1电连接数据电压端Vdata，第一晶体管T1的第二极b 1电连接驱动子电路30。
第二晶体管T2的栅极g 2电连接第一控制信号端S1，第二晶体管T2的第一极a 2电连接发光控制子电路20，第二晶体管T2的第二极b 2电连接驱动子电路30。
作为一些可能的设计，数据写入与补偿子电路10还可以包括与第一晶体管T1并联的多个开关晶体管，和/或，与第二晶体管T2并联的多个开关晶体管。上述仅仅是对数据写入与补偿子电路10的具体结构的举例说明，其他与该数据写入与补偿子电路10功能相同的结构在此不再一一赘述，但都应当属于本公开的保护范围。
进一步的，如图3所示，数据写入与补偿子电路10还电连接发光子电路40，被配置为在第一控制信号端S1的控制下，使发光子电路40的两端的电压相等。
此处，基于发光子电路40两端的压差形成的电场，发光子电路40能够发光。在像素电路100的驱动过程中，一帧的预充电阶段，数据写入与补偿子电路10连通发光子电路40的两端，使发光子电路40两端的电压相等，没有电场产生，从而发光子电路40不发光。
在一些实施例中，如图5a所示，数据写入与补偿子电路10还电连接发光子电路40的情况下，数据写入与补偿子电路10除包括第一晶体管T1和第二晶体管T2外，还包括第三晶体管T3。
其中，第三晶体管T3的栅极g 3电连接第一控制信号端S1，第三晶体管T3的第一极a 3电连接驱动子电路30，第三晶体管T3第二极b 3电连接发光子电路40和第三电压端V3。第一晶体管T1和第二晶体管T2的连接关系参见上面关于第一晶体管T1和第二晶体管T2的连接关系的描述。
作为一些可能的设计，数据写入与补偿子电路10还可以包括与第三 晶体管T3并联的多个开关晶体管。上述仅仅是对数据写入与补偿子电路10的举例说明，其他与该数据写入与补偿子电路10功能相同的结构在此不再一一赘述，但都应当属于本公开的保护范围。
如图4和图5a所示，驱动子电路30包括存储电容C和驱动晶体管Td。
其中，存储电容C的第一端c 1电连接数据写入与补偿子电路10和发光控制子电路20。
驱动晶体管Td的栅极g d电连接存储电容C的第二端c 2和数据写入与补偿子电路10，驱动晶体管Td的第一极a d电连接数据写入与补偿子电路10和发光控制子电路20，驱动晶体管Td的第二极b d电连接发光子电路40。
作为一些可能的设计，驱动子电路30还包括与驱动晶体管Td并联的多个晶体管。上述仅仅是对驱动子电路30的举例说明，其他与该驱动子电路30功能相同的结构在此不再一一赘述，但都应当属于本公开的保护范围。
在一些实施例中，如图4和图5a所示，发光控制子电路20包括第四晶体管T4和第五晶体管T5。
其中，第四晶体管T4的栅极g 4电连接第二控制信号端S2，第四晶体管T4的第一极a 4电连接第一电压端V1，第四晶体管T4的第二极b 4电连接数据写入与补偿子电路10和驱动子电路30。
第五晶体管T5的栅极g 5电连接第二控制信号端S2，第五晶体管T5的第一极a 5电连接数据写入与补偿子电路10和驱动子电路30，第五晶体管T5的第二极b 5电连接第二电压端V2。
作为一些可能的设计，发光控制子电路20还可以包括与第四晶体管T4并联的多个开关晶体管，和/或，与第五晶体管T5并联的多个开关晶体管。上述仅仅是对发光控制子电路20的举例说明，其他与该发光控制子电路20功能相同的结构在此不再一一赘述，但都应当属于本公开的保护范围。
在一些实施例中，如图4所示，发光子电路40包括发光器件D。其中，发光器件D的阳极d 1电连接驱动子电路30，发光器件D的阴极d 2电连接第三电压端V3。发光器件D例如为OLED。
在另一些实施例中，如图5所示，发光子电路40包括发光器件D。 其中，发光器件D的阳极d 1电连接驱动子电路30和数据写入与补偿子电路10，发光器件D的阴极d 2电连接第三电压端V3。发光器件D例如为OLED。
基于上面对像素电路100的各子电路的结构的介绍，下面示例性的介绍像素电路100的具体结构。
在一些示例中，请再次参见图4，像素电路100中，数据写入与补偿子电路10包括：第一晶体管T1，第一晶体管T1的栅极g 1电连接第一控制信号端S1，第一晶体管T1的第一极a 1电连接数据电压端Vdata；第二晶体管T2，第二晶体管T2的栅极g 2电连接第一控制信号端S1。
驱动子电路30包括：存储电容C，存储电容C的第一端c 1电连接第一晶体管T1的第二极b 1，存储电容C的第二端c 2电连接第二晶体管T2的第一极a 2；驱动晶体管Td，驱动晶体管Td的栅极g d电连接第二晶体管T2的第一极a 2和存储电容C的第二端c 2，驱动晶体管Td的第一极a d电连接第二晶体管T2的第二极b 2。
发光控制子电路20包括：第四晶体管T4，第四晶体管T4的栅极g 4电连接第二控制信号端V2，第四晶体管T4的第一极a 4电连接第一电压端V1，第四晶体管T4的第二极b 4电连接第二晶体管T2的第二极b 2和驱动晶体管Td的第一极a d；第五晶体管T5，第五晶体管T5的栅极g 5电连接第二控制信号端V2，第五晶体管T5的第一极a 5电连接第一晶体管T1的第二极b 1和存储电容C的第一端c 1，第五晶体管T5的第二极b 5电连接第二电压端V2。
发光子电路40包括：发光器件D，发光器件D的阳极d 1电连接驱动晶体管Td的第二极b d，发光器件D的阴极d 2电连接第三电压端V3。
在另外一些示例中，请再次参见图5a，像素电路100中，除包括第一晶体管T1、第二晶体管T2、第四晶体管T4、第五晶体管T5、驱动晶体管Td、存储电容C和发光器件D以外，还包括第三晶体管T3。
其中，第三晶体管T3的栅极g 3电连接第一控制信号端S1，第三晶体管T3的第一极a 3电连接驱动晶体管Td的第二极b d和发光器件D的阳极d 1，第三晶体管T3的第二极b 3电连接第三电压端V3和发光器件D的阴极d 2。
需要进一步说明的是，如图5a所示，第一晶体管T1的栅极g 1电连接第一控制信号端S1，第一晶体管T1的第一极a 1电连接数据电压端 Vdata，第一晶体管T1的第二极b 1电连接第一点O。
第二晶体管T2的栅极g 2电连接第一控制信号端S1，第二晶体管T2的第一极a 2电连接第二点P，第二晶体管T2的第二极b 2电连接第三点Q。
第三晶体管T3的栅极g 3电连接第一控制信号端S1，第三晶体管T3的第一极a 3电连接第四点W，第三晶体管T3的第二极b 3电连接第三电压端V3。
存储电容C的第一端c 1电连接第一点O，存储电容C第二端c 2电连接第三点Q。
驱动晶体管Td的栅极g d电连接第三点Q，驱动晶体管Td的第一极a d电连接第二点P，驱动晶体管Td的第二极b d电连接第四点W。
第四晶体管T4的栅极g 4电连接第二控制信号端S2，第四晶体管T4的第一极a 4电连接第一电压端V1，第四晶体管T4的第二极b 4电连接第二点P。
第五晶体管T5的栅极g 5电连接第二控制信号端S2，第五晶体管T5的第一极a 5电连接第一点O，第五晶体管T5的第二极b 5电连接第二电压端V2。
发光器件D的阳极d 1电连接第四点W，发光器件D的阴极d 2电连接第三电压端V3。发光器件D的阳极d 1和阴极d 2分别电连接第三晶体管T3的第一极a 3和第二极b 3。
图5a所示出的像素电路100中包括六个晶体管(T1～T5、及Td)和一个电容(C)，即像素电路100采用6T1C的电路结构。这样，一方面，直接消除了阈值电压Vth对驱动电流I oled的影响，不仅使得像素电路100内的信号稳定，而且大大提高了晶体管的工作寿命。另一方面，相比相关技术中诸如7T1C、7T2C、8T1C等的像素电路，本公开实施例所提供的6T1C的像素电路结构简单，成本低，无需新增工艺，可以大大提高OLED驱动电路的稳定性。
在一些实施例中，像素电路100的数据写入与补偿子电路10中的晶体管为P型晶体管，发光控制子电路20中的晶体管为N型晶体管。示例性的，如图4所示，数据写入与补偿子电路10中的第一晶体管T1和第二晶体管T2均为P型晶体管；如图5a所示，数据写入与补偿子电路10中的第一晶体管T1、第二晶体管T2和第三晶体管T3均为P型晶体 管。发光控制子电路20中的第四晶体管T4和第五晶体管T5均为N型晶体管。
或者，像素电路100的数据写入与补偿子电路10中的晶体管均为N型晶体管，发光控制子电路20中的晶体管均为P型晶体管。
这样，像素电路100中包括多个N型晶体管和多个P型晶体管，即像素电路100为混合型结构，也就是说，像素电路100采用CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)结构的OLED驱动电路设计，消除了阈值电压Vth漂移的影响，也就消除了由此所引起的信号不稳定的问题，使得OLED的驱动电路设计更稳定，解决了相关技术中OLED的驱动电路设计采用单一类型(仅P型或仅N型)的晶体管所带来的像素电路稳定性不佳，均一性差的问题。
基于上述对像素电路100的描述，以下结合图5a、图5b、图6a、图6b、图7～图10对像素电路100的具体驱动过程进行详细的说明。
需要说明的是，第一、本公开的实施例对像素电路100的各个子电路中的晶体管的类型不做限定，即上述第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5以及驱动晶体管Td可以是为N型晶体管或者P型晶体管。
在一些实施例中，像素电路100的数据写入与补偿子电路10中的晶体管(即第一晶体管T1、第二晶体管T2及第三晶体管T3)为N型晶体管，发光控制子电路20中的晶体管(即第四晶体管T4和第五晶体管T5)为P型晶体管；或者，数据写入与补偿子电路10中的晶体管为P型晶体管，发光控制子电路20中的晶体管为N型晶体管。
以下以数据写入与补偿子电路10中的晶体管均为P型晶体管，发光控制子电路20中的晶体管均为N型晶体管为例进行的说明。
其中，像素电路100中的晶体管的第一极a为漏极d、第二极b为源极s；或者，第一极a为源极s、第二极b为漏极d。本公开的实施例对此不作限制。
此外，在一些实施例中，根据晶体管导电方式的不同，将上述像素电路100中的晶体管分为增强型晶体管和耗尽型晶体管。本公开实施例对此不作限制。
第二、请参见图5b，本公开的实施例中，第一电压端V1所输出的第一电压信号为高电平VDD，第二电压端V2所输出的第二电压信号为 低电平，第三电压端V3所输出的第三电压信号为低电平。其中，在一些实施例中，第二电压端V2所输出的第二电压信号和第三电压端V3所输出的第三电压信号为同一低电平VSS，例如，将第二电压端V2和第三电压端V3均接地，使得第二电压信号和第三电压信号均为接地信号。
需要说明的是，上述“高电平”、“低电平”仅表示输入的电压之间的相对大小关系。在另外的一些实施例中，第一电压端V1所输出的第一电压信号为低电平，第二电压端V2所输出的第二电压信号为高电平VDD。
以下以第一电压端V1所输出的第一电压信号为高电平VDD，第二电压端V2和第三电压端V3均接地，二者的电压信号为VSS为例进行说明。
如图6a和图6b所示，像素电路100的一帧画面的时间分为预充电阶段P1、补偿阶段P2和发光阶段P3。
具体的，在一帧的预充电阶段P1，如图6a和图6b所示，第一控制信号端S1输入低电平开启信号，第二控制信号端S2输入高电平开启信号。基于此，如图7所示，像素电路100的第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5以及驱动晶体管Td均开启。
其中，第一控制信号端S1输入低电平开启信号，控制第一晶体管T1、第二晶体管T2和第三晶体管T3开启，数据电压端Vdata的信号通过第一晶体管T1输入至第一点O。
第二控制信号端S2输入高电平开启信号，控制第四晶体管T4和第五晶体管T5开启，第一电压端V1所输出的第一电压信号VDD经第四晶体管T4和第二晶体管T2输入至第三点Q。
驱动晶体管Td在第三点Q的控制下开启(当然，驱动晶体管Td也可以在第三点Q的控制下截止)。
第三晶体管T3处于开启状态，由于第三晶体管T3的第一极a 3电连接发光器件D的阳极d 1，第三晶体管T3的第二极b 3电连接发光器件D的阴极d 2，因此发光器件D的阴极d 2和阳极d 1的电压相等，发光器件D不发光。
需要说明的是，在像素电路100不包括第三晶体管T3的情况下，将第一电压端V1所输出的第一电压信号改变为低电平，使得第三点Q的 电位为低电平，从而在第三点Q的控制下，驱动晶体管Td截止，保证了发光器件D在预充电阶段P1不发光。
这样，在预充电阶段P1结束时，第一点O的电压V O＝Vdata，第三点Q的电压V Q＝VDD。在一些实施例中，VDD为由像素电路100外部的系统提供的电源电压。
在一帧的补偿阶段P2，第一控制信号端S1输入低电平开启信号，第二控制信号端S2输入低电平截止信号。基于此，图5a和图5b所示的像素电路100的等效电路图如图8所示，第一晶体管T1开启、第二晶体管T2开启、第三晶体管T3开启、驱动晶体管Td开启，第四晶体管T4截止、第五晶体管T5截止(处于截止状态的晶体管以打“×”表示)。
其中，第一控制信号端S1输入低电平开启信号，控制第一晶体管T1、第二晶体管T2和第三晶体管T3开启，数据电压端Vdata的信号通过第一晶体管T1输入至第一点O，第二晶体管T2开启将驱动晶体管Td的栅极g d和第一极a d电连接，即将第二点P和第三点Q电连接。
这样，第四点W的电压V W释放，使得第四点W的电压V W＝VSS+Voled。并且，第三点Q的电压V Q释放，电压V Q从VDD下降，直至驱动晶体管Td的栅源电压差Vgs＝V Q-V W＝Vth，驱动晶体管Td截止，第三点Q的电压V Q停止释放。此时，第三点Q的电压V Q＝Vth+V W＝Vth+VSS+Voled，从而实现了对驱动子电路30(即驱动晶体管Td)的阈值电压Vth的补偿。其中，Voled为发光器件D不发光时的电压，Vth为驱动晶体管Td的阈值电压，在一些实施例中，VSS为由像素电路100外部的系统的电源电压。
这样，在补偿阶段P2结束时，第一点O的电压V O＝Vdata，第三点Q的电压V Q＝Vth+VSS+Voled。
在一帧的发光阶段P3，第一控制信号端S1输入高电平截止信号，第二控制信号端S2输入高电平开启信号。基于此，图5a和图5b所示的像素电路100的等效电路图如图10所示，第一晶体管T1截止、第二晶体管T2截止、第三晶体管T3截止，第四晶体管T4开启、第五晶体管T5开启、驱动晶体管Td开启。
其中，第二控制信号端S2输入高电平开启信号，控制第五晶体管T5开启，第二电压端V2所输出的第二电压信号通过第五晶体管T5输出至第一点O，此时，第一点O的电压V O跳变为0，跳变量Δ＝Vdata。
在存储电容C的自举作用下，第三点Q的电压V Q也会发生变化，V Q变为Vth+VSS+Voled+Vdata，第三点Q的电压V Q控制驱动晶体管Td开启。
第二控制信号端S2输入高电平开启信号，同时控制第四晶体管T4开启，第一电压端V1所输出的第一电压信号电压(VDD)通过第四晶体管T4输入至驱动晶体管Td，发光器件D在驱动晶体管Td输出的驱动信号和第三电压端V3所输出的第三电压信号(VSS)的驱动下发光。
可见，在一帧的发光阶段P3，第一点O的电压VO＝0，第三点Q的电压V Q＝Vdata+Vth+VSS+Voled。
此时，驱动晶体管Td开启后，由于驱动晶体管Td为N型晶体管，N型晶体管在Vgs-Vth≤Vds时处于饱和导通状态，因此当驱动晶体管Td的即Vgs-Vth≤Vds时，驱动晶体管Td能够处于饱和开启状态。其中，Vgs为驱动晶体管Td的栅源电压差，Vds为驱动晶体管Td的漏源电压差。此时，流过驱动晶体管Td的驱动电流I oled为：
Figure PCTCN2019079714-appb-000003
其中，C OX为驱动晶体管Td的沟道绝缘层的介电常数，μ为驱动晶体管Td的沟道载流子迁移率，
Figure PCTCN2019079714-appb-000004
为驱动晶体管Td的宽长比。
从上面的公式可以看出，驱动电流I oled只与驱动晶体管Td的自身结构(自身结构决定C OX、μ、
Figure PCTCN2019079714-appb-000005
)及数据电压端Vdata所输出的数据信号有关，而与驱动晶体管Td的阈值电压Vth无关，从而消除了驱动晶体管Td的阈值电压Vth对发光器件D发光亮度的影响，提高了发光器件D的亮度的均一性。
此外，由于驱动晶体管Td的驱动电流I oled中不包含VSS项，因此可以解决VSS信号线上存在压降而造成的显示不均匀的问题。
在一些实施例中，请再次参见图6a和图6b，在补偿阶段P2和发光阶段P3之间还包括稳压阶段P2’。在一帧的稳压阶段P2’，第一控制信号端S1输入高电平截止信号，第二控制信号端S2输入低电平截止信号。基于此，图5a和图5b所示的像素电路100的等效电路图如图9所示，第一晶体管T1截止、第二晶体管T2截止、第三晶体管T3截止、第四 晶体管T4截止和第五晶体管T5截止。
此处，在稳压阶段P2’，数据信号端Vdata的信号，例如为图6a所示的高电平信号，或者，例如为图6b所示的低电平信号。
在稳压阶段P2’，第一控制信号端S1输入高电平截止信号，控制第一晶体管T1截止、第二晶体管T2截止和第三晶体管T3截止。第二控制信号端S2输入低电平截止信号，控制第四晶体管T4和第五晶体管T5截止。此时，第一点O的电压V O保持在Vdata，第三点Q的电压V Q保持在Vth+VSS+Voled。
即，在稳压阶段P2’结束时，第一点O的电压V O＝Vdata，第三点Q的电压V Q＝Vth+VSS+Voled。
这样，通过稳压阶段P2’，为信号在显示面板各个区域传播到位提供一定的缓冲时间，从而显示面板中的各像素电路的V O保持在Vdata，V Q保持在Vth+VSS+Voled，不会存在由于信号延迟所引起的某些像素电路的V O和V Q未达到设定电压(即V O＝Vdata，V Q＝Vth+VSS+Voled)的问题，进而为接下来的发光阶段P3作好充分准备。
在一些实施例中，像素电路100中不包括第三晶体管T3，像素电路100中其他各晶体管(即第一晶体管T1、第二晶体管T2、第四晶体管T4、第五晶体管T5及驱动晶体管Td)在一帧的各阶段的开关情况与上面所述的开关情况相同。
本公开的一些实施例提供一种显示装置，如图12所示，该显示装置200包括多个像素电路100。
其中，示例性的，上述显示装置200具体为OLED显示器、数码相框、手机、平板电脑、导航仪等具有任何显示功能的产品或者部件。
示例性的，本公开的实施例所提供显示装置200包括多个像素Pixel，所述多个像素Pixel呈阵列式排布，所述多个像素Pixel中的每个像素Pixel包括上述任意一个实施例中所述的像素电路100。本公开的实施例提供的显示装置200具有与本公开前述实施例提供的像素电路100相同的有益效果，由于像素电路100在前述实施例中已经进行了详细说明，因此此处不再赘述。
本公开的实施例提供一种像素电路100的驱动方法，一帧画面的时间依次包括预充电阶段P1、补偿阶段P2和发光阶段P3，如图11所示，该驱动方法包括如下步骤：
S10、在一帧的预充电阶段P1，数据写入与补偿子电路10在第一控制信号端S1的控制下开启，将数据电压端Vdata所输出的数据信号传输至驱动子电路30，发光控制子电路20在第二控制信号端S2的控制下开启，将第一电压端V1所输出的第一电压信号传输至驱动子电路30，对驱动子电路30进行预充电。
示例性的，请参见图4、图6a和图6b，在一帧的预充电阶段P1，第一控制信号端S1输入低电平开启信号，控制第一晶体管T1开启、第二晶体管T2开启。第二控制信号端S2输入高电平开启信号，控制第四晶体管T4开启、第五晶体管T5开启，对存储电容C的两端(即第一点O和第三点Q)进行预充电。
在一些实施例中，请参见图3，数据写入与补偿子电路10还与发光子电路40电连接。这样，在一帧的预充电阶段P1，数据写入与补偿子电路10在第一控制信号端S1的控制下开启，对驱动子电路30进行预充电的同时，能够控制发光子电路40的两端的电压相等，从而使发光子电路40在该阶段不发光。
示例性的，请参见图5a和图5b，数据写入与补偿子电路10出包括第一晶体管T1和第二晶体管T2外，还包括第三晶体管T3。第一控制信号端S1输入低电平开启信号，控制第一晶体管T1开启，对第一点O进行充电；同时控制第三晶体管T3开启，使发光器件D两极的电压相等，从而避免发光器件D发光。
S20、在一帧的补偿阶段P2，数据写入与补偿子电路10在第一控制信号端S1的控制下开启，对驱动子电路30进行阈值电压Vth的补偿。
示例性的，请参见图5a和图5b，第一控制信号端S1输入低电平开启信号，控制第一晶体管T1、第二晶体管T2和第三晶体管T3开启，数据电压端Vdata的信号通过第一晶体管T1输入至第一点O，第二晶体管T2开启将驱动晶体管Td的栅极g d和第一极a d电连接，从而将第三点Q和第四点W的电压释放，实现对驱动子电路30的阈值电压Vth的补偿。
S30、在一帧的发光阶段P3，发光控制子电路20在第二控制信号端S2的控制下开启，将第一电压端V1所输出的第一电压信号和第二电压端V2所输出的第二电压信号输入至驱动子电路30，发光子电路40在驱动子电路30所输出的驱动信号和第三电压端V3所输出的第三电压信号的驱动下发光。
示例性的，请参见图5a和图5b，第二控制信号端S2输入高电平开启信号，控制第四晶体管T4和第五晶体管T5开启，第二电压端V2所输出的第二电压信号经第五晶体管T5传输至第一点O，存储电容C的自举作用使得第三电控制驱动晶体管Td开启。第一电压端V1所输出的第二电压信号经第四晶体管T4传输至驱动晶体管Td，并经驱动晶体管Td传输至发光器件D的阳极d 1，第三电压端V3所输出的第三电压信号传输至发光器件D的阴极d 2，驱动发光器件D发光。
在一些实施例中，请参见图6a和图6b，在补偿阶段P2和发光阶段P3之间，还包括稳压阶段P2’，则上述像素电路100的驱动方法还包括如下步骤：
S20’、在一帧的稳压阶段P2’，数据写入与补偿子电路10在第一控制信号端V1的控制下关闭，发光控制子电路20在第二控制信号V2的控制下也关闭，因此驱动子电路30中的信号保持不变。
示例性的，第一控制信号端S1输入高电平截止信号，第二控制信号端S2输入低电平截止信号，控制第一晶体管T1关闭、第二晶体管T2关闭、第三晶体管T3关闭、第四晶体管T4关闭、第五晶体管T5关闭，使存储电容C两端的电压保持不变，即第一点O和第三点Q的电压与补偿阶段P2时的电压相同。这样，能够消除由于信号延迟所引起的某些像素电路的第一点O和第三点Q的电压未达到设定电压(即V O＝Vdata，V Q＝Vth+VSS+Voled)的问题，从而为接下来的发光阶段P3作好充分准备。
本公开的实施例所提供的像素电路的驱动方法的有益效果与上述像素电路100的有益效果相同，此处不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种像素电路，包括：数据写入与补偿子电路、驱动子电路、发光控制子电路、以及发光子电路；
    所述数据写入与补偿子电路，与所述驱动子电路、第一控制信号端、以及数据电压端电连接，被配置为在所述第一控制信号端的控制下，将所述数据电压端所输出的数据信号输入至所述驱动子电路，并对所述驱动子电路进行阈值电压的补偿；
    所述发光控制子电路，与所述驱动子电路、所述数据写入与补偿子电路、第二控制信号端、第一电压端以及第二电压端电连接，被配置为在所述第二控制信号端的控制下，将所述第一电压端所输出的第一电压信号输入至所述驱动子电路和所述数据写入与补偿子电路，将所述第二电压端所输出的第二电压信号输入至所述驱动子电路；
    所述驱动子电路，还与所述发光子电路电连接，被配置为将所述发光控制子电路所输出的信号输入至所述发光子电路；
    所述发光子电路，还与第三电压端电连接，被配置为在所述驱动子电路所输入的信号和所述第三电压端所输出的第三电压信号的驱动下进行发光。
  2. 根据权利要求1所述的像素电路，其中，所述数据写入与补偿子电路包括：
    第一晶体管，所述第一晶体管的栅极电连接所述第一控制信号端，所述第一晶体管的第一极电连接所述数据电压端，所述第一晶体管的第二极电连接所述驱动子电路；
    第二晶体管，所述第二晶体管的栅极电连接所述第一控制信号端，所述第二晶体管的第一极电连接所述发光控制子电路，所述第二晶体管的第二极电连接所述驱动子电路。
  3. 根据权利要求1所述的像素电路，其中，所述数据写入与补偿子电路还与所述发光子电路电连接，被配置为在所述第一控制信号端的控制下，使所述发光子电路的两端的电压相等。
  4. 根据权利要求3所述的像素电路，其中，所述数据写入与补偿子电路包括：
    第一晶体管，所述第一晶体管的栅极电连接所述第一控制信号端，所述第一晶体管的第一极电连接所述数据电压端，所述第一晶体管的第二极 电连接所述驱动子电路；
    第二晶体管，所述第二晶体管的栅极电连接所述第一控制信号端，所述第二晶体管的第一极电连接所述发光控制子电路，所述第二晶体管的第二极电连接所述驱动子电路；
    第三晶体管，所述第三晶体管的栅极电连接所述第一控制信号端，所述第三晶体管的第一极电连接所述驱动子电路，所述第三晶体管的第二极电连接所述发光子电路和所述第三电压端。
  5. 根据权利要求1所述的像素电路，其中，所述驱动子电路包括：
    存储电容，所述存储电容的第一端电连接所述数据写入与补偿子电路和所述发光控制子电路；
    驱动晶体管，所述驱动晶体管的栅极电连接所述存储电容的第二端和所述数据写入与补偿子电路，所述驱动晶体管的第一极电连接所述数据写入与补偿子电路和所述发光控制子电路，所述驱动晶体管的第二极电连接所述发光子电路。
  6. 根据权利要求1所述的像素电路，其中，所述发光控制子电路包括：
    第四晶体管，所述第四晶体管的栅极电连接所述第二控制信号端，所述第四晶体管的第一极电连接所述第一电压端，所述第四晶体管的第二极电连接所述数据写入与补偿子电路和所述驱动子电路；
    第五晶体管，所述第五晶体管的栅极电连接所述第二控制信号端，所述第五晶体管的第一极电连接所述数据写入与补偿子电路和所述驱动子电路，所述第五晶体管的第二极电连接所述第二电压端。
  7. 根据权利要求1所述的像素电路，其中，
    所述数据写入与补偿子电路包括：
    第一晶体管，所述第一晶体管的栅极电连接所述第一控制信号端，所述第一晶体管的第一极电连接所述数据电压端；
    第二晶体管，所述第二晶体管的栅极电连接所述第一控制信号端；
    所述驱动子电路包括：
    存储电容，所述存储电容的第一端电连接所述第一晶体管的第二极，所述存储电容的第二端电连接所述第二晶体管的第一极；
    驱动晶体管，所述驱动晶体管的栅极电连接所述第二晶体管的第一极和所述存储电容的第二端，所述驱动晶体管的第一极电连接所述第二晶体管的第二极；
    所述发光控制子电路包括：
    第四晶体管，所述第四晶体管的栅极电连接所述第二控制信号端，所述第四晶体管的第一极电连接所述第一电压端，所述第四晶体管的第二极电连接所述第二晶体管的第二极和所述驱动晶体管的第一极；
    第五晶体管，所述第五晶体管的栅极电连接所述第二控制信号端，所述第五晶体管的第一极电连接所述第一晶体管的第二极和所述存储电容的第一端，所述第五晶体管的第二极电连接所述第二电压端；
    所述发光子电路包括：
    发光器件，所述发光器件的阳极电连接所述驱动晶体管的第二极，所述发光器件的阴极电连接所述第三电压端。
  8. 根据权利要求7所述的像素电路，其中，所述数据写入与补偿子电路还包括：
    第三晶体管，所述第三晶体管的栅极电连接所述第一控制信号端，所述第三晶体管的第一极电连接所述驱动晶体管的第二极和所述发光器件的阳极，所述第三晶体管的第二极电连接所述第三电压端和所述发光器件的阴极。
  9. 根据权利要求1所述的像素电路，其中，所述数据写入与补偿子电路中的晶体管为P型晶体管，所述发光控制子电路中的晶体管为N型晶体管；或者，
    所述数据写入与补偿子电路中的晶体管为N型晶体管，所述发光控制子电路中的晶体管为P型晶体管。
  10. 一种显示装置，包括多个如权利要求1～9中任一项所述的像素电路。
  11. 一种像素电路的驱动方法，被配置为驱动如权利要求1～9中任一项所述的像素电路，所述驱动方法包括：一帧画面的时间依次包括预充电阶段、补偿阶段和发光阶段；
    在所述预充电阶段，数据写入与补偿子电路在第一控制信号端的控制下开启，将数据电压端所输出的数据信号传输至驱动子电路，发光控制子电路在第二控制信号端的控制下开启，将第一电压端所输出的第一电压信号传输至所述驱动子电路，对所述驱动子电路进行预充电；
    在所述补偿阶段，所述数据写入与补偿子电路在所述第一控制信号端的控制下开启，对所述驱动子电路进行阈值电压的补偿；
    在所述发光阶段，所述发光控制子电路在所述第二控制信号端的控制下开启，将所述第一电压端所输出的第一电压信号和第二电压端所输出的第二电压信号输入至所述驱动子电路，发光子电路在所述驱动子电路所输出的驱动信号和第三电压端所输出的第三电压信号的驱动下发光。
  12. 根据权利要求11所述的驱动方法，其中，在所述补偿阶段和所述发光阶段之间，还包括稳压阶段；
    在所述稳压阶段，所述数据写入与补偿子电路在所述第一控制信号端的控制下关闭，所述发光控制子电路在所述第二控制信号端的控制下关闭，所述驱动子电路中的信号保持不变。
  13. 根据权利要求11所述的驱动方法，其中，所述数据写入与补偿子电路还与所述发光子电路电连接，所述驱动方法包括：
    在所述预充电阶段，所述数据写入与补偿子电路在所述第一控制信号端的控制下开启，对所述驱动子电路进行预充电的同时，控制所述发光子电路的两端的电压相等。
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