WO2018166312A1 - 像素电路及其驱动方法、显示装置 - Google Patents

像素电路及其驱动方法、显示装置 Download PDF

Info

Publication number
WO2018166312A1
WO2018166312A1 PCT/CN2018/075781 CN2018075781W WO2018166312A1 WO 2018166312 A1 WO2018166312 A1 WO 2018166312A1 CN 2018075781 W CN2018075781 W CN 2018075781W WO 2018166312 A1 WO2018166312 A1 WO 2018166312A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
module
voltage
pole
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/075781
Other languages
English (en)
French (fr)
Inventor
王鑫
刘颖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Beijing BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US16/088,600 priority Critical patent/US11024228B2/en
Publication of WO2018166312A1 publication Critical patent/WO2018166312A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • G09G3/325—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • Embodiments of the present disclosure relate to a pixel circuit, a driving method thereof, and a display device.
  • OLED displays are one of the hotspots in the current research field. Compared with liquid crystal display (LCD), OLED display has the advantages of low energy consumption, low production cost, self-illumination, wide viewing angle and corresponding speed. Among them, pixel circuit design is the core technology content of OLED display, which has important Significance.
  • the transistor of the pixel circuit cannot completely guarantee the lossless shutdown, and when the transistor cannot be completely turned off, leakage occurs.
  • an embodiment of the present disclosure provides a pixel circuit, including: an initialization module, a data writing and compensation module, a driving module, a light emitting unit, and a leakage current eliminating module.
  • the initialization module is respectively connected to the driving module, the first signal end, the first voltage end, and the initial voltage end, and is configured to, under the control of the first signal end, the initial voltage end and the first a voltage terminal signal is input to the driving module, and the driving module is initialized;
  • the data writing and compensation module is respectively connected to the driving module, the scanning signal terminal, and the data voltage terminal, and is configured to be in the Under the control of the scanning signal end, the signal of the data voltage end is written to the driving module, and the threshold voltage is compensated for the driving module;
  • the driving module is further connected to the light emitting unit and the second voltage end, Is configured to output the signal of the second voltage end to the light emitting unit in an open state to drive the light emitting unit to emit light;
  • the light emitting unit is further connected to the
  • the leakage current eliminating module includes a first transistor; a gate of the first transistor is connected to the enable signal terminal, and a first electrode of the first transistor is connected to the driving module, and the first transistor is The two poles are connected to the initialization module.
  • the driving module includes a storage capacitor and a driving transistor; a first end of the storage capacitor is connected to the initialization module, the data writing and compensating module, and the light emitting unit, and the second end of the storage capacitor a gate of the driving transistor is connected; a first electrode of the driving transistor is connected to the second voltage terminal, and a second electrode of the driving transistor is connected to the light emitting unit and the data writing and compensation module.
  • the initialization module includes a second transistor, a third transistor, and a fourth transistor; a gate of the second transistor is connected to the first signal terminal, and a first electrode of the second transistor is connected to the first voltage a second pole of the second transistor is connected to the first end of the storage capacitor; a gate of the third transistor is connected to the first signal end, and a first pole of the third transistor is connected to the first a signal terminal, a second pole of the third transistor is connected to a gate of the fourth transistor; a first pole of the fourth transistor is connected to the initial voltage terminal, and a second pole of the fourth transistor is connected The second end of the storage capacitor.
  • the data writing and compensating module includes a fifth transistor and a sixth transistor; a gate of the fifth transistor is connected to the scan signal end, and a first pole of the fifth transistor is connected to the data voltage end, a second pole of the fifth transistor is connected to the first end of the storage capacitor; a gate of the sixth transistor is connected to the scan signal end, and a first pole of the sixth transistor is connected to the first of the drive transistor The second pole of the sixth transistor is connected to the second end of the storage capacitor.
  • the light emitting unit includes a seventh transistor, an eighth transistor, and a light emitting device; a gate of the seventh transistor is connected to the enable signal terminal, and a first electrode of the seventh transistor is connected to the first voltage a second pole of the seventh transistor is connected to the first end of the storage capacitor; a gate of the eighth transistor is connected to the enable signal end, and a first pole of the eighth transistor is connected to the drive a second pole of the transistor, a second pole of the eighth transistor is coupled to an anode of the light emitting device; a cathode of the light emitting device is coupled to the third voltage terminal; and the seventh transistor and the eighth transistor are A type of transistor, the first transistor being a second type of transistor.
  • the seventh transistor and the eighth transistor are P-type transistors, and the first transistor is an N-type transistor.
  • the seventh transistor and the eighth transistor are N-type transistors, and the first transistor is a P-type transistor.
  • the gate of the first transistor is connected to the enable signal terminal
  • the first pole of the first transistor is connected to the second pole of the fourth transistor
  • the second pole of the first transistor is connected to the The gate of the fourth transistor.
  • an embodiment of the present disclosure provides a display device comprising the pixel circuit of the first aspect.
  • an embodiment of the present disclosure provides a driving method of a pixel circuit, including: inputting, at an initialization stage of a frame, a signal of an initial voltage terminal and a first voltage terminal through an initialization module under control of a first signal terminal a driving module, the driving module is initialized; in a data writing phase of one frame, under the control of the scanning signal end, a signal of a data voltage end is written to the driving module by a data writing and compensation module, and The driving module performs compensation of the threshold voltage; under the control of the enabling signal end, the initialization module performs no signal to the initial voltage terminal in the off state through the leakage current eliminating module; in the illumination phase of one frame, Under the control of the enable signal end, the signal of the first voltage end is input to the driving module, the driving module is controlled to be turned on, and the light is controlled under the control of the enabling signal end and the third voltage end The unit emits light.
  • the leakage current cancellation module includes a first transistor
  • the initialization module includes a fourth transistor
  • the drive module includes a storage capacitor. Controlling, by the leakage current cancellation module, the initialization module to output no signal to the initial voltage terminal in the off state, including: in the data writing phase, the enabling signal end Controlling that the first transistor is turned on, and the voltage of the second end of the storage capacitor is input to the gate of the fourth transistor via the first transistor, so that the voltages of the gate and the second pole of the fourth transistor are equal to the second of the storage capacitor
  • the voltage of the terminal, the gate-source voltage of the fourth transistor is zero voltage.
  • the enable signal terminal controls the first transistor to be turned off, the fourth transistor is turned off, and the current of the fourth transistor is a zero current, so that no signal is output to the initial voltage terminal.
  • FIG. 1 is a schematic structural view of a pixel circuit
  • FIG. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of each module of the pixel circuit shown in FIG. 2;
  • FIG. 4 is a timing chart of respective signals used when driving the pixel circuit shown in FIG. 3;
  • FIG. 5-7 are exemplary equivalent circuit diagrams of the pixel circuit shown in FIG. 3 corresponding to different situations;
  • FIG. 8 is a schematic flowchart diagram of a pixel circuit driving method according to an embodiment of the present disclosure.
  • 10-initialization module 20-data writing and compensating module; 30-driving module; 40-lighting unit; 50-leakage current eliminating module.
  • the display area of the display panel includes a plurality of pixel circuits. As shown in FIG. 1, in the light-emitting phase of the pixel circuit, since the second transistor M2 cannot be completely turned off, a part of the current flowing from the driving transistor M3 to the light-emitting device leaks into the M3-M5-M2 path, resulting in flowing through the light-emitting device. The current is unstable, thereby affecting the luminance of the light-emitting device, so that the light-emitting device is prone to flicker when emitting light.
  • Embodiments of the present disclosure provide a pixel circuit, a driving method thereof, and a display device, which can reduce leakage current in a pixel circuit.
  • Embodiments of the present disclosure provide a pixel circuit, a driving method thereof, and a display device.
  • a leakage current eliminating module connected to an initialization module in a pixel circuit
  • initialization is performed.
  • the module outputs no signal to the initial voltage terminal (ie, the current flowing to the light emitting device does not leak into other paths during the light emitting phase), thereby ensuring the stability of the circuit flowing into the light emitting unit, and preventing the light emitting unit from appearing during the light emitting process.
  • a flicker problem and can reduce the power consumption of the pixel circuit to some extent.
  • the embodiment of the present disclosure provides a pixel circuit, as shown in FIG. 2, including an initialization module 10, a data writing and compensation module 20, a driving module 30, a light emitting unit 40, and a leakage current eliminating module 50.
  • the initialization module 10 is respectively connected to the driving module 30, the first signal terminal S1, the first voltage terminal V1, and the initial voltage terminal Vinit, and is configured to, under the control of the first signal terminal S1, the initial voltage terminal Vinit and The signal of the first voltage terminal V1 is input to the drive module 30, and the drive module 30 is initialized.
  • the data writing and compensation module 20 is connected to the driving module 30, the scanning signal terminal S2, and the data voltage terminal Vdata, respectively, and is configured to write the signal of the data voltage terminal Vdata to the driving module 30 under the control of the scanning signal terminal S2. And the drive module 30 is compensated for the threshold voltage.
  • the driving module 30 is further connected to the light emitting unit 40 and the second voltage terminal V2, and is configured to output the signal of the second voltage terminal V2 to the light emitting unit 40 in the on state to drive the light emitting unit 40 to emit light.
  • the light emitting unit 40 is further connected to the first voltage terminal V1, the enable signal terminal EM, and the third voltage terminal V3, and is configured to input the signal of the first voltage terminal V1 to the driving module 30 under the control of the enable signal terminal EM.
  • the control driving module 30 is turned on, and emits light under the control of the enable signal terminal EM and the third voltage terminal V3.
  • the leakage current eliminating module 50 is respectively connected to the initialization module 10, the driving module 30, and the enable signal terminal EM, and is configured to enable the initialization module 10 to have no signal to the initial voltage terminal in the off state under the control of the enable signal terminal EM. Vinit output.
  • the embodiment of the present disclosure provides a pixel circuit in which a leakage current eliminating module 50 connected to the initialization module 10 is added, so that in the shutdown phase of the initialization module 10, under the control of the leakage current eliminating module 50, the initialization module 10 has no signal.
  • the leakage current eliminating module 50 includes a first transistor T1.
  • the gate of the first transistor T1 is connected to the enable signal terminal EM, the first pole is connected to the drive module 30, and the second pole is connected to the initialization module 10.
  • the leakage current eliminating module 50 may further include a plurality of first transistors T1 connected in parallel.
  • the above is only an example of the leakage current elimination module 50.
  • Other structures having the same function as the leakage current elimination module 50 will not be further described herein, but all should fall within the protection scope of the present disclosure.
  • the driving module 30 includes a storage capacitor Cst and a driving transistor Td.
  • the first end of the storage capacitor Cst is connected to the initialization module 10, the data writing and compensating module 20, and the light emitting unit 40, and the second end is connected to the gate of the driving transistor Td and the first pole of the first transistor T1.
  • the first electrode of the driving transistor Td is connected to the second voltage terminal V2, and the second electrode is connected to the light emitting unit 40 and the data writing and compensation module 20.
  • the driving module 30 may further include a plurality of driving transistors Td connected in parallel.
  • Td driving transistors
  • the foregoing is merely an illustration of the driving module 30.
  • Other structures having the same functions as the driving module 30 are not described herein again, but all should fall within the protection scope of the present disclosure.
  • the initialization module 10 includes a second transistor T2, a third transistor T3, and a fourth transistor T4.
  • the gate of the second transistor T2 is connected to the first signal terminal S1, the first electrode is connected to the first voltage terminal V1, and the second electrode is connected to the first terminal of the storage capacitor Cst.
  • the gate of the third transistor T3 is connected to the first signal terminal S1, the first electrode is connected to the first signal terminal S1, and the second electrode is connected to the gate of the fourth transistor T4.
  • the first pole of the fourth transistor T4 is connected to the initial voltage terminal Vinit, and the second pole is connected to the second end of the storage capacitor Cst.
  • the initialization module 10 may further include a plurality of switching transistors connected in parallel with the second transistor T2, and/or a plurality of switching transistors connected in parallel with the third transistor T3, and/or in parallel with the fourth transistor T4. Multiple switching transistors.
  • a plurality of switching transistors connected in parallel with the second transistor T2
  • a plurality of switching transistors connected in parallel with the third transistor T3, and/or in parallel with the fourth transistor T4. Multiple switching transistors.
  • the gate of the first transistor T1 is connected to the enable signal terminal EM
  • the first pole is connected to the second pole of the fourth transistor T4
  • the second pole is connected to the gate of the fourth transistor T4.
  • the data write and compensation module 20 includes a fifth transistor T5 and a sixth transistor T6.
  • the gate of the fifth transistor T5 is connected to the scan signal terminal S2, the first pole is connected to the data voltage terminal Vdata, and the second pole is connected to the first terminal of the storage capacitor Cst.
  • the gate of the sixth transistor T6 is connected to the scanning signal terminal S2, the first electrode is connected to the second electrode of the driving transistor Td, and the second electrode is connected to the second terminal of the storage capacitor Cst.
  • the data writing and compensating module 20 may further include a plurality of switching transistors connected in parallel with the fifth transistor T5 and/or a plurality of switching transistors connected in parallel with the sixth transistor T6.
  • the foregoing is only an example of the data writing and compensating module 20, and other structures having the same functions as those of the data writing and compensating module 20 are not described herein again, but all should fall within the protection scope of the present disclosure.
  • the light emitting unit 40 includes a seventh transistor T7, an eighth transistor T8, and a light emitting device L.
  • the gate of the seventh transistor T7 is connected to the enable signal terminal EM, the first pole is connected to the first voltage terminal V1, and the second pole is connected to the first end of the storage capacitor Cst.
  • the gate of the eighth transistor T8 is connected to the enable signal terminal EM, the first electrode is connected to the second electrode of the driving transistor Td, and the second electrode is connected to the anode of the light emitting device L.
  • the cathode of the light emitting device L is connected to the third voltage terminal V3.
  • the seventh transistor T7 and the eighth transistor T8 are transistors of a first type, and the first transistor T1 is a transistor of a second type.
  • the seventh transistor T7 and the eighth transistor T8 are P-type transistors, and the first transistor T1 is an N-type transistor. That is, the seventh transistor T7 and the eighth transistor T8 in the pixel circuit are turned on under the control of the low voltage, and the first transistor T1 is turned on under the control of the high voltage.
  • the seventh transistor T7 and the eighth transistor T8 are N-type transistors, and the first transistor T1 is a P-type transistor. That is, the seventh transistor T7 and the eighth transistor T8 in the pixel circuit are turned on under the control of the high voltage, and the first transistor T1 is turned on under the control of the low voltage.
  • the seventh transistor T7 and the eighth transistor T8 in the light emitting unit 40 when the seventh transistor T7 and the eighth transistor T8 in the light emitting unit 40 are turned on, the first transistor T1 in the leakage current eliminating module 50 is turned off; the seventh in the light emitting unit 40 When the transistor T7 and the eighth transistor T8 are turned off, the first transistor T1 in the leakage current eliminating module 50 is turned on.
  • the light emitting unit 40 may further include a plurality of switching transistors connected in parallel with the seventh transistor T7, and/or a plurality of switching transistors connected in parallel with the eighth transistor T8.
  • the foregoing is merely an illustration of the light-emitting unit 40.
  • Other structures having the same functions as those of the light-emitting unit 40 are not described herein again, but all should fall within the protection scope of the present disclosure.
  • the types of transistors in the respective modules and the units are not limited, that is, the driving transistor Td, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor.
  • T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be an N-type transistor or a P-type transistor, but the types of the seventh transistor T7 and the eighth transistor T8 and the first transistor T1 The opposite type.
  • the following embodiments of the present disclosure are based on the driving transistor Td, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8.
  • the transistor and the first transistor T1 are an N-type transistor as an example.
  • the first pole of the transistor may be a drain, and the second pole may be a source; or the first pole may be a source, and the second pole may be a drain.
  • the embodiments of the present disclosure do not limit this.
  • the transistors in the above pixel circuit can be classified into an enhancement transistor and a depletion transistor depending on the manner in which the transistors are electrically conductive.
  • the embodiments of the present disclosure do not limit this.
  • the embodiments of the present disclosure are all described in which the second voltage terminal V2 is input to the high level, the third voltage terminal V3 is input to the low level, or the third voltage terminal V3 is grounded as an example, and the height is here. Low refers only to the relative magnitude relationship between the input voltages.
  • each frame display process of the pixel circuit can be divided into an initialization phase P1, a data writing and compensation phase P2, and an illumination phase P3. specific:
  • the first signal terminal S1 inputs a low level signal
  • the enable signal terminal EM and the scan signal terminal S2 input a high level signal.
  • the equivalent circuit diagram of the pixel circuit shown in FIG. 3 is as shown in FIG. .
  • the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are both turned on, and the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the driving transistor Td are both turned off (at The transistor in the off state is indicated by "x".
  • the second transistor T2 is turned on, the voltage of the first voltage terminal V1 is written to the first end of the storage capacitor Cst; the third transistor T3 and the fourth transistor T4 are turned on, and the voltage of the initial voltage terminal Vinit is written to the storage capacitor.
  • the second end of Cst initializes the voltage across the storage capacitor Cst.
  • the voltage of the initial voltage terminal Vinit should be higher than the turn-on voltage of the driving transistor Td, and after the voltage of the initial voltage terminal Vinit is written to the second terminal of the storage capacitor Cst, the driving transistor Td should be kept turned off.
  • the scanning signal terminal S2 inputs a low-level signal
  • the first signal terminal S1 and the enabling signal terminal EM input a high-level signal.
  • the equivalent circuit diagram of the pixel circuit shown in FIG. 3 is as shown in FIG. 6. Shown.
  • the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the driving transistor Td are all turned on, and the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are all turned off.
  • the first transistor T1 is turned on, the voltage of the second end of the storage capacitor Cst (the gate of the driving transistor Td) is written to the second pole of the fourth transistor T4, and is written to the first transistor T1.
  • the gate of the four transistor T4 causes the gate and the second pole of the fourth transistor T4 to be shorted, that is, the gate-source voltage Vgs of the fourth transistor T4 is zero.
  • there is no loss of threshold voltage when the P-type transistor transmits a low potential and there is no loss of the threshold voltage when the N-type transistor transmits a high potential voltage.
  • the third transistor T3 under the action of the third transistor T3 (the third transistor T3 is in the off state), the signal on the first signal terminal S1 can be prevented from being written to the gate Td of the driving transistor via the first transistor T1, and the driving transistor Td is
  • the gate potential has an effect that affects the display of the display phase.
  • the enable signal terminal EM inputs a low-level signal
  • the first signal terminal S1 and the scan signal terminal S2 input a high-level signal.
  • the equivalent circuit diagram of the pixel circuit shown in FIG. 3 is as shown in FIG. 7 . Show.
  • the seventh transistor T7, the eighth transistor T8, and the driving transistor Td are both turned on, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all turned off.
  • the voltage of the second voltage terminal V2 is written to the anode of the light emitting device L via the driving transistor Td and the eighth transistor T8.
  • the voltage of the third voltage terminal V3 is written to the cathode of the light-emitting device L, at which time the light-emitting device L is turned on for screen display.
  • the driving transistor Td In the light-emitting phase P3, after the driving transistor Td is turned on, when the gate-source voltage Vgs of the driving transistor Td minus the threshold voltage Vth of the driving transistor Td is less than or equal to the drain-source voltage Vds of the driving transistor Td, that is, Vgs- When Vth ⁇ Vds, the driving transistor Td can be in a saturated on state, and at this time, the driving current I flowing through the driving transistor Td is:
  • K W / L ⁇ C ⁇ u
  • W / L is the width to length ratio of the driving transistor Td
  • C is the channel insulating layer capacitance
  • u is the channel carrier mobility
  • the above parameters are only related to the structure of the driving transistor Td. Therefore, the current flowing through the driving transistor Td is only related to the data voltage outputted by the data voltage terminal Vdata for realizing display and the voltage outputted by the first voltage terminal V1, and the driving transistor Td.
  • the threshold voltage Vth is independent, thereby eliminating the influence of the threshold voltage Vth of the driving transistor Td on the luminance of the light-emitting device L, and improving the uniformity of the luminance of the light-emitting device L.
  • the first transistor T1 is turned on, so that the gate-source voltage of the fourth transistor T4 is zero voltage; and in the light-emitting phase P3, The first transistor T1 is turned off, the fourth transistor T4 is turned off, and the current of the fourth transistor T4 is zero current, so that no signal is output to the initial voltage terminal Vinit (ie, no leakage current passes through the fourth transistor). T4 is output to the initial voltage terminal Vinit).
  • the range of values of the pixel circuit operating voltage determines the voltage range of the gate of the driving transistor Td.
  • the gate voltage range of the driving transistor Td may be a negative value, which may be a positive value.
  • This design can only optimize the leakage of a part of the gray scale for some pixel circuits. For example, when the gate voltage of the driving transistor Td is positive, the gate attracts a negative charge, and the absolute value of the attracted negative charge is larger (less than the reverse breakdown voltage), and the current between the source electrode and the drain electrode is smaller. Therefore, when the gate voltage of the driving transistor Td is a positive value, the current flowing through the driving transistor Td itself is small, the leakage current is smaller, and the optimization effect is not significant.
  • the gate voltage of the driving transistor Td When the gate voltage of the driving transistor Td is a negative value, the gate attracts a positive charge, and the larger the absolute value of the attracted positive charge, the larger the current between the source electrode and the drain electrode, and therefore, the gate voltage of the driving transistor Td When the value is negative, the current flowing through the driving transistor Td is large, and the leakage current has a greater influence on the light emitting device. For this reason, the pixel circuit provided by the embodiment of the present disclosure can eliminate the leakage current.
  • Embodiments of the present disclosure provide a display device including any of the pixel circuits described above.
  • the display device may include an array of pixel cells, each of which includes any one of the pixel circuits as described above.
  • the display device provided by the embodiment of the present disclosure has the same or similar advantages as the pixel circuit provided by the foregoing embodiments of the present disclosure. Since the pixel circuit has been described in detail in the foregoing embodiments, details are not described herein again.
  • the embodiment of the present disclosure further provides a driving method of a pixel circuit. As shown in FIG. 8, the driving method includes:
  • the initial voltage terminal Vinit and the signal of the first voltage terminal V1 are input to the driving module 30 through the initialization module 10, and the driving module 30 is initialized.
  • the initialization module 10 Under the control of the enable signal terminal EM, the initialization module 10 is caused to output no signal to the initial voltage terminal Vinit in the off state by the leakage current eliminating module 50.
  • the embodiment of the present disclosure provides a driving method of a pixel circuit, in which a leakage current eliminating module 50 connected to the initialization module 10 is added in the pixel circuit, so that the initialization module 10 is initialized under the control of the leakage current eliminating module 50 during the shutdown phase of the initialization module 10.
  • the leakage current cancellation module 50 causes the initialization module 10 to output no signal to the initial voltage terminal Vinit in the off state, which specifically includes:
  • the enable signal terminal EM controls the first transistor T1 to be turned on, and the voltage of the second terminal of the storage capacitor Cst is input to the gate of the fourth transistor T4 via the first transistor T1, so that the fourth transistor T4
  • the voltages of the gate and the second pole are both equal to the voltage of the second terminal of the storage capacitor Cst, and the gate-source voltage of the fourth transistor is zero voltage.
  • the enable signal terminal EM controls the first transistor T1 to be turned on, so that the gate-source voltage Vgs of the fourth transistor T4 is 0.
  • the enable signal terminal controls the first transistor to be turned off, the fourth transistor is turned off, and the current of the fourth transistor is a zero current, so that no signal is output to the initial voltage terminal.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of El Displays (AREA)

Abstract

一种像素电路及其驱动方法、显示装置。像素电路包括：初始化模块（10），被配置为对驱动模块（30）进行初始化；数据写入与补偿模块（20），被配置为对驱动模块（30）进行阈值电压的补偿；驱动模块（30），被配置为将第二电压端（V2）的信号输出至发光单元（40），以驱动发光单元（40）进行发光；发光单元（40），被配置为在使能信号端（EM）的控制下，将第一电压端（V1）的信号输入至驱动模块（30），控制驱动模块（30）开启，并在使能信号端（EM）和第三电压端（V3）的控制下进行发光；漏电流消除模块（50），被配置为在使能信号端（EM）的控制下，使初始化模块（10）在关闭状态下无信号向初始电压端（Vinit）输出。

Description

像素电路及其驱动方法、显示装置
本公开要求于2017年3月13日递交的中国专利申请第201710147593.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本公开的一部分。
技术领域
本公开实施例涉及一种像素电路及其驱动方法、显示装置。
背景技术
有机电致发光二极管(Organic Light Emitting Diode，OLED)显示器是目前研究领域的热点之一。与液晶显示器(Liquid Crystal Display，LCD)相比，OLED显示器具有低能耗、生产成本低、自发光、宽视角及相应速度快等优点，其中，像素电路设计是OLED显示器核心技术内容，具有重要的研究意义。
在每一帧的画面显示阶段，在实际工作过程中，像素电路的晶体管并不能完全保证无损耗的关闭，而在晶体管无法完全关闭时，会出现漏电的情况。
发明内容
第一方面，本公开的实施例提供一种像素电路，包括：初始化模块、数据写入与补偿模块、驱动模块、发光单元、以及漏电流消除模块。所述初始化模块，分别连接所述驱动模块、第一信号端、第一电压端、以及初始电压端，被配置为在所述第一信号端的控制下，将所述初始电压端和所述第一电压端的信号输入至所述驱动模块，对所述驱动模块进行初始化；所述数据写入与补偿模块，分别连接所述驱动模块、扫描信号端、以及数据电压端，被配置为在所述扫描信号端的控制下，将数据电压端的信号写入至所述驱动模块，并对所述驱动模块进行阈值电压的补偿；所述驱动模块，还连接所述发光单元以及所述第二电压端，被配置为在开启状态下将所述第二电压端的信号输出至所述发光单元，以驱动所述发光单元进行发光；所述发光单元，还连接所述第一电压端、使能信号端、第三电压端，被配置为在所述使能信号端的控制下，将所述第一电压端的信号输入至所述驱动模块，控制所述驱动模块开启，并在所述使 能信号端和所述第三电压端的控制下进行发光；所述漏电流消除模块，分别连接所述初始化模块、所述驱动模块、以及所述使能信号端，被配置为在所述使能信号端的控制下，使所述初始化模块在关闭状态下无信号向所述初始电压端输出。
例如，所漏电流消除模块包括第一晶体管；所述第一晶体管的栅极连接所述使能信号端，所述第一晶体管的第一极连接所述驱动模块，所述第一晶体管的第二极连接所述初始化模块。
例如，所述驱动模块包括存储电容和驱动晶体管；所述存储电容的第一端连接所述初始化模块、所述数据写入与补偿模块、以及所述发光单元，所述存储电容的第二端连接所述驱动晶体管的栅极；所述驱动晶体管的第一极连接所述第二电压端，所述驱动晶体管的第二极连接所述发光单元、以及所述数据写入与补偿模块。
例如，所述初始化模块包括第二晶体管、第三晶体管和第四晶体管；所述第二晶体管的栅极连接所述第一信号端，所述第二晶体管的第一极连接所述第一电压端，所述第二晶体管的第二极连接所述存储电容的第一端；所述第三晶体管的栅极连接所述第一信号端，所述第三晶体管的第一极连接所述第一信号端，所述第三晶体管的第二极连接所述第四晶体管的栅极；所述第四晶体管的第一极连接所述初始电压端，所述第四晶体管的第二极连接所述存储电容的第二端。
例如，所述数据写入与补偿模块包括第五晶体管和第六晶体管；所述第五晶体管的栅极连接所述扫描信号端，所述第五晶体管的第一极连接所述数据电压端，所述第五晶体管的第二极连接所述存储电容的第一端；所述第六晶体管的栅极连接所述扫描信号端，所述第六晶体管的第一极连接所述驱动晶体管的第二极，所述第六晶体管的第二极连接所述存储电容的第二端。
例如，所述发光单元包括第七晶体管、第八晶体管、以及发光器件；所述第七晶体管的栅极连接所述使能信号端，所述第七晶体管的第一极连接所述第一电压端，所述第七晶体管的第二极连接所述存储电容的第一端；所述第八晶体管的栅极连接所述使能信号端，所述第八晶体管的第一极连接所述驱动晶体管的第二极，所述第八晶体管的第二极连接所述发光器件的阳极；所述发光器件的阴极连接所述第三电压端；所述第七晶体管和所述第八晶体管为第 一类型的晶体管，所述第一晶体管为第二类型的晶体管。
例如，所述第七晶体管和所述第八晶体管为P型晶体管，所述第一晶体管为N型晶体管。或者，所述第七晶体管和所述第八晶体管为N型晶体管，所述第一晶体管为P型晶体管。
例如，所述第一晶体管的栅极连接所述使能信号端，所述第一晶体管的第一极连接所述第四晶体管的第二极，所述第一晶体管的第二极连接所述第四晶体管的栅极。
第二方面，本公开的实施例提供一种显示装置，包括第一方面所述的像素电路。
第三方面，本公开的实施例提供一种像素电路的驱动方法，包括：在一帧的初始化阶段，在第一信号端的控制下，通过初始化模块将初始电压端和第一电压端的信号输入至驱动模块，对所述驱动模块进行初始化；在一帧的数据写入阶段，在扫描信号端的控制下，通过数据写入与补偿模块将数据电压端的信号写入至所述驱动模块，并对所述驱动模块进行阈值电压的补偿；在使能信号端的控制下，通过漏电流消除模块使所述初始化模块在关闭状态下无信号向所述初始电压端输出；在一帧的发光阶段，在所述使能信号端的控制下，将所述第一电压端的信号输入至所述驱动模块，控制所述驱动模块开启，并在所述使能信号端和所述第三电压端的控制下，控制发光单元进行发光。
例如，所述漏电流消除模块包括第一晶体管，所述初始化模块包括第四晶体管，所述驱动模块包括存储电容。在使能信号端的控制下，通过所述漏电流消除模块使所述初始化模块在关闭状态下无信号向所述初始电压端输出，包括：在所述数据写入阶段，所述使能信号端控制第一晶体管开启，存储电容第二端的电压经所述第一晶体管输入至第四晶体管的栅极，使所述第四晶体管的栅极和第二极的电压均等于所述存储电容第二端的电压，所述第四晶体管的栅-源电压为零电压。在所述发光阶段，所述使能信号端控制所述第一晶体管截止，所述第四晶体管截止，所述第四晶体管的电流为零电流，使得无信号向所述初始电压端输出。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实 施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种像素电路的结构示意图；
图2为本公开实施例提供的一种像素电路的结构示意图；
图3为图2所示像素电路的各个模块的一种示例性的结构示意图；
图4为用于驱动图3所示的像素电路时采用的各个信号的时序图；
图5-7为图3所示的像素电路对应不同情况时的示例性的等效电路图；
图8为本公开实施例提供的一种像素电路驱动方法流程示意图。
附图标记
10-初始化模块；20-数据写入与补偿模块；30-驱动模块；40-发光单元；50-漏电流消除模块。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
显示面板的显示区包括多个像素电路。如图1所示，在像素电路的发光阶段，由于第二晶体管M2无法完全关闭，导致由驱动晶体管M3流向发光器件的电流会有一部分漏到M3-M5-M2通路中，导致流经发光器件的电流不稳定，从而影响发光器件的发光亮度，使得发光器件在发光时容易出现闪烁现象。
本公开的实施例提供一种像素电路及其驱动方法、显示装置，可降低像素电路中的漏电流。
本公开实施例提供一种像素电路及其驱动方法、显示装置，通过在像素电路中增加与初始化模块连接的漏电流消除模块，在初始化模块关闭阶段，在漏电流消除模块的控制下，使初始化模块无信号向初始电压端输出(即，在发光阶段，流向发光器件的电流不会漏到其他通路中)，从而可以保证流向发光单元内的电路的稳定性，避免发光单元在发光过程中出现闪烁(flicker)问题， 并且可以一定程度上降低像素电路的功耗。
本公开实施例提供一种像素电路，如图2所示，包括初始化模块10、数据写入与补偿模块20、驱动模块30、发光单元40、以及漏电流消除模块50。
具体的，初始化模块10，分别连接驱动模块30、第一信号端S1、第一电压端V1、以及初始电压端Vinit，被配置为在第一信号端S1的控制下，将初始电压端Vinit和第一电压端V1的信号输入至驱动模块30，并对驱动模块30进行初始化。
数据写入与补偿模块20，分别连接驱动模块30、扫描信号端S2、以及数据电压端Vdata，被配置为在扫描信号端S2的控制下，将数据电压端Vdata的信号写入至驱动模块30，并对驱动模块30进行阈值电压的补偿。
驱动模块30，还连接发光单元40以及第二电压端V2，被配置为在开启状态下将第二电压端V2的信号输出至发光单元40，以驱动发光单元40进行发光。
发光单元40，还连接第一电压端V1、使能信号端EM、第三电压端V3，被配置为在使能信号端EM的控制下，将第一电压端V1的信号输入至驱动模块30，控制驱动模块30开启，并在使能信号端EM和第三电压端V3的控制下进行发光。
漏电流消除模块50，分别连接初始化模块10、驱动模块30、以及使能信号端EM，被配置为在使能信号端EM的控制下，使初始化模块10在关闭状态下无信号向初始电压端Vinit输出。
由于单个像素中的发光器件(例如有机发光二极管)在发光阶段的电流大小仅为nA级，因此即使很小的漏电也会对发光阶段产生严重的影响。本公开实施例提供一种像素电路，在像素电路中增加与初始化模块10连接的漏电流消除模块50，使得在初始化模块10关闭阶段，在漏电流消除模块50的控制下，初始化模块10无信号向初始电压端Vinit输出(即在发光阶段，流向发光器件的电流不会漏到其他通路中)，从而可以保证流向发光单元40内的电路的稳定性，避免发光单元40在发光过程中出现闪烁(flicker)问题，并且可以一定程度上降低像素电路的功耗。
进一步具体的，如图3所示，漏电流消除模块50包括第一晶体管T1。
第一晶体管T1的栅极连接使能信号端EM，第一极连接驱动模块30，第 二极连接初始化模块10。
需要说明的是，所述漏电流消除模块50还可以包括并联的多个第一晶体管T1。上述仅仅是对漏电流消除模块50的举例说明，其它与该漏电流消除模块50功能相同的结构在此不再一一赘述，但都应当属于本公开的保护范围。
如图3所示，驱动模块30包括存储电容Cst和驱动晶体管Td。
存储电容Cst的第一端连接初始化模块10、数据写入与补偿模块20、以及发光单元40，第二端连接驱动晶体管Td的栅极以及第一晶体管T1的第一极。
驱动晶体管Td的第一极连接第二电压端V2，第二极连接发光单元40、以及数据写入与补偿模块20。
需要说明的是，所述驱动模块30还可以包括并联的多个驱动晶体管Td。上述仅仅是对驱动模块30的举例说明，其它与该驱动模块30功能相同的结构在此不再一一赘述，但都应当属于本公开的保护范围。
如图3所示，初始化模块10包括第二晶体管T2、第三晶体管T3和第四晶体管T4。
第二晶体管T2的栅极连接第一信号端S1，第一极连接第一电压端V1，第二极连接存储电容Cst的第一端。
第三晶体管T3的栅极连接第一信号端S1，第一极连接第一信号端S1，第二极连接第四晶体管T4的栅极。
第四晶体管T4的第一极连接初始电压端Vinit，第二极连接存储电容Cst的第二端。
需要说明的是，所述初始化模块10还可以包括与第二晶体管T2并联的多个开关晶体管、和/或与第三晶体管T3并联的多个开关晶体管、和/或与第四晶体管T4并联的多个开关晶体管。上述仅仅是对初始化模块10的举例说明，其它与初始化模块10功能相同的结构在此不再一一赘述，但都应当属于本公开的保护范围。
进一步具体的，如图3所示，第一晶体管T1的栅极连接使能信号端EM，第一极连接第四晶体管T4的第二极，第二极连接第四晶体管T4的栅极。
如图3所示，数据写入与补偿模块20包括第五晶体管T5和第六晶体管T6。
第五晶体管T5的栅极连接扫描信号端S2，第一极连接数据电压端Vdata，第二极连接存储电容Cst的第一端。
第六晶体管T6的栅极连接扫描信号端S2，第一极连接驱动晶体管Td的第二极，第二极连接存储电容Cst的第二端。
需要说明的是，所述数据写入与补偿模块20还可以包括与第五晶体管T5并联的多个开关晶体管、和/或与第六晶体管T6并联的多个开关晶体管。上述仅仅是对数据写入与补偿模块20的举例说明，其它与数据写入与补偿模块20功能相同的结构在此不再一一赘述，但都应当属于本公开的保护范围。
如图3所示，发光单元40包括第七晶体管T7、第八晶体管T8、以及发光器件L。
第七晶体管T7的栅极连接使能信号端EM，第一极连接第一电压端V1，第二极连接存储电容Cst的第一端。
第八晶体管T8的栅极连接使能信号端EM，第一极连接驱动晶体管Td的第二极，第二极连接发光器件L的阳极。
发光器件L的阴极连接第三电压端V3。
所述第七晶体管T7和所述第八晶体管T8为第一类型的晶体管，所述第一晶体管T1为第二类型的晶体管。
例如，第七晶体管T7和第八晶体管T8为P型晶体管，第一晶体管T1为N型晶体管。即，像素电路中的第七晶体管T7和第八晶体管T8在低电压的控制下导通，第一晶体管T1在高电压的控制下导通。
或者，第七晶体管T7和第八晶体管T8为N型晶体管，第一晶体管T1为P型晶体管。即，像素电路中的第七晶体管T7和第八晶体管T8在高电压的控制下导通，第一晶体管T1在低电压的控制下导通。
综上，本公开实施例提供的像素电路，发光单元40中的第七晶体管T7和第八晶体管T8导通时，漏电流消除模块50内的第一晶体管T1截止；发光单元40中的第七晶体管T7和第八晶体管T8截止时，漏电流消除模块50内的第一晶体管T1导通。
需要说明的是，所述发光单元40还可以包括与第七晶体管T7并联的多个开关晶体管、和/或与第八晶体管T8并联的多个开关晶体管。上述仅仅是对发光单元40的举例说明，其它与发光单元40功能相同的结构在此不再一一 赘述，但都应当属于本公开的保护范围。
基于上述对各模块具体电路的描述，以下结合图3和图4对上述像素驱动电路的具体驱动过程进行详细的说明。
需要说明的是，第一、本公开实施例对各个模块以及单元中的晶体管的类型不做限定，即上述驱动晶体管Td、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、以及第八晶体管T8可以是为N型晶体管或者P型晶体管，但第七晶体管T7和第八晶体管T8的类型与第一晶体管T1的类型相反。本公开以下实施例均是以驱动晶体管Td、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、以及第八晶体管T8为P型晶体管，第一晶体管T1为N型晶体管为例进行的说明。
例如，上述晶体管的第一极可以是漏极、第二极可以是源极；或者，第一极可以是源极、第二极可以是漏极。本公开实施例对此不作限制。
此外，根据晶体管导电方式的不同，可以将上述像素电路中的晶体管分为增强型晶体管和耗尽型晶体管。本公开实施例对此不作限制。
第二、本公开实施例均是以第二电压端V2输入高电平，第三电压端V3输入低电平，或将第三电压端V3接地处理为例进行的说明，并且，这里的高、低仅表示输入的电压之间的相对大小关系。
如图4所示，该像素电路的每一帧显示过程可以分为初始化阶段P1、数据写入与补偿阶段P2和发光阶段P3。具体的：
初始化阶段P1，第一信号端S1输入低电平信号，使能信号端EM以及扫描信号端S2输入高电平信号，基于此，图3所示的像素电路的等效电路图如图5所示。第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4均导通，第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8和驱动晶体管Td均截止(处于截止状态的晶体管以打“×”表示)。
例如，第二晶体管T2导通，第一电压端V1的电压写入到存储电容Cst的第一端；第三晶体管T3和第四晶体管T4导通，初始电压端Vinit的电压写入到存储电容Cst的第二端，对存储电容Cst两端的电压进行初始化。此处，初始电压端Vinit的电压应高于驱动晶体管Td的开启电压，当初始电压端Vinit的电压写入到存储电容Cst的第二端后，驱动晶体管Td应保持截止状 态。
数据写入阶段P2，扫描信号端S2输入低电平信号，第一信号端S1以及使能信号端EM输入高电平信号，基于此，图3所示的像素电路的等效电路图如图6所示。第一晶体管T1、第五晶体管T5、第六晶体管T6和驱动晶体管Td均打开，第二晶体管T2、第三晶体管T3、第四晶体管T4、第七晶体管T7和第八晶体管T8均截止。
例如，第五晶体管T5导通，数据电压端Vdata的电压写入到存储电容Cst的第一端，存储电容Cst的第一端的电压由V1变为Vdata，变化量为ΔV1＝V1-Vdata，基于此，存储电容Cst的第二端的电压变为Vinit-ΔV1，此时，存储电容Cst的第二端的电压控制驱动晶体管Td开启。在驱动晶体管Td和第六晶体管T6均导通时，第二电压端V2的电压经驱动晶体管Td和第六晶体管T6写入到存储电容Cst的第二端，由于驱动晶体管Td中存在阈值电压Vth，因此此时存储电容Cst的第二端的电压变为V2+Vth，存储电容Cst的第二端的电压上升，高于控制驱动晶体管Td的开启电压，控制驱动晶体管Td截止。
在此基础上，第一晶体管T1导通，存储电容Cst的第二端(驱动晶体管Td栅极)的电压写入到第四晶体管T4的第二极，并经第一晶体管T1写入到第四晶体管T4的栅极，使得第四晶体管T4的栅极和第二极发生短接，即第四晶体管T4的栅-源电压Vgs＝0。根据晶体管的特性，P型晶体管传输低电位时没有阈值电压的损失，N型晶体管传输高电位电压时没有阈值电压的损失。
此时，在第三晶体管T3的作用下(第三晶体管T3处于截止状态)，可以避免第一信号端S1上的信号经第一晶体管T1写入到驱动晶体管的栅极Td，对驱动晶体管Td栅极电位产生影响，从而影响显示阶段的显示。
发光阶段P3，使能信号端EM输入低电平信号，第一信号端S1、以及扫描信号端S2输入高电平信号，基于此，图3所示的像素电路的等效电路图如图7所示。第七晶体管T7、第八晶体管T8和驱动晶体管Td均打开，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和第六晶体管T6均截止。
例如，第七晶体管T7导通，第一电压端V1的电压写入到存储电容Cst的第一端，存储电容Cst第一端的电压由Vdata变为V1，变化量为ΔV2＝Vdata-V1，基于此，存储电容Cst的第二端的电压变为V2+Vth-ΔV2＝V2+Vth –Vdata+V1，此时，存储电容Cst的第二端的电压降低，控制驱动晶体管Td开启。在驱动晶体管Td和第八晶体管T8均导通时，第二电压端V2的电压经驱动晶体管Td和第八晶体管T8写入到发光器件L的阳极。第三电压端V3的电压写入到发光器件L的阴极，此时发光器件L开启进行画面显示。
在发光阶段P3中，驱动晶体管Td开启后，当驱动晶体管Td的栅-源电压Vgs减去驱动晶体管Td的阈值电压Vth得到的值小于等于驱动晶体管Td的漏-源电压Vds时，即Vgs-Vth≤Vds时，驱动晶体管Td能够处于饱和开启状态，此时流过驱动晶体管Td的驱动电流I为：
Figure PCTCN2018075781-appb-000001
在此处，K＝W/L×C×u，W/L为驱动晶体管Td的宽长比，C为沟道绝缘层电容，u为沟道载流子迁移率。
上述参数只与驱动晶体管Td结构有关，因此，流过驱动晶体管Td的电流只与数据电压端Vdata输出的用于实现显示的数据电压和第一电压端V1输出的电压有关，与驱动晶体管Td的阈值电压Vth无关，从而消除了驱动晶体管Td的阈值电压Vth对发光器件L发光亮度的影响，提高了发光器件L亮度的均一性。
在此基础上，在发光阶段P3中，由于第四晶体管T4的栅-源电压Vgs＝0(在上述数据写入阶段P2，第四晶体管T4的栅-源电压已被设置为Vgs＝0)，而第四晶体管T4上又无阈值电压的损失，即阈值电压Vth＝0，此时，流经第四晶体管T4的电流I为：
Figure PCTCN2018075781-appb-000002
因此，在Td-T6-T4通路上则不会有漏电流产生，从而可减小发光器件L在发光过程中产生的闪烁(flicker)，并提高了显示面板(panel)的效率，可在一定程度上降低功耗。
例如，在数据写入阶段P2，在所述使能信号端的控制下，所述第一晶体 管T1开启，使得所述第四晶体管T4的栅-源电压为零电压；以及在发光阶段P3，所述第一晶体管T1截止，所述第四晶体管T4截止，所述第四晶体管T4的电流为零电流，使得无信号向所述初始电压端Vinit输出(即，不会有漏电流经过第四晶体管T4向所述初始电压端Vinit输出)。
例如，像素电路工作电压(V1/S1/Vinit/Vdata)取值范围决定了驱动晶体管Td栅极的电压范围。在现有像素电路中，驱动晶体管Td栅极电压范围可能为负值可能为正值，此设计对于部分像素电路只能优化部分灰阶的漏电情况。例如，在驱动晶体管Td栅极电压为正值时，栅极吸引负电荷，吸引的负电荷的绝对值越大(小于反向击穿电压)，源电极和漏电极之间的电流会越小，因此，在驱动晶体管Td栅极电压为正值时，流经驱动晶体管Td的电流本身就很小，漏电流更小，优化效果不明显。
在驱动晶体管Td栅极电压为负值时，栅极吸引正电荷，吸引的正电荷的绝对值越大，源电极和漏电极之间的电流会越大，因此，在驱动晶体管Td栅极电压为负值时，流经驱动晶体管Td的电流较大，漏电流对发光器件产生的影响越大，对此，本公开实施例提供的像素电路可以对漏电流进行消除。
本公开实施例提供一种显示装置，包括如上所述的任意一种像素电路。所述显示装置可以包括像素单元阵列，每一个像素单元包括如上所述的任意一个像素电路。本公开实施例提供的显示装置具有与本公开前述实施例提供的像素电路相同或相似的有益效果，由于像素电路在前述实施例中已经进行了详细说明，此处不再赘述。
本公开实施例还提供一种像素电路的驱动方法，如图8所示，该驱动方法包括：
S10、在一帧的初始化阶段P1，在第一信号端S1的控制下，通过初始化模块10将初始电压端Vinit和第一电压端V1的信号输入至驱动模块30，对驱动模块30进行初始化。
S20、在一帧的数据写入阶段P2，在扫描信号端S2的控制下，通过数据写入与补偿模块20将数据电压端Vdata的信号写入至驱动模块30，并对驱动模块30进行阈值电压的补偿。
在使能信号端EM的控制下，通过漏电流消除模块50使初始化模块10在关闭状态下无信号向初始电压端Vinit输出。
S30、在一帧的发光阶段P3，在使能信号端EM的控制下，将第一电压端V1的信号输入至驱动模块30，控制驱动模块30开启，并在使能信号端EM和第三电压端V3的控制下，控制发光单元40进行发光。
由于单个像素中的发光器件(例如有机发光二极管)在发光阶段的电流大小仅为nA级，因此即使很小的漏电也会对发光阶段产生严重的影响。本公开实施例提供一种像素电路的驱动方法，在像素电路中增加与初始化模块10连接的漏电流消除模块50，使得在初始化模块10关闭阶段，在漏电流消除模块50的控制下，初始化模块10无信号向初始电压端Vinit输出(即在发光阶段，流向发光器件的电流不会漏到其他通路中)，从而可以保证流向发光单元40内的电路的稳定性，避免发光单元40在发光过程中出现闪烁(flicker)问题，并且可以一定程度上降低像素电路的功耗。
例如，在第一晶体管T1为N型晶体管，其余晶体管均为P型晶体管时。在使能信号端EM的控制下，通过漏电流消除模块50使初始化模块10在关闭状态下无信号向初始电压端Vinit输出，具体包括：
在所述数据写入阶段，所述使能信号端EM控制第一晶体管T1开启，存储电容Cst第二端的电压经第一晶体管T1输入至第四晶体管T4的栅极，使第四晶体管T4的栅极和第二极的电压均等于存储电容Cst第二端的电压，所述第四晶体管的栅-源电压为零电压。
即，使能信号端EM控制第一晶体管T1开启，使第四晶体管T4的栅-源电压Vgs＝0。
在所述发光阶段，所述使能信号端控制所述第一晶体管截止，所述第四晶体管截止，所述第四晶体管的电流为零电流，使得无信号向所述初始电压端输出。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (11)

  1. 一种像素电路，包括：初始化模块、数据写入与补偿模块、驱动模块、发光单元、以及漏电流消除模块；
    所述初始化模块，分别连接所述驱动模块、第一信号端、第一电压端、以及初始电压端，被配置为在所述第一信号端的控制下，将所述初始电压端的信号和所述第一电压端的信号输入至所述驱动模块，并对所述驱动模块进行初始化；
    所述数据写入与补偿模块，分别连接所述驱动模块、扫描信号端、以及数据电压端，被配置为在所述扫描信号端的控制下，将数据电压端的信号写入至所述驱动模块，并对所述驱动模块进行阈值电压的补偿；
    所述驱动模块，还连接所述发光单元以及所述第二电压端，被配置为在开启状态下将所述第二电压端的信号输出至所述发光单元，以驱动所述发光单元进行发光；
    所述发光单元，还连接所述第一电压端、使能信号端、第三电压端，被配置为在所述使能信号端的控制下，将所述第一电压端的信号输入至所述驱动模块，控制所述驱动模块开启，并在所述使能信号端和所述第三电压端的控制下进行发光；
    所述漏电流消除模块，分别连接所述初始化模块、所述驱动模块、以及所述使能信号端，被配置为在所述使能信号端的控制下，使所述初始化模块在关闭状态下无信号向所述初始电压端输出。
  2. 根据权利要求1所述的像素电路，其中，所漏电流消除模块包括第一晶体管；
    所述第一晶体管的栅极连接所述使能信号端，所述第一晶体管的第一极连接所述驱动模块，所述第一晶体管的第二极连接所述初始化模块。
  3. 根据权利要求2所述的像素电路，其中，所述驱动模块包括存储电容和驱动晶体管；
    所述存储电容的第一端连接所述初始化模块、所述数据写入与补偿模块、以及所述发光单元，所述存储电容的第二端连接所述驱动晶体管的栅极；以及
    所述驱动晶体管的第一极连接所述第二电压端，所述驱动晶体管的第二极连接所述发光单元、以及所述数据写入与补偿模块。
  4. 根据权利要求3所述的像素电路，其中，所述初始化模块包括第二晶体管、第三晶体管和第四晶体管；
    所述第二晶体管的栅极连接所述第一信号端，所述第二晶体管的第一极连接所述第一电压端，所述第二晶体管的第二极连接所述存储电容的第一端；
    所述第三晶体管的栅极连接所述第一信号端，所述第三晶体管的第一极连接所述第一信号端，所述第三晶体管的第二极连接所述第四晶体管的栅极；以及
    所述第四晶体管的第一极连接所述初始电压端，所述第四晶体管的第二极连接所述存储电容的第二端。
  5. 根据权利要求3所述的像素电路，其中，所述数据写入与补偿模块包括第五晶体管和第六晶体管；
    所述第五晶体管的栅极连接所述扫描信号端，所述第五晶体管的第一极连接所述数据电压端，所述第五晶体管的第二极连接所述存储电容的第一端；以及
    所述第六晶体管的栅极连接所述扫描信号端，所述第六晶体管的第一极连接所述驱动晶体管的第二极，所述第六晶体管的第二极连接所述存储电容的第二端。
  6. 根据权利要求3所述的像素电路，其中，所述发光单元包括第七晶体管、第八晶体管、以及发光器件；
    所述第七晶体管的栅极连接所述使能信号端，所述第七晶体管的第一极连接所述第一电压端，所述第七晶体管的第二极连接所述存储电容的第一端；
    所述第八晶体管的栅极连接所述使能信号端，所述第八晶体管的第一极连接所述驱动晶体管的第二极，所述第八晶体管的第二极连接所述发光器件的阳极；
    所述发光器件的阴极连接所述第三电压端；以及
    所述第七晶体管和所述第八晶体管为第一类型的晶体管，所述第一晶体管为第二类型的晶体管。
  7. 根据权利要求6所述的像素电路，其中，
    所述第七晶体管和所述第八晶体管为P型晶体管，所述第一晶体管为N型晶体管；或者，所述第七晶体管和所述第八晶体管为N型晶体管，所述第 一晶体管为P型晶体管。
  8. 根据权利要求4所述的像素电路，其中，
    所述第一晶体管的栅极连接所述使能信号端，所述第一晶体管的第一极连接所述第四晶体管的第二极，所述第一晶体管的第二极连接所述第四晶体管的栅极。
  9. 一种显示装置，包括权利要求1-8任一项所述的像素电路。
  10. 一种像素电路的驱动方法，包括：
    在一帧的初始化阶段，在第一信号端的控制下，通过初始化模块将初始电压端和第一电压端的信号输入至驱动模块，对所述驱动模块进行初始化；
    在一帧的数据写入阶段，在扫描信号端的控制下，通过将数据电压端的信号写入至所述驱动模块，并对所述驱动模块进行阈值电压的补偿；
    在使能信号端的控制下，通过漏电流消除模块使所述初始化模块在关闭状态下无信号向所述初始电压端输出；以及
    在一帧的发光阶段，在所述使能信号端的控制下，将所述第一电压端的信号输入至所述驱动模块，控制所述驱动模块开启，并在所述使能信号端和所述第三电压端的控制下，控制发光单元进行发光。
  11. 根据权利要求10所述的驱动方法，其中，所述漏电流消除模块包括第一晶体管，所述初始化模块包括第四晶体管，所述驱动模块包括存储电容；
    在使能信号端的控制下，通过所述漏电流消除模块使所述初始化模块在关闭状态下无信号向所述初始电压端输出，包括：
    在所述数据写入阶段，所述使能信号端控制所述第一晶体管开启，所述存储电容第二端的电压经所述第一晶体管输入至所述第四晶体管的栅极，使所述第四晶体管的栅极和第二极的电压均等于所述存储电容第二端的电压，所述第四晶体管的栅-源电压为零电压，
    其中，在所述发光阶段，所述使能信号端控制所述第一晶体管截止，所述第四晶体管截止，所述第四晶体管的电流为零电流，使得无信号向所述初始电压端输出。
PCT/CN2018/075781 2017-03-13 2018-02-08 像素电路及其驱动方法、显示装置 Ceased WO2018166312A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/088,600 US11024228B2 (en) 2017-03-13 2018-02-08 Pixel circuit, driving method therefor and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710147593.8A CN106875894B (zh) 2017-03-13 2017-03-13 一种像素电路及其驱动方法、显示装置
CN201710147593.8 2017-03-13

Publications (1)

Publication Number Publication Date
WO2018166312A1 true WO2018166312A1 (zh) 2018-09-20

Family

ID=59171070

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/075781 Ceased WO2018166312A1 (zh) 2017-03-13 2018-02-08 像素电路及其驱动方法、显示装置

Country Status (3)

Country Link
US (1) US11024228B2 (zh)
CN (1) CN106875894B (zh)
WO (1) WO2018166312A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110751927A (zh) * 2019-10-31 2020-02-04 上海天马有机发光显示技术有限公司 像素驱动电路及其驱动方法、显示面板和显示装置
CN112435624A (zh) * 2020-11-12 2021-03-02 合肥维信诺科技有限公司 像素驱动电路、像素驱动电路的驱动方法和显示面板
CN114677957A (zh) * 2022-03-29 2022-06-28 京东方科技集团股份有限公司 一种像素电路、其驱动方法及显示装置

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106875894B (zh) 2017-03-13 2019-01-18 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN107564478B (zh) * 2017-10-18 2025-03-04 京东方科技集团股份有限公司 一种显示面板及其显示方法、显示装置
CN107908310B (zh) 2017-11-13 2019-12-06 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN109949739B (zh) * 2017-12-20 2020-09-22 上海和辉光电股份有限公司 一种像素电路、驱动方法及显示器
CN108682394A (zh) * 2018-04-18 2018-10-19 武汉华星光电半导体显示技术有限公司 一种像素补偿电路及像素补偿方法
CN108682386B (zh) 2018-05-14 2020-03-10 京东方科技集团股份有限公司 一种像素电路及显示面板
CN108806596A (zh) * 2018-06-26 2018-11-13 京东方科技集团股份有限公司 像素驱动电路及方法、显示装置
CN112639949A (zh) * 2018-09-27 2021-04-09 深圳市柔宇科技股份有限公司 一种像素电路和显示面板
CN109036288B (zh) * 2018-09-28 2020-09-22 昆山国显光电有限公司 像素电路及其控制方法
CN109584803B (zh) * 2019-01-04 2021-01-26 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板
CN109686314B (zh) 2019-03-01 2021-01-29 京东方科技集团股份有限公司 像素电路、显示基板和显示装置
CN110264946A (zh) * 2019-05-21 2019-09-20 合肥维信诺科技有限公司 一种像素电路和显示装置
CN110534062A (zh) * 2019-08-30 2019-12-03 昆山国显光电有限公司 Oled像素驱动电路、控制方法及显示装置
CN110767163B (zh) * 2019-11-08 2021-01-26 京东方科技集团股份有限公司 一种像素电路及显示面板
CN111179841B (zh) 2020-02-28 2021-05-11 京东方科技集团股份有限公司 像素补偿电路及其驱动方法、显示装置
CN111508421B (zh) * 2020-04-27 2023-02-21 昆山国显光电有限公司 像素电路及其驱动方法、显示面板及显示装置
CN111627387B (zh) 2020-06-24 2022-09-02 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板及显示装置
CN111724744A (zh) * 2020-07-14 2020-09-29 武汉华星光电半导体显示技术有限公司 像素电路及显示装置
CN111724746B (zh) * 2020-07-21 2021-11-19 京东方科技集团股份有限公司 像素电路及其老化工艺方法、阵列基板
CN112419967B (zh) * 2020-11-19 2022-04-12 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN115602116A (zh) * 2021-07-08 2023-01-13 乐金显示有限公司（Kr） 像素电路和包括像素电路的显示装置
CN113571013B (zh) * 2021-07-13 2022-09-09 京东方科技集团股份有限公司 像素驱动电路、阵列基板及其制备方法、显示装置
CN113724654B (zh) * 2021-08-31 2023-12-12 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示装置
CN117037713A (zh) * 2021-09-29 2023-11-10 京东方科技集团股份有限公司 像素驱动电路、显示面板
CN113920941B (zh) * 2021-11-16 2023-02-24 京东方科技集团股份有限公司 显示模组、驱动方法及显示装置
CN114170967B (zh) * 2021-12-22 2024-08-16 云谷（固安）科技有限公司 阵列基板、阵列基板的制作方法和显示面板
CN117012154A (zh) * 2022-04-27 2023-11-07 成都辰显光电有限公司 像素电路及其驱动方法和显示面板
CN115171608B (zh) * 2022-09-08 2022-12-23 惠科股份有限公司 驱动电路、驱动方法及显示面板
CN115440161B (zh) * 2022-11-09 2023-03-24 惠科股份有限公司 像素驱动电路和显示面板
CN116543703A (zh) * 2023-05-11 2023-08-04 武汉天马微电子有限公司 一种显示面板、显示面板驱动获取方法及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100141644A1 (en) * 2008-12-05 2010-06-10 Lee Baek-Woon Display device and method of driving the same
CN103927981A (zh) * 2014-03-24 2014-07-16 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN104157240A (zh) * 2014-07-22 2014-11-19 京东方科技集团股份有限公司 像素驱动电路、驱动方法、阵列基板及显示装置
CN104751775A (zh) * 2013-12-27 2015-07-01 昆山工研院新型平板显示技术中心有限公司 带有补偿功能的像素电路和驱动方法及显示电路
CN105006218A (zh) * 2015-05-15 2015-10-28 友达光电股份有限公司 像素电路及其驱动方法
CN106875894A (zh) * 2017-03-13 2017-06-20 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100732828B1 (ko) * 2005-11-09 2007-06-27 삼성에스디아이 주식회사 화소 및 이를 이용한 발광 표시장치
KR101965724B1 (ko) * 2012-10-18 2019-04-04 삼성디스플레이 주식회사 표시장치를 위한 발광 구동 장치, 표시장치 및 그 구동 방법
KR101992405B1 (ko) * 2012-12-13 2019-06-25 삼성디스플레이 주식회사 화소 및 이를 이용한 유기전계발광 표시장치
CN103258501B (zh) * 2013-05-21 2015-02-25 京东方科技集团股份有限公司 一种像素电路及其驱动方法
KR102367462B1 (ko) * 2015-08-11 2022-02-25 삼성디스플레이 주식회사 유기 발광 표시 장치
CN106910468B (zh) * 2017-04-28 2019-05-10 上海天马有机发光显示技术有限公司 显示面板、显示装置及像素电路的驱动方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100141644A1 (en) * 2008-12-05 2010-06-10 Lee Baek-Woon Display device and method of driving the same
CN104751775A (zh) * 2013-12-27 2015-07-01 昆山工研院新型平板显示技术中心有限公司 带有补偿功能的像素电路和驱动方法及显示电路
CN103927981A (zh) * 2014-03-24 2014-07-16 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN104157240A (zh) * 2014-07-22 2014-11-19 京东方科技集团股份有限公司 像素驱动电路、驱动方法、阵列基板及显示装置
CN105006218A (zh) * 2015-05-15 2015-10-28 友达光电股份有限公司 像素电路及其驱动方法
CN106875894A (zh) * 2017-03-13 2017-06-20 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110751927A (zh) * 2019-10-31 2020-02-04 上海天马有机发光显示技术有限公司 像素驱动电路及其驱动方法、显示面板和显示装置
CN112435624A (zh) * 2020-11-12 2021-03-02 合肥维信诺科技有限公司 像素驱动电路、像素驱动电路的驱动方法和显示面板
CN112435624B (zh) * 2020-11-12 2022-09-02 合肥维信诺科技有限公司 像素驱动电路、像素驱动电路的驱动方法和显示面板
CN114677957A (zh) * 2022-03-29 2022-06-28 京东方科技集团股份有限公司 一种像素电路、其驱动方法及显示装置

Also Published As

Publication number Publication date
CN106875894A (zh) 2017-06-20
CN106875894B (zh) 2019-01-18
US11024228B2 (en) 2021-06-01
US20200302859A1 (en) 2020-09-24

Similar Documents

Publication Publication Date Title
WO2018166312A1 (zh) 像素电路及其驱动方法、显示装置
CN106652903B (zh) 一种oled像素电路及其驱动方法、显示装置
CN103971640B (zh) 一种像素驱动电路及其驱动方法和显示装置
CN105427803B (zh) 像素驱动电路、方法、显示面板和显示装置
CN108039149B (zh) 一种oled像素电路及其驱动方法、显示装置
WO2023005694A1 (zh) 像素电路及其驱动方法、显示面板
CN104409047B (zh) 像素驱动电路、像素驱动方法和显示装置
CN103165080B (zh) 像素电路及其驱动方法、显示装置
CN109785797B (zh) 一种amoled像素电路
WO2020233025A1 (zh) 像素电路和显示装置
CN205282057U (zh) 像素驱动电路、显示面板和显示装置
CN106531076A (zh) 一种像素电路、显示面板及其驱动方法
WO2017041453A1 (zh) 像素电路、其驱动方法及相关装置
CN110556076B (zh) 像素电路、驱动方法及显示装置
CN113658555A (zh) 一种像素驱动电路、驱动方法及显示面板
WO2016165529A1 (zh) 像素电路及其驱动方法、显示装置
WO2023011333A1 (zh) 像素驱动电路及其驱动方法、显示面板
WO2016150232A1 (zh) 像素电路及其驱动方法、显示装置
CN107799062A (zh) 一种像素电路及其驱动方法、显示装置
CN104700780A (zh) 一种像素电路及其驱动方法、显示装置
CN107369412B (zh) 一种像素电路及其驱动方法、显示装置
WO2016023311A1 (zh) 像素驱动电路及其驱动方法和显示装置
CN106067291A (zh) 一种像素驱动电路及其驱动方法、显示装置
CN110189707A (zh) 一种像素驱动电路及其驱动方法、显示装置
WO2019184916A1 (zh) 像素电路及其驱动方法、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18767350

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18767350

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 17.03.2020)

122 Ep: pct application non-entry in european phase

Ref document number: 18767350

Country of ref document: EP

Kind code of ref document: A1