WO2020233025A1 - 像素电路和显示装置 - Google Patents

像素电路和显示装置 Download PDF

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Publication number
WO2020233025A1
WO2020233025A1 PCT/CN2019/119497 CN2019119497W WO2020233025A1 WO 2020233025 A1 WO2020233025 A1 WO 2020233025A1 CN 2019119497 W CN2019119497 W CN 2019119497W WO 2020233025 A1 WO2020233025 A1 WO 2020233025A1
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Prior art keywords
module
transistor
terminal
pixel circuit
electrically connected
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PCT/CN2019/119497
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English (en)
French (fr)
Inventor
范龙飞
王龙彦
段培
朱晖
韩珍珍
胡思明
张露
吴剑龙
Original Assignee
合肥维信诺科技有限公司
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Application filed by 合肥维信诺科技有限公司 filed Critical 合肥维信诺科技有限公司
Publication of WO2020233025A1 publication Critical patent/WO2020233025A1/zh
Priority to US17/349,293 priority Critical patent/US11436978B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels

Definitions

  • the embodiments of the present application relate to the field of display technology, for example, to a pixel circuit and a display device.
  • organic light-emitting display devices have been used more and more widely.
  • An organic light emitting display device includes a plurality of pixel circuits, and each pixel circuit usually includes a plurality of thin film transistors.
  • the thin film transistors electrically connected to the driving transistors usually have a large leakage current, resulting in the gate potential of the driving transistor Unstable, the display device consumes a lot of power.
  • the present application provides a pixel circuit and a display device, so as to stabilize the potential of the control terminal of the driving module and reduce the power consumption of the display device.
  • an embodiment of the present application provides a pixel circuit including: a light emitting module;
  • a driving module configured to drive the light emitting module to emit light according to the voltage of the control terminal of the driving module;
  • a storage module configured to store the voltage of the control terminal of the drive module
  • the leakage current suppression module is electrically connected to the control terminal of the drive module and is configured to maintain the potential of the control terminal of the drive module.
  • the embodiment of the present application further provides a display device, including the pixel circuit provided in the present application, and further includes a driving chip electrically connected to the pixel circuit.
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the application.
  • FIG. 2 is a schematic structural diagram of another pixel circuit provided by an embodiment of the application.
  • FIG. 3 is a schematic structural diagram of another pixel circuit provided by an embodiment of the application.
  • FIG. 4 is a working timing diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of still another pixel circuit provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 7 is a working timing diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 9 is a working timing diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 12 is a working timing diagram of still another pixel circuit provided by an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • 16 is a schematic structural diagram of still another pixel circuit provided by an embodiment of the present application.
  • FIG. 17 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the thin film transistor electrically connected to the driving transistor has a large leakage current, the gate potential of the driving transistor is unstable, and the display device consumes a lot of power.
  • the reason for the above problem is that the transistor electrically connected to the gate of the driving transistor is usually a low-temperature polysilicon transistor.
  • the thin film transistor formed by the low-temperature polysilicon process has a large lattice gap and high electron mobility, resulting in low-temperature polysilicon.
  • the leakage current of the transistor is large, so that when the driving transistor is driving the light-emitting device to emit light, the gate potential is gradually discharged through the low-temperature polysilicon transistor electrically connected to it, so that the gate potential of the driving transistor cannot be maintained stable during the light-emitting phase, and the display effect is better. difference.
  • it is necessary to increase the driving frequency of the pixel circuit which greatly increases the power consumption of the driving chip and causes the power consumption of the entire display device to be relatively large.
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • the pixel circuit includes: a driving module (also referred to as a driving circuit) 110, a storage The module (may also be called a storage circuit) 120, a light emitting module (may be an organic light emitting device) 130, and a leakage current suppression module (may also be called a leakage current suppression circuit) 140.
  • the driving module 110 is configured to drive the light-emitting module 130 to emit light according to the voltage of the control terminal G1 of the driving module 110;
  • the storage module 120 is configured to store the voltage of the control terminal G1 of the driving module 110;
  • the leakage current suppression module 140 is electrically connected to the control terminal G1 of the driving module 110 and is configured to maintain the potential of the control terminal G1 of the driving module 110.
  • its working sequence when the pixel circuit is working, its working sequence usually includes at least a data writing phase and a light emitting phase.
  • the data writing phase the data voltage is written to the control terminal G1 of the driving module 110 and one end of the storage module 120
  • the driving module 110 controls the light-emitting module 130 to emit light according to the potential of its control terminal G1.
  • the storage module 120 stores and maintains the potential of the control terminal G1 of the drive module 110.
  • the leakage current suppression module 140 electrically connected to the control terminal G1 of the driving module 110 can have a relatively low leakage current, so that the potential of the control terminal of the driving module 110 is not easily discharged.
  • the potential of the control terminal of the driving module 110 can be better maintained, thereby reducing the driving frequency of the pixel circuit, thereby reducing the power consumption of the driving chip, and reducing the power consumption of the entire display device including the pixel circuit.
  • the power consumption of the driver chip accounts for about half of the power consumption of the entire display device. Therefore, for small and medium-sized display devices, the power consumption of the entire display device can be significantly reduced.
  • the leakage current suppression module 140 can make the potential of the control terminal G1 of the driving module 110 not easily discharged, the area of the storage module 120 can be reduced, which is beneficial to increase the pixel density.
  • the leakage current suppression module 140 is an oxide transistor.
  • the leakage current of the oxide transistor in the off state is significantly smaller than the leakage current of the low-temperature polysilicon thin film transistor in the off state. Therefore, in the light-emitting phase, the potential of the control terminal G1 of the driving module 110 is not easily discharged through the leakage current suppression module 140 Therefore, the potential of the control terminal of the driving module 110 can be kept stable, which is beneficial to improve the display effect.
  • the potential of the control terminal G1 of the driving module 110 remains stable, so that the driving frequency of the pixel circuit (for example, the scanning frequency and the frequency of writing data voltage to the control terminal of the driving module) can be reduced, thereby reducing the power consumption of the driving chip and reducing The power consumption of the entire display device including the pixel circuit.
  • the conductivity of the oxide transistors is good, and the threshold voltages of the oxide transistors in the plurality of pixel circuits are relatively uniform, which in turn can make the brightness of the plurality of light-emitting modules 130 more uniform during display and improve the display effect.
  • the oxide transistor may be, for example, an indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO) transistor.
  • the leakage current suppression module can make the potential of the control terminal of the drive module not easily discharged, the area of the memory module can be reduced, which is beneficial to increase the pixel density.
  • the leakage current suppression module 140 includes a control terminal G2, a first terminal, and a second terminal;
  • the control terminal G2 is set to input a control signal to turn on or off the leakage current suppression module 140;
  • the leakage current suppression module 140 is also set to write a data voltage to the control terminal G1 of the driving module 110;
  • the control terminal G2 of the leakage current suppression module 140 is electrically connected to the first scan signal input terminal Scan1 of the pixel circuit, and the first terminal of the leakage current suppression module 140 is electrically connected to the data voltage input terminal Vdata of the pixel circuit.
  • the second end is electrically connected to the control end G1 of the driving module 110;
  • the first terminal of the driving module 110 is electrically connected to the first voltage signal input terminal Vdd of the pixel circuit
  • the second terminal of the driving module 110 is electrically connected to the first terminal of the light emitting module 130
  • the second terminal of the light emitting module 130 is electrically connected to the pixel circuit.
  • the second voltage signal input terminal Vss is electrically connected;
  • Two ends of the storage module 120 are electrically connected to the control terminal G1 of the driving module 110 and the first terminal of the driving module 110 respectively.
  • the leakage current suppression module 140 is configured to control the writing of the data voltage.
  • the leakage current suppression module 140 may be an oxide transistor, for example, an IGZO thin film transistor.
  • the working sequence of the pixel circuit can be divided into a data writing phase and a light emitting phase.
  • the leakage current suppression module 140 is turned on, and the leakage current suppression module 140 whose data voltage is turned on is written to the control of the driving module 110. Terminal G1.
  • the leakage current suppression module 140 is turned off.
  • the leakage current suppression module 140 has a low leakage current in the off state, it can ensure that the potential of the control terminal G1 of the driving module 110 can be kept stable, which can make it possible to include those provided by this embodiment.
  • the scanning frequency of the scan driving circuit and the frequency of the output data voltage of the data driving circuit in the display device of the pixel circuit can be reduced, and the control signals of the scan driving circuit and the data driving circuit are usually provided by the driving chip, thereby enabling the driving of the driving chip The frequency is reduced, thereby reducing the power consumption of the display device including the pixel circuit.
  • the leakage current suppression module 140 includes a first transistor T1
  • the driving module 110 includes a second transistor T2
  • the storage module 120 includes The first capacitor C1
  • the light emitting module 130 includes an organic light emitting diode D1; wherein, the second transistor T2 is a low temperature polysilicon transistor;
  • the gate of the first transistor T1 serves as the control terminal G2 of the leakage current suppression module 140, the first pole of the first transistor T1 serves as the first terminal of the leakage current suppression module 140, and the second pole of the first transistor T1 serves as the leakage current suppression module 140 second end;
  • the gate of the second transistor T2 serves as the control terminal G1 of the driving module 110, the first pole of the second transistor T2 serves as the first terminal of the driving module 110, and the second pole of the second transistor T2 serves as the second terminal of the driving module 110;
  • the two plates of the first capacitor C1 serve as two ends of the memory module 120 respectively;
  • the anode and cathode of the organic light emitting diode D1 serve as the first end and the second end of the light emitting module 130, respectively.
  • the first electrode of the transistor may be a source or a drain.
  • the drain of the second electrode In the case of the drain of the first electrode, the source of the second electrode.
  • FIG. 4 is a working timing diagram of a pixel circuit provided by an embodiment of the present application, and the working timing diagram may correspond to the pixel circuit shown in FIG. 3.
  • the first transistor T1 is an N-type transistor and the second transistor T2 is a P-type transistor as an example for description.
  • the working sequence of the pixel circuit shown in FIG. 3 can be divided into a data writing stage t1. And the light-emitting stage t2.
  • the first scan signal input terminal Scan1 inputs a high level signal
  • the first transistor T1 is turned on
  • the data voltage is written to the second transistor along the turned-on first transistor T1.
  • the first scan signal input terminal Scan1 inputs a low-level signal
  • the first transistor T1 is turned off
  • the second transistor T2 drives the organic light-emitting diode D1 to emit light according to its gate potential.
  • the first transistor T1 can be an oxide transistor, for example, an IGZO transistor. Since the oxide transistor has a lower leakage current in the off state, it can be ensured that the gate potential of the second transistor T2 can remain stable, and further include the The driving frequency of the driving chip in the display device of the pixel circuit is reduced, thereby reducing the power consumption of the display device including the pixel circuit.
  • the gate potential of the second transistor T2 remains stable, so that the capacitance value of the first capacitor C1 does not need to be large to maintain the gate potential of the second transistor T2, so that the area of the first capacitor C1 can be reduced, which is beneficial to Increase pixel density.
  • the pixel circuit provided by this embodiment only includes two thin film transistors, so that the layout space of the pixel circuit is smaller, which is more conducive to improving pixel density.
  • FIG. 5 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • the pixel circuit further includes a data writing module (also referred to as a data writing circuit) 150 and a first light emission control The module (also referred to as the first lighting control circuit) 160;
  • the leakage current suppression module 140 includes a control terminal G2, a first terminal, and a second terminal; the control terminal G2 of the leakage current suppression module 140 is set to input a control signal to make the leakage current
  • the suppression module 140 is turned on or off;
  • the control terminal G3 of the data writing module 150 is electrically connected to the second scan signal input terminal Scan2 of the pixel circuit, the first terminal of the data writing module 150 is electrically connected to the data voltage input terminal Vdata of the pixel circuit, and the data writing module 150 The second end is electrically connected to the first end of the driving module 110;
  • the first terminal of the first light emission control module 160 is electrically connected to the first voltage signal input terminal Vdd of the pixel circuit, the second terminal of the first light emission control module 160 is electrically connected to the first terminal of the driving module 110, and the first light emission control module
  • the control terminal G4 of 160 is electrically connected to the input terminal EM1 of the first emission control signal of the pixel circuit;
  • the control terminal G1 of the driving module 110 is electrically connected to the second terminal of the leakage current suppression module 140, and the second terminal of the driving module 110 is electrically connected to the first terminal of the leakage current suppression module 140, and also to the first terminal of the light emitting module 130. Electrical connection
  • the second terminal of the light emitting module 130 is electrically connected to the second voltage signal input terminal Vss of the pixel circuit.
  • the control terminal G2 of the leakage current suppression module 140 may be electrically connected to the first control signal input terminal Ctrl of the pixel circuit.
  • its working sequence may include a data writing phase and a light emitting phase.
  • the data writing module 150 and the leakage current suppression module 140 are controlled to be turned on, and the first light emitting control module 160 is controlled to turn off, and the data voltage passes through the turned on data writing module 150, the driving module 110 and the leakage current
  • the suppression module 140 writes to the control terminal G1 of the driving module 110.
  • the control data writing module 150 and the leakage current suppression module 140 are turned off, and the first light-emitting control module 160 is turned on. Because the leakage current suppression module 140 has a low leakage current in the off state, it can be ensured that the potential of the control terminal of the driving module 110 can remain stable, thereby improving the display effect, and can make the display device including the pixel circuit provided in this embodiment The driving frequency of the driving chip is reduced, and the power consumption of the display device including the pixel circuit is reduced.
  • the data writing module 150 includes a third transistor T3, the driving module 110 includes a fourth transistor T4, and a leakage current suppression module 140 includes a fifth transistor T5, the first light emission control module 160 includes a sixth transistor T6, the storage module 120 includes a second capacitor C2, the light emitting module 130 includes an organic light emitting diode D1; a third transistor T3, a fourth transistor T4, and a sixth transistor T6 are low temperature polysilicon transistors;
  • the gate of the third transistor T3 serves as the control terminal G3 of the data writing module 150, the first pole of the third transistor T3 serves as the first terminal of the data writing module 150, and the second pole of the third transistor T3 serves as the data writing module 150 second end;
  • the gate of the fourth transistor T4 serves as the control terminal G1 of the driving module 110, the first pole of the fourth transistor T4 serves as the first terminal of the driving module 110, and the second pole of the fourth transistor T4 serves as the second terminal of the driving module 110;
  • the gate of the fifth transistor T5 serves as the control terminal G2 of the leakage current suppression module 140, the first pole of the fifth transistor T5 serves as the first terminal of the leakage current suppression module 140, and the second pole of the fifth transistor T5 serves as the leakage current suppression module. 140 second end;
  • the gate of the sixth transistor T6 serves as the control terminal G4 of the first light emission control module 160, the first electrode of the sixth transistor T6 serves as the first terminal of the first light emission control module 160, and the second electrode of the sixth transistor T6 serves as the first terminal G4.
  • the two plates of the second capacitor C2 serve as two ends of the storage module 120 respectively;
  • the anode and cathode of the organic light emitting diode D1 serve as the first end and the second end of the light emitting module 130, respectively.
  • FIG. 7 is a working timing diagram of another pixel circuit provided by an embodiment of the present application.
  • the working timing diagram may correspond to the pixel circuit shown in FIG. 6.
  • the working timing of the pixel circuit shown in FIG. 6 includes Data writing stage and light emitting stage.
  • the fifth transistor T5 may be an oxide transistor or an IGZO transistor.
  • FIG. 6 schematically illustrates an example in which the fifth transistor T5 is an N-type transistor and the other transistors are P-type transistors.
  • the second scan signal input terminal Scan2 inputs low level
  • the third transistor T3 is turned on; the first control signal input terminal Ctrl inputs high level, the fifth transistor T5 is turned on ON, the first light-emitting control signal input terminal EM1 inputs a high level, the sixth transistor T6 is turned off, and the data voltage is written to the fourth transistor T4 along the turned-on third transistor T3, fourth transistor T4, and fifth transistor T5.
  • the second scan signal input terminal Scan2 inputs a high level
  • the third transistor T3 is turned off
  • the first control signal input terminal Ctrl inputs a low level
  • the fifth transistor T5 is turned off
  • the first light-emitting control signal input terminal EM1 is input
  • the sixth transistor T6 is turned on
  • the fourth transistor T4 drives the organic light emitting diode D1 to emit light.
  • the fifth transistor T5 may be an oxide transistor, for example, an IGZO transistor.
  • the oxide transistor Since the oxide transistor has a lower leakage current in the off state, it can be ensured that the gate potential of the fourth transistor T4 can remain stable, thereby making the The driving frequency of the pixel circuit can be reduced, thereby reducing the power consumption of the display device including the pixel circuit.
  • the oxide transistor since the oxide transistor has a lower leakage current in the off state, it can be ensured that the gate potential of the fourth transistor T4 can remain stable, so that the capacitance value of the second capacitor C2 does not need to be large to maintain the gate of the fourth transistor T4.
  • the electric potential of the electrode can reduce the area of the second capacitor C2, which is beneficial to increase the pixel density.
  • FIG. 8 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • the channel types of the fifth transistor T5 and the sixth transistor T6 are different, and the fifth The gate of the transistor T5 is electrically connected to the first light emission control signal input terminal EM1 of the pixel circuit.
  • the fifth transistor T5 and the sixth transistor T6 have different on-off states in multiple working stages of the pixel circuit. Therefore, the channel types of the fifth transistor T5 and the sixth transistor T6 are different, so that the fifth transistor T5 and the sixth transistor T6 can use a control line for control, which is beneficial to reduce the wiring of the display device including the pixel circuit, and is beneficial to realize the narrow frame of the display device.
  • the fifth transistor T5 is an N-type transistor.
  • FIG. 9 is a working timing diagram of another pixel circuit provided by an embodiment of the present application.
  • the working timing diagram may correspond to the pixel circuit shown in FIG. 8.
  • the working timing of the pixel circuit shown in FIG. 8 includes Data writing stage and light emitting stage.
  • the fifth transistor T5 may be an oxide transistor, for example, an IGZO transistor.
  • FIG. 8 schematically illustrates an example in which the fifth transistor T5 is an N-type transistor and the other transistors are P-type transistors.
  • the second scan signal input terminal Scan2 inputs a low level
  • the third transistor T3 is turned on
  • the first light emission control signal input terminal EM1 inputs a high level
  • the fifth transistor T5 Turn on
  • the sixth transistor T6 is turned off, and the data voltage is written to the gate of the fourth transistor T4 along the turned-on third transistor T3, the fourth transistor T4, and the fifth transistor T5.
  • where VDD is the voltage input from the first voltage signal input terminal Vdd, and Vth is the threshold voltage of the fourth transistor T4
  • the fourth transistor T4 is turned off to complete the gate potential of the fourth transistor T4 Compensation for writing and threshold voltage.
  • the second scanning signal input terminal Scan2 is inputted with a high level
  • the third transistor T3 is turned off
  • the first light-emitting control signal input terminal EM1 is input with a low level
  • the fifth transistor T5 is turned off
  • the sixth transistor T6 is turned on.
  • the four-transistor T4 drives the organic light emitting diode D1 to emit light.
  • the fifth transistor T5 may be an oxide transistor, for example, an IGZO transistor.
  • the oxide transistor Since the oxide transistor has a lower leakage current in the off state, it can be ensured that the gate potential of the fourth transistor T4 can remain stable, thereby making the The driving frequency of the pixel circuit can be reduced, thereby reducing the power consumption of the display device including the pixel circuit.
  • the oxide transistor since the oxide transistor has a lower leakage current in the off state, it can be ensured that the gate potential of the fourth transistor T4 can remain stable, so that the capacitance value of the second capacitor C2 does not need to be large to maintain the gate of the fourth transistor T4.
  • the electric potential of the electrode can reduce the area of the second capacitor C2, which is beneficial to increase the pixel density.
  • FIG. 10 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • the pixel circuit further includes an initialization module (also referred to as an initialization circuit) 170,
  • the initialization module 170 includes a control terminal G5, a first terminal, and a second terminal.
  • the control terminal G5 of the initialization module 170 is electrically connected to the third scan signal input terminal Scan3 of the pixel circuit.
  • the first terminal of the initialization module 170 is connected to the initialization voltage of the pixel circuit.
  • the input terminal Vref is electrically connected, and the second terminal of the initialization module 170 is electrically connected to the first terminal of the light emitting module 130.
  • the pixel circuit when the pixel circuit is working, its working sequence may include an initialization phase, a data writing phase, and a light-emitting phase.
  • the initialization module 170 is turned on, the first light emitting control module 160, the data writing module 150, and the leakage current suppression module 140 are turned off, and the potential of the first terminal of the light emitting module 130 is initialized to Vref;
  • the initialization module 170 is turned off, the data writing module 150 and the leakage current suppression module 140 are turned on, the first light emitting control module 160 is turned off, and the data voltage passes through the turned-on data writing module 150, the driving module 110 and the drain
  • the current suppression module 140 writes to the control terminal G1 of the driving module 110;
  • the initialization module 170, the data writing module 150, and the leakage current suppression module 140 are turned off, and the first light-emitting control module 160 is turned on. Because the leakage current suppression module 140 has a low leakage current in the off state, it can be ensured that the potential of the control terminal G1 of the driving module 110 can remain stable, thereby reducing the driving frequency of the pixel circuit, thereby reducing the display including the pixel circuit. The power consumption of the device.
  • the pixel circuit provided in this embodiment includes an initialization module.
  • the initialization module can initialize the potential of the first terminal of the light-emitting module and the potential of the control terminal of the drive module, so that the potential of the control terminal of the drive module and the potential of the first terminal of the light-emitting module are Leakage to avoid the impact of residual charges on the display screen of the current frame from the control terminal of the drive module and the first terminal of the light-emitting module when the previous frame is driven, which is beneficial to improve the display effect.
  • FIG. 11 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • the initialization module 170 includes a seventh transistor T7, and the gate of the seventh transistor T7 is used as the control terminal G5 of the initialization module 170 ,
  • the first pole of the seventh transistor T7 serves as the first terminal of the initialization module 170, and the second pole of the seventh transistor T7 serves as the second terminal of the initialization module 170.
  • FIG. 12 is a working timing diagram of still another pixel circuit provided by an embodiment of the present application.
  • the working timing diagram may correspond to the pixel circuit shown in FIG. 11.
  • the working timing of the pixel circuit shown in FIG. 11 includes The initialization phase t11, the data writing phase t12, and the light emitting phase t13.
  • FIG. 11 schematically illustrates an example in which the fifth transistor T5 is an N-type transistor and the other transistors are P-type transistors.
  • the second scan signal input terminal Scan2 inputs a high level
  • the third transistor T3 is turned off
  • the third scan signal input terminal Scan3 inputs a low level
  • the seventh transistor T7 is turned on
  • a control signal input terminal Ctrl inputs a high level
  • the fifth transistor T5 is turned on
  • the first light emission control signal input terminal EM1 inputs a high level
  • the sixth transistor T6 is turned off
  • the initialization voltage input from the initialization voltage input terminal Vref passes the The seventh transistor T7 is written to the anode of the organic light emitting diode D1; and the seventh transistor T7 and the fifth transistor T5 are turned on to write to the gate of the fourth transistor T4.
  • the second scan signal input terminal Scan2 inputs low level
  • the third transistor T3 is turned on
  • the third scan signal input terminal Scan3 inputs high level
  • the seventh transistor T7 is turned off
  • the first control signal input terminal Ctrl input high level
  • fifth transistor T5 is turned on
  • first light emission control signal input terminal EM1 is input high level
  • sixth transistor T6 is turned off
  • the data voltage is along the turned on third transistor T3, fourth transistor T4 and The five-transistor T5 is written to the gate of the fourth transistor T4, and completes the writing of the gate potential of the fourth transistor T4 and the compensation of the threshold voltage.
  • the second scan signal input terminal Scan2 inputs a high level
  • the third transistor T3 is turned off
  • the third scan signal input terminal Scan3 inputs a high level
  • the seventh transistor T7 is turned off
  • the first control signal input terminal Ctrl inputs a low level.
  • the fifth transistor T5 is turned off
  • the first light-emitting control signal input terminal EM1 is input with a low level
  • the sixth transistor T6 is turned on
  • the fourth transistor T4 drives the organic light-emitting diode D1 to emit light.
  • the fifth transistor T5 may be an oxide transistor, for example, an IGZO transistor.
  • the oxide transistor Since the oxide transistor has a lower leakage current in the off state, it can ensure that the gate potential of the fourth transistor T4 can remain stable, thereby making it possible to include
  • the driving chip of the pixel circuit reduces the driving frequency of the pixel circuit, thereby reducing the power consumption of the display device including the pixel circuit.
  • the channel types of the fifth transistor and the sixth transistor are different. For example, when the fifth transistor T5 is an N-type transistor and the sixth transistor T6 is a P-type transistor, it is different from the fifth transistor.
  • the first control signal input terminal Ctrl electrically connected to the gate of T5 and the first light emission control signal input terminal EM1 electrically connected to the gate of the sixth transistor T6 have the same timings in the multiple working stages of the pixel circuit. Therefore, at this time
  • the pixel circuit may not be provided with the first control signal input terminal Ctrl, and the gate of the fifth transistor T5 can be connected to the first light emission control signal input terminal EM1, so that the fifth transistor T5 and the sixth transistor T6 can use one control line to
  • the control is beneficial to reduce the wiring of the display device including the pixel circuit, and is beneficial to realize the narrow frame of the display device.
  • the pixel circuit provided in this embodiment includes a seventh transistor.
  • the initialization voltage input terminal can initialize the anode potential of the organic light emitting diode and the gate potential of the fourth transistor through the seventh transistor, so that the gate potential of the fourth transistor is The anode potential of the organic light-emitting diode and the organic light-emitting diode are discharged during the initialization stage to avoid the influence of the residual charge of the gate of the fourth transistor and the anode of the organic light-emitting diode on the display screen of this frame during the driving of the previous frame, which is beneficial to improve the display effect.
  • FIG. 13 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • the pixel circuit further includes a second light-emitting control module (also called a second light-emitting control circuit) 180.
  • the first end of the light emitting control module 180 is electrically connected to the second end of the driving module 110, the second end of the second light emitting control module 180 is electrically connected to the first end of the light emitting module 130, and the control end of the second light emitting control module 180 G6 is electrically connected to the second light emission control signal input terminal EM2 of the pixel circuit.
  • its working sequence may include an initialization phase, a data writing phase, and a light-emitting phase.
  • the initialization module 170 is turned on, the first light-emitting control module 160, the second light-emitting control module 180, the data writing module 150, and the leakage current suppression module 140 are turned off, and the potential of the first terminal of the light-emitting module 130 is initialized Is Vref;
  • the initialization module 170 is turned off, the data voltage writing module and the leakage current suppression module 140 are turned on, the first light-emitting control module 160 and the second light-emitting module 180 are turned off, and the data voltage passes through the turned-on data writing module 150.
  • the drive module 110 and the leakage current suppression module 140 write to the control terminal G1 of the drive module 110;
  • the initialization module 170, the data writing module 150, and the leakage current suppression module 140 are turned off, and the first light-emitting control module 160 and the second light-emitting control module 180 are turned on. Because the leakage current suppression module 140 has a lower leakage current in the off state, it can ensure that the potential of the control terminal G1 of the driving module 110 can remain stable, thereby reducing the driving frequency of the driving chip and reducing the power of the display device containing the pixel circuit. Consumption.
  • the control terminal G6 of the second lighting control module 180 and the control terminal G4 of the first lighting control module 160 are also It can be electrically connected to the same light-emitting control signal input terminal, thereby reducing the number of light-emitting control signal lines, which is beneficial to realize a narrow frame.
  • the second light emission control module 180 can also be controlled to be turned on and the leakage current suppression module 140 is turned on, so that the initialization voltage input from the initialization voltage input terminal Vref passes through the turned-on initialization module 170 and the second The light-emitting control module 180 and the leakage current suppression module 140 are written to the control terminal G1 of the driving module 110, so that the potential of the control terminal of the driving module 110 is initialized, thereby making it easier to write the data voltage during the data writing phase.
  • the first light emitting control module 160 and the data writing module 150 are still turned off. In this case, the control terminal of the first lighting control module 160 and the control terminal of the second lighting control module 180 are electrically connected to different lighting control signal input terminals.
  • the second light emission control module 180 includes an eighth transistor T8, a first electrode of the eighth transistor T8 and a fourth transistor
  • the second electrode of T4 is electrically connected
  • the second electrode of the eighth transistor T8 is electrically connected to the anode of the organic light emitting diode D1
  • the gate of the eighth transistor T8 is electrically connected to the second light emitting control signal input terminal EM2 of the pixel circuit.
  • FIG. 15 is a working timing diagram of another pixel circuit provided by an embodiment of the present application.
  • the working timing diagram may correspond to the pixel circuit shown in FIG. 14.
  • the working timing of the pixel circuit shown in FIG. 14 includes The initialization phase t11, the data writing phase t12, and the light emitting phase t13.
  • FIG. 14 schematically illustrates an example in which the fifth transistor T5 is an N-type transistor and the other transistors are P-type transistors.
  • the second scan signal input terminal Scan2 inputs a high level
  • the third transistor T3 is turned off
  • the third scan signal input terminal Scan3 inputs a low level
  • the seventh transistor T7 is turned on
  • An emission control signal input terminal EM1 inputs a high level
  • the sixth transistor T6 is turned off
  • the first control signal input terminal Ctrl inputs a high level
  • the fifth transistor T5 turns on
  • a second emission control signal input terminal EM2 inputs a low level
  • the eighth transistor T8 is turned on, and the anode of the organic light emitting diode D1 and the gate of the fourth transistor T4 are initialized to the potential of the initialization voltage input terminal Vref.
  • the second scan signal input terminal Scan2 inputs a low level
  • the third transistor T3 is turned on
  • the third scan signal input terminal Scan3 inputs a high level
  • the seventh transistor T7 is turned off
  • the first control signal input terminal Ctrl input high level
  • the fifth transistor T5 is turned on
  • the first light emission control signal input terminal EM1 is input high level
  • the sixth transistor T6 is turned off
  • the second light emission control signal input terminal EM2 is input high level
  • the eighth transistor T8 is turned off ;
  • the data voltage is written to the gate of the fourth transistor T4 along the turned-on third transistor T3, the fourth transistor T4 and the fifth transistor T5, and completes the compensation of the threshold voltage of the fourth transistor T4.
  • the second scan signal input terminal Scan2 inputs a high level
  • the third transistor T3 is turned off
  • the third scan signal input terminal Scan3 inputs a high level
  • the seventh transistor T7 is turned off
  • the first control signal input terminal Ctrl inputs a low level Level
  • the fifth transistor T5 is turned off
  • the first light emission control signal input terminal EM1 is input low level
  • the sixth transistor T6 is turned on
  • the second light emission control signal input terminal EM2 is input low level
  • the eighth transistor T8 is turned on
  • the four-transistor T4 drives the organic light emitting diode D1 to emit light.
  • the fifth transistor T5 can be an oxide transistor, for example, an IGZO transistor, because the oxide transistor has a lower leakage current in the off state, which can ensure that the gate potential of the fourth transistor T4 can remain stable and improve the display effect
  • the drive chip of the display device including the pixel circuit can reduce the driving frequency of the pixel circuit, thereby reducing the power consumption of the display device including the pixel circuit. 14 and 15, because the control signal input from the gate of the fifth transistor T5 and the control signal input from the gate of the sixth transistor T6 are the same in multiple stages, the gate of the fifth transistor T5 and the sixth transistor The gate of T6 can be electrically connected to the same control signal input terminal.
  • the gate of the fifth transistor T5 is also electrically connected to the first light emission control signal input terminal EM1, so that the first control signal input terminal Ctrl in the pixel circuit can be reduced. Furthermore, the corresponding control signal lines are reduced, which is beneficial to realize the narrow frame of the display device including the pixel circuit.
  • FIG. 16 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor are all double-gate transistors.
  • each transistor in the pixel circuit is configured as a dual-gate transistor, which can reduce the leakage current in the pixel circuit, so that the In the stage, the gate potential of the fourth transistor T4 (driving transistor) can be better maintained, which improves the display effect, and can reduce the driving frequency of the pixel circuit and reduce the power consumption of the entire display device.
  • the transistor in any of the above-mentioned embodiments of the present application may be a double-gate transistor, thereby reducing the leakage current in the pixel circuit.
  • FIG. 17 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the display device 200 also includes a scan The driving circuit 210, the data driving circuit 220 and the driving chip 230.
  • the data driving circuit 220 is integrated in the driving chip 230, as well as multiple data lines (D1, D2, D3...) and multiple scan lines (S1, S2, S3...) ...); the port of the scan driving circuit 210 is electrically connected to the scan line, and the port of the data driving circuit 220 is electrically connected to the data line; taking the display device including the pixel circuit shown in FIG. 2 as an example, referring to FIG.
  • the pixel circuit includes a data voltage input Terminal Vdata, the first scan signal input terminal Scan1, the data voltage input terminal Vdata of each pixel circuit is connected to a data line, and the first scan signal input terminal Scan1 of each pixel circuit is connected to a scan line, as shown schematically in FIG. 17
  • the data voltage input terminal Vdata and the first scan signal input terminal Scan1 of the pixel circuit corresponding to one pixel are shown.
  • the display device provided by the embodiment of the present application includes the pixel circuit provided by any embodiment of the present application.
  • the module electrically connected to the control terminal of the drive module as a leakage current suppression module
  • the potential of the control terminal of the drive module can not be easily discharged
  • the control terminal of the drive module can be better maintained, and the display effect can be improved; and the drive frequency of the pixel circuit can be reduced, thereby reducing the power consumption of the drive chip in the display device containing the pixel circuit, and reducing the pixel circuit.
  • the power consumption of the entire display device of the circuit because the leakage current suppression module can make the potential of the control terminal of the drive module not easily discharged, the area of the memory module can be reduced, which is beneficial to increase the pixel density.

Abstract

一种像素电路和显示装置（200），其中，像素电路包括：发光模块（130）；驱动模块（110），驱动模块（110）设置为根据驱动模块（110）的控制端（G1）的电压驱动发光模块（130）发光；存储模块（120），存储模块（120）设置为存储驱动模块（110）的控制端（G1）的电压；漏电流抑制模块（140），漏电流抑制模块（140）与驱动模块（110）的控制端（G1）电连接，设置为保持驱动模块（110）的控制端（G1）的电位。

Description

像素电路和显示装置
本申请要求在2019年05月21日提交中国专利局、申请号为201910425396.7的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及显示技术领域，例如涉及一种像素电路和显示装置。
背景技术
随着显示技术的发展，有机发光显示装置得到越来越广泛的应用。
有机发光显示装置中包括多个像素电路，每个像素电路通常包括多个薄膜晶体管，相关技术的像素电路中，与驱动晶体管电连接的薄膜晶体管通常漏电流较大，造成驱动晶体管的栅极电位不稳定，显示装置功耗较大。
发明内容
本申请提供一种像素电路和显示装置，以实现稳定驱动模块控制端的电位，降低显示装置的功耗。
在一实施例中，本申请实施例提供了一种像素电路，包括：发光模块；
驱动模块，所述驱动模块设置为根据所述驱动模块的控制端的电压驱动所述发光模块发光；
存储模块，所述存储模块设置为存储所述驱动模块的控制端的电压；
漏电流抑制模块，所述漏电流抑制模块与所述驱动模块的控制端电连接，设置为保持所述驱动模块的控制端的电位。
在一实施例中，本申请实施例还提供了一种显示装置，包括本申请提供的像素电路，还包括与像素电路电连接的驱动芯片。
附图说明
图1为本申请实施例提供的一种像素电路的结构示意图；
图2为本申请实施例提供的另一种像素电路的结构示意图；
图3为本申请实施例提供的又一种像素电路的结构示意图；
图4是本申请实施例提供的一种像素电路的工作时序图；
图5是本申请实施例提供的再一种像素电路的结构示意图；
图6是本申请实施例提供的还一种像素电路的结构示意图；
图7是本申请实施例提供的另一种像素电路的工作时序图；
图8是本申请实施例提供的还一种像素电路的结构示意图；
图9是本申请实施例提供的又一种像素电路的工作时序图；
图10是本申请实施例提供的还一种像素电路的结构示意图；
图11是本申请实施例提供的还一种像素电路的结构示意图
图12是本申请实施例提供的再一种像素电路的工作时序图；
图13是本申请实施例提供的还一种像素电路的结构示意图；
图14是本申请实施例提供的还一种像素电路的结构示意图；
图15是本申请实施例提供的还一种像素电路的工作时序图；
图16是本申请实施例提供的还一种像素电路的结构示意图；
图17是本申请实施例提供的一种显示装置的结构示意图。
具体实施方式
下面结合附图和实施例对本申请进行说明。此处所描述的实施例仅仅用于解释本申请，而非对本申请的限定。为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。
像素电路中，如果与驱动晶体管电连接的薄膜晶体管漏电流较大，造成驱动晶体管的栅极电位不稳定，显示装置功耗较大。出现上述问题的原因在于，与驱动晶体管栅极电连接的晶体管通常为低温多晶体硅晶体管，因采用低温多晶硅工艺形成的薄膜晶体管晶格间隙较大，电子迁移率较高，造成低温多晶体硅晶体管的漏电流较大，使得驱动晶体管在驱动发光器件发光时，栅极电位通过与其电连接的低温多晶硅晶体管逐渐被泄放，使得在发光阶段驱动晶体管的栅极电位无法维持稳定，显示效果较差。为保证显示效果，则需提高对像素电路的驱动频率，造成驱动芯片的功耗大大增加，造成整个显示装置的功耗较大。
基于上述问题，本申请实施例提供了一种像素电路，图1为本申请实施例提供的一种像素电路的结构示意图，该像素电路包括：驱动模块(也可称为驱动电路)110、存储模块(也可称为存储电路)120、发光模块(可以为有机发光器件)130和漏电流抑制模块(也可称为漏电流抑制电路)140。
在一实施例中，驱动模块110设置为根据驱动模块110的控制端G1的电压驱动发光模块130发光；
存储模块120设置为存储驱动模块110的控制端G1的电压；
漏电流抑制模块140与驱动模块110的控制端G1电连接，设置为保持驱动模块110的控制端G1的电位。
在一实施例中，像素电路工作时，其工作时序通常至少包括数据写入阶段和发光阶段，在数据写入阶段，数据电压被写入到驱动模块110的控制端G1以及存储模块120的一端；在发光阶段，驱动模块110根据其控制端G1的电位控制发光模块130发光。并且，在发光阶段，存储模块120对驱动模块110控制端G1的电位进行存储保持。本申请实施例的像素电路中，与驱动模块110的控制端G1电连接的漏电流抑制模块140可具有较低的漏电流，进而可以使得驱动模块110的控制端的电位不容易被泄放掉，使驱动模块110控制端的电位可以得到较好地保持，进而可以使得对像素电路的驱动频率降低，进而降低驱动芯片的功耗，降低包括该像素电路的整个显示装置的功耗，对于中小尺寸显示装置来说，驱动芯片的功耗占整个显示装置功耗的一半左右，因此对于中小尺寸的显示装置来说，整个显示装置的功耗可以显著降低。并且，因漏电流抑制模块140可以使得驱动模块110的控制端G1的电位不容易被泄放，使得存储模块120的面积可以减小，进而有利于提高像素密度。
可选的，漏电流抑制模块140为氧化物晶体管。氧化物晶体管在截止状态时的漏电流明显小于低温多晶硅薄膜晶体管在截止状态时的漏电流，因此在发光阶段，可以使得驱动模块110控制端G1的电位不容易通过漏电流抑制模块140被泄放，使得驱动模块110控制端的电位可以保持稳定，有利于提高显示效果。并且，驱动模块110控制端G1的电位保持稳定，使得对像素电路的驱动频率(例如是扫描频率以及向驱动模块控制端写入数据电压的频率)可以降低，进而降低驱动芯片的功耗，降低包括该像素电路的整个显示装置的功耗。并且氧化物晶体管的导电均匀性好，多个像素电路中氧化物晶体管的阈值电压大小较为均匀，进而可以使得显示时多个发光模块130的亮度更加均匀，提高显示效果。其中，氧化物晶体管例如可以是铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)晶体管。
本申请实施例提供的像素电路，通过设置与驱动模块控制端电连接的模块为漏电流抑制模块，可以使得驱动模块的控制端的电位不容易被泄放掉，使驱动模块控制端的电位可以得到较好地保持，提高显示效果；并且可以使得对像素电路的驱动频率降低，进而降低包含该像素电路的显示装置中驱动芯片的功耗，降低包括该像素电路的整个显示装置的功耗。并且，因漏电流抑制模块可以使得驱动模块的控制端的电位不容易被泄放，使得存储模块的面积可以减小，进而有利于提高像素密度。
图2为本申请实施例提供的另一种像素电路的结构示意图，参考图2，可选的，漏电流抑制模块140包括控制端G2、第一端和第二端；漏电流抑制模块140的控制端G2设置为输入控制信号以使漏电流抑制模块140导通或关断；漏电流抑制模块140还设置为向驱动模块110的控制端G1写入数据电压；
漏电流抑制模块140的控制端G2与像素电路的第一扫描信号输入端Scan1电连接，漏电流抑制模块140的第一端与像素电路的数据电压输入端Vdata电连接，漏电流抑制模块140的第二端与驱动模块110的控制端G1电连接；
驱动模块110的第一端与像素电路的第一电压信号输入端Vdd电连接，驱动模块110的第二端与发光模块130的第一端电连接，发光模块130的第二端与像素电路的第二电压信号输入端Vss电连接；
存储模块120的两端分别与驱动模块110的控制端G1和驱动模块110的第一端电连接。
参考图2，漏电流抑制模块140设置为控制数据电压的写入，该漏电流抑制模块140可为氧化物晶体管，例如可以是IGZO薄膜晶体管。该像素电路的工作时序可以划分为数据写入阶段和发光阶段，在数据写入阶段，漏电流抑制模块140导通，数据电压沿导通的漏电流抑制模块140写入到驱动模块110的控制端G1。在发光阶段，漏电流抑制模块140截止，因漏电流抑制模块140在截止状态具有较低的漏电流，进而可以保证驱动模块110控制端G1的电位可以保持稳定，可以使得包括本实施例提供的像素电路的显示装置中的扫描驱动电路的扫描频率和数据驱动电路的输出数据电压的频率都可以降低，而扫描驱动电路和数据驱动电路的控制信号通常由驱动芯片提供，进而使得驱动芯片的驱动频率降低，进而降低包含该像素电路的显示装置的功耗。
图3为本申请实施例提供的又一种像素电路的结构示意图，参考图3，可选的，漏电流抑制模块140包括第一晶体管T1，驱动模块110包括第二晶体管T2，存储模块120包括第一电容C1，发光模块130包括有机发光二极管D1；其中，第二晶体管T2为低温多晶硅晶体管；
第一晶体管T1的栅极作为漏电流抑制模块140的控制端G2，第一晶体管T1的第一极作为漏电流抑制模块140的第一端，第一晶体管T1的第二极作为漏电流抑制模块140的第二端；
第二晶体管T2的栅极作为驱动模块110的控制端G1，第二晶体管T2的第一极作为驱动模块110的第一端，第二晶体管T2的第二极作为驱动模块110的第二端；
第一电容C1的两个极板分别作为存储模块120的两端；
有机发光二极管D1的阳极和阴极分别作为发光模块130的第一端和第二端。
在一实施例中，晶体管的第一极可以是源极，也可以是漏极。在第一极为源极的情况下，第二极为漏极；在第一极为漏极的情况下，第二极为源极。
图4是本申请实施例提供的一种像素电路的工作时序图，该工作时序图可对应图3所示的像素电路。其中，参考图3，以第一晶体管T1为N型晶体管，第二晶体管T2为P型晶体管为例进行说明，参考图4，图3所示像素电路的工作时序可分为数据写入阶段t1和发光阶段t2。
参考图3和图4，在数据写入阶段t1，第一扫描信号输入端Scan1输入高电平信号，第一晶体管T1导通，数据电压沿着导通的第一晶体管T1写入到第二晶体管T2的栅极。
在发光阶段t2，第一扫描信号输入端Scan1输入低电平信号，第一晶体管T1截止，第二晶体管T2根据其栅极电位驱动有机发光二极管D1发光。其中，第一晶体管T1可为氧化物晶体管，例如可以是IGZO晶体管，因氧化物晶体管在截止状态具有较低的漏电流，进而可以保证第二晶体管T2的栅极电位可以保持稳定，进而包含该像素电路的显示装置中的驱动芯片的驱动频率降低，进而降低包含该像素电路的显示装置的功耗。并且，第二晶体管T2的栅极电位保持稳定，可以使得第一电容C1的电容值无需很大即可保持第二晶体管T2栅极的电位，使得第一电容C1的面积可以减小，有利于提高像素密度。并且，本实施例提供的像素电路，只包括两个薄膜晶体管，使得像素电路的版图空间较小，更加有利于提高像素密度。
图5是本申请实施例提供的再一种像素电路的结构示意图，参考图5，可选的，像素电路还包括数据写入模块(也可称为数据写入电路)150和第一发光控制模块(也可称为第一发光控制电路)160；漏电流抑制模块140包括控制端G2、第一端和第二端；漏电流抑制模块140的控制端G2设置为输入控制信号以使漏电流抑制模块140导通或关断；
数据写入模块150的控制端G3与像素电路的第二扫描信号输入端Scan2电连接，数据写入模块150的第一端与像素电路的数据电压输入端Vdata电连接，数据写入模块150的第二端与驱动模块110的第一端电连接；
第一发光控制模块160的第一端与像素电路的第一电压信号输入端Vdd电连接，第一发光控制模块160的第二端与驱动模块110的第一端电连接，第一发光控制模块160的控制端G4与像素电路的第一发光控制信号的输入端EM1电连接；
驱动模块110的控制端G1与漏电流抑制模块140的第二端电连接，驱动模块110的第二端与漏电流抑制模块140的第一端电连接，以及还与发光模块130的第一端电连接；
发光模块130的第二端与像素电路的第二电压信号输入端Vss电连接。
参考图5，漏电流抑制模块140的控制端G2可与像素电路的第一控制信号输入端Ctrl电连接。该像素电路工作时，其工作时序可包括数据写入阶段和发光阶段。其中，在数据写入阶段，控制数据写入模块150和漏电流抑制模块140导通，控制第一发光控制模块160截止，数据电压通过导通的数据写入模块150、驱动模块110和漏电流抑制模块140写入到驱动模块110控制端G1。
在发光阶段，控制数据写入模块150和漏电流抑制模块140关断，第一发光控制模块160导通。因漏电流抑制模块140在截止状态具有较低的漏电流，进而可以保证驱动模块110控制端的电位可以保持稳定，进而可以提高显示效果，并且可以使得包含本实施例提供的像素电路的显示装置中驱动芯片的驱动频率降低，降低包含该像素电路的显示装置的功耗。
图6是本申请实施例提供的还一种像素电路的结构示意图，参考图6，可选的，数据写入模块150包括第三晶体管T3，驱动模块110包括第四晶体管T4，漏电流抑制模块140包括第五晶体管T5，第一发光控制模块160包括第六晶体管T6，存储模块120包括第二电容C2，发光模块130包括有机发光二极管D1；第三晶体管T3、第四晶体管T4和第六晶体管T6均为低温多晶硅晶体管；
第三晶体管T3的栅极作为数据写入模块150的控制端G3，第三晶体管T3的第一极作为数据写入模块150的第一端，第三晶体管T3的第二极作为数据写入模块150的第二端；
第四晶体管T4的栅极作为驱动模块110的控制端G1，第四晶体管T4的第一极作为驱动模块110的第一端，第四晶体管T4的第二极作为驱动模块110的第二端；
第五晶体管T5的栅极作为漏电流抑制模块140的控制端G2，第五晶体管T5的第一极作为漏电流抑制模块140的第一端，第五晶体管T5的第二极作为漏电流抑制模块140的第二端；
第六晶体管T6的栅极作为第一发光控制模块160的控制端G4，第六晶体管T6的第一极作为第一发光控制模块160的第一端，第六晶体管T6的第二极作为第一发光控制模块160的第二端；
第二电容C2的两个极板分别作为存储模块120的两端；
有机发光二极管D1的阳极和阴极分别作为发光模块130的第一端和第二端。
图7是本申请实施例提供的另一种像素电路的工作时序图，该工作时序图可对应图6所示的像素电路，参考图6和图7，图6所示像素电路的工作时序包括数据写入阶段和发光阶段。其中，第五晶体管T5可为氧化物晶体管，可以是IGZO晶体管。图6以第五晶体管T5为N型晶体管，其他晶体管为P型晶体管为例进行了示意性说明。
参考图6和图7，在数据写入阶段t1，第二扫描信号输入端Scan2输入低电平，第三晶体管T3导通；第一控制信号输入端Ctrl输入高电平，第五晶体管T5导通，第一发光控制信号输入端EM1输入高电平，第六晶体管T6截止，数据电压沿着导通的第三晶体管T3、第四晶体管T4和第五晶体管T5写入到第四晶体管T4的栅极，当第四晶体管T4的栅极电位达到VDD-|Vth|(其中，VDD为第一电压信号输入端Vdd输入的电压，Vth为第四晶体管T4的阈值电压)时，第四晶体管T4截止，完成对第四晶体管T4栅极电位的写入和阈值电压的补偿，使得显示不会受到第四晶体管阈值电压的影响，有利于提高显示均匀性，提高显示效果。
在发光阶段t2，第二扫描信号输入端Scan2输入高电平，第三晶体管T3截止；第一控制信号输入端Ctrl输入低电平，第五晶体管T5截止；第一发光控制信号输入端EM1输入低电平，第六晶体管T6导通，第四晶体管T4驱动有机发光二极管D1发光。其中，第五晶体管T5可为氧化物晶体管，例如可以是IGZO晶体管，因氧化物晶体管在截止状态具有较低的漏电流，进而可以保证第四晶体管T4的栅极电位可以保持稳定，进而使得对该像素电路的驱动频率可以降低，进而降低包含该像素电路的显示装置的功耗。并且，因氧化物晶体管在截止状态具有较低的漏电流，进而可以保证第四晶体管T4的栅极电位可以保持稳定，使得第二电容C2的电容值无需很大即可保持第四晶体管T4栅极的电位，使得第二电容C2的面积可以减小，有利于提高像素密度。
图8是本申请实施例提供的还一种像素电路的结构示意图，参考图8，在上述方案的基础上，可选的，第五晶体管T5和第六晶体管T6的沟道类型不同，第五晶体管T5的栅极与像素电路的第一发光控制信号输入端EM1电连接。
第五晶体管T5和第六晶体管T6在像素电路的多个工作阶段的导通关断状态不同，因此第五晶体管T5和第六晶体管T6的沟道类型不同可以使得第五晶体管T5和第六晶体管T6可以使用一条控制线来进行控制，进而有利于减少包括该像素电路的显示装置的布线，有利于实现显示装置的窄边框。可选的，因氧化物晶体管的工艺限制，第五晶体管T5为N型晶体管。
图9是本申请实施例提供的又一种像素电路的工作时序图，该工作时序图可对应图8所示的像素电路，参考图8和图9，图8所示像素电路的工作时序包括数据写入阶段和发光阶段。其中，第五晶体管T5可为氧化物晶体管，例如可以是IGZO晶体管。图8以第五晶体管T5为N型晶体管，其他晶体管为P型晶体管为例进行了示意性说明。
参考图8和图9，在数据写入阶段t1，第二扫描信号输入端Scan2输入低电平，第三晶体管T3导通，第一发光控制信号输入端EM1输入高电平，第五晶体管T5导通，第六晶体管T6截止，数据电压沿着导通的第三晶体管T3、第四晶体管T4和第五晶体管T5写入到第四晶体管T4的栅极，当第四晶体管T4的栅极电位达到VDD-|Vth|(其中，VDD为第一电压信号输入端Vdd输入的电压，Vth为第四晶体管T4的阈值电压)时，第四晶体管T4截止，完成对第四晶体管T4栅极电位的写入和阈值电压的补偿。
在发光阶段t2，第二扫描信号输入端Scan2输入高电平，第三晶体管T3截止，第一发光控制信号输入端EM1输入低电平，第五晶体管T5截止，第六晶体管T6导通，第四晶体管T4驱动有机发光二极管D1发光。其中，第五晶体管T5可为氧化物晶体管，例如可以是IGZO晶体管，因氧化物晶体管在截止状态具有较低的漏电流，进而可以保证第四晶体管T4的栅极电位可以保持稳定，进而使得对该像素电路的驱动频率可以降低，进而降低包含该像素电路的显示装置的功耗。并且，因氧化物晶体管在截止状态具有较低的漏电流，进而可以保证第四晶体管T4的栅极电位可以保持稳定，使得第二电容C2的电容值无需很大即可保持第四晶体管T4栅极的电位，使得第二电容C2的面积可以减小，有利于提高像素密度。
图10是本申请实施例提供的还一种像素电路的结构示意图，参考图10，在上述方案的基础上，可选的，该像素电路还包括初始化模块(也可称为初始化电路)170，初始化模块170包括控制端G5、第一端和第二端，初始化模块170的控制端G5与像素电路的第三扫描信号输入端Scan3电连接，初始化模块170的第一端与像素电路的初始化电压输入端Vref电连接，初始化模块170的第二端与发光模块130的第一端电连接。
参考图10，该像素电路工作时，其工作时序可包括初始化阶段、数据写入阶段和发光阶段。
其中，在初始化阶段，初始化模块170导通，第一发光控制模块160、数据写入模块150和漏电流抑制模块140关断，发光模块130第一端的电位被初始化为Vref；
在数据写入阶段，初始化模块170截止，数据写入模块150和漏电流抑制模块140导通，第一发光控制模块160截止，数据电压通过导通的数据写入模块150、驱动模块110和漏电流抑制模块140写入到驱动模块110控制端G1；
在发光阶段，初始化模块170、数据写入模块150和漏电流抑制模块140截止，第一发光控制模块160导通。因漏电流抑制模块140在截止状态具有较低的漏电流，进而可以保证驱动模块110控制端G1的电位可以保持稳定，进而使得对该像素电路的驱动频率降低，进而降低包含该像素电路的显示装置的功耗。
本实施例提供的像素电路，包括初始化模块，初始化模块可对发光模块第一端的电位和驱动模块控制端电位进行初始化，使得驱动模块控制端的电位和发光模块第一端的电位在初始化阶段被泄放掉，避免上一帧驱动时，驱动模块控制端和发光模块第一端残留电荷对本帧显示画面的影响，有利于提高显示效果。
图11是本申请实施例提供的还一种像素电路的结构示意图，参考图11，可选的，初始化模块170包括第七晶体管T7，第七晶体管T7的栅极作为初始化模块170的控制端G5，第七晶体管T7的第一极作为初始化模块170的第一端，第七晶体管T7的第二极作为初始化模块170的第二端。
图12是本申请实施例提供的再一种像素电路的工作时序图，该工作时序图可对应图11所示的像素电路，参考图11和图12，图11所示像素电路的工作时序包括初始化阶段t11、数据写入阶段t12和发光阶段t13。图11以第五晶体管T5为N型晶体管，其他晶体管为P型晶体管为例进行了示意性说明。
参考图11和图12，在初始化阶段t11，第二扫描信号输入端Scan2输入高电平，第三晶体管T3截止；第三扫描信号输入端Scan3输入低电平，第七晶体管T7导通；第一控制信号输入端Ctrl输入高电平，第五晶体管T5导通；第一发光控制信号输入端EM1输入高电平，第六晶体管T6截止；初始化电压输入端Vref输入的初始化电压通过导通的第七晶体管T7写入到有机发光二极管D1的阳极；以及通过导通的第七晶体管T7和第五晶体管T5写入到第四晶体管T4的栅极。
在数据写入阶段t12，第二扫描信号输入端Scan2输入低电平，第三晶体管T3导通，第三扫描信号输入端Scan3输入高电平，第七晶体管T7截止，第一控制信号输入端Ctrl输入高电平，第五晶体管T5导通，第一发光控制信号输入端EM1输入高电平，第六晶体管T6截止，数据电压沿着导通的第三晶体管T3、第四晶体管T4和第五晶体管T5写入到第四晶体管T4的栅极，并完成对第四晶体管T4栅极电位的写入和阈值电压的补偿。
在发光阶段t13，第二扫描信号输入端Scan2输入高电平，第三晶体管T3截止，第三扫描信号输入端Scan3输入高电平，第七晶体管T7截止，第一控制信号输入端Ctrl输入低电平，第五晶体管T5截止，第一发光控制信号输入端EM1输入低电平，第六晶体管T6导通，第四晶体管T4驱动有机发光二极管D1发光。其中，第五晶体管T5可为氧化物晶体管，例如可以是IGZO晶体管，因氧化物晶体管在截止状态具有较低的漏电流，进而可以保证第四晶体管T4的栅极电位可以保持稳定，进而使得包含该像素电路的显示装置中驱动芯片对该像素电路的驱动频率降低，降低包含该像素电路的显示装置的功耗。继续参考图11和图12，可选的，第五晶体管和第六晶体管的沟道类型不同，例如当第五晶体管T5为N型晶体管，第六晶体管T6为P型晶体管时，与第五晶体管T5栅极电连接的第一控制信号输入端Ctrl与和与第六晶体管T6栅极电连接的第一发光控制信号输入端EM1在像素电路的多个工作阶段的时序都相同，因此，此时像素电路可不设置第一控制信号输入端Ctrl，第五晶体管T5的栅极与第一发光控制信号输入端EM1连接即可，进而可以使得第五晶体管T5和第六晶体管T6可以使用一条控制线来进行控制，进而有利于减少包括该像素电路的显示装置的布线，有利于实现显示装置的窄边框。
本实施例提供的像素电路，包括第七晶体管，初始化电压输入端可通过第七晶体管对有机发光二级管的阳极电位和第四晶体管的栅极电位进行初始化，使得第四晶体管的栅极电位和有机发光二极管的阳极电位在初始化阶段被泄放掉，避免上一帧驱动时，第四晶体管的栅极和有机发光二极管的阳极残留电荷对本帧显示画面的影响，有利于提高显示效果。
图13是本申请实施例提供的还一种像素电路的结构示意图，参考图13，可选的，该像素电路还包括第二发光控制模块(也可称为第二发光控制电路)180，第二发光控制模块180的第一端与驱动模块110的第二端电连接，第二发光控制模块180的第二端与发光模块130的第一端电连接，第二发光控制模块180的控制端G6与像素电路的第二发光控制信号输入端EM2电连接。该像素电路工作时，其工作时序可包括初始化阶段、数据写入阶段和发光阶段。
其中，在初始化阶段，初始化模块170导通，第一发光控制模块160、第二发光控制模块180、数据写入模块150和漏电流抑制模块140关断，发光模块130第一端的电位被初始化为Vref；
在数据写入阶段，初始化模块170截止，数据电压写入模块和漏电流抑制模块140导通，第一发光控制模块160、第二控制发光模块180截止，数据电压通过导通的数据写入模块150、驱动模块110和漏电流抑制模块140写入到驱动模块110控制端G1；
在发光阶段，初始化模块170、数据写入模块150和漏电流抑制模块140截止，第一发光控制模块160和第二发光控制模块180导通。因漏电流抑制模块140在截止状态具有较低的漏电流，进而可以保证驱动模块110控制端G1的电位可以保持稳定，进而使得驱动芯片的驱动频率降低，降低包含该像素电路的显示装置的功耗。另外，因第一发光控制模块160和第二发光控制模块180的导通和关断状态始终相同，因此，第二发光控制模块180的控制端G6与第一发光控制模块160的控制端G4也可与同一发光控制信号输入端电连接，进而可以减少发光控制信号线的数量，有利于实现窄边框。
在一实施例中，在初始化阶段，也可控制第二发光控制模块180导通和漏电流抑制模块140导通，使得初始化电压输入端Vref输入的初始化电压通过导通的初始化模块170、第二发光控制模块180和漏电流抑制模块140写入到驱动模块110的控制端G1，使得驱动模块110控制端的电位被初始化，进而使得在数据写入阶段时，数据电压更容易写入。在初始化阶段，第一发光控制模块160和数据写入模块150仍保持关断。此种情况下，第一发光控制模块160的控制端和第二发光控制模块180的控制端与不同的发光控制信号输入端电连接。
图14是本申请实施例提供的还一种像素电路的结构示意图，参考图14，可选的，第二发光控制模块180包括第八晶体管T8，第八晶体管T8的第一极与第四晶体管T4的第二极电连接，第八晶体管T8的第二极与有机发光二极管D1的阳极电连接，第八晶体管T8的栅极与像素电路的第二发光控制信号输入端EM2电连接。
图15是本申请实施例提供的还一种像素电路的工作时序图，该工作时序图可对应图14所示的像素电路，参考图14和图15，图14所示像素电路的工作时序包括初始化阶段t11、数据写入阶段t12和发光阶段t13。图14以第五晶体管T5为N型晶体管，其他晶体管为P型晶体管为例进行了示意性说明。
参考图14和图15，在初始化阶段t11，第二扫描信号输入端Scan2输入高电平，第三晶体管T3截止；第三扫描信号输入端Scan3输入低电平，第七晶体管T7导通；第一发光控制信号输入端EM1输入高电平，第六晶体管T6截止；第一控制信号输入端Ctrl输入高电平，第五晶体管T5导通；第二发光控制信号输入端EM2输入低电平，第八晶体管T8导通，有机发光二极管D1的阳极和第四晶体管T4的栅极位被初始化为初始化电压输入端Vref的电位。
在数据写入阶段t12，第二扫描信号输入端Scan2输入低电平，第三晶体管T3导通；第三扫描信号输入端Scan3输入高电平，第七晶体管T7截止；第一控制信号输入端Ctrl输入高电平，第五晶体管T5导通；第一发光控制信号输入端EM1输入高电平，第六晶体管T6截止；第二发光控制信号输入端EM2输入高 电平，第八晶体管T8截止；数据电压沿着导通的第三晶体管T3、第四晶体管T4和第五晶体管T5写入到第四晶体管T4的栅极，并完成对第四晶体管T4的阈值电压的补偿。
在发光阶段t13，第二扫描信号输入端Scan2输入高电平，第三晶体管T3截止，第三扫描信号输入端Scan3输入高电平，第七晶体管T7截止；第一控制信号输入端Ctrl输入低电平，第五晶体管T5截止；第一发光控制信号输入端EM1输入低电平，第六晶体管T6导通，第二发光控制信号输入端EM2输入低电平，第八晶体管T8导通，第四晶体管T4驱动有机发光二极管D1发光。其中，第五晶体管T5可为氧化物晶体管，例如可以是IGZO晶体管，因氧化物晶体管在截止状态具有较低的漏电流，进而可以保证第四晶体管T4的栅极电位可以保持稳定，提高显示效果，并且可以包含该像素电路的显示装置的驱动芯片对该像素电路的驱动频率降低，降低包含该像素电路的显示装置的功耗。继续参考图14和图15，因第五晶体管T5的栅极输入的控制信号与第六晶体管T6栅极输入的控制信号在多个阶段都相同，因此第五晶体管T5的栅极和第六晶体管T6的栅极可与同一控制信号输入端电连接，例如第五晶体管T5的栅极也与第一发光控制信号输入端EM1电连接，进而可以减少像素电路中的第一控制信号输入端Ctrl，进而减少相应的控制信号线，有利于实现包含该像素电路的显示装置的窄边框。
图16是本申请实施例提供的还一种像素电路的结构示意图，参考图16，在上述方案的基础上，可选的，第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和第八晶体管T8均为双栅晶体管。
图15所示工作时序对图16所示像素电路同样适用。在一实施例中，因双栅晶体管的漏电流明显小于单栅晶体管的漏电流，因此，将像素电路中每个晶体管设置为双栅晶体管，可以减小像素电路中的漏电流，使得在发光阶段第四晶体管T4(驱动晶体管)的栅极电位可以得到更好地保持，提高显示效果，并且可以使得对像素电路的驱动频率降低，降低整个显示装置的功耗。
在一实施例中，本申请上述任意实施例中的晶体管都可为双栅晶体管，进而减小像素电路中的漏电流。
本申请实施例还提供了一种显示装置，图17是本申请实施例提供的一种显示装置的结构示意图，参考图17，包括本申请任意实施例提供的像素电路，显示装置200还包括扫描驱动电路210、数据驱动电路220和驱动芯片230，数据驱动电路220集成在驱动芯片230中，以及多条数据线(D1,D2，D3……)、多条扫描线(S1,S2，S3……)；扫描驱动电路210的端口与扫描线电连接，数据 驱动电路220的端口与数据线电连接；以显示装置包括图2所示像素电路为例，参考图2，像素电路包括数据电压输入端Vdata、第一扫描信号输入端Scan1，每个像素电路的数据电压输入端Vdata连接一条数据线，每个像素电路的第一扫描信号输入端Scan1连接一条扫描线，图17示意性地示出了一个像素对应的像素电路的数据电压输入端Vdata、第一扫描信号输入端Scan1。
本申请实施例提供的显示装置，包括本申请任意实施例提供的像素电路，通过设置与驱动模块控制端电连接的模块为漏电流抑制模块，可以使得驱动模块的控制端的电位不容易被泄放掉，使驱动模块控制端的电位可以得到较好地保持，提高显示效果；并且可以使得对像素电路的驱动频率降低，进而降低包含该像素电路的显示装置中驱动芯片的功耗，降低包括该像素电路的整个显示装置的功耗。并且，因漏电流抑制模块可以使得驱动模块的控制端的电位不容易被泄放，使得存储模块的面积可以减小，进而有利于提高像素密度。

Claims (14)

  1. 一种像素电路，包括：
    发光模块；
    驱动模块，所述驱动模块设置为根据所述驱动模块的控制端的电压驱动所述发光模块发光；
    存储模块，所述存储模块设置为存储所述驱动模块的控制端的电压；
    漏电流抑制模块，所述漏电流抑制模块与所述驱动模块的控制端电连接，设置为保持所述驱动模块的控制端的电位。
  2. 根据权利要求1所述的像素电路，其中，所述漏电流抑制模块为氧化物晶体管。
  3. 根据权利要求1所述的像素电路，其中，所述漏电流抑制模块包括控制端、第一端和第二端；所述漏电流抑制模块的控制端设置为输入控制信号以使所述漏电流抑制模块导通或关断；所述漏电流抑制模块还设置为向所述驱动模块的控制端写入数据电压；
    所述漏电流抑制模块的控制端与所述像素电路的第一扫描信号输入端电连接，所述漏电流抑制模块的第一端与所述像素电路的数据电压输入端电连接，所述漏电流抑制模块的第二端与所述驱动模块的控制端电连接；
    所述驱动模块的第一端与所述像素电路的第一电压信号输入端电连接，所述驱动模块的第二端与所述发光模块的第一端电连接，所述发光模块的第二端与所述像素电路的第二电压信号输入端电连接；
    所述存储模块的两端分别与所述驱动模块的控制端和所述驱动模块的第一端电连接。
  4. 根据权利要求3所述的像素电路，其中，所述漏电流抑制模块包括第一晶体管，所述驱动模块包括第二晶体管，所述存储模块包括第一电容，所述发光模块包括有机发光二极管；其中，所述第二晶体管为低温多晶硅晶体管；
    所述第一晶体管的栅极作为所述漏电流抑制模块的控制端，所述第一晶体管的第一极作为所述漏电流抑制模块的第一端，所述第一晶体管的第二极作为所述漏电流抑制模块的第二端；
    所述第二晶体管的栅极作为所述驱动模块的控制端，第二晶体管的第一极作为所述驱动模块的第一端，所述第二晶体管的第二极作为所述驱动模块的第二端；
    所述第一电容的两个极板分别作为所述存储模块的两端；
    所述有机发光二极管的阳极和阴极分别作为所述发光模块的第一端和第二端。
  5. 根据权利要求1所述的像素电路，还包括数据写入模块和第一发光控制模块；所述漏电流抑制模块包括控制端、第一端和第二端；所述漏电流抑制模块的控制端设置为输入控制信号以使所述漏电流抑制模块导通或关断；
    所述数据写入模块的控制端与所述像素电路的第二扫描信号输入端电连接，所述数据写入模块的第一端与所述像素电路的数据电压输入端电连接，所述数据写入模块的第二端与所述驱动模块的第一端电连接；
    所述第一发光控制模块的第一端与所述像素电路的第一电压信号输入端电连接，所述第一发光控制模块的第二端与所述驱动模块的第一端电连接，所述第一发光控制模块的控制端与所述像素电路的第一发光控制信号输入端电连接；
    所述驱动模块的控制端与所述漏电流抑制模块的第二端电连接，所述驱动模块的第二端与所述漏电流抑制模块的第一端电连接，以及还与所述发光模块的第一端电连接；
    所述发光模块的第二端与所述像素电路的第二电压信号输入端电连接。
  6. 根据权利要求5所述的像素电路，其中，所述数据写入模块包括第三晶体管，所述驱动模块包括第四晶体管，所述漏电流抑制模块包括第五晶体管，所述第一发光控制模块包括第六晶体管，所述存储模块包括第二电容，所述发光模块包括有机发光二极管；所述第三晶体管、所述第四晶体管和所述第六晶体管均为低温多晶硅晶体管；
    所述第三晶体管的栅极作为所述数据写入模块的控制端，所述第三晶体管的第一极作为所述数据写入模块的第一端，所述第三晶体管的第二极作为所述数据写入模块的第二端；
    所述第四晶体管的栅极作为所述驱动模块的控制端，所述第四晶体管的第一极作为所述驱动模块的第一端，所述第四晶体管的第二极作为所述驱动模块的第二端；
    所述第五晶体管的栅极作为所述漏电流抑制模块的控制端，所述第五晶体管的第一极作为所述漏电流抑制模块的第一端，所述第五晶体管的第二极作为所述漏电流抑制模块的第二端；
    所述第六晶体管的栅极作为所述第一发光控制模块的控制端，所述第六晶体管的第一极作为所述第一发光控制模块的第一端，所述第六晶体管的第二极作为所述第一发光控制模块的第二端；
    所述第二电容的两个极板分别作为所述存储模块的两端；
    所述有机发光二极管的阳极和阴极分别作为所述发光模块的第一端和第二端。
  7. 根据权利要求6所述的像素电路，还包括初始化模块，所述初始化模块包括控制端、第一端和第二端，所述初始化模块的控制端与所述像素电路的第三扫描信号输入端电连接，所述初始化模块的第一端与所述像素电路的初始化电压输入端电连接，所述初始化模块的第二端与所述发光模块的第一端电连接。
  8. 根据权利要求7所述的像素电路，其中，所述初始化模块包括第七晶体管，所述第七晶体管的栅极作为所述初始化模块的控制端，所述第七晶体管的第一极作为所述初始化模块的第一端，所述第七晶体管的第二极作为所述初始化模块的第二端。
  9. 根据权利要求6-8任一项所述的像素电路，其中，所述第五晶体管和所述第六晶体管的沟道类型不同，所述第五晶体管的栅极与所述像素电路的第一发光控制信号输入端电连接。
  10. 根据权利要求8所述的像素电路，还包括第二发光控制模块，所述第二发光控制模块的第一端与所述驱动模块的第二端电连接，所述第二发光控制模块的第二端与所述发光模块的第一端电连接，所述第二发光控制模块的控制端与所述像素电路的第二发光控制信号输入端电连接。
  11. 根据权利要求10所述的像素电路，所述第二发光控制模块包括第八晶体管，所述第八晶体管的第一极与所述第四晶体管的第二极电连接，所述第八晶体管的第二极与所述有机发光器件的阳极电连接，所述第八晶体管的栅极与所述像素电路的第二发光控制信号输入端电连接。
  12. 根据权利要求11所述的像素电路，其中，所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管和所述第八晶体管均为双栅晶体管。
  13. 根据权利要求6所述的像素电路，其中，所述第五晶体管为N型晶体管。
  14. 一种显示装置，包括权利要求1-13任一项所述的像素电路，还包括与所述像素电路电连接的驱动芯片。
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