WO2024060430A1 - 像素电路及其驱动方法、显示面板 - Google Patents

像素电路及其驱动方法、显示面板 Download PDF

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Publication number
WO2024060430A1
WO2024060430A1 PCT/CN2022/139215 CN2022139215W WO2024060430A1 WO 2024060430 A1 WO2024060430 A1 WO 2024060430A1 CN 2022139215 W CN2022139215 W CN 2022139215W WO 2024060430 A1 WO2024060430 A1 WO 2024060430A1
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Prior art keywords
module
control
reset
transistor
driving
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PCT/CN2022/139215
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English (en)
French (fr)
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郭恩卿
李俊峰
盖翠丽
邢汝博
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昆山国显光电有限公司
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Publication of WO2024060430A1 publication Critical patent/WO2024060430A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present application relates to the field of display technology, for example, to a pixel circuit and its driving method, and a display panel.
  • the pixel circuit in the display panel plays a very important role in driving the light-emitting device to emit light stably.
  • data writing and threshold voltage compensation are the same process, which makes the compensation time of the driving transistor insufficient. For example, at a high refresh frequency and the line time is short, the compensation time is insufficient.
  • the compensation effect on the threshold voltage of the driving transistor is poor; and the pixel circuit in the related art has different threshold voltage compensation degrees under multiple gray levels. Therefore, display panels in the related art have problems such as poor display brightness uniformity and limited resolution and refresh frequency.
  • This application provides a pixel circuit, a driving method thereof, and a display panel to improve the display brightness uniformity of the display panel while taking into account the realization of high resolution and high refresh frequency of the display panel.
  • a pixel circuit including:
  • a storage module electrically connected to the control end and the first end of the driving module respectively, and configured to store the potential of the control end of the driving module and the first end of the driving module;
  • the first end of the coupling module is electrically connected to the first end of the driving module, the coupling module is configured to couple the potential change of the second end of the coupling module to the first end of the coupling module ;
  • the first reset module is electrically connected to the second end of the coupling module, and is configured to transmit the first reset signal to the second end of the coupling module before the data writing stage, and to the second end of the coupling module. end to reset;
  • a second reset module electrically connected to the control end of the driving module, and configured to transmit a second reset signal to the control end of the driving module during the threshold compensation phase and the data writing phase;
  • a discharge module electrically connected to the second end of the drive module, is configured to be turned on during the threshold compensation stage, so that the first end of the drive module discharges through the drive module and the discharge module, so that the storage
  • the module stores the threshold voltage of the driving module
  • a data writing module is electrically connected to the second end of the coupling module and connected to the data voltage
  • the lighting control module, the driving module and the lighting device are connected between the first power supply and the second power supply.
  • the threshold compensation stage and the data writing stage are set to be separated, so that the threshold compensation time can be lengthened without being limited by the data writing line time, so as to achieve better compensation effects.
  • the threshold compensation process of the driving module is only controlled by the second reset signal and the first power signal, and has nothing to do with the size of the data voltage.
  • the existence of time overlap in the threshold compensation stages of different rows of pixel circuits will not affect the data writing effect. Therefore, the increase in threshold compensation time will not affect the refresh frequency of the display panel.
  • this embodiment realizes data writing by providing a potential jump to the second end of the coupling module. Then the value of the data voltage at the end of the data writing phase determines the data voltage finally written into the pixel circuit.
  • this embodiment also allows partial overlap in the data writing time of different rows, which is conducive to the realization of high refresh frequency and at the same time Provide conditions for achieving high resolution of display panels.
  • the threshold compensation process of the driving module has nothing to do with the size of the data voltage, so that the bias of the driving module is not affected by gray scale changes. Regardless of the gray scale level and the data voltage size, the threshold compensation effect of the driving module is basically the same. Reduce the compensation difference between different gray levels and improve display uniformity. Therefore, compared with related technologies, embodiments of the present application can improve the display brightness uniformity of the display panel while taking into account the realization of high resolution and high refresh frequency of the display panel.
  • FIG1 is a schematic structural diagram of a pixel circuit in the related art
  • Figure 2 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • Figure 3 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 4 is a schematic diagram of the driving timing of a pixel circuit provided by an embodiment of the present application.
  • Figure 5 is a schematic diagram of the driving timing of another pixel circuit provided by an embodiment of the present application.
  • Figure 6 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 7 is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present application.
  • Figure 8 is a schematic diagram of the driving timing of another pixel circuit provided by an embodiment of the present application.
  • Figure 9 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 10 is a schematic diagram of the driving timing of another pixel circuit provided by an embodiment of the present application.
  • Figure 11 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 12 is a schematic diagram of the driving timing of another pixel circuit provided by an embodiment of the present application.
  • FIG. 13 is a schematic flowchart of a driving method for a pixel circuit provided by an embodiment of the present application.
  • Figure 1 shows a 7T1C architecture pixel circuit in related technology.
  • the pixel circuit includes: transistor M01, transistor M02, transistor M03, transistor M04, transistor M05, transistor M06, transistor M07 and a storage capacitor.
  • Cst0 the plurality of transistors are P-type transistors, manufactured using a low temperature polysilicon (Low Temperature Poly-Silicon, LTPS) process.
  • the signals that need to be connected to the pixel circuit include: the first power signal VDD, the second power signal VSS, the reset signal Vref0, the data signal Data, the scanning signal Sn01, the scanning signal Sn02, the scanning signal Sn03 and the light emission control signal EM0.
  • the driving process of the pixel circuit includes: a reset stage, a data writing and compensation stage, and a light-emitting stage. The following mainly describes the data writing and compensation stages of the pixel circuit.
  • the transistor M01 is a driving transistor, and the gate potential of the transistor M01 is saved by the storage capacitor Cst0; the transistor M02 is used as a data writing transistor, and the transistor M03 is used as a threshold compensation transistor.
  • the gates of both are connected to the scanning signal Sn02.
  • the scanning signal Sn02 is at a low level, both the transistor M02 and the transistor M03 are turned on, and the data signal Data passes through the transistor M02, the first and second poles of the transistor M01, and the transistor M03 to the gate of the transistor M01. pole transmission and charging the storage capacitor Cst0 at the same time.
  • the goal of this process is to use the storage capacitor Cst0 to correctly store the information including the data signal Data and the threshold voltage Vth of the transistor M01. Then in this process, you need to wait at least for the gate of the transistor M01 to be charged to Data+Vth and turn off. This limits the speed of data writing in the pixel circuit.
  • the row time the driver chip provides the data signal required by a row of pixel circuits
  • the holding time is small, the gate potential of the transistor M01 cannot reach Data+Vth, and the data writing and compensation phase will end early, which will make the compensation effect poor.
  • the potential of the data signal Data is different under different gray scales, which will lead to differences in compensation of the transistor M01 under different gray scales.
  • the threshold voltage compensation effect in the related art pixel circuit is affected by both the data writing time and the data potential size (gray scale size) of the data signal. Insufficient compensation time will make the compensation effect poor. From another perspective, in order to ensure the threshold compensation effect, the data writing time needs to be set longer, which limits the refresh frequency of the display panel; when the refresh frequency is limited, even if the layout arrangement and preparation technology of the pixel circuit are It can meet the requirements of high resolution, but because the driving process does not meet the requirements, the resolution will also be limited.
  • FIG. 2 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • the pixel circuit includes: a driving module 10 , a storage module 20 , a coupling module 30 , a first reset module 40 , a second reset module 50 , a discharge module 60 , a data writing module 70 and a lighting control module 80 .
  • the driving module 10 is configured to generate a driving current according to the voltage of the control terminal N1 and the first terminal N2 of the driving module 10 .
  • the storage module 20 is electrically connected to the control terminal N1 and the first terminal N2 of the driving module 10 respectively, and is configured to store the potentials of the control terminal N1 and the first terminal N2 of the driving module 10 .
  • the first end of the coupling module 30 is electrically connected to the first end N2 of the driving module 10 , and the coupling module 30 is configured to couple the potential change of the second end N3 of the coupling module 30 to the first end of the coupling module 30 .
  • the first reset module 40 is electrically connected to the second terminal N3 of the coupling module 30 .
  • the first reset module 40 is configured to transmit the first reset signal Vini to the second terminal N3 of the coupling module 30 to control the second terminal N3 of the coupling module 30 .
  • N3 is reset.
  • the second reset module 50 is electrically connected to the control terminal N1 of the driving module 10 , and the second reset module 50 is configured to transmit the second reset signal Vref to the control terminal N1 of the driving module 10 .
  • the discharge module 60 is electrically connected to the second end N4 of the drive module 10, and the discharge module 60 is configured to conduct signal transmission between the drive module 10 and the second reset signal line (ie, the signal line used to transmit the second reset signal Vref).
  • the data writing module 70 is electrically connected to the second terminal N3 of the coupling module 30 , and the data writing module 70 is configured to write the data voltage Vdata into the second terminal N3 of the coupling module 30 .
  • the light-emitting control module 80 is connected to the driving module 10 and the light-emitting device L between the first power supply and the second power supply. The light-emitting control module 80 is configured to control the driving module 10 to turn on the first power supply and the second power supply.
  • the driving module 10 includes a driving transistor, and the threshold voltage of the driving transistor is the threshold voltage of the driving module 10 .
  • the first pole of the light-emitting device L is its anode, and the second pole is its cathode.
  • the first power supply is used to generate the first power supply signal VDD
  • the second power supply is used to generate the second power supply signal VSS.
  • the first power signal VDD, the second power signal VSS, the first reset signal Vini and the second reset signal Vref are all DC voltage signals, which can be provided by a power chip or a driver chip in the display panel.
  • the first power supply signal VDD may be a positive voltage signal
  • the second power supply signal VSS may be a negative voltage signal.
  • the driving process of the pixel circuit includes: a reset phase, a threshold compensation phase, a data writing phase and a light emitting phase.
  • the driving process of the pixel circuit includes:
  • the first reset module 40 transmits the first reset signal Vini to the second terminal N3 of the coupling module 30 to reset the second terminal N3 of the coupling module 30;
  • the second reset module 50 transmits the second reset signal Vref to The control terminal N1 of the driving module 10 resets the control terminal N1 of the driving module 10;
  • the discharge module 60 transmits the second reset signal Vref to the second terminal N4 of the driving module 10 to reset the second terminal N4 of the driving module 10. ;
  • the light-emitting control module 80 transmits the first power signal VDD to the first terminal N2 of the driving module 10, and continues to transmit the second reset signal Vref transmitted to the second terminal N4 of the driving module 10 to the first pole of the light-emitting device L. , to reset the first pole of the light-emitting device L.
  • the first reset module 40 transmits the first reset signal Vini to the second terminal N3 of the coupling module 30, keeping the potential of the second terminal N3 of the coupling module 30 unchanged;
  • the second reset module 50 transmits the second reset signal Vref is transmitted to the control terminal N1 of the drive module 10, keeping the potential of the control terminal N1 of the drive module 10 unchanged;
  • the discharge module 60 is turned on, causing the first terminal N2 of the drive module 10 to discharge through the drive module 10 and the discharge module 60 until
  • the potential difference between the control terminal N1 of the driving module 10 and the first terminal N2 of the driving module 10 is equal to the threshold voltage Vth1 of the driving module 10, that is, when the potential of the first terminal N2 of the driving module 10 is equal to Vref-Vth1, the driving module 10 is turned off;
  • the storage module 20 stores the threshold voltage Vth1 of the driving module 10 .
  • the potential of the control terminal N1 of the driving module 10 remains unchanged at the value of the second reset signal Vref, and the threshold compensation process is realized through the discharge of the first terminal N2 of the driving module 10 .
  • the degree of threshold compensation is only controlled by the potential of the first terminal N2 of the driving module 10 at the initial moment of this stage (i.e., the first power supply signal VDD) and the second reset signal Vref, and has nothing to do with the data voltage Vdata, so that under multiple gray levels
  • the threshold compensation effect of the driving module 10 can be unified, the display uniformity can be improved, and the situation where the threshold voltage Vth1 is positive can be compensated.
  • the second reset module 50 transmits the second reset signal Vref to the control terminal N1 of the driving module 10 to keep the potential of the control terminal N1 of the driving module 10 unchanged;
  • the data writing module 70 writes the data voltage Vdata The second end N3 of the coupling module 30;
  • the coupling module 30 couples the potential change of the second end N3 of the coupling module 30 to the first end of the coupling module 30 (that is, the first end N2 of the driving module 10), which is equivalent to carrying the
  • the potential of the data voltage Vdata information (for example, the difference information between the data voltage Vdata and the first reset signal Vini) is coupled to the first terminal N2 of the driving module 10 .
  • the memory module 20 Since the memory module 20 has stored the threshold voltage Vth1 of the driving module 10 in the previous stage, combined with the potential jump of the first terminal N2 of the driving module 10 in this stage, the potential difference between the two ends of the memory module 20 in this stage not only carries The information of the threshold voltage Vth1 also carries the information of the data voltage Vdata.
  • the light-emitting control module 80 is turned on, so that the signal transmission path from the first power supply to the driving module 10 to the light-emitting device L is turned on.
  • the driving module 10 generates a driving current according to the voltage of its control terminal N1 and the first terminal N2, and drives The current drives the light-emitting device L to emit light.
  • the driving current generated by the driving module 10 is a function of Vgs-Vth1, where Vgs is the potential difference between the control terminal N1 and the first terminal N2 of the driving module 10 , that is, the potential difference between the two ends of the memory module 20 . Since Vgs carries information about the threshold voltage Vth1, the influence of the threshold voltage Vth1 on the driving current can be eliminated after the above subtraction operation, thereby achieving a threshold compensation effect.
  • the threshold compensation stage and the data writing stage are set to be separated, so that the threshold compensation time can be lengthened without being limited by the data writing line time, so as to achieve better compensation effects.
  • the threshold compensation process of the driving module 10 is only controlled by the second reset signal Vref and the first power signal VDD, and has nothing to do with the size of the data voltage Vdata.
  • the existence of time overlap in the threshold compensation stages of different rows of pixel circuits will not affect the data. Writing effect, so the increase in threshold compensation time will not affect the refresh frequency of the display panel.
  • this embodiment realizes data writing by providing a potential jump to the second terminal N3 of the coupling module 30.
  • the value of the data voltage Vdata at the end of the data writing phase determines the data voltage finally written into the pixel circuit.
  • Different rows of pixel circuits have different end times of the data writing phase, which ensures the correct writing of data voltages in multiple rows. That is, this embodiment also allows partial overlap of data writing times in different rows, which is conducive to the realization of high refresh frequencies. , and at the same time provide conditions for the realization of high resolution of the display panel.
  • the threshold compensation process of the driving module 10 has nothing to do with the size of the data voltage Vdata, so that the bias of the driving module 10 is not affected by gray scale changes.
  • the threshold compensation effect of the driving module 10 are basically the same, which can reduce the compensation difference between different gray levels and improve the display uniformity. Therefore, compared with related technologies, embodiments of the present application can improve the display brightness uniformity of the display panel while taking into account the realization of high resolution and high refresh frequency of the display panel.
  • the first reset module 40, the second reset module 50, the discharge module 60, the data writing module 70 and the light emitting control module 80 all perform module operation according to the respective accessed control signals. On-off control.
  • FIG. 3 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of the driving timing of a pixel circuit provided by an embodiment of the present application.
  • the control end of the first reset module 40 is connected to the first control signal S1
  • the first control signal S1 is connected to the first reset module 40.
  • a reset module 40 is configured to respond to the first control signal S1, be turned on during the reset phase t1 and the threshold compensation phase t2, and transmit the first reset signal Vini to the second terminal N3 of the coupling module 30.
  • the second reset module 50 includes: a first reset unit 51; the first reset unit 51 is electrically connected to the control terminal N1 of the drive module 10 and receives the third control signal S3; the first reset unit 51 is configured to respond to the third control signal S3, during the reset phase t1, the threshold compensation phase t2 and the data writing phase t3, it is turned on, and the second reset signal Vref is transmitted to the control terminal N1 of the driving module 10.
  • the control terminal of the discharge module 60 is connected to the first control signal S1, and the discharge module 60 is configured to respond to the first control signal S1, be turned on during the reset phase t1, and transmit the second reset signal Vref to the second terminal N4 of the drive module 10, And it is turned on during the threshold compensation stage t2, so that the first terminal N2 of the driving module 10 is discharged through the driving module 10 and the discharging module 60.
  • the control terminal of the data writing module 70 is connected to the second control signal S2.
  • the data writing module 70 is configured to respond to the second control signal S2, conducts during the data writing phase t3, and writes the data voltage Vdata into the coupling module 30. Two terminals N3.
  • the control end of the light-emitting control module 80 is connected to the light-emitting control signal EM.
  • the light-emitting control module 80 is configured to respond to the light-emitting control signal EM and be turned on during the reset phase t1 to realize the control of the first terminal N2 of the driving module 10 and the light-emitting device L.
  • the reset of one pole and the conduction during the light-emitting phase t4 provide a transmission path for the driving current to the light-emitting device L, so that the driving current drives the light-emitting device L to emit light.
  • the first control signal S1, the second control signal S2, the third control signal S3 and the light emission control signal EM are all scanning signals with alternating positive and negative potentials, and can be provided by a scan driving circuit located at the frame of the display panel.
  • the first control signal S1, the second control signal S2, the third control signal S3 and the light emission control signal EM are each provided by different sets of scanning circuits.
  • the low-level pulse of the first control signal S1 and the low-level pulse of the third control signal S3 overlap during the reset phase t1 and the threshold compensation phase t2, and the low-level pulse of the second control signal S2 overlaps with the low-level pulse of the third control signal S2.
  • the low-level pulses of the signal S3 overlap during the data writing phase t3, the low-level pulses of the second control signal S2 do not overlap with the low-level pulses of the first control signal S1, and the high-level pulse time of the light-emitting control signal EM Covers the threshold compensation stage t2 and the data writing stage t3.
  • the pulse width of the third control signal S3 may be slightly shorter than the pulse width of the third control signal S3 in FIG. 4 , as long as it is ensured that the low potential pulse of the third control signal S3 is in the reset phase. It is sufficient that t1 still overlaps with the low-level pulse of the first control signal S1.
  • the pulse width of the third control signal S3 is the same as the pulse width of the first control signal S1.
  • the first control signal S1 and the third control signal S3 can be provided by the same group of scanning circuits connected in cascade to reduce the cost.
  • the number of scan circuit groups set in the drive pixel circuit simplifies the structure of the scan drive circuit, which is beneficial to the realization of narrow borders of the display panel.
  • the scanning circuit used to provide the first control signal S1 can be the previous stage of the scanning circuit used to output the third control signal S3 (the previous stage or previous stages can be ) scan the circuit.
  • FIG. 6 is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present application.
  • the driving module 10 includes: a driving transistor DTFT; the control electrode of the driving transistor DTFT serves as the control terminal N1 of the driving module 10, and the first pole serves as the first terminal N2 of the driving module 10. The second pole serves as the second terminal N4 of the driving module 10 .
  • the driving module 10 is composed of a transistor, so that the structure of the pixel circuit is simple and easy to implement.
  • the storage module 20 includes a first capacitor Cst1; a first end of the first capacitor Cst1 is electrically connected to the control end N1 of the driving module 10, and a second end of the first capacitor Cst1 is electrically connected to the first end N2 of the driving module 10.
  • the storage module 20 is configured to be composed of one capacitor, so that the structure of the pixel circuit is simple and easy to implement.
  • the coupling module 30 includes a second capacitor Cst2; the first terminal of the second capacitor Cst2 serves as the first terminal of the coupling module 30 and is electrically connected to the second terminal of the first capacitor Cst1. Connection: The second end of the second capacitor Cst2 serves as the second end N3 of the coupling module 30 and is electrically connected to the first reset module 40 and the data writing module 70 .
  • the coupling module 30 is composed of a capacitor, so that the structure of the pixel circuit is simple and easy to implement.
  • the first reset module 40 includes: a fourth transistor T4; the control electrode of the fourth transistor T4 is connected to the first control signal S1, and the first electrode is connected to the first reset signal. Vini, the second pole is electrically connected to the second terminal N3 of the coupling module 30 .
  • the first reset module 40 is composed of a transistor, which makes the structure of the pixel circuit simple and easy to implement.
  • the first reset unit 51 when the second reset module includes the first reset unit 51, the first reset unit 51 includes: a first transistor T1; the control electrode of the first transistor T1 is connected to the third The first pole of the control signal S3 is connected to the second reset signal Vref, and the second pole is electrically connected to the control terminal N1 of the driving module 10 .
  • the first reset unit 51 is composed of a transistor, which makes the structure of the pixel circuit simple and easy to implement.
  • the discharge module 60 includes: a fifth transistor T5; the control electrode of the fifth transistor T5 is connected to the first control signal S1, the first electrode is connected to the second reset signal Vref, and the second electrode is electrically connected to the second terminal N4 of the driving module 10.
  • the discharge module 60 is configured to be composed of one transistor, so that the structure of the pixel circuit is simple and easy to implement.
  • the data writing module 70 includes: a sixth transistor T6; the control electrode of the sixth transistor T6 is connected to the second control signal S2, the first electrode is connected to the data voltage Vdata, and the second electrode is electrically connected to the second end N3 of the coupling module 30.
  • the data writing module 70 is configured to be composed of one transistor, so that the structure of the pixel circuit is simple and easy to implement.
  • the lighting control module 80 includes: a seventh transistor T7 and an eighth transistor T8; the control electrode of the seventh transistor T7 and the control electrode of the eighth transistor T8 are both connected to the lighting control. signal EM; the first pole of the seventh transistor T7 is connected to the first power supply, and the second pole is electrically connected to the first pole of the driving transistor DTFT; the first pole of the eighth transistor T8 is electrically connected to the second pole of the driving transistor DTFT, The second electrode is electrically connected to the first electrode of the light emitting device L.
  • the light-emitting control module 80 is composed of two transistors, which makes the structure of the pixel circuit simple and easy to implement.
  • embodiments of the present application provide a 7T2C pixel circuit architecture.
  • the plurality of transistors in the pixel circuit can all be P-type transistors and are manufactured using an LTPS process to reduce the manufacturing cost of the display panel.
  • the driving process of the pixel circuit will be described in detail below with reference to Figures 4 and 6.
  • the driving process of the pixel circuit includes:
  • the first control signal S1, the third control signal S3 and the light-emitting control signal EM are all at low potential, and the second control signal S2 is at a high potential.
  • the first transistor T1, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7 and the eighth transistor T8 are all turned on.
  • the first reset signal Vini is transmitted to the second terminal of the second capacitor Cst2 (ie, the second terminal N3 of the coupling module 30) through the fourth transistor T4.
  • the second reset signal Vref is transmitted to the control electrode of the driving transistor DTFT (ie, the control terminal N1 of the driving module 10) through the first transistor T1.
  • the second reset signal Vref is transmitted to the second pole of the driving transistor DTFT (ie, the second terminal N4 of the driving module 10) through the fifth transistor T5, and continues to be transmitted to the first pole of the light-emitting device L through the eighth transistor T8.
  • the first power signal VDD is transmitted to the first pole of the driving transistor DTFT (ie, the first terminal N2 of the driving module 10) through the seventh transistor T7.
  • both the first capacitor Cst1 and the second capacitor Cst2 are discharged and reset, and the first pole of the light-emitting device L is also reset.
  • the first control signal S1 and the third control signal S3 are both at low potential, and the second control signal S2 and the light emission control signal EM are both at a high potential.
  • the seventh transistor T7 and the eighth transistor T8 are turned off, and the first transistor T1, the fourth transistor T4 and the fifth transistor T5 remain on.
  • the first reset signal Vini is transmitted to the second terminal N3 of the coupling module 30 through the fourth transistor T4 to keep the potential of the second terminal N3 of the coupling module 30 stable.
  • the second reset signal Vref is transmitted to the control terminal N1 of the driving module 10 through the first transistor T1 to keep the potential of the control terminal N1 of the driving module 10 stable.
  • the first terminal N2 of the driving module 10 is discharged through the driving transistor DTFT and the fifth transistor T5.
  • the driving transistor DTFT turns off. Break.
  • the voltage drop of the threshold voltage Vth1 of the driving transistor DTFT is stored in the first capacitor Cst1.
  • the second control signal S2 and the third control signal S3 are both at low potential, and the first control signal S1 and the light-emitting control signal EM are both at a high potential.
  • the fourth transistor T4 and the fifth transistor T5 are turned off, the sixth transistor T6 is turned on, and the first transistor T1 remains turned on.
  • the second reset signal Vref is transmitted to the control terminal N1 of the driving module 10 through the first transistor T1 to keep the potential of the control terminal N1 of the driving module 10 stable.
  • the data voltage Vdata is written into the second terminal N3 of the coupling module 30 through the sixth transistor T6, so that the potential of the second terminal N3 of the coupling module 30 jumps from the first reset signal Vini to the data voltage Vdata.
  • the third The second capacitor Cst2 transmits the potential change at its second end to its first end, so that the potential at the first end N2 of the driving module 10 jumps to: Vref-Vth1+(Vdata-Vini)*(Cst2)/(Cst1+Cst2+ Cgs), where Cgs is the capacitance between the control electrode and the first electrode of the driving transistor DTFT. Then, the voltage difference across the first capacitor Cst1 changes to Vth1-(Vdata-Vini)*(Cst2)/(Cst1+Cst2+Cgs).
  • the light-emitting control signal EM is at a low potential, and the first control signal S1, the second control signal S2, and the third control signal S3 are all at a high potential.
  • the first transistor T1 and the sixth transistor T6 are turned off, the seventh transistor T7 and the eighth transistor T8 are turned on, and the driving transistor DTFT generates a driving current to light the light-emitting device L.
  • the driving current is a function of Vgs-Vth1, where Vgs is equal to the voltage difference across the first capacitor Cst1.
  • Vgs is equal to the voltage difference across the first capacitor Cst1.
  • the driving current is actually a function of Vdata-Vini, that is, the size of the driving current and the threshold voltage of the driving transistor DTFT.
  • Vth1 has nothing to do, that is, threshold compensation is achieved.
  • the embodiments of the present application provide a 7T2C pixel circuit architecture, which separates the threshold compensation process and the data writing process, and combines the advantages of the LTPS transistor with high mobility, strong driving capability, and mature technology, which is beneficial to Improve the brightness uniformity of the display panel while taking into account the realization of high-frequency refresh and high resolution.
  • the plurality of transistors in the pixel are all composed of P-type transistors, but this is not a limitation of the present application.
  • some or all of the transistors can be replaced with N-type transistors according to requirements, and the high and low potentials of the control signals connected to the transistors can be adjusted accordingly. Several of the adjustment methods are described below.
  • FIG. 7 is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present application.
  • the first transistor T1 can be replaced with an N-type transistor, such as an N-type indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO) transistor.
  • an N-type transistor such as an N-type indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO) transistor.
  • the leakage current of the control electrode of the driving transistor DTFT can be reduced, so that the potential of the control electrode of the driving transistor DTFT can be maintained for a long time, so that the pixel circuit supports the low refresh function, which is beneficial to the display Implementation of panel wideband driver.
  • the driving timing of the pixel circuit shown in Figure 7 can be seen in Figure 8. Comparing Figure 8 and Figure 4, it can be seen that after the first transistor T1 is replaced with an N-type transistor, the pulse of the third control signal S3 is inverted.
  • FIG. 9 is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present application.
  • the fourth transistor T4 and the fifth transistor T5 can also be replaced with N-type transistors.
  • the driving timing of the pixel circuit shown in Figure 9 can be seen in Figure 10. Comparing Figure 10 and Figure 5, it can be seen that after the first transistor T1, the fourth transistor T4 and the fifth transistor T5 are all replaced with N-type transistors, the first control signal S1 If the pulses of the third control signal S3 are inverted, the first control signal S1 and the third control signal S3 can still be provided by the same group of scanning circuits connected in cascade, which is beneficial to the realization of a narrow frame of the display panel.
  • the second reset module may also be composed of a second reset unit and a data writing auxiliary unit, which will be described in detail below.
  • the second reset module 50 includes: a second reset unit 52 and a data writing auxiliary unit 53.
  • the second reset unit 52 is electrically connected to the control terminal N1 of the driving module 10, and is configured to respond to the first control signal S1, and is turned on in the reset phase and the threshold compensation phase, and transmits the second reset signal Vref to the control terminal N1 of the driving module 10.
  • the data writing auxiliary unit 53 is electrically connected to the control terminal N1 of the driving module 10, and is configured to respond to the second control signal S2, and is turned on in the data writing phase, and transmits the second reset signal Vref to the control terminal N1 of the driving module 10.
  • the pixel circuit structure and driving timing are set so that the threshold compensation phase t2 and the data writing phase t3 are performed one after another without interfering with each other; for different rows of pixel circuits, it is used to provide control of the data writing phase.
  • the scanning circuit of the second control signal S2 and the scanning circuit of the first control signal S1 used to provide the control threshold compensation stage are set up separately. There is no cascade or other associated control relationship between the two types of scanning circuits, and the signal generation process does not affect each other.
  • the threshold compensation stage t2 and the data writing stage t3 of different rows of pixel circuits will not be restricted by each other due to the correlation of the control signals, which is conducive to simplifying the control logic of the display panel and achieving a high refresh frequency for the display panel. provide conditions.
  • the second reset unit 52 includes a second transistor T2; the control electrode of the second transistor T2 is connected to the first control signal S1, and the first electrode is connected to the second The second pole of the reset signal Vref is electrically connected to the control terminal N1 of the driving module 10 .
  • the data writing auxiliary unit 53 includes: a third transistor T3; the control electrode of the third transistor T3 is connected to the second control signal S2, the first electrode is connected to the second reset signal Vref, and the second electrode is connected to the control terminal N1 of the driving module 10 Electrical connection.
  • the second reset unit 52 and the data writing auxiliary unit 53 are both composed of one transistor, so that the structure of the pixel circuit is simple and easy to implement.
  • Figure 11 provides a pixel circuit with an 8T2C architecture, and exemplarily shows a structure in which multiple transistors are P-type transistors, but this is not intended to limit the application.
  • some Or replace all transistors with N-type transistors for example, in order to reduce the leakage of the control electrode of the driving transistor DTFT, the second transistor T2 and the third transistor T3 are replaced with N-type transistors; on this basis, in order not to increase the number of control signals, the fourth transistor T4 and the fifth transistor can be replaced.
  • T5 and the sixth transistor T6 are also replaced with N-type transistors.
  • the holding duration of the threshold compensation phase t2 can be set to more than one line time, or even hundreds of line times, to extend the threshold compensation time and ensure the threshold compensation effect.
  • the first power signal VDD can be multiplexed as the first reset signal Vini to reduce the number of signal lines in the display panel, which is beneficial to simplifying the structure of the display panel and facilitating the wiring of the display panel. design.
  • the first electrodes of the plurality of transistors may be called sources or drains, and correspondingly, the second electrodes of the plurality of transistors may be called drains or sources, because in The structure of the transistors in the display panel is symmetrical, and the sources and drains of the multiple transistors are not distinguished here.
  • Embodiments of the present application also provide a display panel, which includes the pixel circuit provided by any embodiment of the present application and has corresponding beneficial effects, which will not be described again.
  • FIG13 is a flow chart of a driving method for a pixel circuit provided in an embodiment of the present application.
  • the driving method for the pixel circuit includes:
  • control the first reset module to transmit the first reset signal to the second end of the coupling module; control the second reset module to transmit the second reset signal to the control end of the drive module; control the discharge module to transmit the second reset signal transmitted to the second end of the driving module; controlling the light-emitting control module to transmit the first power signal provided by the first power supply to the first end of the driving module, and transmit the second reset signal to the first pole of the light-emitting device.
  • the first end of the driving module is discharged through the driving module and the discharging module until the potential difference between the control end of the driving module and the first end of the driving module is equal to the threshold voltage of the driving module, and the driving module is turned off; the storage module stores the threshold voltage.
  • the second reset module is controlled to transmit the second reset signal to the control end of the driving module, and the data writing module is controlled to write the data voltage to the second end of the coupling module; the coupling module transfers the second reset signal to the second end of the coupling module.
  • the potential change at the terminal is coupled to the first terminal of the coupling module.
  • the light-emitting control module is controlled to be turned on, so that the driving module generates a driving current according to the voltage of the control terminal and the first terminal of the driving module, and transmits the driving current to the light-emitting device.
  • the driving method of the pixel circuit provided by the embodiment of the present application can take into account the uniformity of display brightness of the display panel and the realization of high resolution and high refresh frequency of the display panel by setting the threshold compensation stage and the data writing stage separately.

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Abstract

一种像素电路及其驱动方法、显示面板。像素电路包括：驱动模块（10）、存储模块（20）、耦合模块（30）、第一复位模块（40）、第二复位模块（50）、放电模块（60）、数据写入模块（70）和发光控制模块（80）。存储模块（20）分别与驱动模块（10）的控制端（N1）和第一端（N2）电连接；耦合模块的第一端（30）与驱动模块（10）的第一端（N2）电连接；第一复位模块（40）与耦合模块（30）的第二端（N3）电连接；第二复位模块（50）与驱动模块（10）的控制端（N1）电连接；放电模块（60）与驱动模块（10）的第二端（N4）电连接；数据写入模块（70）与耦合模块（30）的第二端（N3）电连接，并接入数据电压（Vdata）；发光控制模块（80）与驱动模块（10）以及发光器件（L）连接于第一电源和第二电源之间。该像素电路可以兼顾显示面板的亮度均一性、高分辨率及高刷新频率。

Description

像素电路及其驱动方法、显示面板
本申请要求在2022年9月23日提交中国专利局、申请号为202211161648.8的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，例如涉及一种像素电路及其驱动方法、显示面板。
背景技术
随着显示技术的不断发展，显示面板的应用范围越来越广泛，人们对显示面板的要求也越来越高。显示面板中的像素电路在驱动发光器件稳定发光方面起到了非常重要的作用。然而，相关技术中的像素电路的驱动过程中，数据写入与阈值电压补偿是同一个过程，使得驱动晶体管的补偿时间不足，例如在高刷新频率下，行时间较短时，补偿时间不足使得对驱动晶体管阈值电压的补偿效果较差；并且，相关技术中的像素电路在多个灰阶下的阈值电压补偿程度存在差异。因此，相关技术中的显示面板存在显示亮度均一性欠佳，分辨率及刷新频率受限的问题。
发明内容
本申请提供了一种像素电路及其驱动方法、显示面板，以改善显示面板的显示亮度均一性，同时兼顾显示面板高分辨率和高刷新频率的实现。
本申请实施例提供了如下技术方案：
一种像素电路，包括：
驱动模块；
存储模块，分别与所述驱动模块的控制端和第一端电连接，设置为存储所述驱动模块的控制端和所述驱动模块的第一端的电位；
耦合模块，所述耦合模块的第一端与所述驱动模块的第一端电连接，所述耦合模块设置为将所述耦合模块的第二端的电位变化耦合至所述耦合模块的第一端；
第一复位模块，与所述耦合模块的第二端电连接，设置为在数据写入阶段之前，将第一复位信号传输至所述耦合模块的第二端，对所述耦合模块的第二端进行复位；
第二复位模块，与所述驱动模块的控制端电连接，设置为在阈值补偿阶段和所述数据写入阶段，将第二复位信号传输至所述驱动模块的控制端；
放电模块，与所述驱动模块的第二端电连接，设置为在所述阈值补偿阶段导通，使所述驱动模块的第一端通过所述驱动模块和所述放电模块放电，以使存储模块存储所述驱动模块的阈值电压；
数据写入模块，与所述耦合模块的第二端电连接，并接入数据电压；
发光控制模块，与所述驱动模块以及发光器件连接于第一电源和第二电源之间。
本申请实施例提供的像素电路中，设置阈值补偿阶段与数据写入阶段分离，使得阈值补偿时间可以不受数据写入行时间的限制而加长，以达到更好的补偿效果。并且，驱动模块的阈值补偿过程仅受第二复位信号和第一电源信号的控制，与数据电压的大小无关，不同行像素电路的阈值补偿阶段存在时间交叠并不会影响数据写入效果，因此阈值补偿时间的增长并不会影响显示面板的刷新频率。且本实施例是通过向耦合模块的第二端提供电位跳变来实现数据写入，那么数据写入阶段结束时数据电压的值决定着最终写入像素电路的数据电压，只要保证不同行像素电路的数据写入阶段结束时间不同，即可保证多行数据电压的正确写入，即本实施例还允许不同行数据写入时间存在部分交叠，这有利于高刷新频率的实现，同时为显示面板高分辨率的实现提供条件。以及，驱动模块的阈值补偿过程与数据电压的大小无关， 使得驱动模块的偏置不受灰阶变化的影响，无论灰阶高低、无论数据电压大小，驱动模块的阈值补偿效果都基本一致，可以减小不同灰阶间的补偿差异，提高显示均一性。因此，相比于相关技术，本申请实施例可以改善显示面板的显示亮度均一性，同时兼顾显示面板高分辨率和高刷新频率的实现。
附图说明
图1是相关技术中的一种像素电路的结构示意图；
图2是本申请实施例提供的一种像素电路的结构示意图；
图3是本申请实施例提供的另一种像素电路的结构示意图；
图4是本申请实施例提供的一种像素电路的驱动时序示意图；
图5是本申请实施例提供的另一种像素电路的驱动时序示意图；
图6是本申请实施例提供的又一种像素电路的结构示意图；
图7是本申请实施例提供的又一种像素电路的结构示意图；
图8是本申请实施例提供的又一种像素电路的驱动时序示意图；
图9是本申请实施例提供的又一种像素电路的结构示意图；
图10是本申请实施例提供的又一种像素电路的驱动时序示意图；
图11是本申请实施例提供的又一种像素电路的结构示意图；
图12是本申请实施例提供的又一种像素电路的驱动时序示意图；
图13是本申请实施例提供的一种像素电路的驱动方法的流程示意图。
具体实施方式
需要说明的是，本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含。
正如背景技术中所述，相关技术中的像素电路的驱动过程中，数据写入与阈值电压补偿在同一阶段进行，使得显示面板的显示亮度均一性欠佳，分辨率及刷新频率受限。下面结合图1，对产生上述情况的原因进行说明。图1中给出了相关技术中的一种7T1C架构的像素电路，参见图1，该像素电路包括：晶体管M01、晶体管M02、晶体管M03、晶体管M04、晶体管M05、晶体管M06、晶体管M07和存储电容Cst0。示例性地，多个晶体管均为P型晶体管，采用低温多晶硅(Low Temperature Poly-Silicon，LTPS)工艺制作而成。该像素电路需要接入的信号包括：第一电源信号VDD、第二电源信号VSS、复位信号Vref0、数据信号Data、扫描信号Sn01、扫描信号Sn02、扫描信号Sn03和发光控制信号EM0。该像素电路的驱动过程包括：复位阶段、数据写入和补偿阶段、以及发光阶段。下面主要针对该像素电路的数据写入和补偿阶段进行说明。
该像素电路中，晶体管M01为驱动晶体管，晶体管M01的栅极电位由存储电容Cst0保存；晶体管M02作为数据写入晶体管，晶体管M03作为阈值补偿晶体管，二者的栅极均接入扫描信号Sn02。在数据写入和补偿阶段：扫描信号Sn02为低电位，晶体管M02和晶体管M03均导通，数据信号Data经由晶体管M02、晶体管M01的第一极和第二极、以及晶体管M03向晶体管M01的栅极传输，同时向存储电容Cst0充电。该过程的目标为：利用存储电容Cst0将包含有数据信号Data和晶体管M01的阈值电压Vth的信息正确存储。那么该过程中至少需要等待晶体管M01的栅极被充电至Data+Vth而关断的时长，这限制了像素电路数据写入的速度，当行时间(驱动芯片提供一行像素电路所需的数据信号的维持时间)较小时，晶体管M01的栅极电位达不到Data+Vth，该数据写入和补偿阶段就提 前结束，会使得补偿效果较差。并且，不同灰阶下数据信号Data的电位不同，会导致晶体管M01在不同灰阶下的补偿差异。也就是说，相关技术像素电路中的阈值电压补偿效果受数据写入时长和数据信号Data电位大小(灰阶大小)两方面的影响，补偿时间不足会使补偿效果较差。另一角度而言，为了保证阈值补偿效果，数据写入时间需要设置的较长，使得显示面板的刷新频率受限；在刷新频率受限的情况下，即使像素电路的版图排布和制备技术可满足高分辨率的要求，由于驱动过程不满足要求，也会使得分辨率受限。
本申请实施例提供了一种新的像素电路。图2是本申请实施例提供的一种像素电路的结构示意图。参见图2，该像素电路包括：驱动模块10、存储模块20、耦合模块30、第一复位模块40、第二复位模块50、放电模块60、数据写入模块70和发光控制模块80。
其中，驱动模块10设置为根据驱动模块10的控制端N1和第一端N2的电压生成驱动电流。存储模块20分别与驱动模块10的控制端N1和第一端N2电连接，设置为存储驱动模块10的控制端N1和驱动模块10的第一端N2的电位。耦合模块30的第一端与驱动模块10的第一端N2电连接，耦合模块30设置为将耦合模块30的第二端N3的电位变化耦合至耦合模块30的第一端。第一复位模块40与耦合模块30的第二端N3电连接，第一复位模块40设置为将第一复位信号Vini传输至耦合模块30的第二端N3，以对耦合模块30的第二端N3进行复位。第二复位模块50与驱动模块10的控制端N1电连接，第二复位模块50设置为将第二复位信号Vref传输至驱动模块10的控制端N1。放电模块60与驱动模块10的第二端N4电连接，放电模块60设置为导通驱动模块10与第二复位信号线(即用于传输第二复位信号Vref的信号线)之间的信号传输路径，以将第二复位信号Vref传输至驱动模块10的第二端N4，或者放电模块60设置为在阈值补偿阶段导通，使驱动模块10的第一端N2通过驱动模块10和放电模块60放电，以使存储模块20存储驱动模块10的阈值电压。数据写入模块70与耦合模块30的第二端N3电连接，数据写入模块70设置为将数据电压Vdata写入耦合模块30的第二端N3。发光控制模块80与驱动模块10以及发光器件L连接于第一电源和第二电源之间，发光控制模块80设置为控制驱动模块10接通第一电源和第二电源。
示例性地，驱动模块10包括驱动晶体管，驱动晶体管的阈值电压即为驱动模块10的阈值电压。发光器件L的第一极为其阳极，第二极为其阴极。第一电源用于产生第一电源信号VDD，第二电源用于产生第二电源信号VSS。第一电源信号VDD、第二电源信号VSS、第一复位信号Vini和第二复位信号Vref均为直流电压信号，可由显示面板中的电源芯片或驱动芯片提供。其中，第一电源信号VDD可以是正电压信号；第二电源信号VSS可以是负电压信号。
示例性地，该像素电路的驱动过程包括：复位阶段、阈值补偿阶段、数据写入阶段和发光阶段。下面对多个阶段中多个功能模块的动作过程进行说明。例如，该像素电路的驱动过程包括：
复位阶段，第一复位模块40将第一复位信号Vini传输至耦合模块30的第二端N3，对耦合模块30的第二端N3进行复位；第二复位模块50将第二复位信号Vref传输至驱动模块10的控制端N1，对驱动模块10的控制端N1进行复位；放电模块60将第二复位信号Vref传输至驱动模块10的第二端N4，对驱动模块10的第二端N4进行复位；发光控制模块80将第一电源信号VDD传输至驱动模块10的第一端N2，并将传输至驱动模块10的第二端N4的第二复位信号Vref继续传输至发光器件L的第一极，对发光器件L的第一极进行复位。
阈值补偿阶段，第一复位模块40将第一复位信号Vini传输至耦合模块30的第二端N3，保持耦合模块30的第二端N3的电位不变；第二复位模块50将第二复位信号Vref传输至驱动模块10的控制端N1，保持驱动模块10的控制端N1的电位不变；放电模块60导通，使驱动模块10的第一端N2通过驱动模块10和放电模块60放电，直至驱动模块10的控制端N1和驱动模块10的第一端N2之间的电位差等于驱动模块10的阈值电压Vth1时，即驱动模块10的第一端N2的电位等于Vref-Vth1时，驱动模块10关断；存储模块20存储驱动模块10的阈值电压Vth1。该阶段中，驱动模块10的控制端N1的电位保持在第二复位信号 Vref的值不变，通过驱动模块10的第一端N2的放电实现阈值补偿过程。阈值补偿程度只受驱动模块10的第一端N2在该阶段初始时刻的电位(即第一电源信号VDD)和第二复位信号Vref的控制，而与数据电压Vdata无关，使得多个灰阶下驱动模块10的阈值补偿效果可以得到统一，提高显示均一性，且能补偿阈值电压Vth1为正的情况。
数据写入阶段，第二复位模块50将第二复位信号Vref传输至驱动模块10的控制端N1，保持驱动模块10的控制端N1的电位不变；数据写入模块70将数据电压Vdata写入耦合模块30的第二端N3；耦合模块30将耦合模块30的第二端N3的电位变化耦合至耦合模块30的第一端(即驱动模块10的第一端N2)，相当于将携带有数据电压Vdata信息(例如为数据电压Vdata与第一复位信号Vini之间的差值信息)的电位耦合至驱动模块10的第一端N2。由于上一阶段中存储模块20已经存储了驱动模块10的阈值电压Vth1，结合本阶段驱动模块10的第一端N2的电位跳变，使得该阶段中存储模块20两端的电位差，既携带有阈值电压Vth1的信息，又携带有数据电压Vdata的信息。
发光阶段，发光控制模块80导通，使第一电源-驱动模块10-发光器件L这条信号传输路径导通，驱动模块10根据其控制端N1和第一端N2的电压生成驱动电流，驱动电流驱动发光器件L发光。该阶段中，驱动模块10产生的驱动电流是Vgs-Vth1的函数，其中，Vgs为驱动模块10的控制端N1与第一端N2之间的电位差，即存储模块20两端的电位差。由于Vgs中携带有阈值电压Vth1的信息，经过上述减法运算后可以消除阈值电压Vth1对驱动电流的影响，达到阈值补偿效果。
本申请实施例提供的像素电路中，设置阈值补偿阶段与数据写入阶段分离，使得阈值补偿时间可以不受数据写入行时间的限制而加长，以达到更好的补偿效果。并且，驱动模块10的阈值补偿过程仅受第二复位信号Vref和第一电源信号VDD的控制，与数据电压Vdata的大小无关，不同行像素电路的阈值补偿阶段存在时间交叠并不会影响数据写入效果，因此阈值补偿时间的增长并不会影响显示面板的刷新频率。且本实施例是通过向耦合模块30的第二端N3提供电位跳变来实现数据写入，那么数据写入阶段结束时数据电压Vdata的值决定着最终写入像素电路的数据电压，只要保证不同行像素电路的数据写入阶段结束时间不同，即可保证多行数据电压的正确写入，即本实施例还允许不同行数据写入时间存在部分交叠，这有利于高刷新频率的实现，同时为显示面板高分辨率的实现提供条件。以及，驱动模块10的阈值补偿过程与数据电压Vdata的大小无关，使得驱动模块10的偏置不受灰阶变化的影响，无论灰阶高低、无论数据电压Vdata大小，驱动模块10的阈值补偿效果都基本一致，可以减小不同灰阶间的补偿差异，可提高显示均一性。因此，相比于相关技术，本申请实施例可以改善显示面板的显示亮度均一性，同时兼顾显示面板高分辨率和高刷新频率的实现。
在上述多个实施方式的基础上，例如，第一复位模块40、第二复位模块50、放电模块60、数据写入模块70和发光控制模块80均根据各自接入的控制信号来进行模块的通断控制。下面对像素电路中多个控制信号的连接方式和控制过程进行说明。
图3是本申请实施例提供的另一种像素电路的结构示意图。图4是本申请实施例提供的一种像素电路的驱动时序示意图。结合图3和图4，以多个功能模块均响应低电位的控制信号导通为例，在一种实施方式中，例如，第一复位模块40的控制端接入第一控制信号S1，第一复位模块40设置为响应第一控制信号S1，在复位阶段t1和阈值补偿阶段t2导通，将第一复位信号Vini传输至耦合模块30的第二端N3。第二复位模块50包括：第一复位单元51；第一复位单元51与驱动模块10的控制端N1电连接，并接入第三控制信号S3；第一复位单元51设置为响应第三控制信号S3，在复位阶段t1、阈值补偿阶段t2和数据写入阶段t3导通，将第二复位信号Vref传输至驱动模块10的控制端N1。放电模块60的控制端接入第一控制信号S1，放电模块60设置为响应第一控制信号S1，在复位阶段t1导通，将第二复位信号Vref传输至驱动模块10的第二端N4，以及在阈值补偿阶段t2导通，使驱动模块10的第一端N2通过驱动模块10和放电模块60放电。数据写入 模块70的控制端接入第二控制信号S2，数据写入模块70设置为响应第二控制信号S2，在数据写入阶段t3导通，将数据电压Vdata写入耦合模块30的第二端N3。发光控制模块80的控制端接入发光控制信号EM，发光控制模块80设置为响应发光控制信号EM，在复位阶段t1导通，以实现对驱动模块10的第一端N2和对发光器件L第一极的复位，以及在发光阶段t4导通，提供驱动电流向发光器件L的传输路径，使驱动电流驱动发光器件L发光。
示例性地，第一控制信号S1、第二控制信号S2、第三控制信号S3与发光控制信号EM均为电位正负交替变化的扫描信号，均可由位于显示面板边框位置的扫描驱动电路提供。示例性地，第一控制信号S1、第二控制信号S2、第三控制信号S3与发光控制信号EM各自由不同组扫描电路提供。
根据图4可知，第一控制信号S1的低电位脉冲与第三控制信号S3的低电位脉冲在复位阶段t1和阈值补偿阶段t2存在交叠，第二控制信号S2的低电位脉冲与第三控制信号S3的低电位脉冲在数据写入阶段t3存在交叠，第二控制信号S2的低电位脉冲与第一控制信号S1的低电位脉冲无交叠，以及，发光控制信号EM的高电位脉冲时间涵盖阈值补偿阶段t2和数据写入阶段t3。因此，只要多个控制信号的时序满足上述特征即可保证像素电路的正常驱动，图4所示驱动时序并不作为对本申请的限定。在其他实施方式中，如图5所示，第三控制信号S3的脉冲宽度可以略短于图4中第三控制信号S3的脉冲宽度，只要保证第三控制信号S3的低电位脉冲在复位阶段t1仍与第一控制信号S1的低电位脉冲仍存在交叠即可。示例性地，第三控制信号S3的脉冲宽度与第一控制信号S1的脉冲宽度相同，这样，第一控制信号S1和第三控制信号S3可由级联连接的同组扫描电路提供，以减少用于驱动像素电路所设置的扫描电路组数，简化扫描驱动电路结构，有利于显示面板窄边框的实现。例如，基于多级扫描电路移位输出的特性，用于提供第一控制信号S1的扫描电路可以为用于输出第三控制信号S3的扫描电路的前级(前一级或前几级均可)扫描电路。
下面就像素电路可能具有的几种具体结构进行解释说明。
图6是本申请实施例提供的又一种像素电路的结构示意图。参见图6，在一种实施方式中，例如，驱动模块10包括：驱动晶体管DTFT；驱动晶体管DTFT的控制极作为驱动模块10的控制端N1，第一极作为驱动模块10的第一端N2，第二极作为驱动模块10的第二端N4。本实施例设置驱动模块10由一个晶体管构成，使得像素电路的结构简单，易于实现。
继续参见图6，在一种实施方式中，例如，存储模块20包括第一电容Cst1；第一电容Cst1的第一端与驱动模块10的控制端N1电连接，第一电容Cst1的第二端与驱动模块10的第一端N2电连接。本实施例设置存储模块20由一个电容构成，使得像素电路的结构简单，易于实现。
继续参见图6，在一种实施方式中，例如，耦合模块30包括第二电容Cst2；第二电容Cst2的第一端作为耦合模块30的第一端，与第一电容Cst1的第二端电连接；第二电容Cst2的第二端作为耦合模块30的第二端N3，与第一复位模块40和数据写入模块70电连接。本实施例设置耦合模块30由一个电容构成，使得像素电路的结构简单，易于实现。
继续参见图6，在一种实施方式中，例如，第一复位模块40包括：第四晶体管T4；第四晶体管T4的控制极接入第一控制信号S1，第一极接入第一复位信号Vini，第二极与耦合模块30的第二端N3电连接。本实施例设置第一复位模块40由一个晶体管构成，使像素电路的结构简单，易于实现。
继续参见图6，在一种实施方式中，例如，当第二复位模块包括第一复位单元51时，第一复位单元51包括：第一晶体管T1；第一晶体管T1的控制极接入第三控制信号S3，第一极接入第二复位信号Vref，第二极与驱动模块10的控制端N1电连接。本实施例设置第一复位单元51由一个晶体管构成，使像素电路的结构简单，易于实现。
继续参见图6，在一种实施方式中，例如，放电模块60包括：第五晶体管T5；第五晶体管T5的控制极接入第一控制信号S1，第一极接入第二复位信号Vref，第二极与驱动模块10的第二端N4电连接。本实施例设置放电模块60由一个晶体管构成，使像素电路的结构简单，易于实现。
继续参见图6，在一种实施方式中，例如，数据写入模块70包括：第六晶体管T6；第六晶体管T6的控制极接入第二控制信号S2，第一极接入数据电压Vdata，第二极与耦合模块30的第二端N3电连接。本实施例设置数据写入模块70由一个晶体管构成，使像素电路的结构简单，易于实现。
继续参见图6，在一种实施方式中，例如，发光控制模块80包括：第七晶体管T7和第八晶体管T8；第七晶体管T7的控制极和第八晶体管T8的控制极均接入发光控制信号EM；第七晶体管T7的第一极接入第一电源，第二极与驱动晶体管DTFT的第一极电连接；第八晶体管T8的第一极与驱动晶体管DTFT的第二极电连接，第二极与发光器件L的第一极电连接。本实施例设置发光控制模块80由两个晶体管构成，使像素电路的结构简单，易于实现。
综上所述，本申请实施例提供了一种7T2C的像素电路架构，示例性地，像素电路中的多个晶体管可以均为P型晶体管，采用LTPS工艺制备，以降低显示面板的制备成本。
下面结合图4和图6，对像素电路的驱动过程进行具体说明。该像素电路的驱动过程包括：
复位阶段t1，第一控制信号S1、第三控制信号S3与发光控制信号EM均为低电位，第二控制信号S2为高电位。第一晶体管T1、第四晶体管T4、第五晶体管T5、第七晶体管T7和第八晶体管T8均导通。第一复位信号Vini经过第四晶体管T4传输至第二电容Cst2的第二端(即耦合模块30的第二端N3)。第二复位信号Vref经过第一晶体管T1传输至驱动晶体管DTFT的控制极(即驱动模块10的控制端N1)。同时，第二复位信号Vref经过第五晶体管T5传输至驱动晶体管DTFT的第二极(即驱动模块10的第二端N4)，并继续经过第八晶体管T8传输至发光器件L的第一极。第一电源信号VDD经过第七晶体管T7传输至驱动晶体管DTFT的第一极(即驱动模块10的第一端N2)。该阶段中，第一电容Cst1和第二电容Cst2均被放电复位，发光器件L的第一极也被复位。
阈值补偿阶段t2，第一控制信号S1与第三控制信号S3均为低电位，第二控制信号S2与发光控制信号EM均为高电位。第七晶体管T7和第八晶体管T8关断，第一晶体管T1、第四晶体管T4和第五晶体管T5保持导通。第一复位信号Vini通过第四晶体管T4传输至耦合模块30的第二端N3，保持耦合模块30的第二端N3的电位稳定。第二复位信号Vref通过第一晶体管T1传输至驱动模块10的控制端N1，保持驱动模块10的控制端N1的电位稳定。驱动模块10的第一端N2通过驱动晶体管DTFT和第五晶体管T5放电，直至驱动模块10的第一端N2的电位从第一电源信号VDD的电位值降至Vref-Vth1时，驱动晶体管DTFT关断。第一电容Cst1中保存了驱动晶体管DTFT的阈值电压Vth1的压降。
数据写入阶段t3，第二控制信号S2与第三控制信号S3均为低电位，第一控制信号S1与发光控制信号EM均为高电位。第四晶体管T4和第五晶体管T5关断，第六晶体管T6导通，第一晶体管T1保持导通。第二复位信号Vref通过第一晶体管T1传输至驱动模块10的控制端N1，保持驱动模块10的控制端N1的电位稳定。数据电压Vdata经过第六晶体管T6写入耦合模块30的第二端N3，使得耦合模块30的第二端N3的电位由第一复位信号Vini跳变到数据电压Vdata，基于电容的耦合作用，第二电容Cst2将其第二端的电位变化传输至其第一端，使得驱动模块10的第一端N2的电位跳变为：Vref-Vth1+(Vdata-Vini)*(Cst2)/(Cst1+Cst2+Cgs)，其中，Cgs为驱动晶体管DTFT的控制极与第一极之间的电容。那么，第一电容Cst1两端的电压差变化为Vth1-(Vdata-Vini)*(Cst2)/(Cst1+Cst2+Cgs)。
发光阶段t4，发光控制信号EM为低电位，第一控制信号S1、第二控制信号S2与第三控制信号S3均为高电位。第一晶体管T1与第六晶体管T6关断，第七晶体管T7与第八晶 体管T8导通，驱动晶体管DTFT产生驱动电流以点亮发光器件L。驱动电流是Vgs-Vth1的函数，其中，Vgs等于第一电容Cst1两端的电压差。当像素电路的结构确定时，第一电容Cst1、第二电容Cst2与Cgs随之确定为定值，因此实际上驱动电流为Vdata-Vini的函数，即驱动电流的大小与驱动晶体管DTFT的阈值电压Vth1无关，即实现了阈值补偿。
综上所述，本申请实施例提供了一种7T2C的像素电路架构，将阈值补偿过程和数据写入过程分开，结合LTPS晶体管的迁移率高，驱动能力强，以及技术成熟等优点，有利于提升显示面板亮度均一性，同时兼顾高频刷新和高分辨率的实现。
上述多个实施方式示例性地给出了像素中的多个晶体管均由P型晶体管构成，但不作为对本申请的限定。在其他实施方式中，可以根据需求将部分或全部晶体管替换为N型晶体管，并相应调整晶体管所接入控制信号的高低电位。下面对其中几种调整方式进行说明。
图7是本申请实施例提供的又一种像素电路的结构示意图。参见图7，在一种实施方式中，例如，相较于图6中的像素电路，可以将第一晶体管T1替换为N型晶体管，例如为N型铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)晶体管。这样，基于N型晶体管漏电流低的特性，可以减小驱动晶体管DTFT控制极的漏电流，使驱动晶体管DTFT控制极的电位可以被长时间维持，从而使像素电路支持低刷新功能，有利于显示面板宽频驱动的实现。图7所示像素电路的驱动时序可参见图8，对比图8和图4可知，将第一晶体管T1替换为N型晶体管后，第三控制信号S3的脉冲置反。
图9是本申请实施例提供的又一种像素电路的结构示意图。参见图9，在图7的基础上，例如，还可以将第四晶体管T4和第五晶体管T5也替换为N型晶体管。图9所示像素电路的驱动时序可参见图10，对比图10和图5可知，将第一晶体管T1、第四晶体管T4和第五晶体管T5均替换为N型晶体管后，第一控制信号S1和第三控制信号S3的脉冲均置反，那么第一控制信号S1和第三控制信号S3仍可以由级联连接的同组扫描电路提供，有利于显示面板窄边框的实现。
上述多个实施方式中示例性地给出了第二复位模块的一种结构，但不作为对本申请的限定。在其他实施方式中，如图11所示，第二复位模块还可以由第二复位单元和数据写入辅助单元构成，下面进行具体说明。
参见图11，在一种实施方式中，例如，第二复位模块50包括：第二复位单元52和数据写入辅助单元53。其中，第二复位单元52与驱动模块10的控制端N1电连接，设置为响应第一控制信号S1，在复位阶段和阈值补偿阶段导通，将第二复位信号Vref传输至驱动模块10的控制端N1。数据写入辅助单元53与驱动模块10的控制端N1电连接，设置为响应第二控制信号S2，在数据写入阶段导通，将第二复位信号Vref传输至驱动模块10的控制端N1。本实施例这样设置，使得像素电路不再需要第三控制信号，那么显示面板中可以减少一组控制信号线，有利于简化显示面板结构。
结合图11中的像素电路和图12中的驱动时序可以看出，第一控制信号S1和第二控制信号S2的脉冲时间无交叠，本实施例通过对第二复位单元52和数据写入辅助单元53的作用时段分离，使得在第一控制信号S1的控制下，第二复位单元52与第一复位模块40和放电模块60，均仅作用于复位阶段t1和阈值补偿阶段t2；以及在第二控制信号S2的控制下，数据写入辅助单元53与数据写入模块70均仅作用于数据写入阶段t3。这样相当于将像素电路的阈值补偿和数据写入过程在时段和控制信号上进行了完全的分离。既不需要两控制信号(第一控制信号和第三控制信号)的低电位脉冲交叠来实现阈值补偿过程，也不需要两控制信号(第二控制信号与第三控制信号)的低电位脉冲交叠来实现数据写入，也不需要设置有级联关系的扫描电路向同一像素电路提供控制信号。该像素电路仅需要第一控制信号S1、第二控制信号S2和发光控制信号EM这三个完全分立的控制信号来实现驱动。以及，针对同一行像素电路，像素电路结构和驱动时序的设置使得阈值补偿阶段t2和数据写入阶段t3先后进行，互不干扰；针对不同行像素电路，用于提供控制数据写入阶段实现的第二控制信 号S2的扫描电路与用于提供控制阈值补偿阶段实现的第一控制信号S1的扫描电路分立设置，两类扫描电路之间无级联或其他关联控制关系，信号生成过程互不影响，因此不同行像素电路的阈值补偿阶段t2和数据写入阶段t3之间也不会由于控制信号的关联关系而相互限制，有利于简化显示面板的控制逻辑，并为显示面板高刷新频率的实现提供条件。
继续参见图11，在上述多个实施方式的基础上，例如，第二复位单元52包括第二晶体管T2；第二晶体管T2的控制极接入第一控制信号S1，第一极接入第二复位信号Vref，第二极与驱动模块10的控制端N1电连接。数据写入辅助单元53包括：第三晶体管T3；第三晶体管T3的控制极接入第二控制信号S2，第一极接入第二复位信号Vref，第二极与驱动模块10的控制端N1电连接。本实施例设置第二复位单元52和数据写入辅助单元53均由一个晶体管构成，使像素电路的结构简单，易于实现。
图11中提供了一种8T2C架构的像素电路，并示例性地给出了多个晶体管均为P型晶体管的结构，但不作为对本申请的限定，在其他实施方式中，例如，可以将部分或全部晶体管替换为N型晶体管。例如为了减少驱动晶体管DTFT控制极的漏电，将第二晶体管T2和第三晶体管T3替换为N型晶体管；在此基础上，为了不增加控制信号的数量，可以将第四晶体管T4、第五晶体管T5和第六晶体管T6也均替换为N型晶体管。
在上述多个实施方式的基础上，例如，阈值补偿阶段t2的保持时长可以设置为超过1个行时间，甚至达到数百个行时间，以延长阈值补偿时间，保证阈值补偿效果。
在上述多个实施方式的基础上，例如，第一电源信号VDD可复用为第一复位信号Vini，以减少显示面板中信号线的数量，有利于简化显示面板结构，以便于显示面板的布线设计。
需要说明的是，在上述多个实施例中，多个晶体管的第一极可以称作源极或漏极，相应的，多个晶体管的第二极可以称作漏极或源极，由于在显示面板中晶体管的结构对称，这里对多个晶体管的源极和漏极不做区分。
本申请实施例还提供了一种显示面板，该显示面板包括本申请任意实施例所提供的像素电路，具有相应的有益效果，不再赘述。
本申请实施例还提供了一种像素电路的驱动方法，该驱动方法可适用于本申请任意实施例所提供的像素电路，并具备相应的有益效果。图13是本申请实施例提供的一种像素电路的驱动方法的流程示意图。参见图13，该像素电路的驱动方法包括：
S110、复位阶段，控制第一复位模块将第一复位信号传输至耦合模块的第二端；控制第二复位模块将第二复位信号传输至驱动模块的控制端；控制放电模块将第二复位信号传输至驱动模块的第二端；控制发光控制模块将第一电源提供的第一电源信号传输至驱动模块的第一端，并将第二复位信号传输至发光器件的第一极。
S120、阈值补偿阶段，控制第一复位模块将第一复位信号传输至耦合模块的第二端，控制第二复位模块将第二复位信号传输至驱动模块的控制端，控制放电模块导通，使驱动模块的第一端通过驱动模块和放电模块放电，直至驱动模块的控制端和驱动模块的第一端之间的电位差等于驱动模块的阈值电压，驱动模块关断；存储模块存储阈值电压。
S130、数据写入阶段，控制第二复位模块将第二复位信号传输至驱动模块的控制端，控制数据写入模块将数据电压写入耦合模块的第二端；耦合模块将耦合模块的第二端的电位变化耦合至耦合模块的第一端。
S140、发光阶段，控制发光控制模块导通，使驱动模块根据驱动模块的控制端和第一端的电压生成驱动电流，并使驱动电流传输至发光器件。
本申请实施例提供的像素电路的驱动方法，通过将阈值补偿阶段与数据写入阶段分开设置，可以兼顾显示面板的显示亮度均一性，以及显示面板高分辨率和高刷新频率的实现。
需要说明的是，在像素电路的多个实施例中，针对不同的像素电路进行了驱动方法的 具体说明，这些驱动方法均可以认为是本申请实施例提供的像素电路的驱动方法，重复内容此处不再赘述。
应该理解，可以使用上面所示的多种形式的流程，重新排序、增加或删除步骤。例如，本申请中记载的多个步骤可以并行地执行也可以顺序地执行也可以不同的次序执行，只要能够实现本申请的技术方案所期望的结果，本文在此不进行限制。

Claims (20)

  1. 一种像素电路，包括：
    驱动模块；
    存储模块，分别与所述驱动模块的控制端和第一端电连接，设置为存储所述驱动模块的控制端和所述驱动模块的第一端的电位；
    耦合模块，所述耦合模块的第一端与所述驱动模块的第一端电连接，所述耦合模块设置为将所述耦合模块的第二端的电位变化耦合至所述耦合模块的第一端；
    第一复位模块，与所述耦合模块的第二端电连接，设置为在数据写入阶段之前，将第一复位信号传输至所述耦合模块的第二端，对所述耦合模块的第二端进行复位；
    第二复位模块，与所述驱动模块的控制端电连接，设置为在阈值补偿阶段和所述数据写入阶段，将第二复位信号传输至所述驱动模块的控制端；
    放电模块，与所述驱动模块的第二端电连接，设置为在所述阈值补偿阶段导通，使所述驱动模块的第一端通过所述驱动模块和所述放电模块放电，以使所述存储模块存储所述驱动模块的阈值电压；
    数据写入模块，与所述耦合模块的第二端电连接，并接入数据电压；
    发光控制模块，与所述驱动模块以及发光器件连接于第一电源和第二电源之间。
  2. 根据权利要求1所述的像素电路，其中，所述存储模块包括第一电容；所述第一电容的第一端与所述驱动模块的控制端电连接，所述第一电容的第二端与所述驱动模块的第一端电连接；
    所述耦合模块包括第二电容；所述第二电容的第一端作为所述耦合模块的第一端，所述第二电容的第二端作为所述耦合模块的第二端。
  3. 根据权利要求1所述的像素电路，其中，所述第一复位模块的控制端接入第一控制信号，所述第一复位模块设置为响应所述第一控制信号，在复位阶段和所述阈值补偿阶段导通，将所述第一复位信号传输至所述耦合模块的第二端；
    所述放电模块的控制端接入所述第一控制信号，所述放电模块设置为响应所述第一控制信号，在所述复位阶段导通，将所述第二复位信号传输至所述驱动模块的第二端，以及在所述阈值补偿阶段导通，使所述驱动模块的第一端通过所述驱动模块和所述放电模块放电；
    所述数据写入模块的控制端接入第二控制信号，所述数据写入模块设置为响应所述第二控制信号，在所述数据写入阶段导通，将所述数据电压写入所述耦合模块的第二端；
    所述发光控制模块的控制端接入发光控制信号，所述发光控制模块设置为响应所述发光控制信号，在所述复位阶段和发光阶段导通。
  4. 根据权利要求3所述的像素电路，其中，所述第二复位模块包括：第一复位单元，与所述驱动模块的控制端电连接，并接入第三控制信号；所述第一复位单元设置为响应所述第三控制信号，在所述复位阶段、所述阈值补偿阶段和所述数据写入阶段导通，将所述第二复位信号传输至所述驱动模块的控制端。
  5. 根据权利要求4所述的像素电路，其中，所述第一复位单元包括：第一晶体管；所述第一晶体管的控制极接入所述第三控制信号，所述第一晶体管的第一极接入所述第二复位信号，所述第一晶体管的第二极与所述驱动模块的控制端电连接。
  6. 根据权利要求5所述的像素电路，其中，所述第一晶体管为N型晶体管。
  7. 根据权利要求4所述的像素电路，其中，所述第一控制信号和所述第三控制信号由级联连接的同组扫描电路提供，且用于提供所述第一控制信号的扫描电路为用于输出所述第三控制信号的扫描电路的前级扫描电路。
  8. 根据权利要求3所述的像素电路，其中，所述第二复位模块包括：
    第二复位单元，与所述驱动模块的控制端电连接，设置为响应所述第一控制信号，在所述复位阶段和所述阈值补偿阶段导通，将所述第二复位信号传输至所述驱动模块的控制端；
    数据写入辅助单元，与所述驱动模块的控制端电连接，设置为响应所述第二控制信号，在数据写入阶段导通，将所述第二复位信号传输至所述驱动模块的控制端。
  9. 根据权利要求8所述的像素电路，其中，所述第二复位单元包括第二晶体管；所述第二晶体管的控制极接入所述第一控制信号，所述第二晶体管的第一极接入所述第二复位信号，所述第二晶体管的第二极与所述驱动模块的控制端电连接；
    所述数据写入辅助单元包括：第三晶体管；所述第三晶体管的控制极接入所述第二控制信号，所述第三晶体管的第一极接入所述第二复位信号，所述第三晶体管的第二极与所述驱动模块的控制端电连接。
  10. 根据权利要求1-9任一项所述的像素电路，其中，所述驱动模块包括：驱动晶体管；所述驱动晶体管的控制极作为所述驱动模块的控制端，所述驱动晶体管的第一极作为所述驱动模块的第一端，所述驱动晶体管的第二极作为所述驱动模块的第二端；
    所述第一复位模块包括：第四晶体管；所述第四晶体管的控制极接入第一控制信号，所述第四晶体管的第一极接入所述第一复位信号，所述第四晶体管的第二极与所述耦合模块的第二端电连接；
    所述放电模块包括：第五晶体管；所述第五晶体管的控制极接入所述第一控制信号，所述第五晶体管的第一极接入所述第二复位信号，所述第五晶体管的第二极与所述驱动模块的第二端电连接；
    所述数据写入模块包括：第六晶体管；所述第六晶体管的控制极接入第二控制信号，所述第六晶体管的第一极接入所述数据电压，所述第六晶体管的第二极与所述耦合模块的第二端电连接；
    所述发光控制模块包括：第七晶体管和第八晶体管；所述第七晶体管的控制极和所述第八晶体管的控制极均接入发光控制信号，所述第七晶体管的第一极接入所述第一电源，所述第七晶体管的第二极与所述驱动晶体管的第一极电连接，所述第八晶体管的第一极与所述驱动晶体管的第二极电连接，所述第八晶体管的第二极与所述发光器件的第一极电连接。
  11. 根据权利要求1所述的像素电路，其中，所述第一复位信号和所述第二复位信号分别为直流电压信号。
  12. 根据权利要求4所述的像素电路，其中，所述第一控制信号、所述第二控制信号和所述第三控制信号分别为电位正负交替变化的扫描信号。
  13. 根据权利要求1所述的像素电路，其中，所述第一电源产生的第一电源信号可复用为所述第一复位信号。
  14. 根据权利要求9所述的像素电路，其中，将所述驱动晶体管的阈值电压作为所述驱动模块的阈值电压。
  15. 一种显示面板，包括：权利要求1-14任一项所述的像素电路。
  16. 一种像素电路的驱动方法，用于驱动如权利要求1-14任一项所述的像素电路；所述驱动方法包括：
    在复位阶段，控制所述第一复位模块将所述第一复位信号传输至所述耦合模块的第二端；控制所述第二复位模块将所述第二复位信号传输至所述驱动模块的控制端；控制所述放电模块将所述第二复位信号传输至所述驱动模块的第二端；控制所述发光控制模块将所述第一电源提供的第一电源信号传输至所述驱动模块的第一端，并将所述第二复位信号传输至所述发光器件的第一极；
    在阈值补偿阶段，控制所述第一复位模块将所述第一复位信号传输至所述耦合模块的第二端，控制所述第二复位模块将所述第二复位信号传输至所述驱动模块的控制端，控制所述放电模块导通，使所述驱动模块的第一端通过所述驱动模块和所述放电模块放电，直至所述驱动模块的控制端和所述驱动模块的第一端之间的电位差等于所述驱动模块的阈值电压，所述驱动模块关断；所述存储模块存储所述阈值电压；
    在数据写入阶段，控制所述第二复位模块将所述第二复位信号传输至所述驱动模块的控制端，控制所述数据写入模块将所述数据电压写入所述耦合模块的第二端；所述耦合模块将所述耦合模块的第二端的电位变化耦合至所述耦合模块的第一端；
    在发光阶段，控制所述发光控制模块导通，使所述驱动模块根据所述驱动模块的控制端和第一端的电压生成驱动电流，并使所述驱动电流传输至所述发光器件。
  17. 根据权利要求15所述的驱动方法，其中，在所述复位阶段，所述第一复位模块的控制端接入的第一控制信号，所述第二复位模块接入的第三控制信号，以及所述发光控制模块的控制端输入的发光控制信号分别为低电位，所述数据写入模块的控制端接入的第二控制信号为高电位。
  18. 根据权利要求15所述的驱动方法，其中，在所述阈值补偿阶段，所述第一复位模块的控制端接入的第一控制信号，以及所述第二复位模块接入的第三控制信号分别为低电位，所述数据写入模块的控制端接入的第二控制信号，以及所述发光控制模块的控制端输入的发光控制信号分别为高电位。
  19. 根据权利要求15所述的驱动方法，其中，在所述数据写入阶段，所述数据写入模块的控制端接入的第二控制信号，以及所述第二复位模块接入的第三控制信号分别为低电位，所述第一复位模块的控制端接入的第一控制信号，以及所述发光控制模块的控制端输入的发光控制信号分别为高电位。
  20. 根据权利要求15所述的驱动方法，其中，在所述发光阶段，所述发光控制模块的控制端输入的发光控制信号为低电位，所述第一复位模块的控制端接入的第一控制信号，所述数据写入模块的控制端接入的第二控制信号，以及所述第二复位模块接入的第三控制信号分别为高电位。
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