WO2022227231A1 - 像素电路及显示面板 - Google Patents

像素电路及显示面板 Download PDF

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Publication number
WO2022227231A1
WO2022227231A1 PCT/CN2021/098536 CN2021098536W WO2022227231A1 WO 2022227231 A1 WO2022227231 A1 WO 2022227231A1 CN 2021098536 W CN2021098536 W CN 2021098536W WO 2022227231 A1 WO2022227231 A1 WO 2022227231A1
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WO
WIPO (PCT)
Prior art keywords
transistor
drain
source
light
module
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Application number
PCT/CN2021/098536
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English (en)
French (fr)
Inventor
孙亮
曾勉
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/432,948 priority Critical patent/US20240127738A1/en
Publication of WO2022227231A1 publication Critical patent/WO2022227231A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness

Definitions

  • the present application relates to the field of display technology, and in particular, to a pixel circuit and a display panel.
  • the gate of the driving transistor in the pixel circuit of the traditional technical solution generally has the problem of leakage current, which makes the gate potential of the driving transistor difficult to maintain.
  • the 7T1C pixel circuit shown in Figure 1 its working process can be divided into Figure 2 Three main stages of operation are shown:
  • the first stage S1 the N-1 stage scan signal SCAN(N-1) is set to a low level, the transistor T4 is turned on, and the gate potential of the driving transistor T1 is reset to the potential of the initial signal VI.
  • the second stage S2 the Nth-level scan signal SCAN(N) is set to a low level, the transistor T2 and the transistor T3 are turned on, and the data signal DATA sequentially charges the gate potential of the driving transistor T1 through the transistor T2, the transistor T1 and the transistor T3 to V DATA -Vth, where V DATA is the potential of the data signal DATA, and Vth is the threshold voltage of the driving transistor T1; at the same time, the transistor T7 is turned on, and the anode potential of the light emitting device LED is reset to the potential of the initial signal VI.
  • the third stage S3 the light-emitting control signal EM(N) is set to a low level, and the light-emitting device LED starts to emit light.
  • the transistors T1-T3 are turned on, and the transistors T4-T6 are turned off.
  • the data signal DATA charges the gate potential of the driving transistor T1 through the paths of the transistors T1 to T3.
  • the driving transistor T1 is turned off, and the gate potential of the driving transistor T1 does not rise any more.
  • the light-emitting brightness of the pixel is directly determined by the gate potential of the driving transistor T1, and in the light-emitting stage T, the most important factor affecting the gate potential of the driving transistor T1 is the leakage current, which will directly affect the light-emitting stage Brightness stability of T. As shown in Figure 3, this will cause the brightness of the picture to decrease with time, and then there is a brightness difference ⁇ L1 in the light-emitting stage T within a frame. When the brightness difference ⁇ L1 reaches a certain value, the human eye can feel it.
  • the screen flickers flicker
  • the present application provides a pixel circuit and a display panel, which alleviate the technical problem that the potential of the control terminal of the driving module in the pixel circuit is not easily maintained.
  • the present application provides a pixel circuit, which includes a first power supply line, a second power supply line, a light-emitting device, a driving transistor, a writing transistor, a dump capacitor, and a first switching transistor; connected in series with the first power supply line The light-emitting device and the driving transistor between the second power supply line; the storage capacitor is electrically connected to the gate of the driving transistor; one of the source/drain of the writing transistor is electrically connected to the storage capacitor, and the source/drain of the writing transistor is electrically connected.
  • the other one of the drains is used for accessing data signals; the dump capacitor is electrically connected to one of the source/drain of the write transistor; one of the source/drain of the first switching transistor is connected to the dump capacitor and One of the source/drain of the write transistor is electrically connected, and the other of the source/drain of the first switching transistor is electrically connected to one of the source/drain of the drive transistor.
  • the pixel circuit further includes a second switch transistor; one of the source/drain of the second switch transistor is electrically connected to the other of the source/drain of the drive transistor; The other of the source/drain is electrically connected to the storage capacitor and the gate of the drive transistor.
  • the gate of the write transistor is used to access the first control signal; the gate of the first switch transistor is used to access the second control signal; the gate of the second switch transistor is used to access the first control signal.
  • Two control signals in the same frame, the number of valid pulses of the first control signal is less than the number of valid pulses of the second control signal, and at least one valid pulse of the second control signal is the same as the valid pulse of the first control signal.
  • the pixel circuit further includes a third switch transistor; one of the source/drain of the third switch transistor is electrically connected to one of the source/drain of the first switch transistor; the third switch transistor The other of the source/drain of the first switching transistor is electrically connected with the other of the source/drain of the first switching transistor.
  • the pixel circuit further includes a fourth switch transistor; one of the source/drain of the fourth switch transistor is electrically connected to one of the source/drain of the second switch transistor; the fourth switch transistor The other of the source/drain of the second switching transistor is electrically connected with the other of the source/drain of the second switching transistor.
  • the working phase of the pixel circuit includes a writing phase and a light-emitting phase; the gate of the writing transistor is used to access the first control signal; the gate of the first switching transistor is used to access the first control signal ; the gate of the second switching transistor is used to access the first control signal; the gate of the third switching transistor is used to access the third control signal; the gate of the fourth switching transistor is used to access the third control signal; In the same frame, the active pulse of the first control signal is in the writing phase, and the active pulse of the third control signal is in the light-emitting phase.
  • the pixel circuit further includes a first light emission control transistor; one of the source/drain of the first light emission control transistor and one of the source/drain of the driving transistor and the source of the first switching transistor The other one of the electrode/drain is electrically connected; the gate of the first light-emitting control transistor is used for accessing the light-emitting control signal.
  • the pixel circuit further includes a second light emission control transistor; one of the source/drain of the second light emission control transistor and the other of the source/drain of the driving transistor and the second switch transistor One of the source/drain is electrically connected; the gate of the second light-emitting control transistor is used for accessing the light-emitting control signal.
  • the present application provides a pixel circuit, which includes a writing module, a dumping module, a first time-sharing transmission module, a driving module, a second time-sharing transmission module, and a storage module;
  • the writing module is used to access data signal;
  • the dumping module is connected with the writing module for storing data signals to output compensation signals in the light-emitting stage of the pixel circuit;
  • the first time-sharing transmission module is connected with the writing module and the dumping module for time-sharing transmission of data signal and compensation signal;
  • the input end of the driving module is connected with the output end of the first time-sharing transmission module;
  • the input end of the second time-sharing transmission module is connected with the output end of the driving module for time-sharing transmission of data signals and compensation signals;
  • the storage module is connected to the control terminal of the driving module and the output terminal of the second time-sharing transmission module, and is used for time-sharing storage of the data signal and the compensation signal in the same frame, so as to maintain the potential of the control terminal of the driving module in
  • the pixel circuit further includes a light-emitting control module; the light-emitting control module is connected to the driving module, and is used to control the light-emitting circuit of the pixel circuit on and off according to the light-emitting control signal; in the light-emitting stage, the light-emitting control signal controls the light-emitting control module During the off state, the pixel circuit controls the compensation signal to be written to the memory module.
  • the light-emitting control module is connected to the driving module, and is used to control the light-emitting circuit of the pixel circuit on and off according to the light-emitting control signal; in the light-emitting stage, the light-emitting control signal controls the light-emitting control module During the off state, the pixel circuit controls the compensation signal to be written to the memory module.
  • the write module includes a write transistor; one of the source/drain of the write transistor is used to access the data signal; the other of the source/drain of the write transistor and the dump The module is connected to the first time-sharing transmission module; the gate of the writing transistor is used for accessing the first control signal.
  • the dumping module includes a dumping capacitor; the first end of the dumping capacitor is connected to the other one of the source/drain of the writing transistor; the second end of the dumping capacitor is used to connect to the first end of the dumping capacitor. a power signal.
  • the first time-sharing transmission module includes a first time-sharing transmission transistor; one of the source/drain of the first time-sharing transmission transistor is connected to the first end of the dump capacitor; the first time-sharing transmission transistor The other one of the source/drain of the transmission transistor is connected to the driving module; the gate of the first time-sharing transmission transistor is used to access the second control signal; in the same frame, the number of effective pulses of the first control signal is less than that of the first control signal.
  • the number of valid pulses of the two control signals, and at least one valid pulse of the second control signal is the same as the valid pulse of the first control signal.
  • the driving module includes a driving transistor; one of the source/drain of the driving transistor is connected to the other of the source/drain of the first time-sharing transfer transistor; the source/drain of the driving transistor The other one of the poles is connected to the input terminal of the second time-sharing transmission module.
  • the second time-sharing transmission module includes a second time-sharing transmission transistor; one of the source/drain of the second time-sharing transmission transistor is connected to the other of the source/drain of the driving transistor ; The other one of the source/drain of the second time-division transmission transistor is connected to the gate of the driving transistor; the gate of the second time-division transmission transistor is used for accessing the second control signal.
  • the storage module includes a storage capacitor; a first end of the storage capacitor is connected to the gate of the driving transistor; and a second end of the storage capacitor is connected to the second end of the dump capacitor.
  • the lighting control module includes a first lighting control transistor and a second lighting control transistor; one of the source/drain of the first lighting control transistor is connected to the second terminal of the storage capacitor; the first lighting control The other one of the source/drain of the transistor is connected to one of the source/drain of the driving transistor; the gate of the first light-emitting control transistor is used to access the light-emitting control signal; the source/drain of the second light-emitting control transistor One of the drains is connected to the other of the source/drain of the driving transistor; the gate of the second light-emitting control transistor is used for accessing the light-emitting control signal.
  • the first time-sharing transmission module includes a first transistor and a second transistor; one of the source/drain of the first transistor and one of the source/drain of the second transistor and the dump The first terminal of the capacitor is connected; the other one of the source/drain of the first transistor is connected to the other of the source/drain of the second transistor and the input terminal of the driving module; the gate of the first transistor is used for access the first control signal; the gate of the second transistor is used to access the third control signal; in the same frame, the effective pulse of the first control signal is in the writing phase, and the effective pulse of the third control signal is in the light-emitting phase middle.
  • the second time-sharing transmission module includes a third transistor and a fourth transistor; one of the source/drain of the third transistor and one of the source/drain of the fourth transistor and a driving module
  • the output terminal of the third transistor is connected; the other one of the source/drain of the third transistor is connected to the other of the source/drain of the fourth transistor and the control terminal of the driving module; the gate of the third transistor is used to connect the first control signal; the gate of the fourth transistor is used to access the third control signal.
  • the present application provides a display panel including the pixel circuit in any one of the above embodiments.
  • the pixel circuit and the display panel provided by the present application can simultaneously charge the storage module and the dumping module through data signals, and the dumping module can pass the first time-sharing transmission module, the driving module and the second time-sharing transmission module in the light-emitting stage.
  • the storage module is recharged, which is beneficial to maintain the potential of the control terminal of the driving module.
  • FIG. 1 is a schematic structural diagram of a pixel circuit in a conventional technical solution.
  • FIG. 2 is a timing diagram of the pixel circuit in FIG. 1 .
  • FIG. 3 is the luminance difference of the pixel circuit in FIG. 1 in the light-emitting stage of one frame.
  • FIG. 4 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 5 is a timing diagram of the pixel circuit in FIG. 4 .
  • FIG. 6 is a working schematic diagram of the writing phase of the pixel circuit in FIG. 4 .
  • FIG. 7 is a working schematic diagram of the dumping stage of the pixel circuit in FIG. 4 .
  • FIG. 8 is another schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 9 is a timing diagram of the pixel circuit in FIG. 8 .
  • FIG. 10 is a working schematic diagram of the writing phase of the pixel circuit of FIG. 8 .
  • FIG. 11 is a working schematic diagram of the dumping stage of the pixel circuit in FIG. 8 .
  • FIG. 12 is a schematic diagram showing the comparison of luminance differences of different pixel circuits.
  • FIG. 13 is a schematic structural diagram of a GOA circuit provided by an embodiment of the present application.
  • FIG. 14 is another schematic structural diagram of the GOA circuit provided by the embodiment of the present application.
  • FIG. 15 is a schematic timing diagram of a display panel according to an embodiment of the present application.
  • FIG. 16 is another timing diagram of the display panel provided by the embodiment of the present application.
  • this embodiment provides a pixel circuit, which includes a writing module 30 , a dumping module 90 , a first time-sharing transmission module 80 , a driver
  • the module 10 the second time-sharing transmission module 50 and the storage module 40
  • the writing module 30 is used for accessing the data signal DATA
  • the dumping module 90 is connected with the writing module 30 for storing the data signal DATA to emit light in the pixel circuit
  • the compensation signal is output in the stage
  • the first time-sharing transmission module 80 is connected with the writing module 30 and the dumping module 90 for time-sharing transmission of the data signal DATA and the compensation signal
  • the input end of the driving module 10 is connected to the first time-sharing transmission module
  • the output end of 80 is connected
  • the input end of the second time-sharing transmission module 50 is connected with the output end of the driving module 10 for time-sharing transmission of the data signal DATA and the compensation signal
  • the storage module 40 is connected with the control end of the driving module 10 and the second The
  • the storage module 40 and the dumping module 90 can be charged at the same time through the data signal DATA, and the dumping module 90 can pass through the first time-sharing transmission module 80 and the driving module in the light-emitting stage. 10 and the second time-sharing transmission module 50 recharge the storage module 40 , which is beneficial to maintain the potential of the control terminal of the driving module 10 .
  • the pixel circuit further includes a light-emitting control module 20; the light-emitting control module 20 is connected to the driving module 10, and is used to control the light-emitting circuit of the pixel circuit on and off according to the light-emitting control signal EM(N); in the light-emitting stage, When the light-emitting control signal EM(N) controls the light-emitting control module 20 to be in an off state, the pixel circuit controls the compensation signal to be written to the storage module 40 .
  • the lighting control module 20 includes a first lighting control transistor T5 and a second lighting control transistor T6; one of the source/drain of the first lighting control transistor T5 is connected to the second terminal of the storage capacitor Cst ; The other one of the source/drain of the first light-emitting control transistor T5 is connected to one of the source/drain of the driving transistor T1; the gate of the first light-emitting control transistor T5 is used to access the light-emitting control signal EM ( N); one of the source/drain of the second light-emitting control transistor T6 is connected to the other of the source/drain of the driving transistor T1; the gate of the second light-emitting control transistor T6 is used to access the light-emitting control signal EM(N).
  • the write module 30 includes a write transistor T8; one of the source/drain of the write transistor T8 is used to access the data signal DATA; one of the source/drain of the write transistor T8 The other is connected to the dumping module 90 and the first time-sharing transmission module 80; the gate of the writing transistor T8 is used to access the first control signal.
  • the first control signal may be, but is not limited to, the Nth level scan signal ASCAN(N) of the A group.
  • the dumping module 90 includes a dumping capacitor C; the first end of the dumping capacitor C is connected to the other of the source/drain of the writing transistor T8; the second end of the dumping capacitor C is connected Used to access the first power signal VDD.
  • the driving module 10 includes a driving transistor T1; one of the source/drain of the driving transistor T1 is connected to the other of the source/drain of the first time-sharing transfer transistor T2; the driving transistor T1 The other one of the source/drain is connected to the input terminal of the second time-sharing transmission module 50 .
  • the storage module 40 includes a storage capacitor Cst; the first terminal of the storage capacitor Cst is connected to the gate of the driving transistor T1 ; the second terminal of the storage capacitor Cst is connected to the second terminal of the dump capacitor C.
  • the first time-sharing transmission module 80 includes a first transistor T21 and a second transistor T22; one of the source/drain of the first transistor T21 and the second transistor T22 One of the source/drain is connected to the first end of the dump capacitor C; the other of the source/drain of the first transistor T21 is connected to the other of the source/drain of the second transistor T22 and the drive
  • the input end of the module 10 is connected; the gate of the first transistor T21 is used to access the first control signal; the gate of the second transistor T22 is used to access the third control signal; in the same frame, the valid of the first control signal
  • the pulse is in the write phase and the active pulse of the third control signal is in the light phase.
  • the third control signal may be, but is not limited to, the Nth level scan signal BSCAN(N) of the B group.
  • the second time-sharing transmission module 50 includes a third transistor T31 and a fourth transistor T32; one of the source/drain of the third transistor T31 and the source/drain of the fourth transistor T32 One of the source/drain of the third transistor T31 is connected to the output terminal of the drive module 10; the other of the source/drain of the fourth transistor T32 is connected to the control terminal of the drive module 10; The gates of the three transistors T31 are used to access the first control signal; the gates of the fourth transistor T32 are used to access the third control signal.
  • the pixel circuit may further include a first reset module 60 ; the input terminal of the first reset module 60 is used to access the reset signal VI; the output terminal of the first reset module 60 and the control terminal of the driving module 10 connection; the control terminal of the first reset module 60 is used to access the fourth control signal.
  • the fourth control signal may be, but is not limited to, the N-1 th level scan signal of the A group, the N-1 th level scan signal ASCAN(N-1) of the A group.
  • the first reset module 60 includes a first reset transistor T4; one of the source/drain of the first reset transistor T4 is used to access the reset signal VI; the other one of the source/drain of the first reset transistor T4 is connected to the reset signal VI.
  • the gate of the driving transistor T1 is connected; the gate of the first reset transistor T4 is used to access the fourth control signal.
  • the pixel circuit may further include a second reset module 70; the input terminal of the second reset module 70 is used to connect to the reset signal VI; the output terminal of the second reset module 70 is connected to the anode of the light emitting device LED ; The control terminal of the second reset module 70 is used to access the first control signal.
  • the second reset module 70 includes a second reset transistor T7; one of the source/drain of the second reset transistor T7 is used to access the reset signal VI; the other source/drain of the second reset transistor T7 One is connected to the anode of the light-emitting device LED; the gate of the second reset transistor T7 is used to access the first control signal.
  • the pixel circuit may further include a light emitting device LED; the anode of the light emitting device LED is connected with the other one of the source/drain of the second light emitting control transistor T6; the cathode of the light emitting device LED is used for connecting the first Two power supply signals VSS.
  • the light-emitting device LED can be, but is not limited to, an organic light-emitting diode (OLED, Organic Light-Emitting Diode), a Mini-LED, and a Micro-LED.
  • OLED Organic Light-Emitting Diode
  • Mini-LED Mini-LED
  • Micro-LED Micro-LED
  • the transistors in the above embodiments may be, but are not limited to, P-channel thin film transistors, and may also be N-channel thin film transistors.
  • the transistors in the above embodiments may be, but are not limited to, polysilicon thin film transistors, and may specifically be low temperature polysilicon thin film transistors.
  • At least one of the first reset transistor T4, the third transistor T31, the fourth transistor T32 and the first time-sharing transfer transistor T2 may also be an oxide transistor, specifically a metal oxide transistor. In this way, the gate leakage current of the driving transistor T1 can be further reduced.
  • the working stage of the pixel circuit in one frame time T may include:
  • the first stage S1 is the reset stage: the N-1 stage scan signal of group A is set to a low potential, the first reset transistor T4 is turned on, and the gate potential of the driving transistor T1 is reset to the potential of the reset signal VI.
  • the second stage S21 is the writing stage: as shown in FIG. 6 , the Nth level scan signal of group A is set to a low potential, and the data signal DATA charges the dump capacitor C through the writing transistor T8; at the same time, the data signal DATA passes through the The first transistor T21, the driving transistor T1 and the third transistor T31 charge the storage capacitor Cst.
  • the path for the data signal DATA to simultaneously charge the dump capacitor C and the storage capacitor Cst is shown by the dotted arrow line in FIG. 6 .
  • the first reset transistor T4 , the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are all in the off state.
  • the cross X in FIG. 6 can indicate that the corresponding thin film transistor is in the off state. .
  • the third stage S31 is the first light-emitting stage: it should be noted that the working stage of the pixel circuit in each frame may include a light-emitting stage, and each light-emitting stage may include a first light-emitting stage, a dumping stage, and a second light-emitting stage .
  • the light-emitting control signal EM(N) is set to a low potential, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the light-emitting device LED emits light.
  • the fourth stage S22 is the transfer stage: it can be understood that the fourth stage S22 belongs to a part of the light-emitting stage, and is between the beginning and the end of the light-emitting stage.
  • the light-emitting control signal EM(N) is set to a high potential
  • the Nth level scan signal of group B is set to a low potential.
  • the electrical signal in the dump capacitor C passes through the second transistor T22 and the drive transistor in turn.
  • T1 and the fourth transistor T32 recharge the storage capacitor Cst.
  • the path from the dump capacitor C to dump the electrical signal to the storage capacitor Cst is shown by the dotted arrow line in FIG. 7 .
  • the writing transistor T8, the first reset transistor T4, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are all turned off, as indicated by the cross X in FIG. 7 .
  • the corresponding thin film transistors are in an off state.
  • the fifth stage S32 is the second light-emitting stage: the light-emitting control signal EM(N) is set to a low potential, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the light-emitting device LED emits light.
  • the first time-sharing transmission module 80 includes a first time-sharing transmission transistor T2; one of the source/drain of the first time-sharing transmission transistor T2 and the dump capacitor C
  • the first end of the first time-sharing transmission transistor T2 is connected to the other one of the source/drain electrodes of the first time-sharing transmission transistor T2 and the driving module 10; the gate of the first time-sharing transmission transistor T2 is used to access the second control signal;
  • the number of valid pulses of the first control signal is less than the number of valid pulses of the second control signal, and at least one valid pulse of the second control signal is the same as the valid pulse of the first control signal.
  • both the valid pulse of the first control signal and or the valid pulse of the second control signal can control the corresponding thin film transistors to be turned on, so as to form a transmission path.
  • the first control signal and the second control signal have valid pulses at the same time, and the data signal DATA can be written to the dump capacitor C and the storage capacitor Cst at the same time.
  • the fourth stage S22 the first control signal has no valid pulse, the data signal DATA cannot be written into the dump capacitor C and the storage capacitor Cst, but the second control signal can have a valid pulse, at this time, the dump capacitor C The storage capacitor Cst can be recharged in the same frame.
  • the second time-sharing transmission module 50 includes a second time-sharing transmission transistor T3; one of the source/drain of the second time-sharing transmission transistor T3 and the source/drain of the driving transistor T1 The other one of the source/drain of the second time-division transmission transistor T3 is connected to the gate of the driving transistor T1; the gate of the second time-division transmission transistor T3 is used to access the second control signal.
  • the second control signal may be, but is not limited to, another type of N-th scan signal BSCAN(N) of group B, and the second control signal is different from the third control signal.
  • the working stage of the pixel circuit in one frame time T may include:
  • the first stage S1 is the reset stage: the N-1 stage scan signal of group A is set to a low potential, the first reset transistor T4 is turned on, and the gate potential of the driving transistor T1 is reset to the potential of the reset signal VI.
  • the second stage S21 is the writing stage: as shown in FIG. 10 , the N-th scan signal of group A and the N-th level scan signal of group B are set to low potential at the same time, and the data signal DATA passes the writing transistor T8 to the dump capacitor C. At the same time, the data signal DATA sequentially passes through the first time-division transfer transistor T2, the driving transistor T1 and the second time-division transmission transistor T3 to charge the storage capacitor Cst. The path for the data signal DATA to simultaneously charge the dump capacitor C and the storage capacitor Cst is shown by the dotted arrow line in FIG. 10 .
  • the first reset transistor T4, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are all in the off state.
  • the cross X in FIG. 10 can indicate that the corresponding thin film transistor is in the off state. .
  • the third stage S31 is the first light-emitting stage: it should be noted that the working stage of the pixel circuit in each frame may include a light-emitting stage, and each light-emitting stage may include a first light-emitting stage, a dumping stage, and a second light-emitting stage .
  • the light-emitting control signal EM(N) is set to a low potential, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the light-emitting device LED emits light.
  • the fourth stage S22 is the transfer stage: it can be understood that the fourth stage S22 belongs to a part of the light-emitting stage, and is between the beginning and the end of the light-emitting stage.
  • the light-emitting control signal EM(N) is set to a high potential
  • the Nth level scan signal of group B is set to a low potential.
  • the electrical signal in the dump capacitor C passes through the first time-sharing transfer transistor T2 in sequence. , the drive transistor T1 and the second time-division transfer transistor T3 to recharge the storage capacitor Cst.
  • the path from the dump capacitor C to dump the electrical signal to the storage capacitor Cst is shown by the dotted arrow line in FIG. 11 .
  • the writing transistor T8, the first reset transistor T4, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are all turned off, as indicated by the cross X in FIG. 11 .
  • the corresponding thin film transistors are in an off state.
  • the fifth stage S32 is the second light-emitting stage: the light-emitting control signal EM(N) is set to a low potential, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the light-emitting device LED emits light.
  • the luminance difference of the pixel circuit in one frame time T is ⁇ L1; while in this embodiment, the luminance difference of the pixel circuit in one frame time T is ⁇ L2, because the one frame time
  • the storage capacitor Cst is recharged in T, which can compensate the gate leakage current of the driving transistor T1, so ⁇ L2 is significantly smaller than ⁇ L1.
  • this embodiment provides a pixel circuit, which includes a first power supply line, a second power supply line, a light-emitting device LED, a driving transistor T1, a writing transistor T8, a dump capacitor C, and a first switching transistor; a light-emitting device
  • the LED is connected in series between the first power line and the second power line
  • the driving transistor T1 is connected in series between the first power line and the second power line
  • the storage capacitor Cst is electrically connected to the gate of the driving transistor T1
  • the writing transistor One of the source/drain of T8 is electrically connected to the storage capacitor Cst, and the other of the source/drain of the write transistor T8 is used to access the data signal DATA
  • the dump capacitor C is connected to the source of the write transistor T8 One of the electrode/drain is electrically connected
  • one of the source/drain of the first switching transistor is electrically connected to the dump capacitor C and one of the source/drain of the writing transistor T8, and the first switching transistor is The other of the
  • the data signal DATA can charge the dump capacitor C through the writing transistor T8, and the data signal DATA is electrically connected to the storage capacitor Cst through the writing transistor T8, the first switching transistor, and the driving transistor T1
  • the storage capacitor Cst can be charged at the same time, and the dump capacitor C can be electrically connected to the storage capacitor Cst through the first switching transistor and the driving transistor T1 to be recharged in the same frame, which is beneficial to maintain the gate potential of the driving transistor T1.
  • the first power supply line may be used to transmit one of the first power supply signal VDD and the second power supply signal VSS.
  • the second power supply line may be used to transmit the other of the first power supply signal VDD and the second power supply signal VSS.
  • the first switching transistor may be, but is not limited to, the first time-sharing transfer transistor T2, may also be the first transistor T21, or may be a thin film transistor.
  • the pixel circuit further includes a second switch transistor; one of the source/drain of the second switch transistor is electrically connected to the other of the source/drain of the driving transistor T1; the second switch transistor The other one of the source/drain of the capacitor is electrically connected to the storage capacitor Cst and the gate of the driving transistor T1.
  • the second switching transistor may be, but not limited to, the second time-sharing transfer transistor T3, may also be the third transistor T31, or may be a thin film transistor.
  • the gate of the writing transistor T8 is used to connect the first control signal; the gate of the first switch transistor is used to connect the second control signal; the gate of the second switch transistor is used to connect The second control signal; in the same frame, the number of valid pulses of the first control signal is smaller than the number of valid pulses of the second control signal, and at least one valid pulse of the second control signal is the same as the valid pulse of the first control signal.
  • the pixel circuit further includes a third switch transistor; one of the source/drain of the third switch transistor is electrically connected to one of the source/drain of the first switch transistor; the third switch transistor The other of the source/drain of the first switching transistor is electrically connected with the other of the source/drain of the first switching transistor.
  • the third switching transistor may be, but not limited to, the second transistor T22, and may also be a thin film transistor.
  • the pixel circuit further includes a fourth switch transistor; one of the source/drain of the fourth switch transistor is electrically connected to one of the source/drain of the second switch transistor; the fourth switch transistor The other of the source/drain of the second switching transistor is electrically connected with the other of the source/drain of the second switching transistor.
  • the third switching transistor may be, but not limited to, the fourth transistor T32, and may also be a thin film transistor.
  • the gate of the writing transistor T8 is used to connect the first control signal; the gate of the first switch transistor is used to connect the first control signal; the gate of the second switch transistor is used to connect The first control signal; the gate of the third switch transistor is used to access the third control signal; the gate of the fourth switch transistor is used to access the third control signal; in the same frame, the effective pulse of the first control signal is located at In the writing phase, the active pulse of the third control signal is in the light-emitting phase.
  • the pixel circuit further includes a first light emission control transistor T5; one of the source/drain of the first light emission control transistor T5 and one of the source/drain of the driving transistor T1 and a first switch The other one of the source/drain of the transistor is electrically connected; the gate of the first light-emitting control transistor T5 is used to access the light-emitting control signal EM(N).
  • the pixel circuit further includes a second light-emitting control transistor T6; one of the source/drain of the second light-emitting control transistor T6 and the other of the source/drain of the driving transistor T1 and the second One of the source/drain of the switching transistor is electrically connected; the gate of the second light-emitting control transistor T6 is used to access the light-emitting control signal EM(N).
  • the present application provides a driving method of a pixel circuit.
  • the working stage of the pixel circuit includes at least a writing stage and a light-emitting stage;
  • the pixel circuit includes a storage module 40 and a dump module 90;
  • the driving method includes: providing a The pixel circuit and a data signal DATA; in the writing phase, the pixel circuit synchronously writes the data signal DATA to the storage module 40 and the dumping module 90; and in the light-emitting stage, the pixel circuit outputs the electrical signal in the dumping module 90 to storage module 40.
  • the storage module 40 and the dumping module 90 can be charged at the same time through the data signal DATA, and the dumping module 90 can recharge the storage module 40 in the light-emitting phase, which is beneficial to maintaining The potential of the control terminal of the driving module 10 .
  • the present application provides a display panel, which includes the pixel circuit in any of the above embodiments.
  • the storage module 40 and the dumping module 90 can be charged at the same time through the data signal DATA, and the dumping module 90 can pass through the first time-sharing transmission module 80 and the driving module in the light-emitting stage. 10 and the second time-sharing transmission module 50 recharge the storage module 40 , which is beneficial to maintain the potential of the control terminal of the driving module 10 .
  • the above-mentioned display panel may further include a first GOA (Gate On Array, an array substrate row drive) circuit and a second GOA circuit; wherein, the first GOA circuit can be used to output group A scan signals, and the second GOA circuit can be used to output group B scan signals.
  • first GOA Gate On Array, an array substrate row drive
  • the first GOA circuit may include multiple cascaded first GOA units.
  • the first-level scan signal ASCAN(1) of group A output by the first-level first GOA unit may be used as the first-level scan signal ASCAN(1).
  • the input signal of the second-level first GOA unit; the second-level scan signal ASCAN(2) of group A output by the second-level first GOA unit can be used as the input signal of the third-level first GOA unit; the third-level first GOA unit
  • the outputted third-level scan signal ASCAN(3) of group A can be used as the input signal of the fourth-level first GOA unit; the N-1th level scan signal ASCAN(N-1) of group A can be used as the Nth-level first GOA unit
  • the first GOA unit of the Nth stage outputs the corresponding Nth stage scan signal ASCAN(N) of the A group.
  • the first GOA units of odd-numbered stages are connected to the clock signal CK, and the first GOA units of even-numbered stages are connected to the clock signal XCK.
  • the first GOA unit of the first stage can access the group A initial signal A-STV.
  • the first GOA unit of any level needs to be connected to the corresponding high-potential VGH and low-potential VGL.
  • the high-potential VGH can turn on the corresponding thin film transistor, and the low-potential VGL can turn off the corresponding thin-film transistor.
  • the high potential VGH can turn off the corresponding thin film transistor, and the low potential VGL can turn on the corresponding thin film transistor.
  • the second GOA circuit may include a plurality of cascaded second GOA units.
  • the first-level scan signal BSCAN(1) of group B output by the first-level second GOA unit may be used as the second level The input signal of the second GOA unit;
  • the second-level scan signal BSCAN(2) of group B output by the second-level second GOA unit can be used as the input signal of the third-level second GOA unit;
  • the third-level scan signal BSCAN(3) of group B can be used as the input signal of the fourth-level second GOA unit;
  • the N-1th-level scan signal BSCAN(N-1) of group B can be used as the input of the Nth-level second GOA unit signal, at the same time, the second GOA unit of the Nth stage outputs the corresponding scan signal BSCAN(N) of the Nth stage of the B group.
  • the first GOA unit or the second GOA unit of any level needs to be connected to the corresponding high-potential VGH and low-potential VGL, the high-potential VGH can turn on the corresponding thin film transistor, and the low-potential VGL can turn off the corresponding thin film transistor.
  • the second GOA units of odd-numbered stages are connected to the clock signal XCK, and the second GOA units of even-numbered stages are connected to the clock signal CK.
  • the first-level second GOA unit can access the B-group initial signal B-STV.
  • the first GOA circuit can generate the corresponding group A scan signals under the control of the group A initial signal A-STV, the clock signal CK and the clock signal XCK.
  • the second GOA circuit can generate the corresponding scan signal of the B group under the control of the B group initial signal B-STV, the clock signal CK and the clock signal XCK.
  • the light-emitting driving circuit can generate a corresponding light-emitting control signal, eg, the first-level light-emitting control signal EM( 1 ), under the control of the light-emitting initial signal EM-STV, the clock signal CK, and the clock signal XCK.
  • the first reset transistor T4 When the first-stage scan signal ASCAN( 1 ) of the group A is at a low potential, the first reset transistor T4 is turned on to reset the gate potential of the driving transistor T1 .
  • the data signal DATA is simultaneously written into the dump capacitor C and the storage capacitor Cst.
  • the first-level scan signal BSCAN(1) of group B is output by the first-level second GOA unit.
  • the electrical signal in the dump capacitor C recharges the storage capacitor Cst.
  • the writing of the data signal DATA may be performed during 0.25 ⁇ 0.75T of one frame time T, and the recharging may be performed during 0.5 ⁇ 1T of one frame time T.
  • the first GOA circuit can generate the corresponding group A scan signals under the control of the group A initial signal A-STV, the clock signal CK and the clock signal XCK.
  • the second GOA circuit can generate the corresponding scan signal of the B group under the control of the B group initial signal B-STV, the clock signal CK and the clock signal XCK.
  • the light-emitting driving circuit can generate a corresponding light-emitting control signal, eg, the first-level light-emitting control signal EM( 1 ), under the control of the light-emitting initial signal EM-STV, the clock signal CK, and the clock signal XCK.
  • the first reset transistor T4 When the first-stage scanning signal ASCAN(1) of group A is at a low potential, the first reset transistor T4 is turned on to reset the gate potential of the driving transistor T1, and at the same time, the first-stage scanning signal BSCAN(1) of group B is also low. potential.
  • the data signal DATA is simultaneously written into the dump capacitor C and the storage capacitor Cst.
  • the second-level scan signal BSCAN( 2 ) of the group B is at a low potential, the electrical signal in the dump capacitor C recharges the storage capacitor Cst.
  • the writing of the data signal DATA may be performed during 0.25 ⁇ 0.75T of one frame time T, and the recharging may be performed during 0.5 ⁇ 1T of one frame time T.

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Abstract

一种像素电路及显示面板，该像素电路包括写入模块(30)、转存模块(90)、第一分时传输模块(80)、驱动模块(10)、第二分时传输模块(50)以及存储模块(40)；通过数据信号(DATA)可以同时充电存储模块(40)和转存模块(90)，并在发光阶段中转存模块(90)可以通过第一分时传输模块(80)、驱动模块(10)以及第二分时传输模块(50)对存储模块(40)进行再次充电。

Description

像素电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种像素电路及显示面板。
 背景技术
传统技术方案的像素电路中驱动晶体管的栅极普遍存在漏电流的问题，致使驱动晶体管的栅极电位不容易保持，例如，如图1所示的7T1C像素电路，其工作过程可以分成如图2所示的三个主要运作阶段：
第一个阶段S1：第N-1级扫描信号SCAN(N-1) 置为低电平，晶体管T4打开，驱动晶体管T1的栅极电位复位至初始信号VI的电位。
第二个阶段S2：第N级扫描信号SCAN(N) 置为低电平，晶体管T2、晶体管T3打开，数据信号DATA依次经晶体管T2、晶体管T1以及晶体管T3将驱动晶体管T1的栅极电位充电至V DATA-Vth，其中，V DATA为数据信号DATA的电位，Vth为驱动晶体管T1的阈值电压；与此同时，晶体管T7打开，发光器件LED的阳极电位复位至初始信号VI的电位。
第三个阶段S3：发光控制信号EM（N）置为低电平，发光器件LED开始发光。
其中，第二个阶段S2中，晶体管T1~T3打开，晶体管T4~T6关闭。此时，数据信号DATA通过晶体管T1~T3路径对驱动晶体管T1的栅极电位充电。当驱动晶体管T1的栅极电位上升到V DATA-Vth，驱动晶体管T1截止，驱动晶体管T1的栅极电位不再上升。
第三个阶段S3中，像素的发光亮度直接由驱动晶体管T1的栅极电位决定，而在发光阶段T中，影响驱动晶体管T1的栅极电位的最主要因素是漏电流，将直接影响发光阶段T的亮度稳定性。如图3所示，这样会导致画面的亮度会随时间而降低，进而在一帧内的发光阶段T中存在亮度差异△L1，当该亮度差异△L1达到一定值时，人眼可感受到的画面闪烁（Flicker）。
需要注意的是，上述关于背景技术的介绍仅仅是为了便于清楚、完整地理解本申请的技术方案。因此，不能仅仅由于其出现在本申请的背景技术中，而认为上述所涉及到的技术方案为本领域所属技术人员所公知。
 技术问题
本申请提供一种像素电路及显示面板，缓解了像素电路中驱动模块的控制端电位不易保持的技术问题。
 技术解决方案
第一方面，本申请提供一种像素电路，其包括第一电源线、第二电源线、发光器件、驱动晶体管、写入晶体管、转存电容以及第一开关晶体管；串接于第一电源线与第二电源线之间的发光器件和驱动晶体管；存储电容与驱动晶体管的栅极电连接；写入晶体管的源极/漏极中的一个与存储电容电连接，写入晶体管的源极/漏极中的另一个用于接入数据信号；转存电容与写入晶体管的源极/漏极中的一个电连接；第一开关晶体管的源极/漏极中的一个与转存电容和写入晶体管的源极/漏极中的一个电连接，第一开关晶体管的源极/漏极中的另一个与驱动晶体管的源极/漏极中的一个电连接。
在其中一些实施方式中，像素电路还包括第二开关晶体管；第二开关晶体管的源极/漏极中的一个与驱动晶体管的源极/漏极中的另一个电连接；第二开关晶体管的源极/漏极中的另一个与存储电容和驱动晶体管的栅极电连接。
在其中一些实施方式中，写入晶体管的栅极用于接入第一控制信号；第一开关晶体管的栅极用于接入第二控制信号；第二开关晶体管的栅极用于接入第二控制信号；在同一帧中，第一控制信号的有效脉冲数量小于第二控制信号的有效脉冲数量，且第二控制信号中至少一个有效脉冲与第一控制信号的有效脉冲相同。
在其中一些实施方式中，像素电路还包括第三开关晶体管；第三开关晶体管的源极/漏极中的一个与第一开关晶体管的源极/漏极中的一个电连接；第三开关晶体管的源极/漏极中的另一个与第一开关晶体管的源极/漏极中的另一个电连接。
在其中一些实施方式中，像素电路还包括第四开关晶体管；第四开关晶体管的源极/漏极中的一个与第二开关晶体管的源极/漏极中的一个电连接；第四开关晶体管的源极/漏极中的另一个与第二开关晶体管的源极/漏极中的另一个电连接。
在其中一些实施方式中，像素电路的工作阶段包括写入阶段和发光阶段；写入晶体管的栅极用于接入第一控制信号；第一开关晶体管的栅极用于接入第一控制信号；第二开关晶体管的栅极用于接入第一控制信号；第三开关晶体管的栅极用于接入第三控制信号；第四开关晶体管的栅极用于接入第三控制信号；在同一帧中，第一控制信号的有效脉冲位于写入阶段中，第三控制信号的有效脉冲位于发光阶段中。
在其中一些实施方式中，像素电路还包括第一发光控制晶体管；第一发光控制晶体管的源极/漏极中的一个与驱动晶体管的源极/漏极中的一个和第一开关晶体管的源极/漏极中的另一个电连接；第一发光控制晶体管的栅极用于接入发光控制信号。
在其中一些实施方式中，像素电路还包括第二发光控制晶体管；第二发光控制晶体管的源极/漏极中的一个与驱动晶体管的源极/漏极中的另一个和第二开关晶体管的源极/漏极中的一个电连接；第二发光控制晶体管的栅极用于接入发光控制信号。
第二方面，本申请提供一种像素电路，其包括写入模块、转存模块、第一分时传输模块、驱动模块、第二分时传输模块以及存储模块；写入模块用于接入数据信号；转存模块与写入模块连接，用于存储数据信号以在像素电路的发光阶段中输出补偿信号；第一分时传输模块与写入模块和转存模块连接，用于分时传输数据信号和补偿信号；驱动模块的输入端与第一分时传输模块的输出端连接；第二分时传输模块的输入端与驱动模块的输出端连接，用于分时传输数据信号和补偿信号；存储模块与驱动模块的控制端和第二分时传输模块的输出端连接，用于在同一帧中分时存储数据信号和补偿信号，以在发光阶段中维持驱动模块的控制端电位。
在其中一些实施方式中，像素电路还包括发光控制模块；发光控制模块与驱动模块连接，用于根据发光控制信号通断控制像素电路的发光回路；在发光阶段中，发光控制信号控制发光控制模块处于断开状态期间，像素电路控制补偿信号写入至存储模块。
在其中一些实施方式中，写入模块包括写入晶体管；写入晶体管的源极/漏极中的一个用于接入数据信号；写入晶体管的源极/漏极中的另一个与转存模块和第一分时传输模块连接；写入晶体管的栅极用于接入第一控制信号。
在其中一些实施方式中，转存模块包括转存电容；转存电容的第一端与写入晶体管的源极/漏极中的另一个连接；转存电容的第二端用于接入第一电源信号。
在其中一些实施方式中，第一分时传输模块包括第一分时传输晶体管；第一分时传输晶体管的源极/漏极中的一个与转存电容的第一端连接；第一分时传输晶体管的源极/漏极中的另一个与驱动模块连接；第一分时传输晶体管的栅极用于接入第二控制信号；在同一帧中，第一控制信号的有效脉冲数量小于第二控制信号的有效脉冲数量，且第二控制信号中至少一个有效脉冲与第一控制信号的有效脉冲相同。
在其中一些实施方式中，驱动模块包括驱动晶体管；驱动晶体管的源极/漏极中的一个与第一分时传输晶体管的源极/漏极中的另一个连接；驱动晶体管的源极/漏极中的另一个与第二分时传输模块的输入端连接。
在其中一些实施方式中，第二分时传输模块包括第二分时传输晶体管；第二分时传输晶体管的源极/漏极中的一个与驱动晶体管的源极/漏极中的另一个连接；第二分时传输晶体管的源极/漏极中的另一个与驱动晶体管的栅极连接；第二分时传输晶体管的栅极用于接入第二控制信号。
在其中一些实施方式中，存储模块包括存储电容；存储电容的第一端与驱动晶体管的栅极连接；存储电容的第二端与转存电容的第二端连接。
在其中一些实施方式中，发光控制模块包括第一发光控制晶体管和第二发光控制晶体管；第一发光控制晶体管的源极/漏极中的一个与存储电容的第二端连接；第一发光控制晶体管的源极/漏极中的另一个与驱动晶体管的源极/漏极中的一个连接；第一发光控制晶体管的栅极用于接入发光控制信号；第二发光控制晶体管的源极/漏极中的一个与驱动晶体管的源极/漏极中的另一个连接；第二发光控制晶体管的栅极用于接入发光控制信号。
在其中一些实施方式中，第一分时传输模块包括第一晶体管和第二晶体管；第一晶体管的源极/漏极中的一个与第二晶体管的源极/漏极中的一个和转存电容的第一端连接；第一晶体管的源极/漏极中的另一个与第二晶体管的源极/漏极中的另一个和驱动模块的输入端连接；第一晶体管的栅极用于接入第一控制信号；第二晶体管的栅极用于接入第三控制信号；在同一帧中，第一控制信号的有效脉冲位于写入阶段中，第三控制信号的有效脉冲位于发光阶段中。
在其中一些实施方式中，第二分时传输模块包括第三晶体管和第四晶体管；第三晶体管的源极/漏极中的一个与第四晶体管的源极/漏极中的一个和驱动模块的输出端连接；第三晶体管的源极/漏极中的另一个与第四晶体管的源极/漏极中的另一个和驱动模块的控制端连接；第三晶体管的栅极用于接入第一控制信号；第四晶体管的栅极用于接入第三控制信号。
第三方面，本申请提供一种显示面板，其包括上述任一实施方式中的像素电路。
 有益效果
本申请提供的像素电路及显示面板，通过数据信号可以同时充电存储模块和转存模块，并在发光阶段中转存模块可以通过第一分时传输模块、驱动模块以及第二分时传输模块对存储模块进行再次充电，有利于维持驱动模块的控制端电位。
 附图说明
图1为传统技术方案中像素电路的结构示意图。
图2为图1中像素电路的时序示意图。
图3为图1中像素电路在一帧的发光阶段中的亮度差异。
图4为本申请实施例提供的像素电路的一种结构示意图。
图5为图4中像素电路的时序示意图。
图6为图4中像素电路的写入阶段的工作示意图。
图7为图4中像素电路的转存阶段的工作示意图。
图8为本申请实施例提供的像素电路的另一种结构示意图。
图9为图8中像素电路的时序示意图。
图10为图8中像素电路的写入阶段的工作示意图。
图11为图8中像素电路的转存阶段的工作示意图。
图12为不同像素电路的亮度差异对比示意图。
图13为本申请实施例提供的GOA电路的一种结构示意图。
图14为本申请实施例提供的GOA电路的另一种结构示意图。
图15为本申请实施例提供的显示面板的一种时序示意图。
图16为本申请实施例提供的显示面板的另一种时序示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
请参阅图4至图16，如图4和/或图8所示，本实施例提供了一种像素电路，其包括写入模块30、转存模块90、第一分时传输模块80、驱动模块10、第二分时传输模块50以及存储模块40；写入模块30用于接入数据信号DATA；转存模块90与写入模块30连接，用于存储数据信号DATA以在像素电路的发光阶段中输出补偿信号；第一分时传输模块80与写入模块30和转存模块90连接，用于分时传输数据信号DATA和补偿信号；驱动模块10的输入端与第一分时传输模块80的输出端连接；第二分时传输模块50的输入端与驱动模块10的输出端连接，用于分时传输数据信号DATA和补偿信号；存储模块40与驱动模块10的控制端和第二分时传输模块50的输出端连接，用于在同一帧中分时存储数据信号DATA和补偿信号，以在发光阶段中维持驱动模块10的控制端电位。
可以理解的是，本实施例提供的像素电路，通过数据信号DATA可以同时充电存储模块40和转存模块90，并在发光阶段中转存模块90可以通过第一分时传输模块80、驱动模块10以及第二分时传输模块50对存储模块40进行再次充电，有利于维持驱动模块10的控制端电位。
在其中一个实施例中，像素电路还包括发光控制模块20；发光控制模块20与驱动模块10连接，用于根据发光控制信号EM（N）通断控制像素电路的发光回路；在发光阶段中，发光控制信号EM（N）控制发光控制模块20处于断开状态期间，像素电路控制补偿信号写入至存储模块40。
在其中一个实施例中，发光控制模块20包括第一发光控制晶体管T5和第二发光控制晶体管T6；第一发光控制晶体管T5的源极/漏极中的一个与存储电容Cst的第二端连接；第一发光控制晶体管T5的源极/漏极中的另一个与驱动晶体管T1的源极/漏极中的一个连接；第一发光控制晶体管T5的栅极用于接入发光控制信号EM（N）；第二发光控制晶体管T6的源极/漏极中的一个与驱动晶体管T1的源极/漏极中的另一个连接；第二发光控制晶体管T6的栅极用于接入发光控制信号EM（N）。
在其中一个实施例中，写入模块30包括写入晶体管T8；写入晶体管T8的源极/漏极中的一个用于接入数据信号DATA；写入晶体管T8的源极/漏极中的另一个与转存模块90和第一分时传输模块80连接；写入晶体管T8的栅极用于接入第一控制信号。
其中，第一控制信号可以但不限于为A组第N级扫描信号ASCAN（N）。
在其中一个实施例中，转存模块90包括转存电容C；转存电容C的第一端与写入晶体管T8的源极/漏极中的另一个连接；转存电容C的第二端用于接入第一电源信号VDD。
在其中一个实施例中，驱动模块10包括驱动晶体管T1；驱动晶体管T1的源极/漏极中的一个与第一分时传输晶体管T2的源极/漏极中的另一个连接；驱动晶体管T1的源极/漏极中的另一个与第二分时传输模块50的输入端连接。
在其中一个实施例中，存储模块40包括存储电容Cst；存储电容Cst的第一端与驱动晶体管T1的栅极连接；存储电容Cst的第二端与转存电容C的第二端连接。
如图4所示，在其中一个实施例中，第一分时传输模块80包括第一晶体管T21和第二晶体管T22；第一晶体管T21的源极/漏极中的一个与第二晶体管T22的源极/漏极中的一个和转存电容C的第一端连接；第一晶体管T21的源极/漏极中的另一个与第二晶体管T22的源极/漏极中的另一个和驱动模块10的输入端连接；第一晶体管T21的栅极用于接入第一控制信号；第二晶体管T22的栅极用于接入第三控制信号；在同一帧中，第一控制信号的有效脉冲位于写入阶段中，第三控制信号的有效脉冲位于发光阶段中。
其中，第三控制信号可以但不限于为B组第N级扫描信号BSCAN（N）。
在其中一个实施例中，第二分时传输模块50包括第三晶体管T31和第四晶体管T32；第三晶体管T31的源极/漏极中的一个与第四晶体管T32的源极/漏极中的一个和驱动模块10的输出端连接；第三晶体管T31的源极/漏极中的另一个与第四晶体管T32的源极/漏极中的另一个和驱动模块10的控制端连接；第三晶体管T31的栅极用于接入第一控制信号；第四晶体管T32的栅极用于接入第三控制信号。
在其中一个实施例中，该像素电路还可以包括第一复位模块60；第一复位模块60的输入端用于接入复位信号VI；第一复位模块60的输出端与驱动模块10的控制端连接；第一复位模块60的控制端用于接入第四控制信号。
其中，第四控制信号可以但不限于为A组第N-1级扫描信号A组第N-1级扫描信号ASCAN（N-1）。第一复位模块60包括第一复位晶体管T4；第一复位晶体管T4的源极/漏极中的一个用于接入复位信号VI；第一复位晶体管T4的源极/漏极中的另一个与驱动晶体管T1的栅极连接；第一复位晶体管T4的栅极用于接入第四控制信号。
在其中一个实施例中，该像素电路还可以包括第二复位模块70；第二复位模块70的输入端用于接入复位信号VI；第二复位模块70的输出端与发光器件LED的阳极连接；第二复位模块70的控制端用于接入第一控制信号。
其中，第二复位模块70包括第二复位晶体管T7；第二复位晶体管T7的源极/漏极中的一个用于接入复位信号VI；第二复位晶体管T7的源极/漏极中的另一个与发光器件LED的阳极连接；第二复位晶体管T7的栅极用于接入第一控制信号。
在其中一个实施例中，该像素电路还可以包括发光器件LED；发光器件LED的阳极与第二发光控制晶体管T6的源极/漏极中的另一个链接；发光器件LED的阴极用于连接第二电源信号VSS。
其中，第一电源信号VDD的电位高于第二电源信号VSS的电位。发光器件LED可以但不限于为有机发光二极体（OLED，Organic Light-Emitting Diode），也可以为Mini-LED，还可以为Micro-LED。
在其中一个实施例中，上述实施例中的晶体管可以但不限于为P沟道型薄膜晶体管，还可以是N沟道型薄膜晶体管。
在其中一个实施例中，上述实施例中的晶体管可以但不限于为多晶硅薄膜晶体管，具体还可以是低温多晶硅薄膜晶体管。
其中，第一复位晶体管T4、第三晶体管T31、第四晶体管T32以及第一分时传输晶体管T2中的至少一个还可以为氧化物晶体管，具体也可以为金属氧化物晶体管。这样可以进一步降低驱动晶体管T1的栅极漏电流。
如图5至图7所示，在其中一个实施例中，上述像素电路在一帧时间T内的工作阶段可以包括：
第一阶段S1即复位阶段：A组第N-1级扫描信号置为低电位，第一复位晶体管T4打开，将驱动晶体管T1的栅极电位复位至复位信号VI的电位。
第二阶段S21即写入阶段：如图6所示，A组第N级扫描信号置为低电位，数据信号DATA通过写入晶体管T8对转存电容C进行充电；同时，数据信号DATA依次经过第一晶体管T21、驱动晶体管T1以及第三晶体管T31对存储电容Cst进行充电。其中，数据信号DATA同时充电转存电容C和存储电容Cst的路径如图6中箭头虚线所示。在第二阶段S21中，第一复位晶体管T4、第一发光控制晶体管T5以及第二发光控制晶体管T6均处于关断状态，如图6中的叉号X可以表征对应的薄膜晶体管处于关断状态。
第三阶段S31即第一发光阶段：需要进行说明的是，上述像素电路在每帧中的工作阶段可以包括发光阶段，每个发光阶段可以包括第一发光阶段、转存阶段以及第二发光阶段。发光控制信号EM（N）置为低电位，第一发光控制晶体管T5和第二发光控制晶体管T6打开，发光器件LED进行发光。
第四阶段S22即转存阶段：可以理解的是，第四阶段S22属于发光阶段的一部分，且处于发光阶段的起始与结尾之间。发光控制信号EM（N）置为高电位，B组第N级扫描信号置为低电位，此时，如图7所示，转存电容C中的电信号依次经过第二晶体管T22、驱动晶体管T1以及第四晶体管T32对存储电容Cst进行再次充电。转存电容C转存电信号至存储电容Cst的路径如图7中的箭头虚线所示。此时，在第四阶段S22中，写入晶体管T8、第一复位晶体管T4、第一发光控制晶体管T5以及第二发光控制晶体管T6均处于关断状态，如图7中的叉号X可以表征对应的薄膜晶体管处于关断状态。
第五阶段S32即第二发光阶段：发光控制信号EM（N）置为低电位，第一发光控制晶体管T5和第二发光控制晶体管T6打开，发光器件LED进行发光。
如图8所示，在其中一个实施例中，第一分时传输模块80包括第一分时传输晶体管T2；第一分时传输晶体管T2的源极/漏极中的一个与转存电容C的第一端连接；第一分时传输晶体管T2的源极/漏极中的另一个与驱动模块10连接；第一分时传输晶体管T2的栅极用于接入第二控制信号；在同一帧中，第一控制信号的有效脉冲数量小于第二控制信号的有效脉冲数量，且第二控制信号中至少一个有效脉冲与第一控制信号的有效脉冲相同。
可以理解的是，第一控制信号的有效脉冲和或第二控制信号的有效脉冲均可以控制对应的薄膜晶体管打开，以形成传输路径。在第二阶段S21中，第一控制信号、第二控制信号同时具有有效脉冲，可以将数据信号DATA同时写入至转存电容C和存储电容Cst。在第四阶段S22中，第一控制信号没有有效脉冲，数据信号DATA不能够写入到转存电容C和存储电容Cst中，而第二控制信号可以具有有效脉冲，此时，转存电容C可以对存储电容Cst在同一帧中进行再次充电。
在其中一个实施例中，第二分时传输模块50包括第二分时传输晶体管T3；第二分时传输晶体管T3的源极/漏极中的一个与驱动晶体管T1的源极/漏极中的另一个连接；第二分时传输晶体管T3的源极/漏极中的另一个与驱动晶体管T1的栅极连接；第二分时传输晶体管T3的栅极用于接入第二控制信号。
其中，第二控制信号可以但不限于为另一种的B组第N级扫描信号BSCAN（N），且第二控制信号与第三控制信号不同。
如图9至图11所示，在其中一个实施例中，上述像素电路在一帧时间T内的工作阶段可以包括：
第一阶段S1即复位阶段：A组第N-1级扫描信号置为低电位，第一复位晶体管T4打开，将驱动晶体管T1的栅极电位复位至复位信号VI的电位。
第二阶段S21即写入阶段：如图10所示，A组第N级扫描信号和B组第N级扫描信号同时置为低电位，数据信号DATA通过写入晶体管T8对转存电容C进行充电；同时，数据信号DATA依次经过第一分时传输晶体管T2、驱动晶体管T1以及第二分时传输晶体管T3对存储电容Cst进行充电。其中，数据信号DATA同时充电转存电容C和存储电容Cst的路径如图10中箭头虚线所示。在第二阶段S21中，第一复位晶体管T4、第一发光控制晶体管T5以及第二发光控制晶体管T6均处于关断状态，如图10中的叉号X可以表征对应的薄膜晶体管处于关断状态。
第三阶段S31即第一发光阶段：需要进行说明的是，上述像素电路在每帧中的工作阶段可以包括发光阶段，每个发光阶段可以包括第一发光阶段、转存阶段以及第二发光阶段。发光控制信号EM（N）置为低电位，第一发光控制晶体管T5和第二发光控制晶体管T6打开，发光器件LED进行发光。
第四阶段S22即转存阶段：可以理解的是，第四阶段S22属于发光阶段的一部分，且处于发光阶段的起始与结尾之间。发光控制信号EM（N）置为高电位，B组第N级扫描信号置为低电位，此时，如图11所示，转存电容C中的电信号依次经过第一分时传输晶体管T2、驱动晶体管T1以及第二分时传输晶体管T3对存储电容Cst进行再次充电。转存电容C转存电信号至存储电容Cst的路径如图11中的箭头虚线所示。此时，在第四阶段S22中，写入晶体管T8、第一复位晶体管T4、第一发光控制晶体管T5以及第二发光控制晶体管T6均处于关断状态，如图11中的叉号X可以表征对应的薄膜晶体管处于关断状态。
第五阶段S32即第二发光阶段：发光控制信号EM（N）置为低电位，第一发光控制晶体管T5和第二发光控制晶体管T6打开，发光器件LED进行发光。
如图12所示，传统技术方案中像素电路在一帧时间T中的亮度差异为△L1；而本实施例中像素电路在一帧时间T内的亮度差异为△L2，由于在一帧时间T内对存储电容Cst进行了再次充电，可以补偿驱动晶体管T1的栅极漏电流，因此，△L2明显地小于△L1。
基于上述分析，本实施例提供一种像素电路，其包括第一电源线、第二电源线、发光器件LED、驱动晶体管T1、写入晶体管T8、转存电容C以及第一开关晶体管；发光器件LED串接于第一电源线与第二电源线之间；驱动晶体管T1串接于第一电源线与第二电源线之间；存储电容Cst与驱动晶体管T1的栅极电连接；写入晶体管T8的源极/漏极中的一个与存储电容Cst电连接，写入晶体管T8的源极/漏极中的另一个用于接入数据信号DATA；转存电容C与写入晶体管T8的源极/漏极中的一个电连接；第一开关晶体管的源极/漏极中的一个与转存电容C和写入晶体管T8的源极/漏极中的一个电连接，第一开关晶体管的源极/漏极中的另一个与驱动晶体管T1的源极/漏极中的一个电连接。
可以理解的是，在本实施例中，数据信号DATA通过写入晶体管T8可以充电转存电容C，数据信号DATA通过写入晶体管T8、第一开关晶体管、驱动晶体管T1电连接至存储电容Cst，可以同时充电存储电容Cst，且转存电容C可以通过第一开关晶体管、驱动晶体管T1电连接至存储电容Cst以在同一帧中进行再次充电，有利于维持驱动晶体管T1的栅极电位。
需要进行说明的是，第一电源线可以用于传输第一电源信号VDD和第二电源信号VSS中的一个。第二电源线可以用于传输第一电源信号VDD和第二电源信号VSS中的另一个。第一开关晶体管可以但不限于为第一分时传输晶体管T2，还可以为第一晶体管T21，也可以为一个薄膜晶体管。
在其中一个实施例中，像素电路还包括第二开关晶体管；第二开关晶体管的源极/漏极中的一个与驱动晶体管T1的源极/漏极中的另一个电连接；第二开关晶体管的源极/漏极中的另一个与存储电容Cst和驱动晶体管T1的栅极电连接。
需要进行说明的是，第二开关晶体管可以但不限于为第二分时传输晶体管T3，还可以为第三晶体管T31，也可以为一个薄膜晶体管。
在其中一个实施例中，写入晶体管T8的栅极用于接入第一控制信号；第一开关晶体管的栅极用于接入第二控制信号；第二开关晶体管的栅极用于接入第二控制信号；在同一帧中，第一控制信号的有效脉冲数量小于第二控制信号的有效脉冲数量，且第二控制信号中至少一个有效脉冲与第一控制信号的有效脉冲相同。
在其中一个实施例中，像素电路还包括第三开关晶体管；第三开关晶体管的源极/漏极中的一个与第一开关晶体管的源极/漏极中的一个电连接；第三开关晶体管的源极/漏极中的另一个与第一开关晶体管的源极/漏极中的另一个电连接。
需要进行说明的是，第三开关晶体管可以但不限于为第二晶体管T22，也可以为一个薄膜晶体管。
在其中一个实施例中，像素电路还包括第四开关晶体管；第四开关晶体管的源极/漏极中的一个与第二开关晶体管的源极/漏极中的一个电连接；第四开关晶体管的源极/漏极中的另一个与第二开关晶体管的源极/漏极中的另一个电连接。
需要进行说明的是，第三开关晶体管可以但不限于为第四晶体管T32，也可以为一个薄膜晶体管。
在其中一个实施例中，写入晶体管T8的栅极用于接入第一控制信号；第一开关晶体管的栅极用于接入第一控制信号；第二开关晶体管的栅极用于接入第一控制信号；第三开关晶体管的栅极用于接入第三控制信号；第四开关晶体管的栅极用于接入第三控制信号；在同一帧中，第一控制信号的有效脉冲位于写入阶段中，第三控制信号的有效脉冲位于发光阶段中。
在其中一个实施例中，像素电路还包括第一发光控制晶体管T5；第一发光控制晶体管T5的源极/漏极中的一个与驱动晶体管T1的源极/漏极中的一个和第一开关晶体管的源极/漏极中的另一个电连接；第一发光控制晶体管T5的栅极用于接入发光控制信号EM（N）。
在其中一个实施例中，像素电路还包括第二发光控制晶体管T6；第二发光控制晶体管T6的源极/漏极中的一个与驱动晶体管T1的源极/漏极中的另一个和第二开关晶体管的源极/漏极中的一个电连接；第二发光控制晶体管T6的栅极用于接入发光控制信号EM（N）。
在其中一个实施例中，本申请提供一种像素电路的驱动方法，像素电路的工作阶段至少包括写入阶段和发光阶段；像素电路包括存储模块40和转存模块90；驱动方法包括：提供一像素电路和一数据信号DATA；在写入阶段中，像素电路同步写入数据信号DATA至存储模块40和转存模块90；以及在发光阶段中，像素电路输出转存模块90中的电信号至存储模块40。
可以理解的是，本实施例提供的驱动方法，通过数据信号DATA可以同时充电存储模块40和转存模块90，并在发光阶段中转存模块90可以对存储模块40进行再次充电，有利于维持驱动模块10的控制端电位。
在其中一个实施例中，本申请提供一种显示面板，其包括上述任一实施例中的像素电路。
可以理解的是，本实施例提供的显示面板，通过数据信号DATA可以同时充电存储模块40和转存模块90，并在发光阶段中转存模块90可以通过第一分时传输模块80、驱动模块10以及第二分时传输模块50对存储模块40进行再次充电，有利于维持驱动模块10的控制端电位。
在其中一个实施例中，上述显示面板还可以包括第一GOA（Gate On Array，阵列基板行驱动）电路和第二GOA电路；其中，第一GOA电路可以用于输出A组扫描信号，第二GOA电路可以用于输出B组扫描信号。
其中，如图13所示，该第一GOA电路可以包括多个级联的第一GOA单元，例如，第一级第一GOA单元输出的A组第一级扫描信号ASCAN（1）可以作为第二级第一GOA单元的输入信号；第二级第一GOA单元输出的A组第二级扫描信号ASCAN（2）可以作为第三级第一GOA单元的输入信号；第三级第一GOA单元输出的A组第三级扫描信号ASCAN（3）可以作为第四级第一GOA单元的输入信号；A组第N-1级扫描信号ASCAN（N-1）可以作为第N级第一GOA单元的输入信号，同时，第N级第一GOA单元输出对应的A组第N级扫描信号ASCAN（N）。
其中，奇数级的第一GOA单元接入时钟信号CK，偶数级的第一GOA单元接入时钟信号XCK。第一级第一GOA单元可以接入A组初始信号A-STV。任一级的第一GOA单元均需接入对应的高电位VGH和低电位VGL，高电位VGH可以打开对应的薄膜晶体管，低电位VGL可以关闭对应的薄膜晶体管。或者，高电位VGH可以关闭对应的薄膜晶体管，低电位VGL可以打开对应的薄膜晶体管。
如图14所示，该第二GOA电路可以包括多个级联的第二GOA单元，例如，第一级第二GOA单元输出的B组第一级扫描信号BSCAN（1）可以作为第二级第二GOA单元的输入信号；第二级第二GOA单元输出的B组第二级扫描信号BSCAN（2）可以作为第三级第二GOA单元的输入信号；第三级第二GOA单元输出的B组第三级扫描信号BSCAN（3）可以作为第四级第二GOA单元的输入信号；B组第N-1级扫描信号BSCAN（N-1）可以作为第N级第二GOA单元的输入信号，同时，第N级第二GOA单元输出对应的B组第N级扫描信号BSCAN（N）。
其中，任一级的第一GOA单元或者第二GOA单元均需接入对应的高电位VGH和低电位VGL，高电位VGH可以打开对应的薄膜晶体管，低电位VGL可以关闭对应的薄膜晶体管。奇数级的第二GOA单元接入时钟信号XCK，偶数级的第二GOA单元接入时钟信号CK。第一级第二GOA单元可以接入B组初始信号B-STV。
在其中一个实施例中，如图15所示，第一GOA电路可以在A组初始信号A-STV、时钟信号CK以及时钟信号XCK的控制下，生成对应的A组扫描信号。第二GOA电路可以在B组初始信号B-STV、时钟信号CK以及时钟信号XCK的控制下，生成对应的B组扫描信号。发光驱动电路可以在发光初始信号EM-STV、时钟信号CK以及时钟信号XCK的控制下，生成对应的发光控制信号，例如，第一级发光控制信号EM（1）。
A组第一级扫描信号ASCAN（1）为低电位时，第一复位晶体管T4打开，对驱动晶体管T1的栅极电位进行复位。A组第二级扫描信号ASCAN（2）为低电位时，数据信号DATA同时写入转存电容C和存储电容Cst。B组第一级扫描信号BSCAN（1）为第一级第二GOA单元输出的。B组第二级扫描信号BSCAN（2）为低电位时，转存电容C中的电信号对存储电容Cst进行再次充电。
其中，数据信号DATA的写入可以在一帧时间T的0.25~0.75T期间进行，而再次充电可以在一帧时间T的0.5~1T期间进行。
在其中一个实施例中，如图16所示，第一GOA电路可以在A组初始信号A-STV、时钟信号CK以及时钟信号XCK的控制下，生成对应的A组扫描信号。第二GOA电路可以在B组初始信号B-STV、时钟信号CK以及时钟信号XCK的控制下，生成对应的B组扫描信号。发光驱动电路可以在发光初始信号EM-STV、时钟信号CK以及时钟信号XCK的控制下，生成对应的发光控制信号，例如，第一级发光控制信号EM（1）。
A组第一级扫描信号ASCAN（1）为低电位时，第一复位晶体管T4打开，对驱动晶体管T1的栅极电位进行复位，同时，B组第一级扫描信号BSCAN（1）也为低电位。A组第二级扫描信号ASCAN（2）和B组第二级扫描信号BSCAN（2）均为低电位时，数据信号DATA同时写入转存电容C和存储电容Cst。B组第二级扫描信号BSCAN（2）为低电位时，转存电容C中的电信号对存储电容Cst进行再次充电。
其中，数据信号DATA的写入可以在一帧时间T的0.25~0.75T期间进行，而再次充电可以在一帧时间T的0.5~1T期间进行。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种像素电路，包括：
    第一电源线；
    第二电源线；
    串接于所述第一电源线与所述第二电源线之间的发光器件和驱动晶体管；
    存储电容，与所述驱动晶体管的栅极电连接；
    写入晶体管，所述写入晶体管的源极/漏极中的一个与所述存储电容电连接，所述写入晶体管的源极/漏极中的另一个用于接入数据信号；
    转存电容，与所述写入晶体管的源极/漏极中的一个电连接；以及
    第一开关晶体管，所述第一开关晶体管的源极/漏极中的一个与所述转存电容和所述写入晶体管的源极/漏极中的一个电连接，所述第一开关晶体管的源极/漏极中的另一个与所述驱动晶体管的源极/漏极中的一个电连接。
  2. 根据权利要求1所述的像素电路，其中，所述像素电路还包括第二开关晶体管；
    所述第二开关晶体管的源极/漏极中的一个与所述驱动晶体管的源极/漏极中的另一个电连接；所述第二开关晶体管的源极/漏极中的另一个与所述存储电容和所述驱动晶体管的栅极电连接。
  3. 根据权利要求2所述的像素电路，其中，所述写入晶体管的栅极用于接入第一控制信号；所述第一开关晶体管的栅极用于接入第二控制信号；所述第二开关晶体管的栅极用于接入所述第二控制信号；在同一帧中，所述第一控制信号的有效脉冲数量小于所述第二控制信号的有效脉冲数量，且所述第二控制信号中至少一个有效脉冲与所述第一控制信号的有效脉冲相同。
  4. 根据权利要求2所述的像素电路，其中，所述像素电路还包括第三开关晶体管；
    所述第三开关晶体管的源极/漏极中的一个与所述第一开关晶体管的源极/漏极中的一个电连接；所述第三开关晶体管的源极/漏极中的另一个与所述第一开关晶体管的源极/漏极中的另一个电连接。
  5. 根据权利要求4所述的像素电路，其中，所述像素电路还包括第四开关晶体管；
    所述第四开关晶体管的源极/漏极中的一个与所述第二开关晶体管的源极/漏极中的一个电连接；所述第四开关晶体管的源极/漏极中的另一个与所述第二开关晶体管的源极/漏极中的另一个电连接。
  6. 根据权利要求5所述的像素电路，其中，所述像素电路的工作阶段包括写入阶段和发光阶段；所述写入晶体管的栅极用于接入第一控制信号；所述第一开关晶体管的栅极用于接入所述第一控制信号；所述第二开关晶体管的栅极用于接入所述第一控制信号；所述第三开关晶体管的栅极用于接入第三控制信号；所述第四开关晶体管的栅极用于接入所述第三控制信号；在同一帧中，所述第一控制信号的有效脉冲位于所述写入阶段中，所述第三控制信号的有效脉冲位于所述发光阶段中。
  7. 根据权利要求3或者6所述的像素电路，其中，所述像素电路还包括第一发光控制晶体管；
    所述第一发光控制晶体管的源极/漏极中的一个与所述驱动晶体管的源极/漏极中的一个和所述第一开关晶体管的源极/漏极中的另一个电连接；所述第一发光控制晶体管的栅极用于接入发光控制信号。
  8. 根据权利要求7所述的像素电路，其中，所述像素电路还包括第二发光控制晶体管；
    所述第二发光控制晶体管的源极/漏极中的一个与所述驱动晶体管的源极/漏极中的另一个和所述第二开关晶体管的源极/漏极中的一个电连接；所述第二发光控制晶体管的栅极用于接入所述发光控制信号。
  9. 一种像素电路，包括：
    写入模块，用于接入数据信号；
    转存模块，与所述写入模块连接，用于存储所述数据信号以在所述像素电路的发光阶段中输出补偿信号；
    第一分时传输模块，与所述写入模块和所述转存模块连接，用于分时传输所述数据信号和所述补偿信号；
    驱动模块，与所述第一分时传输模块连接；
    第二分时传输模块，与所述驱动模块连接，用于分时传输所述数据信号和所述补偿信号；以及
    存储模块，与所述驱动模块的控制端和所述第二分时传输模块的输出端连接，用于在同一帧中分时存储所述数据信号和所述补偿信号，以在所述发光阶段中维持所述驱动模块的控制端电位。
  10. 根据权利要求9所述的像素电路，其中，所述像素电路还包括发光控制模块；所述发光控制模块与所述驱动模块连接，用于根据发光控制信号通断控制所述像素电路的发光回路；
    在所述发光阶段中，所述发光控制信号控制所述发光控制模块处于断开状态期间，所述像素电路控制所述补偿信号写入至所述存储模块。
  11. 根据权利要求10所述的像素电路，其中，所述写入模块包括写入晶体管；所述写入晶体管的源极/漏极中的一个用于接入所述数据信号；所述写入晶体管的源极/漏极中的另一个与所述转存模块和所述第一分时传输模块连接；所述写入晶体管的栅极用于接入第一控制信号。
  12. 根据权利要求11所述的像素电路，其中，所述转存模块包括转存电容；所述转存电容的第一端与所述写入晶体管的源极/漏极中的另一个连接；所述转存电容的第二端用于接入第一电源信号。
  13. 根据权利要求12所述的像素电路，其中，所述第一分时传输模块包括第一分时传输晶体管；所述第一分时传输晶体管的源极/漏极中的一个与所述转存电容的第一端连接；所述第一分时传输晶体管的源极/漏极中的另一个与所述驱动模块连接；所述第一分时传输晶体管的栅极用于接入第二控制信号；在同一帧中，所述第一控制信号的有效脉冲数量小于所述第二控制信号的有效脉冲数量，且所述第二控制信号中至少一个有效脉冲与所述第一控制信号的有效脉冲相同。
  14. 根据权利要求13所述的像素电路，其中，所述驱动模块包括驱动晶体管；所述驱动晶体管的源极/漏极中的一个与所述第一分时传输晶体管的源极/漏极中的另一个连接；所述驱动晶体管的源极/漏极中的另一个与所述第二分时传输模块的输入端连接。
  15. 根据权利要求14所述的像素电路，其中，所述第二分时传输模块包括第二分时传输晶体管；所述第二分时传输晶体管的源极/漏极中的一个与所述驱动晶体管的源极/漏极中的另一个连接；所述第二分时传输晶体管的源极/漏极中的另一个与所述驱动晶体管的栅极连接；所述第二分时传输晶体管的栅极用于接入所述第二控制信号。
  16. 根据权利要求15所述的像素电路，其中，所述存储模块包括存储电容；所述存储电容的第一端与所述驱动晶体管的栅极连接；所述存储电容的第二端与所述转存电容的第二端连接。
  17. 根据权利要求16所述的像素电路，其中，所述发光控制模块包括第一发光控制晶体管和第二发光控制晶体管；
    所述第一发光控制晶体管的源极/漏极中的一个与所述存储电容的第二端连接；所述第一发光控制晶体管的源极/漏极中的另一个与所述驱动晶体管的源极/漏极中的一个连接；所述第一发光控制晶体管的栅极用于接入所述发光控制信号；
    所述第二发光控制晶体管的源极/漏极中的一个与所述驱动晶体管的源极/漏极中的另一个连接；所述第二发光控制晶体管的栅极用于接入所述发光控制信号。
  18. 根据权利要求12所述的像素电路，其中，所述第一分时传输模块包括第一晶体管和第二晶体管；
    所述第一晶体管的源极/漏极中的一个与所述第二晶体管的源极/漏极中的一个和所述转存电容的第一端连接；所述第一晶体管的源极/漏极中的另一个与所述第二晶体管的源极/漏极中的另一个和所述驱动模块的输入端连接；
    所述第一晶体管的栅极用于接入所述第一控制信号；所述第二晶体管的栅极用于接入第三控制信号；在同一帧中，所述第一控制信号的有效脉冲位于写入阶段中，所述第三控制信号的有效脉冲位于发光阶段中。
  19. 根据权利要求18所述的像素电路，其中，所述第二分时传输模块包括第三晶体管和第四晶体管；
    所述第三晶体管的源极/漏极中的一个与所述第四晶体管的源极/漏极中的一个和所述驱动模块的输出端连接；所述第三晶体管的源极/漏极中的另一个与所述第四晶体管的源极/漏极中的另一个和所述驱动模块的控制端连接；
    所述第三晶体管的栅极用于接入所述第一控制信号；所述第四晶体管的栅极用于接入所述第三控制信号。
  20. 一种显示面板，包括如权利要求1所述的像素电路。
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