WO2024045484A1 - 像素电路及其驱动方法和显示面板 - Google Patents

像素电路及其驱动方法和显示面板 Download PDF

Info

Publication number
WO2024045484A1
WO2024045484A1 PCT/CN2023/073675 CN2023073675W WO2024045484A1 WO 2024045484 A1 WO2024045484 A1 WO 2024045484A1 CN 2023073675 W CN2023073675 W CN 2023073675W WO 2024045484 A1 WO2024045484 A1 WO 2024045484A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
module
gate
initialization
electrode
Prior art date
Application number
PCT/CN2023/073675
Other languages
English (en)
French (fr)
Inventor
盖翠丽
郭恩卿
李俊峰
邢汝博
潘康观
Original Assignee
云谷（固安）科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 云谷（固安）科技有限公司 filed Critical 云谷（固安）科技有限公司
Publication of WO2024045484A1 publication Critical patent/WO2024045484A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • Embodiments of the present application relate to display technology, for example, to a pixel circuit and its driving method and a display panel.
  • AMOLED Active-matrix Organic Light Emitting Diode
  • This application provides a pixel circuit, a driving method thereof, and a display panel to realize broadband driving of the pixel circuit.
  • embodiments of the present application provide a pixel circuit, including: a driving module, a data writing module and a light-emitting module;
  • the data writing module includes a first transistor and a second transistor connected in series.
  • the first transistor is a low-temperature polysilicon transistor, and the second transistor is an oxide transistor.
  • the data writing module is configured to transmit the data voltage to The drive module;
  • the driving module is configured to drive the light-emitting module to emit light according to the data voltage.
  • inventions of the present application also provide a driving method for a pixel circuit.
  • the pixel circuit includes a driving module, a data writing module and a light emitting module;
  • the data writing module includes a first transistor and a second transistor connected in series.
  • transistor the first transistor is a low-temperature polysilicon transistor, and the second transistor
  • the tube is an oxide transistor;
  • the driving method includes:
  • the first transistor and the second transistor are controlled to be turned on, and the second transistor is turned on earlier than the first transistor to transmit the data voltage provided by the data line to the driver module;
  • the first transistor and the second transistor are controlled to be turned off; the driving module drives the light-emitting module to emit light according to the data voltage.
  • embodiments of the present application further provide a display panel, including the pixel circuit provided in any embodiment of the present application.
  • the pixel circuit provided by the embodiment of the present application includes a driving module, a data writing module and a light-emitting module.
  • the data writing module includes a first transistor and a second transistor connected in series.
  • the first transistor is a low-temperature polysilicon transistor and the second transistor is an oxide transistor.
  • the data writing module is configured to transmit the data voltage to the driving module.
  • the driving module is configured to transmit the data voltage according to The data voltage drives the light-emitting module to emit light.
  • Low-temperature polysilicon transistors have high mobility and fast driving speed.
  • the first transistor is a low-temperature polysilicon transistor, which can quickly write data voltage into the driving module and is suitable for high-frequency driving. The off-state leakage current of the oxide transistor is small.
  • the second transistor is an oxide transistor, which can reduce the leakage current, alleviate the problem of poor display effect caused by long leakage time, and ensure the stability of the display panel. Therefore, in this embodiment, a pixel driving circuit that combines low-temperature polysilicon transistors and oxide transistors is used, which is beneficial to broadband driving of the display panel and reduces power consumption.
  • Figure 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • Figure 2 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 3 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 4 is a driving timing diagram of a pixel circuit provided by an embodiment of the present application.
  • Figure 5 is a schematic diagram of another pixel circuit structure provided by an embodiment of the present application.
  • Figure 6 is a schematic diagram of another pixel circuit structure provided by an embodiment of the present application.
  • Figure 7 is a driving timing diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 8 is a schematic diagram of another pixel circuit structure provided by an embodiment of the present application.
  • Figure 9 is a characteristic curve of a double-gate transistor provided by an embodiment of the present application.
  • Figure 10 is a schematic diagram of another pixel circuit structure provided by an embodiment of the present application.
  • Figure 11 is a schematic diagram of another pixel circuit structure provided by an embodiment of the present application.
  • Figure 12 is a driving timing diagram of another pixel circuit provided by an embodiment of the present application.
  • Figure 13 is a flow chart of a driving method for a pixel circuit provided by an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the pixel circuit in the related art cannot meet the requirements of wide-band driving.
  • the reason for the above problems is that if the display panel uses low temperature polysilicon (LTPS) pixel circuit for driving, the leakage current of the low temperature polysilicon transistor is large, which is inconsistent with the low temperature polysilicon transistor leakage current. If the transistor connected to the driving transistor is in the off state for a long time, its leakage time will be long, causing the gate voltage of the driving transistor to be unstable, resulting in serious uneven display brightness. If a pure oxide circuit is used for driving, the transistors in the pixel circuit are all oxide transistors. Due to the low mobility of the oxide transistors, at high refresh frequencies, the writing of data voltage is insufficient, affecting the display effect.
  • LTPS low temperature polysilicon
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • the pixel circuit provided by an embodiment of the present application includes a driving module 10 , a data writing module 12 and a light-emitting module 13 .
  • the data writing module 12 includes a first transistor T1 and a second transistor T2 connected in series.
  • the first transistor T1 is a low-temperature polysilicon transistor, and the second transistor T2 is an oxide transistor.
  • the data writing module 12 is configured to transmit the data voltage to the driving module. 10.
  • the driving module 11 is configured to drive the light-emitting module 13 to emit light according to the data voltage.
  • the pixel circuit also includes a storage module 11 and at least one lighting control module 14.
  • the storage module 11 is connected to the driving module 10.
  • the storage module 11 is configured to store the data voltage.
  • the lighting control module 14 is configured to control the connection between the driving module 10 and the first power supply Vdd or the second power supply Vdd. Whether at least one of the power supplies Vss is connected.
  • the lighting control module 14 is configured to control whether a path is formed between the first power supply Vdd, the lighting module 13 and the second power supply Vss.
  • the lighting control module 14 and the driving module 10 are exemplarily shown to be connected between the first power supply Vdd and the second power supply Vss.
  • the gate of the first transistor T1 is connected to the first scan line S1
  • the gate of the second transistor T2 is connected to the second scan line S2
  • the first transistor T1 is turned on or off in response to the signal on the first scan line S1.
  • the second transistor T2 is turned on or off in response to the signal on the second scan line S2.
  • the working phase may include at least a data voltage writing phase and a light emitting phase.
  • both the first transistor T1 and the second transistor T2 are turned on to transmit the data voltage to the driving module 10.
  • the first transistor T1 is a low-temperature polysilicon transistor with high mobility and can quickly write the data voltage. In the driver module, it is suitable for situations where the data voltage writing phase time is short under high refresh frequency.
  • the first transistor T1 and the second transistor T2 are turned off, the light-emitting control module 14 is turned on, and a path is formed between the first power supply Vdd, the light-emitting control module 14, the driving module 10, the light-emitting module 13 and the second power supply Vss, and the driving The module 10 generates a driving current according to the data voltage to drive the light-emitting module 13 to emit light.
  • the second transistor T2 is an oxide transistor, such as an indium gallium zinc oxide (IGZO) transistor.
  • IGZO indium gallium zinc oxide
  • Low-temperature polysilicon transistors have high mobility and fast driving speed.
  • the first transistor is a low-temperature polysilicon transistor, which can quickly write data voltage into the driving module and is suitable for high-frequency driving.
  • the off-state leakage current of the oxide transistor is small.
  • the second transistor is an oxide transistor, which can reduce the leakage current, alleviate the problem of poor display effect caused by long leakage time, and ensure the stability of the display panel. Therefore, in this embodiment, a pixel driving circuit in which low-temperature polysilicon transistors and oxide transistors are combined is used. path, which is conducive to realizing broadband driving of display panels, reducing power consumption, and improving display effects.
  • the second transistor T2 is turned on before the first transistor T1 , and the first transistor T1 is turned on during the period when the second transistor T2 is turned on.
  • the second transistor T2 can be turned on before the data voltage writing stage, and the first transistor T1 and the second transistor T2 can be collectively equivalent to low-temperature polysilicon transistors during the data voltage writing stage, thereby quickly writing the data voltage. into the driver module 10.
  • the second transistor T2 is an oxide transistor, during the data voltage writing stage, the second transistor T2 is fully turned on, which does not affect the fast writing of the data voltage.
  • the first transistor T1 and the second transistor T2 are connected in series between the data line Vdata and the driving module 10 .
  • the first transistor T1 and the second transistor T2 are connected in series. After the first transistor T1 and the second transistor T2 are turned off, they are equivalent to oxide transistors, which can reduce the leakage current.
  • the second transistor T2 is closer to the driving module 10 than the first transistor T1. After the second transistor T2 is turned off, it has a strong ability to suppress leakage, which is beneficial to maintaining the control terminal of the driving module 10 (that is, connected to the second transistor T2 one end) of the voltage is stable.
  • the second transistor T2 is connected in series with the first transistor T1. After the first transistor T1 is turned off, the leakage can be further suppressed, thereby improving the stability of the voltage at the control terminal of the driving module 10 and improving the uniformity of the display.
  • FIG. 2 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • the pixel circuit also includes a storage module 11, a lighting control module 14 and an initialization module;
  • the storage module 11 is connected to the driving module 10, Set to store data voltage, the storage module 11 includes a first storage module 111 and a second storage module 112;
  • the driving module 10 includes a double-gate transistor T0, and the light-emitting control module 14, the double-gate transistor T0, and the light-emitting module 13 are connected to the first power supply in sequence.
  • Vdd and the second power supply Vss
  • the first pole D of the double-gate transistor T0 is connected to the light-emitting control module 14
  • the second pole S of the double-gate transistor T0 is connected to the light-emitting module 13;
  • the data writing module 12 is connected between the first gate G of the double-gate transistor T0 and the data line Vdata, and the data writing module 12 is configured to transmit the data voltage output by the data line Vdata to the first gate G;
  • the first memory module 111 is connected between the first gate G and the second electrode S of the double-gate transistor T0.
  • the first memory module 111 is configured to store the voltage of the first gate G.
  • the second memory module 112 is connected to the double-gate transistor T0. Between the second gate B and the second electrode S of the transistor T0, the second storage module 112 is configured to store the voltage of the second gate B;
  • the initialization module is configured to initialize the first gate G, the second gate B, the first pole D and the second pole S of the double-gate transistor T0.
  • the double-gate transistor T0 serves as the driving module 10 of the pixel circuit and drives the light-emitting module 13 to emit light.
  • the double-gate transistor T0 is usually a vertical double-gate transistor.
  • the first gate G may be a top gate
  • the second gate B may be a bottom gate.
  • the threshold voltage of the double-gate transistor T0 can be adjusted by setting the voltage between the second gate B and the second electrode S of the double-gate transistor T0.
  • the initialization module may include a plurality of transistors, such as a transistor connected to the second gate B to initialize the second gate B, and may also include a transistor connected to the first pole D of the double-gate transistor T0 to initialize the first
  • the first gate G and the second pole S of the double-gate transistor T0 may also be initialized by the first gate G and the second pole S of the double-gate transistor T0.
  • the initialization module includes a first initialization module 161, a second initialization module 162 and a third initialization module 163.
  • the first initialization module 161 is connected to the first gate G and the second gate G of the dual-gate transistor T0.
  • the second initialization module 162 is connected between the second gate B and the first terminal D of the dual-gate transistor T0.
  • the third initialization module 163 is connected between the second pole S of the double-gate transistor T0 and the initialization signal line Vref.
  • the working process of the pixel circuit may include an initialization stage, a compensation stage, a data voltage writing stage and a light-emitting stage.
  • the first initialization module 161, the second initialization module 162 and the third initialization module 163 are respectively connected to different scan lines, and are turned on or off in response to signals on the respective connected scan lines.
  • the light-emitting control module 14 is connected to the light-emitting control signal line and turns on or off in response to the signal on the light-emitting control signal line.
  • the first transistor T1 is turned on or off in response to the signal on the first scan line S1
  • the second transistor T2 is turned on or off in response to the signal on the second scan line S2.
  • the first initialization module 161 when the first initialization module 161 is turned on, it means that the second electrode S of the double-gate transistor T0 is connected to the first gate G.
  • the first initialization module 161 when the first initialization module 161 is turned off, it means that the second electrode of the double-gate transistor T0 is connected.
  • the connection between the pole S and the first gate G is disconnected.
  • the first initialization module 161, the second initialization module 162, the third initialization module 163, the lighting control module 14 and the second transistor T2 are controlled to be turned on, and the first transistor T1 is controlled to be turned off.
  • the initialization voltage on the initialization signal line Vref is transmitted to the second electrode S of the dual-gate transistor T0 through the turned-on third initialization module 163, and then transmitted to the first gate G of the dual-gate transistor T0 through the first initialization module 161, To achieve initialization of the first gate G, the second electrode S and the first end of the light emitting module 13 .
  • the first power supply voltage V1 provided by the first power supply Vdd is transmitted to the first pole D of the double-gate transistor T0 through the turned-on light emitting control module 14, and then transmitted to the second pole D of the double-gate transistor T0 through the turned-on second initialization module 162.
  • Gate B implements the initialization of the first electrode D and the second gate B of the double-gate transistor T0.
  • the second transistor T2 is turned on in advance. After both the first transistor T1 and the second transistor T2 are turned on in subsequent stages, they can be equivalent to low-temperature polysilicon transistors as a whole, thereby quickly writing the data voltage into the driving module 10 .
  • the second transistor T2 is an oxide transistor, in the subsequent data voltage writing stage, the second transistor T2 is fully turned on, which does not affect the fast writing of the data voltage.
  • the voltage of the second gate B is the first power supply voltage V1
  • the first power supply voltage V1 is high level, so that the threshold voltage Vth of the double-gate transistor T0 is less than 0.
  • the double-gate transistor T0 The voltage difference between the first gate G and the second electrode S of T0 is greater than the threshold voltage Vth, and the double-gate transistor T0 is turned on.
  • the first transistor T1 and the lighting control module 14 are controlled to be turned off, and the first initialization module 161, the second initialization module 162, the third initialization module 163, the double-gate transistor T0 and the second transistor T2 are controlled to be turned on. Since the voltage of the second gate B is the first power supply voltage V1, and the first power supply voltage V1 is higher than the initialization voltage Vf on the initialization signal line Vref, therefore, between the second gate B, the second initialization module 162, and the double-gate transistor T0 , a path is formed between the third initialization module 163 and the initialization signal line Vref, the charge of the second gate B flows to the second electrode S, and the voltage of the second gate B and the first electrode D decreases.
  • the threshold voltage Vth of the double-gate transistor T0 gradually drifts positively.
  • the threshold voltage Vth increases to 0V
  • the double-gate transistor T0 is turned off, and the second storage module 112 stores the voltage difference VBS between the second gate B and the second pole S of the double-gate transistor T0.
  • the first transistor T1, the second transistor T2 and the third initialization module 163 are controlled to be turned on, the first initialization module 161, the second initialization module 162 and the lighting control module 14 are controlled to be turned off, and the data line Vdata provides
  • the data voltage Vd is transmitted to the first gate G of the double-gate transistor T0 through the turned-on first transistor T1 and the second transistor T2.
  • the first transistor T1 is a low-temperature polysilicon transistor with high mobility. It can quickly write the data voltage to the first gate of the double-gate transistor T0 during the data voltage writing stage, which is beneficial to high-frequency driving.
  • the light-emitting control module 14 is controlled to be turned on, the first transistor T1, the second transistor T2, the first initialization module 161, the second initialization module 162 and the third initialization module 163 are controlled to be turned off, and the double-gate transistor T0 is controlled according to the data voltage.
  • Vd generates a driving current to drive the light-emitting module 13 to emit light.
  • the second transistor T2 is in an off state, and the second transistor T2 is an oxide transistor. The leakage current in the off-state is small.
  • the second transistor T2 can increase the potential of the first gate G. Stability, thereby improving display uniformity and reducing power consumption.
  • the signal on the initialization signal line is provided by the second power supply.
  • the signal on the initialization signal line may be an initialization voltage, or may be a second power supply voltage provided by a second power supply.
  • the signal on the initialization signal line is provided by the second power supply, which can save the number of signal lines and simplify the structural design of the driver IC.
  • Figure 3 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • the first gate G is a top gate
  • the second gate B is a bottom gate
  • first initialization The module 161 includes a third transistor T3,
  • the second initialization module 162 includes a fourth transistor T4,
  • the third initialization module 163 includes a fifth transistor T5,
  • the lighting control module 14 includes a sixth transistor T6;
  • the first storage module 111 includes a first capacitor C1
  • the second storage module 112 includes a second capacitor C2.
  • the first electrode of the first transistor T1 is connected to the data line Vdata, and the second electrode of the first transistor T1 is connected to the data line Vdata.
  • the first electrode of the two transistors T2 the gate of the first transistor T1 is connected to the first scan line S1
  • the second electrode of the second transistor T2 is connected to the first gate G of the double-gate transistor T0
  • the gate of the second transistor T2 is connected to second scan line S2.
  • the first electrode of the third transistor T3 is connected to the second electrode S of the double-gate transistor T0, the second electrode of the third transistor T3 is connected to the first gate G of the double-gate transistor T0, and the gate electrode of the third transistor T3 is connected to the third scan Line S3, the first electrode of the fourth transistor T4 is connected to the first electrode D of the double-gate transistor T0, the second electrode of the fourth transistor T4 is connected to the second gate B of the double-gate transistor T0, and the gate electrode of the fourth transistor T4 is connected to the line S3.
  • the first electrode of the fifth transistor T5 is connected to the initialization signal line Vref
  • the second electrode of the fifth transistor T5 is connected to the second electrode S of the dual-gate transistor T0
  • the gate electrode of the fifth transistor T5 is connected to the second scanning line S2.
  • the first electrode of the sixth transistor T6 is connected to the first power supply Vdd
  • the second electrode of the sixth transistor T6 is connected to the first electrode D of the dual-gate transistor T0
  • the gate electrode of the sixth transistor T6 is connected to the light emission control signal line EM.
  • the first capacitor C1 is connected between the first gate G and the second electrode S of the double-gate transistor T0, and the second capacitor C2 is connected between the second gate B and the second electrode S of the double-gate transistor T0.
  • the sixth transistor T6 is a low-temperature polysilicon transistor, and the double-gate transistor T0 , the third transistor T3 , the fourth transistor T4 and the fifth transistor T5 are all oxide transistors.
  • FIG. 4 is a driving timing diagram of a pixel circuit provided by an embodiment of the present application.
  • the driving timing diagram shown in FIG. 4 can be applied to the pixel circuit shown in FIG. 3 .
  • the first transistor T1 and the sixth transistor T6 are exemplarily shown to be P-type transistors, and the double-gate transistor T0, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are N-type. transistor.
  • the working process of the pixel circuit may include an initialization stage t1, a compensation stage t2, a data voltage writing stage t3, and a light-emitting stage t4.
  • the signal on the second scan line S2 is high level, controlling the second transistor T2 and the fifth transistor T5 to turn on.
  • the signal on the third scan line S3 is at a high level, controlling the third transistor T3 and the fourth transistor T4 to be turned on.
  • the signal on the light emission control signal line EM is at a low level, controlling the sixth transistor T6 to turn on.
  • the signal on the first scan line S1 is at a high level, controlling the first transistor T1 to turn off.
  • the fifth transistor T5 and the third transistor T3 are turned on
  • the initialization voltage Vf on the initialization signal line Vref is transmitted to the first end of the light-emitting module 13 and the first gate G of the double-gate transistor T0 to complete the first gate G, the second electrode S and the first end of the light-emitting module 13 Initialization.
  • the turned-on sixth transistor T6 and the fourth transistor T4 transmit the first power supply voltage V1 provided by the first power supply Vdd to the first pole D and the second gate B of the double-gate transistor T0, completing the connection between the second gate B and the second gate B of the double-gate transistor T0.
  • the second transistor T2 is turned on in advance during the initialization stage t1. Although the second transistor T2 is an oxide transistor, in the subsequent data voltage writing stage t3, the second transistor T2 is fully turned on, and the data voltage Vd can be passed through the first transistor T1. Quickly write the first gate G of the double-gate transistor T0.
  • the second scan signal S2 is at a high level, controlling the second transistor T2 and the fifth transistor T5 to be turned on.
  • the signal on the third scan line S3 is at a high level, controlling the third transistor T3 and the fourth transistor T4 to be turned on.
  • the signal on the light emission control signal line EM is at a high level, controlling the sixth transistor T6 to turn off.
  • the signal on the first scan line S1 is at a high level, controlling the first transistor T1 to turn off.
  • the second capacitor C2 stores the first power supply voltage V1 at the first terminal of the second capacitor C2.
  • a path is formed between the second gate B, the fourth transistor T4, the double-gate transistor T0, the fifth transistor T5 and the initialization signal line Vref.
  • the voltages of the first electrode D and the second gate B of the double-gate transistor T0 decrease, and then the voltages of the first electrode D and the second gate B of the double-gate transistor T0 decrease.
  • the threshold voltage Vth of the double-gate transistor T0 gradually drifts forward.
  • the threshold voltage Vth is equal to 0V
  • the double-gate transistor T0 is turned off, and the second capacitor C2 stores the voltage difference VBS between the second gate B and the second electrode of the double-gate transistor T0.
  • the second scanning signal S2 is at a high level, controlling the second transistor T2 and the fifth transistor T5 to be turned on.
  • the signal on the third scan line S3 is low level, controlling the third transistor T3 and the fourth transistor T4 to turn off.
  • the signal on the light emission control signal line EM is at a high level, controlling the sixth transistor T6 to turn off.
  • the signal on the first scan line S1 is low level, controlling the first transistor T1 to turn on.
  • the turned-on first transistor T1 and the second transistor T2 transmit the data voltage Vd to the first gate G, and the turned-on fifth transistor T5 transmits the initialization voltage Vref to the second electrode S of the double-gate transistor T0.
  • the first transistor T1 is a low-temperature polysilicon transistor with high mobility and can quickly write the data voltage Vd into the double-gate transistor.
  • transistor T0 under high refresh frequency and the time of data voltage writing phase t3 is short, data voltage Vd can still be fully written into double-gate transistor T0, which is beneficial to realizing high-frequency driving.
  • the second scanning signal S2 is low level, controlling the second transistor T2 and the fifth transistor T5 to turn off.
  • the signal on the third scanning line S3 is at a low level, controlling the third transistor T3 and the fourth transistor T4 to turn off.
  • the signal on the first scanning line S1 is at a high level, controlling the first transistor T1 to turn off.
  • the signal on the light-emitting control signal line EM is at a low level, controlling the sixth transistor T6 to turn on, and the double-gate transistor T0 generates a driving current according to the voltages of its first gate G and second pole S to drive the light-emitting module 13 to emit light.
  • the voltage VS of the second pole S of the double-gate transistor T0 V2 + Voled, where Voled is the cross-voltage of the light-emitting module 13 and V2 is the second power supply voltage provided by the second power supply Vss.
  • the first gate G Due to the coupling effect of the first capacitor C1, the first gate G is also raised by ⁇ 1.
  • the pixel circuit provided in this embodiment can compensate for the voltage of the double-gate transistor T0.
  • the problems of uneven threshold voltage, IR drop of the second power supply voltage V2, and uneven light emission caused by different cross-voltage Voled of different light-emitting modules 13 due to aging of the light-emitting module 13 are beneficial to improving the display effect.
  • the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 connected to the double-gate transistor T0 are all oxide transistors.
  • the leakage current of the oxide transistor in the off state is small, which can ensure that the The stability of the potential of the first gate G is beneficial to improving the display effect.
  • the first transistor T1 is a low-temperature polysilicon transistor, which can quickly write the data voltage into the double-gate transistor T0 at high frequency, which is beneficial to realizing high-frequency driving. That is, the pixel circuit provided by this embodiment can realize broadband driving.
  • the gate transistor T0 is an oxide transistor with good long-range uniformity, suitable for medium and large size displays, and high brightness uniformity.
  • the sixth transistor T6 is a low-temperature polysilicon transistor with good negative bias temperature stress (NBTS) stability and small cross-voltage, which is beneficial to reducing power consumption.
  • NBTS negative bias temperature stress
  • FIG. 5 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • the pixel circuit also includes a storage module 11, a lighting control module 14, a compensation module 15 and an initialization module.
  • the storage module 11 includes The first storage module 111 and the second storage module 112; the lighting control module 14, the driving module 10, and the lighting module 13 are connected in sequence between the first power supply Vdd and the second power supply Vss.
  • the first storage module 111 is connected between the data writing module 12 and the control end of the driving module 10 ; the first storage module 111 is configured to couple the data voltage to the driving module 10 .
  • the compensation module 15 is connected between the control end and the first end of the driving module 10 , and the first end of the driving module 10 is connected to the lighting control module 14 .
  • the second storage module 112 is connected between the data writing module 12 and the second end of the driving module 10 , or the second storage module 112 is connected between the first storage module 111 and the second end of the driving module 10 .
  • the memory module 112 is arranged to couple the voltage of the second terminal of the driver module 10 to the first memory module 111 .
  • the initialization module is configured to initialize the first storage module 111 and the second storage module 112 .
  • the initialization module may include a plurality of transistors, at least one transistor is connected to the first storage module 111 and is configured to initialize the first storage module 111, and at least one transistor is connected to the second storage module 112 and is configured to initialize the second storage module 112. initialization.
  • the initialization module includes a first initialization module 161 and a second initialization module 162.
  • the first initialization module 161 is connected between the first initialization signal line Vref1 and the first end of the first storage module 111.
  • the second end of the first storage module 111 is connected to the control end of the driving module 10 .
  • the second initialization module 162 is connected between the second initialization signal line Vref2 and the second end of the driving module 10 .
  • the first initialization voltage Vf1 provided by the first initialization signal line Vref1 is transmitted to the first end of the first memory module 111 to initialize the first memory module 111 .
  • the second initialization voltage Vf2 provided by the second initialization signal line Vref2 is transmitted to the second end of the second memory module 112 to initialize the second memory module 112 .
  • the gate of the first transistor T1 is connected to the first scanning line S1, and the gate of the second transistor T2 may be connected to the light emission control signal line EM.
  • the pixel circuit may include an initialization stage, a compensation stage, a data voltage writing stage and a light emitting stage.
  • the compensation module 15, the first initialization module 161, and the lighting control module 14 are controlled to be turned on, the first transistor T1, the second transistor T2, and the second initialization module 162 are controlled to be turned off, and the first power supply provided by the first power supply Vdd is
  • the voltage V1 is transmitted to the first terminal of the driving module 10 through the light-emitting control module 14, and then transmitted to the control terminal of the driving module 10 through the turned-on compensation module 15 to initialize the control terminal and the first terminal.
  • the lighting control module 14 and the first transistor T1 are controlled to be turned off, the first initialization module 161, the second transistor T2, the compensation module 15 and the second initialization module 162 are controlled to be turned on, and the driving module 10 (including the driving transistor) is controlled.
  • the first terminal charges the second terminal of the driving module 10, causing the voltages of the first terminal and the control terminal of the driving module 10 to decrease.
  • the driving module 10 turns off. off, where Vth is the threshold voltage of the driving transistor included in the driving module 10 .
  • both the first transistor T1 and the second transistor T2 are turned on in subsequent stages, they can be equivalent to low-temperature polysilicon transistors as a whole, thereby quickly writing the data voltage into the driving module 10 .
  • the second transistor T2 is an oxide transistor, in the subsequent data voltage writing stage, the second transistor T2 is fully turned on, which does not affect the fast writing of the data voltage.
  • the lighting control module 14, the compensation module 15 and the first initialization module 161 are controlled to be turned off, the first transistor T1, the second transistor T2 and the second initialization module 162 are controlled to be turned on, and the data voltage Vd is turned on.
  • the first transistor T1 and the second transistor T2 are written to the first terminal of the first memory module 111 .
  • the voltage at the second terminal of the driving module 10 remains unchanged at the second initialization voltage Vf2 of the previous stage.
  • the first transistor T1 is a low-temperature polysilicon transistor with high mobility and can quickly write the data voltage Vd into the driver module 10. At a high refresh frequency, the data voltage Vd can still be fully written when the data voltage writing phase is short. Writing into the driving module 10 is beneficial to improving the display effect under high-frequency driving.
  • the compensation module 15, the first initialization module 161, the second initialization module 162, The first transistor T1 and the second transistor T2 are turned off, the light-emitting control module 14 is controlled to be turned on, and the driving module 10 generates a driving current according to the voltages of its control terminal and the second terminal to drive the light-emitting module 13 to emit light.
  • the second transistor T2 is an oxide transistor. During the light-emitting phase, the leakage current is small when it is turned off. It can ensure the stability of the control terminal voltage of the drive module 10 when the light-emitting phase is long at a low refresh frequency, which is beneficial to improving the performance of low-frequency driving. display effect.
  • the pixel circuit is conducive to realizing wide-band display.
  • the compensation module 15 is connected in parallel with the first memory module 111.
  • the connection relationship of other modules can continue to refer to Figure 5.
  • the compensation module 15 is connected in parallel with the first memory module 111, the first initialization voltage is used.
  • Vf1 initializes the control end of the driving module 10, and other processes are the same as the pixel circuit shown in Figure 5, which will not be described again in this embodiment.
  • Figure 6 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • the driving module 10 includes a seventh transistor T7
  • the compensation module 15 includes an eighth transistor T8.
  • the first initialization The module 161 includes a ninth transistor T9
  • the second initialization module 162 includes a tenth transistor T10
  • the lighting control module 14 includes an eleventh transistor T11
  • the first storage module 111 includes a first capacitor C1
  • the second storage module 112 includes a second capacitor. C2.
  • the first electrode of the first transistor T1 is connected to the data line Vdata
  • the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2
  • the second electrode of the second transistor T2 is connected to the first end of the first capacitor C1.
  • the gate of the first transistor T1 is connected to the first scanning line S1
  • the gate of the second transistor T2 is connected to the light emission control signal line EM.
  • the first electrode of the ninth transistor T9 is connected to the first initialization signal line Vref1
  • the second electrode of the ninth transistor T9 is connected to the first end of the first capacitor C1
  • the gate electrode of the ninth transistor T9 is connected to the second scan line S2.
  • the second terminal of the first capacitor C1 is electrically connected to the gate of the seventh transistor T7.
  • the first electrode of the eighth transistor T8 is connected to the first electrode of the seventh transistor T7
  • the second electrode of the eighth transistor T8 is connected to the gate electrode of the seventh transistor T7
  • the gate electrode of the eighth transistor T8 is connected to the second scan line. S2.
  • the first terminal of the second capacitor C2 is connected to the first terminal of the first capacitor C1, and the second terminal of the second capacitor C2 The terminal is connected to the second pole of the seventh transistor T7.
  • the first electrode of the tenth transistor T10 is connected to the second initialization signal line Vref2, the second electrode of the tenth transistor T10 is connected to the second electrode of the seventh transistor T7, and the gate electrode of the tenth transistor T10 is connected to the light emission control signal line EM. .
  • the first electrode of the eleventh transistor T11 is connected to the first power supply Vdd
  • the second electrode of the eleventh transistor T11 is connected to the first electrode of the seventh transistor T7
  • the gate electrode of the eleventh transistor T11 is connected to the light emission control signal line EM. connect.
  • the eleventh transistor T11 is a low-temperature polysilicon transistor
  • the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are all oxide transistors.
  • Figure 7 is a driving timing diagram of another pixel circuit provided by an embodiment of the present application.
  • the driving timing shown in Figure 7 can be applied to the pixel circuit shown in Figure 6.
  • the first transistor T1 and the eleventh transistor T11 is a P-type transistor
  • the second transistor T2 the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 are all N-type transistors.
  • the working process of the pixel circuit provided by this embodiment includes an initialization stage t1, a compensation stage t2, a data voltage writing stage t3 and a light-emitting stage t4.
  • the signal on the first scan line S1 is high level, controlling the first transistor T1 to turn off.
  • the signal on the second scan line S2 is at a high level, controlling the eighth transistor T8 and the ninth transistor T9 to be turned on.
  • the signal on the light emission control signal line EM is at a low level, controlling the second transistor T2 and the tenth transistor T10 to turn off, and the eleventh transistor T11 to turn on.
  • the first initialization voltage Vf1 provided by the first initialization signal line Vref1 is transmitted to the first ends of the first capacitor C1 and the second capacitor C2 through the turned-on ninth transistor T9.
  • the first power supply voltage V1 provided by the first power supply Vdd is transmitted to the first electrode and gate of the seventh transistor T7 through the turned-on eleventh transistor T11 and the eighth transistor T8. After the first power supply voltage V1 is transmitted to the gate of the seventh transistor T7, the seventh transistor T7 is turned on, and current flows through the light-emitting module 13. However, the time for the light-emitting module 13 to emit light at this stage is very short. Even if the light-emitting module 13 emits light, it will not emit light. Does not affect contrast.
  • the signal on the first scan line S1 is high level, controlling the first transistor T1 to turn off. break.
  • the signal on the second scan line S2 is at a high level, controlling the eighth transistor T8 and the ninth transistor T9 to be turned on.
  • the signal on the light emission control signal line EM is at a high level, controlling the second transistor T2 and the tenth transistor T10 to be turned on, and the eleventh transistor T11 to be turned off.
  • the voltage at the first end of the first capacitor C1 remains unchanged at the first initialization voltage Vf1, and the second initialization voltage Vf2 provided by the second initialization signal line Vref2 is transmitted to the second pole of the seventh transistor T7.
  • the charge on the first pole of the seventh transistor T7 will flow to the second pole, causing the voltage of the first pole and the gate of the seventh transistor T7 to decrease until it drops to Vf2+Vth, the seventh transistor T7 turns off, where Vth is the threshold voltage of the seventh transistor T7.
  • the second transistor T2 is turned on during the compensation stage. After both the first transistor T1 and the second transistor T2 are turned on in subsequent stages, they can be equivalent to low-temperature polysilicon transistors as a whole, thereby quickly writing the data voltage into the seventh transistor T7.
  • the second transistor T2 is an oxide transistor, in the subsequent data voltage writing stage t3, the second transistor T2 is fully turned on, which does not affect the fast writing of the data voltage.
  • the signal on the first scan line S1 is low level, controlling the first transistor T1 to turn on.
  • the signal on the second scan line S2 is low level, controlling the eighth transistor T8 and the ninth transistor T9 to turn off.
  • the signal on the light emission control signal line EM is at a high level, controlling the second transistor T2 and the tenth transistor T10 to be turned on, and the eleventh transistor T11 to be turned off.
  • the second pole of the seventh transistor T7 maintains the second initialization voltage Vf2.
  • the first transistor T1 is a low-temperature polysilicon transistor with high mobility and can quickly write the data voltage Vd into the seventh transistor T7.
  • the data voltage Vd can still be achieved when the time of the data voltage writing phase t3 is short. Full writing of Vd is conducive to improving the display effect of high-frequency drive.
  • the signal on the first scan line S1 is at a high level, controlling the first transistor T1 to turn off.
  • the signal on the second scan line S2 is low level, controlling the eighth transistor T8 and the ninth transistor T9 to turn off.
  • the signal on the light emission control signal line EM is at a low level, controlling the second transistor T2 and the tenth transistor T10 to turn off, and the eleventh transistor T11 to turn on.
  • the first power supply voltage V1 is transmitted to the first electrode of the seventh transistor T7 through the turned-on eleventh transistor T11.
  • the seventh transistor T7 determines the voltage between its gate and the second electrode. The voltage generates a driving current to drive the light-emitting module 13 to emit light.
  • the pixel circuit provided in this embodiment can compensate the seventh transistor T7
  • the problems of uneven threshold voltage, IR drop of the second power supply Vss, and uneven light emission caused by different cross-voltage Voled of different light-emitting modules 13 due to aging of the light-emitting module 13 are beneficial to improving the display effect.
  • the seventh transistor T7 is an oxide transistor with good long-range uniformity, suitable for medium and large size displays, and high brightness uniformity.
  • the second transistor T2, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 are all oxide transistors, and the leakage current in the off state is small, so that the gate voltage retention rate of the seventh transistor T7 is high, which can reduce power consumption.
  • the first transistor T1 is a low-temperature polysilicon transistor, which can quickly write the data voltage into the driving module at high frequency and when the data voltage writing time is short, thereby improving the high-frequency driving effect. That is, the pixel circuit in this embodiment can Implement wideband drive.
  • the eleventh transistor T11 is a low-temperature polysilicon transistor.
  • the NBTS has good stability and small cross-voltage, which is beneficial to reducing power consumption.
  • FIG. 8 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • the first electrode of the eighth transistor T8 is connected to the second electrode of the ninth transistor T9.
  • the second terminal is connected to the second terminal of the first capacitor C1
  • the first terminal of the second capacitor C2 is connected to the first terminal of the first capacitor C1
  • the second terminal of the second capacitor C2 is connected to the second terminal of the seventh transistor T7. connect.
  • the connection relationships of other transistors are the same as in Figure 6, and will not be described again in this embodiment.
  • the driving timing shown in Figure 7 is the same Applicable to the pixel circuit shown in Figure 8.
  • the only difference between the working process of the pixel circuit shown in Figure 8 and the working process of the pixel circuit shown in Figure 6 is that in the initialization stage t1, the gate of the seventh transistor T7 is initialized through the first initialization voltage Vf1, so that in In the initialization stage t1, the seventh transistor T7 will not be turned on, and the light-emitting module 13 will not emit light, which is beneficial to improving the display effect.
  • Figure 9 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • the first pole of the eighth transistor T8 is connected to the first pole of the seventh transistor T7.
  • the second electrode is connected to the gate of the seventh transistor T7.
  • the first end of the second capacitor C2 is connected to the gate of the seventh transistor T7, and the second end of the second capacitor C2 is connected to the second electrode of the seventh transistor T7.
  • the connection relationship of other transistors is the same as in Figure 6.
  • the driving timing shown in Figure 7 is also applicable to the pixel circuit shown in Figure 9.
  • the initialization phase t1 and the compensation phase t2 of the pixel circuit shown in FIG. 9 are the same as those of the pixel circuit shown in FIG. 6 .
  • Figure 10 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • the first electrode of the eighth transistor T8 is connected to the second electrode of the ninth transistor T9.
  • the second pole is connected to the second terminal of the first capacitor C1.
  • the first end of the second capacitor C2 is connected to the gate of the seventh transistor T7, and the second end of the second capacitor C2 is connected to the second electrode of the seventh transistor T7.
  • the driving timing shown in Figure 7 is also applicable to the pixel circuit shown in Figure 10.
  • the pixel circuit shown in Figure 10 differs from Figure 6 in the initialization stage in that the gate of the seventh transistor T7 is initialized through the first initialization voltage Vf1, and the compensation stage t2 is the same as that in Figure 6 .
  • FIG 11 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • the pixel circuit also includes a storage module, a lighting control module, a compensation module and an initialization module.
  • the lighting control module includes an eleventh The transistor T11 and the twelfth transistor T12
  • the driving module includes the seventh transistor T7
  • the compensation module includes the eighth transistor T8
  • the initialization module includes the ninth transistor T9 and the tenth transistor T10
  • the memory module includes the first capacitor C1.
  • the first electrode of the eleventh transistor T11 is connected to the first power supply Vdd
  • the second electrode of the eleventh transistor T11 is connected to the first electrode of the seventh transistor T7
  • the second electrode of the seventh transistor T7 is connected to the twelfth transistor T12.
  • the first terminal of the twelfth transistor T12 is connected to the first terminal of the light-emitting module 13
  • the second terminal of the light-emitting module 13 is connected to the second power supply Vss.
  • the gates of the eleventh transistor T11 and the twelfth transistor T12 are both connected to the light emission control signal line EM.
  • the first electrode of the eighth transistor T8 is connected to the second electrode of the seventh transistor T7, the second electrode of the eighth transistor T8 is connected to the gate electrode of the seventh transistor T7, and the gate electrode of the eighth transistor T8 is connected to the light emission control signal line EM. .
  • the first electrode of the ninth transistor T9 is connected to the initialization signal line Vref, the second electrode of the ninth transistor T9 is connected to the gate electrode of the seventh transistor T7, the first electrode of the tenth transistor T10 is connected to the initialization signal line Vref, and the first electrode of the tenth transistor T10 is connected to the initialization signal line Vref.
  • the second electrode of the transistor T10 is connected to the first end of the light emitting module 13.
  • FIG. 12 is a driving timing diagram of another pixel circuit provided by an embodiment of the present application. The driving timing shown in FIG. 12 is applicable to the pixel circuit shown in FIG. 11 .
  • the first transistor T1, the eleventh transistor T11, and the twelfth transistor T12 are exemplarily shown to be P-type transistors, and the second transistor T2, the seventh transistor T7, the eighth transistor T8, The ninth transistor T9 and the tenth transistor T10 are N-type transistors.
  • the pixel circuit includes an initialization stage t1, a data voltage writing and compensation stage t5, and a light-emitting stage t4.
  • the ninth transistor T9 and the tenth transistor T10 are turned on in response to the high level on the second scan line S2, and the first transistor T1 is turned off in response to the high level on the first scan line S1.
  • the eleventh transistor T11 and the twelfth transistor T12 are turned off in response to the high level on the light emitting control signal line EM, and the second transistor T2 and the eighth transistor T8 are turned on in response to the high level on the light emitting control signal line EM.
  • the initialization voltage Vf is transmitted to the gate of the seventh transistor T7 and the first end of the light-emitting module 13 to initialize the driving module and the light-emitting module 13 .
  • the ninth transistor T9 and the tenth transistor T10 are turned off in response to the low level on the second scan line S2, and the first transistor T1 is turned on in response to the low level on the first scan line S1.
  • the eleventh transistor T11 and the twelfth transistor T12 are turned off in response to the high level on the lighting control signal line EM
  • the second transistor T2 and the eighth transistor T8 are turned on in response to the high level on the lighting control signal line EM.
  • the data voltage is transmitted to the gate of the seventh transistor T7 through the turned-on first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8, and the eighth transistor T8 controls the threshold voltage of the seventh transistor T7.
  • Information is written into the gate of the seventh transistor T7 to complete the compensation of the threshold voltage of the seventh transistor T7.
  • the ninth transistor T9 and the tenth transistor T10 are turned off in response to the low level on the second scan line S2, the first transistor T1 is turned off in response to the high level on the first scan line S1, and the eleventh transistor T11
  • the twelfth transistor T12 is turned on in response to the low level on the light emitting control signal line EM, and the second transistor T2 and the eighth transistor T8 are turned off in response to the low level on the light emitting control signal line EM.
  • the seventh transistor T7 generates a driving current according to the voltages of its gate electrode and the second electrode to drive the light-emitting module 13 to emit light.
  • the second transistor T2 is turned on in advance. After the first transistor T1 and the second transistor T2 are both turned on in subsequent stages, they can be equivalent to low-temperature polysilicon transistors as a whole, thereby quickly writing the data voltage to the driver. module (seventh transistor T7).
  • the second transistor T2 is an oxide transistor, in the subsequent data voltage writing and compensation stage t5, the second transistor T2 is fully turned on, which does not affect the fast writing of the data voltage and is suitable for high-frequency driving.
  • the first transistor T1 and the second transistor T2 are connected in series. After the first transistor T1 and the second transistor T2 are turned off, they are equivalent to oxide transistors, which can reduce the leakage current.
  • the second transistor T2 is closer to the side of the dual seventh transistor T7 than the first transistor T1. After the second transistor T2 is turned off, it has a strong ability to suppress leakage, which is beneficial to maintaining the stability of the gate voltage of the seventh transistor T7. At the same time, the second transistor T2 is connected in series with the first transistor T1. After the first transistor T1 is turned off, the leakage can be further suppressed, thereby improving the stability of the gate voltage of the seventh transistor T7 and improving the uniformity of the display. Therefore, a pixel drive circuit using a combination of low-temperature polysilicon transistors and oxide transistors can ensure the stability of the display panel display at both low and high refresh frequencies, which is beneficial to realizing wide-band driving of the display panel and reducing power consumption.
  • FIG. 13 is a flow chart of a driving method for a pixel circuit provided by an embodiment of the present application.
  • the pixel circuit includes a driving module 10 and a data writing module 12. and the light-emitting module 13;
  • the data writing module 12 includes a first transistor T1 and a second transistor T2 connected in series, the first transistor T1 is a low-temperature polysilicon transistor, and the second transistor T2 is an oxide transistor;
  • the driving method includes:
  • the second transistor T2 may be turned on before the data voltage writing stage so as not to affect the writing of the data voltage during the data voltage writing stage.
  • Low-temperature polysilicon transistors have high mobility and fast driving speed.
  • the first transistor T1 is a low-temperature polysilicon transistor, which can quickly write data voltage into the driving module and is suitable for high-frequency driving.
  • the off-state leakage current of the oxide transistor is small.
  • the second transistor T2 is an oxide transistor, which can reduce the leakage current, alleviate the problem of poor display effect at a low refresh frequency, and ensure the stability of the display panel.
  • a pixel driving circuit using a combination of low-temperature polysilicon transistors and oxide transistors can ensure the stability of the display panel display at both low and high refresh frequencies, which is beneficial to the wide-band driving of the display panel and reduces power consumption. Consumption.
  • the driving module drives the light-emitting module to emit light according to the data voltage.
  • the driving module 10 generates a driving current according to the data voltage, and during the light-emitting phase, the driving module 10 drives the light-emitting module 13 to emit light.
  • the pixel circuit also includes a storage module 11, a lighting control module 14 and an initialization module.
  • the initialization module includes a first initialization module 161, a second initialization module 162 and a third initialization module.
  • Initialization module 163; the storage module 11 is connected to the driving module 10, and the storage module 11 includes a first storage module 111 and a second storage module 112; the driving module 10 includes a double-gate transistor T0, a light-emitting control module 14, a double-gate transistor T0, and a light-emitting module.
  • the driving method also includes:
  • the third initialization module 163, the lighting control module 14, the second transistor T2, the first initialization module 161 and the second initialization module 162 are controlled to be turned on, and the first transistor T1 is controlled to be turned off to provide the first power supply Vdd.
  • the first power supply voltage is transmitted to the second gate B and the first pole D of the double-gate transistor T0, and the initialization voltage or the second power supply voltage provided by the initialization signal line Vref is transmitted to the second pole S and the first pole S of the double-gate transistor T0.
  • a gate G initializes the first gate G, the second gate B, the first pole D and the second pole S of the double-gate transistor T0; wherein the second power supply voltage is the voltage provided by the second power supply Vss.
  • the second transistor T2 is turned on earlier than the first transistor T1 so as not to affect the rapid writing of the data voltage in the subsequent data voltage writing stage.
  • the lighting control module 14 is controlled to be turned off, the third initialization module 163, the second transistor T2, the first initialization module 161 and the second initialization module 162 are controlled to be turned on, the second initialization module 162, the double-gate transistor T0, the A path is formed between the three initialization modules 163 and the initialization signal line Vref to complete the compensation of the threshold voltage of the dual-gate transistor T0.
  • the first power supply voltage V1 is higher than the initialization voltage Vf, so the second gate B, the second initialization module 162, the double-gate transistor T0, the third initialization module 163 and the initialization signal line Vref A path is formed between them, the charge of the second gate B flows to the second electrode S, and the voltage of the second gate B and the first electrode D decreases.
  • the threshold of the double-gate transistor T0 The voltage Vth gradually drifts forward.
  • the threshold voltage Vth is equal to 0V
  • the double-gate transistor T0 is turned off, and the second memory module 112
  • the voltage difference VBS between the second gate B and the second electrode of the double-gate transistor T0 is stored.
  • the first transistor T1, the second transistor T2 and the third initialization module 163 are controlled to be turned on, and the first initialization module 161, the second initialization module 162 and the lighting control module EM are controlled to be turned off to turn off the data line.
  • the data voltage provided by Vdata is transmitted to the driving module 10 .
  • the data voltage Vd provided by the data line Vdata is transmitted to the first gate G of the double-gate transistor T0 through the turned-on first transistor T1 and the second transistor T2.
  • the voltage of the second pole S of the double-gate transistor T0 maintains the initialization voltage Vf. changes, at this time, the voltage difference between the second gate B and the second electrode of the double-gate transistor T0 remains unchanged, and the threshold voltage Vth of the double-gate transistor T0 remains unchanged.
  • the first transistor T1, the second transistor T2, the first initialization module 161, the second initialization module 162 and the third initialization module 163 are controlled to be turned off, the light-emitting control module EM is controlled to be turned on, and the double-gate transistor T0 is controlled according to the data voltage.
  • Vd generates a driving current to drive the light-emitting module 13 to emit light.
  • a path is formed between the first power supply Vdd, the light-emitting control module 14, the double-gate transistor T0, the light-emitting module 13 and the second power supply Vss.
  • the double-gate transistor T0 generates a driving current to drive the light-emitting module 13 to emit light.
  • the pixel circuit also includes a storage module 11, a lighting control module 14, a compensation module 15 and an initialization module.
  • the storage module 11 is connected to the driving module 10; the storage module 11 includes a first storage module 111 and a second storage module.
  • the light-emitting control module 14, the driving module 10, and the light-emitting module 13 are connected in sequence between the first power supply Vdd and the second power supply Vss;
  • the first storage module 111 is connected between the data writing module 12 and the control end of the driving module 10 ;
  • the compensation module 15 is connected in parallel with the first storage module 111, or the compensation module 15 is connected between the control end and the first end of the driving module 10, and the first end of the driving module 10 is connected to the lighting control module 14;
  • the second storage module 112 is connected For data writing module 12 and drive between the second end of the driving module 10, or the second storage module 112 is connected between the first storage module 111 and the second end of the driving module 10;
  • the initialization module includes a first initialization module 161 and a second initialization module 162,
  • the first initialization module 161 is connected between the first initialization signal line Vref1 and the first end of the first storage module 111.
  • the second end of the first storage module 111 is connected to the control end
  • a transistor T1, a second transistor T2 and the second initialization module 162 are controlled to be turned off, and the compensation module 15, the first initialization module 161 and the lighting control module 14 are controlled to be turned on to turn on the first power supply Vdd.
  • the power supply voltage is transmitted between the first end and the control end of the driving module 10, the first initialization voltage on the first initialization signal line Vref1 is transmitted to the first memory module 111, and the control end, the first end and the control end of the driving module 10 are The first storage module 111 is initialized.
  • the first power supply voltage V1 provided by the first power supply Vdd is transmitted to the control terminal and the first terminal of the driving module 10 through the lighting control module 14 and the compensation module 15 to initialize it.
  • the second initialization voltage Vf2 provided by the second initialization signal line Vref2 is transmitted to the second end of the driving module 10 through the turned-on second initialization module 162 to initialize the second end of the driving module 10 .
  • the first transistor T1 and the lighting control module 14 are controlled to be turned off, the compensation module 15, the second transistor T2, the first initialization module 161 and the second initialization module 162 are controlled to be turned on, and the threshold voltage of the driving module 10 is compensated. .
  • the first end of the driving module 10 charges the second end of the driving module 10, causing the voltage of the first end of the driving module 10 to decrease until the voltages of the first end and the control end of the driving module 10 decrease to Vf2+Vth. 10 is turned off, where Vth is the threshold voltage of the driver module 10 . In the compensation stage, the second transistor T2 is turned on in advance to facilitate subsequent writing of the data voltage Vd.
  • the compensation module 15, the first initialization module 161 and the lighting control module 14 are controlled to be turned off, and the first transistor T1, the second transistor T2 and the second initialization module 162 are controlled to be turned on to provide the data line Vdata.
  • the data voltage is transmitted to the driving module 10.
  • the data voltage Vd is written into the first transistor T1 through the turned-on first transistor T1 and the second initialization module 162.
  • the voltage at the second terminal of the driving module 10 remains unchanged at the second initialization voltage Vf2 of the previous stage.
  • the first transistor T1 and the second transistor T2 can be collectively equivalent to low-temperature polysilicon transistors, thereby quickly writing the data voltage into the driving module 10 .
  • the second transistor T2 is an oxide transistor, during the data voltage writing stage, the second transistor T2 is fully turned on, which does not affect the fast writing of the data voltage.
  • the data voltage Vd can still be fully written into the driving module 10, which is beneficial to improving the display effect under high-frequency driving.
  • the first transistor T1, the second transistor T2, the first initialization module 161, the second initialization module 162 and the compensation module 15 are controlled to turn off, and the light-emitting control module 14 is controlled to turn on; the driving module 10 generates drive according to the data voltage Vd.
  • the current drives the light-emitting module 13 to emit light.
  • the driving module 10 generates a driving current according to the voltages of the control terminal and the second terminal of the driving module 10 to drive the light-emitting module 13 to emit light.
  • the second transistor T2 is an oxide transistor, which has a small leakage current when turned off during the light-emitting phase. It can ensure the stability of the control terminal voltage of the driving module 10 when the light-emitting phase is long at a low refresh frequency, which is beneficial to improving the display effect.
  • FIG 14 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel can be the mobile phone panel shown in Figure 14, or can be a panel of any electronic product with a display function, including but not Limited to the following categories: televisions, notebook computers, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, vehicle-mounted monitors, medical equipment, industrial control equipment, touch interactive terminals, etc.
  • the embodiments of this application do not make special arrangements for this limited.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

公开了一种像素电路及其驱动方法和显示面板。像素电路包括驱动模块(10)、数据写入模块(12)和发光模块(13)。数据写入模块(12)包括串联的第一晶体管(T1)和第二晶体管(T2)，第一晶体管(T1)为低温多晶硅晶体管，第二晶体管(T2)为氧化物晶体管，数据写入模块(12)设置为将数据电压(Vdata)传输至驱动模块(10)，驱动模块(10)设置为根据数据电压(Vdata)驱动发光模块发光(13)。

Description

像素电路及其驱动方法和显示面板
本申请要求在2022年8月30日提交中国专利局、申请号为202211049980.5的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及显示技术，例如涉及一种像素电路及其驱动方法和显示面板。
背景技术
有源矩阵有机发光二极体(Active-matrix Organic Light Emitting Diode，AMOLED)显示面板具有体积小，结构简单、自主发光、亮度高、画质好、可视角大、功耗低及响应速度短等优点，成为当前领域研究热点。
但是，目前中尺寸AMOLED显示面板，无法实现宽频驱动。
发明内容
本申请提供一种像素电路及其驱动方法和显示面板，以实现像素电路的宽频驱动。
第一方面，本申请实施例提供了一种像素电路，包括：驱动模块、数据写入模块和发光模块；
所述数据写入模块包括串联的第一晶体管和第二晶体管，所述第一晶体管为低温多晶硅晶体管，所述第二晶体管为氧化物晶体管，所述数据写入模块设置为将数据电压传输至所述驱动模块；
所述驱动模块设置为根据所述数据电压驱动所述发光模块发光。
第二方面，本申请实施例还提供了一种像素电路的驱动方法，所述像素电路包括驱动模块、数据写入模块和发光模块；所述数据写入模块包括串联的第一晶体管和第二晶体管，所述第一晶体管为低温多晶硅晶体管，所述第二晶体 管为氧化物晶体管；
所述驱动方法包括：
在数据写入阶段，控制所述第一晶体管和所述第二晶体管导通，所述第二晶体管早于所述第一晶体管导通，以将所述数据线提供的数据电压传输至所述驱动模块；
在发光阶段，控制所述第一晶体管和所述第二晶体管关断；所述驱动模块根据所述数据电压驱动所述发光模块发光。
第三方面，本申请实施例还提供了一种显示面板，包括本申请任一实施例所提供的像素电路。
本申请实施例提供的像素电路包括驱动模块、数据写入模块和发光模块。数据写入模块包括串联的第一晶体管和第二晶体管，第一晶体管为低温多晶硅晶体管，第二晶体管为氧化物晶体管，数据写入模块设置为将数据电压传输至驱动模块，驱动模块设置为根据数据电压驱动发光模块发光。低温多晶硅晶体管具有高迁移率和较快的驱动速度，第一晶体管为低温多晶硅晶体管，可以快速的将数据电压写入驱动模块中，适用于高频驱动。氧化物晶体管关态漏电流小，第二晶体管为氧化物晶体管可以降低漏电流的大小，缓解漏电时间长造成的显示效果较差的问题，保证显示面板显示的稳定性。因此，本实施例中采用低温多晶硅晶体管和氧化物晶体管相互结合的像素驱动电路，有利于显示面板的宽频驱动，降低功耗。
附图说明
图1为本申请实施例提供的一种像素电路的结构示意图；
图2为本申请实施例提供的另一种像素电路的结构示意图；
图3为本申请实施例提供的另一种像素电路的结构示意图；
图4为本申请实施例提供的一种像素电路的驱动时序图；
图5为本申请实施例提供的另一种像素电路结构示意图；
图6为本申请实施例提供的另一种像素电路结构示意图；
图7为本申请实施例提供的另一种像素电路的驱动时序图；
图8为本申请实施例提供的另一种像素电路结构示意图；
图9为本申请实施例提供的一种双栅晶体管的特性曲线；
图10为本申请实施例提供的另一种像素电路结构示意图；
图11为本申请实施例提供的另一种像素电路结构示意图；
图12为本申请实施例提供的另一种像素电路的驱动时序图；
图13为本申请实施例提供的一种像素电路的驱动方法的流程图；
图14为本申请实施例提供的一种显示面板的结构示意图。
具体实施方式
下面结合附图和实施例对本申请作详细说明。
相关技术中的像素电路不能满足宽频驱动的要求，出现上述问题的原因在于，显示面板若选用低温多晶硅(Low Temperature Poly-silicon，LTPS)像素电路进行驱动，因低温多晶硅晶体管漏电流较大，与驱动晶体管连接的晶体管如果处于关断状态的时间较长，则其漏电时间长，造成驱动晶体管的栅极电压不稳定，导致显示亮度不均的现象较为严重。若选用纯氧化物电路进行驱动，像素电路中晶体管均为氧化物晶体管，因氧化物晶体管迁移率较低，在高刷新频率下，数据电压的写入不充分，影响显示效果。
本申请实施例提供一种新型像素电路结构，以实现宽频显示。图1为本申请实施例提供的一种像素电路的结构示意图，参考图1，本申请实施例提供的像素电路包括驱动模块10、数据写入模块12和发光模块13。
数据写入模块12包括串联的第一晶体管T1和第二晶体管T2，第一晶体管T1为低温多晶硅晶体管，第二晶体管T2为氧化物晶体管，数据写入模块12设置为将数据电压传输至驱动模块10。
驱动模块11设置为根据数据电压驱动发光模块13发光。
像素电路还包括存储模块11和至少一个发光控制模块14，存储模块11连接驱动模块10，存储模块11设置为存储数据电压，发光控制模块14设置为控制驱动模块10与第一电源Vdd或者第二电源Vss中的至少一个是否连通。换句话说，发光控制模块14设置为控制第一电源Vdd、发光模块13和第二电源Vss之间是否形成通路。本实施例中，示例性示出发光控制模块14和驱动模块10连接于第一电源Vdd和第二电源Vss之间。示例性的，第一晶体管T1的栅极连接第一扫描线S1，第二晶体管T2的栅极连接第二扫描线S2，第一晶体管T1响应第一扫描线S1上的信号导通或者关断，第二晶体管T2响应第二扫描线S2上的信号导通或者关断。
示例性的，在本实施例中，像素电路在显示一帧画面的时间内，工作阶段可以至少包括数据电压写入阶段和发光阶段。在数据电压写入阶段，第一晶体管T1、第二晶体管T2均导通，将数据电压传输至驱动模块10，第一晶体管T1为低温多晶硅晶体管，迁移率高，可以快速的将数据电压写入驱动模块中，适用于高刷新频率下，数据电压写入阶段时间短的情况。发光阶段，第一晶体管T1、第二晶体管T2关断，发光控制模块14导通，第一电源Vdd、发光控制模块14、驱动模块10、发光模块13和第二电源Vss之间形成通路，驱动模块10根据数据电压产生驱动电流，驱动发光模块13发光。第二晶体管T2为氧化物晶体管，例如铟镓锌氧化物(indium gallium zinc oxide，IGZO)晶体管，在发光阶段，其关态下的漏电流较小，因此像素电路在低刷新频率下，发光阶段时间较长时，可以降低漏电流的大小，保持驱动模块10的控制端电压的稳定，有利于提高显示效果。
低温多晶硅晶体管具有高迁移率和较快的驱动速度，第一晶体管为低温多晶硅晶体管，可以快速的将数据电压写入驱动模块中，适用于高频驱动。氧化物晶体管关态漏电流小，第二晶体管为氧化物晶体管可以降低漏电流的大小，缓解漏电时间长造成的显示效果较差的问题，保证显示面板显示的稳定性。因此，本实施例中采用低温多晶硅晶体管和氧化物晶体管相互结合的像素驱动电 路，有利于实现显示面板的宽频驱动，降低功耗，有利于改善显示效果。
继续参考图1，可选的，在像素电路的一显示周期，第二晶体管T2先于第一晶体管T1导通，并且第一晶体管T1在第二晶体管T2导通的期间内导通。
示例性的，第二晶体管T2可以在数据电压写入阶段之前导通，第一晶体管T1和第二晶体管T2在数据电压写入阶段，可以整体等效成低温多晶硅晶体管，从而将数据电压快速写入驱动模块10中。虽然第二晶体管T2是氧化物晶体管，但是在数据电压写入阶段，第二晶体管T2已完全导通，不影响数据电压的快速写入。
继续参考图1，可选的，第一晶体管T1和第二晶体管T2依次串联连接于数据线Vdata和驱动模块10之间。
第一晶体管T1和第二晶体管T2串联连接，第一晶体管T1和第二晶体管T2关断后整体等效于氧化物晶体管，可以降低漏电流的大小。第二晶体管T2相较于第一晶体管T1更靠近驱动模块10一侧，第二晶体管T2关断后，抑制漏电的能力较强，有利于维持驱动模块10控制端(即与第二晶体管T2连接的一端)的电压的稳定。同时，第二晶体管T2又与第一晶体管T1串联，第一晶体管T1关断后，可以进一步抑制漏电，从而提高驱动模块10的控制端的电压的稳定性，提高显示的均一性。
图2为本申请实施例提供的另一种像素电路的结构示意图，参考图2，可选的，像素电路还包括存储模块11、发光控制模块14和初始化模块；存储模块11连接驱动模块10，设置为存储数据电压，存储模块11包括第一存储模块111和第二存储模块112；驱动模块10包括双栅晶体管T0，发光控制模块14、双栅晶体管T0、发光模块13依次连接于第一电源Vdd和第二电源Vss之间，双栅晶体管T0的第一极D连接发光控制模块14，双栅晶体管T0的第二极S连接发光模块13；
数据写入模块12连接于双栅晶体管T0的第一栅极G与数据线Vdata之间，数据写入模块12设置为向第一栅极G传输数据线Vdata输出的数据电压；
第一存储模块111连接于双栅晶体管T0的第一栅极G和第二极S之间，第一存储模块111设置为存储第一栅极G的电压，第二存储模块112连接于双栅晶体管T0的第二栅极B和第二极S之间，第二存储模块112设置为存储第二栅极B的电压；
初始化模块设置为对双栅晶体管T0的第一栅极G、第二栅极B、第一极D和第二极S进行初始化。
双栅晶体管T0作为该像素电路的驱动模块10，驱动发光模块13发光。其中，双栅晶体管T0通常为垂直型双栅晶体管，第一栅极G可以为顶栅，第二栅极B可以为底栅。可以通过设置双栅晶体管T0的第二栅极B与第二极S之间的电压来调节双栅晶体管T0的阈值电压。
初始化模块可以包括多个晶体管，例如与第二栅极B连接的晶体管，以对第二栅极B进行初始化，还可以包括与双栅晶体管T0的第一极D连接的晶体管，以对第一极D进行初始化，还可以包括与双栅晶体管T0的第一栅极G和第二极S连接的晶体管，以对第一栅极G和第二极S进行初始化。
继续参考图2，可选的，初始化模块包括第一初始化模块161、第二初始化模块162和第三初始化模块163，第一初始化模块161连接于双栅晶体管T0的第一栅极G和第二极S之间，第二初始化模块162连接于双栅晶体管T0的第二栅极B与第一极D之间。
第三初始化模块163连接于双栅晶体管T0的第二极S和初始化信号线Vref之间。
本实施例中，像素电路的工作过程可以包括初始化阶段、补偿阶段、数据电压写入阶段和发光阶段。第一初始化模块161、第二初始化模块162和第三初始化模块163分别连接于不同的扫描线，且响应各自连接的扫描线上的信号导通或关断。发光控制模块14与发光控制信号线连接，响应发光控制信号线上的信号导通或关断。第一晶体管T1响应第一扫描线S1上的信号导通或关断，第二晶体管T2响应第二扫描线S2上的信号导通或关断。示例性的，以第一初始 化模块161为例，第一初始化模块161导通即指双栅晶体管T0的第二极S与第一栅极G之间连通，第一初始化模块161关断即指双栅晶体管T0的第二极S与第一栅极G之间的连接断开。示例性的，在初始化阶段，控制第一初始化模块161、第二初始化模块162、第三初始化模块163、发光控制模块14和第二晶体管T2导通，控制第一晶体管T1关断。初始化信号线Vref上的初始化电压经导通的第三初始化模块163传输至双栅晶体管T0的第二极S，且再经第一初始化模块161传输至双栅晶体管T0的第一栅极G，以实现对第一栅极G、第二极S以及发光模块13的第一端的初始化。第一电源Vdd提供的第一电源电压V1经导通的发光控制模块14传输至双栅晶体管T0的第一极D，再经导通的第二初始化模块162传输至双栅晶体管T0的第二栅极B，实现对双栅晶体管T0的第一极D和第二栅极B的初始化。在初始化阶段，第二晶体管T2提前导通，第一晶体管T1和第二晶体管T2在后续阶段均导通后，可以整体等效成低温多晶硅晶体管，从而将数据电压快速写入驱动模块10中。虽然第二晶体管T2是氧化物晶体管，但是在后续数据电压写入阶段，第二晶体管T2已完全导通，不影响数据电压的快速写入。值得注意的是，在初始化阶段，第二栅极B的电压为第一电源电压V1，第一电源电压V1为高电平，使得双栅晶体管T0的阈值电压Vth小于0，此时双栅晶体管T0的第一栅极G、和第二极S之间的电压差大于阈值电压Vth，双栅晶体管T0导通。
在补偿阶段，控制第一晶体管T1和发光控制模块14关断，控制第一初始化模块161、第二初始化模块162、第三初始化模块163、双栅晶体管T0和第二晶体管T2导通。由于第二栅极B的电压为第一电源电压V1，第一电源电压V1高于初始化信号线Vref上的初始化电压Vf，因此在第二栅极B、第二初始化模块162、双栅晶体管T0、第三初始化模块163和初始化信号线Vref之间形成通路，第二栅极B的电荷向第二极S流动，第二栅极B和第一极D的电压降低。随着第二栅极B的电压降低，双栅晶体管T0的阈值电压Vth逐渐正漂，当阈值电压Vth增大至0V时，双栅晶体管T0的第一栅极G和第二极S的电压差 VGS＝Vth＝0，双栅晶体管T0关断，第二存储模块112存储双栅晶体管T0的第二栅极B和第二极S的电压差VBS。
在数据电压写入阶段，控制第一晶体管T1、第二晶体管T2和第三初始化模块163导通，控制第一初始化模块161、第二初始化模块162和发光控制模块14关断，数据线Vdata提供的数据电压Vd经导通的第一晶体管T1和第二晶体管T2传输至双栅晶体管T0的第一栅极G，第一栅极G的电压VG＝Vd，双栅晶体管T0的第二极S的电压VS＝Vf，此时双栅晶体管T0的第二栅极B和第二极S的电压差VBS不变，双栅晶体管T0的阈值电压Vth不变。第一晶体管T1为低温多晶硅晶体管，迁移率高，可在数据电压写入阶段快速地将数据电压写入双栅晶体管T0的第一栅极，有利于高频驱动。
在发光阶段，控制发光控制模块14导通，控制第一晶体管T1、第二晶体管T2、第一初始化模块161、第二初始化模块162和第三初始化模块163关断，双栅晶体管T0根据数据电压Vd产生驱动电流驱动发光模块13发光。在发光阶段，第二晶体管T2处于关断状态，而第二晶体管T2为氧化物晶体管，关态下漏电流较小，发光阶段较长时，第二晶体管T2可以提高第一栅极G电位的稳定性，进而提高显示的均一性，降低功耗。
可选的，初始化信号线上的信号由第二电源提供。
初始化信号线上的信号可以为初始化电压，也可以为由第二电源提供的第二电源电压。初始化信号线上的信号由第二电源提供可以节省信号线的数量，简化驱动IC的结构设计。
图3为本申请实施例提供的另一种像素电路的结构示意图，参考图2和图3，可选的，第一栅极G为顶栅，第二栅极B为底栅；第一初始化模块161包括第三晶体管T3，第二初始化模块162包括第四晶体管T4，第三初始化模块163包括第五晶体管T5，发光控制模块14包括第六晶体管T6；第一存储模块111包括第一电容C1，第二存储模块112包括第二电容C2。
第一晶体管T1的第一极连接数据线Vdata，第一晶体管T1的第二极连接第 二晶体管T2的第一极，第一晶体管T1的栅极连接第一扫描线S1，第二晶体管T2的第二极连接双栅晶体管T0的第一栅极G，第二晶体管T2的栅极连接第二扫描线S2。
第三晶体管T3的第一极连接双栅晶体管T0的第二极S，第三晶体管T3的第二极连接双栅晶体管T0的第一栅极G，第三晶体管T3的栅极连接第三扫描线S3，第四晶体管T4的第一极连接双栅晶体管T0的第一极D，第四晶体管T4的第二极连接双栅晶体管T0的第二栅极B，第四晶体管T4的栅极连接第三扫描线S3。
第五晶体管T5的第一极连接初始化信号线Vref，第五晶体管T5的第二极连接双栅晶体管T0的第二极S，第五晶体管T5的栅极连接第二扫描线S2。
第六晶体管T6的第一极连接第一电源Vdd，第六晶体管T6的第二极连接双栅晶体管T0的第一极D，第六晶体管T6的栅极连接发光控制信号线EM。
第一电容C1连接于双栅晶体管T0的第一栅极G和第二极S之间，第二电容C2连接于双栅晶体管T0的第二栅极B和第二极S之间。
继续参考图3，可选的，第六晶体管T6为低温多晶硅晶体管，双栅晶体管T0、第三晶体管T3、第四晶体管T4和第五晶体管T5均为氧化物晶体管。
图4为本申请实施例提供的一种像素电路的驱动时序图，图4所示的驱动时序图可适用于图3所示的像素电路。本实施例中，示例性示出第一晶体管T1和第六晶体管T6为P型晶体管，双栅晶体管T0、第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5为N型晶体管。
可选的，像素电路的工作过程可以包括初始化阶段t1、补偿阶段t2、数据电压写入阶段t3和发光阶段t4。示例性的，在初始化阶段t1，第二扫描线S2上的信号为高电平，控制第二晶体管T2和第五晶体管T5导通。第三扫描线S3上的信号为高电平，控制第三晶体管T3和第四晶体管T4导通。发光控制信号线EM上的信号为低电平，控制第六晶体管T6导通。第一扫描线S1上的信号为高电平，控制第一晶体管T1关断。导通的第五晶体管T5和第三晶体管T3 将初始化信号线Vref上的初始化电压Vf传输至发光模块13的第一端和双栅晶体管T0的第一栅极G，完成对第一栅极G、第二极S和发光模块13第一端的初始化。导通的第六晶体管T6和第四晶体管T4将第一电源Vdd提供的第一电源电压V1传输至双栅晶体管T0的第一极D和第二栅极B，完成对第二栅极B和第一极D的初始化。第二晶体管T2在初始化阶段t1提前导通，虽然第二晶体管T2是氧化物晶体管，但是在后续数据电压写入阶段t3，第二晶体管T2已完全导通，数据电压Vd经第一晶体管T1可以快速写入双栅晶体管T0的第一栅极G。
在补偿阶段t2，第二扫描信号S2为高电平，控制第二晶体管T2和第五晶体管T5导通。第三扫描线S3上的信号为高电平，控制第三晶体管T3和第四晶体管T4导通。发光控制信号线EM上的信号为高电平，控制第六晶体管T6关断。第一扫描线S1上的信号为高电平，控制第一晶体管T1关断。第六晶体管T6关断后，第二电容C2将第一电源电压V1存储在第二电容C2的第一端。第二栅极B、第四晶体管T4、双栅晶体管T0、第五晶体管T5和初始化信号线Vref之间形成通路，双栅晶体管T0的第一极D和第二栅极B的电压降低，随着第二栅极B的电压的降低，双栅晶体管T0的阈值电压Vth逐渐正漂，当阈值电压Vth等于0V时，双栅晶体管T0的第一栅极G和第二极S的电压差VGS＝Vth＝0，双栅晶体管T0关断，第二电容C2存储双栅晶体管T0的第二栅极B和第二极的电压差VBS。
在数据电压写入阶段t3，第二扫描信号S2为高电平，控制第二晶体管T2和第五晶体管T5导通。第三扫描线S3上的信号为低电平，控制第三晶体管T3和第四晶体管T4关断。发光控制信号线EM上的信号为高电平，控制第六晶体管T6关断。第一扫描线S1上的信号为低电平，控制第一晶体管T1导通。导通的第一晶体管T1和第二晶体管T2将数据电压Vd传输至第一栅极G，导通的第五晶体管T5将初始化电压Vref传输至双栅晶体管T0的第二极S。第一晶体管T1为低温多晶硅晶体管，迁移率高，可以快速的将数据电压Vd写入双栅晶体 管T0中，在高刷新频率下，数据电压写入阶段t3的时间短时，依然能将数据电压Vd充分写入双栅晶体管T0中，有利于实现高频驱动。
在发光阶段t4，第二扫描信号S2为低电平，控制第二晶体管T2和第五晶体管T5关断。第三扫描线S3上的信号为低电平，控制第三晶体管T3和第四晶体管T4关断，第一扫描线S1信号为高电平，控制第一晶体管T1关断。发光控制信号线EM上的信号为低电平，控制第六晶体管T6导通，双栅晶体管T0根据其第一栅极G和第二极S的电压产生驱动电流，驱动发光模块13发光。发光模块13导通后，双栅晶体管T0的第二极S的电压VS＝V2+Voled，其中Voled为发光模块13的跨压，V2为第二电源Vss提供的第二电源电压。在发光阶段t4，第二极S的电压抬升量Δ1＝V2+Voled-Vf，因第一电容C1的耦合作用，第一栅极G也被抬升Δ1，此时第一栅极G的电压VG＝Vd+Δ1＝Vd+V2+Voled-Vf。虽然在第二电容C2的耦合作用下，第二栅极B的电压也会被抬升，但是第二栅极B和第二极S的电压差VBS不变，因此双栅晶体管T0的阈值电压Vth＝0不变。
在发光阶段，双栅晶体管T0的驱动电流I＝K*(VGS-Vth)2＝K[(Vd+V2+Voled-Vf)-(V2+Voled)]2＝K*(Vd-Vf)2，其中，K＝1/2*μ*Cox*W/L，μ为双栅晶体管T0的迁移率，Cox为栅绝缘层电容，W/L为双栅晶体管T0的宽长比。由上式可知，最后的驱动电流与双栅晶体管T0的阈值电压Vth、第二电源电压V2以及发光模块13的跨压均没有关系，因此本实施例提供的像素电路可以补偿双栅晶体管T0的阈值电压不均匀、第二电源电压V2的IR drop的问题，以及因发光模块13老化导致的不同发光模块13的跨压Voled不同造成的发光不均的问题，有利于提高显示效果。
示例性的，与双栅晶体管T0连接的第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5均为氧化物晶体管，氧化物晶体管关态下漏电流较小，可以保证第一栅极G的电位的稳定，有利于提高显示效果。且第一晶体管T1为低温多晶硅晶体管，可以在高频下，快速的将数据电压写入双栅晶体管T0中，有利于实现高频驱动。即本实施例提供的像素电路可以实现宽频驱动。双 栅晶体管T0为氧化物晶体管，长程均一性好，适合中大尺寸显示，亮度均一性高。第六晶体管T6为低温多晶硅晶体管，负偏置温度应力(Negative Bias Temperature Stress，NBTS)稳定性好，跨压小，有利于降低功耗。
图5为本申请实施例提供的另一种像素电路的结构示意图，参考图5，可选的，像素电路还包括存储模块11、发光控制模块14、补偿模块15和初始化模块，存储模块11包括第一存储模块111和第二存储模块112；发光控制模块14、驱动模块10、发光模块13依次连接于第一电源Vdd和第二电源Vss之间。
第一存储模块111连接于数据写入模块12和驱动模块10的控制端之间；第一存储模块111设置为将数据电压耦合至驱动模块10。
补偿模块15连接于驱动模块10的控制端和第一端之间，驱动模块10的第一端连接发光控制模块14。
第二存储模块112连接于数据写入模块12和驱动模块10的第二端之间，或者，第二存储模块112连接于第一存储模块111和驱动模块10的第二端之间，第二存储模块112设置为将驱动模块10的第二端的电压耦合至第一存储模块111。
初始化模块设置为对第一存储模块111和第二存储模块112进行初始化。
初始化模块可以包括多个晶体管，至少一个晶体管与第一存储模块111连接，设置为对第一存储模块111进行初始化，至少一个晶体管与第二存储模块112连接，设置为对第二存储模块112进行初始化。
继续参考图5，可选的，初始化模块包括第一初始化模块161和第二初始化模块162，第一初始化模块161连接于第一初始化信号线Vref1和第一存储模块111的第一端之间，第一存储模块111的第二端与驱动模块10的控制端连接。
第二初始化模块162连接于第二初始化信号线Vref2和驱动模块10的第二端之间。
第一初始化模块161导通后，将第一初始化信号线Vref1提供的第一初始化电压Vf1传输至第一存储模块111的第一端，对第一存储模块111进行初始化。 第二初始化模块162导通后，将第二初始化信号线Vref2提供的第二初始化电压Vf2传输至第二存储模块112的第二端，对第二存储模块112进行初始化。
示例性的，第一晶体管T1的栅极连接第一扫描线S1，第二晶体管T2的栅极可以连接发光控制信号线EM。像素电路可以包括初始化阶段、补偿阶段、数据电压写入阶段和发光阶段。在初始化阶段，控制补偿模块15、第一初始化模块161、发光控制模块14导通，控制第一晶体管T1、第二晶体管T2和第二初始化模块162关断，第一电源Vdd提供的第一电源电压V1经发光控制模块14传输至驱动模块10的第一端，再经导通的补偿模块15传输至驱动模块10的控制端，对控制端和第一端进行初始化。
在补偿阶段，控制发光控制模块14和第一晶体管T1关断，控制第一初始化模块161、第二晶体管T2、补偿模块15和第二初始化模块162导通，驱动模块10(包括驱动晶体管)的第一端向驱动模块10的第二端充电，使得驱动模块10的第一端和控制端的电压降低，直至驱动模块10的第一端和控制端的电压降低至Vf2+Vth时，驱动模块10关断，其中Vth为驱动模块10包括的驱动晶体管的阈值电压。第一晶体管T1和第二晶体管T2在后续阶段均导通后，可以整体等效成低温多晶硅晶体管，从而将数据电压快速写入驱动模块10中。虽然第二晶体管T2是氧化物晶体管，但是在后续数据电压写入阶段，第二晶体管T2已完全导通，不影响数据电压的快速写入。
在数据电压写入阶段，控制发光控制模块14、补偿模块15和第一初始化模块161关断，控制第一晶体管T1、第二晶体管T2和第二初始化模块162导通，数据电压Vd经导通的第一晶体管T1、第二晶体管T2写入第一存储模块111的第一端。驱动模块10的第二端的电压维持上一阶段的第二初始化电压Vf2不变。第一晶体管T1为低温多晶硅晶体管，迁移率高，可以快速的将数据电压Vd写入驱动模块10中，在高刷新频率下，数据电压写入阶段的时间短时，依然能将数据电压Vd充分写入驱动模块10中，有利于提高高频驱动下的显示效果。
在发光阶段，控制补偿模块15、第一初始化模块161、第二初始化模块162、 第一晶体管T1和第二晶体管T2关断，控制发光控制模块14导通，驱动模块10根据其控制端和第二端的电压产生驱动电流驱动发光模块13发光。第二晶体管T2为氧化物晶体管，在发光阶段，自身关断时漏电流较小，可以在低刷新频率下发光阶段较长时，保证驱动模块10控制端电压的稳定，有利于提高低频驱动下的显示效果。
综上，像素电路有利于实现宽频显示。
在其他实施例中，可选的，补偿模块15与第一存储模块111并联，其他模块的连接关系可继续参考图5，补偿模块15与第一存储模块111并联时，是通过第一初始化电压Vf1对驱动模块10的控制端进行初始化，其他过程与图5所示的像素电路相同，本实施例在此不再赘述。
图6为本申请实施例提供的另一种像素电路的结构示意图，参考图5和图6，可选的，驱动模块10包括第七晶体管T7、补偿模块15包括第八晶体管T8，第一初始化模块161包括第九晶体管T9，第二初始化模块162包括第十晶体管T10，发光控制模块14包括第十一晶体管T11；第一存储模块111包括第一电容C1，第二存储模块112包括第二电容C2。
第一晶体管T1的第一极连接数据线Vdata，第一晶体管T1的第二极连接第二晶体管T2的第一极，第二晶体管T2的第二极与第一电容C1的第一端连接，第一晶体管T1的栅极连接第一扫描线S1，第二晶体管T2的栅极连接发光控制信号线EM。
第九晶体管T9的第一极与第一初始化信号线Vref1连接，第九晶体管T9的第二极与第一电容C1的第一端连接，第九晶体管T9的栅极连接第二扫描线S2，第一电容C1的第二端与第七晶体管T7的栅极电连接。
第八晶体管T8的第一极与第七晶体管T7的第一极连接，第八晶体管T8的第二极与第七晶体管T7的栅极连接，第八晶体管T8的栅极与第二扫描线连接S2。
第二电容C2的第一端与第一电容C1的第一端连接，第二电容C2的第二 端与第七晶体管T7的第二极连接。
第十晶体管T10的第一极与第二初始化信号线Vref2连接，第十晶体管T10的第二极与第七晶体管T7的第二极连接，第十晶体管T10的栅极与发光控制信号线EM连接。
第十一晶体管T11的第一极与第一电源Vdd连接，第十一晶体管T11的第二极与第七晶体管T7的第一极连接，第十一晶体管T11的栅极与发光控制信号线EM连接。
可选的，第十一晶体管T11为低温多晶硅晶体管，第七晶体管T7、第八晶体管T8、第九晶体管T9和第十晶体管T10均为氧化物晶体管。
图7为本申请实施例提供的另一种像素电路的驱动时序图，图7所示的驱动时序可适用于图6所示的像素电路，可选的，第一晶体管T1和第十一晶体管T11为P型晶体管，第二晶体管T2、第七晶体管T7、第八晶体管T8、第九晶体管T9和第十晶体管T10均为N型晶体管。参考图6和图7，本实施例提供的像素电路的工作过程包括初始化阶段t1、补偿阶段t2、数据电压写入阶段t3和发光阶段t4。
在初始化阶段t1，第一扫描线S1上的信号为高电平，控制第一晶体管T1关断。第二扫描线S2上的信号为高电平，控制第八晶体管T8和第九晶体管T9导通。发光控制信号线EM上的信号为低电平，控制第二晶体管T2和第十晶体管T10关断、第十一晶体管T11导通。第一初始化信号线Vref1提供的第一初始化电压Vf1经导通的第九晶体管T9传输至第一电容C1和第二电容C2的第一端。第一电源Vdd提供的第一电源电压V1经导通的第十一晶体管T11和第八晶体管T8传输至第七晶体管T7的第一极和栅极。第一电源电压V1传输至第七晶体管T7的栅极后，第七晶体管T7导通，有电流流过发光模块13，但是发光模块13在此阶段发光的时间非常短，发光模块13即使发光也不影响对比度。
在补偿阶段t2，第一扫描线S1上的信号为高电平，控制第一晶体管T1关 断。第二扫描线S2上的信号为高电平，控制第八晶体管T8和第九晶体管T9导通。发光控制信号线EM上的信号为高电平，控制第二晶体管T2和第十晶体管T10导通、第十一晶体管T11关断。第一电容C1的第一端的电压维持第一初始化电压Vf1不变，第二初始化信号线Vref2提供的第二初始化电压Vf2传输至第七晶体管T7的第二极。第七晶体管T7的第一极的电荷会向第二极流动，使得第七晶体管T7的第一极和栅极的电压降低，直至降低至Vf2+Vth时，第七晶体管T7关断，其中Vth为第七晶体管T7的阈值电压。第二晶体管T2在补偿阶段导通，第一晶体管T1和第二晶体管T2在后续阶段均导通后，可以整体等效成低温多晶硅晶体管，从而将数据电压快速写入第七晶体管T7中。虽然第二晶体管T2是氧化物晶体管，但是在后续数据电压写入阶段t3，第二晶体管T2已完全导通，不影响数据电压的快速写入。
在数据电压写入阶段t3，第一扫描线S1上的信号为低电平，控制第一晶体管T1导通。第二扫描线S2上的信号为低电平，控制第八晶体管T8和第九晶体管T9关断。发光控制信号线EM上的信号为高电平，控制第二晶体管T2和第十晶体管T10导通、第十一晶体管T11关断。第一电容C1第一端的电压变为数据电压Vd，即第一电容C1第一端的电压抬升量Δ2＝Vd-Vf1，因第一电容C1的耦合作用，第一电容C1的第二端的电压也被抬升Δ2，此时，第七晶体管T7的栅极电压Vg＝Vf2+Vth+Vd-Vf1。第七晶体管T7的第二极维持第二初始化电压Vf2。第一晶体管T1为低温多晶硅晶体管，迁移率高，可以快速的将数据电压Vd写入第七晶体管T7中，在高刷新频率下，数据电压写入阶段t3的时间短时，依然能实现数据电压Vd的充分写入，有利于提高高频驱动的显示效果。
在发光阶段t4，第一扫描线S1上的信号为高电平，控制第一晶体管T1关断。第二扫描线S2上的信号为低电平，控制第八晶体管T8和第九晶体管T9关断。发光控制信号线EM上的信号为低电平，控制第二晶体管T2和第十晶体管T10关断、第十一晶体管T11导通。第一电源电压V1经导通的第十一晶体管T11传输至第七晶体管T7的第一极，第七晶体管T7根据其栅极和第二极的电 压产生驱动电流，驱动发光模块13发光。发光模块13导通后，第七晶体管T7的第二极的电压Vs＝V2+Voled，其中，Voled为发光模块13的跨压。第二电容C2的第二端的电压抬升量Δ3＝V2+Voled-Vf2，因第二电容C2的耦合作用，第一电容C1的第一端的电压Vn＝Vd+V2+Voled-Vf2，第一电容C1的第一端的电压被抬升，抬升量Δ2＝V2+Voled-Vf2，因第一电容C1的耦合作用，第七晶体管T7的栅极被抬升Δ2，此时第七晶体管T7的栅极电压Vg＝Vf2+Vth+Vd-Vf1+V2+Voled-Vf2＝Vth+Vd-Vf1+V2+Voled。驱动电流I＝K*(Vgs-Vth)2＝K[(Vth+Vd-Vf1+V2+Voled)-(V2+Voled)-Vth]2＝K*(Vd-Vf1)2，其中，K＝1/2*μ*Cox*W/L,μ为第七晶体管T7的迁移率，Cox为栅绝缘层电容，W/L为第七晶体管T7的宽长比。由上式可知，最后的驱动电流值与第七晶体管T7的阈值电压Vth、第二电源电压V2以及发光模块13的跨压均没有关系，因此本实施例提供的像素电路可以补偿第七晶体管T7的阈值电压不均匀、第二电源Vss的IR drop的问题，以及因发光模块13老化导致的不同发光模块13的跨压Voled不同造成的发光不均的问题，有利于提高显示效果。
第七晶体管T7为氧化物晶体管，长程均一性好，适合中大尺寸显示，亮度均一性高。第二晶体管T2、第八晶体管T8、第九晶体管T9和第十晶体管T10均为氧化物晶体管，关态下漏电流小，使得第七晶体管T7的栅极电压保持率高，可以降低功耗。第一晶体管T1为低温多晶硅晶体管，可以在高频下、数据电压写入时间较短时，快速将数据电压写入驱动模块中，提高高频驱动的效果，即本实施例中的像素电路可以实现宽频驱动。第十一晶体管T11为低温多晶硅晶体管，NBTS稳定性好，跨压小，有利于降低功耗。
图8为本申请实施例提供的另一种像素电路的结构示意图，参考图8，可选的，第八晶体管T8的第一极与第九晶体管T9的第二极连接，第八晶体管T8的第二极与第一电容C1的第二端连接，第二电容C2的第一端与第一电容C1的第一端连接，第二电容C2的第二端与第七晶体管T7的第二极连接。其他晶体管的连接关系同图6中，本实施例在此不再赘述。图7所示的驱动时序同样 适用于图8所示的像素电路。图8所示的像素电路的工作过程与图6所示的像素电路的工作过程唯一的区别在于，在初始化阶段t1，通过第一初始化电压Vf1对第七晶体管T7的栅极进行初始化，使得在初始化阶段t1，第七晶体管T7不会导通，发光模块13不会发光，有利于提高显示效果。
图9为本申请实施例提供的另一种像素电路的结构示意图，参考图9，可选的，第八晶体管T8的第一极与第七晶体管T7的第一极连接，第八晶体管T8的第二极与第七晶体管T7的栅极连接。第二电容C2的第一端与第七晶体管T7的栅极连接，第二电容C2的第二端与第七晶体管T7的第二极连接，其他晶体管的连接关系同图6中，在此不再赘述。图7所示的驱动时序同样适用于图9所示的像素电路。图9所示的像素电路的初始化阶段t1和补偿阶段t2与图6所示的像素电路相同。图9所示的像素电路，在数据电压写入阶段t3，第七晶体管T7的栅极电压Vg＝Vf2+Vth+a(Vd-Vf1)，其中，a＝Cs1/(Cs1+Cs2)，Cs1为第一电容C1的电容值，Cs2为第二电容C2的电容值。发光阶段t4，Vg＝Vf2+Vth+a(Vd-Vf1)+V2+Voled-Vf2＝Vth+a(Vd-Vf1)+V2+Voled，驱动电流I＝K(a(Vd-Vf1))2。
图10为本申请实施例提供的另一种像素电路的结构示意图，参考图10，可选的，第八晶体管T8的第一极与第九晶体管T9的第二极连接，第八晶体管T8的第二极与第一电容C1的第二端连接。第二电容C2的第一端与第七晶体管T7的栅极连接，第二电容C2的第二端与第七晶体管T7的第二极连接。图7所示的驱动时序同样适用于图10所示的像素电路。图10所示的像素电路，在初始化阶段与图6区别在于，通过第一初始化电压Vf1对第七晶体管T7的栅极进行初始化，补偿阶段t2与图6相同。图10所示的像素电路，在数据电压写入阶段t3，第七晶体管T7的栅极电压Vg＝Vf2+Vth+a(Vd-Vf1)，其中，a＝Cs1/(Cs1+Cs2)，Cs1为第一电容C1的电容值，Cs2为第二电容C2的电容值。发光阶段t4，Vg＝Vf2+Vth+a(Vd-Vf1)+V2+Voled-Vf2＝Vth+a(Vd-Vf1)+V2+Voled，驱动电流I＝K(a(Vd-Vf1))2。
图11为本申请实施例提供的另一种像素电路的结构示意图，参考图11，可选的，像素电路还包括存储模块、发光控制模块、补偿模块和初始化模块，发光控制模块包括第十一晶体管T11和第十二晶体管T12、驱动模块包括第七晶体管T7、补偿模块包括第八晶体管T8、初始化模块包括第九晶体管T9和第十晶体管T10、存储模块包括第一电容C1。第十一晶体管T11的第一极与第一电源Vdd连接，第十一晶体管T11的第二极与第七晶体管T7的第一极连接，第七晶体管T7的第二极与第十二晶体管T12的第一极连接，第十二晶体管T12的第二极与发光模块13的第一端连接，发光模块13的第二端与第二电源Vss连接。第十一晶体管T11和第十二晶体管T12的栅极均连接发光控制信号线EM。第八晶体管T8的第一极与第七晶体管T7的第二极连接，第八晶体管T8的第二极与第七晶体管T7的栅极连接，第八晶体管T8的栅极连接发光控制信号线EM。第九晶体管T9的第一极与初始化信号线Vref连接，第九晶体管T9的第二极与第七晶体管T7的栅极连接，第十晶体管T10的第一极与初始化信号线Vref连接，第十晶体管T10的第二极与发光模块13的第一端连接，第九晶体管T9和第十晶体管T10的栅极均连接第二扫描线S2，第一晶体管T1和第二晶体管T2依次串联连接于数据线Vdata与第七晶体管T7的第一极之间，第一晶体管T1的栅极连接第一扫描线S1、第二晶体管T2的栅极连接发光控制信号线EM。第一电容C1的第一端与第一电源Vdd连接，第一电容C1的第二端与第七晶体管T7的栅极连接。图12为本申请实施例提供的另一种像素电路的驱动时序图，图12所示的驱动时序适用于图11所示的像素电路。在图11所示的像素电路中，示例性示出第一晶体管T1、第十一晶体管T11和第十二晶体管T12为P型晶体管，第二晶体管T2、第七晶体管T7、第八晶体管T8、第九晶体管T9和第十晶体管T10为N型晶体管。像素电路包括初始化阶段t1、数据电压写入和补偿阶段t5和发光阶段t4。
示例性的，在初始化阶段t1，第九晶体管T9、第十晶体管T10响应第二扫描线S2上的高电平导通，第一晶体管T1响应第一扫描线S1上的高电平关断， 第十一晶体管T11和第十二晶体管T12响应发光控制信号线EM上的高电平关断,第二晶体管T2和第八晶体管T8响应发光控制信号线EM上的高电平导通。初始化电压Vf传输至第七晶体管T7的栅极和发光模块13的第一端，实现对驱动模块和发光模块13的初始化。
在数据电压写入和补偿阶段t5，第九晶体管T9、第十晶体管T10响应第二扫描线S2上的低电平关断，第一晶体管T1响应第一扫描线S1上的低电平导通，第十一晶体管T11和第十二晶体管T12响应发光控制信号线EM上的高电平关断,第二晶体管T2和第八晶体管T8响应发光控制信号线EM上的高电平导通。数据电压经导通的第一晶体管T1、第二晶体管T2、第七晶体管T7和第八晶体管T8传输至第七晶体管T7的栅极，且第八晶体管T8将第七晶体管T7的阈值电压有关的信息写入第七晶体管T7的栅极，完成对第七晶体管T7的阈值电压的补偿。
发光阶段t4，第九晶体管T9、第十晶体管T10响应第二扫描线S2上的低电平关断，第一晶体管T1响应第一扫描线S1上的高电平关断，第十一晶体管T11和第十二晶体管T12响应发光控制信号线EM上的低电平导通，第二晶体管T2和第八晶体管T8响应发光控制信号线EM上的低电平关断。第七晶体管T7根据其栅极和第二极的电压产生驱动电流驱动发光模块13发光。
在示例性的实施例中，第二晶体管T2提前导通，第一晶体管T1和第二晶体管T2在后续阶段均导通后，可以整体等效成低温多晶硅晶体管，从而将数据电压快速写入驱动模块(第七晶体管T7)中。虽然第二晶体管T2是氧化物晶体管，但是在后续数据电压写入和补偿阶段t5，第二晶体管T2已完全导通，不影响数据电压的快速写入，适用于高频驱动。第一晶体管T1和第二晶体管T2串联连接，第一晶体管T1和第二晶体管T2关断后整体等效于氧化物晶体管，可以降低漏电流的大小。第二晶体管T2相较于第一晶体管T1更靠近双第七晶体管T7一侧，第二晶体管T2关断后，抑制漏电的能力较强，有利于维持第七晶体管T7栅极电压的稳定。同时，第二晶体管T2又与第一晶体管T1串联，第 一晶体管T1关断后，可以进一步抑制漏电，从而提高第七晶体管T7栅极电压的稳定性，提高显示的均一性。因此，采用低温多晶硅晶体管和氧化物晶体管相互结合的像素驱动电路，在低刷新频率和高刷新频率下均能保证显示面板显示的稳定性，有利于实现显示面板的宽频驱动，降低功耗。
本申请实施例还提供了一种像素电路的驱动方法，图13为本申请实施例提供的一种像素电路的驱动方法流程图，参考图2，像素电路包括驱动模块10、数据写入模块12和发光模块13；数据写入模块12包括串联的第一晶体管T1和第二晶体管T2，第一晶体管T1为低温多晶硅晶体管，第二晶体管T2为氧化物晶体管；
参考图2和图13，该驱动方法包括：
S110、在数据写入阶段，控制第一晶体管和第二晶体管导通，第二晶体管早于第一晶体管导通，以将数据线提供的数据电压传输至驱动模块。
第二晶体管T2可以在数据电压写入阶段之前导通，以不影响数据电压写入阶段数据电压的写入。低温多晶硅晶体管具有高迁移率和较快的驱动速度，第一晶体管T1为低温多晶硅晶体管，可以快速的将数据电压写入驱动模块中，适用于高频驱动。氧化物晶体管关态漏电流小，第二晶体管T2为氧化物晶体管可以降低漏电流的大小，缓解较低刷新频率情况下显示效果较差的问题，保证显示面板显示的稳定性。因此，本实施例中采用低温多晶硅晶体管和氧化物晶体管相互结合的像素驱动电路，在低刷新频率和高刷新频率下均能保证显示面板显示的稳定性，有利于显示面板的宽频驱动，降低功耗。
S120、发光阶段，控制第一晶体管和所述第二晶体管关断；驱动模块根据数据电压驱动发光模块发光。
驱动模块10根据数据电压产生驱动电流，在发光阶段驱动模块10驱动发光模块13发光。
可选地，继续参考图2，像素电路还包存储模块11、发光控制模块14和初始化模块，初始化模块包括第一初始化模块161、第二初始化模块162和第三初 始化模块163；存储模块11连接驱动模块10，存储模块11包括第一存储模块111和第二存储模块112；驱动模块10包括双栅晶体管T0，发光控制模块14、双栅晶体管T0、发光模块13依次连接于第一电源Vdd和第二电源Vss之间；双栅晶体管T0的第一极D连接所述发光控制模块，双栅晶体管T0的第二极S连接发光模块13；数据写入模块12连接于双栅晶体管T0的第一栅极G与数据线Vdata之间；第一存储模块111连接于双栅晶体管T0的第一栅极G和第二极S之间、第二存储模块112连接于双栅晶体管T0的第二栅极B和第二极S之间；第一初始化模块161连接于双栅晶体管T0的第一栅极G和第二极S之间，第二初始化模块162连接于双栅晶体管T0的第二栅极B与第一极D之间；第三初始化模块163连接于双栅晶体管T0的第二极S和初始化信号线Vref之间。参考图2，该驱动方法还包括：
在初始化阶段，控制第三初始化模块163、发光控制模块14、第二晶体管T2、第一初始化模块161和第二初始化模块162导通，控制第一晶体管T1关断，以将第一电源Vdd提供的第一电源电压传输至双栅晶体管T0的第二栅极B和第一极D、将初始化信号线Vref提供的初始化电压或第二电源电压传输至双栅晶体管T0的第二极S和第一栅极G，对双栅晶体管T0的第一栅极G、第二栅极B、第一极D和第二极S进行初始化；其中，第二电源电压为第二电源Vss提供的电压。
第二晶体管T2提前于第一晶体管T1导通，以不影响后续数据电压写入阶段，数据电压的快速写入。
在补偿阶段，控制发光控制模块14关断，控制第三初始化模块163、第二晶体管T2、第一初始化模块161和第二初始化模块162导通，第二初始化模块162、双栅晶体管T0、第三初始化模块163和初始化信号线Vref之间形成通路，以完成对双栅晶体管T0的阈值电压的补偿。
在补偿阶段，第一电源电压V1高于初始化电压Vf，因此在第二栅极B、第二初始化模块162、双栅晶体管T0、第三初始化模块163和初始化信号线Vref 之间形成通路，第二栅极B的电荷向第二极S流动，第二栅极B和第一极D的电压降低，随着第二栅极B的电压降低，双栅晶体管T0的阈值电压Vth逐渐正漂，当阈值电压Vth等于0V时，双栅晶体管T0的第一栅极G和第二极S的电压差VGS＝Vth＝0，双栅晶体管T0关断，第二存储模块112存储双栅晶体管T0的第二栅极B和第二极的电压差VBS。
在数据电压写入阶段，控制第一晶体管T1、第二晶体管T2和第三初始化模块163导通，控制第一初始化模块161、第二初始化模块162和发光控制模块EM关断，以将数据线Vdata提供的数据电压传输至驱动模块10。
数据线Vdata提供的数据电压Vd经导通的第一晶体管T1和第二晶体管T2传输至双栅晶体管T0的第一栅极G，双栅晶体管T0的第二极S的电压维持初始化电压Vf不变，此时双栅晶体管T0的第二栅极B和第二极的电压差不变，双栅晶体管T0的阈值电压Vth不变。
在发光阶段，控制第一晶体管T1、第二晶体管T2、第一初始化模块161、第二初始化模块162和第三初始化模块163关断，控制发光控制模块EM导通，双栅晶体管T0根据数据电压Vd产生驱动电流驱动发光模块13发光。
发光阶段，双栅晶体管T0的第二栅极B和第二极S的电压差不变，因此双栅晶体管T0的阈值电压Vth＝0不变。第一电源Vdd、发光控制模块14、双栅晶体管T0、发光模块13和第二电源Vss之间形成通路，双栅晶体管T0产生驱动电流驱动发光模块13发光。
可选的，参考图5，像素电路还包括存储模块11、发光控制模块14、补偿模块15和初始化模块，存储模块11连接驱动模块10；存储模块11包括第一存储模块111和第二存储模块112；发光控制模块14、驱动模块10、发光模块13依次连接于第一电源Vdd和第二电源Vss之间；第一存储模块111连接于数据写入模块12和驱动模块10的控制端之间；补偿模块15与第一存储模块111并联，或者补偿模块15连接于驱动模块10的控制端和第一端之间，驱动模块10的第一端连接发光控制模块14；第二存储模块112连接于数据写入模块12和驱 动模块10的第二端之间，或者，第二存储模块112连接于第一存储模块111和驱动模块10的第二端之间；初始化模块包括第一初始化模块161和第二初始化模块162，第一初始化模块161连接于第一初始化信号线Vref1和第一存储模块111的第一端之间，第一存储模块111的第二端与驱动模块10的控制端连接；第二初始化模块162连接于第二初始化信号线Vref2和驱动模块10的第二端之间。该驱动方法还包括：
在初始化阶段，控制一晶体管T1、第二晶体管T2和第二初始化模块162关断，控制补偿模块15、第一初始化模块161和发光控制模块14导通，以将第一电源Vdd提供的第一电源电压传输至驱动模块10的第一端和控制端之间、将第一初始化信号线Vref1上的第一初始化电压传输至第一存储模块111，对驱动模块10的控制端、第一端以及第一存储模块111进行初始化。
第一电源Vdd提供的第一电源电压V1经发光控制模块14和补偿模块15传输至驱动模块10的控制端和第一端，对其进行初始化。第二初始化信号线Vref2提供的第二初始化电压Vf2经导通的第二初始化模块162传输至驱动模块10的第二端，对驱动模块10的第二端进行初始化。
在补偿阶段，控制第一晶体管T1和发光控制模块14关断，控制补偿模块15、第二晶体管T2、第一初始化模块161和第二初始化模块162导通，对驱动模块10进行阈值电压的补偿。
驱动模块10的第一端向驱动模块10的第二端充电，使得驱动模块10的第一端的电压降低，直至驱动模块10的第一端和控制端的电压降低为Vf2+Vth时，驱动模块10关断，其中Vth为驱动模块10的阈值电压。在补偿阶段，第二晶体管T2提前导通，以便后续进行数据电压Vd的写入。
在数据电压写入阶段，控制补偿模块15、第一初始化模块161和发光控制模块14关断，控制第一晶体管T1、第二晶体管T2和第二初始化模块162导通，以将数据线Vdata提供的数据电压传输至驱动模块10。
数据电压Vd经导通的第一晶体管T1和第二初始化模块162导通写入第一 存储模块111的第一端。驱动模块10的第二端的电压维持上一阶段的第二初始化电压Vf2不变。第一晶体管T1和第二晶体管T2在数据电压写入阶段，可以整体等效成低温多晶硅晶体管，从而将数据电压快速写入驱动模块10中。虽然第二晶体管T2是氧化物晶体管，但是在数据电压写入阶段，第二晶体管T2已完全导通，不影响数据电压的快速写入。在高刷新频率下，数据电压写入阶段的时间短时，依然能将数据电压Vd充分写入驱动模块10中，有利于提高高频驱动下的显示效果。
在发光阶段，控制第一晶体管T1、第二晶体管T2、第一初始化模块161、第二初始化模块162和补偿模块15关断，控制发光控制模块14导通；驱动模块10根据数据电压Vd产生驱动电流驱动发光模块13发光。
驱动模块10根据驱动模块10的控制端和第二端的电压产生驱动电流驱动发光模块13发光。第二晶体管T2为氧化物晶体管，在发光阶段关断时漏电流较小，可以在低刷新频率下，发光阶段较长时，保证驱动模块10控制端电压的稳定，有利于提高显示效果。
可选地，本申请实施例还提供了一种显示面板，该显示面板包括本申请任意实施例所提供的像素电路。图14为本申请实施例提供的一种显示面板的结构示意图，参考图14，该显示面板可以是图14所示的手机面板，也可以为任何具有显示功能的电子产品的面板，包括但不限于以下类别：电视机、笔记本电脑、桌上型显示器、平板电脑、数码相机、智能手环、智能眼镜、车载显示器、医疗设备、工控设备、触摸交互终端等，本申请实施例对此不作特殊限定。

Claims (20)

  1. 一种像素电路，包括：驱动模块、数据写入模块和发光模块；
    所述数据写入模块包括串联的第一晶体管和第二晶体管，所述第一晶体管为低温多晶硅晶体管，所述第二晶体管为氧化物晶体管，所述数据写入模块设置为将数据电压传输至所述驱动模块；
    所述驱动模块设置为根据所述数据电压驱动所述发光模块发光。
  2. 根据权利要求1所述的像素电路，其中，在所述像素电路的一显示周期，所述第二晶体管先于所述第一晶体管导通，并且所述第一晶体管在所述第二晶体管导通的期间内导通。
  3. 根据权利要求1所述的像素电路，其中，所述第一晶体管和所述第二晶体管依次串联连接于数据线和所述驱动模块之间。
  4. 根据权利要求1-3任一项所述的像素电路，还包括存储模块、发光控制模块和初始化模块，所述存储模块连接所述驱动模块，所述存储模块设置为存储所述数据电压；所述存储模块包括第一存储模块和第二存储模块；所述驱动模块包括双栅晶体管，所述发光控制模块、所述双栅晶体管、所述发光模块依次连接于第一电源和第二电源之间，所述双栅晶体管的第一极连接所述发光控制模块，所述双栅晶体管的第二极连接所述发光模块；
    所述数据写入模块连接于所述双栅晶体管的第一栅极与数据线之间，所述数据写入模块设置为向所述第一栅极传输所述数据线输出的数据电压；
    所述第一存储模块连接于所述双栅晶体管的第一栅极和第二极之间，所述第一存储模块设置为存储所述第一栅极的电压，所述第二存储模块连接于所述双栅晶体管的第二栅极和第二极之间，所述第二存储模块设置为存储所述第二栅极的电压；
    所述初始化模块设置为对所述双栅晶体管的第一栅极、第二栅极、第一极和第二极进行初始化。
  5. 根据权利要求4所述的像素电路，其中，所述初始化模块包括第一初始化模块、第二初始化模块和第三初始化模块，所述第一初始化模块连接于所述双 栅晶体管的第一栅极和第二极之间，所述第二初始化模块连接于所述双栅晶体管的第二栅极与第一极之间；
    所述第三初始化模块连接于所述双栅晶体管的第二极和初始化信号线之间。
  6. 根据权利要求5所述的像素电路，其中，所述初始化信号线上的信号由所述第二电源提供。
  7. 根据权利要求5或6所述的像素电路，其中，所述第一栅极为顶栅，所述第二栅极为底栅；所述第一初始化模块包括第三晶体管，所述第二初始化模块包括第四晶体管，所述第三初始化模块包括第五晶体管，所述发光控制模块包括第六晶体管；所述第一存储模块包括第一电容，所述第二存储模块包括第二电容；
    所述第一晶体管的第一极连接所述数据线，所述第一晶体管的第二极连接所述第二晶体管的第一极，所述第一晶体管的栅极连接第一扫描线，所述第二晶体管的第二极连接所述双栅晶体管的第一栅极，所述第二晶体管的栅极连接第二扫描线；
    所述第三晶体管的第一极连接所述双栅晶体管的第二极，所述第三晶体管的第二极连接所述双栅晶体管的第一栅极，所述第三晶体管的栅极连接第三扫描线，所述第四晶体管的第一极连接所述双栅晶体管的第一极，所述第四晶体管的第二极连接所述双栅晶体管的第二栅极，所述第四晶体管的栅极连接所述第三扫描线；
    所述第五晶体管的第一极连接所述初始化信号线，所述第五晶体管的第二极连接所述双栅晶体管的第二极，所述第五晶体管的栅极连接所述第二扫描线；
    所述第六晶体管的第一极连接所述第一电源，所述第六晶体管的第二极连接所述双栅晶体管的第一极，所述第六晶体管的栅极连接发光控制信号线；
    所述第一电容连接于所述双栅晶体管的第一栅极和第二极之间，所述第二电容连接于所述双栅晶体管的第二栅极和第二极之间。
  8. 根据权利要求7所述的像素电路，其中，所述第六晶体管为所述低温多晶 硅晶体管，所述双栅晶体管、第三晶体管、所述第四晶体管和所述第五晶体管均为所述氧化物晶体管。
  9. 根据权利要求1-3任一项所述的像素电路，还包括存储模块、发光控制模块、补偿模块和初始化模块，所述存储模块连接所述驱动模块，所述存储模块设置为存储所述数据电压；所述存储模块包括第一存储模块和第二存储模块；所述发光控制模块、所述驱动模块、所述发光模块依次连接于第一电源和第二电源之间；
    所述第一存储模块连接于所述数据写入模块和所述驱动模块的控制端之间，所述第一存储模块设置为将所述数据电压耦合至所述驱动模块；
    所述补偿模块与所述第一存储模块并联，所述驱动模块的第一端连接所述发光控制模块，或者所述补偿模块连接于所述驱动模块的控制端和第一端之间，所述驱动模块的第一端连接所述发光控制模块；
    所述第二存储模块连接于所述数据写入模块和所述驱动模块的第二端之间，或者，所述第二存储模块连接于所述第一存储模块和所述驱动模块的第二端之间，所述第二存储模块设置为将所述驱动模块的第二端的电压耦合至所述第一存储模块；
    所述初始化模块设置为对所述第一存储模块和所述第二存储模块进行初始化。
  10. 根据权利要求9所述的像素电路，其中，所述初始化模块包括第一初始化模块和第二初始化模块，所述第一初始化模块连接于所述第一初始化信号线和所述第一存储模块的第一端之间，所述第一存储模块的第二端与所述驱动模块的控制端连接；
    所述第二初始化模块连接于第二初始化信号线和所述驱动模块的第二端之间。
  11. 根据权利要求10所述的像素电路，其中，所述驱动模块包括第七晶体管、所述补偿模块包括第八晶体管，所述第一初始化模块包括第九晶体管，所述第 二初始化模块包括第十晶体管，所述发光控制模块包括第十一晶体管；所述第一存储模块包括第一电容，所述第二存储模块包括第二电容；
    所述第一晶体管的第一极连接所述数据线，所述第一晶体管的第二极连接所述第二晶体管的第一极，所述第二晶体管的第二极与所述第一电容的第一端连接，所述第一晶体管的栅极连接第一扫描线，所述第二晶体管的栅极连接发光控制信号线；
    所述第九晶体管的第一极与所述第一初始化信号线连接，所述第九晶体管的第二极与所述第一电容的第一端连接，所述第九晶体管的栅极连接第二扫描线，所述第一电容的第二端与所述第七晶体管的栅极电连接；
    所述第八晶体管的第一极与所述第七晶体管的第一极连接，所述第八晶体管的第二极与所述第七晶体管的栅极连接，所述第八晶体管的栅极与所述第二扫描线连接；或者所述第八晶体管的第一极与所述第九晶体管的第二极连接，所述第八晶体管的第二极与所述第一电容的第二端连接，所述第八晶体管的栅极与所述第二扫描线连接；
    所述第二电容的第一端与所述第一电容的第一端连接，所述第二电容的第二端与所述第七晶体管的第二极连接，或者所述第二电容的第一端与所述第七晶体管的栅极连接，所述第二电容的第二端与所述第七晶体管的第二极连接；
    所述第十晶体管的第一极与所述第二初始化信号线连接，所述第十晶体管的第二极与所述第七晶体管的第二极连接，所述第十晶体管的栅极与发光控制信号线连接；
    所述第十一晶体管的第一极与所述第一电源连接，所述第十一晶体管的第二极与所述第七晶体管的第一极连接，所述第十一晶体管的栅极与所述发光控制信号线连接。
  12. 根据权利要求11所述的像素电路，其中，所述第十一晶体管为所述低温多晶硅晶体管，所述第七晶体管、所述第八晶体管、所述第九晶体管和所述第十晶体管均为氧化物晶体管。
  13. 根据权利要求1-3任一项所述的像素电路，还包括存储模块和至少一个发光控制模块，所述存储模块连接所述驱动模块，所述存储模块设置为存储数据电压，所述至少一个发光控制模块设置为控制所述驱动模块与所述第一电源或者所述第二电源中的至少一个是否连通。
  14. 根据权利要求13所述的像素电路，其中，所述至少一个发光控制模块和所述驱动模块连接于所述第一电源和所述第二电源之间。
  15. 根据权利要求1-3任一项所述的像素电路，还包括存储模块、发光控制模块、补偿模块和初始化模块，所述发光控制模块包括第十一晶体管和第十二晶体管、所述驱动模块包括第七晶体管、所述补偿模块包括第八晶体管、所述初始化模块包括第九晶体管、所述存储模块包括第一电容；
    所述第十一晶体管的第一极与第一电源连接，所述第十一晶体管的第二极与所述第七晶体管的第一极连接，所述第七晶体管的第二极与所述第十二晶体管的第一极连接，所述第十二晶体管的第二极与所述发光模块的第一端连接，所述发光模块的第二端与第二电源连接；所述第十一晶体管和所述第十二晶体管的栅极均连接发光控制信号线；
    所述第八晶体管的第一极与所述第七晶体管的第二极连接，所述第八晶体管的第二极与所述第七晶体管的栅极连接，所述第八晶体管的栅极连接所述发光控制信号线；
    所述第九晶体管的第一极与初始化信号线连接，所述第九晶体管的第二极与所述第七晶体管的栅极连接，所述第九晶体管的栅极连接第二扫描线；
    所述第一晶体管和所述第二晶体管串联连接于数据线与所述第七晶体管的第一极之间，所述第一晶体管的栅极连接第一扫描线、所述第二晶体管的栅极连接所述发光控制信号线；
    所述第一电容的第一端与所述第一电源连接，所述第一电容的第二端与所述第七晶体管的栅极连接。
  16. 根据权利要求15所述的像素电路，其中，所述初始化模块还包括第十晶 体管，所述第十晶体管的第一极与所述初始化信号线连接，所述第十晶体管的第二极与所述发光模块的第一端连接，所述第十晶体管的栅极连接所述第二扫描线。
  17. 一种像素电路的驱动方法，所述像素电路包括驱动模块、数据写入模块和发光模块；所述数据写入模块包括串联的第一晶体管和第二晶体管，所述第一晶体管为低温多晶硅晶体管，所述第二晶体管为氧化物晶体管；
    所述驱动方法包括：
    在数据写入阶段，控制所述第一晶体管和所述第二晶体管导通，所述第二晶体管早于所述第一晶体管导通，以将所述数据线提供的数据电压传输至所述驱动模块；
    在发光阶段，控制所述第一晶体管和所述第二晶体管关断；所述驱动模块根据所述数据电压驱动所述发光模块发光。
  18. 根据权利要求17所述的方法，其中，所述像素电路还包括存储模块、发光控制模块和初始化模块；所述存储模块连接所述驱动模块；所述初始化模块包括第一初始化模块、第二初始化模块和第三初始化模块；所述存储模块包括第一存储模块和第二存储模块；所述驱动模块包括双栅晶体管，所述发光控制模块、所述双栅晶体管、所述发光模块依次连接于第一电源和第二电源之间，所述双栅晶体管的第一极连接所述发光控制模块，所述双栅晶体管的第二极连接所述发光模块；所述数据写入模块连接于所述双栅晶体管的第一栅极与数据线之间；所述第一存储模块连接于所述双栅晶体管的第一栅极和第二极之间、所述第二存储模块连接于所述双栅晶体管的第二栅极和第二极之间；所述第一初始化模块连接于所述双栅晶体管的第一栅极和第二极之间，所述第二初始化模块连接于所述双栅晶体管的第一栅极与第一极之间；所述第三初始化模块连接于所述双栅晶体管的第二极和初始化信号线之间；
    所述驱动方法包括：
    在初始化阶段，控制所述第三初始化模块、所述发光控制模块、所述第二 晶体管、所述第一初始化模块和所述第二初始化模块导通，控制所述第一晶体管关断，以将所述第一电源提供的第一电源电压传输至所述双栅晶体管的第二栅极和第一极、将所述初始化信号线提供的初始化电压或第二电源电压传输至所述双栅晶体管的第二极和第一栅极，对所述双栅晶体管的第一栅极、第二栅极、第一极和第二极进行初始化；其中，第二电源电压为所述第二电源提供的电压；
    在补偿阶段，控制所述发光控制模块关断，控制所述第三初始化模块、所述第二晶体管、所述第一初始化模块和所述第二初始化模块导通，所述第二初始化模块、所述双栅晶体管、所述第三初始化模块和所述初始化信号线之间形成通路，以完成对所述双栅晶体管的阈值电压的补偿；
    在所述数据写入阶段，控制所述第一晶体管、所述第二晶体管和所述第三初始化模块导通，控制所述第一初始化模块、所述第二初始化模块和所述发光控制模块关断，以将所述数据线提供的数据电压传输至所述驱动模块；
    在发光阶段，控制所述第一晶体管、所述第二晶体管、所述第一初始化模块、所述第二初始化模块和所述第三初始化模块关断，控制所述发光控制模块导通，所述双栅晶体管根据所述数据电压产生驱动电流驱动所述发光模块发光。
  19. 根据权利要求17所述的方法，其中，所述像素电路还包括存储模块、发光控制模块、补偿模块和初始化模块，所述存储模块连接所述驱动模块；所述存储模块包括第一存储模块和第二存储模块；所述发光控制模块、所述驱动模块、所述发光模块依次连接于第一电源和第二电源之间；所述数据写入模块连接于第一存储模块与数据线之间；所述第一存储模块连接于所述数据写入模块和所述驱动模块的控制端之间；所述补偿模块与所述第一存储模块并联，所述驱动模块的第一端连接所述发光控制模块，或者所述补偿模块连接于所述驱动模块的控制端和第一端之间，所述驱动模块的第一端连接所述发光控制模块；所述第二存储模块连接于所述数据写入模块和所述驱动模块的第二端之间，或者，所述第二存储模块连于所述第一存储模块和所述驱动模块的第二端之间； 所述初始化模块包括第一初始化模块和第二初始化模块，所述第一初始化模块连接于所述第一初始化信号线和所述第一存储模块的第一端之间，所述第一存储模块的第二端与所述驱动模块的控制端连接；所述第二初始化模块连接于第二初始化信号线和所述驱动模块的第二端之间；
    所述驱动方法包括：
    在初始化阶段，控制所述一晶体管、所述第二晶体管和所述第二初始化模块关断，控制所述补偿模块、所述第一初始化模块和所述发光控制模块导通，以将所述第一电源提供的第一电源电压传输至所述驱动模块的第一端和控制端之间、将所述第一初始化信号线上的第一初始化电压传输至所述第一存储模块，对所述驱动模块的控制端、第一端以及所述第一存储模块进行初始化；
    在补偿阶段，控制所述第一晶体管和所述发光控制模块关断，控制所述补偿模块、所述第二晶体管、所述第一初始化模块和所述第二初始化模块导通，对所述驱动模块进行阈值电压的补偿；
    在数据电压写入阶段，控制所述补偿模块、所述第一初始化模块和所述发光控制模块关断，控制所述第一晶体管、所述第二晶体管和所述第二初始化模块导通，以将所述数据线提供的数据电压传输至所述驱动模块；
    在发光阶段，控制所述第一晶体管、所述第二晶体管、所述第一初始化模块、所述第二初始化模块和所述补偿模块关断，控制所述发光控制模块导通；所述驱动模块根据所述数据电压产生驱动电流驱动所述发光模块发光。
  20. 一种显示面板，包括权利要求1-16任一项所述的像素电路。
PCT/CN2023/073675 2022-08-30 2023-01-29 像素电路及其驱动方法和显示面板 WO2024045484A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211049980.5 2022-08-30
CN202211049980.5A CN115294940A (zh) 2022-08-30 2022-08-30 像素电路及其驱动方法和显示面板

Publications (1)

Publication Number Publication Date
WO2024045484A1 true WO2024045484A1 (zh) 2024-03-07

Family

ID=83831737

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/073675 WO2024045484A1 (zh) 2022-08-30 2023-01-29 像素电路及其驱动方法和显示面板

Country Status (2)

Country Link
CN (1) CN115294940A (zh)
WO (1) WO2024045484A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115294940A (zh) * 2022-08-30 2022-11-04 云谷（固安）科技有限公司 像素电路及其驱动方法和显示面板

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103218970A (zh) * 2013-03-25 2013-07-24 京东方科技集团股份有限公司 Amoled像素单元及其驱动方法、显示装置
CN104732927A (zh) * 2015-04-09 2015-06-24 京东方科技集团股份有限公司 一种像素电路及其驱动方法和显示装置
US20180357964A1 (en) * 2017-06-12 2018-12-13 Lg Display Co., Ltd. Electroluminescent display
CN109087609A (zh) * 2018-11-13 2018-12-25 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板、显示装置
CN111354322A (zh) * 2020-04-08 2020-06-30 深圳市华星光电半导体显示技术有限公司 一种同步发光的像素补偿电路及显示面板
CN111429836A (zh) * 2020-04-09 2020-07-17 深圳市华星光电半导体显示技术有限公司 一种像素驱动电路和显示面板
US11011113B1 (en) * 2020-03-26 2021-05-18 Sharp Kabushiki Kaisha TFT pixel threshold voltage compensation circuit with global compensation
CN113140179A (zh) * 2021-04-12 2021-07-20 武汉华星光电半导体显示技术有限公司 像素驱动电路及其驱动方法、显示面板
CN115294940A (zh) * 2022-08-30 2022-11-04 云谷（固安）科技有限公司 像素电路及其驱动方法和显示面板

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103218970A (zh) * 2013-03-25 2013-07-24 京东方科技集团股份有限公司 Amoled像素单元及其驱动方法、显示装置
CN104732927A (zh) * 2015-04-09 2015-06-24 京东方科技集团股份有限公司 一种像素电路及其驱动方法和显示装置
US20180357964A1 (en) * 2017-06-12 2018-12-13 Lg Display Co., Ltd. Electroluminescent display
CN109087609A (zh) * 2018-11-13 2018-12-25 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板、显示装置
US11011113B1 (en) * 2020-03-26 2021-05-18 Sharp Kabushiki Kaisha TFT pixel threshold voltage compensation circuit with global compensation
CN111354322A (zh) * 2020-04-08 2020-06-30 深圳市华星光电半导体显示技术有限公司 一种同步发光的像素补偿电路及显示面板
CN111429836A (zh) * 2020-04-09 2020-07-17 深圳市华星光电半导体显示技术有限公司 一种像素驱动电路和显示面板
CN113140179A (zh) * 2021-04-12 2021-07-20 武汉华星光电半导体显示技术有限公司 像素驱动电路及其驱动方法、显示面板
CN115294940A (zh) * 2022-08-30 2022-11-04 云谷（固安）科技有限公司 像素电路及其驱动方法和显示面板

Also Published As

Publication number Publication date
CN115294940A (zh) 2022-11-04

Similar Documents

Publication Publication Date Title
WO2021068637A1 (zh) 像素电路及其驱动方法、显示面板
WO2023035613A1 (zh) 像素电路及其驱动方法、显示面板
WO2019205898A1 (zh) 像素电路及其驱动方法、显示面板
CN107452338B (zh) 一种像素电路、其驱动方法、显示面板及显示装置
WO2015188532A1 (zh) 像素驱动电路、驱动方法、阵列基板及显示装置
US20220415273A1 (en) Simultaneous emission pixel compensation circuit and display panel
WO2015085699A1 (zh) Oled像素电路及驱动方法、显示装置
WO2023006100A1 (zh) 像素电路及其驱动方法、显示装置
WO2015188533A1 (zh) 像素驱动电路、驱动方法、阵列基板及显示装置
WO2021203497A1 (zh) 像素驱动电路和显示面板
WO2022062614A1 (zh) 像素驱动电路、显示面板和显示装置
US11922881B2 (en) Pixel circuit and driving method thereof, array substrate and display apparatus
US11568815B2 (en) Pixel driving circuit, manufacturing method thereof, and display device
WO2021142871A1 (zh) 像素补偿电路及显示面板
WO2022016706A1 (zh) 像素电路、其驱动方法及显示装置
CN106940983A (zh) 像素电路及其驱动方法、显示装置
WO2023103038A1 (zh) 像素电路及显示面板
WO2024021465A1 (zh) 像素驱动电路和显示面板
US11942036B2 (en) Pixel circuit, pixel circuit driving method and display device
CN114627817A (zh) 像素电路、像素驱动方法及显示装置
CN108986742A (zh) 像素结构、像素电路和显示面板
WO2024045484A1 (zh) 像素电路及其驱动方法和显示面板
CN108987453B (zh) 像素结构、驱动方法、像素电路和显示面板
TWI410928B (zh) 畫素結構、顯示面板及其驅動方法
WO2023011327A1 (zh) 像素驱动电路及其驱动方法、显示基板和显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23858527

Country of ref document: EP

Kind code of ref document: A1