WO2022062614A1 - 像素驱动电路、显示面板和显示装置 - Google Patents

像素驱动电路、显示面板和显示装置 Download PDF

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Publication number
WO2022062614A1
WO2022062614A1 PCT/CN2021/107572 CN2021107572W WO2022062614A1 WO 2022062614 A1 WO2022062614 A1 WO 2022062614A1 CN 2021107572 W CN2021107572 W CN 2021107572W WO 2022062614 A1 WO2022062614 A1 WO 2022062614A1
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Prior art keywords
transistor
module
signal input
initialization
input terminal
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PCT/CN2021/107572
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English (en)
French (fr)
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解红军
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云谷（固安）科技有限公司
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Publication of WO2022062614A1 publication Critical patent/WO2022062614A1/zh
Priority to US17/990,166 priority Critical patent/US12062326B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Definitions

  • the embodiments of the present application relate to the field of display technology, and in particular, to a pixel driving circuit, a display panel, and a display device
  • the pixel driving circuit drives the light emitting diodes to emit light for display.
  • the refresh frequency of the display panel is relatively high or the pixel density (Pixels Per Inch, PPI) is relatively high, the charging rates of the pixel driving circuits at the far end and the near end of the display panel are different, resulting in different luminous brightness at different positions of the display panel, and the display The display uniformity of the panel is relatively poor.
  • the present application provides a pixel driving circuit, a display panel and a display device, so as to reduce the charging time of the pixel driving circuit and improve the display uniformity of the display panel.
  • An embodiment of the present application provides a pixel driving circuit, including: a driving transistor; a first initialization module, the first initialization module is connected to the driving transistor, and the first initialization module is set to be a gate of the driving transistor a light-emitting device; a scan signal input terminal; a second initialization module, the control terminal and the first terminal of the second initialization module are connected to the scan signal input terminal, and the second terminal of the second initialization module is connected to the scan signal input terminal.
  • the light-emitting device is connected, and the second initialization module is set to initialize the light-emitting device; a data writing module is connected to the driving transistor, and the data writing module is set to writing data voltage to the gate of the drive transistor; a storage module, the storage module is connected to the drive transistor, and the storage module is configured to store the gate voltage of the drive transistor; the drive transistor is connected to the light-emitting device connected, and the driving transistor is configured to output a driving current according to the data voltage, so as to drive the light-emitting device to emit light.
  • Embodiments of the present application further provide a display panel, including the pixel driving circuit provided by any embodiment of the present application.
  • the embodiment of the present application further provides a display device, including the display panel provided by any embodiment of the present application.
  • the first terminal of the first initialization module is connected to the input terminal of the initialization signal
  • the control terminal and the first terminal of the second initialization module are connected to the input terminal of the scan signal
  • the gate of the driving transistor is connected to the input terminal of the scanning signal.
  • the data voltage is too low, the writing of the data is insufficient, and at the same time, different driving currents caused by different charging rates of different pixel driving circuits can be avoided, and the display uniformity of the display panel provided with the pixel driving circuits can be improved.
  • the scanning signal it is possible to avoid setting up another initialization signal input terminal, thereby avoiding setting an additional initialization signal line, reducing the wiring difficulty of the display panel, and helping the display panel to achieve a high refresh rate or high PPI.
  • FIG. 1 is a schematic structural diagram of a display panel.
  • FIG. 2 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another pixel driving circuit according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of another pixel driving circuit according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another pixel driving circuit according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another pixel driving circuit according to an embodiment of the present application.
  • FIG. 7 is a timing diagram corresponding to the pixel driving circuit provided in FIG. 6 .
  • FIG. 8 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a display device according to an embodiment of the present application.
  • the display panel includes a signal line 101 and a driving chip 102
  • the driving chip 102 is disposed at the first end 103 of the display panel
  • the signal line 101 extends from the first end 103 of the display panel to opposite to the first end 103
  • the driving chip 102 provides data signals for the pixel driving circuit in the display panel through the signal line 101 .
  • the signal lines 101 may be data lines and power signal lines.
  • the refresh frequency of the display panel is relatively high or the PPI is relatively high
  • the duration of one frame of the pixel driving circuit in the display panel is relatively short, so that the duration of the data writing phase of the pixel driving circuit is relatively short.
  • the signal line 101 is connected to a plurality of pixel driving circuits along its extending direction, and serves as the load of the signal line 101, so that the impedance of the signal line 101 along its own extending direction becomes larger and larger, which causes the signal line 101 to charge the pixel driving circuit in different positions when charging. rate is different.
  • the charging rates of the signal lines 101 for charging the pixel driving circuits at different positions are different, so that the signal lines 101 provide different signal voltages for the pixel driving circuits at different positions, resulting in different positions.
  • the driving currents formed by the pixel driving circuits are different, so that the display uniformity of the display panel is relatively poor.
  • the signal line 101 is a data line, along the direction in which the signal line 101 extends, the charging rates of the plurality of pixel driving circuits are getting smaller and smaller, so that the data voltages written by the plurality of pixel driving circuits are getting smaller and smaller. , resulting in brighter and brighter light-emitting brightness of the display panel, and poor display uniformity of the display panel.
  • the pixel driving circuit includes a driving transistor Tdr, a storage module 10, a data writing module 20, a first initialization module 30, a second initialization module 40 and a light-emitting device D1; the first initialization module 30 and the driving transistor Tdr connected, the first initialization module 30 is set to initialize the gate of the driving transistor Tdr; the control terminal and the first terminal of the second initialization module 40 are connected to the scan signal input terminal of the pixel driving circuit, and are set to initialize the light-emitting device D1
  • the data writing module 20 is set to write the data voltage to the gate of the drive transistor Tdr; the storage module 10 is set to store the gate voltage of the drive transistor Tdr; the drive transistor Tdr is set to output the drive current according to the data voltage to drive the light-emitting device D1 glow.
  • the first terminal of the first initialization module 30 may be connected to the initialization signal input terminal VREF of the pixel driving circuit, and the second terminal of the first initialization module 30 may be connected to the gate of the driving transistor Tdr.
  • the initialization signal provided by the initialization signal input terminal VREF is transmitted to the gate of the driving transistor Tdr, so that the gate of the driving transistor Tdr can be initialized.
  • the control terminal and the first terminal of the second initialization module 40 are connected to the scan signal input terminal of the pixel driving circuit, and the second terminal of the second initialization module 40 is connected to the anode of the light-emitting device D1.
  • the scan signal provided by the scan signal input terminal can be transmitted to the anode of the light-emitting device D1 through the second initialization module 40 to realize the initialization of the anode of the light-emitting device D1.
  • a data voltage is written to the gate of the driving transistor Tdr through the data writing module 20, and the storage module 10 stores the gate voltage of the driving transistor Tdr, and drives the The transistor Tdr forms a driving current according to the gate voltage, and drives the light-emitting device D1 to emit light.
  • the gate of the driving transistor Tdr is initialized by the initialization signal provided by the initialization signal input terminal VREF, and the gate potential of the driving transistor Tdr is initialized Signal.
  • the time required to write the data voltage to the gate of the driving transistor Tdr is related to the initialization signal and the charging rate. The higher the potential of the initialization signal, the higher the charging rate and the shorter the time required. When the working time of one frame of the pixel driving circuit is relatively short, the data writing time of the pixel driving circuit is relatively short.
  • the potential of the initialization signal can be relatively high, and the data voltage can be written into the driving transistor Tdr in a short time.
  • the gate can avoid insufficient data voltage writing caused by the low gate potential of the drive transistor Tdr at the end of initialization, and can avoid different drive currents caused by different charging rates of different pixel drive circuits. Display uniformity of the display panel of the circuit.
  • the second initialization module 40 initializes the anode of the light-emitting device D1 through the scan signal provided by the scan signal input terminal, so as to avoid additionally setting another initialization signal input terminal, so as to avoid setting an additional initialization signal line and reduce the display panel's
  • the difficulty of wiring is conducive to the realization of high refresh rate or high PPI of the display panel.
  • the scan signal input terminal includes a first scan signal input terminal SCAN1 and a second scan signal input terminal SCAN2; the first scan signal input terminal SCAN1 is connected to the control terminal of the first initialization module 30, and the second scan signal input terminal is connected to the control terminal of the first initialization module 30.
  • SCAN2 is connected to the control end of the data writing module 20; the control end and the first end of the second initialization module 40 are connected to the first scan signal input end SCAN1 or the second scan signal input end SCAN2.
  • FIG. 2 exemplarily shows that the control terminal and the first terminal of the second initialization module 40 are connected to the first scan signal input terminal SCAN1.
  • the first scan signal provided by the first scan signal input terminal SCAN1 controls the first initialization module 30 and the second initialization module 40 to conduct, and the initialization signal provided by the initialization signal input terminal VREF passes through the first initialization module.
  • 30 is transmitted to the gate of the drive transistor Tdr to initialize the gate of the drive transistor Tdr.
  • the second initialization module 40 transmits the first scan signal to the anode of the light-emitting device D1 to initialize the anode of the light-emitting device D1.
  • the potential of the gate of the driving transistor Tdr after initialization is the potential of the initialization signal
  • the potential of the anode of the light-emitting device D1 after initialization is the potential of the first scan signal
  • the potential of the initialization signal can be relatively high, and the pixel driving circuit can realize the data writing in the pixel driving circuit.
  • the data voltage is written into the gate of the driving transistor Tdr in a short time to improve the display uniformity of the display panel.
  • the potential of the first scan signal may be a low level, which meets the anode initialization requirement of the light emitting device D1.
  • the control terminal and the first terminal of the second initialization module 40 may also be connected to the second scan signal input terminal SCAN2.
  • the first scan signal provided by the first scan signal input terminal SCAN1 controls the first initialization module 30 to turn on, and the initialization signal provided by the initialization signal input terminal VREF is transmitted to the driving transistor Tdr through the first initialization module 30
  • the gate of the drive transistor Tdr is initialized.
  • the second scan signal provided by the second scan signal input end SCAN2 controls the second initialization module 40 to be turned on, and the second scan signal provided by the second scan signal input end SCAN2 is transmitted to the light-emitting device through the second initialization module 40
  • the anode of the device D1 initializes the anode of the light-emitting device D1.
  • the second initialization module 40 includes a first transistor T1 ; the gate of the first transistor T1 serves as the control terminal of the second initialization module 40 , and the first pole of the first transistor T1 serves as the first electrode of the second initialization module 40 .
  • the second pole of the first transistor T1 serves as the second end of the second initialization module 40 , and the second pole of the first transistor T1 is connected to the anode of the light emitting device D1 .
  • FIG. 4 exemplarily shows that the first transistor T1 is a P-type transistor, and the gate and the first electrode of the first transistor T1 are connected to the first scan signal input terminal SCAN1 .
  • the first scan signal is at a low level
  • the first transistor T1 is controlled to be turned on
  • the first scan signal is transmitted to the anode of the light-emitting device D1 through the first transistor T1
  • the anode of the light-emitting device D1 is initialized .
  • the first scan signal is at a low level, its potential is less than zero, which can meet the anode initialization requirement of the light-emitting device D1.
  • the gate and first electrode of the first transistor T1 may also be connected to the second scan signal input terminal SCAN2.
  • the first scan signal provided by the first scan signal input terminal SCAN1 controls the first initialization module 30 to be turned on, and initializes the gate of the driving transistor Tdr.
  • the second scan signal provided by the second scan signal input terminal SCAN2 is at a low level, which controls the first transistor T1 to be turned on, and the second scan signal is transmitted to the anode of the light-emitting device D1 through the first transistor T1.
  • the anode of the light emitting device D1 is initialized.
  • the second scan signal is at a low level, its potential is less than zero, which can meet the anode initialization requirement of the light-emitting device D1.
  • the pixel driving circuit further includes an initialization signal input terminal VREF and a data signal input terminal VDATA;
  • the first initialization module 30 includes a second transistor T2, and the data writing module 20 includes a third transistor T3;
  • the gate is connected to the first scan signal input terminal SCAN1, the first pole of the second transistor T2 is connected to the initialization signal input terminal VREF, and the second pole of the second transistor T2 is connected to the gate of the driving transistor Tdr;
  • the gate is connected to the second scan signal input terminal SCAN2, the first pole of the third transistor T3 is connected to the data signal input terminal VDATA, and the second pole of the third transistor T3 is connected to the first pole of the driving transistor Tdr.
  • FIG. 5 exemplarily shows that the second transistor T2 and the third transistor T3 are P-type transistors.
  • the first scanning signal is at a low level
  • the second transistor T2 is turned on
  • the initialization signal provided by the initialization signal input terminal VREF is transmitted to the gate of the driving transistor Tdr through the second transistor T2, and the driving transistor The gate of Tdr is initialized.
  • the second scanning signal is at a low level
  • the third transistor T3 is turned on, and the data signal provided by the data signal input terminal VDATA is transmitted to the gate of the driving transistor Tdr through the third transistor T3 to realize data write.
  • the driving transistor Tdr forms a driving current according to the gate voltage, and drives the light-emitting device D1 to emit light.
  • the pixel driving circuit further includes a threshold compensation module 50, a lighting control module 60, a lighting control signal input terminal EM, a first power supply signal input terminal VDD and a second power supply signal input terminal VSS;
  • the storage module 10 includes a storage capacitor Cst; the control end of the threshold compensation module 50 is connected to the second scan signal input end SCAN2, the first end of the threshold compensation module 50 is connected to the gate of the driving transistor Tdr and the first pole of the storage capacitor Cst, and the first end of the threshold compensation module 50 is connected to the gate of the drive transistor Tdr and the first pole of the storage capacitor Cst.
  • the two terminals are connected to the second pole of the driving transistor Tdr; the control terminal of the lighting control module 60 is connected to the lighting control signal input terminal EM, the first terminal of the lighting control module 60 and the second pole of the storage capacitor Cst are input to the first power supply signal
  • the terminal VDD is connected, the second terminal of the lighting control module 60 is connected to the first pole of the driving transistor Tdr, the third terminal of the lighting control module 60 is connected to the second pole of the driving transistor Tdr, and the fourth terminal of the lighting control module 60 is connected to the lighting
  • the anode of the device D1 is connected, and the cathode of the light-emitting device D1 is connected to the second power signal input terminal VSS.
  • the control terminal of the threshold compensation module 50 is connected to the second scan signal input terminal SCAN2, and the threshold compensation module 50 is configured to compensate the threshold voltage of the driving transistor Tdr in the data writing stage of the pixel driving circuit.
  • the control terminal of the light-emitting control module 60 is connected to the light-emitting control signal input terminal EM, and the light-emitting control module 60 is configured to control the storage capacitor Cst to couple the data voltage to the driving transistor Tdr during the light-emitting stage of the pixel driving circuit, so that the driving transistor Tdr forms a voltage according to the data signal.
  • the driving current drives the light-emitting device D1 to emit light.
  • the threshold compensation module 50 includes a fourth transistor T4; the gate of the fourth transistor T4 serves as the control terminal of the threshold compensation module 50, the first pole of the fourth transistor T4 serves as the first end of the threshold compensation module 50, and the first The second pole of the four transistors T4 serves as the second terminal of the threshold compensation module 50 .
  • FIG. 6 exemplarily shows that the fourth transistor T4 is a P-type transistor.
  • the gate of the fourth transistor T4 is connected to the second scan signal input terminal SCAN2, the first pole of the fourth transistor T4 is connected to the gate of the driving transistor Tdr, and the second pole of the fourth transistor T4 is connected to the second pole of the driving transistor Tdr connect.
  • the second scan signal provided by the second scan signal input terminal SCAN2 is at a low level, the third transistor T3 and the fourth transistor T4 are turned on, and the data signal passes through the third transistor T3 and the driving transistor.
  • Tdr and the fourth transistor T4 are written to the gate of the driving transistor Tdr until the gate potential of the driving transistor Tdr is the sum of the data voltage and the threshold voltage of the driving transistor Tdr, the driving transistor Tdr is turned off, and the data signal writing and driving are realized Threshold voltage compensation for transistor Tdr.
  • the lighting control module 60 includes a fifth transistor T5 and a sixth transistor T6.
  • the first pole of the fifth transistor T5 is used as the first terminal of the lighting control module 60
  • the second pole of the fifth transistor T5 is used as the second terminal of the lighting control module 60
  • the first pole of the sixth transistor T6 is used as the lighting control module 60 .
  • the third end, the second pole of the sixth transistor T6 serves as the fourth end of the light emitting control module 60
  • the gate of the fifth transistor T5 and the gate of the sixth transistor T6 serve as the control ends of the light emitting control module 60 .
  • FIG. 6 exemplarily shows that the fifth transistor T5 and the sixth transistor T6 are P-type transistors.
  • the light-emitting control signal provided by the light-emitting control signal input terminal EM is at a low level, which controls the fifth transistor T5 and the sixth transistor T6 to be turned on, and the first power supply signal provided by the first power supply signal input terminal VDD. is transmitted to the first pole of the driving transistor Tdr, and the gate potential of the driving transistor Tdr is the sum of the data signal and the threshold voltage of the driving transistor Tdr, then the driving transistor Tdr is based on the first power supply signal, the data signal and the threshold voltage of the driving transistor Tdr.
  • the driving current is formed and transmitted to the light emitting device D1 through the sixth transistor T6 to drive the light emitting device D1 to emit light.
  • s1 is the timing diagram of the first scan signal provided by the first scan signal input terminal SCAN1
  • s2 is the timing diagram of the second scan signal provided by the second scan signal input terminal SCAN2
  • em is the light emission control signal input terminal EM Provides a timing diagram of the lighting control signals.
  • the first scan signal s1 is at a low level
  • the second scan signal s2 is at a high level
  • the light-emitting control signal em is at a high level
  • the first transistor T1 and the second transistor T2 are turned on
  • the first scan signal The first transistor T1 is transmitted to the anode of the light-emitting device D1, and the anode of the light-emitting device D1 is initialized.
  • the initialization signal provided by the initialization signal input terminal VREF is transmitted to the gate of the driving transistor Tdr through the second transistor T2. gate is initialized. After the initialization phase t1 ends, the driving transistor Tdr is turned on.
  • the first scan signal s1 is at a high level
  • the second scan signal s2 is at a low level
  • the light-emitting control signal em is at a high level
  • the third transistor T3 and the fourth transistor T4 are turned on
  • the data signal The data signal provided by the input terminal VDATA is written to the gate of the driving transistor Tdr through the third transistor T3, the driving transistor Tdr and the fourth transistor T4 until the gate potential of the driving transistor Tdr is the data voltage vdata' and the threshold value of the driving transistor Tdr
  • the sum of the voltages vth is vdata'+vth
  • the drive transistor Tdr is turned off
  • the writing of the data signal vdata and the threshold voltage compensation of the drive transistor Tdr are completed, and the gate of Tdr and the first pole are maintained through the storage capacitor Cst. Potential does not change.
  • the first scan signal s1 is at a high level
  • the second scan signal s2 is at a high level
  • the light-emitting control signal em is at a low level
  • the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the first power signal vdd provided by the first power signal input terminal VDD is transmitted to the first pole of the driving transistor Tdr through the fifth transistor T5, so that the first pole of the driving transistor Tdr jumps from the data signal vdata to the first power signal vdd,
  • the driving transistor Tdr is turned on.
  • the driving transistor Tdr forms a driving current according to the gate potential and the first electrode voltage, and transmits the driving current to the anode of the light emitting device D1 through the sixth transistor T6 to drive the light emitting device D1 to emit light.
  • the drive current is:
  • ⁇ is the carrier mobility of the driving transistor Tdr
  • Cox is the capacitance constant of the driving transistor Tdr
  • w is the channel width of the driving transistor Tdr
  • L is the channel length of the driving transistor Tdr
  • vgs is the gate of the driving transistor Tdr.
  • the voltage difference between the pole and the first pole, vth is the threshold voltage of the driving transistor Tdr, vdd' is the voltage of the first power supply signal, and vdata' is the data voltage.
  • the driving current has nothing to do with the threshold voltage of the driving transistor Tdr, and realizes the threshold voltage compensation of the driving transistor Tdr.
  • FIG. 6 exemplarily shows that the gate of the first transistor T1 is connected to the first scan signal input terminal SCAN1.
  • the gate of the first transistor T1 may also be connected to the second scan signal input terminal SCAN2.
  • the first transistor T1 is turned on during the data writing phase to initialize the anode of the light-emitting device D1.
  • the driving transistor Tdr is a P-type transistor, and the sum of the first power supply signal vdd provided by the first power signal input terminal VDD and the threshold voltage vth of the driving transistor Tdr is the first voltage; the initialization signal input terminal VREF provides the initialization The voltage of the signal is greater than zero and less than the first voltage.
  • the threshold voltage vth of the driving transistor Tdr is a negative value.
  • the driving transistor Tdr is turned on.
  • the gate potential of the driving transistor Tdr is the initialization signal vref provided by the initialization signal input terminal VREF.
  • the third transistor T3 and the fourth transistor T4 are turned on, and the first electrode potential of the driving transistor Tdr is the potential of the data signal vdata.
  • Level correlation when the display gray level of the pixel driving circuit is a black gray level, the potential of the data signal vdata is the largest, and at this time, the potential of the data signal vdata can be the first voltage.
  • the initialization signal vref In the data writing stage, by setting the initialization signal vref to be lower than the first voltage, it can be ensured that the difference between the gate potential of the driving transistor Tdr and the first electrode potential is less than the threshold voltage of the driving transistor Tdr, so that the driving transistor Tdr is turned on and the data is realized. Threshold compensation for write and drive transistor Tdr.
  • the potential of the initialization signal vref is greater than zero, which can ensure that the gate potential of the driving transistor Tdr is relatively high after initialization, so that the time required to write the gate of the driving transistor Tdr to the first voltage in the data writing stage is relatively short, avoiding initialization.
  • the gate potential of the driving transistor Tdr is too low, resulting in insufficient data voltage writing, and at the same time, it can avoid different driving currents caused by different charging rates of different pixel driving circuits, and improve the display of the display panel provided with the pixel driving circuit. uniformity.
  • an embodiment of the present application further provides a display panel, where the display panel includes the pixel driving circuit provided by any embodiment of the present application.
  • the display panel 10 includes a plurality of pixel driving circuits 11 , and each pixel driving circuit 11 drives the light-emitting device to emit light during operation, thereby realizing the display of the display panel 10 .
  • an embodiment of the present application further provides a display device, and the display device 20 includes the display panel 21 provided in any embodiment of the present application.

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Abstract

一种像素驱动电路、显示面板和显示装置，该像素驱动电路包括：驱动晶体管（Tdr）、存储模块（10）、数据写入模块（20）、第一初始化模块（30）、第二初始化模块（40）和发光器件（D1）；第一初始化模块（30）设置为对驱动晶体管（Tdr）的栅极进行初始化；第二初始化模块（40）的控制端和第一端与扫描信号输入端连接，设置为对发光器件（D1）进行初始化；数据写入模块（20）设置为向驱动晶体管（Tdr）的栅极写入数据电压；存储模块（10）设置为存储驱动晶体管（Tdr）的栅极电压；驱动晶体管（Tdr）设置为根据数据电压输出驱动电流，驱动发光器件（D1）发光。

Description

像素驱动电路、显示面板和显示装置
本申请要求在2020年09月25日提交中国专利局、申请号为202011025787.9的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及显示技术领域，尤其涉及一种像素驱动电路、显示面板和显示装置
背景技术
在显示面板显示的过程中，像素驱动电路驱动发光二极管发光进行显示。当显示面板的刷新频率比较高或像素密度(Pixels Per Inch，PPI)比较高时，显示面板的远端和近端的像素驱动电路的充电率不同，导致显示面板的不同位置发光亮度不同，显示面板的显示均一性比较差。
发明内容
本申请提供一种像素驱动电路、显示面板和显示装置，以减少像素驱动电路的充电时间，提高显示面板的显示均一性。
本申请实施例提供了一种像素驱动电路，包括：驱动晶体管；第一初始化模块，所述第一初始化模块与所述驱动晶体管连接，所述第一初始化模块设置为对所述驱动晶体管的栅极进行初始化；发光器件；扫描信号输入端；第二初始化模块，所述第二初始化模块的控制端和第一端与所述扫描信号输入端连接，所述第二初始化模块的第二端与所述发光器件连接，所述第二初始化模块设置为对所述发光器件进行初始化；数据写入模块，所述数据写入模块与所述驱动晶体管连接，所述数据写入模块设置为向所述驱动晶体管的栅极写入数据电压；存储模块，所述存储模块与所述驱动晶体管连接，所述存储模块设置为存储所述驱动晶体管的栅极电压；所述驱动晶体管与所述发光器件连接，所述驱动晶体管设置为根据所述数据电压输出驱动电流，驱动所述发光器件发光。
本申请实施例还提供了一种显示面板，包括本申请任意实施例提供的像素驱动电路。
本申请实施例还提供了一种显示装置，包括本申请任意实施例提供的显示面板。
本申请实施例的技术方案，通过设置第一初始化模块的第一端与初始化信号输入端连接，第二初始化模块的控制端和第一端与扫描信号输入端连接，在对驱动晶体管的栅极和发光器件的阳极进行初始化时，可以通过初始化信号对驱动晶体管的栅极进行初始化，初始化信号可以根据像素驱动电路的数据写入阶段的时长适应性设置，避免初始化结束时驱动晶体管的栅极电位太低导致的数据电压写入不充分，同时可以避免不同的像素驱动电路的充电率不同导致的驱动电流不同，提高了设置有像素驱动电路的显示面板的显示均一性。而且，通过扫描信号对发光器件的阳极进行初始化，可以避免额外设置另一初始化信号输入端，从而可以避免额外设置一条初始化信号线，降低了显示面板的布线难度，有利于显示面板实现高刷新频率或高PPI。
附图说明
图1为一种显示面板的结构示意图。
图2为本申请实施例提供的一种像素驱动电路的结构示意图。
图3为本申请实施例提供的另一种像素驱动电路的结构示意图。
图4为本申请实施例提供的另一种像素驱动电路的结构示意图。
图5为本申请实施例提供的另一种像素驱动电路的结构示意图。
图6为本申请实施例提供的另一种像素驱动电路的结构示意图。
图7为图6提供的像素驱动电路对应的一种时序图。
图8为本申请实施例提供的一种显示面板的结构示意图。
图9为本申请实施例提供的一种显示装置的结构示意图。
具体实施方式
下面结合附图和实施例对本申请进行说明。此处所描述的实施例仅仅用于解释本申请，而非对本申请的限定。为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。
如图1所示，该显示面板包括信号线101和驱动芯片102，驱动芯片102设置于显示面板的第一端103，信号线101由显示面板的第一端103延伸至与第一端103相对设置的第二端104，驱动芯片102通过信号线101为显示面板中的像素驱动电路提供数据信号。
例如，信号线101可以为数据线和电源信号线。当显示面板的刷新频率比较高或PPI比较高时，显示面板中的像素驱动电路的一帧时长比较短，使得像 素驱动电路的数据写入阶段的时长比较短。信号线101沿其延伸方向连接多个像素驱动电路，作为信号线101的负载，使得信号线101沿自身延伸方向的阻抗越来越大，导致信号线101为不同位置的像素驱动电路充电时充电率不同。在像素驱动电路的数据写入阶段时长比较短时，信号线101为不同位置的像素驱动电路充电的充电率不同，使得信号线101为不同位置的像素驱动电路提供的信号电压不同，导致不同位置的像素驱动电路形成的驱动电流不同，进而使得显示面板的显示均一性比较差。示例性地，当信号线101为数据线时，沿着信号线101延伸的方向，多个像素驱动电路的充电率越来越小，使得多个像素驱动电路写入的数据电压越来越小，导致显示面板的发光亮度越来越亮，显示面板的显示均一性比较差。
本申请实施例提供了一种像素驱动电路。如图2所示，该像素驱动电路包括驱动晶体管Tdr、存储模块10、数据写入模块20、第一初始化模块30、第二初始化模块40和发光器件D1；第一初始化模块30与驱动晶体管Tdr连接，第一初始化模块30设置为对驱动晶体管Tdr的栅极进行初始化；第二初始化模块40的控制端和第一端与像素驱动电路的扫描信号输入端连接，设置为对发光器件D1进行初始化；数据写入模块20设置为向驱动晶体管Tdr的栅极写入数据电压；存储模块10设置为存储驱动晶体管Tdr的栅极电压；驱动晶体管Tdr设置为根据数据电压输出驱动电流，驱动发光器件D1发光。
第一初始化模块30的第一端可以与像素驱动电路的初始化信号输入端VREF连接，第一初始化模块30的第二端可以与驱动晶体管Tdr的栅极连接。通过控制第一初始化模块30导通，初始化信号输入端VREF提供的初始化信号传输至驱动晶体管Tdr的栅极，可以对驱动晶体管Tdr的栅极进行初始化。第二初始化模块40的控制端和第一端与像素驱动电路的扫描信号输入端连接，第二初始化模块40的第二端与发光器件D1的阳极连接，通过控制第二初始化模块40导通，扫描信号输入端提供的扫描信号可以通过第二初始化模块40传输至发光器件D1的阳极，实现对发光器件D1的阳极的初始化。在对驱动晶体管Tdr的栅极初始化和对发光器件D1的阳极初始化后，通过数据写入模块20向驱动晶体管Tdr的栅极写入数据电压，存储模块10存储驱动晶体管Tdr的栅极电压，驱动晶体管Tdr根据栅极电压形成驱动电流，驱动发光器件D1发光。
在对驱动晶体管Tdr的栅极初始化和对发光器件D1的阳极初始化的过程中，通过初始化信号输入端VREF提供的初始化信号对驱动晶体管Tdr的栅极进行初始化，驱动晶体管Tdr的栅极电位为初始化信号。在像素驱动电路的数据写入阶段，将数据电压写入驱动晶体管Tdr的栅极所需的时间与初始化信号和充电率相关。初始化信号的电位越高，充电率越大，所需时间越短。当像素驱动电路的一帧工作时长比较短时，像素驱动电路的数据写入时间比较短，此 时可以使初始化信号的电位比较高，实现在短时间内实现将数据电压写入驱动晶体管Tdr的栅极，避免了初始化结束时驱动晶体管Tdr的栅极电位太低导致的数据电压写入不充分，同时可以避免不同的像素驱动电路的充电率不同导致的驱动电流不同，提高了设置有像素驱动电路的显示面板的显示均一性。同时，第二初始化模块40通过扫描信号输入端提供的扫描信号对发光器件D1的阳极进行初始化，避免额外设置另一初始化信号输入端，从而可以避免额外设置一条初始化信号线，降低了显示面板的布线难度，有利于显示面板实现高刷新频率或高PPI。
继续参考图2，扫描信号输入端包括第一扫描信号输入端SCAN1和第二扫描信号输入端SCAN2；第一扫描信号输入端SCAN1与第一初始化模块30的控制端连接，第二扫描信号输入端SCAN2与数据写入模块20的控制端连接；第二初始化模块40的控制端和第一端与第一扫描信号输入端SCAN1或第二扫描信号输入端SCAN2连接。
图2示例性地示出了第二初始化模块40的控制端和第一端与第一扫描信号输入端SCAN1连接。在像素驱动电路的初始化阶段，第一扫描信号输入端SCAN1提供的第一扫描信号控制第一初始化模块30和第二初始化模块40导通，初始化信号输入端VREF提供的初始化信号通过第一初始化模块30传输至驱动晶体管Tdr的栅极，对驱动晶体管Tdr的栅极进行初始化。同时，第二初始化模块40将第一扫描信号传输至发光器件D1的阳极，对发光器件D1的阳极进行初始化。由于驱动晶体管Tdr的栅极初始化后的电位为初始化信号的电位，发光器件D1的阳极初始化后的电位为第一扫描信号的电位，初始化信号的电位可以比较高，实现像素驱动电路在数据写入阶段，短时间内将数据电压写入驱动晶体管Tdr的栅极，提高显示面板的显示均一性。同时，第一扫描信号的电位可以为低电平，满足发光器件D1的阳极初始化要求。
如图3所示，第二初始化模块40的控制端和第一端还可以与第二扫描信号输入端SCAN2连接。在像素驱动电路的初始化阶段，第一扫描信号输入端SCAN1提供的第一扫描信号控制第一初始化模块30导通，初始化信号输入端VREF提供的初始化信号通过第一初始化模块30传输至驱动晶体管Tdr的栅极，对驱动晶体管Tdr的栅极进行初始化。在数据写入阶段，第二扫描信号输入端SCAN2提供的第二扫描信号控制第二初始化模块40导通，第二扫描信号输入端SCAN2提供的第二扫描信号通过第二初始化模块40传输至发光器件D1的阳极，对发光器件D1的阳极进行初始化。
如图4所示，第二初始化模块40包括第一晶体管T1；第一晶体管T1的栅极作为第二初始化模块40的控制端，第一晶体管T1的第一极作为第二初始化 模块40的第一端，第一晶体管T1的第二极作为第二初始化模块40的第二端，第一晶体管T1的第二极与发光器件D1的阳极连接。
图4中示例性地示出了第一晶体管T1为P型晶体管，且第一晶体管T1的栅极和第一极与第一扫描信号输入端SCAN1连接。在像素驱动电路的初始化阶段，第一扫描信号为低电平，控制第一晶体管T1导通，第一扫描信号通过第一晶体管T1传输至发光器件D1的阳极，对发光器件D1的阳极进行初始化。而且，第一扫描信号为低电平时，其电位小于零，可以满足发光器件D1的阳极初始化需求。
在其他实施例中，第一晶体管T1的栅极和第一极还可以与第二扫描信号输入端SCAN2连接。在像素驱动电路的初始化阶段，第一扫描信号输入端SCAN1提供的第一扫描信号控制第一初始化模块30导通，对驱动晶体管Tdr的栅极进行初始化。在数据写入阶段，第二扫描信号输入端SCAN2提供的第二扫描信号为低电平，控制第一晶体管T1导通，第二扫描信号通过第一晶体管T1传输至发光器件D1的阳极，对发光器件D1的阳极进行初始化。同理，第二扫描信号为低电平时，其电位小于零，可以满足发光器件D1的阳极初始化需求。
如图5所示，像素驱动电路还包括初始化信号输入端VREF和数据信号输入端VDATA；第一初始化模块30包括第二晶体管T2，数据写入模块20包括第三晶体管T3；第二晶体管T2的栅极与第一扫描信号输入端SCAN1连接，第二晶体管T2的第一极与初始化信号输入端VREF连接，第二晶体管T2的第二极与驱动晶体管Tdr的栅极连接；第三晶体管T3的栅极与第二扫描信号输入端SCAN2连接，第三晶体管T3的第一极与数据信号输入端VDATA连接，第三晶体管T3的第二极与驱动晶体管Tdr的第一极连接。
图5中示例性地示出了第二晶体管T2和第三晶体管T3为P型晶体管。在像素驱动电路的初始化阶段，第一扫描信号为低电平，第二晶体管T2导通，初始化信号输入端VREF提供的初始化信号通过第二晶体管T2传输至驱动晶体管Tdr的栅极，对驱动晶体管Tdr的栅极进行初始化。在像素驱动电路的数据写入阶段，第二扫描信号为低电平，第三晶体管T3导通，数据信号输入端VDATA提供的数据信号通过第三晶体管T3传输至驱动晶体管Tdr的栅极，实现数据写入。然后，驱动晶体管Tdr根据栅极电压形成驱动电流，驱动发光器件D1发光。
如图6所示，像素驱动电路还包括阈值补偿模块50、发光控制模块60、发光控制信号输入端EM、第一电源信号输入端VDD和第二电源信号输入端VSS；存储模块10包括存储电容Cst；阈值补偿模块50的控制端与第二扫描信号输入端SCAN2连接，阈值补偿模块50的第一端与驱动晶体管Tdr的栅极和存储电容Cst的第一极连接，阈值补偿模块50的第二端与驱动晶体管Tdr的第二极连 接；发光控制模块60的控制端与发光控制信号输入端EM连接，发光控制模块60的第一端和存储电容Cst的第二极与第一电源信号输入端VDD连接，发光控制模块60的第二端与驱动晶体管Tdr的第一极连接，发光控制模块60的第三端与驱动晶体管Tdr的第二极连接，发光控制模块60的第四端与发光器件D1的阳极连接，发光器件D1的阴极与第二电源信号输入端VSS连接。
阈值补偿模块50的控制端与第二扫描信号输入端SCAN2连接，阈值补偿模块50设置为在像素驱动电路的数据写入阶段对驱动晶体管Tdr的阈值电压进行补偿。发光控制模块60的控制端与发光控制信号输入端EM连接，发光控制模块60，设置为在像素驱动电路的发光阶段控制存储电容Cst耦合数据电压至驱动晶体管Tdr，使驱动晶体管Tdr根据数据信号形成驱动电流，驱动发光器件D1发光。
继续参考图6，阈值补偿模块50包括第四晶体管T4；第四晶体管T4的栅极作为阈值补偿模块50的控制端，第四晶体管T4的第一极作为阈值补偿模块50的第一端，第四晶体管T4的第二极作为阈值补偿模块50的第二端。
图6中示例性地示出了第四晶体管T4为P型晶体管。第四晶体管T4的栅极与第二扫描信号输入端SCAN2连接，第四晶体管T4的第一极与驱动晶体管Tdr的栅极连接，第四晶体管T4的第二极与驱动晶体管Tdr的第二极连接。在像素驱动电路的数据写入阶段，第二扫描信号输入端SCAN2提供的第二扫描信号为低电平，第三晶体管T3和第四晶体管T4导通，数据信号通过第三晶体管T3、驱动晶体管Tdr和第四晶体管T4写入至驱动晶体管Tdr的栅极，直至驱动晶体管Tdr的栅极电位为数据电压和驱动晶体管Tdr的阈值电压之和，驱动晶体管Tdr截止，实现了数据信号写入和驱动晶体管Tdr的阈值电压补偿。
继续参考图6，发光控制模块60包括第五晶体管T5和第六晶体管T6。第五晶体管T5的第一极作为发光控制模块60的第一端，第五晶体管T5的第二极作为发光控制模块60的第二端，第六晶体管T6的第一极作为发光控制模块60的第三端，第六晶体管T6的第二极作为发光控制模块60的第四端，第五晶体管T5的栅极和第六晶体管T6的栅极作为发光控制模块60的控制端。
图6中示例性地示出了第五晶体管T5和第六晶体管T6为P型晶体管。在像素驱动电路的发光阶段，发光控制信号输入端EM提供的发光控制信号为低电平，控制第五晶体管T5和第六晶体管T6导通，第一电源信号输入端VDD提供的第一电源信号传输至驱动晶体管Tdr的第一极，且驱动晶体管Tdr的栅极电位为数据信号和驱动晶体管Tdr的阈值电压之和，则驱动晶体管Tdr根据第一电源信号、数据信号和驱动晶体管Tdr的阈值电压形成驱动电流，并通过第六晶体管T6传输至发光器件D1，驱动发光器件D1发光。
参阅图7，s1为第一扫描信号输入端SCAN1提供的第一扫描信号的时序图，s2为第二扫描信号输入端SCAN2提供的第二扫描信号的时序图，em为发光控制信号输入端EM提供的发光控制信号的时序图。
以下结合图6和图7说明像素驱动电路的工作过程。
在初始化阶段t1，第一扫描信号s1为低电平，第二扫描信号s2为高电平，发光控制信号em为高电平，第一晶体管T1和第二晶体管T2导通，第一扫描信号通过第一晶体管T1传输至发光器件D1的阳极，对发光器件D1的阳极进行初始化，初始化信号输入端VREF提供的初始化信号通过第二晶体管T2传输至驱动晶体管Tdr的栅极，对驱动晶体管Tdr的栅极进行初始化。在初始化阶段t1结束后，驱动晶体管Tdr导通。
在数据写入阶段t2，第一扫描信号s1为高电平，第二扫描信号s2为低电平，发光控制信号em为高电平，第三晶体管T3和第四晶体管T4导通，数据信号输入端VDATA提供的数据信号通过第三晶体管T3、驱动晶体管Tdr和第四晶体管T4写入至驱动晶体管Tdr的栅极，直至驱动晶体管Tdr的栅极电位为数据电压vdata'和驱动晶体管Tdr的阈值电压vth之和，即为vdata'+vth，驱动晶体管Tdr截止，完成了数据信号vdata的写入以及驱动晶体管Tdr的阈值电压补偿，并通过存储电容Cst维持Tdr的栅极和第一极两极的电位不变。
在发光阶段t3，第一扫描信号s1为高电平，第二扫描信号s2为高电平，发光控制信号em为低电平，第五晶体管T5和第六晶体管T6导通。第一电源信号输入端VDD提供的第一电源信号vdd通过第五晶体管T5传输至驱动晶体管Tdr的第一极，使得驱动晶体管Tdr的第一极由数据信号vdata跳变为第一电源信号vdd，驱动晶体管Tdr导通。驱动晶体管Tdr根据栅极电位和第一极电压形成驱动电流，并通过第六晶体管T6传输至发光器件D1的阳极，驱动发光器件D1发光。驱动电流为：
Figure PCTCN2021107572-appb-000001
Figure PCTCN2021107572-appb-000002
其中，μ为驱动晶体管Tdr的载流子迁移率，Cox为驱动晶体管Tdr的电容常数，w为驱动晶体管Tdr的沟道宽度，L为驱动晶体管Tdr的沟道长度，vgs为驱动晶体管Tdr的栅极和第一极的压差，vth为驱动晶体管Tdr的阈值电压，vdd′为第一电源信号的电压，vdata′为数据电压。
由驱动电流公式可知，驱动电流与驱动晶体管Tdr的阈值电压无关，实现 了驱动晶体管Tdr的阈值电压补偿。
图6中示例性地示出了第一晶体管T1的栅极与第一扫描信号输入端SCAN1连接。在其他实施例中，第一晶体管T1的栅极还可以与第二扫描信号输入端SCAN2连接，此时第一晶体管T1在数据写入阶段导通，对发光器件D1的阳极进行初始化。
继续参考图6，驱动晶体管Tdr为P型晶体管，第一电源信号输入端VDD提供的第一电源信号vdd和驱动晶体管Tdr的阈值电压vth之和为第一电压；初始化信号输入端VREF提供的初始化信号的电压大于零，且小于第一电压。
当驱动晶体管Tdr为P型晶体管时，驱动晶体管Tdr的阈值电压vth为负值。驱动晶体管Tdr的栅源压差(即驱动晶体管Tdr的栅极电位和第一极电位的差值)小于驱动晶体管Tdr的阈值电压vth时，驱动晶体管Tdr导通。
在像素驱动电路的初始化阶段，驱动晶体管Tdr的栅极电位为初始化信号输入端VREF提供的初始化信号vref。在像素驱动电路的数据写入阶段，第三晶体管T3和第四晶体管T4导通，驱动晶体管Tdr的第一极电位为数据信号vdata的电位，由于数据信号vdata的电位与像素驱动电路的显示灰阶相关，当像素驱动电路的显示灰阶为黑灰阶时，数据信号vdata的电位最大，此时数据信号vdata的电位可以为第一电压。在数据写入阶段，通过设置初始化信号vref小于第一电压，可以保证驱动晶体管Tdr的栅极电位和第一极电位的差值小于驱动晶体管Tdr的阈值电压，保证驱动晶体管Tdr导通，实现数据写入和驱动晶体管Tdr的阈值补偿。
初始化信号vref的电位大于零，可以保证初始化后驱动晶体管Tdr的栅极电位比较高，从而在数据写入阶段将驱动晶体管Tdr的栅极写至第一电压所需要的时间比较短，避免了初始化结束时驱动晶体管Tdr的栅极电位太低导致的数据电压写入不充分，同时可以避免不同的像素驱动电路的充电率不同导致的驱动电流不同，提高了设置有像素驱动电路的显示面板的显示均一性。
如图8所示，本申请实施例还提供一种显示面板，该显示面板包括本申请任意实施例提供的像素驱动电路。
如图8所示，显示面板10包括多个像素驱动电路11，每个像素驱动电路11在工作过程中驱动发光器件发光，从而实现显示面板10的显示。
如图9所示，本申请实施例还提供一种显示装置，该显示装置20包括本申请任意实施例提供的显示面板21。

Claims (16)

  1. 一种像素驱动电路，包括：
    驱动晶体管；
    第一初始化模块，所述第一初始化模块与所述驱动晶体管连接，所述第一初始化模块设置为对所述驱动晶体管的栅极进行初始化；
    发光器件；
    第二初始化模块，所述第二初始化模块的控制端和第一端与扫描信号输入端连接，所述第二初始化模块的第二端与所述发光器件连接，所述第二初始化模块设置为对所述发光器件进行初始化；
    数据写入模块，所述数据写入模块与所述驱动晶体管连接，所述数据写入模块设置为向所述驱动晶体管的栅极写入数据电压；
    存储模块，所述存储模块与所述驱动晶体管连接，所述存储模块设置为存储所述驱动晶体管的栅极电压；
    所述驱动晶体管与所述发光器件连接，所述驱动晶体管设置为根据所述数据电压输出驱动电流，驱动所述发光器件发光。
  2. 根据权利要求1所述的像素驱动电路，其中，所述扫描信号输入端包括第一扫描信号输入端和第二扫描信号输入端；
    所述第一扫描信号输入端与所述第一初始化模块的控制端连接，所述第二扫描信号输入端与所述数据写入模块的控制端连接；
    所述第二初始化模块的控制端和第一端与所述第一扫描信号输入端或所述第二扫描信号输入端连接。
  3. 根据权利要求1所述的像素驱动电路，其中，所述第二初始化模块包括第一晶体管；
    所述第一晶体管的栅极作为所述第二初始化模块的控制端，所述第一晶体管的第一极作为所述第二初始化模块的第一端，所述第一晶体管的第二极与所述发光器件的阳极连接。
  4. 根据权利要求3所述的像素驱动电路，其中，所述扫描信号输入端包括第一扫描信号输入端和第二扫描信号输入端；所述第一初始化模块包括第二晶体管，所述数据写入模块包括第三晶体管。
    所述第二晶体管的栅极与所述第一扫描信号输入端连接，所述第二晶体管的第一极与初始化信号输入端连接，所述第二晶体管的第二极与所述驱动晶体管的栅极连接；
    所述第三晶体管的栅极与所述第二扫描信号输入端连接，所述第三晶体管的第一极与数据信号输入端连接，所述第三晶体管的第二极与所述驱动晶体管的第一极连接。
  5. 根据权利要求4所述的像素驱动电路，还包括阈值补偿模块、发光控制模块；所述存储模块包括存储电容；
    所述阈值补偿模块的控制端与所述第二扫描信号输入端连接，所述阈值补偿模块的第一端与所述驱动晶体管的栅极和所述存储电容的第一极连接，所述阈值补偿模块的第二端与所述驱动晶体管的第二极连接；所述发光控制模块的控制端与发光控制信号输入端连接，所述发光控制模块的第一端和所述存储电容的第二极与第一电源信号输入端连接，所述发光控制模块的第二端与所述驱动晶体管的第一极连接，所述发光控制模块的第三端与所述驱动晶体管的第二极连接，所述发光控制模块的第四端与所述发光器件的阳极连接，所述发光器件的阴极与第二电源信号输入端连接。
  6. 根据权利要求5所述的像素驱动电路，其中，所述阈值补偿模块包括第四晶体管；
    所述第四晶体管的栅极作为所述阈值补偿模块的控制端，所述第四晶体管的第一极作为所述阈值补偿模块的第一端，所述第四晶体管的第二极作为所述阈值补偿模块的第二端。
  7. 根据权利要求6所述的像素驱动电路，其中，所述发光控制模块包括第五晶体管和第六晶体管；
    所述第五晶体管的第一极作为所述发光控制模块的第一端，所述第五晶体管的第二极作为所述发光控制模块的第二端，所述第六晶体管的第一极作为所述发光控制模块的第三端，所述第六晶体管的第二极作为所述发光控制模块的第四端，所述第五晶体管的栅极和所述第六晶体管的栅极作为所述发光控制模块的控制端。
  8. 根据权利要求5所述的像素驱动电路，其中，所述驱动晶体管为P型晶体管，所述第一电源信号输入端提供的第一电源信号和所述驱动晶体管的阈值电压之和为第一电压；所述初始化信号输入端提供的初始化信号的电压大于零，且小于所述第一电压。
  9. 根据权利要求2所述的像素驱动电路，其中，所述第一初始化模块的第一端与所述初始化信号输入端连接，所述第一初始化模块的第二端与所述驱动晶体管的栅极连接。
  10. 根据权利要求3所述的像素驱动电路，其中，所述第一晶体管T1为P 型晶体管。
  11. 根据权利要求4所述的像素驱动电路，其中，所述第二晶体管和所述第三晶体管均为P型晶体管。
  12. 根据权利要求6所述的像素驱动电路，其中，所述第四晶体管为P型晶体管。
  13. 根据权利要求7所述的像素驱动电路，其中，所述第五晶体管和所述第六晶体管均为P型晶体管。
  14. 一种显示面板，包括权利要求1-13任一项所述的像素驱动电路。
  15. 根据权利要求14所述的显示面板，包括多个像素驱动电路，其中，每个像素驱动电路设置为驱动所述每个像素驱动电路中的发光器件发光。
  16. 一种显示装置，包括权利要求14所述的显示面板。
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