WO2019233120A1 - 像素电路及其驱动方法、显示面板 - Google Patents
像素电路及其驱动方法、显示面板 Download PDFInfo
- Publication number
- WO2019233120A1 WO2019233120A1 PCT/CN2019/075239 CN2019075239W WO2019233120A1 WO 2019233120 A1 WO2019233120 A1 WO 2019233120A1 CN 2019075239 W CN2019075239 W CN 2019075239W WO 2019233120 A1 WO2019233120 A1 WO 2019233120A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- circuit
- transistor
- terminal
- signal
- driving
- Prior art date
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0202—Addressing of scan or signal lines
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
- G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0278—Details of driving circuits arranged to drive both scan and data electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0294—Details of sampling or holding circuits arranged for use in a driver for data electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/06—Details of flat display driving waveforms
- G09G2310/061—Details of flat display driving waveforms for resetting or blanking
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
Definitions
- Embodiments of the present disclosure relate to a pixel circuit, a driving method thereof, and a display panel.
- OLED display devices have gradually received people's attention due to their advantages such as wide viewing angles, high contrast, fast response speed, and higher luminous brightness and lower driving voltage than inorganic light-emitting display devices. extensive attention. Due to the above characteristics, organic light emitting diodes (OLEDs) can be applied to devices with display functions such as mobile phones, displays, notebook computers, digital cameras, instruments and meters.
- the pixel circuit in the OLED display device generally adopts a matrix driving method, and is divided into an active matrix (AM) drive and a passive matrix (PM) drive according to whether a switching element is introduced in each pixel unit.
- AM active matrix
- PM passive matrix
- AMOLED integrates a set of thin film transistors and storage capacitors in the pixel circuit of each pixel. By driving and controlling the thin film transistors and storage capacitors, the control of the current flowing through the OLED is achieved, so that the OLED can be used as required. Glow.
- AMOLED Compared with PMOLED, AMOLED requires less driving current, lower power consumption, and longer life, which can meet the large-scale display requirements of high resolution and multi-gray scale. At the same time, AMOLED has obvious advantages in terms of viewing angle, color reduction, power consumption, and response time. It is suitable for high information content and high resolution display devices.
- At least one embodiment of the present disclosure provides a pixel circuit including a driving circuit, a data writing circuit, a compensation circuit, and a light emitting element.
- the driving circuit includes a control terminal, a first terminal, and a second terminal, and is configured to control a driving current flowing through the first terminal and the second terminal for driving the light emitting element to emit light;
- the data write The circuit is connected to a first end of the driving circuit, and is configured to write a data signal to the first end of the driving circuit in response to a first scanning signal;
- the light emitting element includes a first terminal And a second terminal, a first terminal of the light emitting element is configured to receive the driving current, and a second terminal of the light emitting element is connected to a second voltage terminal.
- the pixel circuit provided by an embodiment of the present disclosure further includes a first light emission control circuit, the first light emission control circuit is connected to the first terminal of the driving circuit and the first voltage terminal, and is configured to respond to the first A light-emitting control signal applies a first voltage received by the first voltage terminal to a first terminal of the driving circuit.
- the pixel circuit provided by an embodiment of the present disclosure further includes a second light emission control circuit, the second light emission control circuit is connected to the second end of the driving circuit and the first end of the light emitting element, and is configured to The driving current is applied to the light emitting element in response to a second light emission control signal.
- the pixel circuit provided by an embodiment of the present disclosure further includes a reset circuit connected to a reset voltage terminal and a first terminal of the light emitting element, and configured to receive the reset voltage terminal in response to a reset signal.
- a reset voltage is applied to the first terminal of the light emitting element; the reset signal is the second scan signal.
- the driving circuit includes a first transistor; a gate of the first transistor is used as a control terminal of the driving circuit, and a first electrode of the first transistor is used as A first terminal of the driving circuit and a second electrode of the first transistor serve as a second terminal of the driving circuit.
- the data writing circuit includes a second transistor; a gate of the second transistor is connected to a first scanning line to receive the first scanning signal, and A first pole of a second transistor is connected to a data line to receive the data signal, and a second pole of the second transistor is connected to a first end of the driving circuit.
- the compensation circuit includes a third transistor and a capacitor; a gate of the third transistor is connected to a second scan line to receive the second scan signal, and The first pole of the third transistor is connected to the second end of the driving circuit, and the second pole of the third transistor is connected to the control end of the driving circuit; the first pole of the capacitor is connected to the driving circuit.
- the control terminal is connected, and the second pole of the capacitor is connected to the first voltage terminal.
- the first light emission control circuit includes a fourth transistor; a gate of the fourth transistor is connected to a first light emission control line to receive the first light emission control signal A first pole of the fourth transistor is connected to the first voltage terminal to receive the first voltage, and a second pole of the fourth transistor is connected to a first terminal of the driving transistor.
- the second light emission control circuit includes a fifth transistor; a gate of the fifth transistor is connected to a second light emission control line to receive the second light emission control signal A first pole of the fifth transistor is connected to a second end of the driving circuit, and a second pole of the fifth transistor is connected to a first end of the light emitting element.
- the reset circuit includes a sixth transistor; a gate of the sixth transistor is connected to a second scan line to receive the second scan signal as the reset signal A first pole of the sixth transistor is connected to a reset voltage terminal to receive the reset voltage, and a second pole of the sixth transistor is connected to a first terminal of the light emitting element.
- the third transistor and the sixth transistor are N-type transistors, the first transistor, the second transistor, the fourth transistor, and the The fifth transistor is a P-type transistor.
- the compensation circuit and the driving circuit include different types of transistors.
- the compensation circuit includes an N-type transistor
- the driving circuit includes a P-type transistor
- the compensation circuit and the reset circuit each include an N-type transistor, the driving circuit, the data writing circuit, the first light emission control circuit, and the Each of the second light emission control circuits includes a P-type transistor.
- At least one embodiment of the present disclosure also provides a display panel including a plurality of pixel units arranged in an array, each of the pixel units including a pixel circuit provided by any of the embodiments of the present disclosure.
- the display panel provided by an embodiment of the present disclosure further includes a plurality of light emission control lines, the plurality of pixel units are arranged in a plurality of rows, the second light emission control circuit of the pixel circuit of the n-th pixel unit and the n + 1th
- the first light emission control circuit of the pixel circuit of the row pixel unit is connected to the same light emission control line, and n is an integer greater than zero.
- At least one embodiment of the present disclosure also provides a driving method of a pixel circuit, including a data writing and compensation phase and a light emitting phase.
- a driving method of a pixel circuit including a data writing and compensation phase and a light emitting phase.
- the data writing and compensation phase inputting the first scanning signal, the second scanning signal, and the data signal to make the data writing circuit, the driving circuit, and the compensation circuit conductive;
- the data writing circuit writes the data signal into the driving circuit, the compensation circuit stores the data signal, and the compensation circuit compensates the driving circuit; in the light-emitting stage, inputting the data signal A first light emission control signal to turn on the first light emission control circuit and the driving circuit, the first light emission control circuit applying the driving current to the light emitting element to make it emit light; the first scan
- the signal and the second scanning signal are simultaneously on signals for at least part of the time period.
- At least one embodiment of the present disclosure also provides a driving method of a pixel circuit, including: an initialization phase, a data writing and compensation phase, a pre-light-emitting phase, and a light-emitting phase.
- the reset signal, the second scan signal, and the second light-emission control signal are input to make the reset circuit, the compensation circuit, and the second light-emission control circuit conductive, and turn all the The reset voltage is applied to the control terminal, the first terminal and the second terminal of the driving circuit, and the first terminal of the light emitting element;
- the data writing and compensation phase the first scanning signal, the A second scan signal and the data signal to turn on the data writing circuit, the driving circuit, and the compensation circuit, the data writing circuit writing the data signal to the driving circuit, and A compensation circuit stores the data signal, and the compensation circuit compensates the driving circuit;
- the pre-light emitting phase the first light emission control signal is input so that the first light emission control circuit and the driving circuit Is turned on, the first light-emitting control
- the driving method provided by an embodiment of the present disclosure further includes: a data writing and holding phase; in the data writing and holding phase, inputting the first scan signal to make the data writing circuit conduct, and inputting The second scan signal is used to turn off the compensation circuit so as to maintain the voltage of the control terminal of the driving circuit.
- FIG. 1 is a schematic block diagram of a pixel circuit provided by some embodiments of the present disclosure
- FIG. 2 is a schematic block diagram of another pixel circuit provided by some embodiments of the present disclosure.
- FIG. 3 is a circuit diagram of an implementation example of the pixel circuit shown in FIG. 2;
- FIG. 4 is a timing diagram of a driving method of a pixel circuit provided by some embodiments of the present disclosure.
- 5 to 9 are schematic circuit diagrams of the pixel circuit shown in FIG. 3 corresponding to the five stages in FIG. 4;
- FIG. 10 is a schematic diagram of a display panel provided by some embodiments of the present disclosure.
- An OLED display device generally includes a plurality of pixel units arranged in an array, and each pixel unit can implement a basic function of driving OLED light emission through a pixel circuit.
- the basic pixel circuit used in an AMOLED display device is usually a 2T1C pixel circuit, that is, two TFTs (Thin-film transistors) and a storage capacitor Cs are used to implement the basic function of driving the OLED to emit light.
- the pixel circuits in the embodiments of the present disclosure are not limited to the above-mentioned pixel circuits, but may also be pixel circuits of other structures, such as 4T1C, 4T2C, 6T1C, or 8T2C pixel circuits.
- the pixel circuit In the process of displaying some video images, in order to reduce the power consumption of the OLED, the pixel circuit can be driven by using low-frequency signals.
- the leakage current of the P-type transistor is relatively large. Low-frequency driving can cause phenomena such as flickers, which limits the use of this pixel circuit.
- At least one embodiment of the present disclosure provides a pixel circuit including a driving circuit, a data writing circuit, a compensation circuit, and a light emitting element.
- the driving circuit includes a control terminal, a first terminal, and a second terminal, and is configured to control a driving current for driving the light emitting element to emit light through the first terminal and the second terminal;
- the data writing circuit is connected to the first terminal of the driving circuit, And configured to write a data signal to the first terminal of the driving circuit in response to the first scanning signal;
- the compensation circuit is connected to the control terminal and the second terminal of the driving circuit and connected to the first voltage terminal, and is configured to store the data writing circuit
- the written data signal compensates the driving circuit in response to the second scanning signal;
- the light-emitting element includes a first end and a second end, the first end of the light-emitting element is configured to receive a driving current, and the second end of the light-emitting element and the second end
- the voltage terminal is connected.
- At least one embodiment of the present disclosure also provides a driving method and a display panel corresponding to the above-mentioned pixel circuit.
- the pixel circuit adopts a hybrid P-type transistor and an N-type transistor, so that low-frequency driving can be achieved.
- the pixel circuit can also be driven.
- the resolution of the display panel using the pixel circuit is improved; on the other hand, since the leakage current of the N-type transistor of the pixel circuit is small, the aging problem of the N-type transistor need not be considered during the use of the pixel circuit.
- the pixel circuit 10 such as a pixel unit for an OLED display device. As shown in FIGS. 1 and 2, the pixel circuit 10 includes a driving circuit 100, a data writing circuit 200, a compensation circuit 300, a first light emitting control circuit 400, and a light emitting element 500.
- the driving circuit 100 includes a first terminal 110, a second terminal 120, and a control terminal 130, which are configured to control a driving current that drives the light emitting element 500 to emit light, and the control terminal 130 of the driving circuit 100 is connected to the first node N1.
- a first terminal 110 of 100 is connected to a second node N2, and a second terminal 120 of the driving circuit 100 is connected to a third node N3.
- the driving circuit 100 may provide a driving current to the light-emitting element 500 to drive the light-emitting element 500 to emit light, and may emit light according to a required "gray scale".
- the light emitting element 500 may be an OLED and configured to be connected to the third node N3 and the second voltage terminal VSS (for example, the second voltage terminal VSS provides a low level, for example, the second voltage terminal VSS is grounded). Examples include, but are not limited to, this situation.
- the light-emitting element 500 may also be connected to the third node N3 through the second light-emitting control circuit 600.
- Embodiments of the present disclosure include, but are not limited to, this case.
- the data writing circuit 200 is connected to the first terminal 110 (the second node N2) of the driving circuit 100, and is configured to write a data signal to the first terminal 110 of the driving circuit 100 in response to the first scan signal.
- the data writing circuit 200 is connected to a data line (data signal terminal Vdata), a second node N2, and a first scan line (first scan signal terminal Gate_N).
- a first scan signal from the first scan signal terminal Gate_N is applied to the data writing circuit 200 to control whether the data writing circuit 200 is turned on or not.
- the data writing circuit 200 may be turned on in response to the first scanning signal, so that the data signal may be written into the first terminal 110 (the second node N2) of the driving circuit 100, and
- the data signal is stored in the compensation circuit 300 so that, for example, a driving current for driving the light emitting element 500 to emit light can be generated based on the data signal during a light emitting stage.
- the compensation circuit 300 is connected to the control terminal 130 (the first node N1) and the second terminal 120 (the third node N3) of the driving circuit and is connected to the first voltage terminal VDD, and is configured to be written by the storage data writing circuit 200.
- the data signal compensates the driving circuit 100 in response to the second scanning signal.
- the compensation circuit 300 may be connected to the second scanning signal line (the second scanning signal terminal Gate_N-1), the first voltage terminal VDD, the first node N1, and the third node N3.
- a second scan signal from the second scan signal terminal Gate_N-1 is applied to the compensation circuit 300 to control whether it is turned on or not.
- the compensation circuit 300 may be turned on in response to the second scan signal, so that the data signal written by the data writing circuit 200 may be stored in the In the capacitor.
- the compensation circuit 300 may electrically connect the control terminal 130 and the second terminal 120 of the driving circuit 100, so that information related to the threshold voltage of the driving circuit 100 is also stored in the corresponding In the capacitor, for example, the driving circuit 100 can be controlled by using the stored data signal and the threshold voltage in the light emitting stage, so that the output of the driving circuit 100 is compensated.
- the compensation circuit 300 may include an N-type transistor.
- the N-type transistor and the P-type transistor have different turn-on voltages.
- the P-type transistor turns on in response to a low-level signal, and the N-type transistor responds to a high-level signal (high Turn on at the aforementioned low-level signal), so that high-level data signals can be prevented from being written to the driving circuit and the compensation circuit during the light-emitting stage to turn off the driving transistor, thereby avoiding the pixel circuit from flickering during low-frequency driving.
- the pixel circuit can be adapted for low-frequency driving.
- an N-type transistor when used, it can use IGZO (Indium, Gallium, Zinc, Oxide) as the active layer of a thin film transistor.
- IGZO Indium, Gallium, Zinc, Oxide
- LTPS Low Temperature, Polysilicon, Low Temperature Polysilicon
- amorphous silicon for example, (Hydrogenated amorphous silicon
- the resolution in the following embodiments is the same, and will not be described again.
- the first light emitting control circuit 400 is connected to the first terminal 110 (the second node N2) and the first voltage terminal VDD of the driving circuit 100, and is configured to receive the first voltage terminal VDD in response to the first light emitting control signal.
- a voltage is applied to the first terminal 110 of the driving circuit 100.
- the first light emission control circuit 400 is connected to the first light emission control terminal EM1, the first voltage terminal VDD, and the second node N2.
- the first light emission control terminal EM1 may be connected to a first light emission control line that provides a first light emission control signal, or connected to a control circuit that provides the first light emission control signal.
- the first light emitting control circuit 400 may be turned on in response to the first light emitting control signal, so that the first voltage VDD may be applied to the first terminal 110 of the driving circuit 100.
- the driving circuit 100 applies this first voltage VDD to the light emitting element 500 to provide a driving current, thereby driving the light emitting element to emit light.
- the first voltage VDD may be a driving voltage, such as a high voltage (higher than the second voltage VSS).
- the light emitting element 500 includes a first end 510 and a second end 520.
- the first end 510 of the light emitting element 500 is configured to receive a driving current from the second end 120 of the driving circuit 100, and the second end 520 of the light emitting element 500 is configured to communicate with The second voltage terminal VSS is connected.
- the first end 510 of the light emitting element 500 is connected to the third node N3.
- FIG. 1 shows that in another embodiment of the present disclosure, as shown in FIG.
- the first end 510 of the light-emitting element 500 may also be connected to the fourth node N4, and The second light emitting control circuit 600 is connected to the third node N3.
- Embodiments of the present disclosure include, but are not limited to, this case.
- the pixel circuit 10 further includes a second light emitting control circuit 600 and a reset circuit 700.
- the second light emission control circuit 600 is connected to the second light emission control terminal EM2, the first terminal 510 of the light emitting element 500, and the second terminal 120 of the driving circuit 100, and is configured to apply a driving current to the second light emission control signal in response to the second light emission control signal.
- Light emitting element 500 is connected to the second light emission control terminal EM2, the first terminal 510 of the light emitting element 500, and the second terminal 120 of the driving circuit 100, and is configured to apply a driving current to the second light emission control signal in response to the second light emission control signal.
- Light emitting element 500 is connected to the second light emission control terminal EM2, the first terminal 510 of the light emitting element 500, and the second terminal 120 of the driving circuit 100, and is configured to apply a driving current to the second light emission control signal in response to the second light emission control signal.
- the second light-emitting control circuit 600 is turned on in response to the second light-emitting control signal provided by the second light-emitting control terminal EM2, so that the driving circuit 100 can apply a driving current to the light-emitting element through the second light-emitting control circuit 600. 500 to make it emit light; and in the non-light-emitting stage, the second light-emitting control circuit 600 is turned off in response to the second light-emitting control signal, thereby preventing current from flowing through the light-emitting element 500 to make it emit light, which can improve the contrast of the corresponding display device .
- the second light-emitting control circuit 600 may also be turned on in response to the second light-emitting control signal, so that the reset circuit 700 may be combined to perform a reset operation on the driving circuit 100 and the light-emitting element 500.
- the second light-emitting control signal is different from the first light-emitting control signal.
- the two light-emitting control signals can be connected to different signal output terminals.
- the second light-emitting control signal can be separately turned on during the initialization phase.
- the first light-emitting control signal and the second light-emitting control signal are both on signals for at least part of the time period.
- the first light-emitting control signal and the second light-emitting control signal can be both on signals at the same time, so that the light-emitting element 500 glow.
- the falling edge of the second light emitting control signal may also be synchronized with the falling edge of the first light emitting control signal in time sequence, so that the data writing and compensation phase directly enters the light emitting phase.
- the first light emission control signal and the second light emission control signal described in the embodiments of the present disclosure are two light emission control signals with different timings.
- the first light emission control signal may be the first light emission control circuit 400 in the pixel circuit 10 that controls the pixel units of the row.
- the first light-emitting control signal also controls the second light-emitting control circuit 600 in the pixel circuit 10 of the pixel unit in the previous row; similarly, the second light-emitting control signal is in the pixel circuit 10 controlling the pixel unit in the same row.
- the control signal of the second light-emitting control circuit 600 is, at the same time, the second light-emitting control signal also controls the first light-emitting control circuit 400 in the pixel circuit 10 of the pixel unit of the next row.
- the way in which the pixel circuits in the two rows of pixel units share the same light emission control signal can simplify the layout space of the display panel, thereby enabling the development of high-resolution display panels.
- the reset circuit 700 is connected to the reset voltage terminal Vinit and the first terminal 510 of the light emitting element 500 and is configured to apply the reset voltage received by the reset voltage terminal Vinit to the first terminal 510 of the light emitting element 500 in response to a reset signal.
- the reset signal is a second scan signal, and the reset signal may also be another signal synchronized with the second scan signal, which is not limited in the embodiments of the present disclosure.
- the reset circuit 700 is connected to the fourth node N4, the reset voltage terminal Vinit, the first terminal 510 of the light-emitting element 500, and the reset control terminal Rst (reset control line), respectively.
- the reset circuit 700 may be turned on in response to a reset signal, so that a reset voltage may be applied to the first terminal 510 (the fourth node N4) of the light-emitting element 500 and reset by the second light-emitting control circuit 600 The voltage is applied to the third node N3, and the reset voltage is applied to the first node N1 through the compensation circuit 300, so that the driving circuit 100, the compensation circuit 300, and the light emitting element 500 can be reset to eliminate the influence of the previous light emitting stage.
- the reset circuit 700 may be implemented using an N-type transistor.
- the types of transistors included in the compensation circuit 300 and the driving circuit 100 are different.
- the compensation circuit 300 includes an N-type transistor
- the driving circuit 100 includes a P-type transistor.
- the pixel circuit includes both an N-type transistor and a P-type transistor. Since the N-type transistor has a small leakage current, the pixel circuit can be prevented from flickering when used for low-frequency driving. Screen phenomenon, and because the size of the N-type transistor is small, the resolution of the display panel using the pixel circuit can be improved; on the other hand, because the leakage current of the N-type transistor in the pixel circuit is small, there is no need to consider N Of aging transistors.
- the driving circuit 100 when the driving circuit 100 is implemented as a driving transistor, for example, the gate of the driving transistor can be used as the control terminal 130 of the driving circuit 100 (connected to the first node N1), and the first electrode (such as the source) can be used as the driving circuit.
- the first terminal 110 of the 100 (connected to the second node N2), and the second electrode (for example, the drain) can be used as the second terminal 120 of the driving circuit 100 (connected to the third node N3).
- the first voltage terminal VDD holds, for example, a DC high-level signal, and this DC high level is referred to as a first voltage; and the second voltage terminal VSS, for example, maintains a DC low level input.
- the DC low level is called a second voltage, and the second voltage is smaller than the first voltage.
- the first node N1, the second node N2, the third node N3, and the fourth node N4 do not indicate actual components, but rather indicate a convergence point of related circuit connections in the circuit diagram. .
- the symbol Vdata can represent both the data signal terminal and the level of the data signal.
- the symbol Vinit can represent both the reset voltage terminal and the reset voltage.
- VDD can represent both the first voltage terminal and the first voltage
- the symbol VSS can represent both the second voltage terminal and the second voltage.
- the pixel circuit 10 shown in FIG. 2 may be implemented as the circuit structure shown in FIG. 3.
- the pixel circuit 10 includes first to sixth transistors T1, T2, T3, T4, T5, and T6, and includes a capacitor C and a light emitting element L1.
- the first transistor T1 is used as a driving transistor, and the other second to sixth transistors are used as switching transistors.
- the light-emitting element L1 may be various types of OLEDs, such as top emission, bottom emission, double-sided emission, and the like, and may emit red, green, blue, or white light, which is not limited in the embodiments of the present disclosure.
- the driving circuit 100 may be implemented as the first transistor T1.
- the gate of the first transistor T1 serves as the control terminal 130 of the driving circuit 100 and is connected to the first node N1;
- the first pole of the first transistor T1 serves as the first terminal 110 of the driving circuit 100 and is connected to the second node N2;
- the second electrode of the transistor T1 serves as the second terminal 120 of the driving circuit 100 and is connected to the third node N3.
- the first transistor T1 is a P-type transistor.
- the P-type transistor is turned on in response to a low-level signal.
- the embodiments of the present disclosure are not limited thereto, and the driving circuit 100 may be a circuit composed of other components.
- the data writing circuit 200 may be implemented as a second transistor T2.
- the gate of the second transistor T2 is connected to the first scan line (the first scan signal terminal Gate_N) to receive the first scan signal, and the first electrode of the second transistor T2 is connected to the data line (the data signal terminal Vdata) to receive the data signal
- the second electrode of the second transistor T2 is connected to the first terminal 110 (second node N2) of the driving circuit 100.
- the second transistor T2 is a P-type transistor, such as a thin film transistor whose active layer is low temperature doped polysilicon. It should be noted that the embodiments of the present disclosure are not limited thereto, and the data writing circuit 200 may be a circuit composed of other components.
- the compensation circuit 300 may be implemented to include a third transistor T3 and a capacitor C.
- the gate of the third transistor T3 is configured to be connected to a second scan line (second scan signal terminal Gate_N-1) to receive a scan signal.
- the first electrode of the third transistor T3 and the control terminal 130 (first node of the driving circuit 100) N1) connection, the second electrode of the third transistor T3 is connected to the second terminal 120 (third node N3) of the driving circuit 100; the first electrode of the capacitor C is connected to the control terminal 130 of the driving circuit 100, and the second terminal of the capacitor C is connected Is connected to the first voltage terminal VDD.
- the third transistor T3 is an N-type transistor.
- the third transistor T3 is an N-type transistor
- IGZO can be used as the active layer of the thin film transistor to reduce the size of the transistor and prevent leakage current.
- the N-type transistor is turned on in response to a high-level signal.
- the first light emission control circuit 400 may be implemented as a fourth transistor T4.
- the gate of the fourth transistor T4 is connected to the first light emission control line (the first light emission control terminal EM1) to receive the first light emission control signal, and the first electrode of the fourth transistor T4 is connected to the first voltage terminal VDD to receive the first voltage
- the second electrode of the fourth transistor T4 is connected to the first terminal 110 (the second node N2) of the driving transistor.
- the fourth transistor T4 is a P-type transistor, for example, a thin film transistor whose active layer is low temperature doped polysilicon. It should be noted that the embodiments of the present disclosure are not limited thereto, and the first light emission control circuit 400 may also be a circuit composed of other components.
- the first terminal 510 (for example, the anode) of the light emitting element L1 is connected to the fourth node N4 and is configured to receive a driving current from the second terminal 120 of the driving circuit 100 through the second light emitting control circuit 600.
- the second terminal of the light emitting element L1 520 (for example, a cathode) is configured to be connected to the second voltage terminal VSS to receive a second voltage.
- the second voltage terminal VSS may be grounded, that is, the second voltage VSS may be 0V.
- the second light emission control circuit 600 may be implemented as a fifth transistor T5.
- the gate of the fifth transistor T5 and the second light emission control line (the second light emission control terminal EM2) are connected to receive the second light emission control signal.
- the first electrode of the fifth transistor T5 and the second terminal 120 (third of the driving circuit 100)
- the node N3 is connected
- the second electrode of the fifth transistor T5 is connected to the first terminal 510 (the fourth node N4) of the light emitting element L1.
- the fifth transistor T5 is a P-type transistor, such as a thin film transistor whose active layer is low temperature doped polysilicon. It should be noted that the embodiments of the present disclosure are not limited thereto, and the second light emission control circuit 700 may also be a circuit composed of other components.
- the reset circuit 400 may be implemented as a sixth transistor T6.
- the gate of the sixth transistor T6 is configured to be connected to a second scan line (reset control terminal Rst) to receive a second scan signal as a reset signal, and the first electrode of the sixth transistor T6 is connected to a reset voltage terminal Vinit to receive a reset voltage.
- the second electrode of the sixth transistor T6 is configured to be connected to the first terminal 510 of the light emitting element L1.
- the sixth transistor T6 is an N-type transistor, such as a thin film transistor with an active layer of IGZO. It should be noted that the embodiments of the present disclosure are not limited thereto, and the reset circuit 400 may also be a circuit composed of other components.
- the low-frequency signal can be used to drive the pixel circuit.
- the low-frequency signal of the P-type transistor is used, and low-frequency signals are used.
- the driver may generate phenomena such as a flicker, which limits the use of the pixel circuit.
- the pixel circuit uses a mixture of N-type and P-type transistors.
- the third transistor T3 and the sixth transistor T6 use N-type transistors, and the remaining transistors use P-type transistors.
- the small-type transistor has a small leakage current, so that the pixel circuit can avoid a flicker phenomenon when it is used for low-frequency driving.
- the third transistor T3 in the compensation circuit in the pixel circuit uses an N-type transistor with a smaller leakage current and a smaller size
- the capacitor C in the compensation circuit can use a smaller size capacitor, which can improve the use of the capacitor.
- the resolution of the display panel of the pixel circuit meanwhile, because the leakage current of the N-type transistor is small, there is no need to consider the aging problem of the N-type transistor.
- the display process of each frame of image includes five phases, namely initialization phase 1, data writing and compensation phase 2, data writing holding phase 3, pre-lighting phase 4 and light-emitting phase 5.
- initialization phase 1 data writing and compensation phase 2
- data writing holding phase 3 data writing holding phase 3
- pre-lighting phase 4 pre-lighting phase 4
- light-emitting phase 5 The timing waveforms of the individual signals in each phase are shown.
- FIG. 5 is a schematic diagram when the pixel circuit shown in FIG. 3 is in the initialization phase 1
- FIG. 6 is a schematic diagram when the pixel circuit shown in FIG. 3 is in the data writing and compensation phase 2
- FIG. 7 is The pixel circuit shown in FIG. 3 is a schematic diagram when the data writing and holding phase 3 is in progress
- FIG. 8 is a schematic diagram when the pixel circuit shown in FIG. 3 is in a pre-light emitting phase 4
- FIG. 9 is the pixel circuit shown in FIG. 3 Schematic diagram when in lighting stage 5.
- the transistors indicated by dashed lines in FIGS. 5 to 9 indicate that they are in an off state during the corresponding phase, and the dashed lines with arrows in FIGS.
- the transistors shown in FIG. 5 to 9 indicate the current direction of the pixel circuit in the corresponding phase.
- the transistors shown in FIG. 5 to FIG. 9 are described by taking the first transistor T1 and the sixth transistor T6 as N-type transistors, and the other transistors as P-type transistors.
- the gates of each N-type transistor are connected to high power It is normally turned on and turned off when it is connected to a low level, and the gate of each P-type transistor is turned on when it is connected to a low level, and turned off when it is connected to a high level.
- the following embodiments are the same and will not be described again.
- a reset signal, a second scan signal, and a second light emission control signal are input to turn on the reset circuit 700, the compensation circuit 300, and the second light emission control circuit 600, so that a reset voltage can be applied to the control of the driving circuit 100
- the second scanning signal and the reset signal are synchronized, that is, the reset signal may also be the second scanning signal.
- the sixth transistor T6 is turned on by the high level of the reset signal, and the third transistor T3 is scanned by the second The high level of the signal is turned on, and the fifth transistor T5 is turned on by the low level of the second light emission control signal; at the same time, the second transistor T2 is turned off by the high level of the first scan signal, and the fourth transistor T4 is turned on by the first light The high level of the control signal is turned off.
- a reset path is formed (as shown by a dashed line with an arrow in FIG. 5). So at this stage, the storage capacitor C and the gate of the first transistor T1 are discharged through the third transistor T3, the fifth transistor T5, and the sixth transistor T6, and the first transistor T1 is discharged through the fifth transistor T5 and the sixth transistor T6 to emit light.
- the element L1 is discharged through the sixth transistor T6, thereby resetting the first node N1, the second node N2, the third node N3, and the light emitting element L1 (that is, the fourth node N4).
- the potentials of the first node N1, the third node N3, and the fourth node N4 are the reset voltage Vinit (a low-level signal, which can be grounded or other low-level signals, for example).
- Vinit a low-level signal, which can be grounded or other low-level signals, for example.
- the first transistor T1 and the fifth transistor T5 are turned on, and the fourth transistor T4 is turned off.
- the potential of the source of the first transistor T1 is discharged until Vinit-Vth is turned off.
- the voltage V GS of the gate (ie, the first node N1) and the source (ie, the second node N2) of the first transistor T1 can be satisfied:
- the first transistor T1 is in an off-bias state where V GS is a fixed bias. With this configuration, the first transistor T1 can enter the data writing and compensation phase 2 from the off state of the fixed bias regardless of whether the data signal of the previous frame is a black state or a white state signal.
- a short-term afterimage problem that may occur in the display device of the pixel circuit 10 due to a hysteresis effect.
- the potential of the first node N1 is the reset voltage Vinit, and the potential of the second node N2 is Vinit-Vth.
- the capacitor C is reset, so that the charge stored in the capacitor C is discharged, so that the data signal in the subsequent stage can be stored in the capacitor C more quickly and reliably; at the same time, the third node N3 and the light emitting The element L1 (ie, the fourth node N4) is also reset, so that the light-emitting element L1 can be displayed in a black state and not emit light before the light-emitting stage 5, and display effects such as the contrast of a display device using the pixel circuit can be improved.
- the first scanning signal, the second scanning signal, and the data signal are input to make the data writing circuit 200, the driving circuit 100, and the compensation circuit 300 conductive, and the data writing circuit 200 writes the data signal
- the driving circuit 100 and the compensation circuit 300 store the data signal, and the compensation circuit 300 compensates the driving circuit 100.
- the second transistor T2 is turned on by the low level of the first scan signal
- the third transistor T3 is turned on by the high level of the second scan signal.
- the sixth transistor T6 is turned on by the high level of the reset signal; at the same time, the fourth transistor T4 is turned off by the high level of the first light emission control signal, and the fifth transistor T5 It is turned off by the high level of the second light emission control signal.
- a data writing and compensation path (shown as a dotted line 1 with an arrow in FIG. 6) and a reset path (shown as a dotted line 2 with an arrow in FIG. 6) are formed.
- the first node N1 is charged (that is, the capacitor C is charged), that is, the potential of the first node N1 is increased.
- the potential of the second node N2 is maintained at Vdata, and according to the characteristics of the first transistor T1, when the potential of the first node N1 increases to Vdata + Vth, the first transistor T1 is turned off and the charging process ends.
- Vdata represents the voltage value of the data signal
- Vth represents the threshold voltage of the first transistor T1. Since the first transistor T1 is described using a P-type transistor as an example, the threshold voltage Vth may be a negative value here.
- the fourth node N4 continues to be discharged through the sixth transistor T6, so the voltage of the fourth node N4 is still the reset voltage Vinit.
- the reset circuit 700 may also be turned off in response to other reset signals, which will not affect the subsequent light-emitting stage of the pixel circuit, which is not limited in the embodiments of the present disclosure.
- the potentials of the first node N1 and the third node N3 are both Vdata + Vth, that is, the voltage information with the data signal and the threshold voltage Vth is stored in the capacitor C for use in In the subsequent light-emitting phase, gray-scale display data is provided and the threshold voltage of the first transistor T1 itself is compensated.
- a first scanning signal is inputted to make the data writing circuit 200 turn on, and a second scanning signal is inputted to make the compensation circuit 300 turn off to maintain the voltage of the control terminal 130 of the driving circuit 100.
- the second transistor T2 is turned on by the low level of the first scan signal; at the same time, the third transistor T3 is turned off by the low level of the second scan signal.
- the second scan signal is a reset signal
- the sixth transistor T6 is turned off by the low level of the reset signal
- the fourth transistor T4 is turned off by the high level of the first light emission control signal
- the fifth transistor T5 is turned off by the second The high level of the light emission control signal is turned off.
- a data writing and holding path is formed (shown by a dotted line with an arrow in FIG. 7).
- the third transistor T3 is turned off, and the potential of the first node N1 is maintained at Vdata + Vth due to the nature of the capacitor.
- the potential of the first node N1 is maintained at Vdata + Vth. That is to say, the voltage information with the data signal and the threshold voltage Vth is continuously stored in the capacitor C, so as to provide the grayscale display data and compensate the threshold voltage of the first transistor T1 itself in the subsequent light-emitting stage.
- a first light emission control signal is input to make the first light emission control circuit 400 and the driving circuit 100 conductive, and the first light emission control circuit 400 applies a first voltage to the first terminal 110 of the driving circuit 100.
- the fourth transistor T4 is turned on by the low level of the first light emission control signal; at the same time, the second transistor T2 is turned off by the high level of the first scanning signal, and The three transistors T3 are turned off by the low level of the second scan signal, the sixth transistor T6 is turned off by the low level of the reset signal, and the fifth transistor T5 is turned off by the high level of the second light emission control signal.
- a pre-emission path is formed (as shown by a dotted line with an arrow in FIG. 8).
- the first voltage is transmitted to the second node N2 through the fourth transistor T4, and the potential of the second node N2 changes from Vdata to the first voltage VDD. Since the fifth transistor T5 is turned off at this stage, it is the voltage of the light emitting element L1 in the next stage. Glowing preparing.
- a first light-emitting control signal and a second light-emitting control signal are input to make the first light-emitting control circuit 400, the second light-emitting control circuit 600, and the driving circuit 100 conductive, and the second light-emitting control circuit 600 applies a driving current to The light-emitting element L1 emits light.
- the fourth transistor T4 is turned on by the low level of the first light emission control signal, and the fifth transistor T5 is turned on by the low level of the second light emission control signal;
- the second transistor T2 is turned off by the high level of the first scan signal, the third transistor T3 is turned off by the low level of the second scan signal, and the sixth transistor T6 is turned off by the low level of the reset signal.
- the potential Vdata + Vth of the first node N1 and the potential of the second node N2 are VDD, so the first transistor T1 also remains on at this stage.
- a driving light-emitting path is formed (shown by a dotted line with an arrow in FIG. 9).
- the light emitting element L1 can emit light under the action of a driving current flowing through the first transistor T1.
- the value of the driving current I L1 flowing through the light-emitting element L1 can be obtained according to the following formula:
- I L1 K (V GS -Vth) 2
- Vth represents the threshold voltage of the first transistor T1
- V GS represents the voltage difference between the gate and source (here, the first electrode) of the first transistor T1
- K is related to the first transistor T1 itself A constant value of.
- all the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics.
- the thin film transistors are used as an example for description.
- the source and drain of the transistor used here can be symmetrical in structure, so there can be no difference in structure of the source and drain of the transistor.
- one pole is directly described as the first pole and the other pole is the second pole.
- the transistor in the pixel circuit 10 shown in FIG. 3 is described by taking the third transistor T3 and the sixth transistor T6 as N-type transistors, and the other transistors as P-type transistors.
- a cathode of the light emitting element L1 in the pixel circuit 10 is connected to a second voltage terminal VSS to receive a second voltage.
- the cathodes of the light-emitting elements L1 can be electrically connected to the same voltage terminal, that is, a common cathode connection method is adopted.
- At least one embodiment of the present disclosure also provides a display panel including a plurality of pixel units arranged in an array, each of the plurality of pixel units including a pixel circuit provided by any embodiment of the present disclosure.
- FIG. 10 is a schematic block diagram of a display panel according to an embodiment of the present disclosure.
- the display panel 11 is provided in the display device 1 and is electrically connected to the gate driver 12, the timing controller 13, and the data driver 14.
- the display panel 11 includes pixel units P defined in accordance with the intersection of a plurality of scanning lines GL and a plurality of data lines DL; a gate driver 12 for driving a plurality of scanning lines GL; a data driver 14 for driving a plurality of data lines DL;
- the controller 13 is configured to process the image data RGB input from the outside of the display device 1, provide the processed image data RGB to the data driver 14, and output the scan control signal GCS and the data control signal DCS to the gate driver 12 and the data driver 14 to The gate driver 12 and the data driver 14 perform control.
- the display panel 11 includes a plurality of pixel units P, and the pixel units P include the pixel circuit 10 provided in any one of the above embodiments.
- the pixel unit P includes a pixel circuit 10 shown in FIG. 3.
- the display panel 11 further includes a plurality of scan lines GL and a plurality of data lines DL.
- the plurality of scanning lines GL correspond to the data writing circuit 200 in the pixel circuit 10 connected to each row of pixel units to provide a first scanning signal
- the plurality of scanning lines also correspond to the pixel circuits connected to each row of pixel units.
- the compensation circuit 300 and the reset circuit 700 in 10 use the second scan signal as a reset signal.
- the pixel unit P is provided at a crossing region of the scan line GL and the data line DL.
- each pixel unit P is connected to five scan lines GL (providing a first scan signal, a second scan signal, a reset signal, a first light emission control signal, and a second light emission control signal), and one piece of data.
- Line DL a first voltage line for providing a first voltage
- a second voltage line for providing a second voltage
- a reset voltage line for providing a reset voltage.
- the first voltage line or the second voltage line may be replaced with a corresponding plate-shaped common electrode (for example, a common anode or a common cathode).
- each pixel unit P may be connected to only four scan lines GL, that is, the above-mentioned second scan signal And the reset signal is provided by a second scan line GL. It should be noted that the following embodiments are the same and will not be described again.
- the plurality of pixel units P are arranged in multiple rows.
- the compensation circuit 300 and the reset circuit 700 of the pixel circuit of each row of pixel units P are connected to the same scanning line GL, and the data writing circuit of the pixel circuit of each row of pixel units P is connected.
- 200 is connected to another scan line GL to receive a first scan signal.
- the data line DL of each column is connected to the data writing circuit 200 in the pixel circuit 10 of the column to provide a data signal.
- the display panel further includes a plurality of light emission control lines.
- a plurality of pixel units are arranged in multiple rows, a second light emission control circuit of a pixel circuit of an n-th (n is an integer greater than zero) pixel unit, and a first light emission control circuit of a pixel circuit of an n + 1th pixel unit. Connect to the same illuminated control line.
- the first light emission control circuit of the pixel circuit of the first row of pixel units is connected to the same light emission control line
- the second light emission control circuit of the pixel circuit of the first row of pixel units and the first of the pixel circuits of the second row of pixel units The light emission control circuit is connected to the same light emission control line
- the second light emission control circuit of the pixel circuit of the second row of pixel units and the first light emission control circuit of the pixel circuit of the third row of pixel units are connected to the same light emission control line.
- the pixel circuits of adjacent row pixel units can share the same light emission control line. In this way, the layout space of the display panel can be saved, so that the high-resolution display panel can be realized. Development.
- the gate driver 12 supplies a plurality of gate signals to the plurality of scanning lines GL according to the plurality of scanning control signals GCS originating from the timing controller 13.
- the plurality of strobe signals include a first scan signal, a second scan signal, a first light emission control signal, a second light emission control signal, and a reset signal (ie, a second scan signal). These signals are supplied to each pixel unit P through a plurality of scanning lines GL.
- the data driver 14 converts digital image data RGB input from the timing controller 13 into a data signal according to a plurality of data control signals DCS originating from the timing controller 13 using a reference gamma voltage.
- the data driver 14 supplies the converted data signals to the plurality of data lines DL.
- the timing controller 13 processes externally input image data RGB to match the size and resolution of the display panel 11, and then supplies the processed image data to the data driver 14.
- the timing controller 13 generates a plurality of scan control signals GCS and a plurality of data control signals DCS using synchronization signals (such as the dot clock DCLK, the data enable signal DE, the horizontal synchronization signal Hsync, and the vertical synchronization signal Vsync) input from the outside of the display device.
- the timing controller 13 provides the generated scan control signal GCS and data control signal DCS to the gate driver 12 and the data driver 14, respectively, for the control of the gate driver 12 and the data driver 14.
- the data driving appliance 14 may be connected to a plurality of data lines DL to provide a data signal Vdata; at the same time, it may also be connected to a plurality of first voltage lines, a plurality of second voltage lines, and a plurality of reset voltage lines to respectively provide a first Voltage, second voltage, and reset voltage.
- the gate driver 12 and the data driver 14 may be implemented as a semiconductor chip.
- the display device 1 may further include other components, such as a signal decoding circuit, a voltage conversion circuit, and the like. These components may use existing conventional components, for example, and will not be described in detail here.
- the display panel 11 provided by some embodiments of the present disclosure can be applied to any product or component having a display function, such as electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, and the like.
- a display function such as electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, and the like.
- Some embodiments of the present disclosure also provide a driving method that can be used to drive the pixel circuit 10 provided by the embodiments of the present disclosure.
- the driving method includes the following operations:
- the first scanning signal, the second scanning signal, and the data signal are input to turn on the data writing circuit 200, the driving circuit 100, and the compensation circuit 300.
- the data writing circuit 200 writes the data signal to the driving circuit 100
- the compensation circuit 300 stores the data signal, and the compensation circuit 300 compensates the driving circuit 100;
- a first light emitting control signal is input to turn on the first light emitting control circuit 400 and the driving circuit 100, and the first light emitting control circuit 400 applies a driving current to the light emitting element to cause it to emit light.
- the first scan signal and the second scan signal are simultaneously on signals for at least part of the time period.
- the driving method includes the following operations:
- a reset signal, a second scan signal, and a second light-emitting control signal are input to turn on the reset circuit 700, the compensation circuit 300, and the second light-emitting control circuit 600, and a reset voltage is applied to the control terminal 130 of the driving circuit 100, the first The end 110 and the second end 120 and the first end 510 of the light-emitting element 500;
- the first scanning signal, the second scanning signal, and the data signal are input to turn on the data writing circuit 200, the driving circuit 100, and the compensation circuit 300.
- the data writing circuit 200 writes the data signal to the driving circuit 100 ,
- the compensation circuit 300 stores the data signal, and the compensation circuit 300 compensates the driving circuit 100;
- a first light emission control signal is input to turn on the first light emission control circuit 400 and the driving circuit 100, and the first light emission control circuit 400 applies a first voltage to the first terminal 110 of the driving circuit 100;
- a first light emitting control signal and a second light emitting control signal are input to turn on the first light emitting control circuit 400, the second light emitting control circuit 600, and the driving circuit 100, and the second light emitting control circuit 600 applies a driving current to the light emitting element 500 To make it glow.
- the first scanning signal and the second scanning signal are both on signals for at least part of the time period
- the first lighting control signal and the second lighting control signal are both on signals for at least part of the time period
- the driving method may further include a data write holding phase.
- a first scanning signal and a data signal are input to turn on the data writing circuit 200 and the driving circuit 100, and the data writing circuit 200 writes the data signal to the first terminal 110 and the second terminal 120 of the driving circuit 100.
- the driving method provided by some embodiments of the present disclosure can achieve low-frequency driving and improve the resolution of the display panel. At the same time, since the leakage current of the N-type transistor is small, the aging problem of the N-type transistor need not be considered during use.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Control Of El Displays (AREA)
Abstract
Description
Claims (20)
- 一种像素电路,包括:驱动电路、数据写入电路、补偿电路和发光元件;其中,所述驱动电路包括控制端、第一端和第二端,且配置为控制流经所述第一端和所述第二端的用于驱动所述发光元件发光的驱动电流;所述数据写入电路与所述驱动电路的第一端连接,且配置为响应于第一扫描信号将数据信号写入所述驱动电路的第一端;所述补偿电路与所述驱动电路的控制端以及第二端连接且与第一电压端连接,且配置为存储所述数据写入电路写入的所述数据信号并响应于第二扫描信号对所述驱动电路进行补偿;所述发光元件包括第一端和第二端,所述发光元件的第一端配置为接收所述驱动电流,所述发光元件的第二端与第二电压端连接。
- 根据权利要求1所述的像素电路,还包括第一发光控制电路,其中,所述第一发光控制电路与所述驱动电路的第一端以及所述第一电压端连接,且配置为响应于第一发光控制信号将所述第一电压端接收的第一电压施加至所述驱动电路的第一端。
- 根据权利要求2所述的像素电路,还包括第二发光控制电路,其中,所述第二发光控制电路与所述驱动电路的第二端以及所述发光元件的第一端连接,且配置为响应于第二发光控制信号将所述驱动电流施加至所述发光元件。
- 根据权利要求3所述的像素电路,还包括复位电路,其中,所述复位电路与复位电压端以及所述发光元件的第一端连接,且配置为响应于复位信号将所述复位电压端接收的复位电压施加至所述发光元件的第一端;其中,所述复位信号为所述第二扫描信号。
- 根据权利要求1-4任一所述的像素电路,其中,所述驱动电路包括第一晶体管;所述第一晶体管的栅极作为所述驱动电路的控制端,所述第一晶体管 的第一极作为所述驱动电路的第一端,所述第一晶体管的第二极作为所述驱动电路的第二端。
- 根据权利要求1-5任一所述的像素电路,其中,所述数据写入电路包括第二晶体管;所述第二晶体管的栅极和第一扫描线连接以接收所述第一扫描信号,所述第二晶体管的第一极和数据线连接以接收所述数据信号,所述第二晶体管的第二极和所述驱动电路的第一端连接。
- 根据权利要求1-6任一所述的像素电路,其中,所述补偿电路包括第三晶体管和电容;所述第三晶体管的栅极和第二扫描线连接以接收所述第二扫描信号,所述第三晶体管的第一极和所述驱动电路的第二端连接,所述第三晶体管的第二极和所述驱动电路的控制端连接;所述电容的第一极和所述驱动电路的控制端连接,所述电容的第二极和所述第一电压端连接。
- 根据权利要求2-4任一所述的像素电路,其中,所述第一发光控制电路包括第四晶体管;所述第四晶体管的栅极和第一发光控制线连接以接收所述第一发光控制信号,所述第四晶体管的第一极和所述第一电压端连接以接收所述第一电压,所述第四晶体管的第二极和所述驱动电路的第一端连接。
- 根据权利要求3或4所述的像素电路,其中,所述第二发光控制电路包括第五晶体管;所述第五晶体管的栅极和第二发光控制线连接以接收所述第二发光控制信号,所述第五晶体管的第一极和所述驱动电路的第二端连接,所述第五晶体管的第二极和所述发光元件的第一端连接。
- 根据权利要求4所述的像素电路,其中,所述复位电路包括第六晶体管;所述第六晶体管的栅极和第二扫描线连接以接收所述第二扫描信号作为所述复位信号,所述第六晶体管的第一极和所述复位电压端连接以接收所述复位电压,所述第六晶体管的第二极和所述发光元件的第一端连接。
- 根据权利要求10所述的像素电路,其中,所述驱动电路包括第一晶体管,所述第一晶体管的栅极作为所述驱动 电路的控制端,所述第一晶体管的第一极作为所述驱动电路的第一端,所述第一晶体管的第二极作为所述驱动电路的第二端;所述数据写入电路包括第二晶体管,所述第二晶体管的栅极和第一扫描线连接以接收所述第一扫描信号,所述第二晶体管的第一极和数据线连接以接收所述数据信号,所述第二晶体管的第二极和所述驱动电路的第一端连接;所述补偿电路包括第三晶体管和电容,所述第三晶体管的栅极和第二扫描线连接以接收所述第二扫描信号,所述第三晶体管的第一极和所述驱动电路的第二端连接,所述第三晶体管的第二极和所述驱动电路的控制端连接;所述电容的第一极和所述驱动电路的控制端连接,所述电容的第二极和所述第一电压端连接;所述第一发光控制电路包括第四晶体管,所述第四晶体管的栅极和第一发光控制线连接以接收所述第一发光控制信号,所述第四晶体管的第一极和所述第一电压端连接以接收所述第一电压,所述第四晶体管的第二极和所述驱动电路的第一端连接;所述第二发光控制电路包括第五晶体管,所述第五晶体管的栅极和第二发光控制线连接以接收所述第二发光控制信号,所述第五晶体管的第一极和所述驱动电路的第二端连接,所述第五晶体管的第二极和所述发光元件的第一端连接。
- 根据权利要求11所述的像素电路,其中,所述第三晶体管和所述第六晶体管为N型晶体管,所述第一晶体管、所述第二晶体管、所述第四晶体管和所述第五晶体管为P型晶体管。
- 根据权利要求1-12任一所述的像素电路,其中,所述补偿电路和所述驱动电路包括的晶体管类型不同。
- 根据权利要求13所述的像素电路,其中,所述补偿电路包括N型晶体管,所述驱动电路包括P型晶体管。
- 根据权利要求4所述的像素电路,其中,所述补偿电路和所述复位电路均包括N型晶体管,所述驱动电路、所述数据写入电路、所述第一发光控制电路以及所述第二发光控制电路均包括P型晶体管。
- 一种显示面板,包括阵列布置的多个像素单元,其中,所述多个像素单元的每个包括如权利要求1-15任一所述的像素电路。
- 根据权利要求16所述的显示面板,还包括多条发光控制线,其 中,所述多个像素单元排列为多行,第n行像素单元的像素电路的第二发光控制电路和第n+1行像素单元的像素电路的第一发光控制电路连接到同一条发光控制线,n为大于零的整数。
- 一种如权利要求2所述的像素电路的驱动方法,包括:数据写入及补偿阶段和发光阶段;其中,在所述数据写入及补偿阶段,输入所述第一扫描信号、所述第二扫描信号和所述数据信号以使得所述数据写入电路、所述驱动电路和所述补偿电路导通,所述数据写入电路将所述数据信号写入所述驱动电路,所述补偿电路存储所述数据信号,且所述补偿电路对所述驱动电路进行补偿;在所述发光阶段,输入所述第一发光控制信号以使得所述第一发光控制电路和所述驱动电路导通,所述第一发光控制电路将所述驱动电流施加至所述发光元件以使其发光;其中,所述第一扫描信号和所述第二扫描信号至少部分时间段内同时为开启信号。
- 一种权利要求4所述的像素电路的驱动方法,包括:初始化阶段、数据写入及补偿阶段、预发光阶段和发光阶段;其中,在所述初始化阶段,输入所述复位信号、所述第二扫描信号和所述第二发光控制信号以使得所述复位电路、所述补偿电路和所述第二发光控制电路导通,将所述复位电压施加至所述驱动电路的控制端、第一端和第二端以及所述发光元件的第一端;在所述数据写入及补偿阶段,输入所述第一扫描信号、所述第二扫描信号和所述数据信号以使得所述数据写入电路、所述驱动电路和所述补偿电路导通,所述数据写入电路将所述数据信号写入所述驱动电路,所述补偿电路存储所述数据信号,且所述补偿电路对所述驱动电路进行补偿;在所述预发光阶段,输入所述第一发光控制信号以使得所述第一发光控制电路和所述驱动电路导通,所述第一发光控制电路将所述第一电压施加至所述驱动电路的第一端;在所述发光阶段,输入所述第一发光控制信号和所述第二发光控制信号以使得所述第一发光控制电路、所述第二发光控制电路和所述驱动电路导通,所述第二发光控制电路将所述驱动电流施加至所述发光元件以使其 发光;其中,所述第一扫描信号和所述第二扫描信号至少部分时间段内同时为开启信号,所述第一发光控制信号和所述第二发光控制信号至少部分时间段内同时为开启信号。
- 根据权利要求19所述的像素电路的驱动方法,还包括:数据写入保持阶段;其中,在所述数据写入保持阶段,输入所述第一扫描信号以使得所述数据写入电路导通,输入所述第二扫描信号以使得所述补偿电路截止,以保持所述驱动电路的控制端的电压。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/492,676 US11373582B2 (en) | 2018-06-08 | 2019-02-15 | Pixel circuit and driving method thereof, display panel |
US17/824,046 US11631369B2 (en) | 2018-06-08 | 2022-05-25 | Pixel circuit and driving method thereof, display panel |
US18/119,915 US11837162B2 (en) | 2018-06-08 | 2023-03-10 | Pixel circuit and driving method thereof, display panel |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201810588684.XA CN110176213B (zh) | 2018-06-08 | 2018-06-08 | 像素电路及其驱动方法、显示面板 |
CN201810588684.X | 2018-06-08 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/492,676 A-371-Of-International US11373582B2 (en) | 2018-06-08 | 2019-02-15 | Pixel circuit and driving method thereof, display panel |
US17/824,046 Continuation US11631369B2 (en) | 2018-06-08 | 2022-05-25 | Pixel circuit and driving method thereof, display panel |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2019233120A1 true WO2019233120A1 (zh) | 2019-12-12 |
Family
ID=67689234
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2019/075239 WO2019233120A1 (zh) | 2018-06-08 | 2019-02-15 | 像素电路及其驱动方法、显示面板 |
Country Status (3)
Country | Link |
---|---|
US (3) | US11373582B2 (zh) |
CN (1) | CN110176213B (zh) |
WO (1) | WO2019233120A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2021033265A (ja) * | 2019-08-15 | 2021-03-01 | 三星ディスプレイ株式會社Samsung Display Co.,Ltd. | 電流感知システムおよび方法 |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI713006B (zh) * | 2019-09-24 | 2020-12-11 | 友達光電股份有限公司 | 畫素電路 |
CN110634432B (zh) * | 2019-10-25 | 2023-05-12 | 京东方科技集团股份有限公司 | Oled像素电路、驱动方法、老化检测方法和显示面板 |
KR20210126177A (ko) | 2020-04-09 | 2021-10-20 | 삼성디스플레이 주식회사 | 유기 발광 표시 장치의 화소, 및 유기 발광 표시 장치 |
CN117198202A (zh) * | 2020-10-15 | 2023-12-08 | 厦门天马微电子有限公司 | 显示面板及其驱动方法以及显示装置 |
CN112289266B (zh) * | 2020-10-30 | 2021-11-16 | 维沃移动通信有限公司 | 像素补偿电路、显示装置和像素补偿方法 |
CN112435630A (zh) * | 2020-11-25 | 2021-03-02 | 京东方科技集团股份有限公司 | 一种像素驱动电路、驱动方法及显示面板 |
CN114822387B (zh) * | 2021-01-28 | 2023-11-14 | 成都辰显光电有限公司 | 像素电路和显示面板 |
CN112967684B (zh) * | 2021-02-08 | 2023-04-21 | 成都京东方光电科技有限公司 | 像素电路及其驱动方法、显示装置 |
CN115699145A (zh) * | 2021-02-10 | 2023-02-03 | 京东方科技集团股份有限公司 | 像素电路及其驱动方法、显示装置 |
CN112992071A (zh) * | 2021-04-22 | 2021-06-18 | 京东方科技集团股份有限公司 | 像素电路及其驱动方法、显示装置 |
US11935470B2 (en) | 2021-04-30 | 2024-03-19 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Pixel circuit and driving method thereof, and display device |
CN113892132B (zh) * | 2021-06-23 | 2022-08-09 | 京东方科技集团股份有限公司 | 像素电路、驱动方法和显示装置 |
CN114514573B (zh) * | 2021-07-30 | 2022-08-09 | 京东方科技集团股份有限公司 | 像素电路、驱动方法和显示装置 |
CN113707086B (zh) * | 2021-08-26 | 2023-12-19 | 京东方科技集团股份有限公司 | 像素补偿电路及其驱动方法、显示面板和显示装置 |
CN113763880B (zh) * | 2021-09-18 | 2023-03-14 | 广州国显科技有限公司 | 像素电路、像素电路的驱动方法及显示装置 |
CN113823222B (zh) * | 2021-09-26 | 2023-08-18 | 合肥维信诺科技有限公司 | 显示面板的驱动方法、驱动装置及显示装置 |
CN114093318B (zh) * | 2021-11-18 | 2023-06-20 | 广州国显科技有限公司 | 像素电路、像素电路的控制方法及显示装置 |
CN114067720A (zh) * | 2021-12-03 | 2022-02-18 | 武汉华星光电半导体显示技术有限公司 | 像素电路及显示装置 |
CN114446241B (zh) * | 2022-02-28 | 2023-07-21 | 京东方科技集团股份有限公司 | 像素电路及其驱动方法、显示基板 |
CN114333702B (zh) | 2022-03-03 | 2022-05-31 | 惠科股份有限公司 | 显示面板的驱动电路、显示面板 |
CN114758612A (zh) * | 2022-04-18 | 2022-07-15 | 深圳市华星光电半导体显示技术有限公司 | 像素补偿电路、显示面板及像素补偿方法 |
CN115035854A (zh) * | 2022-06-24 | 2022-09-09 | 惠科股份有限公司 | 像素驱动电路、驱动方法和显示装置 |
WO2024065614A1 (zh) * | 2022-09-30 | 2024-04-04 | 京东方科技集团股份有限公司 | 像素驱动电路、驱动方法及其显示装置 |
CN115938307B (zh) * | 2022-12-28 | 2024-01-09 | 惠科股份有限公司 | 像素电路、显示面板及显示装置 |
CN116564233B (zh) * | 2023-04-27 | 2024-06-18 | 惠科股份有限公司 | 像素驱动电路及其驱动方法、显示装置 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20050116206A (ko) * | 2004-06-07 | 2005-12-12 | 삼성에스디아이 주식회사 | 발광 표시장치 |
CN104851386A (zh) * | 2014-02-14 | 2015-08-19 | 三星显示有限公司 | 驱动电路及包括该驱动电路的显示装置 |
CN105575327A (zh) * | 2016-03-21 | 2016-05-11 | 京东方科技集团股份有限公司 | 一种像素电路、其驱动方法及有机电致发光显示面板 |
CN105679236A (zh) * | 2016-04-06 | 2016-06-15 | 京东方科技集团股份有限公司 | 像素电路及其驱动方法、阵列基板、显示面板和显示装置 |
CN106531075A (zh) * | 2017-01-10 | 2017-03-22 | 上海天马有机发光显示技术有限公司 | 有机发光像素驱动电路、驱动方法以及有机发光显示面板 |
CN107564468A (zh) * | 2016-07-01 | 2018-01-09 | 三星显示有限公司 | 像素、级电路和具有该像素和级电路的有机发光显示装置 |
CN107945743A (zh) * | 2018-01-04 | 2018-04-20 | 京东方科技集团股份有限公司 | 一种像素电路、其驱动方法及显示装置 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101324756B1 (ko) * | 2005-10-18 | 2013-11-05 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 표시장치 및 그의 구동방법 |
JP2008151963A (ja) * | 2006-12-15 | 2008-07-03 | Semiconductor Energy Lab Co Ltd | 半導体装置及び半導体装置の駆動方法 |
CN104575367B (zh) * | 2013-10-15 | 2017-10-13 | 昆山工研院新型平板显示技术中心有限公司 | 一种像素电路及其驱动方法和应用 |
US9490276B2 (en) * | 2014-02-25 | 2016-11-08 | Lg Display Co., Ltd. | Display backplane and method of fabricating the same |
KR102455618B1 (ko) * | 2015-02-05 | 2022-10-17 | 삼성디스플레이 주식회사 | 유기 발광 표시 장치 |
CN106157880A (zh) * | 2015-04-23 | 2016-11-23 | 上海和辉光电有限公司 | Oled像素补偿电路 |
CN104851392B (zh) * | 2015-06-03 | 2018-06-05 | 京东方科技集团股份有限公司 | 一种像素驱动电路及方法、阵列基板和显示装置 |
CN105895022A (zh) * | 2016-04-13 | 2016-08-24 | 信利(惠州)智能显示有限公司 | 一种amoled像素驱动电路及像素驱动方法 |
KR20180061524A (ko) * | 2016-11-29 | 2018-06-08 | 엘지디스플레이 주식회사 | 표시패널과 이를 이용한 전계 발광 표시장치 |
CN109215581B (zh) * | 2017-06-30 | 2020-05-29 | 京东方科技集团股份有限公司 | 一种显示面板的补偿方法、补偿装置及显示装置 |
CN109509427A (zh) | 2017-09-15 | 2019-03-22 | 京东方科技集团股份有限公司 | 像素电路及其驱动方法、显示装置 |
US11069282B2 (en) * | 2019-08-15 | 2021-07-20 | Samsung Display Co., Ltd. | Correlated double sampling pixel sensing front end |
CN112767883A (zh) * | 2019-11-01 | 2021-05-07 | 京东方科技集团股份有限公司 | 像素驱动电路及其驱动方法、显示装置 |
CN110942743B (zh) * | 2019-12-26 | 2021-04-13 | 云谷(固安)科技有限公司 | 像素电路的驱动方法、显示面板和显示装置 |
KR20210149976A (ko) * | 2020-06-02 | 2021-12-10 | 삼성디스플레이 주식회사 | 표시 장치 |
CN112017593A (zh) * | 2020-09-28 | 2020-12-01 | 京东方科技集团股份有限公司 | 一种显示基板及其制作方法、显示装置 |
-
2018
- 2018-06-08 CN CN201810588684.XA patent/CN110176213B/zh active Active
-
2019
- 2019-02-15 US US16/492,676 patent/US11373582B2/en active Active
- 2019-02-15 WO PCT/CN2019/075239 patent/WO2019233120A1/zh active Application Filing
-
2022
- 2022-05-25 US US17/824,046 patent/US11631369B2/en active Active
-
2023
- 2023-03-10 US US18/119,915 patent/US11837162B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20050116206A (ko) * | 2004-06-07 | 2005-12-12 | 삼성에스디아이 주식회사 | 발광 표시장치 |
CN104851386A (zh) * | 2014-02-14 | 2015-08-19 | 三星显示有限公司 | 驱动电路及包括该驱动电路的显示装置 |
CN105575327A (zh) * | 2016-03-21 | 2016-05-11 | 京东方科技集团股份有限公司 | 一种像素电路、其驱动方法及有机电致发光显示面板 |
CN105679236A (zh) * | 2016-04-06 | 2016-06-15 | 京东方科技集团股份有限公司 | 像素电路及其驱动方法、阵列基板、显示面板和显示装置 |
CN107564468A (zh) * | 2016-07-01 | 2018-01-09 | 三星显示有限公司 | 像素、级电路和具有该像素和级电路的有机发光显示装置 |
CN106531075A (zh) * | 2017-01-10 | 2017-03-22 | 上海天马有机发光显示技术有限公司 | 有机发光像素驱动电路、驱动方法以及有机发光显示面板 |
CN107945743A (zh) * | 2018-01-04 | 2018-04-20 | 京东方科技集团股份有限公司 | 一种像素电路、其驱动方法及显示装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2021033265A (ja) * | 2019-08-15 | 2021-03-01 | 三星ディスプレイ株式會社Samsung Display Co.,Ltd. | 電流感知システムおよび方法 |
Also Published As
Publication number | Publication date |
---|---|
US20230215348A1 (en) | 2023-07-06 |
US11631369B2 (en) | 2023-04-18 |
CN110176213A (zh) | 2019-08-27 |
US11373582B2 (en) | 2022-06-28 |
US20220284851A1 (en) | 2022-09-08 |
US20210366363A1 (en) | 2021-11-25 |
US11837162B2 (en) | 2023-12-05 |
CN110176213B (zh) | 2023-09-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2019233120A1 (zh) | 像素电路及其驱动方法、显示面板 | |
US11881164B2 (en) | Pixel circuit and driving method thereof, and display panel | |
CN113838421B (zh) | 像素电路及其驱动方法、显示面板 | |
CN110268465B (zh) | 像素电路、显示面板及像素电路的驱动方法 | |
CN109523956B (zh) | 像素电路及其驱动方法、显示装置 | |
US10978002B2 (en) | Pixel circuit and driving method thereof, and display panel | |
CN110021273B (zh) | 像素电路及其驱动方法、显示面板 | |
CN109872692B (zh) | 像素电路及其驱动方法、显示装置 | |
WO2020233491A1 (zh) | 像素电路及其驱动方法、阵列基板及显示装置 | |
US11620942B2 (en) | Pixel circuit, driving method thereof and display device | |
WO2019062579A1 (zh) | 像素电路及其驱动方法、显示装置 | |
CN113838419B (zh) | 像素电路及其驱动方法、显示面板 | |
CN108376534B (zh) | 像素电路及其驱动方法、显示面板 | |
GB2620507A (en) | Pixel circuit and driving method therefor and display panel | |
US11527199B2 (en) | Pixel circuit including discharge control circuit and storage control circuit and method for driving pixel circuit, display panel and electronic device | |
WO2024041217A1 (zh) | 像素电路及其驱动方法、显示面板、显示装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 19814928 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 19814928 Country of ref document: EP Kind code of ref document: A1 |
|
32PN | Ep: public notification in the ep bulletin as address of the adressee cannot be established |
Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 12.05.2021) |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 19814928 Country of ref document: EP Kind code of ref document: A1 |