WO2024065614A1 - 像素驱动电路、驱动方法及其显示装置 - Google Patents

像素驱动电路、驱动方法及其显示装置 Download PDF

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Publication number
WO2024065614A1
WO2024065614A1 PCT/CN2022/123087 CN2022123087W WO2024065614A1 WO 2024065614 A1 WO2024065614 A1 WO 2024065614A1 CN 2022123087 W CN2022123087 W CN 2022123087W WO 2024065614 A1 WO2024065614 A1 WO 2024065614A1
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Prior art keywords
transistor
signal terminal
electrode
coupled
signal
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PCT/CN2022/123087
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English (en)
French (fr)
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曹丹
高文辉
郭永林
杨慧娟
张跳梅
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to PCT/CN2022/123087 priority Critical patent/WO2024065614A1/zh
Publication of WO2024065614A1 publication Critical patent/WO2024065614A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel driving circuit, a driving method and a display device thereof.
  • Light-emitting devices such as Organic Light Emitting Diode (OLED), Quantum Dot Light Emitting Diode (QLED), Micro Light Emitting Diode (Micro LED), and Mini Light Emitting Diode (Mini LED) have the advantages of self-luminescence and low energy consumption, and are one of the hot spots in the current research field of display device applications.
  • OLED Organic Light Emitting Diode
  • QLED Quantum Dot Light Emitting Diode
  • Micro LED Micro Light Emitting Diode
  • Mini LED Mini Light Emitting Diode
  • a driving transistor configured to generate a current for driving the light emitting device to emit light according to the data voltage
  • a first control circuit configured to conduct the first electrode of the driving transistor to the first node in response to a signal at the first scanning signal terminal;
  • a second control circuit configured to respond to signals at the second scanning signal terminal and the third scanning signal terminal, and to form a current path from the first node to the first initialization signal terminal when the first control circuit conducts the first electrode of the driving transistor to the first node, so that the threshold voltage of the driving transistor is input to the first node;
  • a data writing circuit configured to input the data voltage of the data signal terminal to the first node in response to a signal of the fourth scanning signal terminal, so that the voltage of the first node changes from V1-Vth to Vda;
  • a third control circuit configured to provide a signal from a second initialization signal terminal to the gate electrode of the driving transistor in response to a signal from a first scanning signal terminal, provide a signal from a third initialization signal terminal to the first electrode of the driving transistor in response to a signal from a fifth scanning signal terminal, and provide a signal from a first power supply terminal to the first electrode of the driving transistor in response to a signal from a light emitting control signal terminal;
  • a first storage circuit configured to keep a voltage difference between the first node and the first power supply terminal stable
  • the second storage circuit is configured to keep the voltage difference between the first node and the gate of the driving transistor stable, and when the voltage of the first node changes from V1-Vth to Vda, the voltage of the gate of the driving transistor changes from V1 to Vda+Vth;
  • V1 represents the voltage value of the second initialization signal at the second initial voltage signal terminal
  • Vth represents the threshold voltage of the driving transistor
  • Vda represents the data voltage loaded at the data signal terminal.
  • the second electrode of the driving transistor is coupled to the light emitting device through the second control circuit
  • the second control circuit is configured to connect the second electrode of the driving transistor to the light emitting device in response to the signal of the third scan signal terminal, and to provide the signal of the first initialization signal terminal to the light emitting device in response to the signal of the second scan signal terminal.
  • the second control circuit includes a first transistor and a second transistor
  • the gate of the first transistor is coupled to the third scanning signal terminal, the first electrode of the first transistor is coupled to the light emitting device, and the second electrode of the first transistor is coupled to the second electrode of the driving transistor;
  • a gate of the second transistor is coupled to the second scan signal terminal, a first electrode of the second transistor is coupled to the light emitting device, and a second electrode of the second transistor is coupled to the first initialization signal terminal.
  • the second electrode of the driving transistor is coupled to the light emitting device, and the second control circuit is coupled to the light emitting device;
  • the second control circuit is configured to provide the signal of the first initialization signal terminal to the second electrode of the driving transistor in response to the common control of the signals of the second scanning signal terminal and the third scanning signal terminal.
  • the second control circuit includes a first transistor and a second transistor
  • the gate of the first transistor is coupled to the third scanning signal terminal, the first electrode of the first transistor is coupled to the second electrode of the driving transistor, and the second electrode of the first transistor is coupled to the first electrode of the second transistor;
  • a gate of the second transistor is coupled to the second scanning signal terminal, and a second electrode of the second transistor is coupled to the first initialization signal terminal.
  • the first control circuit includes a third transistor
  • a gate of the third transistor is coupled to the first scan signal terminal, a first electrode of the third transistor is coupled to the first electrode of the driving transistor, and a second electrode of the third transistor is coupled to the first node.
  • the data writing circuit includes a fourth transistor
  • a gate of the fourth transistor is coupled to the fourth scan signal terminal, a first electrode of the fourth transistor is coupled to the data signal terminal, and a second electrode of the fourth transistor is coupled to the first node.
  • the third control circuit includes a fifth transistor, a sixth transistor, and a seventh transistor;
  • the gate of the fifth transistor is coupled to the first scanning signal terminal, the first electrode of the fifth transistor is coupled to the gate of the driving transistor, and the second electrode of the fifth transistor is coupled to the second initial voltage signal terminal;
  • a gate of the sixth transistor is coupled to the fifth scanning signal terminal, a first electrode of the sixth transistor is coupled to the first electrode of the driving transistor, and a second electrode of the sixth transistor is coupled to the third initial voltage signal terminal.
  • a gate of the seventh transistor is coupled to the light emitting control signal terminal, a first electrode of the seventh transistor is coupled to a first electrode of the driving transistor, and a second electrode of the seventh transistor is coupled to the first power supply terminal.
  • the first storage subcircuit includes a first capacitor, a first electrode of the first capacitor is coupled to the first power supply terminal, and a second electrode of the first capacitor is coupled to the first node;
  • the second storage sub-circuit includes: a second capacitor, a first electrode of the second capacitor is coupled to the first node, and a second electrode of the second capacitor is coupled to the gate of the driving transistor.
  • the third scan signal terminal and the fifth scan signal terminal are the same signal terminal.
  • a phase of the signal at the third scanning signal end is opposite to a phase of the signal at the fifth scanning signal end.
  • the first scan signal terminal and the second scan signal terminal are the same signal terminal.
  • the display device provided by the embodiment of the present disclosure includes the above-mentioned pixel driving circuit.
  • the first control circuit conducts the first electrode of the driving transistor with the first node in response to the signal of the first scanning signal terminal;
  • the second control circuit forms a current path from the first node to the first initialization signal terminal in response to the signal of the second scanning signal terminal and the third scanning signal terminal;
  • the third control circuit provides the signal of the second initialization signal terminal to the gate of the driving transistor in response to the signal of the first scanning signal terminal;
  • the first control circuit conducts the first electrode of the driving transistor with the first node in response to the signal of the first scanning signal terminal;
  • the second control circuit forms a current path from the first node to the first initialization signal terminal in response to the signal of the second scanning signal terminal and the third scanning signal terminal, so that the threshold voltage of the driving transistor is input to the first node;
  • the third control circuit provides the signal of the second initialization signal terminal to the gate of the driving transistor in response to the signal of the first scanning signal terminal;
  • the data writing circuit responds to the signal of the fourth scanning signal terminal, inputs the data voltage of the data signal terminal to the first node, so that the voltage of the first node changes from V1-Vth to Vda; due to the action of the second storage circuit, the voltage of the gate of the driving transistor changes from V1 to Vda+Vth; V1 represents the voltage value of the second initialization signal of the second initial voltage signal terminal, Vth represents the threshold voltage of the driving transistor, and Vda represents the data voltage loaded on the data signal terminal;
  • the third control circuit responds to the signal of the light-emitting control signal terminal to provide the signal of the first power supply terminal to the first electrode of the driving transistor; the second control circuit responds to the signal of the third scanning signal terminal to turn on the second electrode of the driving transistor and the light-emitting device.
  • FIG1 is a schematic diagram of some structures of a pixel driving circuit provided by an embodiment of the present disclosure.
  • FIG2 is another schematic diagram of the structure of the pixel driving circuit provided by the embodiment of the present disclosure.
  • FIG3 is a flow chart of a driving method of a pixel driving circuit provided by an embodiment of the present disclosure
  • FIG4 is a timing diagram of some signals provided by an embodiment of the present disclosure.
  • FIG5 is a schematic diagram of some other structures of the pixel driving circuit provided by the embodiment of the present disclosure.
  • FIG6 is another signal timing diagram provided by an embodiment of the present disclosure.
  • FIG7 is a schematic diagram of some other structures of the pixel driving circuit provided by the embodiment of the present disclosure.
  • FIG8 is a schematic diagram of some other structures of the pixel driving circuit provided by the embodiment of the present disclosure.
  • FIG9 is a schematic diagram of some other structures of the pixel driving circuit provided by the embodiment of the present disclosure.
  • FIG10 is a timing diagram of some further signals provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of some further structures of the pixel driving circuit provided in the embodiment of the present disclosure.
  • the display device includes: a display panel, wherein the display area of the display panel includes a plurality of pixel units arranged in an array, and the pixel unit includes a plurality of sub-pixels.
  • each pixel unit includes a plurality of sub-pixels.
  • the pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that a color display can be achieved by mixing red, green, and blue.
  • the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that a color display can be achieved by mixing red, green, blue, and white.
  • the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here.
  • each sub-pixel includes a pixel driving circuit
  • the pixel driving circuit includes a driving transistor and a light-emitting device to control the light-emitting device to emit light, so that the display panel can realize the function of displaying a picture.
  • An embodiment of the present disclosure provides a pixel driving circuit, as shown in FIG1 , including: a light emitting device L, a driving transistor M0 , a first control circuit 10 , a second control circuit 20 , a data writing circuit 30 , a third control circuit 40 , a first storage circuit 50 , and a second storage circuit 60 .
  • the driving transistor M0 is configured to generate a current for driving the light emitting device L to emit light according to the data voltage.
  • the first control circuit 10 is configured to conduct the first electrode of the driving transistor M0 with the first node in response to the signal of the first scanning signal terminal SS1;
  • the second control circuit 20 is configured to respond to the signals of the second scanning signal terminal SS2 and the third scanning signal terminal SS3, and when the first control circuit 10 conducts the first electrode of the driving transistor M0 with the first node N1, a current path from the first node N1 to the first initialization signal terminal Vinit1 is formed, so that the threshold voltage Vth of the driving transistor M0 is input to the first node N1;
  • the data writing circuit 30 is configured to respond to the signal of the fourth scanning signal terminal SS4, input the data voltage Vda of the data signal terminal DA to the first node N1, so that the voltage of the first node N1 changes from V1-Vth to Vda;
  • the third control circuit 40 is configured to respond to the signal
  • the gate of the driving transistor M0 is provided to the first electrode of the driving transistor M0, and in response to the signal of the fifth scanning signal terminal SS5, the signal of the third initialization signal terminal Vinit3 is provided to the first electrode of the driving transistor M0, and in response to the signal of the light emitting control signal terminal EM, the signal of the first power supply terminal VDD is provided to the first electrode of the driving transistor M0;
  • the first storage circuit 50 is configured to keep the voltage difference between the first node N1 and the first power supply terminal VDD stable;
  • the second storage circuit 60 is configured to keep the voltage difference between the first node N1 and the gate of the driving transistor M0 stable, and when the voltage of the first node N1 changes from V1-Vth to Vda, the voltage of the gate of the driving transistor M0 changes from V1 to Vda+Vth;
  • V1 represents the voltage value of the second initialization signal of the second initial voltage signal terminal Vinit2
  • Vth represents the threshold voltage of the driving transistor M0
  • Vda represents
  • the time period for initializing the driving transistor and the time period for threshold compensation of the threshold voltage Vth of the driving transistor do not overlap, so that part of the current path in the pixel driving circuit can be blocked, thereby reducing the current in the circuit, reducing the risk of circuit short circuit and burning, and thus improving the performance of the pixel driving circuit.
  • the driving transistor M0 can be set as a P-type transistor; wherein the first electrode of the driving transistor M0 can be its source, the second electrode of the driving transistor M0 can be its drain, and when the driving transistor M0 is in a saturated state, the current flows from the source of the driving transistor M0 to its drain.
  • the driving transistor M0 can also be set as an N-type transistor, which is not limited here.
  • the first electrode of the light emitting device L can be coupled to the second electrode of the driving transistor M0 through the second control circuit 20.
  • the second electrode of the light emitting device L can be coupled to the second power supply terminal VSS.
  • the first electrode of the light emitting device L can be its anode, and the second electrode can be its cathode.
  • the light emitting device L can be an organic light emitting diode.
  • the light emitting device L can include: at least one of a micro light emitting diode (Micro Light Emitting Diode, Micro LED), an organic light emitting diode (Organic Light Emitting Diode, OLED) and a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED).
  • the light emitting device L can include an anode, a light emitting layer, and a cathode that are stacked.
  • the light emitting layer can also include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.
  • the specific structure of the light emitting device L can be designed and determined according to the actual application environment, and is not limited here.
  • the second electrode of the driving transistor M0 is coupled to the light emitting device L through the second control circuit 20 ;
  • the second control circuit 20 is configured to connect the second electrode of the driving transistor M0 to the light emitting device L in response to the signal of the third scan signal terminal SS3, and to provide the signal of the first initialization signal terminal Vinit1 to the light emitting device L in response to the signal of the second scan signal terminal SS2.
  • the second control circuit 20 includes a first transistor M1 and a second transistor M2; the gate of the first transistor M1 is coupled to the third scan signal terminal SS3, the first electrode of the first transistor M1 is coupled to the light emitting device L, and the second electrode of the first transistor M1 is coupled to the second electrode of the driving transistor M0.
  • the gate of the second transistor M2 is coupled to the second scan signal terminal SS2, the first electrode of the second transistor M2 is coupled to the light emitting device L, and the second electrode of the second transistor M2 is coupled to the first initialization signal terminal Vinit1.
  • the first transistor M1 can be turned on under the control of the effective level of the third scan signal transmitted by the third scan signal terminal SS3, and can be turned off under the control of the ineffective level of the third scan signal.
  • the first transistor M1 is set as a P-type transistor, then the effective level of the third scan signal is a low level, and the ineffective level of the third scan signal is a high level.
  • the first transistor M1 is set as an N-type transistor, then the effective level of the third scan signal is a high level, and the ineffective level of the third scan signal is a low level.
  • the second transistor M2 can be turned on under the control of the effective level of the second scan signal transmitted by the second scan signal terminal SS2, and can be turned off under the control of the ineffective level of the second scan signal.
  • the second transistor M2 is set as an N-type transistor, then the effective level of the second scan signal is a high level, and the ineffective level of the second scan signal is a low level.
  • the second transistor M2 is set as a P-type transistor, then the effective level of the second scan signal is a low level, and the ineffective level of the second scan signal is a high level.
  • the first control circuit 10 includes a third transistor M3; the gate of the third transistor M3 is coupled to the first scan signal terminal SS1, the first electrode of the third transistor M3 is coupled to the first electrode of the driving transistor M0, and the second electrode of the third transistor M3 is coupled to the first node N1.
  • the third transistor M3 can be turned on under the control of the effective level of the first scan signal transmitted by the first scan signal terminal SS1, and can be turned off under the control of the ineffective level of the first scan signal.
  • the third transistor M3 is set as an N-type transistor, then the effective level of the first scan signal is a high level, and the ineffective level of the first scan signal is a low level.
  • the third transistor M3 is set as a P-type transistor, then the effective level of the first scan signal is a low level, and the ineffective level of the first scan signal is a high level.
  • the data writing circuit 30 includes a fourth transistor M4; the gate of the fourth transistor M4 is coupled to the fourth scan signal terminal SS4, the first electrode of the fourth transistor M4 is coupled to the data signal terminal DA, and the second electrode of the fourth transistor M4 is coupled to the first node N1.
  • the fourth transistor M4 can be turned on under the control of the effective level of the fourth scan signal transmitted by the fourth scan signal terminal SS4, and can be turned off under the control of the ineffective level of the fourth scan signal.
  • the fourth transistor M4 is set as an N-type transistor, then the effective level of the fourth scan signal is a high level, and the ineffective level of the fourth scan signal is a low level.
  • the fourth transistor M4 is set as a P-type transistor, then the effective level of the fourth scan signal is a low level, and the ineffective level of the fourth scan signal is a high level.
  • the third control circuit 40 includes a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7; the gate of the fifth transistor M5 is coupled to the first scan signal terminal SS1, the first electrode of the fifth transistor M5 is coupled to the gate of the driving transistor M0, and the second electrode of the fifth transistor M5 is coupled to the second initial voltage signal terminal Vinit2; the gate of the sixth transistor M6 is coupled to the fifth scan signal terminal SS5, the first electrode of the sixth transistor M6 is coupled to the first electrode of the driving transistor M0, and the second electrode of the sixth transistor M6 is coupled to the third initial voltage signal terminal Vinit3.
  • the gate of the seventh transistor M7 is coupled to the light emitting control signal terminal EM, the first electrode of the seventh transistor M7 is coupled to the first electrode of the driving transistor M0, and the second electrode of the seventh transistor M7 is coupled to the first power supply terminal VDD.
  • the fifth transistor M5 can be turned on under the control of the effective level of the first scan signal transmitted by the first scan signal terminal SS1, and can be turned off under the control of the ineffective level of the first scan signal.
  • the fifth transistor M5 is set as an N-type transistor, then the effective level of the first scan signal is a high level, and the ineffective level of the first scan signal is a low level.
  • the fifth transistor M5 is set as a P-type transistor, then the effective level of the first scan signal is a low level, and the ineffective level of the first scan signal is a high level.
  • the sixth transistor M6 can be turned on under the control of the effective level of the fifth scan signal transmitted by the fifth scan signal terminal SS5, and can be turned off under the control of the ineffective level of the fifth scan signal.
  • the sixth transistor M6 is set as an N-type transistor, then the effective level of the fifth scan signal is a high level, and the ineffective level of the fifth scan signal is a low level.
  • the sixth transistor M6 is set as a P-type transistor, then the effective level of the fifth scan signal is a low level, and the ineffective level of the fifth scan signal is a high level.
  • the seventh transistor M7 can be turned on under the control of the effective level of the light emitting control signal transmitted by the light emitting control signal terminal EM, and can be turned off under the control of the invalid level of the light emitting control signal.
  • the seventh transistor M7 is set as a P-type transistor, then the effective level of the light emitting control signal is a low level, and the invalid level of the light emitting control signal is a high level.
  • the seventh transistor M7 is set as an N-type transistor, then the effective level of the light emitting control signal is a high level, and the invalid level of the light emitting control signal is a low level.
  • the first storage sub-circuit 50 includes a first capacitor C1 , a first electrode of the first capacitor C1 is coupled to the first power supply terminal VDD, and a second electrode of the first capacitor C1 is coupled to the first node N1 .
  • the second storage subcircuit 60 includes: a second capacitor C2 , a first electrode of the second capacitor C2 is coupled to the first node N1 , and a second electrode of the second capacitor C2 is coupled to the gate of the driving transistor M0 .
  • the first electrode of the transistor may be its source, and the second electrode may be its drain.
  • the first electrode may be its drain, and the second electrode may be its source. This is not limited here.
  • transistors using low temperature polysilicon (LTPS) material as active layers have high mobility and can be made thinner and smaller, with lower power consumption, etc.
  • the material of the active layer of at least one of the above transistors can be set to low temperature polysilicon material. In this way, the above transistor can be set to an LTPS transistor, so that the pixel circuit can achieve high mobility and can be made thinner and smaller, with lower power consumption, etc.
  • the material of the active layer of at least one of the transistors may include a metal oxide semiconductor material, such as IGZO (Indium Gallium Zinc Oxide). Of course, it may also be other metal oxide semiconductor materials, which are not limited here. In this way, the transistor may be set as an oxide-type transistor (Oxide Thin Film Transistor) to reduce the leakage current of the pixel circuit.
  • IGZO Indium Gallium Zinc Oxide
  • the transistor may be set as an oxide-type transistor (Oxide Thin Film Transistor) to reduce the leakage current of the pixel circuit.
  • all transistors may be set as LTPS transistors.
  • all transistors may be set as oxide transistors.
  • some transistors may be set as oxide transistors, and the remaining transistors may be set as LTPS transistors.
  • the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 may be set as oxide transistors, and the driving transistor M0, the first transistor M1, and the seventh transistor M7 may be set as LTPS transistors.
  • the leakage current of the gate of the driving transistor M0 may be smaller, and the power consumption may be lower.
  • the first power supply terminal VDD can be configured to load a constant first power supply voltage vdd, and the first power supply voltage vdd is generally a positive value.
  • the second power supply terminal VSS can load a constant second power supply voltage vss, and the second power supply voltage vss can generally be a ground voltage or a negative value.
  • the specific values of the first power supply voltage vdd and the second power supply voltage vss can be designed and determined according to the actual application environment, and are not limited here.
  • a driving method of a pixel driving circuit is provided in an embodiment of the present disclosure, which may include the following steps:
  • the first control circuit responds to the signal of the first scanning signal terminal to connect the first electrode of the driving transistor to the first node;
  • the second control circuit responds to the signals of the second scanning signal terminal and the third scanning signal terminal to form a current path from the first node to the first initialization signal terminal;
  • the third control circuit responds to the signal of the first scanning signal terminal to provide the signal of the second initialization signal terminal to the gate of the driving transistor;
  • the first control circuit responds to the signal of the first scanning signal terminal to conduct the first electrode of the driving transistor with the first node;
  • the second control circuit responds to the signals of the second scanning signal terminal and the third scanning signal terminal to form a current path from the first node to the first initialization signal terminal, so that the threshold voltage of the driving transistor is input to the first node;
  • the third control circuit responds to the signal of the first scanning signal terminal to provide the signal of the second initialization signal terminal to the gate of the driving transistor;
  • the data writing circuit responds to the signal of the fourth scanning signal terminal, inputs the data voltage of the data signal terminal into the first node, so that the voltage of the first node changes from V1-Vth to Vda; due to the action of the second storage circuit, the voltage of the gate of the driving transistor changes from V1 to Vda+Vth; V1 represents the voltage value of the second initialization signal of the second initial voltage signal terminal, Vth represents the threshold voltage of the driving transistor M0, and Vda represents the data voltage loaded on the data signal terminal;
  • the third control circuit responds to the signal at the light-emitting control signal terminal to provide the signal at the first power supply terminal to the first electrode of the driving transistor; the second control circuit responds to the signal at the third scanning signal terminal to turn on the second electrode of the driving transistor and the light-emitting device.
  • the following takes the pixel driving circuit shown in FIG. 2 as an example, and describes the working process of the pixel driving circuit provided by the embodiment of the present disclosure in combination with the signal timing diagram shown in FIG. 4 .
  • em represents the light-emitting control signal of the light-emitting control signal terminal EM
  • ss1 represents the first scanning signal of the first scanning signal terminal SS1
  • ss2 represents the second scanning signal of the second scanning signal terminal SS2
  • ss3 represents the third scanning signal of the third scanning signal terminal SS3
  • ss4 represents the fourth scanning signal of the fourth scanning signal terminal SS4
  • ss5 represents the fifth scanning signal of the fifth scanning signal terminal SS5.
  • an initialization phase T1 a threshold compensation phase T2 , a data writing phase T3 , and a light emitting phase T4 in a display frame are selected.
  • Initialization stage T1 also includes a first stage T11 and a second stage T12, wherein in the first stage T11, the first transistor M1 is turned on under the control of the low level of the third scanning signal ss3, the second transistor M2 is turned on under the control of the high level of the second scanning signal ss2, the third transistor M3 and the fifth transistor M5 are turned on under the control of the high level of the first scanning signal ss1, the fourth transistor M4 is turned off under the control of the low level of the fourth scanning signal ss4, the sixth transistor M6 is turned off under the control of the low level of the fifth scanning signal ss5, and the seventh transistor M7 is turned off under the control of the high level of the light emitting control signal em.
  • the turned-on second transistor M2 inputs the first initialization signal of the first initial voltage signal terminal Vinit1 to the anode of the light emitting device L (i.e., the third node N3), and initializes the anode of the light emitting device L (i.e., the third node N3).
  • the turned-on first transistor M1 inputs the first initialization signal input to the light emitting device L (i.e., the third node N3) to the second electrode of the driving transistor M0.
  • the turned-on third transistor M3 turns on the first electrode of the driving transistor M0 and the first node N1.
  • the turned-on fifth transistor M5 inputs the second initialization signal of the second initial voltage signal terminal Vinit2 to the gate of the driving transistor M0 to initialize the gate of the driving transistor M0. And the turned-on first transistor M1 and the turned-on second transistor M2 form a current path from the first node N1 to the first initialization signal terminal Vinit1 when the third transistor M3 is turned on.
  • the first transistor M1 is turned off under the control of the high level of the third scan signal ss3
  • the second transistor M2 is turned on under the control of the high level of the second scan signal ss2
  • the third transistor M3 and the fifth transistor M5 are turned on under the control of the high level of the first scan signal ss1
  • the fourth transistor M4 is turned off under the control of the low level of the fourth scan signal ss4
  • the sixth transistor M6 is turned on under the control of the high level of the fifth scan signal ss5
  • the seventh transistor M7 is turned off under the control of the high level of the light emitting control signal em.
  • the turned-on second transistor M2 inputs the first initialization signal of the first initial voltage signal terminal Vinit1 to the anode of the light emitting device L (i.e., the third node N3), and initializes the anode of the light emitting device L (i.e., the third node N3).
  • the turned-on fifth transistor M5 inputs the second initialization signal of the second initial voltage signal terminal Vinit2 to the gate of the driving transistor M0, and initializes the gate of the driving transistor M0.
  • the turned-on sixth transistor M6 inputs the third initialization signal of the third initial voltage signal terminal Vinit3 to the first pole (i.e., the second node N2) of the driving transistor M0, and initializes the first pole (i.e., the second node N2) of the driving transistor M0.
  • the turned-on third transistor M3 conducts the first pole of the driving transistor M0 with the first node N1, so that the third initialization signal of the third initial voltage signal terminal Vinit3 is input to the first node N1, and the first node N1 is initialized.
  • the third initialization signal of the third initial voltage signal terminal Vinit3 is a high voltage.
  • Vgs represents the voltage difference between the gate and the first pole of the driving transistor M0
  • Vth represents the threshold voltage of the driving transistor M0.
  • the first transistor M1 is turned on under the control of the low level of the third scanning signal ss3
  • the second transistor M2 is turned on under the control of the high level of the second scanning signal ss2
  • the third transistor M3 and the fifth transistor M5 are turned on under the control of the high level of the first scanning signal ss1
  • the fourth transistor M4 is turned off under the control of the low level of the fourth scanning signal ss4
  • the sixth transistor M6 is turned off under the control of the low level of the fifth scanning signal ss5
  • the seventh transistor M7 is turned off under the control of the high level of the light emitting control signal em.
  • the turned-on fifth transistor M5 inputs the second initialization signal of the second initial voltage signal terminal Vinit2 to the gate of the driving transistor M0, and the gate voltage of the driving transistor M0 is V1.
  • V1 represents the voltage value of the second initialization signal of the second initial voltage signal terminal Vinit2.
  • the turned-on third transistor M3 turns on the first electrode of the driving transistor M0 and the first node N1.
  • the turned-on second transistor M2 inputs the first initialization signal of the first initial voltage signal terminal Vinit1 to the anode of the light emitting device L (i.e., the third node N3).
  • the first transistor M1 is turned on to conduct the second electrode of the driving transistor M0 with the anode of the light emitting device L (i.e., the third node N3).
  • the driving transistor M0 is still in the on state, and the first transistor M1 and the second transistor M2 are turned on.
  • the third transistor M3 is turned on, a current path from the first node N1 to the first initialization signal terminal Vinit1 is formed, so that the threshold voltage Vth of the driving transistor M0 is input to the first node N1.
  • the first transistor M1 is turned on under the control of the low level of the third scanning signal ss3
  • the second transistor M2 is turned off under the control of the low level of the second scanning signal ss2
  • the third transistor M3 and the fifth transistor M5 are turned off under the control of the low level of the first scanning signal ss1
  • the fourth transistor M4 is turned on under the control of the high level of the fourth scanning signal ss4
  • the sixth transistor M6 is turned off under the control of the low level of the fifth scanning signal ss5
  • the seventh transistor M7 is turned off under the control of the high level of the light emitting control signal em.
  • the first transistor M1 is turned on under the control of the low level of the third scanning signal ss3
  • the second transistor M2 is turned off under the control of the low level of the second scanning signal ss2
  • the third transistor M3 and the fifth transistor M5 are turned off under the control of the low level of the first scanning signal ss1
  • the fourth transistor M4 is turned off under the control of the low level of the fourth scanning signal ss4
  • the sixth transistor M6 is turned off under the control of the low level of the fifth scanning signal ss5
  • the seventh transistor M7 is turned on under the control of the low level of the light emitting control signal em.
  • the turned-on seventh transistor M7 conducts the first power supply terminal VDD with the first electrode (i.e., the second node N2) of the driving transistor M0, and the turned-on first transistor M1 conducts the second electrode of the driving transistor M0 with the anode (i.e., the third node N3) of the light emitting device L, so that the driving transistor M0 generates a current for driving the light emitting device L to emit light, so that the first power supply terminal VDD, the seventh transistor M7, the driving transistor M0, the light emitting device L and the second power supply terminal VSS form a current path, thereby driving the light emitting device L to emit light.
  • the first transistor M1 blocks the current path formed between the third initial voltage signal terminal Vinit3, the driving transistor M0, the second transistor M2 and the first initial voltage signal terminal Vinit1, that is, the short circuit path is blocked, reducing the risk of burning.
  • the disclosed embodiment provides some other structural schematic diagrams of the pixel driving circuit, as shown in Figure 5, which is a modification of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • the third scan signal terminal SS3 and the fifth scan signal terminal SS5 can be the same signal terminal.
  • the gate of the sixth transistor M6 is coupled to the third scan signal terminal SS3.
  • the first transistor M1 is a P-type transistor
  • the sixth transistor M6 is an N-type transistor.
  • the first scan signal terminal SS1 and the second scan signal terminal SS2 can be the same signal terminal.
  • the gate of the third transistor M3 and the gate of the fifth transistor M5 are coupled to the second scan signal terminal SS2. This can reduce the number of signal routing lines and reduce the wiring difficulty.
  • the second transistor M2 and the fifth transistor M5 are N-type transistors.
  • the signal timing diagram corresponding to the pixel driving circuit shown in Figure 5 may be shown in Figure 6.
  • the driving process of this embodiment is similar to the driving process of the aforementioned pixel driving circuit, so the driving process of this embodiment may be implemented with reference to the driving process of the aforementioned pixel driving circuit, and the repeated parts will not be repeated here.
  • the disclosed embodiment provides some structural schematic diagrams of the pixel driving circuit, as shown in Figure 7, which is a modification of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • the second electrode of the driving transistor M0 is coupled to the light-emitting device L
  • the second control circuit 20 is coupled to the light-emitting device L
  • the second control circuit 20 is configured to provide the signal of the first initialization signal terminal Vinit1 to the second electrode of the driving transistor M0 in response to the common control of the signals of the second scan signal terminal SS2 and the third scan signal terminal SS3.
  • the second control circuit 20 includes a first transistor M1 and a second transistor M2; the gate of the first transistor M1 is coupled to the third scan signal terminal SS3, the first electrode of the first transistor M1 is coupled to the second electrode of the driving transistor M0, and the second electrode of the first transistor M1 is coupled to the first electrode of the second transistor M2.
  • the gate of the second transistor M2 is coupled to the second scan signal terminal SS2, and the second electrode of the second transistor M2 is coupled to the first initialization signal terminal Vinit1.
  • the first transistor M1 is a P-type transistor
  • the sixth transistor M6 is an N-type transistor.
  • the following takes the pixel driving circuit shown in FIG. 8 as an example and describes the working process of the pixel driving circuit provided by the embodiment of the present disclosure in combination with the signal timing diagram shown in FIG. 4 .
  • em represents the light-emitting control signal of the light-emitting control signal terminal EM
  • ss1 represents the first scanning signal of the first scanning signal terminal SS1
  • ss2 represents the second scanning signal of the second scanning signal terminal SS2
  • ss3 represents the third scanning signal of the third scanning signal terminal SS3
  • ss4 represents the fourth scanning signal of the fourth scanning signal terminal SS4
  • ss5 represents the fifth scanning signal of the fifth scanning signal terminal SS5.
  • an initialization phase T1 a threshold compensation phase T2 , a data writing phase T3 , and a light emitting phase T4 in a display frame are selected.
  • Initialization stage T1 also includes a first stage T11 and a second stage T12, wherein in the first stage T11, the first transistor M1 is turned on under the control of the low level of the third scanning signal ss3, the second transistor M2 is turned on under the control of the high level of the second scanning signal ss2, the third transistor M3 and the fifth transistor M5 are turned on under the control of the high level of the first scanning signal ss1, the fourth transistor M4 is turned off under the control of the low level of the fourth scanning signal ss4, the sixth transistor M6 is turned off under the control of the low level of the fifth scanning signal ss5, and the seventh transistor M7 is turned off under the control of the high level of the light emitting control signal em.
  • the turned-on second transistor M2 inputs the first initialization signal of the first initial voltage signal terminal Vinit1 to the anode of the light emitting device L (i.e., the third node N3), and initializes the anode of the light emitting device L (i.e., the third node N3).
  • the turned-on first transistor M1 inputs the first initialization signal input to the light emitting device L (i.e., the third node N3) to the second electrode of the driving transistor M0.
  • the turned-on third transistor M3 turns on the first electrode of the driving transistor M0 and the first node N1.
  • the turned-on fifth transistor M5 inputs the second initialization signal of the second initial voltage signal terminal Vinit2 to the gate of the driving transistor M0 to initialize the gate of the driving transistor M0. And the turned-on first transistor M1 and the turned-on second transistor M2 form a current path from the first node N1 to the first initialization signal terminal Vinit1 when the third transistor M3 is turned on.
  • the first transistor M1 is turned off under the control of the high level of the third scan signal ss3
  • the second transistor M2 is turned on under the control of the high level of the second scan signal ss2
  • the third transistor M3 and the fifth transistor M5 are turned on under the control of the high level of the first scan signal ss1
  • the fourth transistor M4 is turned off under the control of the low level of the fourth scan signal ss4
  • the sixth transistor M6 is turned on under the control of the high level of the fifth scan signal ss5
  • the seventh transistor M7 is turned off under the control of the high level of the light emitting control signal em.
  • the turned-on second transistor M2 inputs the first initialization signal of the first initial voltage signal terminal Vinit1 to the anode of the light emitting device L (i.e., the third node N3), and initializes the anode of the light emitting device L (i.e., the third node N3).
  • the turned-on fifth transistor M5 inputs the second initialization signal of the second initial voltage signal terminal Vinit2 to the gate of the driving transistor M0, and initializes the gate of the driving transistor M0.
  • the turned-on sixth transistor M6 inputs the third initialization signal of the third initial voltage signal terminal Vinit3 to the first pole (i.e., the second node N2) of the driving transistor M0, and initializes the first pole (i.e., the second node N2) of the driving transistor M0.
  • the turned-on third transistor M3 conducts the first pole of the driving transistor M0 with the first node N1, so that the third initialization signal of the third initial voltage signal terminal Vinit3 is input to the first node N1, and the first node N1 is initialized.
  • the third initialization signal of the third initial voltage signal terminal Vinit3 is a high voltage.
  • Vgs represents the voltage difference between the gate and the first pole of the driving transistor M0
  • Vth represents the threshold voltage of the driving transistor M0.
  • the first transistor M1 is turned on under the control of the low level of the third scanning signal ss3
  • the second transistor M2 is turned on under the control of the high level of the second scanning signal ss2
  • the third transistor M3 and the fifth transistor M5 are turned on under the control of the high level of the first scanning signal ss1
  • the fourth transistor M4 is turned off under the control of the low level of the fourth scanning signal ss4
  • the sixth transistor M6 is turned off under the control of the low level of the fifth scanning signal ss5
  • the seventh transistor M7 is turned off under the control of the high level of the light emitting control signal em.
  • the turned-on fifth transistor M5 inputs the second initialization signal of the second initial voltage signal terminal Vinit2 to the gate of the driving transistor M0, and the gate voltage of the driving transistor M0 is V1.
  • V1 represents the voltage value of the second initialization signal of the second initial voltage signal terminal Vinit2.
  • the turned-on third transistor M3 turns on the first electrode of the driving transistor M0 and the first node N1.
  • the turned-on second transistor M2 inputs the first initialization signal of the first initial voltage signal terminal Vinit1 to the anode of the light emitting device L (i.e., the third node N3).
  • the first transistor M1 is turned on to conduct the second electrode of the driving transistor M0 with the anode of the light emitting device L (i.e., the third node N3).
  • the driving transistor M0 is still in the on state, and the first transistor M1 and the second transistor M2 are turned on.
  • the third transistor M3 is turned on, a current path from the first node N1 to the first initialization signal terminal Vinit1 is formed, so that the threshold voltage Vth of the driving transistor M0 is input to the first node N1.
  • the first transistor M1 is turned on under the control of the low level of the third scanning signal ss3
  • the second transistor M2 is turned off under the control of the low level of the second scanning signal ss2
  • the third transistor M3 and the fifth transistor M5 are turned off under the control of the low level of the first scanning signal ss1
  • the fourth transistor M4 is turned on under the control of the high level of the fourth scanning signal ss4
  • the sixth transistor M6 is turned off under the control of the low level of the fifth scanning signal ss5
  • the seventh transistor M7 is turned off under the control of the high level of the light emitting control signal em.
  • the first transistor M1 is turned on under the control of the low level of the third scanning signal ss3
  • the second transistor M2 is turned off under the control of the low level of the second scanning signal ss2
  • the third transistor M3 and the fifth transistor M5 are turned off under the control of the low level of the first scanning signal ss1
  • the fourth transistor M4 is turned off under the control of the low level of the fourth scanning signal ss4
  • the sixth transistor M6 is turned off under the control of the low level of the fifth scanning signal ss5
  • the seventh transistor M7 is turned on under the control of the low level of the light emitting control signal em.
  • the turned-on seventh transistor M7 conducts the first power supply terminal VDD with the first electrode (i.e., the second node N2) of the driving transistor M0, and the turned-on first transistor M1 conducts the second electrode of the driving transistor M0 with the anode (i.e., the third node N3) of the light emitting device L, so that the driving transistor M0 generates a current for driving the light emitting device L to emit light, so that the first power supply terminal VDD, the seventh transistor M7, the driving transistor M0, the light emitting device L and the second power supply terminal VSS form a current path, thereby driving the light emitting device L to emit light.
  • the disclosed embodiment provides some structural schematic diagrams of the pixel driving circuit, as shown in Figure 9, which is a modification of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • the first transistor M1 is an N-type transistor
  • the sixth transistor M6 is an N-type transistor.
  • the phase of the signal at the third scan signal terminal SS3 is opposite to the phase of the signal at the fifth scan signal terminal SS5 .
  • the following takes the pixel driving circuit shown in FIG. 9 as an example, and describes the working process of the pixel driving circuit provided by the embodiment of the present disclosure in combination with the signal timing diagram shown in FIG. 10 .
  • em represents the light-emitting control signal of the light-emitting control signal terminal EM
  • ss1 represents the first scanning signal of the first scanning signal terminal SS1
  • ss2 represents the second scanning signal of the second scanning signal terminal SS2
  • ss3 represents the third scanning signal of the third scanning signal terminal SS3
  • ss4 represents the fourth scanning signal of the fourth scanning signal terminal SS4
  • ss5 represents the fifth scanning signal of the fifth scanning signal terminal SS5.
  • an initialization phase T1 a threshold compensation phase T2 , a data writing phase T3 , and a light emitting phase T4 in a display frame are selected.
  • Initialization stage T1 also includes a first stage T11 and a second stage T12, wherein, in the first stage T11, the first transistor M1 is turned on under the control of the high level of the third scanning signal ss3, the second transistor M2 is turned on under the control of the high level of the second scanning signal ss2, the third transistor M3 and the fifth transistor M5 are turned on under the control of the high level of the first scanning signal ss1, the fourth transistor M4 is turned off under the control of the low level of the fourth scanning signal ss4, the sixth transistor M6 is turned off under the control of the low level of the fifth scanning signal ss5, and the seventh transistor M7 is turned off under the control of the high level of the light emitting control signal em.
  • the turned-on second transistor M2 inputs the first initialization signal of the first initial voltage signal terminal Vinit1 to the anode of the light emitting device L (i.e., the third node N3), and initializes the anode of the light emitting device L (i.e., the third node N3).
  • the turned-on first transistor M1 inputs the first initialization signal input to the light emitting device L (i.e., the third node N3) to the second electrode of the driving transistor M0.
  • the turned-on third transistor M3 turns on the first electrode of the driving transistor M0 and the first node N1.
  • the turned-on fifth transistor M5 inputs the second initialization signal of the second initial voltage signal terminal Vinit2 to the gate of the driving transistor M0 to initialize the gate of the driving transistor M0. And the turned-on first transistor M1 and the turned-on second transistor M2 form a current path from the first node N1 to the first initialization signal terminal Vinit1 when the third transistor M3 is turned on.
  • the first transistor M1 is turned off under the control of the low level of the third scan signal ss3
  • the second transistor M2 is turned on under the control of the high level of the second scan signal ss2
  • the third transistor M3 and the fifth transistor M5 are turned on under the control of the high level of the first scan signal ss1
  • the fourth transistor M4 is turned off under the control of the low level of the fourth scan signal ss4
  • the sixth transistor M6 is turned on under the control of the high level of the fifth scan signal ss5
  • the seventh transistor M7 is turned off under the control of the high level of the light emitting control signal em.
  • the turned-on second transistor M2 inputs the first initialization signal of the first initial voltage signal terminal Vinit1 to the anode of the light emitting device L (i.e., the third node N3), and initializes the anode of the light emitting device L (i.e., the third node N3).
  • the turned-on fifth transistor M5 inputs the second initialization signal of the second initial voltage signal terminal Vinit2 to the gate of the driving transistor M0, and initializes the gate of the driving transistor M0.
  • the turned-on sixth transistor M6 inputs the third initialization signal of the third initial voltage signal terminal Vinit3 to the first electrode (i.e., the second node N2) of the driving transistor M0, and initializes the first electrode (i.e., the second node N2) of the driving transistor M0.
  • the turned-on third transistor M3 conducts the first electrode of the driving transistor M0 with the first node N1, so that the third initialization signal of the third initial voltage signal terminal Vinit3 is input to the first node N1, and initializes the first node N1.
  • the third initialization signal of the third initial voltage signal terminal Vinit3 is a high voltage.
  • Vgs represents the voltage difference between the gate and the first electrode of the driving transistor M0
  • Vth represents the threshold voltage of the driving transistor M0.
  • the first transistor M1 is turned on under the control of the high level of the third scan signal ss3
  • the second transistor M2 is turned on under the control of the high level of the second scan signal ss2
  • the third transistor M3 and the fifth transistor M5 are turned on under the control of the high level of the first scan signal ss1
  • the fourth transistor M4 is turned off under the control of the low level of the fourth scan signal ss4
  • the sixth transistor M6 is turned off under the control of the low level of the fifth scan signal ss5
  • the seventh transistor M7 is turned off under the control of the high level of the light emitting control signal em.
  • the turned-on fifth transistor M5 inputs the second initialization signal of the second initial voltage signal terminal Vinit2 to the gate of the driving transistor M0, and the gate voltage of the driving transistor M0 is V1.
  • V1 represents the voltage value of the second initialization signal of the second initial voltage signal terminal Vinit2.
  • the turned-on third transistor M3 turns on the first electrode of the driving transistor M0 and the first node N1.
  • the turned-on second transistor M2 inputs the first initialization signal of the first initial voltage signal terminal Vinit1 to the anode of the light emitting device L (i.e., the third node N3).
  • the first transistor M1 that is turned on conducts the second electrode of the driving transistor M0 with the anode of the light emitting device L (i.e., the third node N3).
  • the driving transistor M0 is still in the on state, and the first transistor M1 that is turned on and the second transistor M2 that is turned on form a current path from the first node N1 to the first initialization signal terminal Vinit1 when the third transistor M3 is turned on, so that the threshold voltage Vth of the driving transistor M0 is input to the first node N1.
  • the first transistor M1 is turned on under the control of the high level of the third scanning signal ss3
  • the second transistor M2 is turned off under the control of the low level of the second scanning signal ss2
  • the third transistor M3 and the fifth transistor M5 are turned off under the control of the low level of the first scanning signal ss1
  • the fourth transistor M4 is turned on under the control of the high level of the fourth scanning signal ss4
  • the sixth transistor M6 is turned off under the control of the low level of the fifth scanning signal ss5
  • the seventh transistor M7 is turned off under the control of the high level of the light emitting control signal em.
  • the first transistor M1 is turned on under the control of the high level of the third scanning signal ss3, the second transistor M2 is turned off under the control of the low level of the second scanning signal ss2, the third transistor M3 and the fifth transistor M5 are turned off under the control of the low level of the first scanning signal ss1, the fourth transistor M4 is turned off under the control of the low level of the fourth scanning signal ss4, the sixth transistor M6 is turned off under the control of the low level of the fifth scanning signal ss5, and the seventh transistor M7 is turned on under the control of the low level of the light emitting control signal em.
  • the turned-on seventh transistor M7 connects the first power supply terminal VDD with the first electrode (i.e., the second node N2) of the driving transistor M0, and the turned-on first transistor M1 connects the second electrode of the driving transistor M0 with the anode (i.e., the third node N3) of the light emitting device L, so that the driving transistor M0 generates a current for driving the light emitting device L to emit light, so that the first power supply terminal VDD, the seventh transistor M7, the driving transistor M0, the light emitting device L and the second power supply terminal VSS form a current path, thereby driving the light emitting device L to emit light.
  • the disclosed embodiment provides some structural schematic diagrams of the pixel driving circuit, as shown in Figure 11, which is a modification of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • the third scan signal terminal SS3 and the fifth scan signal terminal SS5 can be the same signal terminal.
  • the gate of the sixth transistor M6 is coupled to the third scan signal terminal SS3 .
  • the first scan signal terminal SS1 and the second scan signal terminal SS2 can be the same signal terminal.
  • the gate of the third transistor M3 and the gate of the fifth transistor M5 are coupled to the second scan signal terminal SS2. This can reduce the number of signal routing lines and reduce the wiring difficulty.
  • the signal timing diagram corresponding to the pixel driving circuit shown in Figure 11 can be shown in Figure 6.
  • the driving process of this embodiment is similar to the driving process of the aforementioned pixel driving circuit, so the driving process of this embodiment can be implemented with reference to the driving process of the aforementioned pixel driving circuit, and the repeated parts are not repeated here.
  • the embodiment of the present invention further provides a display device, comprising a plurality of sub-pixels; wherein each sub-pixel comprises the above-mentioned pixel driving circuit.
  • a display device comprising a plurality of sub-pixels; wherein each sub-pixel comprises the above-mentioned pixel driving circuit.
  • the principle of solving the problem by the display device is similar to that of the above-mentioned pixel driving circuit, so the implementation of the display device can refer to the implementation of the above-mentioned pixel driving circuit, and the repeated parts are not repeated here.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.
  • Other essential components of the display device are well understood by those skilled in the art, and are not described in detail here, nor should they be used as limitations on the present invention.

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Abstract

一种像素驱动电路、驱动方法及其显示装置，包括：发光器件(L)；驱动晶体管(M0)，被配置为根据数据电压(Vda)产生驱动发光器件(L)发光的电流；第一控制电路(10)，被配置为响应于第一扫描信号端(SS1)的信号，将驱动晶体管(M0)的第一极与第一节点(N1)导通；第二控制电路(20)，被配置为响应于第二扫描信号端(SS2)和第三扫描信号端(SS3)的信号，并在第一控制电路(10)将驱动晶体管(M0)的第一极与第一节点(N1)导通时，形成第一节点(N1)至第一初始化信号端(Vinit1)的电流通路，使驱动晶体管(M0)的阈值电压(Vth)输入第一节点(N1)；数据写入电路(30)，被配置为响应于第四扫描信号端(SS4)的信号，将数据信号端(DA)的数据电压(Vda)输入第一节点(N1)，使第一节点(N1)的电压由V1-Vth 变化为Vda。

Description

像素驱动电路、驱动方法及其显示装置 技术领域
本公开涉及显示技术领域，尤其涉及像素驱动电路、驱动方法及其显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)、微型发光二极管(Micro Light Emitting Diode，Micro LED)、迷你发光二极管(Mini Light Emitting Diode，Mini LED)等发光器件具有自发光、低能耗等优点，是当今显示装置应用研究领域的热点之一。一般显示装置中采用像素驱动电路来驱动发光器件发光。
发明内容
本公开实施例提供的像素驱动电路，包括：
发光器件；
驱动晶体管，被配置为根据数据电压产生驱动所述发光器件发光的电流；
第一控制电路，被配置为响应于第一扫描信号端的信号，将所述驱动晶体管的第一极与第一节点导通；
第二控制电路，被配置为响应于第二扫描信号端和第三扫描信号端的信号，并在所述第一控制电路将所述驱动晶体管的第一极与所述第一节点导通时，形成所述第一节点至第一初始化信号端的电流通路，使所述驱动晶体管的阈值电压输入所述第一节点；
数据写入电路，被配置为响应于第四扫描信号端的信号，将数据信号端的所述数据电压输入所述第一节点，使所述第一节点的电压由V1-Vth变化为Vda；
第三控制电路，被配置为响应于第一扫描信号端的信号，将第二初始化 信号端的信号提供给所述驱动晶体管的栅极，响应于第五扫描信号端的信号，将第三初始化信号端的信号提供给所述驱动晶体管的第一极，以及响应于发光控制信号端的信号，将第一电源端的信号提供给所述驱动晶体管的第一极；
第一存储电路，被配置为保持所述第一节点与所述第一电源端之间的电压差稳定；
第二存储电路，被配置为保持所述第一节点与所述驱动晶体管的栅极之间的电压差稳定，并在所述第一节点的电压由V1-Vth变化为Vda时，使所述驱动晶体管的栅极的电压由V1变化为Vda+Vth；V1代表第二初始电压信号端的第二初始化信号的电压值，Vth代表驱动晶体管的阈值电压，Vda代表数据信号端加载的数据电压。
在一些可能的实施方式中，所述驱动晶体管的第二极通过所述第二控制电路与所述发光器件耦接；
所述第二控制电路被配置为响应于所述第三扫描信号端的信号，将所述驱动晶体管的第二极与所述发光器件导通，以及响应于所述第二扫描信号端的信号，将所述第一初始化信号端的信号提供给所述发光器件。
在一些可能的实施方式中，所述第二控制电路包括第一晶体管以及第二晶体管；
所述第一晶体管的栅极与所述第三扫描信号端耦接，所述第一晶体管的第一极与所述发光器件耦接，所述第一晶体管的第二极与所述驱动晶体管的第二极耦接；
所述第二晶体管的栅极与所述第二扫描信号端耦接，所述第二晶体管的第一极与所述发光器件耦接，所述第二晶体管的第二极与所述第一初始化信号端耦接。
在一些可能的实施方式中，所述驱动晶体管的第二极与所述发光器件耦接，所述第二控制电路与所述发光器件耦接；
所述第二控制电路被配置为响应于所述第二扫描信号端和所述第三扫描信号端的信号的共同控制，将所述第一初始化信号端的信号提供给所述驱动 晶体管的第二极。
在一些可能的实施方式中，所述第二控制电路包括第一晶体管以及第二晶体管；
所述第一晶体管的栅极与所述第三扫描信号端耦接，所述第一晶体管的第一极与所述驱动晶体管的第二极耦接，所述第一晶体管的第二极与所述第二晶体管的第一极耦接；
所述第二晶体管的栅极与所述第二扫描信号端耦接，所述第二晶体管的第二极与所述第一初始化信号端耦接。
在一些可能的实施方式中，所述第一控制电路包括第三晶体管；
所述第三晶体管的栅极与所述第一扫描信号端耦接，所述第三晶体管的第一极与所述驱动晶体管的第一极耦接，所述第三晶体管的第二极与所述第一节点耦接。
在一些可能的实施方式中，所述数据写入电路包括第四晶体管；
所述第四晶体管的栅极与所述第四扫描信号端耦接，所述第四晶体管的第一极与所述数据信号端耦接，所述第四晶体管的第二极与所述第一节点耦接。
在一些可能的实施方式中，所述第三控制电路包括第五晶体管、第六晶体管以及第七晶体管；
所述第五晶体管的栅极与所述第一扫描信号端耦接，所述第五晶体管的第一极与所述驱动晶体管的栅极耦接，所述第五晶体管的第二极与所述第二初始电压信号端耦接；
所述第六晶体管的栅极与所述第五扫描信号端耦接，所述第六晶体管的第一极与所述驱动晶体管的第一极耦接，所述第六晶体管的第二极与所述第三初始电压信号端耦接。
所述第七晶体管的栅极与所述发光控制信号端耦接，所述第七晶体管的第一极与所述驱动晶体管的第一极耦接，所述第七晶体管的第二极与所述第一电源端耦接。
在一些可能的实施方式中，所述第一存储子电路包括第一电容，所述第一电容的第一电极与所述第一电源端耦接，所述第一电容的第二电极与所述第一节点耦接；
和/或，所述第二存储子电路包括：第二电容，所述第二电容的第一电极与所述第一节点耦接，所述第二电容的第二电极与所述驱动晶体管的栅极耦接。
在一些可能的实施方式中，所述第三扫描信号端与所述第五扫描信号端为同一信号端。
在一些可能的实施方式中，所述第三扫描信号端的信号的相位与所述第五扫描信号端的信号的相位相反。
在一些可能的实施方式中，所述第一扫描信号端与所述第二扫描信号端为同一信号端。
本公开实施例提供的显示装置，包括上述的像素驱动电路。
本公开实施例提供的上述的像素驱动电路的驱动方法包括：
初始化阶段，所述第一控制电路响应于所述第一扫描信号端的信号，将所述驱动晶体管的第一极与第一节点导通；所述第二控制电路响应于所述第二扫描信号端和所述第三扫描信号端的信号，形成所述第一节点至第一初始化信号端的电流通路；所述第三控制电路响应于所述第一扫描信号端的信号，将所述第二初始化信号端的信号提供给所述驱动晶体管的栅极；
阈值补偿阶段，所述第一控制电路响应于所述第一扫描信号端的信号，将所述驱动晶体管的第一极与第一节点导通；所述第二控制电路响应于所述第二扫描信号端和所述第三扫描信号端的信号，形成所述第一节点至第一初始化信号端的电流通路，使所述驱动晶体管的阈值电压输入所述第一节点；所述第三控制电路响应于所述第一扫描信号端的信号，将所述第二初始化信号端的信号提供给所述驱动晶体管的栅极；
数据写入阶段，所述数据写入电路响应于第四扫描信号端的信号，将数据信号端的所述数据电压输入所述第一节点，使所述第一节点的电压由 V1-Vth变化为Vda；由于第二存储电路的作用，使所述驱动晶体管的栅极的电压由V1变为Vda+Vth；V1代表所述第二初始电压信号端的第二初始化信号的电压值，Vth代表所述驱动晶体管的阈值电压，Vda代表所述数据信号端加载的数据电压；
发光阶段，所述第三控制电路响应于所述发光控制信号端的信号，将所述第一电源端的信号提供给所述驱动晶体管的第一极；所述第二控制电路响应于所述第三扫描信号端的信号，将所述驱动晶体管的第二极与所述发光器件导通。
附图说明
图1为本公开实施例提供的像素驱动电路的一些结构示意图；
图2为本公开实施例提供的像素驱动电路的另一些结构示意图；
图3为本公开实施例提供的像素驱动电路的驱动方法的流程图；
图4为本公开实施例提供的一些信号时序图；
图5为本公开实施例提供的像素驱动电路的又一些结构示意图；
图6为本公开实施例提供的另一些信号时序图；
图7为本公开实施例提供的像素驱动电路的又一些结构示意图；
图8为本公开实施例提供的像素驱动电路的又一些结构示意图；
图9为本公开实施例提供的像素驱动电路的又一些结构示意图；
图10为本公开实施例提供的又一些信号时序图；
图11为本公开实施例提供的像素驱动电路的又一些结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所 描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
本公开实施例提供的显示装置，包括：显示面板，显示面板的显示区中包括多个阵列排布的像素单元，像素单元包括多个子像素。示例性地，每个像素单元包括多个子像素。例如，像素单元可以包括红色子像素，绿色子像素以及蓝色子像素，这样可以通过红绿蓝进行混色，以实现彩色显示。或者，像素单元也可以包括红色子像素，绿色子像素、蓝色子像素以及白色子像素，这样可以通过红绿蓝白进行混色，以实现彩色显示。当然，在实际应用中，像素单元中的子像素的发光颜色可以根据实际应用环境来设计确定，在此不作限定。
在本公开实施例中，各子像素中包括像素驱动电路，像素驱动电路包括驱动晶体管和发光器件，以控制发光器件发光，从而使显示面板实现画面显示的功能。
本公开实施例提供了像素驱动电路，如图1所示，包括：发光器件L、驱动晶体管M0、第一控制电路10、第二控制电路20、数据写入电路30、第三控制电路40、第一存储电路50以及第二存储电路60。
其中，驱动晶体管M0被配置为根据数据电压产生驱动发光器件L发光 的电流。第一控制电路10，被配置为响应于第一扫描信号端SS1的信号，将驱动晶体管M0的第一极与第一节点导通；第二控制电路20，被配置为响应于第二扫描信号端SS2和第三扫描信号端SS3的信号，并在第一控制电路10将驱动晶体管M0的第一极与第一节点N1导通时，形成第一节点N1至第一初始化信号端Vinit1的电流通路，使驱动晶体管M0的阈值电压Vth输入第一节点N1；数据写入电路30，被配置为响应于第四扫描信号端SS4的信号，将数据信号端DA的数据电压Vda输入第一节点N1，使第一节点N1的电压由V1-Vth变化为Vda；第三控制电路40，被配置为响应于第一扫描信号端SS1的信号，将第二初始化信号端Vinit2的信号提供给驱动晶体管M0的栅极，响应于第五扫描信号端SS5的信号，将第三初始化信号端Vinit3的信号提供给驱动晶体管M0的第一极，以及响应于发光控制信号端EM的信号，将第一电源端VDD的信号提供给驱动晶体管M0的第一极；第一存储电路50，被配置为保持第一节点N1与第一电源端VDD之间的电压差稳定；第二存储电路60，被配置为保持第一节点N1与驱动晶体管M0的栅极之间的电压差稳定，并在第一节点N1的电压由V1-Vth变化为Vda时，使驱动晶体管M0的栅极的电压由V1变化为Vda+Vth；V1代表第二初始电压信号端Vinit2的第二初始化信号的电压值，Vth代表驱动晶体管M0的阈值电压，Vda代表数据信号端DA加载的数据电压。
在本公开实施例中，通过设置第一控制电路、第二控制电路、数据写入电路、第三控制电路、第一存储电路以及第二存储电路，从而实现对驱动晶体管进行初始化的时间段与对驱动晶体管的阈值电压Vth进行阈值补偿的时间段不重叠，这样可以阻断像素驱动电路中部分的电流通路，从而减小电路中的电流，降低电路短路风险和灼烧风险，从而改善像素驱动电路的性能。
在本公开一些实施例中，如图1所示，驱动晶体管M0可以设置为P型晶体管；其中，驱动晶体管M0的第一极可以为其源极，驱动晶体管M0的第二极可以为其漏极，并且该驱动晶体管M0处于饱和状态时，电流由驱动晶体管M0的源极流向其漏极。当然，驱动晶体管M0也可以设置为N型晶体管， 在此不作限定。
在本公开实施例中，如图1所示，发光器件L的第一电极可以通过第二控制电路20与驱动晶体管M0的第二极耦接。发光器件L的第二电极可以与第二电源端VSS耦接。在一些示例中，发光器件L的第一电极可以为其阳极，第二电极为其阴极。示例性地，发光器件L可以为有机发光二极管。例如，发光器件L可以包括：微型发光二极管(Micro Light Emitting Diode，Micro LED)、有机发光二极管(Organic Light Emitting Diode，OLED)以及量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)中的至少一种。示例性地，发光器件L可以包括层叠设置的阳极、发光层、阴极。进一步地，发光层还可以包括空穴注入层、空穴传输层、电子传输层、电子注入层等膜层。在实际应用中，可以根据实际应用环境来设计确定发光器件L的具体结构，在此不作限定。
在本公开实施例中，如图2所示，驱动晶体管M0的第二极通过第二控制电路20与发光器件L耦接；
第二控制电路20被配置为响应于第三扫描信号端SS3的信号，将驱动晶体管M0的第二极与发光器件L导通，以及响应于第二扫描信号端SS2的信号，将第一初始化信号端Vinit1的信号提供给发光器件L。
在本公开实施例中，如图2所示，第二控制电路20包括第一晶体管M1以及第二晶体管M2；第一晶体管M1的栅极与第三扫描信号端SS3耦接，第一晶体管M1的第一极与发光器件L耦接，第一晶体管M1的第二极与驱动晶体管M0的第二极耦接。第二晶体管M2的栅极与第二扫描信号端SS2耦接，第二晶体管M2的第一极与发光器件L耦接，第二晶体管M2的第二极与第一初始化信号端Vinit1耦接。
示例性地，第一晶体管M1可以在第三扫描信号端SS3传输的第三扫描信号的有效电平的控制下导通，可以在第三扫描信号的无效电平的控制下截止。示例性地，第一晶体管M1设置为P型晶体管，则第三扫描信号有效电平为低电平，第三扫描信号的无效电平为高电平。或者，第一晶体管M1设置 为N型晶体管，则第三扫描信号的有效电平为高电平，第三扫描信号的无效电平为低电平。
示例性地，第二晶体管M2可以在第二扫描信号端SS2传输的第二扫描信号的有效电平的控制下导通，可以在第二扫描信号的无效电平的控制下截止。示例性地，第二晶体管M2设置为N型晶体管，则第二扫描信号的有效电平为高电平，第二扫描信号的无效电平为低电平。或者，第二晶体管M2设置为P型晶体管，则第二扫描信号有效电平为低电平，第二扫描信号的无效电平为高电平。
在本公开实施例中，如图2所示，第一控制电路10包括第三晶体管M3；第三晶体管M3的栅极与第一扫描信号端SS1耦接，第三晶体管M3的第一极与驱动晶体管M0的第一极耦接，第三晶体管M3的第二极与第一节点N1耦接。
示例性地，第三晶体管M3可以在第一扫描信号端SS1传输的第一扫描信号的有效电平的控制下导通，可以在第一扫描信号的无效电平的控制下截止。示例性地，第三晶体管M3设置为N型晶体管，则第一扫描信号的有效电平为高电平，第一扫描信号的无效电平为低电平。或者，第三晶体管M3设置为P型晶体管，则第一扫描信号的有效电平为低电平，第一扫描信号的无效电平为高电平。
在本公开实施例中，如图2所示，数据写入电路30包括第四晶体管M4；第四晶体管M4的栅极与第四扫描信号端SS4耦接，第四晶体管M4的第一极与数据信号端DA耦接，第四晶体管M4的第二极与第一节点N1耦接。
示例性地，第四晶体管M4可以在第四扫描信号端SS4传输的第四扫描信号的有效电平的控制下导通，可以在第四扫描信号的无效电平的控制下截止。示例性地，第四晶体管M4设置为N型晶体管，则第四扫描信号的有效电平为高电平，第四扫描信号的无效电平为低电平。或者，第四晶体管M4设置为P型晶体管，则第四扫描信号的有效电平为低电平，第四扫描信号的无效电平为高电平。
在本公开实施例中，如图2所示，第三控制电路40包括第五晶体管M5、第六晶体管M6以及第七晶体管M7；第五晶体管M5的栅极与第一扫描信号端SS1耦接，第五晶体管M5的第一极与驱动晶体管M0的栅极耦接，第五晶体管M5的第二极与第二初始电压信号端Vinit2耦接；第六晶体管M6的栅极与第五扫描信号端SS5耦接，第六晶体管M6的第一极与驱动晶体管M0的第一极耦接，第六晶体管M6的第二极与第三初始电压信号端Vinit3耦接。第七晶体管M7的栅极与发光控制信号端EM耦接，第七晶体管M7的第一极与驱动晶体管M0的第一极耦接，第七晶体管M7的第二极与第一电源端VDD耦接。
示例性地，第五晶体管M5可以在第一扫描信号端SS1传输的第一扫描信号的有效电平的控制下导通，可以在第一扫描信号的无效电平的控制下截止。示例性地，第五晶体管M5设置为N型晶体管，则第一扫描信号的有效电平为高电平，第一扫描信号的无效电平为低电平。或者，第五晶体管M5设置为P型晶体管，则第一扫描信号的有效电平为低电平，第一扫描信号的无效电平为高电平。
示例性地，第六晶体管M6可以在第五扫描信号端SS5传输的第五扫描信号的有效电平的控制下导通，可以在第五扫描信号的无效电平的控制下截止。示例性地，第六晶体管M6设置为N型晶体管，则第五扫描信号的有效电平为高电平，第五扫描信号的无效电平为低电平。或者，第六晶体管M6设置为P型晶体管，则第五扫描信号的有效电平为低电平，第五扫描信号的无效电平为高电平。
示例性地，第七晶体管M7可以在发光控制信号端EM传输的发光控制信号的有效电平的控制下导通，可以在发光控制信号的无效电平的控制下截止。示例性地，第七晶体管M7设置为P型晶体管，则发光控制信号有效电平为低电平，发光控制信号的无效电平为高电平。或者，第七晶体管M7设置为N型晶体管，则发光控制信号有效电平为高电平，发光控制信号的无效电平为低电平。
在本公开实施例中，如图2所示，第一存储子电路50包括第一电容C1，第一电容C1的第一电极与第一电源端VDD耦接，第一电容C1的第二电极与第一节点N1耦接。
在本公开实施例中，如图2所示，第二存储子电路60包括：第二电容C2，第二电容C2的第一电极与第一节点N1耦接，第二电容C2的第二电极与驱动晶体管M0的栅极耦接。
示例性地，上述的晶体管的第一极可以为其源极，第二极可以为其漏极。或者，第一极为其漏极，第二极为其源极。在此不作限定。
一般采用低温多晶硅(Low Temperature Poly-Silicon，LTPS)材料作为有源层的晶体管的迁移率高且可以做得更薄更小、功耗更低等，在具体实施时，上述至少一个晶体管的有源层的材料可以设置为低温多晶硅材料。这样可以将上述晶体管设置为LTPS型晶体管，以使像素电路实现迁移率高且可以做得更薄更小、功耗更低等。
一般采用金属氧化物半导体材料作为有源层的晶体管的漏电流较小，因此为了降低漏电流，在本公开一些实施例中，也可以使上述至少一个晶体管的有源层的材料包括金属氧化物半导体材料，例如可以为IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)，当然，也可以为其他金属氧化物半导体材料，在此不作限定。这样可以将上述晶体管设置为氧化物型晶体管(Oxide Thin Film Transistor)，以使像素电路的漏电流减小。
示例性地，可以将所有晶体管均设置为LTPS型晶体管。或者，可以将所有晶体管均设置为氧化物型晶体管。或者，也可以使部分晶体管设置为氧化物型晶体管，其余晶体管设置为LTPS型晶体管。示例性的，可以将第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5以及第六晶体管M6置为氧化物型晶体管，将驱动晶体管M0、第一晶体管M1以及第七晶体管M7设置为LTPS型晶体管。这样通过将LTPS型晶体管与氧化物型晶体管，这两种制备晶体管的工艺进行结合制备低温多晶硅氧化物的LTPO像素驱动电路，可以使驱动晶体管M0的栅极的漏电流较小，以及使功耗较低。
在本公开实施例中，第一电源端VDD可以被配置为加载恒定的第一电源电压vdd，并且第一电源电压vdd一般为正值。以及，第二电源端VSS可以加载恒定的第二电源电压vss，并且第二电源电压vss一般可以为接地电压或为负值。在实际应用中，第一电源电压vdd和第二电源电压vss的具体数值可以根据实际应用环境来设计确定，在此不作限定。
以上仅是举例说明本发明实施例提供的像素电路中的各电路的具体结构，在具体实施时，上述电路的具体结构不限于本发明实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，这些均在本发明的保护范围之内，具体在此不作限定。
在本公开实施例中，如图3所示，本公开实施例中提供像素驱动电路的驱动方法，可以包括如下步骤：
S100、初始化阶段，第一控制电路响应于第一扫描信号端的信号，将驱动晶体管的第一极与第一节点导通；第二控制电路响应于第二扫描信号端和第三扫描信号端的信号，形成第一节点至第一初始化信号端的电流通路；第三控制电路响应于第一扫描信号端的信号，将第二初始化信号端的信号提供给驱动晶体管的栅极；
S200、阈值补偿阶段，第一控制电路响应于第一扫描信号端的信号，将驱动晶体管的第一极与第一节点导通；第二控制电路响应于第二扫描信号端和第三扫描信号端的信号，形成第一节点至第一初始化信号端的电流通路，使驱动晶体管的阈值电压输入第一节点；第三控制电路响应于第一扫描信号端的信号，将第二初始化信号端的信号提供给驱动晶体管的栅极；
S300、数据写入阶段，数据写入电路响应于第四扫描信号端的信号，将数据信号端的数据电压输入第一节点，使第一节点的电压由V1-Vth变化为Vda；由于第二存储电路的作用，使驱动晶体管的栅极的电压由V1变为Vda+Vth；V1代表所述第二初始电压信号端的第二初始化信号的电压值，Vth代表所述驱动晶体管M0的阈值电压，Vda代表所述数据信号端加载的数据电压；
S400、发光阶段，第三控制电路响应于发光控制信号端的信号，将第一电源端的信号提供给驱动晶体管的第一极；第二控制电路响应于第三扫描信号端的信号，将驱动晶体管的第二极与发光器件导通。
下面以图2所示的像素驱动电路为例，结合图4所示的信号时序图，对本公开实施例提供的像素驱动电路的工作过程作以描述。
在本公开实施例中，如图4所示，em代表发光控制信号端EM的发光控制信号，ss1代表第一扫描信号端SS1的第一扫描信号，ss2代表第二扫描信号端SS2的第二扫描信号，ss3代表第三扫描信号端SS3的第三扫描信号，ss4代表第四扫描信号端SS4的第四扫描信号，ss5代表第五扫描信号端SS5的第五扫描信号。
并且，选取一个显示帧中的初始化阶段T1、阈值补偿阶段T2、数据写入阶段T3以及发光阶段T4。
初始化阶段T1，初始化阶段T1还包括第一阶段T11以及第二阶段T12，其中，在第一阶段T11时，第一晶体管M1在第三扫描信号ss3的低电平控制下导通，第二晶体管M2在第二扫描信号ss2高电平的控制下导通，第三晶体管M3和第五晶体管M5在第一扫描信号ss1高电平的控制下导通，第四晶体管M4在第四扫描信号ss4低电平的控制下截止，第六晶体管M6在第五扫描信号ss5的低电平的控制下截止，第七晶体管M7在发光控制信号em的高电平的控制下截止。导通的第二晶体管M2将第一初始电压信号端Vinit1的第一初始化信号输入到发光器件L的阳极(即第三节点N3)，对发光器件L的阳极(即第三节点N3)进行初始化。导通的第一晶体管M1将输入到发光器件L(即第三节点N3)的第一初始化信号输入到驱动晶体管M0的第二极。导通的第三晶体管M3将驱动晶体管M0的第一极与第一节点N1导通。导通的第五晶体管M5将第二初始电压信号端Vinit2的第二初始化信号输入到驱动晶体管M0的栅极，对驱动晶体管M0的栅极进行初始化。并且导通的第一晶体管M1和导通的第二晶体管M2，在第三晶体管M3导通时，形成第一节点N1至第一初始化信号端Vinit1的电流通路。
在第二阶段T12时，第一晶体管M1在第三扫描信号ss3的高电平控制下截止，第二晶体管M2在第二扫描信号ss2高电平的控制下导通，第三晶体管M3和第五晶体管M5在第一扫描信号ss1高电平的控制下导通，第四晶体管M4在第四扫描信号ss4低电平的控制下截止，第六晶体管M6在第五扫描信号ss5的高电平的控制下导通，第七晶体管M7在发光控制信号em的高电平的控制下截止。导通的第二晶体管M2将第一初始电压信号端Vinit1的第一初始化信号输入到发光器件L的阳极(即第三节点N3)，对发光器件L的阳极(即第三节点N3)进行初始化。导通的第五晶体管M5将第二初始电压信号端Vinit2的第二初始化信号输入到驱动晶体管M0的栅极，对驱动晶体管M0的栅极进行初始化。导通的第六晶体管M6将第三初始电压信号端Vinit3的第三初始化信号输入到驱动晶体管M0的第一极(即第二节点N2)，对驱动晶体管M0的第一极(即第二节点N2)进行初始化。导通的第三晶体管M3将驱动晶体管M0的第一极与第一节点N1导通，从而使第三初始电压信号端Vinit3的第三初始化信号输入到第一节点N1，对第一节点N1进行初始化。其中，第三初始电压信号端Vinit3的第三初始化信号为高电压，由于该高电压输入到驱动晶体管M0的第一极，可以给驱动晶体管M0的第一极加载一个高电压，保证Vgs<Vth，从而保证了驱动晶体管M0处于开启状态。并且，Vgs代表驱动晶体管M0的栅极与第一极之间的电压差，Vth代表驱动晶体管M0的阈值电压。
阈值补偿阶段T2，第一晶体管M1在第三扫描信号ss3的低电平控制下导通，第二晶体管M2在第二扫描信号ss2高电平的控制下导通，第三晶体管M3和第五晶体管M5在第一扫描信号ss1高电平的控制下导通，第四晶体管M4在第四扫描信号ss4低电平的控制下截止，第六晶体管M6在第五扫描信号ss5的低电平的控制下截止，第七晶体管M7在发光控制信号em的高电平的控制下截止。导通的第五晶体管M5将第二初始电压信号端Vinit2的第二初始化信号输入到驱动晶体管M0的栅极，则驱动晶体管M0的栅极电压为V1。其中，V1代表第二初始电压信号端Vinit2的第二初始化信号的电压值。导通 的第三晶体管M3将驱动晶体管M0的第一极与第一节点N1导通。导通的第二晶体管M2将第一初始电压信号端Vinit1的第一初始化信号输入到发光器件L的阳极(即第三节点N3)。导通的第一晶体管M1将驱动晶体管M0的第二极与发光器件L的阳极(即第三节点N3)导通。并且，驱动晶体管M0仍处于开启状态，导通的第一晶体管M1和导通的第二晶体管M2，在第三晶体管M3导通时，形成第一节点N1至第一初始化信号端Vinit1的电流通路，使驱动晶体管M0的阈值电压Vth输入第一节点N1。当Vgs＝Vth时，驱动晶体管M0截止，此时第二节点N2的电压VN2等于V1与阈值电压Vth之差，即VN2＝V1-Vth，由于第三晶体管M3是导通的状态，所以第一节点N1的电压VN1＝VN2＝V1-Vth。
数据写入阶段T3，第一晶体管M1在第三扫描信号ss3的低电平控制下导通，第二晶体管M2在第二扫描信号ss2低电平的控制下截止，第三晶体管M3和第五晶体管M5在第一扫描信号ss1低电平的控制下截止，第四晶体管M4在第四扫描信号ss4高电平的控制下导通，第六晶体管M6在第五扫描信号ss5的低电平的控制下截止，第七晶体管M7在发光控制信号em的高电平的控制下截止。导通的第四晶体管M4将数据信号端DA加载的数据电压Vda提供给驱动晶体管M0，则第一节点N1的电压VN1由V1-Vth变化为Vda，且第一节点N1的电压变化量为ΔVN1＝Vda-V1+Vth。由于第二电容C2的存在，使驱动晶体管M0的栅极电压的耦合量为ΔVN1，则驱动晶体管M0栅极的电压由V1跳变为Vda+Vth。
发光阶段T4，第一晶体管M1在第三扫描信号ss3的低电平控制下导通，第二晶体管M2在第二扫描信号ss2低电平的控制下截止，第三晶体管M3和第五晶体管M5在第一扫描信号ss1低电平的控制下截止，第四晶体管M4在第四扫描信号ss4低电平的控制下截止，第六晶体管M6在第五扫描信号ss5的低电平的控制下截止，第七晶体管M7在发光控制信号em的低电平的控制下导通。导通的第七晶体管M7将第一电源端VDD与驱动晶体管M0的第一极(即第二节点N2)导通，导通的第一晶体管M1将驱动晶体管M0的第二 极与发光器件L的阳极(即第三节点N3)导通，使驱动晶体管M0产生驱动发光器件L发光的电流，则使第一电源端VDD、第七晶体管M7、驱动晶体管M0，发光器件L以及第二电源端VSS形成电流通路，从而驱动发光器件L发光。
在本公开实施例中，在T12阶段中，由于第六晶体管M6导通，第一晶体管M1截止，使第一晶体管M1阻断了第三初始电压信号端Vinit3、驱动晶体管M0、第二晶体管M2以及第一初始电压信号端Vinit1之间形成的电流通路，即阻断了短路通路，降低灼烧风险。
本公开实施例该提供了像素驱动电路另一些结构示意图，如图5所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不作赘述。
在本公开实施例中，可以使第三扫描信号端SS3与第五扫描信号端SS5为同一信号端。例如，如图5所示，第六晶体管M6的栅极与第三扫描信号端SS3耦接。示例性的，第一晶体管M1为P型晶体管，第六晶体管M6为N型晶体管。
在本公开实施例中，可以使第一扫描信号端SS1与第二扫描信号端SS2为同一信号端。例如，如图5所示，第三晶体管M3的栅极和第五晶体管M5的栅极与第二扫描信号端SS2耦接。这样可以降低信号走线的数量，降低布线难度。示例性的，第二晶体管M2和第五晶体管M5为N型晶体管。
图5所示的像素驱动电路对应的信号时序图，可以如图6所示。该实施例的驱动过程与前述像素驱动电路的驱动过程相似，因此该实施例的驱动过程可以参见前述像素驱动电路的驱动过程实施，重复之处在此不再赘述。
本公开实施例提供了像素驱动电路又一些结构示意图，如图7所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不作赘述。
在本公开实施例中，如图7和图8所示，驱动晶体管M0的第二极与发光器件L耦接，第二控制电路20与发光器件L耦接；第二控制电路20被配置 为响应于第二扫描信号端SS2和第三扫描信号端SS3的信号的共同控制，将第一初始化信号端Vinit1的信号提供给驱动晶体管M0的第二极。
在本公开实施例中，如图8所示，第二控制电路20包括第一晶体管M1以及第二晶体管M2；第一晶体管M1的栅极与第三扫描信号端SS3耦接，第一晶体管M1的第一极与驱动晶体管M0的第二极耦接，第一晶体管M1的第二极与第二晶体管M2的第一极耦接。第二晶体管M2的栅极与第二扫描信号端SS2耦接，第二晶体管M2的第二极与第一初始化信号端Vinit1耦接。
在本公开实施例中，如图8所示，第一晶体管M1为P型晶体管，第六晶体管M6为N型晶体管。
下面以图8所示的像素驱动电路为例，结合图4所示的信号时序图，对本公开实施例提供的像素驱动电路的工作过程作以描述。
在本公开实施例中，如图4所示，em代表发光控制信号端EM的发光控制信号，ss1代表第一扫描信号端SS1的第一扫描信号，ss2代表第二扫描信号端SS2的第二扫描信号，ss3代表第三扫描信号端SS3的第三扫描信号，ss4代表第四扫描信号端SS4的第四扫描信号，ss5代表第五扫描信号端SS5的第五扫描信号。
并且，选取一个显示帧中的初始化阶段T1、阈值补偿阶段T2、数据写入阶段T3以及发光阶段T4。
初始化阶段T1，初始化阶段T1还包括第一阶段T11以及第二阶段T12，其中，在第一阶段T11时，第一晶体管M1在第三扫描信号ss3的低电平控制下导通，第二晶体管M2在第二扫描信号ss2高电平的控制下导通，第三晶体管M3和第五晶体管M5在第一扫描信号ss1高电平的控制下导通，第四晶体管M4在第四扫描信号ss4低电平的控制下截止，第六晶体管M6在第五扫描信号ss5的低电平的控制下截止，第七晶体管M7在发光控制信号em的高电平的控制下截止。导通的第二晶体管M2将第一初始电压信号端Vinit1的第一初始化信号输入到发光器件L的阳极(即第三节点N3)，对发光器件L的阳极(即第三节点N3)进行初始化。导通的第一晶体管M1将输入到发光器件 L(即第三节点N3)的第一初始化信号输入到驱动晶体管M0的第二极。导通的第三晶体管M3将驱动晶体管M0的第一极与第一节点N1导通。导通的第五晶体管M5将第二初始电压信号端Vinit2的第二初始化信号输入到驱动晶体管M0的栅极，对驱动晶体管M0的栅极进行初始化。并且导通的第一晶体管M1和导通的第二晶体管M2，在第三晶体管M3导通时，形成第一节点N1至第一初始化信号端Vinit1的电流通路。
在第二阶段T12时，第一晶体管M1在第三扫描信号ss3的高电平控制下截止，第二晶体管M2在第二扫描信号ss2高电平的控制下导通，第三晶体管M3和第五晶体管M5在第一扫描信号ss1高电平的控制下导通，第四晶体管M4在第四扫描信号ss4低电平的控制下截止，第六晶体管M6在第五扫描信号ss5的高电平的控制下导通，第七晶体管M7在发光控制信号em的高电平的控制下截止。导通的第二晶体管M2将第一初始电压信号端Vinit1的第一初始化信号输入到发光器件L的阳极(即第三节点N3)，对发光器件L的阳极(即第三节点N3)进行初始化。导通的第五晶体管M5将第二初始电压信号端Vinit2的第二初始化信号输入到驱动晶体管M0的栅极，对驱动晶体管M0的栅极进行初始化。导通的第六晶体管M6将第三初始电压信号端Vinit3的第三初始化信号输入到驱动晶体管M0的第一极(即第二节点N2)，对驱动晶体管M0的第一极(即第二节点N2)进行初始化。导通的第三晶体管M3将驱动晶体管M0的第一极与第一节点N1导通，从而使第三初始电压信号端Vinit3的第三初始化信号输入到第一节点N1，对第一节点N1进行初始化。其中，第三初始电压信号端Vinit3的第三初始化信号为高电压，由于该高电压输入到驱动晶体管M0的第一极，可以给驱动晶体管M0的第一极加载一个高电压，保证Vgs<Vth，从而保证了驱动晶体管M0处于开启状态。并且，Vgs代表驱动晶体管M0的栅极与第一极之间的电压差，Vth代表驱动晶体管M0的阈值电压。
阈值补偿阶段T2，第一晶体管M1在第三扫描信号ss3的低电平控制下导通，第二晶体管M2在第二扫描信号ss2高电平的控制下导通，第三晶体管 M3和第五晶体管M5在第一扫描信号ss1高电平的控制下导通，第四晶体管M4在第四扫描信号ss4低电平的控制下截止，第六晶体管M6在第五扫描信号ss5的低电平的控制下截止，第七晶体管M7在发光控制信号em的高电平的控制下截止。导通的第五晶体管M5将第二初始电压信号端Vinit2的第二初始化信号输入到驱动晶体管M0的栅极，则驱动晶体管M0的栅极电压为V1。其中，V1代表第二初始电压信号端Vinit2的第二初始化信号的电压值。导通的第三晶体管M3将驱动晶体管M0的第一极与第一节点N1导通。导通的第二晶体管M2将第一初始电压信号端Vinit1的第一初始化信号输入到发光器件L的阳极(即第三节点N3)。导通的第一晶体管M1将驱动晶体管M0的第二极与发光器件L的阳极(即第三节点N3)导通。并且，驱动晶体管M0仍处于开启状态，导通的第一晶体管M1和导通的第二晶体管M2，在第三晶体管M3导通时，形成第一节点N1至第一初始化信号端Vinit1的电流通路，使驱动晶体管M0的阈值电压Vth输入第一节点N1。当Vgs＝Vth时，驱动晶体管M0截止，此时第二节点N2的电压VN2等于V1与阈值电压Vth之差，即VN2＝V1-Vth，由于第三晶体管M3是导通的状态，所以第一节点N1的电压VN1＝VN2＝V1-Vth。
数据写入阶段T3，第一晶体管M1在第三扫描信号ss3的低电平控制下导通，第二晶体管M2在第二扫描信号ss2低电平的控制下截止，第三晶体管M3和第五晶体管M5在第一扫描信号ss1低电平的控制下截止，第四晶体管M4在第四扫描信号ss4高电平的控制下导通，第六晶体管M6在第五扫描信号ss5的低电平的控制下截止，第七晶体管M7在发光控制信号em的高电平的控制下截止。导通的第四晶体管M4将数据信号端DA加载的数据电压Vda提供给驱动晶体管M0，则第一节点N1的电压VN1由V1-Vth变化为Vda，且第一节点N1的电压变化量为ΔVN1＝Vda-V1+Vth。由于第二电容C2的存在，使驱动晶体管M0的栅极电压的耦合量为ΔVN1，则驱动晶体管M0栅极的电压由V1跳变为Vda+Vth。
发光阶段T4，第一晶体管M1在第三扫描信号ss3的低电平控制下导通， 第二晶体管M2在第二扫描信号ss2低电平的控制下截止，第三晶体管M3和第五晶体管M5在第一扫描信号ss1低电平的控制下截止，第四晶体管M4在第四扫描信号ss4低电平的控制下截止，第六晶体管M6在第五扫描信号ss5的低电平的控制下截止，第七晶体管M7在发光控制信号em的低电平的控制下导通。导通的第七晶体管M7将第一电源端VDD与驱动晶体管M0的第一极(即第二节点N2)导通，导通的第一晶体管M1将驱动晶体管M0的第二极与发光器件L的阳极(即第三节点N3)导通，使驱动晶体管M0产生驱动发光器件L发光的电流，则使第一电源端VDD、第七晶体管M7、驱动晶体管M0，发光器件L以及第二电源端VSS形成电流通路，从而驱动发光器件L发光。
本公开实施例提供了像素驱动电路又一些结构示意图，如图9所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不作赘述。
在本公开实施例中，如图9所示，第一晶体管M1为N型晶体管，第六晶体管M6为N型晶体管。
在本公开实施例中，如图10所示，第三扫描信号端SS3的信号的相位与第五扫描信号端SS5的信号的相位相反。
下面以如图9所示的像素驱动电路为例，结合图10所示的信号时序图，对本公开实施例提供的像素驱动电路的工作过程作以描述。
在本公开实施例中，如图10所示，em代表发光控制信号端EM的发光控制信号，ss1代表第一扫描信号端SS1的第一扫描信号，ss2代表第二扫描信号端SS2的第二扫描信号，ss3代表第三扫描信号端SS3的第三扫描信号，ss4代表第四扫描信号端SS4的第四扫描信号，ss5代表第五扫描信号端SS5的第五扫描信号。
并且，选取一个显示帧中的初始化阶段T1、阈值补偿阶段T2、数据写入阶段T3以及发光阶段T4。
初始化阶段T1，初始化阶段T1还包括第一阶段T11以及第二阶段T12， 其中，在第一阶段T11时，第一晶体管M1在第三扫描信号ss3的高电平控制下导通，第二晶体管M2在第二扫描信号ss2高电平的控制下导通，第三晶体管M3和第五晶体管M5在第一扫描信号ss1高电平的控制下导通，第四晶体管M4在第四扫描信号ss4低电平的控制下截止，第六晶体管M6在第五扫描信号ss5的低电平的控制下截止，第七晶体管M7在发光控制信号em的高电平的控制下截止。导通的第二晶体管M2将第一初始电压信号端Vinit1的第一初始化信号输入到发光器件L的阳极(即第三节点N3)，对发光器件L的阳极(即第三节点N3)进行初始化。导通的第一晶体管M1将输入到发光器件L(即第三节点N3)的第一初始化信号输入到驱动晶体管M0的第二极。导通的第三晶体管M3将驱动晶体管M0的第一极与第一节点N1导通。导通的第五晶体管M5将第二初始电压信号端Vinit2的第二初始化信号输入到驱动晶体管M0的栅极，对驱动晶体管M0的栅极进行初始化。并且导通的第一晶体管M1和导通的第二晶体管M2，在第三晶体管M3导通时，形成第一节点N1至第一初始化信号端Vinit1的电流通路。
在第二阶段T12时，第一晶体管M1在第三扫描信号ss3的低电平控制下截止，第二晶体管M2在第二扫描信号ss2高电平的控制下导通，第三晶体管M3和第五晶体管M5在第一扫描信号ss1高电平的控制下导通，第四晶体管M4在第四扫描信号ss4低电平的控制下截止，第六晶体管M6在第五扫描信号ss5的高电平的控制下导通，第七晶体管M7在发光控制信号em的高电平的控制下截止。导通的第二晶体管M2将第一初始电压信号端Vinit1的第一初始化信号输入到发光器件L的阳极(即第三节点N3)，对发光器件L的阳极(即第三节点N3)进行初始化。导通的第五晶体管M5将第二初始电压信号端Vinit2的第二初始化信号输入到驱动晶体管M0的栅极，对驱动晶体管M0的栅极进行初始化。导通的第六晶体管M6将第三初始电压信号端Vinit3的第三初始化信号输入到驱动晶体管M0的第一极(即第二节点N2)，对驱动晶体管M0的第一极(即第二节点N2)进行初始化。导通的第三晶体管M3将驱动晶体管M0的第一极与第一节点N1导通，从而使第三初始电压信号端Vinit3 的第三初始化信号输入到第一节点N1，对第一节点N1进行初始化。其中，第三初始电压信号端Vinit3的第三初始化信号为高电压，由于该高电压输入到驱动晶体管M0的第一极，可以给驱动晶体管M0的第一极加载一个高电压，保证Vgs<Vth，从而保证了驱动晶体管M0处于开启状态。并且，Vgs代表驱动晶体管M0的栅极与第一极之间的电压差，Vth代表驱动晶体管M0的阈值电压。
阈值补偿阶段T2，第一晶体管M1在第三扫描信号ss3的高电平控制下导通，第二晶体管M2在第二扫描信号ss2高电平的控制下导通，第三晶体管M3和第五晶体管M5在第一扫描信号ss1高电平的控制下导通，第四晶体管M4在第四扫描信号ss4低电平的控制下截止，第六晶体管M6在第五扫描信号ss5的低电平的控制下截止，第七晶体管M7在发光控制信号em的高电平的控制下截止。导通的第五晶体管M5将第二初始电压信号端Vinit2的第二初始化信号输入到驱动晶体管M0的栅极，则驱动晶体管M0的栅极电压为V1。其中，V1代表第二初始电压信号端Vinit2的第二初始化信号的电压值。导通的第三晶体管M3将驱动晶体管M0的第一极与第一节点N1导通。导通的第二晶体管M2将第一初始电压信号端Vinit1的第一初始化信号输入到发光器件L的阳极(即第三节点N3)。导通的第一晶体管M1将驱动晶体管M0的第二极与发光器件L的阳极(即第三节点N3)导通。并且，驱动晶体管M0仍处于开启状态，导通的第一晶体管M1和导通的第二晶体管M2，在第三晶体管M3导通时，形成第一节点N1至第一初始化信号端Vinit1的电流通路，使驱动晶体管M0的阈值电压Vth输入第一节点N1。当Vgs＝Vth时，驱动晶体管M0截止，此时第二节点N2的电压VN2等于V1与阈值电压Vth之差，即VN2＝V1-Vth，由于第三晶体管M3是导通的状态，所以第一节点N1的电压VN1＝VN2＝V1-Vth。
数据写入阶段T3，第一晶体管M1在第三扫描信号ss3的高电平控制下导通，第二晶体管M2在第二扫描信号ss2低电平的控制下截止，第三晶体管M3和第五晶体管M5在第一扫描信号ss1低电平的控制下截止，第四晶体管 M4在第四扫描信号ss4高电平的控制下导通，第六晶体管M6在第五扫描信号ss5的低电平的控制下截止，第七晶体管M7在发光控制信号em的高电平的控制下截止。导通的第四晶体管M4将数据信号端DA加载的数据电压Vda提供给驱动晶体管M0，则第一节点N1的电压VN1由V1-Vth变化为Vda，且第一节点N1的电压变化量为ΔVN1＝Vda-V1+Vth。由于第二电容C2的存在，使驱动晶体管M0的栅极电压的耦合量为ΔVN1，则驱动晶体管M0栅极的电压由V1跳变为Vda+Vth。
发光阶段T4，第一晶体管M1在第三扫描信号ss3的高电平控制下导通，第二晶体管M2在第二扫描信号ss2低电平的控制下截止，第三晶体管M3和第五晶体管M5在第一扫描信号ss1低电平的控制下截止，第四晶体管M4在第四扫描信号ss4低电平的控制下截止，第六晶体管M6在第五扫描信号ss5的低电平的控制下截止，第七晶体管M7在发光控制信号em的低电平的控制下导通。导通的第七晶体管M7将第一电源端VDD与驱动晶体管M0的第一极(即第二节点N2)导通，导通的第一晶体管M1将驱动晶体管M0的第二极与发光器件L的阳极(即第三节点N3)导通，使驱动晶体管M0产生驱动发光器件L发光的电流，则使第一电源端VDD、第七晶体管M7、驱动晶体管M0，发光器件L以及第二电源端VSS形成电流通路，从而驱动发光器件L发光。
本公开实施例提供了像素驱动电路又一些结构示意图，如图11所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不作赘述。
在本公开实施例中，可以使第三扫描信号端SS3与第五扫描信号端SS5为同一信号端。例如，如图11示，第六晶体管M6的栅极与第三扫描信号端SS3耦接。
在本公开实施例中，可以使第一扫描信号端SS1与第二扫描信号端SS2为同一信号端。例如，如图11示，第三晶体管M3的栅极和第五晶体管M5的栅极与第二扫描信号端SS2耦接。这样可以降低信号走线的数量，降低布 线难度。
图11所示的像素驱动电路对应的信号时序图，可以如图6所示。该实施例的驱动过程与前述像素驱动电路的驱动过程相似，因此该实施例的驱动过程可以参见前述像素驱动电路的驱动过程实施，重复之处在此不再赘述。
本发明实施例还提供了显示装置，包括多个子像素；其中，各子像素包括上述像素驱动电路。该显示装置解决问题的原理与前述像素驱动电路相似，因此该显示装置的实施可以参见前述像素驱动电路的实施，重复之处在此不再赘述。
在具体实施时，在本发明实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。
以上仅是举例说明本发明实施例提供的像素电路中各模块的具体结构，在具体实施时，上述的具体结构不限于本发明实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (14)

  1. 一种像素驱动电路，其中，包括：
    发光器件；
    驱动晶体管，被配置为根据数据电压产生驱动所述发光器件发光的电流；
    第一控制电路，被配置为响应于第一扫描信号端的信号，将所述驱动晶体管的第一极与第一节点导通；
    第二控制电路，被配置为响应于第二扫描信号端和第三扫描信号端的信号，并在所述第一控制电路将所述驱动晶体管的第一极与所述第一节点导通时，形成所述第一节点至第一初始化信号端的电流通路，使所述驱动晶体管的阈值电压输入所述第一节点；
    数据写入电路，被配置为响应于第四扫描信号端的信号，将数据信号端的所述数据电压输入所述第一节点，使所述第一节点的电压由V1-Vth变化为Vda；
    第三控制电路，被配置为响应于第一扫描信号端的信号，将第二初始化信号端的信号提供给所述驱动晶体管的栅极，响应于第五扫描信号端的信号，将第三初始化信号端的信号提供给所述驱动晶体管的第一极，以及响应于发光控制信号端的信号，将第一电源端的信号提供给所述驱动晶体管的第一极；
    第一存储电路，被配置为保持所述第一节点与所述第一电源端之间的电压差稳定；
    第二存储电路，被配置为保持所述第一节点与所述驱动晶体管的栅极之间的电压差稳定，并在所述第一节点的电压由V1-Vth变化为Vda时，使所述驱动晶体管的栅极的电压由V1变化为Vda+Vth；V1代表所述第二初始电压信号端的第二初始化信号的电压值，Vth代表所述驱动晶体管的阈值电压，Vda代表所述数据信号端加载的数据电压。
  2. 如权利要求1所述的像素驱动电路，其中，所述驱动晶体管的第二极通过所述第二控制电路与所述发光器件耦接；
    所述第二控制电路被配置为响应于所述第三扫描信号端的信号，将所述驱动晶体管的第二极与所述发光器件导通，以及响应于所述第二扫描信号端的信号，将所述第一初始化信号端的信号提供给所述发光器件。
  3. 如权利要求2所述的像素驱动电路，其中，所述第二控制电路包括第一晶体管以及第二晶体管；
    所述第一晶体管的栅极与所述第三扫描信号端耦接，所述第一晶体管的第一极与所述发光器件耦接，所述第一晶体管的第二极与所述驱动晶体管的第二极耦接；
    所述第二晶体管的栅极与所述第二扫描信号端耦接，所述第二晶体管的第一极与所述发光器件耦接，所述第二晶体管的第二极与所述第一初始化信号端耦接。
  4. 如权利要求1所述的像素驱动电路，其中，所述驱动晶体管的第二极与所述发光器件耦接，所述第二控制电路与所述发光器件耦接；
    所述第二控制电路被配置为响应于所述第二扫描信号端和所述第三扫描信号端的信号的共同控制，将所述第一初始化信号端的信号提供给所述驱动晶体管的第二极。
  5. 如权利要求4所述的像素驱动电路，其中，所述第二控制电路包括第一晶体管以及第二晶体管；
    所述第一晶体管的栅极与所述第三扫描信号端耦接，所述第一晶体管的第一极与所述驱动晶体管的第二极耦接，所述第一晶体管的第二极与所述第二晶体管的第一极耦接；
    所述第二晶体管的栅极与所述第二扫描信号端耦接，所述第二晶体管的第二极与所述第一初始化信号端耦接。
  6. 如权利要求1-5任一项所述的像素驱动电路，其中，所述第一控制电路包括第三晶体管；
    所述第三晶体管的栅极与所述第一扫描信号端耦接，所述第三晶体管的第一极与所述驱动晶体管的第一极耦接，所述第三晶体管的第二极与所述第 一节点耦接。
  7. 如权利要求1-6任一项所述的像素驱动电路，其中，所述数据写入电路包括第四晶体管；
    所述第四晶体管的栅极与所述第四扫描信号端耦接，所述第四晶体管的第一极与所述数据信号端耦接，所述第四晶体管的第二极与所述第一节点耦接。
  8. 如权利要求1-7任一项所述的像素驱动电路，其中，所述第三控制电路包括第五晶体管、第六晶体管以及第七晶体管；
    所述第五晶体管的栅极与所述第一扫描信号端耦接，所述第五晶体管的第一极与所述驱动晶体管的栅极耦接，所述第五晶体管的第二极与所述第二初始电压信号端耦接；
    所述第六晶体管的栅极与所述第五扫描信号端耦接，所述第六晶体管的第一极与所述驱动晶体管的第一极耦接，所述第六晶体管的第二极与所述第三初始电压信号端耦接；
    所述第七晶体管的栅极与所述发光控制信号端耦接，所述第七晶体管的第一极与所述驱动晶体管的第一极耦接，所述第七晶体管的第二极与所述第一电源端耦接。
  9. 如权利要求1-8任一项所述的像素驱动电路，其中，所述第一存储子电路包括第一电容，所述第一电容的第一电极与所述第一电源端耦接，所述第一电容的第二电极与所述第一节点耦接；
    和/或，所述第二存储子电路包括：第二电容，所述第二电容的第一电极与所述第一节点耦接，所述第二电容的第二电极与所述驱动晶体管的栅极耦接。
  10. 如权利要求1-9任一项所述的像素驱动电路，其中，所述第三扫描信号端与所述第五扫描信号端为同一信号端。
  11. 如权利要求1-9任一项所述的像素驱动电路，其中，所述第三扫描信号端的信号的相位与所述第五扫描信号端的信号的相位相反。
  12. 如权利要求1-11任一项所述的像素驱动电路，其中，所述第一扫描信号端与所述第二扫描信号端为同一信号端。
  13. 一种显示装置，包括如权利要求1-12任一项所述的像素驱动电路。
  14. 一种如权利要求1-12任一项所述的像素驱动电路的驱动方法，包括：
    初始化阶段，所述第一控制电路响应于所述第一扫描信号端的信号，将所述驱动晶体管的第一极与第一节点导通；所述第二控制电路响应于所述第二扫描信号端和所述第三扫描信号端的信号，形成所述第一节点至第一初始化信号端的电流通路；所述第三控制电路响应于所述第一扫描信号端的信号，将所述第二初始化信号端的信号提供给所述驱动晶体管的栅极；
    阈值补偿阶段，所述第一控制电路响应于所述第一扫描信号端的信号，将所述驱动晶体管的第一极与第一节点导通；所述第二控制电路响应于所述第二扫描信号端和所述第三扫描信号端的信号，形成所述第一节点至第一初始化信号端的电流通路，使所述驱动晶体管的阈值电压输入所述第一节点；所述第三控制电路响应于所述第一扫描信号端的信号，将所述第二初始化信号端的信号提供给所述驱动晶体管的栅极；
    数据写入阶段，所述数据写入电路响应于第四扫描信号端的信号，将数据信号端的所述数据电压输入所述第一节点，使所述第一节点的电压由V1-Vth变化为Vda；由于第二存储电路的作用，使所述驱动晶体管的栅极的电压由V1变为Vda+Vth；V1代表所述第二初始电压信号端的第二初始化信号的电压值，Vth代表所述驱动晶体管的阈值电压，Vda代表所述数据信号端加载的数据电压；
    发光阶段，所述第三控制电路响应于所述发光控制信号端的信号，将所述第一电源端的信号提供给所述驱动晶体管的第一极；所述第二控制电路响应于所述第三扫描信号端的信号，将所述驱动晶体管的第二极与所述发光器件导通。
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