WO2020192382A1 - 像素驱动电路、显示装置及像素驱动方法 - Google Patents

像素驱动电路、显示装置及像素驱动方法 Download PDF

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Publication number
WO2020192382A1
WO2020192382A1 PCT/CN2020/077937 CN2020077937W WO2020192382A1 WO 2020192382 A1 WO2020192382 A1 WO 2020192382A1 CN 2020077937 W CN2020077937 W CN 2020077937W WO 2020192382 A1 WO2020192382 A1 WO 2020192382A1
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Prior art keywords
circuit
terminal
sub
transistor
switch sub
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PCT/CN2020/077937
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English (en)
French (fr)
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石领
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication of WO2020192382A1 publication Critical patent/WO2020192382A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements

Definitions

  • the embodiment of the present invention relates to a pixel driving circuit, a display device and a pixel driving method.
  • OLED Organic Light-Emitting Diode
  • the basic OLED driving circuit is 2T1C.
  • the value of the driving current (that is, the current flowing through the driving transistor) can determine the brightness produced by the OLED device.
  • the magnitude of the driving current is related to the threshold voltage of the driving transistor.
  • the characteristics of the transistors in each region of the display device will be different, that is, the threshold voltages of the driving transistors will be different. Therefore, when multiple display units in different regions write the same data signal, the driving transistors provide different driving currents to the OLED device, resulting in uneven brightness display of the display device.
  • At least one embodiment of the present disclosure provides a pixel driving circuit including: a charge storage sub-circuit, a driving sub-circuit, a first switching sub-circuit, a second switching sub-circuit, and a third switching sub-circuit.
  • the charge storage sub-circuit includes a first terminal, a second terminal, and a third terminal.
  • the first terminal of the charge storage sub-circuit is electrically connected to the first voltage terminal
  • the second terminal of the charge storage sub-circuit is electrically connected to the first terminal.
  • the third end of the charge storage sub-circuit is electrically connected to the second node;
  • the driving sub-circuit includes a first end, a second end, and a third end. The first end of the driving sub-circuit is connected to the second node.
  • the first node is electrically connected, the third end of the driving sub-circuit is electrically connected to the second node, and the driving sub-circuit is configured to control the flow through the second end and the third end for driving light emission
  • the first switch sub-circuit includes a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal.
  • the first terminal of the first switch sub-circuit is configured to be connected to the scan signal
  • the second end of the first switch sub-circuit is configured to be electrically connected to the data signal line to receive the data voltage
  • the third end of the first switch sub-circuit is electrically connected to the second node
  • the The fourth terminal of the first switch sub-circuit is electrically connected to the first node
  • the fifth terminal of the first switch sub-circuit is electrically connected to the third node
  • the second switch sub-circuit includes a first terminal and a second node.
  • the first terminal of the second switch sub-circuit is configured to be electrically connected to the first control signal line, and the second terminal of the second switch sub-circuit is connected to the The first voltage terminal is electrically connected to receive the first power supply voltage, the third terminal of the second switch sub-circuit is electrically connected to the third node, and the fourth terminal of the second switch sub-circuit is electrically connected to the second node
  • the fifth end of the second switch sub-circuit is configured to be electrically connected to the light emitting element;
  • the third switch sub-circuit includes a first end, a second end and a third end, and the third switch sub-circuit The first end is configured to be electrically connected to the second control signal line, the second end of the third switch sub-circuit is electrically connected to the third node, and the third end of the third switch sub-circuit is electrically connected to the driver The second end of the circuit is electrically connected.
  • the charge storage sub-circuit includes a first capacitor and a second capacitor; the first pole of the first capacitor serves as the first terminal of the charge storage sub-circuit; the second pole of the first capacitor Both the first pole of the second capacitor and the second capacitor serve as the second end of the charge storage sub-circuit; the second pole of the second capacitor serves as the third end of the charge storage sub-circuit.
  • the charge storage sub-circuit is configured to adjust the voltage of the first node through coupling according to the amount of voltage change of the second node.
  • the driver sub-circuit includes a first transistor; the gate, first pole, and second pole of the first transistor serve as the first terminal, the second terminal, and the third terminal of the driver sub-circuit, respectively .
  • the first switch sub-circuit is configured to write the data voltage to the second node and write the voltage of the third node to the second node in response to the scan signal from the scan signal line.
  • the first node is configured to write the data voltage to the second node and write the voltage of the third node to the second node in response to the scan signal from the scan signal line. The first node.
  • the second switch sub-circuit is configured to write the first power supply voltage from the first voltage terminal to the third node in response to a first control signal from the first control signal line , And transmit the voltage of the second node to the light-emitting element.
  • the third switch sub-circuit is configured to write the voltage of the third node to the second end of the driving sub-circuit in response to a second control signal from the second control signal line.
  • the first power supply voltage is configured to be greater than or equal to the sum of the data voltage and the threshold voltage of the first transistor.
  • the charge storage sub-circuit includes a first capacitor and a second capacitor;
  • the driving sub-circuit includes a first transistor;
  • the first switch sub-circuit includes a second transistor and a third transistor, and the second The switch sub-circuit includes a fourth transistor and a fifth transistor,
  • the third switch sub-circuit includes a sixth transistor;
  • the first pole of the first capacitor serves as the first terminal of the charge storage sub-circuit;
  • the first capacitor The second pole of the second capacitor and the first pole of the second capacitor serve as the second terminal of the charge storage sub-circuit;
  • the second pole of the second capacitor serves as the third terminal of the charge storage sub-circuit;
  • the gate, the first pole, and the second pole of the first transistor serve as the first terminal, the second terminal, and the third terminal of the driving sub-circuit, respectively;
  • the poles are electrically connected to each other and serve as the first terminal of the first switch sub-circuit;
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are all N-type transistors.
  • the pixel driving circuit further includes the light-emitting element, and the light-emitting element is electrically connected to the fifth terminal of the second switch sub-circuit.
  • the first switch sub-circuit includes a second transistor and a third transistor; the gate of the second transistor and the gate of the third transistor are electrically connected to each other and serve as the first switch.
  • the first terminal of the circuit; the first pole and the second pole of the second transistor respectively serve as the second terminal and the third terminal of the first switch sub-circuit; the first pole and the second pole of the third transistor They respectively serve as the fourth terminal and the fifth terminal of the first switch sub-circuit.
  • the second switch sub-circuit includes a fourth transistor and a fifth transistor; the gate of the fourth transistor is electrically connected to the gate of the fifth transistor, and serves as the second switch sub-circuit
  • the first terminal and the second terminal of the fourth transistor are respectively used as the second terminal and the third terminal of the second switch sub-circuit; the first terminal and the second terminal of the fifth transistor are respectively As the fourth terminal and the fifth terminal of the second switch sub-circuit.
  • the third switch sub-circuit includes a sixth transistor; the gate, first pole, and second pole of the sixth transistor serve as the first terminal and the second terminal of the third switch sub-circuit, respectively , The third end.
  • At least one embodiment of the present disclosure further provides a display device including a plurality of pixel units, and at least one pixel unit includes the aforementioned pixel driving circuit.
  • the display device further includes the scan signal line, the first control signal line, the second control signal line, and the data signal line, the scan signal line and the first switch
  • the first end of the sub-circuit is electrically connected, the first control signal line is electrically connected to the first end of the second switch sub-circuit, and the second control signal line is electrically connected to the first end of the third switch sub-circuit Electrically connected, the data signal line is electrically connected to the second end of the first switch sub-circuit.
  • At least one embodiment of the present disclosure further provides a pixel driving method, which is applied to the above pixel driving circuit, including: in a reset phase, turning on the first switching sub-circuit and the second switching sub-circuit, and turning off the third
  • the switch sub-circuit writes the first power supply voltage from the first voltage terminal into the first node, and transmits the initial signal from the data signal line to the second node; in the data writing and compensation stage , Turning on the first switching sub-circuit and the third switching sub-circuit, and turning off the second switching sub-circuit, transmitting the data signal from the data signal line to the second node, and responding to the The driver sub-circuit compensates; in the light-emitting phase, the second switch sub-circuit and the third switch sub-circuit are turned on, and the first switch sub-circuit is turned off.
  • the charge storage sub-circuit is based on the second node
  • the amount of voltage change adjusts the voltage of the first node through coupling, and the driving sub-circuit applies
  • the charge storage sub-circuit changes according to the voltage change of the second node.
  • Adjusting the voltage of the first node through coupling includes: the gate voltage of the first transistor jumps with the voltage of the second electrode, the jump amount of the gate voltage ⁇ Vg and the voltage of the second electrode
  • the jump variable ⁇ Vs satisfies: Wherein, C1 represents the capacitance value of the first capacitor, and C2 represents the capacitance value of the second capacitor.
  • the voltage of the gate of the first transistor in the light-emitting stage is Wherein, Vth is the threshold voltage of the first transistor.
  • Figure 1 is a schematic diagram of the circuit principle of an OLED drive circuit
  • 2A is a schematic block diagram of a pixel driving circuit provided by an embodiment of the application.
  • FIG. 2B is a circuit diagram of a specific implementation example of the pixel driving circuit shown in FIG. 2A;
  • 3A is a schematic flowchart of a pixel driving method according to an embodiment of the application.
  • 3B is a schematic flowchart of a pixel driving method according to another embodiment of the application.
  • FIG. 4 is a signal timing diagram of a pixel driving circuit provided by an embodiment of the application.
  • FIG. 5 is a schematic diagram of the compensation effect of the pixel driving circuit and the pixel driving method provided by the embodiments of the application;
  • FIG. 6 is a schematic diagram of a display device provided by an embodiment of the disclosure.
  • FIG. 1 is a schematic diagram of an OLED drive circuit (2T1C).
  • Gate in Figure 1 represents a scan signal line (also called a gate signal line or gate line)
  • Data represents a data signal line (also called a data line)
  • Sw-T represents a switching transistor
  • Dr- T represents the driving TFT (Thin Film Transistor)
  • Vg and Vs represent the gate and source of Dr-T respectively
  • VDD represents the first voltage terminal connected to the drive transistor
  • VSS represents the second voltage connected to the diode element
  • Cst represents the storage capacitor.
  • the driving current Id flowing through the diode element in Figure 1 can be expressed as:
  • k is the conductivity parameter of the driving TFT
  • Vgs is the voltage difference between the gate and the source of the driving TFT
  • Vth is the threshold voltage of the driving TFT.
  • the magnitude of the drive current Id is related to Vth.
  • Vth the magnitude of Vth
  • the drive current Id is also unstable, thereby reducing This leads to uneven brightness of the display device.
  • the pixel driving circuit, display device, and pixel driving method provided by the present application aim to solve the above technical problems in the prior art.
  • the pixel driving circuit includes: a charge storage sub-circuit 1, a driving sub-circuit 2, a first switching sub-circuit 3, a second Switch sub-circuit 4 and third switch sub-circuit 5.
  • the charge storage sub-circuit 1 includes a first terminal 11, a second terminal 12, and a third terminal 13.
  • the first terminal 11 of the charge storage sub-circuit 1 is electrically connected to the first voltage terminal VDD, and the second terminal 12 is electrically connected to the first node A.
  • the third terminal 13 is electrically connected to the second node B.
  • the charge storage sub-circuit 1 is configured to adjust the voltage of the first node A through coupling according to the amount of voltage change of the second node B.
  • the driver sub-circuit 2 includes a first terminal 21, a second terminal 22, and a third terminal 23.
  • the first terminal of the driver sub-circuit 2 is electrically connected to the first node A, and the third terminal 23 is electrically connected to the second node B;
  • the circuit 2 is configured to control the driving current flowing through the second terminal 22 and the third terminal 23 for driving the light emitting element 6 to emit light.
  • the first switch sub-circuit 3 includes a first terminal 31, a second terminal 32, a third terminal 33, a fourth terminal 34, and a fifth terminal 35.
  • the first terminal 31 of the first switch sub-circuit 3 is configured to be connected to the scanning signal line Gate Electrically connected to receive the scan signal Gate
  • the second end 32 is configured to be electrically connected to the data signal line Data to receive the data signal Data
  • the third end 33 is electrically connected to the second node B
  • the fourth end 34 is electrically connected to the first node A
  • the fifth terminal 35 is electrically connected to the third node C.
  • the first switch sub-circuit 3 is configured to transmit the signal from the data signal line Data (such as the data signal Data and the initial signal Vref later) to the second node B in response to the scan signal Gate, and transfer the third node C The voltage is written to the first node A.
  • Data such as the data signal Data and the initial signal Vref later
  • the second switch sub-circuit 4 includes a first terminal 41, a second terminal 42, a third terminal 43, a fourth terminal 44, and a fifth terminal 45.
  • the first terminal 41 of the second switch sub-circuit 4 is configured to interact with the first control signal
  • the line EM2 is electrically connected to receive the first control signal EM2
  • the second terminal 42 is electrically connected to the first voltage terminal VDD
  • the third terminal 43 is electrically connected to the third node C
  • the fourth terminal 44 is electrically connected to the second node B.
  • the five terminal 45 is configured to be electrically connected to the light emitting element 6.
  • the second switch sub-circuit 4 is configured to write the first power supply voltage from the first voltage terminal VDD to the third node C and write the voltage of the second node B to the light emitting element 6 in response to the first control signal EM2 The first electrode.
  • the third switch sub-circuit 5 includes a first terminal 51, a second terminal 52, and a third terminal 53, and the first terminal 51 of the third switch sub-circuit 5 is configured to be electrically connected to the second control signal line EM1 to receive the second control signal EM1, the second terminal 52 is electrically connected to the third node C, and the third terminal 53 is electrically connected to the second terminal 22 of the driving sub-circuit 2.
  • the third switch sub-circuit 5 is configured to write the voltage of the third node C into the second terminal 22 of the driving sub-circuit 2 in response to the second control signal EM1.
  • the symbol Gate can represent both the scan signal line and the scan signal
  • the symbol EM2 can represent both the first control signal line and the first control signal
  • the symbol EM1 is both It can represent the second control signal line and the second control signal.
  • the symbol Data can represent both the data signal line and the data signal.
  • the symbol VDD can represent both the first voltage terminal and the first power supply voltage.
  • the symbol VSS can represent both the second voltage terminal and the second power supply voltage.
  • FIG. 2B is a circuit diagram of a specific implementation example of the pixel driving circuit shown in FIG. 2A.
  • the charge storage sub-circuit 1 includes a first capacitor C1 and a second capacitor C2; the first pole of the first capacitor C1 serves as the first terminal 11 of the charge storage sub-circuit 1, and the first voltage terminal VDD Electrically connected; the second pole of the first capacitor C1 and the first pole of the second capacitor C2 are both used as the second terminal 12 of the charge storage sub-circuit 1, electrically connected to the first node A; the second pole of the second capacitor C2 is used as The third terminal 13 of the charge storage sub-circuit 1 is electrically connected to the second node B.
  • the driving sub-circuit 2 includes a first transistor T1 (that is, a driving transistor); the gate, first pole, and second pole of the first transistor T1 serve as the first terminal 21, the second terminal 22, and the second terminal of the driving sub-circuit 2 respectively.
  • the three terminals 23 are electrically connected to the first node A, the second node B, and the third terminal 53 of the third switch sub-circuit 5 respectively.
  • the first switch sub-circuit 3 includes a second transistor T2 and a third transistor T3; the gate of the second transistor T2 and the gate of the third transistor T3 are both used as the first terminal 31 of the first switch sub-circuit 3, and both are connected to The scan signal line Gate is electrically connected; the first pole and the second pole of the second transistor T2 serve as the second terminal 32 and the third terminal 33 of the first switch sub-circuit 3, respectively, and are electrically connected to the data signal line Data and the second node B. Connected; the first pole and the second pole of the third transistor T3 are respectively used as the fourth terminal 34 and the fifth terminal 35 of the first switch sub-circuit 3, and are electrically connected to the first node A and the third node C, respectively.
  • the second switch sub-circuit 4 includes a fourth transistor T4 and a fifth transistor T5; the gate of the fourth transistor T4 and the gate of the fifth transistor both serve as the first terminal 41 of the second switch sub-circuit 4, and both are connected to the first terminal 41 of the second switch sub-circuit 4.
  • a control signal line EM2 is electrically connected; the first pole and the second pole of the fourth transistor T4 serve as the second terminal 42 and the third terminal 43 of the second switch sub-circuit 4, respectively, and are respectively connected to the first voltage terminal and the third node C Electrically connected; the first pole and the second pole of the fifth transistor T5 are respectively used as the fourth terminal 44 and the fifth terminal 45 of the second switch sub-circuit 4, and are respectively electrically connected to the second node B and the light emitting element 6 (such as OLED) .
  • the light emitting element 6 is electrically connected to the second voltage terminal (VSS terminal).
  • the third switch sub-circuit 5 includes a sixth transistor T6; the gate, first pole, and second pole of the sixth transistor T6 serve as the first terminal 51, the second terminal 52, and the third terminal of the third switch sub-circuit 5, respectively.
  • the terminal 53 is electrically connected to the second control signal line EM1, the third node C, and the second terminal 22 of the driving sub-circuit 2 respectively.
  • the light-emitting element 6 may include an organic light-emitting diode (OLED), which may be of various types, such as top-emission, bottom-emission, double-side emission, etc., and can emit red, green, blue, or white light.
  • OLED organic light-emitting diode
  • the embodiment does not limit this.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • thin film transistors are used as examples for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • the transistors in the pixel driving circuit shown in FIG. 2B are all N-type transistors as an example.
  • the first electrode may be the drain and the second electrode may be the source.
  • the embodiments of the present disclosure include, but are not limited to, the configuration of FIG. 2B.
  • the transistors in the pixel driving circuit can also be mixed with P-type transistors and N-type transistors, and only need to select at the same time.
  • the polarity of each terminal of the type of transistor can be connected according to the port polarity of the corresponding transistor in the embodiment of the present disclosure.
  • first node A, the second node B, and the third node C do not necessarily represent actual components, but rather represent the junction of related electrical connections in the circuit diagram.
  • the embodiment of the present application also provides a pixel driving method, which can be applied to the pixel driving circuit provided in the embodiment of the present application.
  • FIG. 3A is a schematic flowchart of a pixel driving method provided by at least one embodiment of the present disclosure.
  • the pixel driving method at least includes: step S201, in the reset phase, turning on the first switch sub-circuit and the second switch Sub-circuit, and close the third switch sub-circuit, write the first power supply voltage from the first voltage terminal to the first node, and transmit the initial signal from the data signal line to the second node; step S202, In the data writing and compensation phase, the first switch sub-circuit and the third switch sub-circuit are turned on, and the second switch sub-circuit is turned off, the data voltage from the data signal line is transmitted to the second node, and the The driving sub-circuit performs compensation; step S203, during the light-emitting phase, the second switching sub-circuit and the third switching sub-circuit are turned on, and the first switching sub-circuit is turned off, and the charge storage sub-circuit is based on the voltage of the second node The amount of change adjust
  • FIG. 3B is a flowchart of a pixel driving method provided by another embodiment of the present disclosure. As shown in FIG. 2B and FIG. 3B, the pixel driving method includes the following steps S301-S303.
  • the first switch sub-circuit 3 and the second switch sub-circuit 4 in the pixel drive circuit are both turned on when they receive a first level signal through their first terminals, and will pass through the second switch sub-circuit.
  • the first power supply voltage VDD received by the second terminal of the circuit 4 and the initial signal Vref received through the second terminal of the first switch sub-circuit 3 are output to the first node A and the second node B, respectively.
  • the second switch sub-circuit 4 is turned off when receiving the second level signal through its first terminal, the first switch sub-circuit 3 and the third switch sub-circuit in the pixel drive circuit 5.
  • the first switch sub-circuit 3 outputs the data signal Data received through its second terminal to the second node B .
  • the pixel driving circuit compensates the threshold voltage Vth of the driving sub-circuit 2 according to the data signal Data.
  • the first switch sub-circuit 3 is turned off when receiving a second level signal through its first end, and the second switch sub-circuit 4 and the third switch sub-circuit 5 receive signals through their respective first ends.
  • the signal reaches the first level, it is respectively turned on and maintained in the on state, so that the driving sub-circuit 2 in the pixel driving circuit outputs a driving current to the light-emitting element.
  • the first level signal is a high level signal and the second level signal is a low level signal; or the first level signal is a low level signal and the second level signal is a high level signal.
  • each transistor is an N-type TFT as an example
  • the pixel driving method provided in the embodiment of the present application will be exemplarily described. .
  • the scan signal Gate and the first control signal EM2 are both at a logic high potential, and the scan signal line Gate is directed to the second transistor T2 and the second transistor T2 in the first switch sub-circuit 3, respectively.
  • the gate of the three transistor T3 inputs a high-level signal
  • the first control signal line EM2 inputs a high-level signal to the gates of the fourth transistor T4 and the fifth transistor T5 in the second switch sub-circuit 4, and the transistors T2 to T5 It is turned on under the control of the received high-level signal.
  • the second control signal EM1 is at a logic low potential, and the second control signal line EM1 inputs a low level signal to the gate of the sixth transistor T6 in the third switch sub-circuit 5, and the sixth transistor T6 remains off, thereby ensuring the light emitting element OLED does not emit light.
  • the power supply voltage VDD provided by the first voltage terminal is transmitted to the first node A through the fourth transistor T4 and the third transistor T3, and is further transmitted to the driving sub-circuit 2 electrically connected to the first node A
  • the gate of the first transistor T1 is reset, and the gate voltage Vg of the first transistor T1 becomes VDD.
  • the initial signal Vref provided by the data signal line Data is transmitted to the first transistor T2 through the second transistor T2.
  • the second node B is then transmitted to the anode of the OLED electrically connected to the second node B, thereby resetting the anode of the OLED.
  • the first control signal EM2 becomes a logic low potential, and the first control signal line EM2 inputs low-level signals to the gates of the fourth transistor T4 and the fifth transistor T5, respectively, and the fourth transistor T4 and The fifth transistor T5 is turned off under the control of the received low-level signal, thereby ensuring that the light-emitting element OLED does not emit light.
  • the scan signal Gate and the second control signal EM1 are both at a logic high potential.
  • the scan signal line Gate inputs a high level signal to the gates of the second transistor T2 and the third transistor T3, respectively, and the second transistor T2 and the third transistor T3 are receiving Under the control of the received high-level signal, the second control signal line EM1 inputs a high-level signal to the gate of the sixth transistor T6, and the sixth transistor T6 is under the control of the received high-level signal. Conduction.
  • the data signal (data voltage) Vdata provided by the data signal line Data is transmitted to the second node B through the second transistor T2, that is, the second electrode of the first transistor T1 connected to the second node B, and the source of the first transistor T1
  • the voltage Vs becomes Vdata.
  • the conditions for N-type TFT to turn on are:
  • the precondition can also be expressed as:
  • the first power supply voltage VDD is configured to be greater than or equal to the sum of the data voltage Vdata and the threshold voltage of the first transistor T1.
  • the scan signal Gate becomes a logic low potential, and the scan signal line Gate inputs a low level signal to the gates of the second transistor T2 and the third transistor T3, respectively, and the second transistor T2 and the third transistor T3 are both disconnected.
  • the voltage stored in the second capacitor C2 is maintained at Vth.
  • the second control signal EM1 is maintained at a logic high potential, the second control signal line EM1 continues to input a high-level signal to the gate of the sixth transistor T6, and the sixth transistor T6 maintains a conductive state under the received high-level signal;
  • the first control signal EM2 becomes a logic high potential.
  • the first control signal line EM2 inputs a high level signal to the gates of the fourth transistor T4 and the fifth transistor T5, respectively.
  • the fourth transistor T4 and the fifth transistor T5 receive It is turned on under the control of a high level signal.
  • T4, T5 and T6 are all turned on, the source voltage Vs of the first transistor T1 jumps, and the jump variable is:
  • Vel represents the voltage of the second node B in the light-emitting phase, for example, the anode voltage of the light-emitting element OLED. Vel is related to the internal resistance of the light-emitting element OLED and has nothing to do with the threshold voltage of the first transistor T1.
  • the compensation effect on Vth is shown in FIG. 5.
  • the abscissa of FIG. 5 represents the threshold voltage Vth (unit V, namely volt) of the driving transistor T1, and the ordinate represents Drive current Id (unit is ⁇ A, namely microampere).
  • Vth unit V, namely volt
  • Id Drive current
  • the compensation range of Vth in the embodiment of this application is 0-5.5V, which is larger than the compensation range of the existing pixel driving circuit or pixel compensation circuit (usually 1V).
  • the embodiment of this application uses OLED driving
  • the current fluctuation ⁇ Id ⁇ 5% has a significant advantage over the compensation effect of the existing pixel driving circuit or pixel compensation circuit.
  • Using the pixel driving circuit and pixel driving method provided by the embodiments of the present application can effectively compensate the threshold voltage Vth of the driving transistor, and has a better compensation effect, which can reduce the impact of the instability of the threshold voltage Vth on the display brightness Influence, make the display brightness more stable and uniform, thereby improving the display quality of the display screen.
  • the gate of the driving transistor can be reset by the power supply voltage VDD of the first voltage terminal, and the anode of the OLED can be reset by the initial voltage Vref input by the data signal line Data, thereby reducing The number of driving signals is reduced, and the reset process is simplified.
  • An embodiment of the present application also provides a display device, including the pixel driving circuit provided in the embodiment of the present application.
  • FIG. 6 is a schematic block diagram of a display device provided by an embodiment of the disclosure.
  • the display device 20 includes a display panel 2000, a gate driver 2010, a timing controller 2020, and a data driver 2030.
  • the display panel 2000 includes a plurality of scan lines GL and a plurality of data lines DL.
  • the gate driver 2010 is used to drive a plurality of scan lines GL;
  • the data driver 2030 is used to drive a plurality of data lines DL;
  • the timing controller 2020 is used to process image data RGB input from the outside of the display device 20, and provide processing information to the data driver 2030
  • the image data RGB and the scan control signal GCS and the data control signal DCS are output to the gate driver 2010 and the data driver 2030 to control the gate driver 2010 and the data driver 2030.
  • the scan line GL may include the aforementioned scan signal line Gate, the first control signal line EM2, and the second control signal line EM1.
  • the data line GL may include the aforementioned data signal line Date.
  • the display panel 2000 includes a plurality of pixel units P, and the pixel units P include the pixel driving circuit provided in any of the above embodiments, for example, including the pixel driving circuit as shown in FIGS. 2A-2B.
  • the pixel unit P is disposed in the intersection area of the scan line GL and the data line DL.
  • each pixel unit P is connected to three scan lines GL (respectively provide scan signal Gate, first control signal EM2 and second control signal EM1), one data line DL (provide data signal Vdata), for providing first power A first voltage line for voltage and a second voltage line for supplying a second power supply voltage.
  • the first voltage line or the second voltage line may be replaced with a corresponding plate-shaped common electrode (such as a common anode or a common cathode). It should be noted that only a part of the pixel unit P, the scan line GL, and the data line DL are shown in FIG. 6.
  • the gate driver 2010 provides a plurality of gate signals to a plurality of scan lines GL according to a plurality of scan control signals GCS from the timing controller 2020.
  • the multiple strobe signals include scan signals and reset signals. These signals are supplied to each pixel unit P through a plurality of scan lines GL.
  • the data driver 2030 uses a reference gamma voltage to convert digital image data RGB input from the timing controller 2020 into data signals according to a plurality of data control signals DCS from the timing controller 2020.
  • the data driver 2030 provides the converted data signals to the plurality of data lines DL.
  • the timing controller 2020 processes externally input image data RGB to match the size and resolution of the display panel 2000, and then provides the processed image data to the data driver 2030.
  • the timing controller 2020 uses synchronization signals (such as dot clock DCLK, data enable signal DE, horizontal synchronization signal Hsync, and vertical synchronization signal Vsync) input from the outside of the display device 20 to generate multiple scan control signals GCS and multiple data control signals DCS .
  • the timing controller 2020 provides the generated scan control signal GCS and data control signal DCS to the gate driver 2010 and the data driver 2030, respectively, for control of the gate driver 2010 and the data driver 2030.
  • the data driver 2030 may be connected to a plurality of data lines DL to provide data signals; at the same time, it may also be connected to a plurality of first voltage lines and a plurality of second voltage lines to respectively provide a first voltage and a second voltage.
  • the gate driver 2010 and the data driver 2030 may be implemented as semiconductor chips.
  • the display device 20 may also include other components, such as a signal decoding circuit, a voltage conversion circuit, etc., for example, these components may use existing conventional components, which will not be described in detail here.
  • the display panel 2000 can be applied to any products or components with display functions, such as e-books, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, and navigators.
  • display functions such as e-books, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, and navigators.

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Abstract

一种像素驱动电路、显示装置及像素驱动方法。该像素驱动电路包括：电荷存储子电路(1)、驱动子电路(2)、第一开关子电路(3)、第二开关子电路(4)和第三开关子电路(5)；电荷存储子电路(1)的第一端(11)与第一电压端(VDD)电连接，第二端(12)与第一节点(A)电连接，第三端(13)与第二节点(B)电连接；驱动子电路(2)的第一端(21)与第一节点(A)电连接，第三端(23)与第二节点(B)电连接；第一开关子电路(3)的第一端(31)与扫描信号线(Gate)电连接，第二端(32)与数据信号线(Data)电连接，第三端(33)与第二节点(B)电连接，第四端(34)与第一节点(A)电连接，第五端(35)与第三节点(C)电连接。该像素驱动电路能够有效地对驱动晶体管的阈值电压进行补偿，具有较好的补偿效果。

Description

像素驱动电路、显示装置及像素驱动方法
本申请要求于2019年3月28日递交的中国专利申请第201910243634.2的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本发明的实施例涉及一种像素驱动电路、显示装置及像素驱动方法。
背景技术
有机发光二极管(OLED，Organic Light-Emitting Diode)作为一种电流型发光器件已越来越多地被应用于新一代显示装置中。
基础的OLED驱动电路为2T1C，驱动电流(即流过驱动晶体管的电流)的值可决定OLED器件所产生的亮度，驱动电流的大小与驱动晶体管的阈值电压有关。
由于晶体管的制程因素，在显示装置各区域的晶体管的特性会存在差异，即驱动晶体管的阈值电压存在差异。因此，当不同区域的多个显示单元写入相同的数据信号时，驱动晶体管提供给OLED器件不同的驱动电流，导致显示装置亮度显示不均。
发明内容
本公开至少一实施例提供一种像素驱动电路，包括：电荷存储子电路、驱动子电路、第一开关子电路、第二开关子电路和第三开关子电路。所述电荷存储子电路包括第一端、第二端和第三端，所述电荷存储子电路的第一端与第一电压端电连接，所述电荷存储子电路的第二端与第一节点电连接，所述电荷存储子电路的第三端与第二节点电连接；所述驱动子电路包括第一端、第二端和第三端，所述驱动子电路的第一端与所述第一节点电连接，所述驱动子电路的第三端与所述第二节点电连接，所述驱动子电路配置为控制流经所述第二端和所述第三端的用于驱动发光元件发光的驱动电流；所述第一开 关子电路包括第一端、第二端、第三端、第四端和第五端，所述第一开关子电路的第一端配置为与扫描信号线电连接，所述第一开关子电路的第二端配置为与数据信号线电连接以接收数据电压，所述第一开关子电路的第三端与所述第二节点电连接，所述第一开关子电路的第四端与所述第一节点电连接，所述第一开关子电路的第五端与第三节点电连接；所述第二开关子电路包括第一端、第二端、第三端、第四端和第五端，所述第二开关子电路的第一端配置为与第一控制信号线电连接，所述第二开关子电路的第二端与所述第一电压端电连接以接收第一电源电压，所述第二开关子电路的第三端与所述第三节点电连接，所述第二开关子电路的第四端与所述第二节点电连接，所述第二开关子电路的第五端配置为与发光元件电连接；所述第三开关子电路包括第一端、第二端和第三端，所述第三开关子电路的第一端配置为与第二控制信号线电连接，所述第三开关子电路的第二端与所述第三节点电连接，所述第三开关子电路的第三端与所述驱动子电路的第二端电连接。
在一些示例中，所述电荷存储子电路包括第一电容和第二电容；所述第一电容的第一极作为所述电荷存储子电路的第一端；所述第一电容的第二极和所述第二电容的第一极均作为所述电荷存储子电路的第二端；所述第二电容的第二极作为所述电荷存储子电路的第三端。
在一些示例中，所述电荷存储子电路配置为根据所述第二节点的电压变化量通过耦合调整所述第一节点的电压。
在一些示例中，所述驱动子电路包括第一晶体管；所述第一晶体管的栅极、第一极、第二极分别作为所述驱动子电路的第一端、第二端、第三端。
在一些示例中，所述第一开关子电路配置为响应于来自所述扫描信号线的扫描信号将所述数据电压写入所述第二节点，并将所述第三节点的电压写入所述第一节点。
在一些示例中，所述第二开关子电路配置为响应于来自所述第一控制信号线的第一控制信号将来自所述第一电压端的所述第一电源电压写入所述第三节点，并将所述第二节点的电压传输至所述发光元件。
在一些示例中，所述第三开关子电路配置为响应于来自所述第二控制信号线的第二控制信号将第所述第三节点的电压写入所述驱动子电路的第二端。
在一些示例中，所述第一电源电压配置为大于等于所述数据电压与所述第一晶体管的阈值电压之和。
在一些示例中，所述电荷存储子电路包括第一电容和第二电容；所述驱动子电路包括第一晶体管；所述第一开关子电路包括第二晶体管和第三晶体管，所述第二开关子电路包括第四晶体管和第五晶体管，所述第三开关子电路包括第六晶体管；所述第一电容的第一极作为所述电荷存储子电路的第一端；所述第一电容的第二极和所述第二电容的第一极均作为所述电荷存储子电路的第二端；所述第二电容的第二极作为所述电荷存储子电路的第三端；所述第一晶体管的栅极、第一极、第二极分别作为所述驱动子电路的第一端、第二端、第三端；所述第二晶体管的栅极和所述第三晶体管的栅极彼此电连接，并作为所述第一开关子电路的第一端；所述第二晶体管的第一极、第二极分别作为所述第一开关子电路的第二端、第三端；所述第三晶体管的第一极、第二极分别作为所述第一开关子电路的第四端、第五端；所述第四晶体管的栅极和所述第五晶体管的栅极电连接，并作为所述第二开关子电路的第一端；所述第四晶体管的第一极、第二极分别作为所述第二开关子电路的第二端、第三端；所述第五晶体管的第一极、第二极分别作为所述第二开关子电路的第四端、第五端；所述第六晶体管的栅极、第一极、第二极分别作为所述第三开关子电路的第一端、第二端、第三端。
在一些示例中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管和所述第六晶体管均为N型晶体管。
在一些示例中，所述像素驱动电路还包括所述发光元件，所述发光元件与所述第二开关子电路的第五端电连接。
在一些示例中，所述第一开关子电路包括第二晶体管和第三晶体管；所述第二晶体管的栅极和所述第三晶体管的栅极彼此电连接，并作为所述第一开关子电路的第一端；所述第二晶体管的第一极、第二极分别作为所述第一开关子电路的第二端、第三端；所述第三晶体管的第一极、第二极分别作为所述第一开关子电路的第四端、第五端。
在一些示例中，所述第二开关子电路包括第四晶体管和第五晶体管；所述第四晶体管的栅极和所述第五晶体管的栅极电连接，并作为所述第二开关子电路的第一端；所述第四晶体管的第一极、第二极分别作为所述第二开关 子电路的第二端、第三端；所述第五晶体管的第一极、第二极分别作为所述第二开关子电路的第四端、第五端。
在一些示例中，所述第三开关子电路包括第六晶体管；所述第六晶体管的栅极、第一极、第二极分别作为所述第三开关子电路的第一端、第二端、第三端。
本公开至少一实施例还提供一种显示装置，包括多个像素单元，至少一个像素单元包括上述像素驱动电路。
在一些示例中，所述显示装置还包括所述扫描信号线、所述第一控制信号线、所述第二控制信号线和所述数据信号线，所述扫描信号线与所述第一开关子电路的第一端电连接，所述第一控制信号线与所述第二开关子电路的第一端电连接，所述第二控制信号线与所述第三开关子电路的第一端电连接，所述数据信号线与所述第一开关子电路的第二端电连接。
本公开至少一实施例还提供一种像素驱动方法，应用于上述像素驱动电路，包括：在复位阶段，开启所述第一开关子电路和所述第二开关子电路，并关闭所述第三开关子电路，将来自所述第一电压端的第一电源电压写入所述第一节点，并将来自所述数据信号线的初始信号传输至所述第二节点；在数据写入和补偿阶段，开启所述第一开关子电路和所述第三开关子电路，并关闭所述第二开关子电路，将来自所述数据信号线的数据信号传输至所述第二节点，并对所述驱动子电路进行补偿；在发光阶段，开启所述第二开关子电路和所述第三开关子电路，并关闭所述第一开关子电路，所述电荷存储子电路根据所述第二节点的电压变化量通过耦合调整所述第一节点的电压，所述驱动子电路将所述驱动电流施加至所述发光元件以使其发光。
在一些示例中，在所述电荷存储子电路包括第一电容和第二电容，所述驱动子电路包括第一晶体管的情形下，所述电荷存储子电路根据所述第二节点的电压变化量通过耦合调整所述第一节点的电压包括：所述第一晶体管的栅极电压随着其第二极的电压发生跳变，所述栅极电压的跳变量ΔVg与所述第二极的电压的跳变量ΔVs满足：
Figure PCTCN2020077937-appb-000001
其中，C1表示所述第一电容的电容值，C2表示所述第二电容的电容值。
在一些示例中，所述第一晶体管的第二极的电压的跳变量为 ΔVs＝Vel-Vdata，其中，Vel表示所述第二节点在所述发光阶段的电压，Vdata表示所述数据电压。
在一些示例中，所述第一晶体管的栅极在所述发光阶段的电压为
Figure PCTCN2020077937-appb-000002
其中，Vth为所述第一晶体管的阈值电压。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为一种OLED驱动电路的电路原理示意图；
图2A为本申请实施例提供的一种像素驱动电路的示意框图；
图2B图2A中所示的像素驱动电路的一种具体实现示例的电路图；
图3A为本申请一实施例提供的像素驱动方法的流程示意图；
图3B为本申请另一实施例提供的像素驱动方法的流程示意图；
图4为本申请实施例提供的像素驱动电路的信号时序图；
图5为本申请实施例提供的像素驱动电路和像素驱动方法的补偿效果示意图；
图6为本公开实施例提供的显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第 一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为一种OLED驱动电路(2T1C)示意图。如图1所示，图1中的Gate表示扫描信号线(亦可称栅极信号线或栅线)，Data表示数据信号线(亦可称数据线)，Sw-T表示开关晶体管，Dr-T表示驱动TFT(Thin Film Transistor，薄膜晶体管)，Vg和Vs分别表示Dr-T的栅极和源极，VDD表示与驱动晶体管连接的第一电压端，VSS表示与二极管元件连接的第二电压端，Cst表示存储电容。
流经图1中的二极管元件的驱动电流Id可表示为：
Figure PCTCN2020077937-appb-000003
表达式(1)中，k为驱动TFT的导电参数，Vgs为驱动TFT的栅极与源极的电压差，Vth为驱动TFT的阈值电压。
由表达式(1)可知，驱动电流Id的大小与Vth有关，当Vth的大小不稳定时，在不同区域的多个显示单元写入相同的数据信号时，驱动电流Id也不稳定，从而将导致显示装置的亮度显示不均。
本申请提供的像素驱动电路、显示装置及像素驱动方法，旨在解决现有技术的如上技术问题。
下面以具体地实施例对本申请的技术方案以及本申请的技术方案如何解决上述技术问题进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例中不再赘述。下面将结合附图，对本申请的实施例进行描述。
图2A为本申请实施例提供的一种像素驱动电路的示意框图，如图2A 所示，该像素驱动电路包括：电荷存储子电路1、驱动子电路2、第一开关子电路3、第二开关子电路4和第三开关子电路5。
电荷存储子电路1包括第一端11、第二端12和第三端13，电荷存储子电路1的第一端11与第一电压端VDD电连接，第二端12与第一节点A电连接，第三端13与第二节点B电连接。例如，电荷存储子电路1配置为根据第二节点B的电压变化量通过耦合调整第一节点A的电压。
驱动子电路2包括第一端21、第二端22和第三端23，驱动子电路2的第一端与第一节点A电连接，第三端23与第二节点B电连接；驱动子电路2配置为控制流经其第二端22和第三端23的用于驱动发光元件6发光的驱动电流。
第一开关子电路3包括第一端31、第二端32、第三端33、第四端34和第五端35，第一开关子电路3的第一端31配置为与扫描信号线Gate电连接以接收扫描信号Gate，第二端32配置为与数据信号线Data电连接以接收数据信号Data，第三端33与第二节点B电连接，第四端34与第一节点A电连接，第五端35与第三节点C电连接。例如，第一开关子电路3配置为响应于该扫描信号Gate将来自数据信号线Data的信号(如数据信号Data以及后文的初始信号Vref)传输至第二节点B，并将第三节点C的电压写入第一节点A。
第二开关子电路4包括第一端41、第二端42、第三端43、第四端44和第五端45，第二开关子电路4的第一端41配置为与第一控制信号线EM2电连接以接收第一控制信号EM2，第二端42与第一电压端VDD电连接，第三端43与第三节点C电连接，第四端44与第二节点B电连接，第五端45配置为与发光元件6电连接。例如，第二开关子电路4配置为响应于该第一控制信号EM2将来自第一电压端VDD的第一电源电压写入第三节点C，并将第二节点B的电压写入发光元件6的第一电极。
第三开关子电路5包括第一端51、第二端52和第三端53，第三开关子电路5的第一端51配置为与第二控制信号线EM1电连接以接收第二控制信号EM1，第二端52与第三节点C电连接，第三端53与驱动子电路2的第二端22电连接。例如，第三开关子电路5配置为响应于该第 二控制信号EM1将第三节点C的电压写入驱动子电路2的第二端22。
需要说明的是，在本公开的实施例的描述中，符号Gate既可以表示扫描信号线又可以表示扫描信号，符号EM2既可以表示第一控制信号线又可以表示第一控制信号，符号EM1既可以表示第二控制信号线又可以表示第二控制信号，符号Data既可以表示数据信号线又可以表示数据信号，同样地，符号VDD既可以表示第一电压端又可以表示第一电源电压，符号VSS既可以表示第二电压端又可以表示第二电源电压。以下各实施例与此相同，不再赘述。
图2B为图2A中所示的像素驱动电路的一种具体实现示例的电路图。例如，如图2B所示，电荷存储子电路1包括第一电容C1和第二电容C2；第一电容C1的第一极作为电荷存储子电路1的第一端11，与第一电压端VDD电连接；第一电容C1的第二极和第二电容C2的第一极均作为电荷存储子电路1的第二端12，与第一节点A电连接；第二电容C2的第二极作为电荷存储子电路1的第三端13，与第二节点B电连接。
例如，驱动子电路2包括第一晶体管T1(即驱动晶体管)；第一晶体管T1的栅极、第一极、第二极分别作为驱动子电路2的第一端21、第二端22、第三端23，分别与第一节点A、第二节点B、第三开关子电路5的第三端53电连接。
例如，第一开关子电路3包括第二晶体管T2和第三晶体管T3；第二晶体管T2的栅极和第三晶体管T3的栅极均作为第一开关子电路3的第一端31，均与扫描信号线Gate电连接；第二晶体管T2的第一极、第二极分别作为第一开关子电路3的第二端32、第三端33，分别与数据信号线Data、第二节点B电连接；第三晶体管T3的第一极、第二极分别作为第一开关子电路3的第四端34、第五端35，分别与第一节点A、第三节点C电连接。
例如，第二开关子电路4包括第四晶体管T4和第五晶体管T5；第四晶体管T4的栅极和第五晶体管的栅极均作为第二开关子电路4的第一端41，均与第一控制信号线EM2电连接；第四晶体管T4的第一极、第二极分别作为第二开关子电路4的第二端42、第三端43，分别与第一电压 端、第三节点C电连接；第五晶体管T5的第一极、第二极分别作为第二开关子电路4的第四端44、第五端45，分别与第二节点B、发光元件6(如OLED)电连接。发光元件6与第二电压端(VSS端)电连接。
例如，第三开关子电路5包括第六晶体管T6；第六晶体管T6的栅极、第一极、第二极分别作为第三开关子电路5的第一端51、第二端52、第三端53，分别与第二控制信号线EM1、第三节点C、驱动子电路2的第二端22电连接。
例如，发光元件6可以包括有机发光二极管(OLED)，该OLED可以为各种类型，例如顶发射、底发射、双侧发射等，可以发红光、绿光、蓝光或白光等，本公开的实施例对此不作限制。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
另外，需要说明的是，图2B所示的像素驱动电路中的晶体管均是以N型晶体管为例进行说明的，此时，第一极可以是漏极，第二极可以是源极。本公开的实施例包括但不限于图2B的配置方式，在本公开的另一个实施例中，该像素驱动电路中的晶体管也可以混合采用P型晶体管和N型晶体管，只需同时将选定类型的晶体管的各端的极性按照本公开的实施例中的相应晶体管的端口极性相应连接即可。
在本公开的说明中，第一节点A、第二节点B、第三节点C并非一定表示实际存在的部件，而是表示电路图中相关电连接的汇合点。
本申请实施例还提供了一种像素驱动方法，可应用于本申请实施例提供的像素驱动电路。
图3A为本公开至少一实施例提供的像素驱动方法的流程示意图，如图3A所示，该像素驱动方法至少包括：步骤S201，在复位阶段，开启该第一开关子电路和该第二开关子电路，并关闭该第三开关子电路， 将来自该第一电压端的第一电源电压写入该第一节点，并将来自该数据信号线的初始信号传输至该第二节点；步骤S202，在数据写入和补偿阶段，开启该第一开关子电路和该第三开关子电路，并关闭该第二开关子电路，将来自该数据信号线的数据电压传输至该第二节点，并对该驱动子电路进行补偿；步骤S203，在发光阶段，开启该第二开关子电路和该第三开关子电路，并关闭该第一开关子电路，该电荷存储子电路根据该第二节点的电压变化量通过耦合调整该第一节点的电压，该驱动子电路将驱动电流施加至该发光元件以使其发光。
图3B为本公开另一一实施例提供的像素驱动方法的流程图。结合图2B和图3B所示，该像素驱动方法包括如下步骤S301-S303。
S301，在复位阶段，像素驱动电路中的第一开关子电路3和第二开关子电路4，在通过各自的第一端接收到第一电平信号时均导通，将通过第二开关子电路4的第二端接收到的第一电源电压VDD和通过第一开关子电路3的第二端接收到的初始信号Vref，分别输出至第一节点A和第二节点B。
S302，在数据写入和补偿阶段，第二开关子电路4在通过其第一端接收到第二电平信号时断开，第一开关子电路3和像素驱动电路中的第三开关子电路5，在通过各自的第一端接收到第一电平信号时分别保持导通状态和导通，第一开关子电路3将通过其第二端接收到的数据信号Data输出至第二节点B，像素驱动电路根据数据信号Data对驱动子电路2的阈值电压Vth进行补偿。
S303，在发光阶段，第一开关子电路3在通过其第一端接收到第二电平信号时断开，第二开关子电路4和第三开关子电路5在通过各自的第一端接收到第一电平信号时分别导通和保持导通状态，使得像素驱动电路中的驱动子电路2输出驱动电流至发光元件。
例如，第一电平信号为高电平信号，第二电平信号为低电平信号；或者，第一电平信号为低电平信号，第二电平信号为高电平信号。
下面参照图2B所示的像素驱动电路以及图4所示的像素驱动电路的信号时序图，以各晶体管均为N型TFT的情况为例，对本申请实施例提 供的像素驱动方法进行示例性说明。
在复位阶段，在图2B所示的像素驱动电路中，扫描信号Gate和第一控制信号EM2均处于逻辑高电位，扫描信号线Gate分别向第一开关子电路3中的第二晶体管T2和第三晶体管T3的栅极输入高电平信号，第一控制信号线EM2分别向第二开关子电路4中的第四晶体管T4和第五晶体管T5的栅极输入高电平信号，晶体管T2～T5在接收到的高电平信号的控制下导通。
第二控制信号EM1处于逻辑低电位，第二控制信号线EM1向第三开关子电路5中第六晶体管T6的栅极输入低电平信号，第六晶体管T6保持断开状态，从而保证发光元件OLED不发光。
T2～T5全部导通后，第一电压端提供的电源电压VDD通过第四晶体管T4和第三晶体管T3传输至第一节点A，进一步传输至与第一节点A电连接的驱动子电路2中的第一晶体管T1的栅极，从而为第一晶体管T1复位，使第一晶体管T1的栅极电压Vg变为VDD；同时，数据信号线Data提供的初始信号Vref通过第二晶体管T2传输至第二节点B，进而传输至与第二节点B电连接的OLED的阳极，从而为OLED的阳极复位。
在数据写入和补偿阶段，第一控制信号EM2变为逻辑低电位，第一控制信号线EM2分别向第四晶体管T4和第五晶体管T5的栅极输入低电平信号，第四晶体管T4和第五晶体管T5在接收到的低电平信号的控制下断开，从而保证发光元件OLED不发光。
扫描信号Gate和第二控制信号EM1均处于逻辑高电位，扫描信号线Gate分别向第二晶体管T2和第三晶体管T3的栅极输入高电平信号，第二晶体管T2和第三晶体管T3在接收到的高电平信号的控制下均保持导通状态，第二控制信号线EM1向第六晶体管T6的栅极输入高电平信号，第六晶体管T6在接收到的高电平信号的控制下导通。
数据信号线Data提供的数据信号(数据电压)Vdata通过第二晶体管T2传输至第二节点B，也即与第二节点B连接的第一晶体管T1的第二极，第一晶体管T1的源极电压Vs变为Vdata。N型TFT导通的条件为：
Vg-Vs≥Vth，且Vth≥0        表达式(2)
将第一晶体管T1的栅极电压(Vg＝VDD)和源极电压(Vs＝Vdata)代入表达式(2)，则该前提条件还可表示为：
VDD≥Vdata+Vth，且Vth≥0        表达式(3)
也即该第一电源电压VDD配置为大于等于该数据电压Vdata与第一晶体管T1的阈值电压之和。当第一电源电压VDD、数据电压Vdata和第一晶体管T1的阈值电压Vth满足表达式(3)时，第一晶体管T1的栅极电压Vg开始下降，由VDD降低到Vdata+Vth，从而实现第一晶体管T1的阈值电压Vth的补偿；Vg降低到Vdata+Vth时，第一晶体管T1断开，此时电荷存储子电路1中的第二电容C2存储的电压为Vg-Vs＝Vth。
在发光阶段，扫描信号Gate变为逻辑低电位，扫描信号线Gate分别向第二晶体管T2和第三晶体管T3的栅极输入低电平信号，第二晶体管T2和第三晶体管T3均断开，第二电容C2存储的电压保持在Vth。
第二控制信号EM1保持在逻辑高电位，第二控制信号线EM1向第六晶体管T6的栅极持续输入高电平信号，第六晶体管T6在接收到的高电平信号下保持导通状态；第一控制信号EM2变为逻辑高电位，第一控制信号线EM2分别向第四晶体管T4和第五晶体管T5的栅极输入高电平信号，第四晶体管T4和第五晶体管T5在接收到的高电平信号的控制下导通。
在发光阶段，T4、T5和T6均导通，第一晶体管T1的源极电压Vs发生跳变，跳变量为：
ΔVs＝Vel-Vdata          表达式(4)
在表达式(4)中，Vel表示发光阶段第二节点B的电压，例如为发光元件OLED的阳极电压。Vel与发光元件OLED的内阻有关，与第一晶体管T1的阈值电压无关。
由于第一电容C1和第二电容C2的耦合作用，第一晶体管T1的源极电压Vs发生跳变时，其栅极电压Vg随之发生跳变。由于第一电容C1和第二电容C2串联，第一电容C1的第一极的电位保持不变(即为第一电源电压VDD)，根据电荷守恒原理可以得到第一晶体管T1的栅极电 压Vg的跳变量
Figure PCTCN2020077937-appb-000004
C1表示第一电容的电容值，C2表示第二电容的电容值。
因此，跳变后的栅极电压Vg为：
Figure PCTCN2020077937-appb-000005
Figure PCTCN2020077937-appb-000006
由表达式(6)可以看出，当Vdata-Vel≥0时，Vg-Vs-Vth≥0，进而可得Vg-Vs≥Vth，当Vth≥0时，可满足如表达式(2)所示的N型TFT导通的条件，驱动晶体管T1导通，驱动晶体管T1产生驱动电流Id以驱动OLED发光；结合表达式(1)可知，通过OLED的驱动电流Id与(Vdata-Vel)有关，而与驱动晶体管T1的阈值电压Vth无关，从而实现了对阈值电压Vth的补偿，降低了阈值电压Vth对驱动电流的影响，降低了阈值电压Vth的不稳定对显示亮度的影响，显示亮度更加稳定，均一性较佳，有效地改善了画面显示质量。
应用本申请实施例提供的像素驱动电路和像素驱动方法，对Vth的补偿效果如图5所示，图5的横坐标表示驱动晶体管T1的阈值电压Vth(单位V，即伏特)，纵坐标表示驱动电流Id(单位为μA，即微安)。由图5可以看出，本申请实施例对Vth的补偿范围为0～5.5V，大于现有的像素驱动电路或像素补偿电路的补偿范围(通常为1V)，本申请实施例通过OLED的驱动电流的波动ΔId<5％，相对于现有的像素驱动电路或像素补偿电路的补偿效果，有着显著优势。
应用本申请实施例提供的像素驱动电路和像素驱动方法，至少可以实现如下1)-4)项有益效果。
1)采用本申请实施例提供的像素驱动电路和像素驱动方法，能够有效地对驱动晶体管的阈值电压Vth进行补偿，并具有较好的补偿效果，可降低阈值电压Vth的不稳定对显示亮度的影响，使显示亮度更加稳定、均一性更佳，从而改善显示画面的显示质量。
2)无需设计单独的基准电源信号，利用第一电压端的电源电压VDD即可对驱动晶体管的栅极进行复位，利用数据信号线Data输入的初始电压Vref即可对OLED的阳极进行复位，从而减少了驱动信号的数量，简化了复位流程。
3)在本申请实施例提供的像素驱动电路工作时，只需要3条栅极驱动线(分别为扫描信号线Gate、第一控制信号线EM2和第二控制信号线EM1)，信号波形简单，有利于实现显示装置的GOA(Gate on Array，栅极驱动电路阵列)设计。
4)从图4所示的信号时序图可知，第一控制信号EM2和第二控制信号EM1波形是一致的，只存在相位差，因此二者可以由一个栅极驱动电路单元(例如GOA单元)提供，从而简化了电路，节省了成本。
本申请实施例还提供了一种显示装置，包括本申请实施例提供的像素驱动电路。
图6为本公开一实施例提供的一种显示装置的示意框图。参考图6，显示装置20包括显示面板2000、栅极驱动器2010、定时控制器2020和数据驱动器2030。显示面板2000包括据多条扫描线GL和多条数据线DL。栅极驱动器2010用于驱动多条扫描线GL；数据驱动器2030用于驱动多条数据线DL；定时控制器2020用于处理从显示装置20外部输入的图像数据RGB，向数据驱动器2030提供处理的图像数据RGB以及向栅极驱动器2010和数据驱动器2030输出扫描控制信号GCS和数据控制信号DCS，以对栅极驱动器2010和数据驱动器2030进行控制。
例如，该扫描线GL可以包括上述扫描信号线Gate、第一控制信号线EM2和第二控制信号线EM1。该数据线GL可以包括上述数据信号线Date。
例如，显示面板2000包括多个像素单元P，像素单元P包括上述任一实施例中提供的像素驱动电路，例如，包括如图2A-2B所示的像素驱动电路。如图6所示，例如，像素单元P设置在扫描线GL和数据线DL的交叉区域。例如，每个像素单元P连接到三条扫描线GL(分别提供扫描信号Gate、第一控制信号EM2和第二控制信号EM1)、一条数据线DL(提供数据信号Vdata)、用于提供第一电源电压的第一电压线和用 于提供第二电源电压的第二电压线。例如，第一电压线或第二电压线可以用相应的板状公共电极(例如公共阳极或公共阴极)替代。需要说明的是，在图6中仅示出了部分的像素单元P、扫描线GL和数据线DL。
例如，栅极驱动器2010根据源自定时控制器2020的多个扫描控制信号GCS向多个扫描线GL提供多个选通信号。多个选通信号包括扫描信号和复位信号等。这些信号通过多个扫描线GL提供给每个像素单元P。
例如，数据驱动器2030使用参考伽玛电压根据源自定时控制器2020的多个数据控制信号DCS将从定时控制器2020输入的数字图像数据RGB转换成数据信号。数据驱动器2030向多条数据线DL提供转换的数据信号。
例如，定时控制器2020对外部输入的图像数据RGB进行处理以匹配显示面板2000的大小和分辨率，然后向数据驱动器2030提供处理后的图像数据。定时控制器2020使用从显示装置20外部输入的同步信号(例如点时钟DCLK、数据使能信号DE、水平同步信号Hsync以及垂直同步信号Vsync)产生多条扫描控制信号GCS和多条数据控制信号DCS。定时控制器2020分别向栅极驱动器2010和数据驱动器2030提供产生的扫描控制信号GCS和数据控制信号DCS，以用于栅极驱动器2010和数据驱动器2030的控制。
例如，数据驱动器2030可以与多条数据线DL连接，以提供数据信号；同时还可以与多条第一电压线和多条第二电压线连接以分别提供第一电压和第二电压。
例如，栅极驱动器2010和数据驱动器2030可以实现为半导体芯片。该显示装置20还可以包括其他部件，例如信号解码电路、电压转换电路等，这些部件例如可以采用已有的常规部件，这里不再详述。
例如，显示面板2000可以应用于电子书、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件中。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。

Claims (20)

  1. 一种像素驱动电路，包括：电荷存储子电路、驱动子电路、第一开关子电路、第二开关子电路和第三开关子电路；其中，所述电荷存储子电路包括第一端、第二端和第三端，所述电荷存储子电路的第一端与第一电压端电连接，所述电荷存储子电路的第二端与第一节点电连接，所述电荷存储子电路的第三端与第二节点电连接；
    所述驱动子电路包括第一端、第二端和第三端，所述驱动子电路的第一端与所述第一节点电连接，所述驱动子电路的第三端与所述第二节点电连接，所述驱动子电路配置为控制流经所述第二端和所述第三端的用于驱动发光元件发光的驱动电流；
    所述第一开关子电路包括第一端、第二端、第三端、第四端和第五端，所述第一开关子电路的第一端配置为与扫描信号线电连接，所述第一开关子电路的第二端配置为与数据信号线电连接以接收数据电压，所述第一开关子电路的第三端与所述第二节点电连接，所述第一开关子电路的第四端与所述第一节点电连接，所述第一开关子电路的第五端与第三节点电连接；
    所述第二开关子电路包括第一端、第二端、第三端、第四端和第五端，所述第二开关子电路的第一端配置为与第一控制信号线电连接，所述第二开关子电路的第二端与所述第一电压端电连接以接收第一电源电压，所述第二开关子电路的第三端与所述第三节点电连接，所述第二开关子电路的第四端与所述第二节点电连接，所述第二开关子电路的第五端配置为与发光元件电连接；
    所述第三开关子电路包括第一端、第二端和第三端，所述第三开关子电路的第一端配置为与第二控制信号线电连接，所述第三开关子电路的第二端与所述第三节点电连接，所述第三开关子电路的第三端与所述驱动子电路的第二端电连接。
  2. 根据权利要求1所述的像素驱动电路，其中，所述电荷存储子电路配置为根据所述第二节点的电压变化量通过耦合调整所述第一节点的 电压。
  3. 根据权利要求1或2所述的像素驱动电路，其中，所述第一开关子电路配置为响应于来自所述扫描信号线的扫描信号将所述数据电压写入所述第二节点，并将所述第三节点的电压写入所述第一节点。
  4. 根据权利要求1-3任一所述的像素驱动电路，其中，所述第二开关子电路配置为响应于来自所述第一控制信号线的第一控制信号将来自所述第一电压端的所述第一电源电压写入所述第三节点，并将所述第二节点的电压传输至所述发光元件。
  5. 根据权利要求1-4任一所述的像素驱动电路，其中，所述第三开关子电路配置为响应于来自所述第二控制信号线的第二控制信号将第所述第三节点的电压写入所述驱动子电路的第二端。
  6. 根据权利要求1-5任一所述的像素驱动电路，其中，所述电荷存储子电路包括第一电容和第二电容；
    所述第一电容的第一极作为所述电荷存储子电路的第一端；
    所述第一电容的第二极和所述第二电容的第一极均作为所述电荷存储子电路的第二端；
    所述第二电容的第二极作为所述电荷存储子电路的第三端。
  7. 根据权利要求1-6任一所述的像素驱动电路，其中，所述驱动子电路包括第一晶体管；
    所述第一晶体管的栅极、第一极、第二极分别作为所述驱动子电路的第一端、第二端、第三端。
  8. 根据权利要求7所述的像素驱动电路，其中，所述第一电源电压配置为大于等于所述数据电压与所述第一晶体管的阈值电压之和。
  9. 根据权利要求1-8任一所述的像素驱动电路，其中，所述第一开关子电路包括第二晶体管和第三晶体管；
    所述第二晶体管的栅极和所述第三晶体管的栅极彼此电连接，并作为所述第一开关子电路的第一端；
    所述第二晶体管的第一极、第二极分别作为所述第一开关子电路的第二端、第三端；
    所述第三晶体管的第一极、第二极分别作为所述第一开关子电路的第四端、第五端。
  10. 根据权利要求1-9任一所述的像素驱动电路，其中，所述第二开关子电路包括第四晶体管和第五晶体管；
    所述第四晶体管的栅极和所述第五晶体管的栅极电连接，并作为所述第二开关子电路的第一端；
    所述第四晶体管的第一极、第二极分别作为所述第二开关子电路的第二端、第三端；
    所述第五晶体管的第一极、第二极分别作为所述第二开关子电路的第四端、第五端。
  11. 根据权利要求1-10任一所述的像素驱动电路，其中，所述第三开关子电路包括第六晶体管；
    所述第六晶体管的栅极、第一极、第二极分别作为所述第三开关子电路的第一端、第二端、第三端。
  12. 根据权利要求1-5任一所述的像素驱动电路，其中，所述电荷存储子电路包括第一电容和第二电容；所述驱动子电路包括第一晶体管；所述第一开关子电路包括第二晶体管和第三晶体管，所述第二开关子电路包括第四晶体管和第五晶体管，所述第三开关子电路包括第六晶体管；
    所述第一电容的第一极作为所述电荷存储子电路的第一端；所述第一电容的第二极和所述第二电容的第一极均作为所述电荷存储子电路的第二端；所述第二电容的第二极作为所述电荷存储子电路的第三端；
    所述第一晶体管的栅极、第一极、第二极分别作为所述驱动子电路的第一端、第二端、第三端；
    所述第二晶体管的栅极和所述第三晶体管的栅极彼此电连接，并作为所述第一开关子电路的第一端；所述第二晶体管的第一极、第二极分别作为所述第一开关子电路的第二端、第三端；所述第三晶体管的第一极、第二极分别作为所述第一开关子电路的第四端、第五端；
    所述第四晶体管的栅极和所述第五晶体管的栅极电连接，并作为所述第二开关子电路的第一端；所述第四晶体管的第一极、第二极分别作 为所述第二开关子电路的第二端、第三端；所述第五晶体管的第一极、第二极分别作为所述第二开关子电路的第四端、第五端；
    所述第六晶体管的栅极、第一极、第二极分别作为所述第三开关子电路的第一端、第二端、第三端。
  13. 根据权利要求1-12任一所述的像素驱动电路，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管和所述第六晶体管均为N型晶体管。
  14. 根据权利要求1-13任一所述的像素驱动电路，还包括所述发光元件，其中，所述发光元件与所述第二开关子电路的第五端电连接。
  15. 一种显示装置，包括多个像素单元，至少一个像素单元包括如权利要求1-14中任一项所述的像素驱动电路。
  16. 根据权利要求15所述的显示装置，还包括所述扫描信号线、所述第一控制信号线、所述第二控制信号线和所述数据信号线，
    其中，所述扫描信号线与所述第一开关子电路的第一端电连接，所述第一控制信号线与所述第二开关子电路的第一端电连接，所述第二控制信号线与所述第三开关子电路的第一端电连接，所述数据信号线与所述第一开关子电路的第二端电连接。
  17. 一种像素驱动方法，应用于如权利要求1-14中任一项所述的像素驱动电路，包括：
    在复位阶段，开启所述第一开关子电路和所述第二开关子电路，并关闭所述第三开关子电路，将来自所述第一电压端的第一电源电压写入所述第一节点，并将来自所述数据信号线的初始信号传输至所述第二节点；
    在数据写入和补偿阶段，开启所述第一开关子电路和所述第三开关子电路，并关闭所述第二开关子电路，将来自所述数据信号线的数据电压传输至所述第二节点，并对所述驱动子电路进行补偿；
    在发光阶段，开启所述第二开关子电路和所述第三开关子电路，并关闭所述第一开关子电路，所述电荷存储子电路根据所述第二节点的电压变化量通过耦合调整所述第一节点的电压，所述驱动子电路将所述驱 动电流施加至所述发光元件以使其发光。
  18. 根据权利要求17所述的像素驱动方法，其中，在所述电荷存储子电路包括第一电容和第二电容，所述驱动子电路包括第一晶体管的情形下，所述电荷存储子电路根据所述第二节点的电压变化量通过耦合调整所述第一节点的电压包括：
    所述第一晶体管的栅极电压随着所述第一晶体管的第二极的电压发生跳变，所述第一晶体管的栅极电压的跳变量ΔVg与所述第一晶体管的第二极的电压的跳变量ΔVs满足：
    Figure PCTCN2020077937-appb-100001
    其中，C1表示所述第一电容的电容值，C2表示所述第二电容的电容值。
  19. 根据权利要求18所述的像素驱动方法，其中，所述第一晶体管的第二极的电压的跳变量ΔVs满足：ΔVs＝Vel-Vdata，其中，Vel表示所述第二节点在所述发光阶段的电压，Vdata表示所述数据电压。
  20. 根据权利要求19所述的像素驱动方法，其中，所述第一晶体管的栅极在所述发光阶段的电压Vg满足：
    Figure PCTCN2020077937-appb-100002
    其中，Vth为所述第一晶体管的阈值电压。
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CN109754757B (zh) * 2019-03-28 2020-11-06 京东方科技集团股份有限公司 像素驱动电路、显示装置及像素驱动方法
CN110444167A (zh) * 2019-06-28 2019-11-12 福建华佳彩有限公司 一种amoled补偿电路
CN110472606B (zh) 2019-08-21 2022-05-20 京东方科技集团股份有限公司 一种超声波识别模组、其驱动方法及显示装置
CN110544458B (zh) * 2019-09-10 2021-08-06 京东方科技集团股份有限公司 一种像素电路、其驱动方法及显示装置
TWI708233B (zh) * 2019-09-20 2020-10-21 友達光電股份有限公司 適用於低更新頻率的畫素電路與相關的顯示裝置
KR20210085540A (ko) * 2019-12-30 2021-07-08 엘지디스플레이 주식회사 화소회로, 발광표시장치 및 그의 구동방법
US20240185780A1 (en) * 2021-06-25 2024-06-06 Chengdu Boe Optoelectronics Technology Co., Ltd. Pixel driving circuit, driving method for the pixel driving circuit, and display panel
CN113920923B (zh) * 2021-10-18 2022-09-09 深圳市华星光电半导体显示技术有限公司 发光器件驱动电路、背光模组以及显示面板
CN115881029A (zh) * 2022-12-27 2023-03-31 深圳市华星光电半导体显示技术有限公司 像素驱动电路及其驱动方法、显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160133190A1 (en) * 2014-11-10 2016-05-12 Samsung Display Co., Ltd. Organic light emitting diode display
CN105845082A (zh) * 2015-01-28 2016-08-10 三星显示有限公司 有机发光显示装置
CN106887207A (zh) * 2015-12-15 2017-06-23 昆山工研院新型平板显示技术中心有限公司 像素电路及其驱动方法和有机发光显示器
CN107230451A (zh) * 2017-07-11 2017-10-03 深圳市华星光电半导体显示技术有限公司 一种amoled像素驱动电路及像素驱动方法
KR20190010058A (ko) * 2017-07-20 2019-01-30 엘지디스플레이 주식회사 유기발광 표시장치와 그의 구동방법
CN109754757A (zh) * 2019-03-28 2019-05-14 京东方科技集团股份有限公司 像素驱动电路、显示装置及像素驱动方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104409043B (zh) * 2014-12-05 2016-08-24 京东方科技集团股份有限公司 像素驱动电路和像素驱动方法、显示装置
CN104809989A (zh) * 2015-05-22 2015-07-29 京东方科技集团股份有限公司 一种像素电路、其驱动方法及相关装置
CN106023900A (zh) * 2016-08-01 2016-10-12 上海天马有机发光显示技术有限公司 一种有机发光显示面板及其驱动方法
CN106652912B (zh) * 2016-12-13 2020-05-19 上海天马有机发光显示技术有限公司 有机发光像素驱动电路、驱动方法以及有机发光显示面板
CN109215569B (zh) * 2017-07-04 2020-12-25 京东方科技集团股份有限公司 一种像素电路、驱动方法及显示装置
CN107221289B (zh) * 2017-08-02 2019-09-27 上海天马有机发光显示技术有限公司 一种像素驱动电路及其控制方法和显示面板、显示装置
CN109064975B (zh) * 2018-09-28 2020-04-03 昆山国显光电有限公司 像素电路及其驱动方法、显示面板、显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160133190A1 (en) * 2014-11-10 2016-05-12 Samsung Display Co., Ltd. Organic light emitting diode display
CN105845082A (zh) * 2015-01-28 2016-08-10 三星显示有限公司 有机发光显示装置
CN106887207A (zh) * 2015-12-15 2017-06-23 昆山工研院新型平板显示技术中心有限公司 像素电路及其驱动方法和有机发光显示器
CN107230451A (zh) * 2017-07-11 2017-10-03 深圳市华星光电半导体显示技术有限公司 一种amoled像素驱动电路及像素驱动方法
KR20190010058A (ko) * 2017-07-20 2019-01-30 엘지디스플레이 주식회사 유기발광 표시장치와 그의 구동방법
CN109754757A (zh) * 2019-03-28 2019-05-14 京东方科技集团股份有限公司 像素驱动电路、显示装置及像素驱动方法

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