WO2023011474A1 - 像素电路、显示装置和驱动方法 - Google Patents

像素电路、显示装置和驱动方法 Download PDF

Info

Publication number
WO2023011474A1
WO2023011474A1 PCT/CN2022/109707 CN2022109707W WO2023011474A1 WO 2023011474 A1 WO2023011474 A1 WO 2023011474A1 CN 2022109707 W CN2022109707 W CN 2022109707W WO 2023011474 A1 WO2023011474 A1 WO 2023011474A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
control signal
reset
circuit
pole
Prior art date
Application number
PCT/CN2022/109707
Other languages
English (en)
French (fr)
Inventor
陈义鹏
石领
周伟峰
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2023011474A1 publication Critical patent/WO2023011474A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element

Definitions

  • the present application relates to the field of display technology, and in particular to a pixel circuit, a display device and a driving method for the pixel circuit.
  • Low temperature polycrystalline oxide (LTPO) display technology can make the display panel have both strong driving capability and low
  • a pixel circuit based on LTPO technology which can also stabilize the display screen of a display panel including a plurality of pixel circuits.
  • a pixel circuit including: a driving circuit, a data writing circuit, a compensation circuit, a light emission control circuit, a first reset circuit, a second reset circuit, and a light emitting element;
  • the drive circuit includes a control terminal, a first terminal and a second terminal, which are respectively connected to the first node, the second node and the third node, and are used to control the drive for driving the light-emitting element to emit light flowing through the first terminal and the second terminal current;
  • the data writing circuit is used to write the data signal into the first end of the drive circuit under the control of the write control signal;
  • the compensation circuit is used to write the drive circuit under the control of the compensation control signal
  • the control terminal and the second terminal are electrically connected, and store the voltage of the control terminal of the driving circuit;
  • the light emitting control circuit is used to make the driving current flow through the light emitting element under the control of the light emitting control signal;
  • the first reset circuit is used for The first reset voltage is applied to the control terminal of the drive circuit
  • each display period sequentially includes a writing frame and at least one holding frame
  • the writing control signal and the second reset control signal are synchronized, and each In one holding frame, the writing control signal is kept at an inactive level, and the second reset control signal has the same characteristics as the second reset control signal of the writing frame.
  • a display device comprising: a plurality of pixel units distributed in an array, wherein each of the pixel units includes the above-mentioned pixel circuit.
  • a driving method for the above pixel circuit including: in the case that each display period includes one writing frame and at least one holding frame in sequence, within the writing frame, The writing control signal is synchronized with the second reset control signal, and the writing frame includes: a reset phase, a data writing and compensation phase, and a light emitting phase; in each holding frame, the writing The input control signal remains at an inactive level, the second reset control signal has the same characteristics as the second reset control signal of the write frame, and the maintain frame includes: the data writing and compensation phase of the write frame The corresponding lighting reset phase and the lighting phase corresponding to the lighting phase written in the frame.
  • the driving method further includes: making the first light emission control signal and the second light emission control signal The two light emission control signals are synchronized, and in each holding frame, the first light emission control signal is kept at an active level, and the second light emission control signal has the same characteristics as the second light emission control signal of the writing frame.
  • FIG. 1A shows a structural block diagram of a pixel circuit based on LTPO technology according to an embodiment of the present disclosure.
  • FIG. 1B-1C show circuit diagrams and corresponding timing diagrams of example circuit structures of the pixel circuit.
  • 1D-1E show circuit diagrams and corresponding timing diagrams of yet another exemplary circuit structure of the pixel circuit.
  • FIGS. 2A-2B show a circuit diagram of a first exemplary circuit structure of a pixel circuit according to an embodiment of the disclosure and a corresponding timing diagram in combination with a low frequency display.
  • 3A-3B show a circuit diagram of a second exemplary circuit structure of a pixel circuit according to an embodiment of the present disclosure and a corresponding timing diagram in combination with a low frequency display.
  • FIGS. 4A-4B show a circuit diagram and a corresponding timing diagram of a third exemplary circuit structure of a pixel circuit according to an embodiment of the present disclosure in combination with a low frequency display.
  • Fig. 5 shows a structural block diagram of an improved pixel circuit based on LTPO technology according to an embodiment of the present disclosure in combination with low frequency display.
  • 6A-6B show a circuit diagram and a corresponding timing diagram of a first exemplary circuit structure of another pixel circuit according to an embodiment of the present disclosure in combination with a low-frequency display.
  • FIGS. 7A-7B show a circuit diagram and a corresponding timing diagram of a second exemplary circuit structure of the other pixel circuit according to an embodiment of the present disclosure in combination with a low frequency display.
  • FIGS. 8A-8B show a circuit diagram and a corresponding timing diagram of a third exemplary circuit structure of another pixel circuit according to an embodiment of the present disclosure in combination with low-frequency display
  • FIG. 9 shows a schematic diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 1A shows a structural block diagram of a pixel circuit based on LTPO technology according to an embodiment of the present disclosure.
  • the pixel circuit 10 includes: a driving circuit 101, a data writing circuit 102, a compensation circuit 103, a light emission control circuit 104 (104-1 and 104-2), a first reset circuit 105 and a second reset circuit 106 .
  • the driving circuit includes a control terminal, a first terminal and a second terminal, and is used for controlling the driving current flowing through the first terminal and the second terminal for driving the light-emitting element to emit light.
  • the data writing circuit is used for writing the data signal into the first end of the driving circuit under the control of the scan signal (Scan).
  • the scanning signal may be generated by a GOA circuit, and applied to the plurality of pixel circuits on each row by row shift, so as to control the pixel circuits to write data.
  • the signals controlling the various circuits inside it need to meet a specific timing relationship with the scanning signal, so these signals are also shifted by row.
  • the compensation circuit is used to electrically connect the control terminal of the drive circuit to the second terminal under the control of the compensation control signal, or the control of the compensation control signal and the scanning signal, and store the voltage of the control terminal of the drive circuit.
  • the light emission control circuit is used to make the driving current flow through the light emitting element under the control of the light emission control signal.
  • the light emission control circuit may include a first light emission control circuit and a second light emission control circuit, and correspondingly, the light emission control signal may include a first light emission control signal and a second light emission control signal.
  • the first lighting control circuit is used for applying the first power supply voltage (VDD) of the first power supply terminal to the first terminal of the driving circuit under the control of the first lighting control signal.
  • the second light emission control circuit is used for applying the driving current from the second terminal of the driving circuit to the first pole of the light emitting element under the control of the second light emission control signal.
  • the first light emission control signal and the second light emission control signal are the same signal (EM).
  • the first reset circuit is used for applying the first reset voltage to the control terminal of the driving circuit under the control of the first reset control signal.
  • the second reset circuit is used for applying the second reset voltage to the first pole of the light emitting element under the control of the second reset control signal.
  • the second reset control signal is a scan signal or is synchronized with the scan signal, that is, the voltage of the first electrode of the light-emitting element is also reset while data is being written, so that the possible existing parasitic capacitance of the light-emitting element can be eliminated. The charge is released to ensure normal light emission.
  • the second reset control signal may also be synchronized with the first reset control signal, as long as the voltage of the first pole of the light emitting element is reset before the light emission control signal of this frame is valid.
  • the second pole of the light emitting element is connected to the second power terminal to receive the second power voltage (VSS).
  • FIG. 1B-1C show circuit diagrams and corresponding timing diagrams of example circuit structures of the pixel circuit.
  • each example pixel circuit shown herein is an example description of the circuit configuration in each circuit module in FIG. 1A , but this is not limited to the fact that each circuit module must adopt the same structure as that described in FIG. 1B
  • the drive circuit adopts the circuit configuration shown in Figure 1B
  • the data writing circuit can adopt a circuit configuration different from that shown in Figure 1B, for example, it can include more transistors, etc., as long as it can It is sufficient to apply the data voltage to the second node ( N2 ).
  • This understanding also applies to other example circuit structures of the present disclosure.
  • the drive circuit includes a first transistor (T1), the gate of the first transistor is connected to the first node (N1) as the control terminal of the drive circuit, and the first transistor of the first transistor One pole serves as the first terminal of the driving circuit and is connected to the second node (N2), and the second pole of the first transistor serves as the second terminal of the driving circuit and is connected to the third node (N3).
  • the data writing circuit includes a second transistor (T2), the gate of the second transistor is used to receive the scan signal (Scan), the first pole of the second transistor is used to receive the data signal, The second pole of the second transistor is connected to the second node (N2).
  • the compensation circuit includes a third transistor (T3) and a storage capacitor (Cs), the gate of the third transistor (T3) is used to receive the compensation control signal (C), and the first pole of the third transistor connected to the third node, the second pole of the third transistor is connected to the first pole of the storage capacitor and the first node, and the second pole of the storage capacitor is connected to the first power supply terminal for A first supply voltage is received.
  • the compensation control signal (C) is the scanning signal (Scan) (hereinafter used as an example) or is synchronized with it.
  • the first light emission control circuit includes a fourth transistor (T4), the gate of the fourth transistor is used to receive the light emission control signal (EM), and the first pole of the fourth transistor is connected to the first power supply terminal for Receiving the first power supply voltage, the second pole of the fourth transistor is connected to the second node (N2).
  • T4 the gate of the fourth transistor is used to receive the light emission control signal (EM)
  • EM light emission control signal
  • N2 the second node
  • the second light emission control circuit includes a fifth transistor (T5), the gate of the fifth transistor is used to receive the light emission control signal (EM), the first pole of the fifth transistor and the third node (N3 ), the second pole of the fifth transistor is connected to the first pole of the light-emitting element (as the fourth node).
  • T5 the gate of the fifth transistor is used to receive the light emission control signal (EM)
  • EM light emission control signal
  • N3 third node
  • the second pole of the fifth transistor is connected to the first pole of the light-emitting element (as the fourth node).
  • the first reset circuit includes a sixth transistor (T6), the gate of the sixth transistor is used to receive the first reset control signal (RST), the first pole of the sixth transistor and the first nodes, and the second pole of the sixth transistor is used to receive the first reset voltage.
  • T6 the gate of the sixth transistor is used to receive the first reset control signal (RST), the first pole of the sixth transistor and the first nodes, and the second pole of the sixth transistor is used to receive the first reset voltage.
  • the second reset circuit includes a seventh transistor (T7), the gate of the seventh transistor is used to receive the second reset control signal, the first pole of the seventh transistor and the first pole of the light emitting element The pole is connected, and the second pole of the seventh transistor is used to receive the second reset voltage.
  • the second reset control signal may be a light-emitting control signal (hereinafter, take this as an example) or be synchronized with the light-emitting control signal.
  • the seventh transistor When the light-emitting control signal is at an inactive level, the seventh transistor is reset; when the light-emitting control signal is at an active level, the driving current flows through the light-emitting element to emit light.
  • the gate-source voltage of the driving transistor (first transistor) is stable, so it is necessary to avoid leakage at each node as much as possible.
  • the transistors outside the drive current flow path can be selected as transistors with better leakage current characteristics, that is, the leakage current characteristics are better than those of transistors on the drive current flow path.
  • the LTPO TFT has lower driving power than the LTPS TFT.
  • the LTPS transistor has a large leakage current, but the driving speed is fast and the on-state current is large.
  • the LTPO transistor can refer to an oxide transistor. Leakage current is small. For the pixel circuit shown in FIG.
  • the transistors outside the drive current flow path i.e., transistors T2, T3, T6, and T7 can be set as oxide transistors, while the transistors on the drive current flow path (T1, T4, T5) adopt LTPS to ensure fast driving speed.
  • the polarities of the transistors in the first and second light emission control circuits and the driving transistors (T1, T4, T5) are shown to be related to the data writing circuit, the first and the second The polarity of the transistors (T2, T3, T6, T7) in the reset circuit is reversed. But it can be changed adaptively according to the actual situation.
  • FIG. 1C it includes a reset phase, a data writing and compensation phase, and a light emitting phase.
  • the first reset control signal is at an active level, and the scanning signal and the light emission control signal are at an inactive level.
  • the sixth transistor (T6) is turned on, and the seventh transistor (T7) is opposite to the transistor polarity of the light emission control circuit, so it is EM inactive) is turned on, and the rest of the transistors are turned off, so as to provide the first reset voltage to the first node (N1), and provide the second reset voltage to the first pole (fourth node) of the light-emitting element.
  • the voltage of the first node is Vint1
  • the voltage of the fourth node is Vint2
  • the voltages of the second node and the third node float after the end of the previous stage.
  • the scan signal is at an active level, and the first reset control signal and the light emission control signal are at an inactive level.
  • the first transistor T1, the second transistor T2, the third transistor T3 and the seventh transistor T7 are turned on, and the other transistors are turned off, the first transistor T1 forms a diode connection, and the data signal Data passes through the second transistor T2, the first transistor T1 and the third transistor T3 charge the first node N1 until the charging ends when the voltage of the first node N1 is Vdata+Vth, the voltage of the second node N2 is Vdata, and the voltage of the third node N3 is Vdata+Vth, thus completing The threshold voltage Vth of the first transistor T1 is extracted and the data voltage Vdata is written. At this time, the voltage on the storage capacitor is Vdata+Vth-VDD, that is, the threshold voltage Vth of the first transistor T1 is stored in the storage capacitor.
  • the light-emitting control signal is at an active level, and the scanning signal and the first reset control signal are at an inactive level.
  • the first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on, and the other transistors are turned off, and the current flows from VDD to VSS.
  • the voltage of the first node N1 is still Vdata+Vth due to the storage capacitor
  • the second The voltage of the node is VDD
  • the voltage of the third node N3 is the voltage of the first pole of the light emitting element.
  • the light emission control signal can be changed from an active level (low level in the figure) to an inactive level (high level in the figure) before or simultaneously with the first reset control signal, and the data write And after the end of the compensation phase (scanning signal becomes inactive level again) or at the end, it becomes active level again, so as to emit light based on the newly written data of the current display frame.
  • the first reset control signal changes from an active level to an inactive level one clock cycle before, and changes to an active level again three clock cycles after the end of the data writing phase.
  • the voltage of the first electrode of the light-emitting element is reset.
  • the lighting control signal can also be set in other ways, as long as the inactive level is maintained during the reset phase and the data writing and compensation phase.
  • the light-emitting element may be an organic light-emitting diode (OLED), the first stage of which is the anode of the OLED, and the second stage is the cathode of the OLED.
  • OLED organic light-emitting diode
  • the first power supply voltage VDD may be a DC voltage greater than 0, such as 5V, 4.6V, or the like.
  • the second power supply voltage VSS may be a DC voltage less than or equal to 0, such as 0V, -2V, or the like.
  • the first reset voltage and the second reset voltage may be the same, for example, both are the second power supply voltage VSS, and of course the two may also take other different values less than or equal to 0.
  • the threshold voltage Vth of the drive transistor (first transistor T1) in the drive circuit may be greater than or equal to -5V and less than or equal to -2V, preferably, Vth may be greater than or equal to -4V and less than or equal to -2.5V; for example, Vth can be -4V, -3.5V, -3V or -2.5V, but not limited thereto.
  • oxide transistors are used to reduce the leakage in the circuit, and since the light-emitting control signal is used to control the reset of the voltage on the first pole of the light-emitting element, the length of time is greatly lengthened.
  • the reset time of the second reset voltage on the light-emitting element is ensured, the voltage on the light-emitting element is completely released, and the signal overhead is saved; and the second transistor of the data writing circuit and the third transistor of the compensation circuit are of the same type
  • an oxide transistor it can be driven by the same signal (that is, the scan signal), so there is no need for two separate signals, and signal overhead can also be saved, which is conducive to the design of narrow borders and the signal generation circuit that generates each signal (for example, The reduction of the overall power consumption of the GOA circuit).
  • 1D-1E show circuit diagrams and corresponding timing diagrams of yet another exemplary circuit structure of the pixel circuit.
  • a third reset circuit is added.
  • the third reset circuit is used for applying a third reset voltage to the first terminal (ie, the second node) of the driving transistor under the control of the third reset control signal.
  • the third reset control signal may be the first reset control signal or be synchronized with the first reset control signal.
  • the third reset circuit includes a reset transistor (Tr), the gate of the reset transistor is used to receive the third reset control signal, the first pole of the sixth transistor and the second nodes, and the second pole of the sixth transistor is used to receive the third reset voltage.
  • the third reset voltage is a DC voltage, for example, 5V, or the same as the first power supply voltage, so as to reduce wiring.
  • the reset transistor can also be selected as an oxide transistor.
  • the timing diagram shown in FIG. 1E is the same as that in FIG. 1C. The only difference is that in the reset phase, the reset transistor (Tr) is turned on under the control of the first reset control signal (RST), the third reset voltage is applied to the second node (N2), and the first node is also pulled down to the first reset voltage.
  • the gate-source voltage of the first transistor (T1) can also be reset, which is conducive to accelerating the recovery speed of the first transistor, thus improving the hysteresis phenomenon of the first transistor and increasing the hysteresis recovery speed. It is beneficial to improve the stability of the first transistor, thereby maintaining the brightness of the display screen when switching between high and low frequency displays (for example, switching from video to displaying still images), and reducing the risk of shaking.
  • One application for using transistors based on LTPO technology is to reduce drive power consumption when displaying at low frequencies.
  • the leakage current of the LTPS transistor is large.
  • a high data refresh rate for example, 60Hz, that is, 1s
  • Refresh 60 times to charge the capacitor continuously, which consumes a lot of power.
  • LTPO transistors are oxide transistors with a small leakage current, allowing the voltage on the capacitor to be maintained for a longer period of time, so it is possible to connect transistors in parts of the circuit that are prone to leakage (for example, its first pole or second pole with one of the capacitors)
  • the electrode or the transistor directly connected to the gate of the driving transistor uses an oxide transistor (IGZO transistor), so when displaying a still image, data can be refreshed at a very low frequency (for example, 1Hz, that is, refreshed once within 1s), so that
  • the pixel circuit is adapted to realize low-frequency driving, and the power consumption of the display panel is reduced. Therefore, the example pixel circuits introduced in this disclosure all use LTPO transistors.
  • the content to be displayed on the display panel may require a high data refresh rate, such as a frequency of 60Hz, that is, 60 refreshes per second, and the data writing of all rows of pixels is completed between two refreshes (1s/60) Input, the duration between the start of data writing in the first row of pixel circuits and the completion of data writing in the last row of pixel circuits corresponds to the duration of one display frame, so in this case 1s includes 60 display frames.
  • the display data may not require a high data refresh rate, such as a still image, which only needs a data refresh rate of 1 Hz, that is, the display data is only updated once a second. Since the general clock signal is determined, the duration of the display frame is constant relative to different data refresh frequencies. In this way, the first display frame (called the write frame) of the display cycle (for example, 1s) is completed Data is written to the pixel circuits of all rows, and each pixel circuit still controls the light-emitting element to emit light according to the voltage on its storage capacitor and according to the light-emitting control signal in the subsequent display frame (called holding frame or frame skipping).
  • the write frame the display cycle
  • FIGS. 2A-2B show a circuit diagram of a first exemplary circuit structure of a pixel circuit and a corresponding timing diagram in conjunction with low frequency display.
  • the example circuit structure shown in FIG. 2A is the same as the example circuit structure shown in FIG. 1B, except that the transistor types and/or respective control signals applied to the data writing circuit, the compensation circuit, and the second reset circuit are the same as those shown in FIG. 1B. s difference.
  • FIG. 2A compared with the circuit shown in FIG. 1B , fewer oxide transistors are used, that is, only the third transistor and the sixth transistor are oxide transistors, so the speed is faster.
  • the data writing circuit includes a second transistor (T2), the gate of the second transistor is used to receive the scan signal, the first pole of the second transistor is used to receive the data signal, and the second transistor The second pole of is connected to said second node (N2).
  • the second transistor is a low temperature polysilicon transistor.
  • the compensation circuit includes a third transistor (T3) and a storage capacitor (Cs), the gate of the third transistor (T3) is used to receive the compensation control signal (no longer a scanning signal), and the third transistor
  • the first pole of the third transistor is connected to the third node
  • the second pole of the third transistor is connected to the first pole of the storage capacitor and the first node
  • the second pole of the storage capacitor is connected to the first
  • the power supply end is used for receiving the first power supply voltage. Since the second pole of the third transistor ( T3 ) is connected to the first pole of the storage capacitor, the third transistor is an oxide transistor.
  • the second reset circuit includes a seventh transistor (T7), the gate of the seventh transistor is used to receive the second reset control signal (scanning signal instead of light emission control signal), the first of the seventh transistor The electrode is connected to the first electrode of the light emitting element, and the second electrode of the seventh transistor is used to receive the second reset voltage.
  • the seventh transistor is a low temperature polysilicon transistor.
  • each display frame (such as , 60 display frames within 1 s) are all the same as the timing of writing frames as described with reference to FIGS.
  • a reset phase As shown in FIG. 2B , for a writing frame, a reset phase, a data writing and compensation phase ( t2 ), and a light emitting phase ( t3 ) are included.
  • the first reset control signal is at an active level, and the scanning signal, the compensation control signal, and the light emission control signal are at an inactive level.
  • the sixth transistor (T6) is turned on, and the rest of the transistors are turned off, so as to provide the first reset voltage to the first node (N1).
  • the first node voltage is Vint1
  • the voltages of the second node, the third node, and the first pole (fourth node) of the light emitting element float after the previous stage is completed.
  • the first reset control signal and the light emission control signal are at an inactive level, and the scanning signal and the compensation control signal are at an active level.
  • the first transistor T1, the second transistor T2, the third transistor T3 and the seventh transistor T7 are turned on, and the other transistors are turned off, the first transistor T1 forms a diode connection, and the data signal Data passes through the second transistor T2, the first transistor T1 and the third transistor T3 charge the first node N1 until the charging ends when the voltage of the first node N1 is Vdata+Vth, the voltage of the second node N2 is Vdata, and the voltage of the third node N3 is Vdata+Vth, thus completing The threshold voltage Vth of the first transistor T1 is extracted and the data voltage Vdata is written. At this time, the voltage on the storage capacitor is Vdata+Vth-VDD, that is, the threshold voltage Vth of the first transistor T1 is stored in the storage capacitor.
  • a second reset voltage is also applied to the first pole of the light-emitting element, so that the subsequent light is emitted according to the written data.
  • the light-emitting control signal is at an active level, and the scanning signal, the compensation control signal, the first reset control signal and the second reset control signal are at an inactive level.
  • the first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on, and the other transistors are turned off, and the current flows from VDD to VSS.
  • the voltage of the first node N1 is still Vdata+Vth due to the storage capacitor
  • the second The voltage of the node is VDD
  • the voltage of the third node N3 is the voltage of the first pole of the light emitting element.
  • the compensation control signal may maintain an inactive level during the sustain frame.
  • the display brightness is related to the duty ratio of the light emission control signal
  • maintaining the light emission control signal (EM) in the frame still needs to be related to the duty cycle of the light emission control signal written in the frame.
  • the dummy ratio is the same instead of remaining in effect.
  • the first pole of the light-emitting element will have a charge release process due to the existence of parasitic capacitance, and in the data writing and compensation phase
  • the light-emitting control signal After completing the reset of the voltage of the first pole (shown as N4) of the light-emitting element, when entering the light-emitting stage, the light-emitting control signal becomes an active level again, and there will be a process of charging the parasitic capacitance, so in the light-emitting element There will be a process of voltage decrease and increase on the first pole.
  • the holding frame in order to keep the display brightness of the light emitting element in each display frame the same, it is also necessary to form the same process of decreasing and increasing the voltage on the first electrode of the light emitting element in each holding frame. In this way, for each display frame (writing frame and each holding frame), the parasitic capacitance of the light-emitting element is charged from the second reset voltage until the voltage is stable when entering the light-emitting phase.
  • a lighting reset phase corresponding to the data writing and compensation phase in the writing frame and a lighting phase corresponding to the lighting phase in the writing frame are included in the holding frame.
  • the second reset control signal is at an active level
  • the writing control signal, the compensation control signal, the first reset control signal and the lighting control signal are all at an inactive level.
  • the first transistor T1, the second transistor T2 and the seventh transistor T7 controlled only by the scanning signal are turned on, and the other transistors are turned off, and the light-emitting element will not emit light.
  • the first transistor T7 of the light-emitting element can Apply a second reset voltage (Vint1) to the pole.
  • the setting method of each signal in the light-emitting phase and the working process of the circuit are similar to those in the writing frame, that is, only EM is an active level, and will not be repeated here.
  • the scanning signal, the compensation control signal, the first reset control signal and the light-emitting control signal are all at inactive levels.
  • 3A-3B show the circuit diagram of the second exemplary circuit structure of the pixel circuit and the corresponding timing diagram in combination with the low frequency display.
  • the second example circuit structure is mostly the same as the first example structure shown in FIG. 2A , only the different parts will be described below.
  • the drive circuit, data writing circuit, compensation circuit, light emission control circuit, and second reset circuit are all the same as those in the first exemplary structure described with reference to FIG. 2A .
  • the first reset circuit includes a sixth transistor (T6), the gate of the sixth transistor is used to receive the first reset control signal, the first pole of the sixth transistor and the The third node is connected, and the second pole of the sixth transistor is used to receive the first reset voltage.
  • T6 sixth transistor
  • the third transistor directly connected to the storage capacitor can be selected as an oxide transistor to avoid leakage of the storage capacitor.
  • the writing frame also for the writing frame, it includes a reset phase, a data writing and compensation phase ( t2 ), and a light emitting phase ( t3 ).
  • the first reset control signal and the compensation control signal are at an active level, and the scanning signal and the light emission control signal are at an inactive level.
  • the third transistor (T3) and the sixth transistor (T6) are turned on, and the rest of the transistors are turned off, so that the first reset voltage is passed through the turned-on T3 and T6 are provided to the first node (N1), and the voltage of the first node is Vint1 at this time, and the voltages of the second node, the third node, and the first pole of the light-emitting element are floating after the previous stage is completed.
  • the first reset control signal and the light emission control signal are at an inactive level, and the scanning signal and the compensation control signal are at an active level.
  • the first transistor T1, the second transistor T2, the third transistor T3 and the seventh transistor T7 are turned on, and the other transistors are turned off, the first transistor T1 forms a diode connection, and the data signal Data passes through the second transistor T2, the first transistor T1 and the third transistor T3 charge the first node N1 until the charging ends when the voltage of the first node N1 is Vdata+Vth, the voltage of the second node N2 is Vdata, and the voltage of the third node N3 is Vdata+Vth, thus completing The threshold voltage Vth of the first transistor T1 is extracted and the data voltage Vdata is written. At this time, the voltage on the storage capacitor is Vdata+Vth-VDD, that is, the threshold voltage Vth of the first transistor T1 is stored in the storage capacitor.
  • a second reset voltage is also applied to the first pole of the light-emitting element, so that the subsequent light is emitted according to the written data.
  • the light-emitting control signal is at an active level, and the scanning signal, the compensation control signal, the first reset control signal and the second reset control signal are at an inactive level.
  • the first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on, and the other transistors are turned off, and the current flows from VDD to VSS.
  • the voltage of the first node N1 is still Vdata+Vth due to the storage capacitor
  • the second The voltage of the node is VDD
  • the voltage of the third node N3 is the voltage of the first pole of the light emitting element.
  • a lighting reset phase corresponding to the data writing and compensation phase in the writing frame and a lighting phase corresponding to the lighting phase in the writing frame are included in the holding frame.
  • FIGS. 4A-4B show a circuit diagram of a third exemplary circuit structure of the pixel circuit and a corresponding timing diagram in combination with a low frequency display.
  • the driving circuit, the data writing circuit, the light emission control circuit, the first reset circuit and the second reset circuit are all the same as those in the first example structure as described with reference to FIG. 2A .
  • the compensation circuit includes a third transistor (T3), an eighth transistor (T8) and a storage capacitor.
  • the gate of the third transistor (T3) is used to receive the scan signal, the first pole of the third transistor is connected to the third node, and the second pole of the third transistor is connected to the fifth node , the third transistor ( T3 ) can connect the third node to the fifth node under the control of the scan signal.
  • the first pole of the eighth transistor (T8) is connected to the fifth node
  • the second pole of the eighth transistor (T8) is connected to the first pole of the storage capacitor and the first node
  • the storage capacitor The second pole of the transistor is connected to the first power supply terminal for receiving the first power supply voltage (VDD)
  • the eighth transistor (T3) can connect the fifth node to the first node under the control of the compensation control signal
  • the third node is connected to the first node (the scanning signal is at an active level when performing compensation).
  • the eighth transistor directly connected to the storage capacitor can be selected as an oxide transistor to avoid leakage of the storage capacitor.
  • the writing frame also for the writing frame, it includes a reset phase, a data writing and compensation phase ( t2 ), and a light emitting phase ( t3 ).
  • the first reset control signal and the compensation control signal are at an active level, and the scanning signal and the light emission control signal are at an inactive level.
  • the sixth transistor (T6) and the eighth transistor (T8) are turned on, and the rest of the transistors are turned off, so that the first reset voltage is passed through the turned-on T3 and T6 are supplied to the first node (N1), at this time the voltages of the first node and the fifth node are Vint1, and the voltages of the second node, the third node, and the first pole (the fourth node) of the light-emitting element are the previous one The voltage at the end of the phase.
  • the first reset control signal and light emission control signal are set to inactive level, and the scan signal and compensation control signal are set to active level.
  • the first transistor T1, the second transistor T2, the third transistor T3, the seventh transistor T7 and the eighth transistor T8 are turned on, and the other transistors are turned off, the first transistor T1 forms a diode connection, and the data signal Data passes through the second transistor in sequence T2, the first transistor T1, the third transistor T3 and the eighth transistor T8 charge the first node N1 until the voltage of the first node N1 is Vdata+Vth, the charging ends, the voltage of the second node N2 is Vdata, and the voltage of the third node N2 The voltage of N3 and the fifth node N5 is Vdata+Vth, thereby completing the extraction of the threshold voltage Vth of the first transistor T1 and the writing of the data voltage Vdata.
  • the voltage value on the storage capacitor is Vdata+Vth-VDD, that is, the first A threshold voltage Vth of the transistor T1 is stored in the storage capacitor.
  • a second reset voltage is also applied to the first pole of the light-emitting element, so that the subsequent light is emitted according to the written data.
  • the light-emitting control signal is at an active level, and the scanning signal, the compensation control signal, the first reset control signal and the second reset control signal are at an inactive level.
  • the first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on, and the other transistors are turned off, and the current flows from VDD to VSS.
  • the voltage of the first node N1 is still Vdata+Vth due to the storage capacitor
  • the second The voltage of the node is VDD
  • the voltage of the third node N3 is the voltage of the first pole (N4) of the light-emitting element
  • the voltage of the fifth node is floating after the previous stage.
  • a lighting reset phase corresponding to the data writing and compensation phase in the writing frame and a lighting phase corresponding to the lighting phase in the writing frame are included in the holding frame.
  • Each example circuit structure and corresponding working process described above with reference to FIGS. 2A, 3A and 4A, and each transistor as will be described later can be selected as P-type or N-type according to needs, and the corresponding effective levels can be respectively low level and high level.
  • the transistor is P-type
  • the first pole refers to the source
  • the second pole refers to the drain
  • the first pole refers to the drain
  • the second pole refers to the source.
  • the pixel circuit described above with reference to FIG. 1A-FIG. 4B adopts LPTO technology, so it can have low driving power consumption when displaying at low frequency, and because the light-emitting reset phase is still set in the holding frame, it can be used for every The display brightness of each display frame in a display cycle is balanced, so it has a good display effect.
  • the above-mentioned pixel circuit brings the above-mentioned benefits, but also has certain defects.
  • a lighting reset phase is set in the holding frame, and the scanning signal is a valid signal in the lighting reset phase, so even in the case of low-frequency display, the scanning signal is still switched at high frequency, combined with Fig.
  • the voltage of the first node N1 is Vdata+Vth due to the existence of the storage capacitor, and the voltage of the second node is VDD, it is hoped that the voltages of these two nodes are also maintained in the holding frame In this way, the display brightness of the light-emitting element of each pixel circuit can be stabilized during low-frequency display, thereby making the display picture of the display panel stable.
  • the embodiment of the present disclosure also proposes an improved pixel circuit, so as to realize the above-mentioned benefits of the pixel circuit and also make the display picture of the display panel more stable during low-frequency display.
  • FIG. 5 shows a structural block diagram of an improved pixel circuit according to an embodiment of the present disclosure in combination with a low frequency display.
  • the structure of the pixel circuit shown in FIG. 5 is the same as the pixel circuit described with reference to FIG. 1A , except that the signals controlling each part of the circuit have been adjusted.
  • the pixel circuit 10 includes: a driving circuit 101, a data writing circuit 102, a compensation circuit 103, a light emission control circuit 104 (104-1 and 104-2), a first reset circuit 105 and a second reset circuit 106 .
  • the driving circuit 101 includes a control terminal, a first terminal and a second terminal, and is used for controlling the driving current flowing through the first terminal and the second terminal for driving the light-emitting element to emit light.
  • the data writing circuit 102 is used for writing data signals into the first end (N2) of the driving circuit under the control of the writing control signal.
  • the compensation circuit 103 is used to electrically connect the control terminal (N1) and the second terminal (N3) of the driving circuit under the control of the compensation control signal, or under the control of the compensation control signal and the write control signal, and store the The voltage of the control terminal of the drive circuit.
  • the light emitting control circuit 104 is used for making the driving current flow through the light emitting element under the control of the light emitting control signal.
  • the light emission control circuit may include a first light emission control circuit and a second light emission control circuit, and correspondingly, the light emission control signal may include a first light emission control signal and a second light emission control signal.
  • the first light emission control circuit is used for applying the first power supply voltage (VDD) of the first power supply terminal to the first terminal of the driving circuit under the control of the first light emission control signal (EM1).
  • the second light emission control circuit is used for applying the driving current from the second terminal of the driving circuit to the first pole of the light emitting element under the control of the second light emission control signal (EM2).
  • the first light emission control signal and the second light emission control signal may be the same or different signals.
  • the first reset circuit is used for applying the first reset voltage to the control terminal of the driving circuit under the control of the first reset control signal.
  • the second reset circuit is used for applying the second reset voltage to the first pole of the light emitting element under the control of the second reset control signal.
  • the write control signal is made inactive in the hold frame, so that the data does not It will be input to the second node N2, so it will not cause the voltage fluctuation of the first node N1. Due to the better leakage current characteristics of the oxide transistor, the voltage of the first node N1 can still be maintained at the Vdata+ at the end of the previous light-emitting phase Vth.
  • the voltage of the second node N2 is VDD, therefore, the first node N1 and the second node N1
  • the second reset control signal that appears in each display frame can be considered to have the same characteristics, for example, the level changes from inactive level to active level at the same moment in each display frame, and then continues for the same time Restore invalid level.
  • the first light-emitting control signal and the second The light emission control signal is set to a different signal in the hold frame.
  • the first light emission control signal (EM1) and the second light emission control signal (EM2) are synchronized in the writing frame, and in each holding frame after the writing frame, the second light emission control signal (EM2) is an active level, and the first light emission control signal has the same characteristics as the first light emission control signal written in the frame.
  • the first light-emitting control circuit is enabled (that is, the fourth transistor T4 is turned on), so that the first power supply voltage VDD is applied to the second node N2, and the second The voltage of the node N2 is stabilized at VDD, which further stabilizes the display brightness during the light-emitting phase.
  • FIG. 6A-6B show the circuit diagram of the first example circuit structure of the improved pixel circuit and the corresponding timing diagram in combination with the low frequency display. This corresponds to the circuit diagram described above with reference to Fig. 2A.
  • the drive circuit includes a first transistor (T1), the gate of the first transistor is connected to the first node (N1) as the control terminal of the drive circuit, so The first pole of the first transistor is used as the first terminal of the driving circuit and connected to the second node (N2), and the second pole of the first transistor is used as the second terminal of the driving circuit and the third node (N3 )connect.
  • the data writing circuit includes a second transistor (T2), the gate of the second transistor is used to receive the write control signal (Sp), and the first pole of the second transistor is used to receive the data signal ( Vdata), the second pole of the second transistor is connected to the second node (N2).
  • the compensation circuit includes a third transistor and a storage capacitor, the gate of the third transistor (T3) is used to receive the compensation control signal (C), the first pole of the third transistor and the third node connected, the second pole of the third transistor is connected to the first pole of the storage capacitor and the first node, the second pole of the storage capacitor is connected to the first power supply terminal for receiving the first power supply voltage.
  • the first light emission control circuit includes a fourth transistor (T4), the gate of the fourth transistor is used to receive the first light emission control signal (EM1), and the first pole of the fourth transistor is connected to the first The power supply end is used to receive the first power supply voltage, and the second pole of the fourth transistor is connected to the second node (N2).
  • the second light emission control circuit includes a fifth transistor (T5), the gate of the fifth transistor is used to receive the second light emission control signal (EM2), the first electrode of the fifth transistor and the first pole of the fifth transistor Three nodes (N3) are connected, and the second pole of the fifth transistor is connected to the first pole (as the fourth node) of the light emitting element.
  • T5 the gate of the fifth transistor is used to receive the second light emission control signal (EM2), the first electrode of the fifth transistor and the first pole of the fifth transistor Three nodes (N3) are connected, and the second pole of the fifth transistor is connected to the first pole (as the fourth node) of the light emitting element.
  • the first reset circuit includes a sixth transistor (T6), the gate of the sixth transistor is used to receive the first reset control signal (RST), the first pole of the sixth transistor and the first nodes, and the second pole of the sixth transistor is used to receive the first reset voltage.
  • T6 the gate of the sixth transistor is used to receive the first reset control signal (RST), the first pole of the sixth transistor and the first nodes, and the second pole of the sixth transistor is used to receive the first reset voltage.
  • the second reset circuit includes a seventh transistor (T7), the gate of the seventh transistor is used to receive the second reset control signal (Scan), the first pole of the seventh transistor and the light emitting element The first pole of the seventh transistor is connected to the second pole of the seventh transistor for receiving the second reset voltage.
  • the second reset control signal may be a scan signal of the pixel circuits, for example, a row-shifted signal generated by the GOA circuit, which is provided to each row of pixel circuits row by row.
  • the third transistor T3 and the sixth transistor T6 are still selected as oxide transistors, while the remaining transistors are still selected as low temperature polysilicon transistors.
  • timing diagram described below with reference to FIG. 6B is for the case of low-frequency display, while in the case of high-frequency display, the driving timing of each display frame is the same as the timing of writing frames as described with reference to FIG. 6B , Therefore no description is given.
  • a reset phase As shown in FIG. 6B , for a writing frame, a reset phase, a data writing and compensation phase, and a light emitting phase are included.
  • the first reset control signal is at an active level
  • the write control signal, the second reset control signal, the compensation control signal, the first light emission control signal and the second light emission control signal are at an inactive level
  • the sixth transistor (T6) is turned on, and the rest of the transistors are turned off, so as to provide the first reset voltage to the first node (N1).
  • the first node voltage is Vint1
  • the voltages of the second node, the third node, and the first pole (fourth node) of the light emitting element float after the previous stage is completed.
  • the first reset control signal, the first light emission control signal and the second light emission control signal are set to inactive level, and the write control signal, second reset control signal and compensation control signal are active level.
  • the first transistor T1, the second transistor T2, the third transistor T3 and the seventh transistor T7 are turned on, and the other transistors are turned off, the first transistor T1 forms a diode connection, and the data signal Data passes through the second transistor T2, the first transistor T1 and the third transistor T3 charge the first node N1 until the charging ends when the voltage of the first node N1 is Vdata+Vth, the voltage of the second node N2 is Vdata, and the voltage of the third node N3 is Vdata+Vth, thus completing The threshold voltage Vth of the first transistor T1 is extracted and the data voltage Vdata is written. At this time, the voltage on the storage capacitor is Vdata+Vth-VDD, that is, the threshold voltage Vth of the first transistor T1 is stored in the storage capacitor.
  • a second reset voltage is also applied to the first pole of the light-emitting element, so that the subsequent light is emitted according to the written data.
  • the first light-emitting control signal and the second light-emitting control signal are set to active levels, and the writing control signal, the second reset control signal, the compensation control signal, the first reset control signal and the second reset control signal are: invalid level.
  • the first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on, and the other transistors are turned off, and the current flows from VDD to VSS.
  • the voltage of the first node N1 is still Vdata+Vth due to the storage capacitor
  • the second The voltage of the node is VDD
  • the voltage of the third node N3 is the voltage of the first pole of the light emitting element.
  • the write control signal (Sp) and the second reset control signal (Scan) are synchronized.
  • the first light emission control signal (EM1) is maintained at an active level and the write control signal (Sn) is maintained at an inactive level in the sustain frame.
  • the compensation control signal (C) and the first reset signal (RST) are also maintained at inactive levels.
  • the voltage of the second node is maintained at the first power supply voltage VDD in each sustaining frame.
  • each holding frame includes a lighting reset phase corresponding to the data writing and compensation phase in the writing frame and a lighting phase corresponding to the lighting phase in the writing frame.
  • the first light-emitting control signal is at an active level
  • the writing control signal is at an inactive level
  • the second reset control signal is at an active level
  • the compensation control signal is at an active level
  • the first reset control signal and the second The lighting control signals are all inactive levels.
  • the first transistor T1, the fourth transistor T4, and the seventh transistor T7 are turned on, and the rest of the transistors are turned off, and the light-emitting element does not emit light.
  • a second reset voltage can be applied to the first pole of the light-emitting element. (Vint1), the voltage of the second node N2 remains at VDD.
  • the first light-emitting control signal is at an active level
  • the writing control signal is at an inactive level
  • the second light-emitting control signal is at an active level
  • the second reset control signal is at an active level
  • the compensation control signal the first reset control signal
  • the signals are all inactive levels.
  • the driving current will flow from the first power supply voltage to the light emitting element through T4, T1, T5, making it emit light.
  • the first light-emitting control signal is at an active level
  • the writing control signal is at an inactive level
  • the second reset control signal, compensation control signal, The first reset control signal and the second light emission control signal are at an inactive level.
  • the second transistor controlled by the write control signal remains turned off, so the data write circuit is disabled, so even if the second reset control signal (which may be a scan signal) needs The high frequency makes the display brightness uniform, but because the write control signal is independent and invalid, the data voltage will not be frequently written into the second node N2, so the voltage of the second node N2 can be relatively stable and will not affect The voltage of the first node N1 interferes.
  • the fourth transistor controlled by the first light emission control signal is kept turned on, so the first light emission control circuit is kept enabled, so the voltage of the second node N2 is kept at VDD, and better stability is obtained .
  • FIG. 7A-7B show a circuit diagram of a second exemplary circuit structure of another pixel circuit and a corresponding timing diagram in conjunction with low frequency display. This corresponds to the circuit diagram described above with reference to Figure 3A.
  • the second exemplary circuit structure is mostly the same as the first exemplary structure in FIG. 6A , only the different parts will be described below.
  • the drive circuit, data writing circuit, compensation circuit, light emission control circuit, and second reset circuit are all the same as those in the first exemplary structure described with reference to FIG. 6A .
  • the first reset circuit includes a sixth transistor (T6), the gate of the sixth transistor is used to receive the first reset control signal, the first pole of the sixth transistor and the The third node is connected, and the second pole of the sixth transistor is used to receive the first reset voltage.
  • T6 sixth transistor
  • the third transistor ( T3 ) directly connected to the storage capacitor can be selected as an oxide transistor to avoid leakage of the storage capacitor.
  • the writing frame similarly, for the writing frame, it includes a reset phase, a data writing and compensation phase, and a light emitting phase.
  • the first reset control signal and the compensation control signal are at an active level, and the write control signal, the second reset control signal, the first light emission control signal and the second light emission control signal are at an inactive level.
  • the third transistor (T3) and the sixth transistor (T6) are turned on, and the rest of the transistors are turned off, so that the first reset voltage is passed through the turned-on T3 and T6 are provided to the first node (N1), and the voltage of the first node is Vint1 at this time, and the voltages of the second node, the third node, and the first pole of the light-emitting element are floating after the previous stage is completed.
  • the driving mode and working process in the data writing and compensation phase and the light emitting phase are the same or similar to the process described with reference to FIG. 6B , so the description thereof is omitted here.
  • the writing control signal and the second reset control signal are synchronized.
  • the first light emission control signal is maintained at an active level and the write control signal is maintained at an inactive level in the sustain frame.
  • the compensation control signal and the first reset signal are also maintained at inactive levels.
  • the voltage of the second node is maintained at the first power supply voltage VDD in each sustaining frame.
  • each holding frame includes a lighting reset phase corresponding to the data writing and compensation phase in the writing frame and a lighting phase corresponding to the lighting phase in the writing frame.
  • FIG. 8A-8B show the circuit diagram and the corresponding timing diagram of the third exemplary circuit structure of the other pixel circuit in combination with the low frequency display. This corresponds to the circuit diagram described above with reference to Fig. 4A.
  • the drive circuit, the data writing circuit, the light emission control circuit (first and second light emission control circuits), the first reset circuit and the second reset circuit are all the same as the first exemplary structure described with reference to FIG. 2A. in the same.
  • the compensation circuit includes a third transistor (T3), an eighth transistor (T8) and a storage capacitor.
  • the gate of the third transistor (T3) is used to receive a write control signal, the first pole of the third transistor is connected to the third node, and the second pole of the third transistor is connected to the fifth node , the third transistor ( T3 ) can connect the third node to the fifth node under the control of the write control signal.
  • the first pole of the eighth transistor (T8) is connected to the fifth node
  • the second pole of the eighth transistor (T8) is connected to the first pole of the storage capacitor and the first node
  • the storage capacitor The second pole of the transistor is connected to the first power supply terminal for receiving the first power supply voltage (VDD)
  • the eighth transistor (T3) can connect the fifth node to the first node under the control of the compensation control signal.
  • the eighth transistor directly connected to the storage capacitor can be selected as an oxide transistor to avoid leakage of the storage capacitor.
  • the writing frame also for the writing frame, it includes a reset phase, a data writing and compensation phase ( t2 ), and a light emitting phase ( t3 ).
  • the first reset control signal and the compensation control signal are at an active level, and the write control signal, the second reset control signal, the first light emission control signal and the second light emission control signal are at an inactive level.
  • the sixth transistor (T6) and the eighth transistor (T8) are turned on, and the rest of the transistors are turned off, so that the first reset voltage is passed through the turned-on T3 and T6 are supplied to the first node (N1), at this time the voltages of the first node and the fifth node are Vint1, and the voltages of the second node, the third node, and the first pole (the fourth node) of the light-emitting element are the previous one voltage at the end of the phase.
  • the first reset control signal, the first light-emitting control signal and the second light-emitting control signal are at an inactive level, and the writing control signal, the second reset control signal and the compensation control signal are at an active level. flat.
  • the first transistor T1, the second transistor T2, the third transistor T3, the seventh transistor T7 and the eighth transistor T8 are turned on, and the other transistors are turned off, the first transistor T1 forms a diode connection, and the data signal Data passes through the second transistor in sequence T2, the first transistor T1, the third transistor T3 and the eighth transistor T8 charge the first node N1 until the voltage of the first node N1 is Vdata+Vth, the charging ends, the voltage of the second node N2 is Vdata, and the voltage of the third node N2 The voltage of N3 and the fifth node N5 is Vdata+Vth, thereby completing the extraction of the threshold voltage Vth of the first transistor T1 and the writing of the data voltage Vdata.
  • the voltage value on the storage capacitor is Vdata+Vth-VDD, that is, the first A threshold voltage Vth of the transistor T1 is stored in the storage capacitor.
  • the second reset control signal is at an active level, so the second reset voltage is also applied to the first pole of the light-emitting element, so that the subsequent light is emitted according to the written data.
  • the first light-emitting control signal and the second light-emitting control signal are at an active level, and the writing control signal, compensation control signal, first reset control signal, and second reset control signal are at an inactive level.
  • the first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on, and the other transistors are turned off, and the current flows from VDD to VSS.
  • the voltage of the first node N1 is still Vdata+Vth due to the storage capacitor
  • the second The voltage of the node is VDD
  • the voltage of the third node N3 is the voltage of the first pole (N4) of the light-emitting element
  • the voltage of the fifth node is floating after the previous stage.
  • the writing control signal and the second reset control signal are synchronized.
  • the first light emission control signal is kept at an active level
  • the writing control signal is kept at an inactive level
  • the compensation control signal and the first reset control signal are kept at an inactive level.
  • the voltage of the second node is maintained at the first power supply voltage VDD in each sustaining frame.
  • each holding frame includes a lighting reset phase corresponding to the data writing and compensation phase in the writing frame and a lighting phase corresponding to the lighting phase in the writing frame.
  • the improved pixel circuit described with reference to Fig. 5-Fig. 8B is an improvement of the stability of the display picture for the pixel circuit described in Fig. 1A and Fig. 2A-4B respectively, by keeping the high-frequency
  • the signal second reset control signal is independent from the write control signal, and makes the write control signal inactive level in the hold frame, or additionally also sets the first light emission control signal and the second light emission control signal to Different signals, and set the first light-emitting control signal to an active level in the hold frame, so that the voltage of the second node N2 can be stabilized during low-frequency display, so the voltage difference between the first node N1 and the second node N2 Stable, so that the display brightness of the pixels is more stable, and the display effect of the display panel is also more stable.
  • the present disclosure also provides a driving method for the above pixel circuit.
  • the driving method includes: in the case that each display period sequentially includes a writing frame and at least one holding frame, in the writing frame, synchronizing the writing control signal and the second reset control signal, and
  • the writing frame includes: a reset phase, a data writing and compensation phase, and a light-emitting phase; in each holding frame, the write control signal remains at an inactive level, and the second reset control signal and the write
  • the second reset control signal of the incoming frame has the same characteristics, and includes in the holding frame: a lighting reset phase corresponding to the data writing and compensation phase of the writing frame and a lighting phase corresponding to the lighting phase of the writing frame .
  • the driving method further includes: synchronizing the first light emission control signal (EM1) and the second light emission control signal (EM2) in a write frame; and making the first light emission control signal (EM2)
  • the light emission control signal (EM1) is at an active level, and the second light emission control signal has the same characteristics as the second light emission control signal written into the frame.
  • a display device is also provided.
  • FIG. 9 shows a schematic diagram of a display device 900 according to an embodiment of the present disclosure.
  • the display device 900 includes: a plurality of pixel units 60 distributed in an array.
  • each pixel unit 60 may include any pixel circuit described above with reference to FIGS. 1A-8B , for example, the pixel circuit shown in FIG. 6A . It is similar that the pixel unit includes other example pixel circuits, only the type and method of the signal lines connected to each pixel unit are adaptively changed.
  • the display device 900 may also include a plurality of write control lines, a plurality of compensation control lines, a plurality of data lines, a plurality of light emission control lines (a plurality of first light emission control lines and a plurality of second light emission control lines) and a plurality of reset Control lines (a plurality of first reset control lines and a plurality of second reset control lines). It should be noted that only part of the pixel units 60 and related connections are shown in FIG. 9 .
  • S N represents the write control line of the Nth row (provides the Sp signal)
  • S N+1 represents the write control line of the N+1th row
  • C N represents the compensation control line of the Nth row (provides the C signal)
  • C N+1 represents the compensation control line of row N+1
  • R N1 and R N2 represent the first reset control line (providing RST signal) and second reset control line (providing Scan) of row N
  • R N1+ 1 and R N2+1 represent the first reset control line and the second reset control line of the N+1th row
  • D M represents the data signal line of the Mth column (providing Vdata)
  • D M+1 represents the M+1th column
  • L N1 and L N2 represent the first light emitting control line (providing EM1) and the second light emitting control line (providing EM2) of the Nth row
  • L N1+1 and L N2+1 represent the N+1th row
  • each pixel unit 60 may include any example pixel circuit described above, for example, the pixel circuit shown in FIG. 6A .
  • the writing control line of each row is connected to the data writing circuit in the pixel circuit of this row (in some structures, the pixel circuit shown in dotted line in Fig. 5 or Fig. 8A can also be connected to the compensation circuit) to Provide write control signal;
  • the compensation control line of each row is connected to the compensation circuit in the pixel circuit of this row to provide compensation control signal;
  • the data line of each column is connected to the data writing circuit in the pixel circuit of this column to provide data signal Vdata;
  • the first reset control line of each row is connected to the first reset circuit in the pixel circuit of this row to provide the first reset control signal, and the second reset control line of each row is connected to the second reset circuit in the pixel circuit to provide Provide the second reset control signal;
  • the first light emitting control line of each row is connected to the first light emitting circuit in the pixel circuit of this row to provide the first light emitting control signal,
  • the second light emitting control line of each row is connected to the first light emitting circuit in the pixel circuit
  • the display device shown in FIG. 9 may also include a plurality of first voltage lines, a plurality of second voltage lines, and a plurality of reset voltage lines (or a plurality of first reset voltage lines and a plurality of second reset voltage lines). voltage lines) to respectively provide the first power supply voltage VDD, the second power supply voltage VSS, and the reset voltage Vinit (may include the first reset voltage Vint1 and the second reset voltage Vinit2) (not shown in the figure).
  • the display device 1 may further include a scan driving circuit 20 and a data driving circuit 30 .
  • the data driving circuit 30 can be connected with multiple data lines (D M , D M+1 , etc.)
  • a reset voltage line (not shown in the figure) and so on are connected to respectively supply respective voltages.
  • the scan driving circuit 20 can be connected with various control lines that need to be shifted, such as multiple write control lines ( SN , S N+1, etc.), to provide write control signals; at the same time, it can also be connected with multiple
  • the compensation control line is connected to provide a compensation control signal, and is connected to a plurality of (first and second) lighting control lines ( EN1 , E N1+1 , E N1 , E N1+1, etc.) to provide (first and second ) lighting control signal, and connected with multiple (first and second) reset control lines to provide reset control signal and so on.
  • the scan driving circuit 20 and the data driving circuit 30 may be implemented as semiconductor chips.
  • the display device may also include other components, such as a timing controller, a signal decoding circuit, a voltage conversion circuit, etc. These components may be existing conventional components, and will not be described in detail here.
  • the display device provided in this embodiment may be any product or component with a display function, such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, and navigator.
  • a display function such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, and navigator.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

一种像素电路（10）、显示装置和驱动方法。像素电路（10）包括：驱动电路（101）、数据写入电路（102）、补偿电路（103）、发光控制电路（104）、第一复位电路（105）、第二复位电路（106）和发光元件；驱动电路（101）包括控制端、第一端和第二端；数据写入电路（102）用于在写入控制信号的控制下将数据信号写入驱动电路（101）的第一端；第一复位电路（105）用于在第一复位控制信号的控制下将第一复位电压施加至驱动电路（101）的控制端，第二复位电路（106）用于在第二复位控制信号的控制下将第二复位电压施加至发光元件的第一极，其中，在每个显示周期依次包括一个写入帧和至少一个保持帧的情况下，在写入帧内，写入控制信号和第二复位控制信号同步，在每个保持帧内，写入控制信号保持为无效电平，第二复位控制信号与写入帧的第二复位控制信号具有相同特性。

Description

像素电路、显示装置和驱动方法 技术领域
本申请涉及显示技术领域，尤其涉及一种像素电路、显示装置和像素电路的驱动方法。
背景技术
低温多晶氧化物(LTPO)显示技术由于结合了低温多晶硅(LTPS)和氧化物半导体(例如，氧化铟镓锌IGZO)两种类型的薄膜晶体管，因此可以使显示面板同时具有强驱动能力和低功率消耗的特点，同时适用于高频显示和低频显示，已经越来越成为显示面板中炙手可热的技术。
另一方面，从显示效果方面来说，希望显示面板的显示画面尽量稳定。
因此，需要一种基于LTPO技术的像素电路，并且还可以使得包括多个像素电路的显示面板的显示画面稳定。
发明内容
根据本公开的一方面，提供了一种像素电路，包括：驱动电路、数据写入电路、补偿电路、发光控制电路、第一复位电路、第二复位电路和发光元件；所述驱动电路包括控制端、第一端和第二端，分别与第一节点、第二节点和第三节点连接，且用于控制流经所述第一端和所述第二端的用于驱动发光元件发光的驱动电流；所述数据写入电路用于在写入控制信号的控制下将数据信号写入所述驱动电路的第一端；所述补偿电路用于在补偿控制信号的控制下将所述驱动电路的控制端和第二端电连接，并存储所述驱动电路的控制端的电压；发光控制电路用于在发光控制信号的控制下使得所述驱动电流流经所述发光元件；第一复位电路用于在第一复位控制信号的控制下将第一复位电压施加至所述驱动电路的控制端，第二复位电路用于在第二复位控制信号的控制下将第二复位电压施加至发光元件的第一极，其中，在每个显示周期依次包括一个写入帧和至少一个保持帧的情况下，在写入帧内，所述写入控制信号和所述第二复位控制信号同步，在每个保持帧内，所述写入控制信号保持为无效电平，所述第二复位控制信号与所述写入帧的第二复位控制 信号具有相同特性。
根据本公开的另一方面，提供了一种显示装置，包括：呈阵列分布的多个像素单元，其中，每个所述像素单元包括如上所述的像素电路。
根据本公开的又一方面，还提供了一种用于上述像素电路的驱动方法，包括：在每个显示周期依次包括一个写入帧和至少一个保持帧的情况下，在写入帧内，使所述写入控制信号和所述第二复位控制信号同步，并且所述写入帧包括：复位阶段、数据写入和补偿阶段、以及发光阶段；在每个保持帧内，使所述写入控制信号保持为无效电平，所述第二复位控制信号与所述写入帧的第二复位控制信号具有相同特性，并且所述保持帧包括：与写入帧的数据写入和补偿阶段对应的发光重置阶段以及与写入帧内的发光阶段对应的发光阶段。
根据本公开的实施例，其中，所述发光控制信号包括第一发光控制信号和第二发光控制信号，该驱动方法还包括：在写入帧内使所述第一发光控制信号和所述第二发光控制信号同步，在每个保持帧内，使所述第一发光控制信号保持为有效电平，所述第二发光控制信号与所述写入帧的第二发光控制信号具有相同特性。
附图说明
图1A示出了根据本公开实施例的一种基于LTPO技术的像素电路的结构框图。
图1B-1C示出了该像素电路的示例电路结构的电路图以及对应的时序图。
图1D-1E示出了该像素电路的又一种示例电路结构的电路图以及对应的时序图。
图2A-2B结合低频显示，示出了根据本公开实施例的像素电路的第一种示例电路结构的电路图以及对应的时序图。
图3A-3B结合低频显示，示出了根据本公开实施例的像素电路的第二种示例电路结构的电路图以及对应的时序图。
图4A-4B结合低频显示，示出了根据本公开实施例的像素电路的第三种示例电路结构的电路图以及对应的时序图。
图5结合低频显示，示出了根据本公开实施例的一种基于LTPO技术的 改进的像素电路的结构框图。
图6A-6B结合低频显示，示出了根据本公开实施例的该另一种像素电路的第一种示例电路结构的电路图以及对应的时序图。
图7A-7B结合低频显示，示出了根据本公开实施例的该另一种像素电路的第二种示例电路结构的电路图以及对应的时序图。
图8A-8B结合低频显示，示出了根据本公开实施例的该另一种像素电路的第三种示例电路结构的电路图以及对应的时序图
图9示出了根据本公开实施例的显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1A示出了根据本公开实施例的一种基于LTPO技术的像素电路的结构框图。
如图1A所示，像素电路10包括：驱动电路101、数据写入电路102、补偿电路103、发光控制电路104(104-1和104-2)、第一复位电路105和第二复位电路106。
驱动电路包括控制端、第一端和第二端，且用于控制流经所述第一端和 所述第二端的用于驱动发光元件发光的驱动电流。
数据写入电路用于在扫描信号(Scan)的控制下将数据信号写入所述驱动电路的第一端。
可选地，该扫描信号可以由GOA电路生成，且按行移位施加到各行上的多个所述像素电路，以控制所述像素电路进行数据写入。
此外，如将在后续描述的，针对每个像素电路，控制其内部的各个电路的信号由于与扫描信号需要满足特定的时序关系，因此这些信号也是按行移位的。
补偿电路用于在补偿控制信号的控制下、或在补偿控制信号和扫描信号的控制下将所述驱动电路的控制端和第二端电连接，并存储所述驱动电路的控制端的电压。
发光控制电路用于在发光控制信号的控制下使得所述驱动电流流经所述发光元件。
可选地，发光控制电路可以包括第一发光控制电路和第二发光控制电路，相应地发光控制信号可以包括第一发光控制信号和第二发光控制信号。第一发光控制电路用于在第一发光控制信号的控制下将第一电源端的第一电源电压(VDD)施加至所述驱动电路的第一端。第二发光控制电路用于在第二发光控制信号的控制下将来自所述驱动电路的第二端的所述驱动电流施加至发光元件的第一极。第一发光控制信号和第二发光控制信号是相同的信号(EM)。
第一复位电路用于在第一复位控制信号的控制下将第一复位电压施加至所述驱动电路的控制端。
第二复位电路用于第二复位控制信号的控制下将第二复位电压施加至发光元件的第一极。
可选地，第二复位控制信号为扫描信号或与扫描信号同步，即在进行数据写入的同时也将发光元件的第一极的电压复位，这样可以在将发光元件寄生电容上可能存在的电荷释放，以保证正常发光。在另一些实施方式中，第二复位控制信号也可以与第一复位控制信号同步，只要在这一帧的发光控制信号有效之前将发光元件的第一极的电压复位即可。
发光元件的第二极连接到第二电源端以接收第二电源电压(VSS)。
图1B-1C示出了该像素电路的示例电路结构的电路图以及对应的时序 图。
应注意，本文示出的各个示例像素电路对于图1A中的各个电路模块中的电路构成进行了示例描述，但是这不是限定于每个电路模块都必须采用与图1B中描述的完全一致的结构，例如，驱动电路采用了如图1B所示的电路构成，数据写入电路可以采用不同于图1B所示的电路构成，例如可以包括更多的晶体管等等，只要能够在扫描信号的控制下将数据电压施加到第二节点(N2)即可。该理解同样适用于本公开的其他示例电路结构。
如图1B所示，所述驱动电路包括第一晶体管(T1)，所述第一晶体管的栅极作为所述驱动电路的控制端和第一节点(N1)连接，所述第一晶体管的第一极作为所述驱动电路的第一端和第二节点(N2)连接，所述第一晶体管的第二极作为所述驱动电路的第二端和第三节点(N3)连接。
所述数据写入电路包括第二晶体管(T2)，所述第二晶体管的栅极用于接收所述扫描信号(Scan)，所述第二晶体管的第一极用于接收所述数据信号，所述第二晶体管的第二极与所述第二节点(N2)连接。
所述补偿电路包括第三晶体管(T3)和存储电容(Cs)，所述第三晶体管(T3)的栅极用于接收所述补偿控制信号(C)，所述第三晶体管的第一极和所述第三节点连接，所述第三晶体管的第二极和所述存储电容的第一极以及所述第一节点连接，所述存储电容的第二极连接到第一电源端用于接收第一电源电压。补偿控制信号(C)为所述扫描信号(Scan)(后文以此为例)或与其同步。
所述第一发光控制电路包括第四晶体管(T4)，所述第四晶体管的栅极用于接收发光控制信号(EM)，所述第四晶体管的第一极连接到第一电源端用于接收所述第一电源电压，所述第四晶体管的第二极和所述第二节点(N2)连接。
所述第二发光控制电路包括第五晶体管(T5)，所述第五晶体管的栅极用于接收发光控制信号(EM)，所述第五晶体管的第一极和所述第三节点(N3)连接，所述第五晶体管的第二极和所述发光元件的第一极(作为第四节点)连接。
所述第一复位电路包括第六晶体管(T6)，所述第六晶体管的栅极用于接收所述第一复位控制信号(RST)，所述第六晶体管的第一极和所述第一节点连接，所述第六晶体管的第二极用于接收第一复位电压。
所述第二复位电路包括第七晶体管(T7)，所述第七晶体管的栅极用于接收所述第二复位控制信号，所述第七晶体管的第一极和所述发光元件的第一极连接，所述第七晶体管的第二极用于接收所述第二复位电压。该第二复位控制信号可以为发光控制信号(后文以此为例)或与发光控制信号同步。
所述发光控制信号为无效电平时使得第七晶体管复位，所述发光控制信号在有效电平时使得所述驱动电流流经所述发光元件，以进行发光。
发光元件的亮度要稳定的一个重要因素是驱动晶体管(第一晶体管)的栅源极电压稳定，因此需要尽可能避免各个节点处的漏电。可以将在驱动电流流通路径之外的晶体管选择为漏电流特性较好的晶体管，即漏电流特性优于驱动电流流通路径上的晶体管。目前在显示领域中，采用LTPO TFT具有比采用LTPS TFT更低的驱动功率，例如，LTPS晶体管的漏电流较大，但是驱动速度快，开态电流大，LTPO晶体管可以指代氧化物晶体管，其漏电流较小。对于图1B中所示的像素电路，可以将在驱动电流流通路径之外的晶体管(即，晶体管T2,T3,T6和T7)设置为氧化物晶体管，而驱动电流流通路径上的晶体管(T1,T4,T5)采用LTPS以保证快的驱动速度。
此外，在图1B所示的像素电路中，第一和第二发光控制电路中的晶体管以及驱动晶体管(T1,T4,T5)的极性被示出与数据写入电路、第一和第二复位电路中的晶体管(T2,T3,T6,T7)的极性是相反的。但是可以根据实际情况而适应地改变。
以下结合图1C对图1B所示像素电路的驱动方式以及工作过程进行描述。
如图1C所示，包括复位阶段、数据写入和补偿阶段、和发光阶段。
在复位阶段，使所述第一复位控制信号为有效电平，扫描信号、发光控制信号为无效电平。
这样，由于第一复位控制信号为有效电平，发光控制信号为无效电平，因此第六晶体管(T6)导通，第七晶体管(T7，与发光控制电路的晶体管极性相反，因此是EM无效时导通)导通，其余晶体管均关断，以将第一复位电压提供到第一节点(N1)，并将第二复位电压提供到发光元件的第一极(第四节点)，此时第一节点电压为Vint1，第四节点的电压为Vint2，第二节点、第三节点的电压在前一阶段结束后浮置。
在数据写入和补偿阶段，使扫描信号为有效电平，第一复位控制信号和发光控制信号为无效电平。
这样，第一晶体管T1、第二晶体管T2、第三晶体管T3和第七晶体管T7导通，其余晶体管关断，第一晶体管T1形成二极管连接，数据信号Data依次经过第二晶体管T2、第一晶体管T1和第三晶体管T3向第一节点N1充电，直至第一节点N1的电压为Vdata+Vth时充电结束，第二节点N2的电压为Vdata，第三节点N3的电压为Vdata+Vth，从而完成第一晶体管T1的阈值电压Vth的提取和数据电压Vdata的写入，此时存储电容上的电压值为Vdata+Vth-VDD，即第一晶体管T1的阈值电压Vth储存于存储电容中。
此外，在数据写入和补偿阶段中，由于第二复位电路中的第七晶体管T7仍然导通，因此仍然在对发光元件的第一极(第四节点)的电压进行复位。
在发光阶段，使所述发光控制信号为有效电平，扫描信号、第一复位控制信号为无效电平。
这样，第一晶体管T1、第四晶体管T4和第五晶体管T5导通，其余晶体管关断，电流从VDD流向VSS，此时，第一节点N1的电压由于存储电容仍为Vdata+Vth，第二节点的电压为VDD，第三节点N3的电压为发光元件的第一极的电压。第一晶体管T1的栅源极电压差为：Vgs＝N1电压-N2电压＝Vdata+Vth-VDD，流经发光元件的驱动电流I＝K(Vgs-Vth)2＝K(Vdata+Vth-VDD-Vth)2＝K(Vdata-VDD)2，其中，K为晶体管的本征因子。由此可知，流经发光元件的驱动电流I与第一晶体管T1的阈值电压Vth无关，该像素电路实现了对第一晶体管T1的阈值电压Vth的补偿。
发光控制信号可以在第一复位控制信号之前或与第一复位控制信号同时从有效电平(图中为低电平)变为无效电平(图中为高电平)，并且在数据写入和补偿阶段结束(扫描信号重新变为无效电平)之后或结束时又重新变为有效电平，以基于当前显示帧的新写入的数据进行发光。例如在图1C中示为在第一复位控制信号前一个时钟周期从有效电平变为无效电平，且在数据写入阶段结束之后三个时钟周期又重新变为有效电平。在发光控制信号为无效电平期间，均对发光元件的第一极的电压进行复位操作。
当然，也可以以其他方式设置发光控制信号，只需在复位阶段和数据写入和补偿阶段期间保持无效电平即可。
在本公开的实施例中示出的各个像素电路中，发光元件可以为有机发光二极管(OLED),其第一极为OLED的阳极，第二级为OLED的阴极。
在本公开中，第一电源电压VDD可以是例如5V、4.6V等大于0的直流 电压。第二电源电压VSS可以是例如0V、-2V等小于等于0的直流电压。第一复位电压和第二复位电压可以相同，例如，均为第二电源电压VSS，当然两者也可以取不同的小于等于0的其他值。
驱动电路中的驱动晶体管(第一晶体管T1)的阈值电压Vth可以大于或等于-5V而小于或等于-2V，优选情况下，Vth可以大于或等于-4V而小于或等于-2.5V；例如，Vth可以为-4V、-3.5V、-3V或-2.5V，但不以此为限。
在参考图1B-1C描述的像素电路中，采用氧化物晶体管，可以减小电路中的漏电，并且由于采用发光控制信号来控制用于对发光元件的第一极上的电压的复位，大幅加长了第二复位电压对发光元件的复位时间，确保了发光元件上的电压的完全释放，节省了信号开销；并且在数据写入电路的第二晶体管与补偿电路的第三晶体管均为同类型的氧化物晶体管时，可以用同一个信号(即，扫描信号)驱动，因此不需要单独的两个信号，也可以节省信号开销，有利于窄边框的设计和生成各个信号的信号生成电路(例如，GOA电路)的整体功耗的降低。
图1D-1E示出了该像素电路的又一种示例电路结构的电路图以及对应的时序图。
由于该种示例电路结构与参考图1B-1C描述的示例结构大部分相同，因此以下仅对不同的部分进行描述。
如图1D所示，在参考图1B描述的示例结构的基础上，还增加了第三复位电路。第三复位电路用于在第三复位控制信号的控制下，将第三复位电压施加到驱动晶体管的第一端(即，第二节点)。第三复位控制信号可以是第一复位控制信号或与第一复位控制信号同步。
在图1D中，所述第三复位电路包括复位晶体管(Tr)，所述复位晶体管的栅极用于接收所述第三复位控制信号，所述第六晶体管的第一极和所述第二节点连接，所述第六晶体管的第二极用于接收第三复位电压。第三复位电压为直流电压，例如，5V，或者与第一电源电压相同，以减少线路。
同样的，该复位晶体管也可以选择为氧化物晶体管。
图1E中示出的时序图与图1C中的时序图相同。区别仅在于，在复位阶段，复位晶体管(Tr)在第一复位控制信号(RST)的控制下导通，将第三复位电压施加到第二节点(N2)，并且第一节点也被拉低到第一复位电压。这样除了能够减小漏电流之外，还可以对第一晶体管(T1)的栅源电压进行复位， 利于第一晶体管的恢复速度加快，因此会改善第一晶体管的迟滞现象，提升迟滞恢复速度，有利于提高第一晶体管的稳定性，进而可以在高低频显示(例如从视频切换到显示静止图像)切换时保持显示画面亮度，降低抖动风险。
采用基于LTPO技术的晶体管的一种应用是在低频显示时降低驱动功耗。
如前面所述的，LTPS晶体管的漏电流较大，为了保持显示面板的各像素电路中的电容上的电压，即使显示例如静止图像时仍需要较高的数据刷新率(例如，60Hz，即1s内刷新60次)以不停地对电容充电，功耗较大。LTPO晶体管是氧化物晶体管，其漏电流较小，使得电容上的电压能够保持较长时间，因此可以将电路中容易漏电的部分的晶体管(例如，其第一极或第二极与电容的一个电极或者驱动晶体管的栅极直接相连的晶体管)采用氧化物晶体管(IGZO晶体管)，因此在显示静止图像时可以以很低的频率(例如，1Hz，即1s内刷新1次)进行数据刷新，从而使像素电路适于实现低频驱动，降低显示面板的功耗。因此，本公开介绍的示例像素电路均采用了LTPO晶体管。
显示面板上的待显示内容(诸如视频)可能需要高数据刷新频率，例如60Hz的频率，即一秒钟刷新60次，每两次刷新之间(1s/60)完成所有行的像素的数据写入，将开始第一行的像素电路的数据写入和完成最后一行的像素电路的数据写入之间的时长与一个显示帧的时长对应，因此在这种情况下1s包括60个显示帧。
而另一些待显示内容可能不需要高的数据刷新频率，例如静止图像，只需要1Hz的数据刷新频率即可，即一秒钟仅更新1次显示数据。由于一般时钟信号是确定的，因此显示帧的时长相对于不同的数据刷新频率是不变的，这样，在显示周期(例如1s)的第一个显示帧(称为写入帧)内完成了所有行的像素电路的数据写入，在后续的显示帧(称为保持帧或跳帧)中每个像素电路仍根据其存储电容上的电压，并根据发光控制信号而控制发光元件进行发光。
以下将对高频显示和低频显示，特别是低频显示时更多的像素电路的工作过程进行进一步的介绍。
图2A-2B结合低频显示，示出了像素电路的第一种示例电路结构的电路图以及对应的时序图。
图2A示出的示例电路结构与图1B所示的示例电路结构相同，区别在于施加到数据写入电路、补偿电路、第二复位电路的晶体管类型和/或各个控制 信号与图1B所示出的不同。
具体如图2A所示，相比图1B所示的电路，采用了数量更少的氧化物晶体管，即仅第三晶体管和第六晶体管为氧化物晶体管，因此速度更快。
数据写入电路包括第二晶体管(T2)，所述第二晶体管的栅极用于接收所述扫描信号，所述第二晶体管的第一极用于接收所述数据信号，所述第二晶体管的第二极与所述第二节点(N2)连接。该第二晶体管为低温多晶硅晶体管。
所述补偿电路包括第三晶体管(T3)和存储电容(Cs)，所述第三晶体管(T3)的栅极用于接收所述补偿控制信号(不再是扫描信号)，所述第三晶体管的第一极和所述第三节点连接，所述第三晶体管的第二极和所述存储电容的第一极以及所述第一节点连接，所述存储电容的第二极连接到第一电源端用于接收第一电源电压。由于第三晶体管(T3)的第二极与存储电容的第一极连接，因此第三晶体管为氧化物晶体管。
所述第二复位电路包括第七晶体管(T7)，所述第七晶体管的栅极用于接收所述第二复位控制信号(扫描信号而不是发光控制信号)，所述第七晶体管的第一极和所述发光元件的第一极连接，所述第七晶体管的第二极用于接收所述第二复位电压。该第七晶体管为低温多晶硅晶体管。
以下结合图2B对图2A所示像素电路的驱动方式以及工作过程进行描述。
应注意，在本公开中描述的各个时序图针对的是不需要高数据刷新频率的情况(后文也称为低频显示)，而在需要高数据刷新频率的情况下，每个显示帧(例如，1s内60个显示帧)的驱动时序都与如参考图2B、3B、4B、6B、7B或8B所描述的写入帧的时序相同，因此不进行描述。
如图2B所示，针对写入帧，包括复位阶段、数据写入和补偿阶段(t2)、和发光阶段(t3)。
在复位阶段，使所述第一复位控制信号为有效电平，扫描信号、补偿控制信号、发光控制信号为无效电平。
这样，由于第一复位控制信号为有效电平，因此第六晶体管(T6)导通，其余晶体管均关断，以将第一复位电压提供到第一节点(N1)，此时第一节点电压为Vint1，第二节点、第三节点、发光元件的第一极(第四节点)的电压在前一阶段结束后浮置。
在数据写入和补偿阶段，使所述第一复位控制信号和发光控制信号为无效电平，扫描信号和补偿控制信号为有效电平。
这样，第一晶体管T1、第二晶体管T2、第三晶体管T3和第七晶体管T7导通，其余晶体管关断，第一晶体管T1形成二极管连接，数据信号Data依次经过第二晶体管T2、第一晶体管T1和第三晶体管T3向第一节点N1充电，直至第一节点N1的电压为Vdata+Vth时充电结束，第二节点N2的电压为Vdata，第三节点N3的电压为Vdata+Vth，从而完成第一晶体管T1的阈值电压Vth的提取和数据电压Vdata的写入，此时存储电容上的电压值为Vdata+Vth-VDD，即第一晶体管T1的阈值电压Vth储存于存储电容中。
此外，在数据写入和补偿阶段中，还向发光元件的第一极施加了第二复位电压，使得后续根据写入的数据发光。
在发光阶段，使所述发光控制信号为有效电平，扫描信号、补偿控制信号、第一复位控制信号和第二复位控制信号为无效电平。
这样，第一晶体管T1、第四晶体管T4和第五晶体管T5导通，其余晶体管关断，电流从VDD流向VSS，此时，第一节点N1的电压由于存储电容仍为Vdata+Vth，第二节点的电压为VDD，第三节点N3的电压为发光元件的第一极的电压。第一晶体管T1的栅源极电压差为：Vgs＝N1电压-N2电压＝Vdata+Vth-VDD，流经发光元件的驱动电流I＝K(Vgs-Vth) 2＝K(Vdata+Vth-VDD-Vth) 2＝K(Vdata-VDD) 2，其中，K为晶体管的本征因子。由此可知，流经发光元件的驱动电流I与第一晶体管T1的阈值电压Vth无关，该像素电路实现了对第一晶体管T1的阈值电压Vth的补偿。
针对每个显示周期内的写入帧之后的每个保持帧，无需再进行数据写入，只需要能够保证第一电源端到第二电源端之间的电流路径，因此补偿控制信号、第一复位控制信号在保持帧期间可以保持无效电平。
此外，为了使得每一帧的显示亮度均衡，而显示亮度是与发光控制信号的占空比相关的，因此保持帧中发光控制信号(EM)仍然需要与写入帧中的发光控制信号的占空比相同，而不是保持有效。
再进一步，在写入帧中，发光控制信号从有效电平变为无效电平之后，发光元件的第一极由于寄生电容的存在，会有一个电荷释放过程，并且在数据写入和补偿阶段完成了对发光元件的第一极(示为N4)的电压的复位，当进入发光阶段时，发光控制信号再次变为有效电平，会存在对寄生电容进行 充电的过程，因此在发光元件的第一极上会存在电压降低又增加的过程。因此，在保持帧中，为了保持各个显示帧中的发光元件的显示亮度相同，因此在每个保持帧中也需要在该发光元件的第一极上形成相同的电压降低又增加的过程。这样，对于每个显示帧(写入帧和每个保持帧)，进入发光阶段时都是从第二复位电压开始对发光元件的寄生电容进行充电，直到电压稳定。
即，在保持帧中包括与写入帧中的数据写入和补偿阶段对应的发光重置阶段以及与写入帧中的发光阶段对应的发光阶段。
在发光重置阶段，使所述第二复位控制信号为有效电平，写入控制信号、补偿控制信号、第一复位控制信号和发光控制信号均为无效电平。
这样，第一晶体管T1以及仅由扫描信号控制的第二晶体管T2和第七晶体管T7导通，其余晶体管关断，发光元件不会发光，通过导通第七晶体管T7可以向发光元件的第一极施加第二复位电压(Vint1)。
发光阶段中的各个信号的设置方式和电路的工作过程与写入帧中的类似，即仅EM为有效电平，这里不再重复。
在所述保持帧的发光重置阶段和发光阶段之外的阶段，使所述扫描信号、补偿控制信号、第一复位控制信号和发光控制信号均为无效电平。
图3A-3B结合低频显示，示出了该像素电路的第二种示例电路结构的电路图以及对应的时序图。
由于该第二种示例电路结构与图2A所示的第一种示例结构大部分相同，因此以下仅对不同的部分进行描述。
如图3A所示，驱动电路、数据写入电路、补偿电路、发光控制电路以及第二复位电路均与如参考图2A描述的第一种示例结构中的相同。
在图3A中，所述第一复位电路包括第六晶体管(T6)，所述第六晶体管的栅极用于接收所述第一复位控制信号，所述第六晶体管的第一极和所述第三节点连接，所述第六晶体管的第二极用于接收第一复位电压。
同样的，可以将与存储电容直接相连的第三晶体管选择为氧化物晶体管，以避免存储电容的漏电。
以下结合图3B对图3A所示像素电路的驱动方式以及工作过程进行描述。
如图3B所示，同样的，针对写入帧，包括复位阶段、数据写入和补偿阶段(t2)、和发光阶段(t3)。
在复位阶段，使所述第一复位控制信号、补偿控制信号为有效电平，扫描信号、发光控制信号为无效电平。
这样，由于第一复位控制信号和补偿控制信号为有效电平，因此第三晶体管(T3)和第六晶体管(T6)导通，其余晶体管均关断，以将第一复位电压经由导通的T3和T6提供到第一节点(N1)，此时第一节点电压为Vint1，第二节点、第三节点、发光元件的第一极的电压在前一阶段结束后浮置。
在数据写入和补偿阶段，使所述第一复位控制信号和发光控制信号为无效电平，扫描信号和补偿控制信号为有效电平。
这样，第一晶体管T1、第二晶体管T2、第三晶体管T3和第七晶体管T7导通，其余晶体管关断，第一晶体管T1形成二极管连接，数据信号Data依次经过第二晶体管T2、第一晶体管T1和第三晶体管T3向第一节点N1充电，直至第一节点N1的电压为Vdata+Vth时充电结束，第二节点N2的电压为Vdata，第三节点N3的电压为Vdata+Vth，从而完成第一晶体管T1的阈值电压Vth的提取和数据电压Vdata的写入，此时存储电容上的电压值为Vdata+Vth-VDD，即第一晶体管T1的阈值电压Vth储存于存储电容中。
此外，在数据写入和补偿阶段中，还向发光元件的第一极施加了第二复位电压，使得后续根据写入的数据发光。
在发光阶段，使所述发光控制信号为有效电平，扫描信号、补偿控制信号、第一复位控制信号和第二复位控制信号为无效电平。
这样，第一晶体管T1、第四晶体管T4和第五晶体管T5导通，其余晶体管关断，电流从VDD流向VSS，此时，第一节点N1的电压由于存储电容仍为Vdata+Vth，第二节点的电压为VDD，第三节点N3的电压为发光元件的第一极的电压。第一晶体管T1的栅源极电压差为：Vgs＝N1电压-N2电压＝Vdata+Vth-VDD，流经发光元件的驱动电流I＝K(Vgs-Vth) 2＝K(Vdata+Vth-VDD-Vth) 2＝K(Vdata-VDD) 2，其中，K为晶体管的本征因子。由此可知，流经发光元件的驱动电流I与第一晶体管T1的阈值电压Vth无关，该像素电路实现了对第一晶体管T1的阈值电压Vth的补偿。
同样地，在保持帧中包括与写入帧中的数据写入和补偿阶段对应的发光重置阶段以及与写入帧中的发光阶段对应的发光阶段。
发光重置阶段和发光阶段的更多细节与前文参考图2B描述的内容相同，因此这里不再重复描述。
图4A-4B结合低频显示，示出了该像素电路的第三种示例电路结构的电路图以及对应的时序图。
由于该第三种示例电路结构与第一种和第二种示例结构大部分相同，因此以下仅对不同的部分进行描述。
如图4A所示，驱动电路、数据写入电路、发光控制电路、第一复位电路和第二复位电路均与如参考图2A描述的第一种示例结构中的相同。
在图4A中，补偿电路包括第三晶体管(T3)、第八晶体管(T8)和存储电容。
所述第三晶体管(T3)的栅极用于接收所述扫描信号，所述第三晶体管的第一极和所述第三节点连接，所述第三晶体管的第二极与第五节点连接，所述第三晶体管(T3)在所述扫描信号的控制下可以将第三节点与第五节点连接。
所述第八晶体管(T8)的第一极连接第五节点，所述第八晶体管(T8)的第二极与所述存储电容的第一极以及所述第一节点连接，所述存储电容的第二极连接到第一电源端以用于接收第一电源电压(VDD)，所述第八晶体管(T3)在所述补偿控制信号的控制下可以将第五节点与第一节点连接，进而将第三节点与第一节点连接(在进行补偿时扫描信号为有效电平)。
同样的，可以将与存储电容直接相连的第八晶体管选择为氧化物晶体管，以避免存储电容的漏电。
以下结合图4B对图4A所示像素电路的驱动方式以及工作过程进行描述。
如图4B所示，同样的，针对写入帧，包括复位阶段、数据写入和补偿阶段(t2)、和发光阶段(t3)。
在复位阶段，使所述第一复位控制信号、补偿控制信号为有效电平，扫描信号、发光控制信号为无效电平。
这样，由于第一复位控制信号和补偿控制信号为有效电平，因此第六晶体管(T6)和第八晶体管(T8)导通，其余晶体管均关断，以将第一复位电压经由导通的T3和T6提供到第一节点(N1)，此时第一节点和第五节点的电压为Vint1，第二节点、第三节点、发光元件的第一极(第四节点)的电压为前一阶段结束时的电压。
在数据写入和补偿阶段，使所述第一复位控制信号和发光控制信号为无 效电平，扫描信号和补偿控制信号为有效电平。
这样，第一晶体管T1、第二晶体管T2、第三晶体管T3、第七晶体管T7和第八晶体管T8导通，其余晶体管关断，第一晶体管T1形成二极管连接，数据信号Data依次经过第二晶体管T2、第一晶体管T1、第三晶体管T3和第八晶体管T8向第一节点N1充电，直至第一节点N1的电压为Vdata+Vth时充电结束，第二节点N2的电压为Vdata，第三节点N3和第五节点N5的电压为Vdata+Vth，从而完成第一晶体管T1的阈值电压Vth的提取和数据电压Vdata的写入，此时存储电容上的电压值为Vdata+Vth-VDD，即第一晶体管T1的阈值电压Vth储存于存储电容中。
此外，在数据写入和补偿阶段中，还向发光元件的第一极施加了第二复位电压，使得后续根据写入的数据发光。
在发光阶段，使所述发光控制信号为有效电平，扫描信号、补偿控制信号、第一复位控制信号和第二复位控制信号为无效电平。
这样，第一晶体管T1、第四晶体管T4和第五晶体管T5导通，其余晶体管关断，电流从VDD流向VSS，此时，第一节点N1的电压由于存储电容仍为Vdata+Vth，第二节点的电压为VDD，第三节点N3的电压为发光元件的第一极(N4)的电压，第五节点的电压在前一阶段结束后浮置。第一晶体管T1的栅源极电压差为：Vgs＝N1电压-N2电压＝Vdata+Vth-VDD，流经发光元件的驱动电流I＝K(Vgs-Vth) 2＝K(Vdata+Vth-VDD-Vth) 2＝K(Vdata-VDD) 2，其中，K为晶体管的本征因子。由此可知，流经发光元件的驱动电流I与第一晶体管T1的阈值电压Vth无关，该像素电路实现了对第一晶体管T1的阈值电压Vth的补偿。
同样地，在保持帧中包括与写入帧中的数据写入和补偿阶段对应的发光重置阶段以及与写入帧中的发光阶段对应的发光阶段。
发光重置阶段和发光阶段的更多细节与前文参考图2B和3B描述的内容相同，因此这里不再重复描述。
以上参考图2A、3A和4A描述的各个示例电路结构和对应的工作过程，以及如将在后文描述的各个晶体管可以根据需要而选择是P型或者N型，对应的有效电平可以分别为低电平和高电平。当晶体管为P型时，第一极是指源极，第二极是指漏极，类似的，当晶体管为N型时，第一极是指漏极，第二极是指源极。
以上参考图1A-图4B描述的像素电路，由于采用了LPTO技术，因此可以在低频显示的时候具有小的驱动功耗，并且由于在保持帧中仍然设置发光重置阶段，使得可以使得对于每个显示周期内的每个显示帧显示亮度是均衡的，因此具有良好的显示效果。
申请人还发现，上述像素电路带来上述益处，但是也存在一定的缺陷。在上述像素电路中，在保持帧中设置了发光重置阶段，在该发光重置阶段中扫描信号为有效信号，因此即使在低频显示的情况下，扫描信号仍然是高频切换的，结合图2A-4B看到，当发光控制信号为无效，从而第四晶体管T4关断时，此时数据电压会频繁施加到第二节点N2，由于第一节点N1和第二节点N2之间存在寄生电容，因此第二节点N2的电压波动在保持帧中会对第一节点N1的电压产生一定的干扰，使得存储电容存储的电压发生变化，从而在发光阶段时驱动晶体管的栅源极电压会发生变化，因此会影响OLED的显示亮度。
由于在写入帧中，在发光阶段时，第一节点N1的电压由于存储电容的存在而为Vdata+Vth，第二节点的电压为VDD，希望在保持帧中也保持这两个节点的电压差，这样就可以使得在低频显示时每个像素电路的发光元件的显示亮度是稳定的，从而使得显示面板的显示画面稳定。
因此，本公开的实施例还提出了一种改进的像素电路，以在实现前面所述的像素电路的益处之外，还能使得在低频显示时，显示面板的显示画面更稳定。
图5结合低频显示，示出了根据本公开实施例的改进的像素电路的结构框图。图5所示的像素电路与参考图1A描述的像素电路的结构相同，只是在控制各部分电路的信号方面进行了调整。
如图5所示，类似地，像素电路10包括：驱动电路101、数据写入电路102、补偿电路103、发光控制电路104(104-1和104-2)、第一复位电路105和第二复位电路106。
驱动电路101包括控制端、第一端和第二端，且用于控制流经所述第一端和所述第二端的用于驱动发光元件发光的驱动电流。
数据写入电路102用于在写入控制信号的控制下将数据信号写入所述驱动电路的第一端(N2)。
补偿电路103用于在补偿控制信号的控制下、或在补偿控制信号和写入 控制信号的控制下将所述驱动电路的控制端(N1)和第二端(N3)电连接，并存储所述驱动电路的控制端的电压。
发光控制电路104用于在发光控制信号的控制下使得所述驱动电流流经所述发光元件。
可选地，发光控制电路可以包括第一发光控制电路和第二发光控制电路，相应地发光控制信号可以包括第一发光控制信号和第二发光控制信号。第一发光控制电路用于在第一发光控制信号(EM1)的控制下将第一电源端的第一电源电压(VDD)施加至所述驱动电路的第一端。第二发光控制电路用于在第二发光控制信号(EM2)的控制下将来自所述驱动电路的第二端的所述驱动电流施加至发光元件的第一极。第一发光控制信号和第二发光控制信号可以是相同或不同的信号。
第一复位电路用于在第一复位控制信号的控制下将第一复位电压施加至所述驱动电路的控制端。
第二复位电路用于第二复位控制信号的控制下将第二复位电压施加至发光元件的第一极。
这样，通过将在保持帧中仍需要的高频信号-第二复位控制信号(仍示为Scan)与写入控制信号独立，在保持帧中使得写入控制信号为无效电平，从而数据不会输入到第二节点N2，因此不会引起第一节点N1的电压波动，由于氧化物晶体管较优的漏电流特性，第一节点N1的电压仍可保持在前一发光阶段结束时的Vdata+Vth。当在保持帧中，发光控制信号(第一发光控制信号和第二发光控制信号相同的情况)变为有效电平时，第二节点N2的电压为VDD，因此，第一节点N1和第二节点的电压差仍然与在写入帧中的电压差相同，因此显示亮度是稳定的，显示面板的显示效果也是稳定的。这时，在每个显示帧中出现的第二复位控制信号可以被认为具有相同特性，例如在每个显示帧的相同时刻电平从无效电平变为有效电平，然后持续相同的时间又恢复无效电平。
此外，为了使第二节点N2的电压更好地稳定在第一电源电压VDD，除了使第二复位控制信号与写入控制信号独立之外，还可以附加地将第一发光控制信号和第二发光控制信号在保持帧中设置为不同的信号。
例如，在写入帧内所述第一发光控制信号(EM1)和所述第二发光控制信号(EM2)同步，并且在写入帧之后的每个保持帧内，所述第二发光控制信号(EM2) 为有效电平，所述第一发光控制信号与写入帧中的第一发光控制信号具有相同特性。
这样，在每个保持帧的起始点，即将第一发光控制电路启用(即将第四晶体管T4导通)，这样第一电源电压VDD被施加到第二节点N2，在进入发光阶段之前即将第二节点N2的电压稳定在VDD，则进一步地稳定了在发光阶段时候的显示亮度。
也就是说，在保持帧中，只有第二复位控制信号、或者第二复位控制信号和第二发光控制信号仍然是按行移位的(例如，从第一行像素移位到最后一行像素)，其余控制信号均是保持无效电平或有效电平。
图6A-6B结合低频显示，示出了该改进的像素电路的第一种示例电路结构的电路图以及对应的时序图。这与前文参考图2A描述的电路图相对应。
如图6A所示，与图2A类似的，所述驱动电路包括第一晶体管(T1)，所述第一晶体管的栅极作为所述驱动电路的控制端和第一节点(N1)连接，所述第一晶体管的第一极作为所述驱动电路的第一端和第二节点(N2)连接，所述第一晶体管的第二极作为所述驱动电路的第二端和第三节点(N3)连接。
所述数据写入电路包括第二晶体管(T2)，所述第二晶体管的栅极用于接收写入控制信号(Sp)，所述第二晶体管的第一极用于接收所述数据信号(Vdata)，所述第二晶体管的第二极与所述第二节点(N2)连接。
所述补偿电路包括第三晶体管和存储电容，所述第三晶体管(T3)的栅极用于接收所述补偿控制信号(C)，所述第三晶体管的第一极和所述第三节点连接，所述第三晶体管的第二极和所述存储电容的第一极以及所述第一节点连接，所述存储电容的第二极连接到第一电源端用于接收第一电源电压。
所述第一发光控制电路包括第四晶体管(T4)，所述第四晶体管的栅极用于接收所述第一发光控制信号(EM1)，所述第四晶体管的第一极连接到第一电源端用于接收所述第一电源电压，所述第四晶体管的第二极和所述第二节点(N2)连接。
所述第二发光控制电路包括第五晶体管(T5)，所述第五晶体管的栅极用于接收所述第二发光控制信号(EM2)，所述第五晶体管的第一极和所述第三节点(N3)连接，所述第五晶体管的第二极和所述发光元件的第一极(作为第四节点)连接。
所述第一复位电路包括第六晶体管(T6)，所述第六晶体管的栅极用于接 收所述第一复位控制信号(RST)，所述第六晶体管的第一极和所述第一节点连接，所述第六晶体管的第二极用于接收第一复位电压。
所述第二复位电路包括第七晶体管(T7)，所述第七晶体管的栅极用于接收所述第二复位控制信号(Scan)，所述第七晶体管的第一极和所述发光元件的第一极连接，所述第七晶体管的第二极用于接收所述第二复位电压。
可选地，第二复位控制信号可以是像素电路的扫描信号，例如，由GOA电路生成的按行移位的信号，逐行提供给各行像素电路。
可选地，将第三晶体管T3和第六晶体管T6仍然选择为氧化物晶体管，而其余晶体管仍然选择为低温多晶硅晶体管。
以下结合图6B对图6A所示像素电路的驱动方式以及工作过程进行描述。
应注意，以下参考图6B描述的时序图针对的低频显示的情况，而在高频显示的情况下，每个显示帧的驱动时序都与如参考图6B所描述的写入帧的时序相同，因此不进行描述。
如图6B所示，针对写入帧，包括复位阶段、数据写入和补偿阶段、和发光阶段。
在复位阶段，使所述第一复位控制信号为有效电平，写入控制信号、第二复位控制信号、补偿控制信号、所述第一发光控制信号和第二发光控制信号为无效电平。
这样，由于第一复位控制信号为有效电平，因此第六晶体管(T6)导通，其余晶体管均关断，以将第一复位电压提供到第一节点(N1)，此时第一节点电压为Vint1，第二节点、第三节点、发光元件的第一极(第四节点)的电压在前一阶段结束后浮置。
在数据写入和补偿阶段，使所述第一复位控制信号、所述第一发光控制信号和第二发光控制信号为无效电平，写入控制信号、第二复位控制信号和补偿控制信号为有效电平。
这样，第一晶体管T1、第二晶体管T2、第三晶体管T3和第七晶体管T7导通，其余晶体管关断，第一晶体管T1形成二极管连接，数据信号Data依次经过第二晶体管T2、第一晶体管T1和第三晶体管T3向第一节点N1充电，直至第一节点N1的电压为Vdata+Vth时充电结束，第二节点N2的电压为Vdata，第三节点N3的电压为Vdata+Vth，从而完成第一晶体管T1的阈值电 压Vth的提取和数据电压Vdata的写入，此时存储电容上的电压值为Vdata+Vth-VDD，即第一晶体管T1的阈值电压Vth储存于存储电容中。
此外，在数据写入和补偿阶段中，还向发光元件的第一极施加了第二复位电压，使得后续根据写入的数据发光。
在发光阶段，使所述第一发光控制信号和第二发光控制信号为有效电平，写入控制信号、第二复位控制信号、补偿控制信号、第一复位控制信号和第二复位控制信号为无效电平。
这样，第一晶体管T1、第四晶体管T4和第五晶体管T5导通，其余晶体管关断，电流从VDD流向VSS，此时，第一节点N1的电压由于存储电容仍为Vdata+Vth，第二节点的电压为VDD，第三节点N3的电压为发光元件的第一极的电压。第一晶体管T1的栅源极电压差为：Vgs＝N1电压-N2电压＝Vdata+Vth-VDD，流经发光元件的驱动电流I＝K(Vgs-Vth)2＝K(Vdata+Vth-VDD-Vth)2＝K(Vdata-VDD)2，其中，K为晶体管的本征因子。由此可知，流经发光元件的驱动电流I与第一晶体管T1的阈值电压Vth无关，该像素电路实现了对第一晶体管T1的阈值电压Vth的补偿。
在写入帧中，写入控制信号(Sp)和第二复位控制信号(Scan)是同步的。
针对每个保持帧，在保持帧中第一发光控制信号(EM1)保持为有效电平，且写入控制信号(Sn)保持为无效电平。此外，补偿控制信号(C)和第一复位信号(RST)也保持为无效电平。
这样，每个保持帧中第二节点的电压保持为第一电源电压VDD。
同样地，每个保持帧包括与写入帧中的数据写入和补偿阶段对应的发光重置阶段以及与写入帧中的发光阶段对应的发光阶段。
在发光重置阶段，使第一发光控制信号为有效电平，写入控制信号为无效电平，所述第二复位控制信号为有效电平，补偿控制信号、第一复位控制信号和第二发光控制信号均为无效电平。
这样，第一晶体管T1、第四晶体管T4以及第七晶体管T7导通，其余晶体管关断，发光元件不会发光，通过导通第七晶体管T7可以向发光元件的第一极施加第二复位电压(Vint1)，第二节点N2的电压保持为VDD。
在发光阶段，使第一发光控制信号为有效电平，写入控制信号为无效电平，第二发光控制信号为有效电平，所述第二复位控制信号、补偿控制信号、 第一复位控制信号均为无效电平。
这样，驱动电流将从第一电源电压经T4、T1、T5流向发光元件，使其发光。
在所述保持帧的发光重置阶段和发光阶段之外的阶段，使第一发光控制信号为有效电平，写入控制信号为无效电平，所述第二复位控制信号、补偿控制信号、第一复位控制信号和第二发光控制信号为无效电平。
结合参考图6B的时序图可知，在保持帧中，由写入控制信号控制的第二晶体管保持关断，因此数据写入电路被禁用，因此即使第二复位控制信号(可以是扫描信号)需要是高频使得显示亮度均匀，但是由于写入控制信号与其是独立的且是无效的，数据电压不会频繁地写入第二节点N2，因此第二节点N2的电压能够相对稳定，不会对第一节点N1的电压进行干扰。
进一步地，在保持帧中，由第一发光控制信号控制的第四晶体管保持导通，因此第一发光控制电路保持启用，因此第二节点N2的电压被保持在VDD，得到了更好的稳定。
可见，将写入控制信号与第二复位控制信号独立设置，或者在前者的同时还将第一发光控制信号和第二发光控制信号独立设置都能够对低频显示时的显示画面的稳定(通过稳定第二节点N2的电压)进行优化，虽然图6A-6B中对两者组合的实施方式进行了详细介绍，但是只选择其中一种方式也能起到使低频显示时的显示画面的稳定的效果。
图7A-7B结合低频显示，示出了该另一种像素电路的第二种示例电路结构的电路图以及对应的时序图。这与前文参考图3A描述的电路图相对应。
由于该第二种示例电路结构与图6A中的第一种示例结构大部分相同，因此以下仅对不同的部分进行描述。
如图7A所示，驱动电路、数据写入电路、补偿电路、发光控制电路以及第二复位电路均与如参考图6A描述的第一种示例结构中的相同。
在图7A中，所述第一复位电路包括第六晶体管(T6)，所述第六晶体管的栅极用于接收所述第一复位控制信号，所述第六晶体管的第一极和所述第三节点连接，所述第六晶体管的第二极用于接收第一复位电压。
同样的，可以将与存储电容直接相连的第三晶体管(T3)选择为氧化物晶体管，以避免存储电容的漏电。
以下结合图7B对图7A所示像素电路的驱动方式以及工作过程进行描 述。
如图7B所示，同样的，针对写入帧，包括复位阶段、数据写入和补偿阶段、和发光阶段。
在复位阶段，使所述第一复位控制信号、补偿控制信号为有效电平，写入控制信号、第二复位控制信号、第一发光控制信号和第二发光控制信号为无效电平。
这样，由于第一复位控制信号和补偿控制信号为有效电平，因此第三晶体管(T3)和第六晶体管(T6)导通，其余晶体管均关断，以将第一复位电压经由导通的T3和T6提供到第一节点(N1)，此时第一节点电压为Vint1，第二节点、第三节点、发光元件的第一极的电压在前一阶段结束后浮置。
在数据写入和补偿阶段和发光阶段的驱动方式和工作过程与参考图6B描述的过程相同或相似，因此这里省略其描述。
同样的，在写入帧中，写入控制信号和第二复位控制信号是同步的。
针对每个保持帧，在保持帧中第一发光控制信号保持为有效电平，且写入控制信号保持为无效电平。此外，补偿控制信号和第一复位信号也保持为无效电平。
这样，每个保持帧中第二节点的电压保持为第一电源电压VDD。
同样地，每个保持帧包括与写入帧中的数据写入和补偿阶段对应的发光重置阶段以及与写入帧中的发光阶段对应的发光阶段。
发光重置阶段和发光阶段的更多细节与前文参考图6B描述的内容相同，因此这里不再重复描述。
图8A-8B结合低频显示，示出了该另一种像素电路的第三种示例电路结构的电路图以及对应的时序图。这与前文参考图4A描述的电路图相对应。
由于该第三种示例电路结构与第一种和第二种示例结构大部分相同，因此以下仅对不同的部分进行描述。
如图8A所示，驱动电路、数据写入电路、发光控制电路(第一和第二发光控制电路)、第一复位电路和第二复位电路均与如参考图2A描述的第一种示例结构中的相同。
在图8A中，补偿电路包括第三晶体管(T3)、第八晶体管(T8)和存储电容。
所述第三晶体管(T3)的栅极用于接收写入控制信号，所述第三晶体管 的第一极和所述第三节点连接，所述第三晶体管的第二极与第五节点连接，所述第三晶体管(T3)在写入控制信号的控制下可以将第三节点与第五节点连接。
所述第八晶体管(T8)的第一极连接第五节点，所述第八晶体管(T8)的第二极与所述存储电容的第一极以及所述第一节点连接，所述存储电容的第二极连接到第一电源端以用于接收第一电源电压(VDD)，所述第八晶体管(T3)在所述补偿控制信号的控制下可以将第五节点与第一节点连接。
同样的，可以将与存储电容直接相连的第八晶体管选择为氧化物晶体管，以避免存储电容的漏电。
以下结合图8B对图8A所示像素电路的驱动方式以及工作过程进行描述。
如图8B所示，同样的，针对写入帧，包括复位阶段、数据写入和补偿阶段(t2)、和发光阶段(t3)。
在复位阶段，使所述第一复位控制信号、补偿控制信号为有效电平，写入控制信号、第二复位控制信号、第一发光控制信号和第二发光控制信号为无效电平。
这样，由于第一复位控制信号和补偿控制信号为有效电平，因此第六晶体管(T6)和第八晶体管(T8)导通，其余晶体管均关断，以将第一复位电压经由导通的T3和T6提供到第一节点(N1)，此时第一节点和第五节点的电压为Vint1，第二节点、第三节点、发光元件的第一极(第四节点)的电压为前一阶段结束时的电压。
在数据写入和补偿阶段，使所述第一复位控制信号、第一发光控制信号和第二发光控制信号为无效电平，写入控制信号、第二复位控制信号和补偿控制信号为有效电平。
这样，第一晶体管T1、第二晶体管T2、第三晶体管T3、第七晶体管T7和第八晶体管T8导通，其余晶体管关断，第一晶体管T1形成二极管连接，数据信号Data依次经过第二晶体管T2、第一晶体管T1、第三晶体管T3和第八晶体管T8向第一节点N1充电，直至第一节点N1的电压为Vdata+Vth时充电结束，第二节点N2的电压为Vdata，第三节点N3和第五节点N5的电压为Vdata+Vth，从而完成第一晶体管T1的阈值电压Vth的提取和数据电压Vdata的写入，此时存储电容上的电压值为Vdata+Vth-VDD，即第一晶体管 T1的阈值电压Vth储存于存储电容中。
此外，在数据写入和补偿阶段中，第二复位控制信号为有效电平，因此还向发光元件的第一极施加了第二复位电压，使得后续根据写入的数据发光。
在发光阶段，使第一发光控制信号和第二发光控制信号为有效电平，写入控制信号、补偿控制信号、第一复位控制信号和第二复位控制信号为无效电平。
这样，第一晶体管T1、第四晶体管T4和第五晶体管T5导通，其余晶体管关断，电流从VDD流向VSS，此时，第一节点N1的电压由于存储电容仍为Vdata+Vth，第二节点的电压为VDD，第三节点N3的电压为发光元件的第一极(N4)的电压，第五节点的电压在前一阶段结束后浮置。第一晶体管T1的栅源极电压差为：Vgs＝N1电压-N2电压＝Vdata+Vth-VDD，流经发光元件的驱动电流I＝K(Vgs-Vth)2＝K(Vdata+Vth-VDD-Vth)2＝K(Vdata-VDD)2，其中，K为晶体管的本征因子。由此可知，流经发光元件的驱动电流I与第一晶体管T1的阈值电压Vth无关，该像素电路实现了对第一晶体管T1的阈值电压Vth的补偿。
同样的，在写入帧中，写入控制信号和第二复位控制信号是同步的。
针对每个保持帧，在保持帧中第一发光控制信号保持为有效电平，且写入控制信号保持为无效电平，补偿控制信号、第一复位控制信号保持无效电平。
这样，每个保持帧中第二节点的电压保持为第一电源电压VDD。
同样地，每个保持帧包括与写入帧中的数据写入和补偿阶段对应的发光重置阶段以及与写入帧中的发光阶段对应的发光阶段。
发光重置阶段和发光阶段的更多细节与前文参考图6B和7B描述的内容相同或相似，因此这里不再重复描述。
通过参考图5-图8B所描述的改进的像素电路，是分别针对图1A、图2A-4B描述的像素电路针对显示画面的稳定性方面的改进，通过将在保持帧中仍需要的高频信号第二复位控制信号与写入控制信号独立，且在保持帧中使得写入控制信号为无效电平，或者附加地还将第一发光控制信号和第二发光控制信号在保持帧中设置为不同的信号，且在保持帧中将第一发光控制信号设置为有效电平，从而可以使得在低频显示时第二节点N2的电压稳定，因此，第一节点N1和第二节点N2的电压差稳定，使得像素的显示亮度更稳定， 显示面板的显示效果也更稳定。
根据以上的像素电路的结构以及时序进行的描述，本公开还提供了一种用于上述像素电路的驱动方法。
该驱动方法包括：在每个显示周期依次包括一个写入帧和至少一个保持帧的情况下，在写入帧内，使所述写入控制信号和所述第二复位控制信号同步，并且在该写入帧中包括：复位阶段、数据写入和补偿阶段以及发光阶段；在每个保持帧内，所述写入控制信号保持为无效电平，所述第二复位控制信号与所述写入帧的第二复位控制信号具有相同特性，并且在该保持帧中包括：与写入帧的数据写入和补偿阶段对应的发光重置阶段以及与写入帧内的发光阶段对应的发光阶段。
此外，该驱动方法还包括：在写入帧内使所述第一发光控制信号(EM1)和所述第二发光控制信号(EM2)同步；以及在每个保持帧内，使所述第一发光控制信号(EM1)为有效电平，所述第二发光控制信号与所述写入帧的第二发光控制信号具有相同特性。
每个阶段的具体细节已经在前文参考图5-图8B进行详细介绍，因此这里不再重复。
根据本公开的又一方面，还提供了一种显示装置。
图9示出了根据本公开实施例的显示装置900的示意图。
如图9所示，该显示装置900包括：呈阵列分布的多个像素单元60。例如，每个像素单元60可以包括上述参考图1A-图8B描述的任一像素电路，例如包括图6A中所示的像素电路。像素单元包括其他示例像素电路也是类似的，只是适应性地改变每个像素单元所连接的信号线的类型和方式。
显示装置900还可以包括多条写入控制线、多条补偿控制线、多条数据线、多条发光控制线(多条第一发光控制线和多条第二发光控制线)和多条复位控制线(多条第一复位控制线和多条第二复位控制线)。需要说明的是，在图9中仅示出了部分的像素单元60以及相关连线。例如，S N表示第N行的写入控制线(提供Sp信号)，S N+1表示第N+1行的写入控制线；C N表示第N行的补偿控制线(提供C信号)，C N+1表示第N+1行的补偿控制线；R N1和R N2表示第N行的第一复位控制线(提供RST信号)和第二复位控制线(提供Scan)，R N1+1和R N2+1表示第N+1行的第一复位控制线和第二复位控制线；D M表示第M列的数据信号线(提供Vdata)，D M+1表示第M+1列的数据信号 线；L N1和L N2表示第N行的第一发光控制线(提供EM1)和第二发光控制线(提供EM2)，L N1+1和L N2+1表示第N+1行的第一发光控制线和第二发光控制线。这里，N与M例如为大于0的整数。
例如，每个像素单元60可以包括上述描述的任一示例像素电路，例如包括图6A中所示的像素电路。
例如，每一行的写入控制线和本行的像素电路中的数据写入电路连接(在一些结构中，如图5中虚线或图8A所示的像素电路，还可以与补偿电路连接)以提供写入控制信号；每一行的补偿控制线和本行的像素电路中的补偿电路连接以提供补偿控制信号；每一列的数据线和本列像素电路中的数据写入电路连接以提供数据信号Vdata；每一行的第一复位控制线与本行的像素电路中的第一复位电路连接以提供第一复位控制信号，每一行的第二复位控制线与像素电路中的第二复位电路连接以提供第二复位控制信号；每一行的第一发光控制线与本行的像素电路中的第一发光电路连接以提供第一发光控制信号，每一行的第二发光控制线与像素电路中的第二发光电路连接以提供第二发光控制信号。
需要说明的是，图9所示的显示装置还可以包括多条第一电压线、多条第二电压线、和多条复位电压线(或多条第一复位电压线和多条第二复位电压线)以分别提供第一电源电压VDD、第二电源电压VSS、和复位电压Vinit(可以包括第一复位电压Vint1和第二复位电压Vinit2)(图中未示出)。
可选地，如图9所示，该显示装置1还可以包括扫描驱动电路20和数据驱动电路30。
例如，数据驱动电路30可以与多条数据线(D M、D M+1等)连接，以提供数据信号Vdata；同时还可以与多条第一电源电压线(图中未示出)和多条复位电压线(图中未示出)等等连接以分别提供各个电压。
例如，扫描驱动电路20可以与需要移位的各条控制线连接，例如多条写入控制线(S N、S N+1等)连接，以提供写入控制信号；同时还可以与多条补偿控制线连接以提供补偿控制信号，与多条(第一和第二)发光控制线(E N1、E N1+1，E N1、E N1+1等)连接以提供(第一和第二)发光控制信号，以及与多条(第一和第二)复位控制线连接以提供复位控制信号等等。
例如，扫描驱动电路20和数据驱动电路30可以实现为半导体芯片。该显示装置还可以包括其他部件，例如时序控制器、信号解码电路、电压转换 电路等，这些部件例如可以采用已有的常规部件，这里不再详述。
例如，本实施例提供的显示装置可以为电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种像素电路，包括：驱动电路、数据写入电路、补偿电路、发光控制电路、第一复位电路、第二复位电路和发光元件；
    所述驱动电路包括控制端、第一端和第二端，分别与第一节点、第二节点和第三节点连接，且用于控制流经所述第一端和所述第二端的用于驱动发光元件发光的驱动电流；
    所述数据写入电路用于在写入控制信号的控制下将数据信号写入所述驱动电路的第一端；
    所述补偿电路用于在补偿控制信号的控制下将所述驱动电路的控制端和第二端电连接，并存储所述驱动电路的控制端的电压；
    发光控制电路用于在发光控制信号的控制下使得所述驱动电流流经所述发光元件；
    第一复位电路用于在第一复位控制信号的控制下将第一复位电压施加至所述驱动电路的控制端，
    第二复位电路用于在第二复位控制信号的控制下将第二复位电压施加至发光元件的第一极，
    其中，在每个显示周期依次包括一个写入帧和至少一个保持帧的情况下，在写入帧内，所述写入控制信号和所述第二复位控制信号同步，在每个保持帧内，所述写入控制信号保持为无效电平，所述第二复位控制信号与所述写入帧的第二复位控制信号具有相同特性。
  2. 根据权利要求1所述的像素电路，其中，发光控制信号包括第一发光控制信号和第二发光控制信号，并且所述发光控制电路包括：
    第一发光控制电路,被用于在第一发光控制信号的控制下将第一电源电压施加至所述驱动电路的第一端；
    第二发光控制电路,被用于在第二发光控制信号的控制下将来自所述驱动电路的第二端的所述驱动电流施加至作为第四节点的发光元件的第一极，
    其中，针对每个显示周期，在写入帧和每个保持帧内，所述第一发光控制信号和所述第二发光控制信号均为同步信号；或者
    针对每个显示周期，在写入帧内所述第一发光控制信号和所述第二发光控制信号同步，并且在每个保持帧内，所述第一发光控制信号保持为有效电 平，所述第二发光控制信号与所述写入帧的第二发光控制信号具有相同特性。
  3. 根据权利要求2所述的像素电路，其中，所述驱动电路包括第一晶体管，
    所述第一晶体管的栅极作为所述驱动电路的控制端和第一节点连接，所述第一晶体管的第一极作为所述驱动电路的第一端和第二节点连接，所述第一晶体管的第二极作为所述驱动电路的第二端和第三节点连接。
  4. 根据权利要求2所述的像素电路，其中，所述数据写入电路包括第二晶体管，
    所述第二晶体管的栅极用于接收所述写入控制信号，所述第二晶体管的第一极用于接收所述数据信号，所述第二晶体管的第二极与第二节点连接。
  5. 根据权利要求2所述的像素电路，其中，所述补偿电路包括第三晶体管和存储电容，
    所述第三晶体管的栅极用于接收所述补偿控制信号，所述第三晶体管的第一极和第三节点连接，所述第三晶体管的第二极和所述存储电容的第一极以及所述第一节点连接，所述存储电容的第二极用于接收第一电源电压。
  6. 根据权利要求2所述的像素电路，其中，所述补偿电路包括第三晶体管、附加晶体管和存储电容，
    所述第三晶体管的栅极用于接收写入控制信号，所述第三晶体管的第一极和第三节点连接，所述第三晶体管的第二极与第五节点连接，所述第三晶体管在写入控制信号的控制下将第三节点与第五节点连接；
    所述附加晶体管的栅极用于接收补偿控制信号，所述附加晶体管的第一极和第五节点连接，所述附加晶体管的第二极与所述存储电容的第一极以及第一节点连接，所述存储电容的第二极用于接收第一电源电压，所述附加晶体管在所述补偿控制信号的控制下将第五节点与第一节点连接。
  7. 根据权利要求2所述的像素电路，其中，
    所述第一发光控制电路包括第四晶体管，所述第四晶体管的栅极用于接 收所述第一发光控制信号，所述第四晶体管的第一极用于接收所述第一电源电压，所述第四晶体管的第二极和所述第二节点连接；
    所述第二发光控制电路包括第五晶体管，所述第五晶体管的栅极用于接收所述第二发光控制信号，所述第五晶体管的第一极和所述第三节点连接，所述第五晶体管的第二极和所述发光元件的第一极连接，所述发光元件的第二极用于接收第二电源电压。
  8. 根据权利要求5所述的像素电路，其中，所述第一复位电路包括第六晶体管，
    所述第六晶体管的栅极用于接收所述第一复位信号，并且所述第六晶体管的第一极和所述第一节点连接，所述第六晶体管的第二极用于接收第一复位电压。
  9. 根据权利要求5所述的像素电路，其中，所述第一复位电路包括第六晶体管，
    所述第六晶体管的栅极用于接收所述第一复位信号，并且所述第六晶体管的第一极和第三节点连接，所述第六晶体管的第二极用于接收第一复位电压。
  10. 根据权利要求6所述的像素电路，其中，所述第一复位电路包括第六晶体管，
    所述第六晶体管的栅极用于接收所述第一复位信号，并且所述第六晶体管的第一极和所述第五节点连接，所述第六晶体管的第二极用于接收第一复位电压。
  11. 根据权利要求8-10任一项所述的像素电路，其中，所述第二复位电路包括第七晶体管，
    所述第七晶体管的栅极用于接收所述第二复位控制信号，所述第七晶体管的第一极和所述发光元件的第一极连接，所述第七晶体管的第二极用于接收所述第二复位电压。
  12. 根据权利要求11所述的像素电路，其中，第一极或第二极与所述存储电容直接相连的晶体管中至少一者的漏电流特性优于像素电路中的其他晶体管的漏电流特性。
  13. 一种显示装置，包括：呈阵列分布的多个像素单元，其中，每个所述像素单元包括如权利要求1-12任一项所述的像素电路。
  14. 一种用于权利要求1-12中任一项所述的像素电路的驱动方法，包括：在每个显示周期依次包括一个写入帧和至少一个保持帧的情况下，
    在写入帧内，使所述写入控制信号和所述第二复位控制信号同步，并且所述写入帧包括：复位阶段、数据写入和补偿阶段、以及发光阶段；
    在每个保持帧内，使所述写入控制信号保持为无效电平，所述第二复位控制信号与所述写入帧的第二复位控制信号具有相同特性，并且所述保持帧包括：与写入帧的数据写入和补偿阶段对应的发光重置阶段以及与写入帧内的发光阶段对应的发光阶段。
  15. 根据权利要求14所述的驱动方法，其中，所述发光控制信号包括第一发光控制信号和第二发光控制信号，所述驱动方法还包括：
    在写入帧内使所述第一发光控制信号和所述第二发光控制信号同步，
    在每个保持帧内，使所述第一发光控制信号保持为有效电平，所述第二发光控制信号与所述写入帧的第二发光控制信号具有相同特性。
PCT/CN2022/109707 2021-08-05 2022-08-02 像素电路、显示装置和驱动方法 WO2023011474A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110898670.X 2021-08-05
CN202110898670.XA CN113838420B (zh) 2021-08-05 2021-08-05 像素电路、显示装置和驱动方法

Publications (1)

Publication Number Publication Date
WO2023011474A1 true WO2023011474A1 (zh) 2023-02-09

Family

ID=78963017

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/109707 WO2023011474A1 (zh) 2021-08-05 2022-08-02 像素电路、显示装置和驱动方法

Country Status (2)

Country Link
CN (1) CN113838420B (zh)
WO (1) WO2023011474A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113838420B (zh) * 2021-08-05 2022-03-18 京东方科技集团股份有限公司 像素电路、显示装置和驱动方法
CN114155815B (zh) * 2022-01-21 2023-04-18 京东方科技集团股份有限公司 像素电路、像素驱动方法和显示装置
CN114822383A (zh) * 2022-05-07 2022-07-29 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
WO2023225931A1 (zh) * 2022-05-26 2023-11-30 京东方科技集团股份有限公司 像素电路、驱动方法和显示装置
CN117897761A (zh) * 2022-06-29 2024-04-16 京东方科技集团股份有限公司 像素电路、驱动方法和显示装置
CN117651991A (zh) * 2022-06-30 2024-03-05 京东方科技集团股份有限公司 一种像素驱动电路及其控制方法、显示装置
CN117672139A (zh) * 2022-08-23 2024-03-08 北京京东方技术开发有限公司 像素电路及其驱动方法、显示面板、显示装置
CN117957942A (zh) * 2022-08-31 2024-04-30 京东方科技集团股份有限公司 显示面板及显示装置
CN117423314B (zh) * 2023-12-18 2024-04-26 维信诺科技股份有限公司 像素电路及其驱动方法、显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111009218A (zh) * 2018-10-04 2020-04-14 三星显示有限公司 显示装置以及使用该显示装置驱动显示面板的方法
CN111710299A (zh) * 2020-06-30 2020-09-25 厦门天马微电子有限公司 一种显示面板、其驱动方法及显示装置
CN111710300A (zh) * 2020-06-30 2020-09-25 厦门天马微电子有限公司 一种显示面板、驱动方法及显示装置
CN111724745A (zh) * 2020-07-15 2020-09-29 武汉华星光电半导体显示技术有限公司 像素电路及其驱动方法、显示装置
CN113012643A (zh) * 2021-03-01 2021-06-22 上海天马微电子有限公司 显示面板及其驱动方法和显示装置
CN113838420A (zh) * 2021-08-05 2021-12-24 京东方科技集团股份有限公司 像素电路、显示装置和驱动方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105679236B (zh) * 2016-04-06 2018-11-30 京东方科技集团股份有限公司 像素电路及其驱动方法、阵列基板、显示面板和显示装置
CN106097964B (zh) * 2016-08-22 2018-09-18 京东方科技集团股份有限公司 像素电路、显示面板、显示设备及驱动方法
CN109523956B (zh) * 2017-09-18 2022-03-04 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN109599062A (zh) * 2017-09-30 2019-04-09 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN113096593A (zh) * 2019-12-23 2021-07-09 深圳市柔宇科技股份有限公司 像素单元、阵列基板与显示终端
CN112053661B (zh) * 2020-09-28 2023-04-11 京东方科技集团股份有限公司 像素电路、像素驱动方法、显示面板和显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111009218A (zh) * 2018-10-04 2020-04-14 三星显示有限公司 显示装置以及使用该显示装置驱动显示面板的方法
CN111710299A (zh) * 2020-06-30 2020-09-25 厦门天马微电子有限公司 一种显示面板、其驱动方法及显示装置
CN111710300A (zh) * 2020-06-30 2020-09-25 厦门天马微电子有限公司 一种显示面板、驱动方法及显示装置
CN111724745A (zh) * 2020-07-15 2020-09-29 武汉华星光电半导体显示技术有限公司 像素电路及其驱动方法、显示装置
CN113012643A (zh) * 2021-03-01 2021-06-22 上海天马微电子有限公司 显示面板及其驱动方法和显示装置
CN113838420A (zh) * 2021-08-05 2021-12-24 京东方科技集团股份有限公司 像素电路、显示装置和驱动方法

Also Published As

Publication number Publication date
CN113838420B (zh) 2022-03-18
CN113838420A (zh) 2021-12-24

Similar Documents

Publication Publication Date Title
WO2023011474A1 (zh) 像素电路、显示装置和驱动方法
WO2021068637A1 (zh) 像素电路及其驱动方法、显示面板
US10964264B1 (en) Electroluminescent display panel having pixel driving circuit
WO2023005621A1 (zh) 像素电路及其驱动方法、显示面板
US11348520B2 (en) Organic light emitting display device and driving method thereof
WO2019233120A1 (zh) 像素电路及其驱动方法、显示面板
US9514683B2 (en) Gate driving circuit, gate driving method, gate on array (GOA) circuit and display device
TWI602169B (zh) 掃描驅動器及使用其之有機發光二極體顯示器
CN112150967A (zh) 一种显示面板、驱动方法及显示装置
WO2016173124A1 (zh) 像素电路、其驱动方法及相关装置
WO2023005694A1 (zh) 像素电路及其驱动方法、显示面板
US11205380B2 (en) Pixel that compensates for a threshold voltage of a driving transistor using a power source voltage and display device having the same
WO2020052287A1 (zh) 像素电路及其驱动方法、显示装置
KR20190018982A (ko) 게이트 구동회로와 이를 이용한 표시장치
WO2016045261A1 (zh) 像素电路及其驱动方法、显示面板和显示装置
US11935470B2 (en) Pixel circuit and driving method thereof, and display device
WO2015188533A1 (zh) 像素驱动电路、驱动方法、阵列基板及显示装置
US10559264B2 (en) Display panel
WO2019037476A1 (zh) 像素补偿电路、其驱动方法、显示面板及显示装置
WO2016155161A1 (zh) Oeld像素电路、显示装置及控制方法
JP6853662B2 (ja) 表示パネルおよび表示装置
CN112216244B (zh) 显示面板及其驱动方法和显示模组
WO2021026827A1 (zh) 像素电路及其驱动方法、阵列基板及显示装置
US11538379B2 (en) Foldable display panel and driving method thereof, display device and electronic apparatus
US9214110B2 (en) Display unit and electronic apparatus

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22852186

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 18289108

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE