WO2024098247A1 - 显示面板及其制备方法、显示装置 - Google Patents

显示面板及其制备方法、显示装置 Download PDF

Info

Publication number
WO2024098247A1
WO2024098247A1 PCT/CN2022/130594 CN2022130594W WO2024098247A1 WO 2024098247 A1 WO2024098247 A1 WO 2024098247A1 CN 2022130594 W CN2022130594 W CN 2022130594W WO 2024098247 A1 WO2024098247 A1 WO 2024098247A1
Authority
WO
WIPO (PCT)
Prior art keywords
light
emitting unit
emitting
layer
sub
Prior art date
Application number
PCT/CN2022/130594
Other languages
English (en)
French (fr)
Inventor
谢明哲
冯宇
祝文秀
盖人荣
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/130594 priority Critical patent/WO2024098247A1/zh
Publication of WO2024098247A1 publication Critical patent/WO2024098247A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details

Definitions

  • the present disclosure relates to but is not limited to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device.
  • Embodiments of the present disclosure provide a display panel and a method for manufacturing the same, and a display device.
  • an embodiment of the present disclosure provides a display panel, comprising: a substrate, and a display structure layer disposed on the substrate.
  • the display structure layer comprises a plurality of sub-pixels. At least one of the plurality of sub-pixels comprises: a pixel circuit and a light-emitting element electrically connected to the pixel circuit.
  • the light-emitting element comprises: a first light-emitting unit and a second light-emitting unit; the light-emitting region of the first light-emitting unit is isolated from the light-emitting region of the second light-emitting unit.
  • the pixel circuit is configured to drive at least one of the first light-emitting unit and the second light-emitting unit to emit light in an anti-peeping display mode.
  • the pixel circuit is configured to drive only the first light emitting unit to emit light in the anti-peeping display mode, and to drive the second light emitting unit to emit light together with the first light emitting unit in the sharing display mode.
  • the area of the light emitting region of the first light emitting unit of the light emitting element is greater than or equal to the area of the light emitting region of the second light emitting unit.
  • the display panel further includes: at least one shielding layer located on the light-emitting side of the display structure layer, the orthographic projection of the shielding layer on the substrate substrate having no overlap with the orthographic projection of the light-emitting regions of the first light-emitting unit and the second light-emitting unit of the light-emitting element on the substrate substrate; the orthographic projection of the shielding layer on the substrate substrate surrounds the orthographic projection of the first light-emitting unit of the light-emitting element on the substrate substrate, or the orthographic projection of the shielding layer on the substrate substrate surrounds the orthographic projection of the light-emitting element on the substrate substrate.
  • the display panel further includes: a color filter layer located on a side of the at least one shielding layer away from the base substrate, the color filter layer including: a plurality of periodically arranged filter units and a black matrix located between adjacent filter units, the plurality of filter units corresponding one-to-one to the light-emitting elements of the plurality of sub-pixels.
  • an orthographic projection of at least one of the plurality of filter units on the base substrate covers an orthographic projection of a light emitting element of a corresponding sub-pixel on the base substrate.
  • the display panel further includes: a light adjustment layer located on a side of the at least one shielding layer away from the base substrate, the light adjustment layer including: at least one lens unit, the orthographic projection of the at least one lens unit on the base substrate at least partially overlapping with the orthographic projection of the light emitting area of the first light emitting unit of the light emitting element on the base substrate.
  • the display panel further includes: a first protective layer and a second protective layer located on a side of the at least one shielding layer away from the base substrate; the second protective layer is located on a side of the first protective layer close to the base substrate, the refractive index of the second protective layer is smaller than the refractive index of the first protective layer, the orthographic projection of the second protective layer on the base substrate does not overlap with the light-emitting area of the light-emitting element, and the orthographic projection of the first protective layer on the base substrate covers the orthographic projection of the second protective layer on the base substrate.
  • the display structure layer includes an anode layer
  • the anode layer includes a first anode of a first light-emitting unit and a second anode of a second light-emitting unit of the light-emitting element, the first anode and the second anode are both electrically connected to the pixel circuit, and the first anode and the second anode are isolated from each other; the planes where the first anode and the second anode are located are flush, or the second anode is located on a side of the first anode away from the base substrate.
  • the display structure layer includes: an anode layer and a pixel definition layer located on a side of the anode layer away from the base substrate, the pixel definition layer is provided with a plurality of pixel openings exposing at least a portion of the surface of the anode layer, and the pixel definition layer is black.
  • a spacing between a first light emitting unit and a second light emitting unit of a light emitting element of the at least one sub-pixel is smaller than a spacing between light emitting elements of adjacent sub-pixels emitting light of different colors.
  • the light-emitting elements of the plurality of sub-pixels are arranged in an array, and the first light-emitting units and the second light-emitting units of the light-emitting elements of the sub-pixels emitting light of the same color are arranged alternately along a first direction and alternately along a second direction, and the first direction and the second direction intersect.
  • the pixel circuit includes at least: a data writing subcircuit, a storage subcircuit, a driving subcircuit, and a control subcircuit.
  • the data writing subcircuit is electrically connected to the data line, the first scan line, and the driving subcircuit, and is configured to provide the driving subcircuit with a data signal transmitted by the data line under the control of the first scan line.
  • the driving subcircuit is electrically connected to the data writing subcircuit, the storage subcircuit, the control subcircuit, and the first light-emitting unit of the light-emitting element, and is configured to drive the first light-emitting unit to emit light under the control of the data signal.
  • the control subcircuit is electrically connected to the second scan line, the driving subcircuit, the first light-emitting unit and the second light-emitting unit of the light-emitting element, and is configured to control the second light-emitting unit to emit light together with the first light-emitting unit under the control of the second scan line.
  • control subcircuit includes: a first control transistor; a gate of the first control transistor is electrically connected to the second scan line, a first electrode is electrically connected to the first light emitting unit, and a second electrode is electrically connected to the second light emitting unit.
  • the pixel circuit of the at least one sub-pixel is configured to drive only the second light-emitting unit to emit light in an anti-peeping display mode, or to drive the first light-emitting unit and the second light-emitting unit to emit light separately; and to drive the second light-emitting unit to emit light together with the first light-emitting unit in a shared display mode.
  • the display panel further includes: a light-blocking layer located on the light-emitting side of the display structure layer, the light-blocking layer including at least one light-blocking portion, the orthographic projection of the light-blocking portion on the base substrate covers the orthographic projection of the light-emitting area of the second light-emitting unit on the base substrate.
  • the plurality of sub-pixels include a first sub-pixel that emits a first color light, a second sub-pixel that emits a second color light, and a third sub-pixel that emits a third color light; in the anti-peeping display mode, the second light-emitting units of the light-emitting elements of the first sub-pixel, the second sub-pixel, and the third sub-pixel are all configured to emit light.
  • the pixel circuit includes at least: a data writing subcircuit, a storage subcircuit, a driving subcircuit, and a control subcircuit.
  • the data writing subcircuit is electrically connected to the data line, the first scan line, and the driving subcircuit, and is configured to provide the driving subcircuit with a data signal transmitted by the data line under the control of the first scan line.
  • the driving subcircuit is electrically connected to the data writing subcircuit, the storage subcircuit, the control subcircuit, and the first light-emitting unit of the light-emitting element, and is configured to drive the first light-emitting unit to emit light under the control of the data signal.
  • the control subcircuit is electrically connected to the second scan line, the first power line, the driving subcircuit, the first light-emitting unit and the second light-emitting unit of the light-emitting element, and is configured to control the second light-emitting unit to emit light together with the first light-emitting unit under the control of the second scan line, or drive the second light-emitting unit to emit light.
  • the control subcircuit includes: a first control transistor and a second control transistor; the gate of the first control transistor is electrically connected to the second scan line, the first electrode is electrically connected to the first light-emitting unit, and the second electrode is electrically connected to the second light-emitting unit; the gate of the second control transistor is electrically connected to the second scan line, the first electrode is electrically connected to the first power line, and the second electrode is electrically connected to the second light-emitting unit; the transistor type of the second control transistor and the first control transistor is different.
  • an embodiment of the present disclosure provides a display device, including the display panel as described above.
  • an embodiment of the present disclosure provides a method for preparing a display panel, which is used to prepare the display panel as described above.
  • the preparation method includes: forming a display structure layer on a base substrate, wherein the display structure layer includes a plurality of sub-pixels. At least one of the plurality of sub-pixels includes: a pixel circuit and a light-emitting element electrically connected to the pixel circuit, wherein the light-emitting element includes: a first light-emitting unit and a second light-emitting unit; the light-emitting area of the first light-emitting unit is isolated from the light-emitting area of the second light-emitting unit.
  • the pixel circuit is configured to drive at least one of the first light-emitting unit and the second light-emitting unit to emit light in an anti-peeping display mode.
  • FIG1 is a schematic structural diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG2 is a schematic diagram of a planar structure of a display panel according to at least one embodiment of the present disclosure
  • FIG3 is a schematic plan view of a sub-pixel of a display panel according to at least one embodiment of the present disclosure
  • FIG4 is a schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG5 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG6 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG7 is an exemplary partial cross-sectional view along the Q-Q' direction in FIG3;
  • FIG8 is a schematic plan view of a first shielding layer according to at least one embodiment of the present disclosure.
  • FIG9 is another partial cross-sectional example diagram along the Q-Q' direction in FIG3;
  • FIG10 is a schematic diagram of light emission of the cross-sectional structure along the R-R’ direction in FIG3 ;
  • FIG11 is a schematic diagram of light emission of the cross-sectional structure along the U-U’ direction in FIG3 ;
  • FIG12 is another partial cross-sectional example diagram along the Q-Q' direction in FIG3;
  • FIG13 is another partial cross-sectional example diagram along the Q-Q' direction in FIG3;
  • FIG14 is another partial cross-sectional example diagram along the Q-Q' direction in FIG3;
  • FIG15 is another partial cross-sectional example diagram along the Q-Q' direction in FIG3;
  • FIG16 is another partial cross-sectional example diagram along the Q-Q' direction in FIG3;
  • FIG. 17 is another schematic plan view of a sub-pixel of a display panel according to at least one embodiment of the present disclosure.
  • FIG18 is a schematic diagram of light emission of the cross-sectional structure along the V-V′ direction in FIG17 in the anti-peeping display mode
  • FIG19 is a schematic diagram of light emission of the cross-sectional structure along the V-V' direction in FIG17 in the sharing display mode
  • FIG20 is a schematic diagram of light emission of the cross-sectional structure along the O-O' direction in FIG17 in the sharing display mode
  • FIG21 is a schematic diagram of the cross-sectional structure along the V-V' direction in FIG17;
  • FIG. 22 is another schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG23 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG24 is a partial cross-sectional schematic diagram of a light emitting element according to at least one embodiment of the present disclosure.
  • FIG25A is a schematic diagram of a monochrome image of a display panel in an anti-peeping display mode according to at least one embodiment of the present disclosure
  • FIG25B is a schematic diagram of a monochrome image of a display panel in a sharing display mode according to at least one embodiment of the present disclosure
  • FIG26A is a schematic diagram of a black screen of a display panel in an anti-peeping display mode according to at least one embodiment of the present disclosure
  • FIG26B is a schematic diagram of a black screen of a display panel in a shared display mode according to at least one embodiment of the present disclosure
  • FIG27 is a schematic diagram of a white screen of a display panel in an anti-peeping display mode according to at least one embodiment of the present disclosure
  • FIG. 28 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • electrical connection includes the case where components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the "element having some electrical function” as long as it can transmit electrical signals between connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.
  • a transistor refers to an element including at least three terminals: a gate electrode (gate), a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode.
  • a channel region refers to a region where current mainly flows.
  • one of the electrodes is called the first pole and the other electrode is called the second pole.
  • the first pole can be a source electrode or a drain electrode
  • the second pole can be a drain electrode or a source electrode.
  • the gate of the transistor can be called a control electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the "source electrode” and the “drain electrode” can be interchanged.
  • parallel means that the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle may be greater than -5° and less than 5°.
  • perpendicular means that the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle may be greater than 85° and less than 95°.
  • triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced by “conductive film”.
  • insulating film may be replaced by “insulating layer”.
  • an external anti-peeping film is used, and the anti-peeping function is realized by manually hanging the anti-peeping film in front of the display screen, and the anti-peeping film can be manually removed when not needed;
  • another example is adding a liquid crystal layer in front of the display screen, and the anti-peeping function is realized by limiting the light output angle by turning the liquid crystal molecules.
  • the above solutions easily lead to a complex structure of the display panel and increase the thickness of the display panel, which is not conducive to improving the user experience.
  • the present embodiment provides a display panel, comprising: a base substrate, and a display structure layer disposed on the base substrate.
  • the display structure layer comprises a plurality of sub-pixels. At least one sub-pixel comprises: a pixel circuit and a light-emitting element electrically connected to the pixel circuit.
  • the light-emitting element comprises: a first light-emitting unit and a second light-emitting unit. The light-emitting region of the first light-emitting unit and the light-emitting region of the second light-emitting unit are isolated from each other.
  • the pixel circuit is configured to drive at least one of the first light-emitting unit and the second light-emitting unit to emit light in an anti-peeping display mode.
  • the display panel provided in this embodiment achieves an anti-peeping effect by dividing the light-emitting element of the sub-pixel into two light-emitting units (i.e., a first light-emitting unit and a second light-emitting unit), and controlling the light emission of the first light-emitting unit and the second light-emitting unit through a pixel circuit.
  • the display panel provided in this embodiment improves the internal structure of the display panel, and can achieve an anti-peeping display effect without increasing the thickness of the display panel, thereby improving the user experience.
  • the display panel may be an organic light emitting diode (OLED) display panel, or a quantum dot light emitting diode (QLED) display panel, or a plasma display device (PDP) display panel, or an electrophoretic display (EPD) display panel. This embodiment is not limited thereto.
  • OLED organic light emitting diode
  • QLED quantum dot light emitting diode
  • PDP plasma display device
  • EPD electrophoretic display
  • the display panel may include an anti-peeping display mode and a sharing display mode.
  • the anti-peeping display mode can meet the user's display needs for privacy protection, and the sharing display mode can meet the user's display needs in information sharing scenarios.
  • the display panel may be provided with a switching button, and the user switches the display mode of the display panel by switching the button.
  • this embodiment is not limited to this.
  • voice control, induction and other triggering methods can be used to start the display mode switching of the display panel.
  • the pixel circuit may be configured to drive only the first light-emitting unit to emit light in the anti-peeping display mode, and to drive the second light-emitting unit to emit light together with the first light-emitting unit in the sharing display mode.
  • the pixel circuit may be configured to drive only the second light-emitting unit to emit light in the anti-peeping display mode, or to drive the first light-emitting unit and the second light-emitting unit to emit light respectively, and to drive the second light-emitting unit to emit light together with the first light-emitting unit in the sharing display mode.
  • this embodiment is not limited to this. This example improves the internal structure of the display panel to achieve an anti-peeping display effect and a sharing display effect without increasing the thickness of the display panel, thereby improving the user experience.
  • the display panel may include: at least one shielding layer located on the light-emitting side of the display structure layer, and the orthographic projection of the shielding layer on the substrate substrate may not overlap with the orthographic projection of the light-emitting area of the first light-emitting unit and the second light-emitting unit of the light-emitting element on the substrate substrate.
  • the orthographic projection of the shielding layer on the substrate substrate may surround the orthographic projection of the first light-emitting unit of the light-emitting element on the substrate substrate, or the orthographic projection of the shielding layer on the substrate substrate may surround the orthographic projection of the light-emitting element on the substrate substrate.
  • the number of shielding layers may be two, and a protective layer may be provided between adjacent shielding layers.
  • the light emission angle of the first light-emitting unit of the light-emitting element can be limited, thereby facilitating the realization of an anti-peeping display effect.
  • the display panel may further include: a color filter layer located on the side of at least one shielding layer away from the substrate.
  • the color filter layer may include: a plurality of periodically arranged filter units and a black matrix located between adjacent filter units, and the plurality of filter units correspond one to one to the light emitting elements of the plurality of sub-pixels.
  • the black matrix and the filter unit can limit the light emission angle of the light emitting element, thereby facilitating the realization of an anti-peeping display effect.
  • FIG1 is a schematic diagram of the structure of a display panel of at least one embodiment of the present disclosure.
  • the display panel may include: a timing controller 20, a data driver 40, a gate drive circuit, and a sub-pixel array 10.
  • the gate drive circuit may include at least one driver, for example, a scan driver 30.
  • the timing controller 20, the data driver 40, and the gate drive circuit may be located in a peripheral area outside the display area of the display panel.
  • the sub-pixel array 10 located in the display area may include a plurality of sub-pixels PX arranged in a regular pattern.
  • the scan driver 30 may be configured to provide a scan signal to the sub-pixel PX along a scan line; the data driver 40 may be configured to provide a data signal to the sub-pixel PX along a data line; and the timing controller 20 may be configured to control the scan driver 30 and the data driver 40.
  • the timing controller 20 may provide the data driver 40 with a grayscale value and a control signal suitable for the specifications of the data driver 40; the timing controller 20 may provide the scan driver 30 with a clock signal, an initial signal, etc. suitable for the specifications of the scan driver 30.
  • the data driver 40 may generate a data voltage to be provided to the data lines D1 to Dn using the grayscale value and the control signal received from the timing controller 20.
  • the data driver 40 may sample the grayscale value using the clock signal, and apply the data signal corresponding to the grayscale value to the data lines D1 to Dn in units of sub-pixel rows.
  • the scan driver 30 may generate a scan signal to be provided to the scan lines G1 to Gm using the clock signal, the initial signal, etc. received from the timing controller 20.
  • the scan driver 30 may sequentially provide a scan signal having an on-level pulse to the scan line.
  • the scan driver 30 may include a shift register, and may sequentially transmit the scan initial signal provided in the form of an on-level pulse to the next level circuit under the control of the clock signal to generate a scan signal.
  • n and m are both natural numbers.
  • the gate driver circuit can be directly disposed on the substrate substrate.
  • the gate driver can be disposed in the peripheral areas on the left and right sides of the display area.
  • the gate driver can be formed together with the sub-pixel in the process of forming the sub-pixel.
  • the present embodiment does not limit the location or formation method of the gate driver.
  • the gate driver can be disposed on a separate chip or printed circuit board to be connected to a pad or pad formed on the substrate substrate.
  • the data driver 40 may be disposed on a separate chip or printed circuit board to be connected to the sub-pixel PX through a signal access pin disposed on the substrate.
  • the data driver 40 may be formed by a chip on glass, a chip on plastic, a chip on a film, etc. to be connected to a signal access pin on the substrate.
  • the timing controller 20 may be disposed separately from the data driver 40 or integrally with the data driver 40. However, this embodiment is not limited thereto.
  • FIG. 2 is a schematic diagram of a planar structure of a display panel of at least one embodiment of the present disclosure.
  • the display area of the display panel may include a plurality of pixel units P arranged in a matrix manner, and at least one of the plurality of pixel units P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light.
  • the first color light may be red light
  • the second color light may be green light
  • the third color light may be blue light.
  • the first sub-pixel P1 may be a red (R) sub-pixel
  • the second sub-pixel P2 may be a green (G) sub-pixel
  • the third sub-pixel P3 may be a blue (B) sub-pixel.
  • the pixel unit P may include four sub-pixels, for example, a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.
  • the present disclosure is not limited thereto.
  • the shape of the sub-pixels in the pixel unit P may be a rectangle, a rhombus, a pentagon, or a hexagon. As shown in FIG2 , the shape of the sub-pixels in the pixel unit P may be a rectangle.
  • the three sub-pixels may be arranged in a horizontal parallel, vertical parallel, or in a triangular manner; when the pixel unit includes four sub-pixels, the four sub-pixels may be arranged in a horizontal parallel, vertical parallel, or in a square manner.
  • the present disclosure is not limited thereto.
  • At least one sub-pixel may include a pixel circuit and a light-emitting element.
  • the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 may each include a pixel circuit and a light-emitting element.
  • the pixel circuit may include a plurality of transistors and at least one capacitor, for example, the pixel circuit may be a 3T1C structure, a 7T1C structure, a 5T1C structure, an 8T1C structure, or an 8T2C structure, etc., wherein T in the above circuit structure refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.
  • the light-emitting elements in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel circuits of the sub-pixels in which they are located, and the light-emitting elements can be configured to emit light of corresponding brightness in response to the driving current output by the pixel circuit of the sub-pixel in which they are located.
  • the light-emitting element can be an organic light-emitting diode (OLED), which can include a stacked first pole (anode), an organic light-emitting layer, and a second pole (cathode).
  • OLED organic light-emitting diode
  • this embodiment is not limited to this.
  • the light-emitting element can be a micro light-emitting diode (Micro-LED, Micro Light Emitting Diode), or a mini diode (Mini-LED), or a quantum dot light-emitting diode (QLED).
  • Micro-LED Micro Light Emitting Diode
  • Mini-LED mini diode
  • QLED quantum dot light-emitting diode
  • FIG3 is a plan view of a sub-pixel of a display panel of at least one embodiment of the present disclosure.
  • a plurality of sub-pixels in a display area of the display panel may be arranged in an array, for example, arranged in sequence along a first direction X, and arranged in sequence along a second direction Y.
  • the first direction X and the second direction Y may be located in the same plane and intersect each other, for example, the first direction X may be perpendicular to the second direction Y.
  • a plurality of sub-pixels arranged along the first direction X may be referred to as a row of sub-pixels, and a plurality of sub-pixels arranged along the second direction Y may be referred to as a column of sub-pixels.
  • the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 may be arranged periodically; a plurality of sub-pixels emitting light of the same color may be arranged in a column of sub-pixels.
  • a plurality of first sub-pixels P1 may be arranged in one column
  • a plurality of second sub-pixels P2 may be arranged in another column
  • a plurality of third sub-pixels P3 may be arranged in another column.
  • the light-emitting element of at least one sub-pixel may be divided into two light-emitting units along the second direction Y.
  • the light-emitting element of the first sub-pixel P1 may include: a first light-emitting unit P1-1 and a second light-emitting unit P1-2 arranged along the second direction Y;
  • the light-emitting element of the second sub-pixel P2 may include: a first light-emitting unit P2-1 and a second light-emitting unit P2-2 arranged along the second direction Y;
  • the light-emitting element of the third sub-pixel P3 may include: a first light-emitting unit P3-1 and a second light-emitting unit P3-2 arranged along the second direction Y.
  • the first light-emitting units P1-1, P2-1 and P3-1 may be arranged in a row in sequence, and the second light-emitting units P1-2, P2-2 and P3-2 may be arranged in a row in sequence.
  • the first light-emitting unit P1-1 and the second light-emitting unit P1-2 may be arranged at intervals
  • the first light-emitting unit P2-1 and the second light-emitting unit P2-2 may be arranged at intervals
  • the first light-emitting unit P3-1 and the second light-emitting unit P3-2 may be arranged at intervals.
  • the light-emitting region of at least one light-emitting element may include the light-emitting region of a first light-emitting unit and the light-emitting region of a second light-emitting unit of the light-emitting element.
  • the light-emitting region of the first light-emitting unit and the light-emitting region of the second light-emitting unit of at least one light-emitting element may be isolated from each other.
  • the area of the light-emitting region of the first light-emitting unit of at least one light-emitting element may be substantially the same as the area of the light-emitting region of the second light-emitting unit.
  • the shape of the first light-emitting unit of at least one light-emitting element may be substantially the same as the shape of the second light-emitting unit.
  • this embodiment is not limited to this.
  • the shapes of the two light-emitting units of at least one light-emitting element may be different; for another example, the areas of the light-emitting regions of the two light-emitting units of at least one light-emitting element may be different, for example, the area of the light-emitting region of the first light-emitting unit may be greater than the area of the light-emitting region of the second light-emitting unit.
  • FIG4 is a schematic diagram of a pixel circuit of at least one embodiment of the present disclosure.
  • the pixel circuit may include at least: a driving subcircuit 11, a data writing subcircuit 12, a storage subcircuit 13, and a control subcircuit 14.
  • the data writing subcircuit 12 may be electrically connected to the first scan line GL1, the data line DL, and the driving subcircuit 11, and configured to provide the driving subcircuit 11 with a data signal transmitted by the data line DL under the control of the first scan line GL1.
  • the driving subcircuit 11 may be electrically connected to the storage subcircuit 13, the data writing subcircuit 12, the control subcircuit 14, and the first light-emitting unit EL1, and configured to drive the first light-emitting unit EL1 to emit light.
  • the storage subcircuit 13 may be electrically connected to the driving subcircuit 11 and the first power line VDD.
  • the control subcircuit 14 may be electrically connected to the second scan line GL2, the driving subcircuit 11, the first light-emitting unit EL1, and the second light-emitting unit EL2, and configured to control the second light-emitting unit EL2 to emit light together with the first light-emitting unit EL1 under the control of the second scan line GL2.
  • the first light emitting unit EL1 may include a first anode, a first organic light emitting layer, and a first cathode stacked.
  • the second light emitting unit EL2 may include a second anode, a second organic light emitting layer, and a second cathode stacked.
  • the first anode of the first light emitting unit EL1 may be electrically connected to the driving subcircuit 11 and the control subcircuit 14, and the first cathode may be electrically connected to the second power line VSS.
  • the second anode of the second light emitting unit EL2 may be electrically connected to the control subcircuit 14, and the second cathode may be electrically connected to the second power line VSS.
  • the first power line VDD can be configured to continuously provide a first voltage signal of a high potential
  • the second power line VSS can be configured to continuously provide a second voltage signal of a low potential.
  • the first voltage signal is greater than the second voltage signal.
  • the gate driving circuit disposed in the peripheral area of the display panel may include: a first scan driver and a second scan driver.
  • the first scan driver may be configured to provide a first scan signal to a first scan line
  • the second scan driver may be configured to provide a second scan signal to a second scan line.
  • a plurality of transistors of a pixel circuit may be low-temperature polysilicon thin-film transistors, or may be oxide thin-film transistors, or may be low-temperature polysilicon thin-film transistors and oxide thin-film transistors.
  • the active layer of the low-temperature polysilicon thin-film transistor is low-temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin-film transistor is oxide (Oxide).
  • LTPS Low Temperature Poly-Silicon
  • oxide thin-film transistor oxide (Oxide).
  • Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current.
  • low-temperature polysilicon thin-film transistors and oxide thin-film transistors can be integrated on a display panel to form a low-temperature polycrystalline oxide display panel, which can take advantage of the advantages of both, can achieve high resolution (PPI, Pixel Per Inch), low-frequency driving, can reduce power consumption, and can improve display quality.
  • PPI Pixel Per Inch
  • this embodiment is not limited to this.
  • FIG5 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure.
  • the pixel circuit may be a 3T1C structure.
  • the driving subcircuit 11 may include a driving transistor T3
  • the data writing subcircuit 12 may include a data writing transistor T4
  • the storage subcircuit 13 may include a storage capacitor Cst
  • the control subcircuit 14 may include a first control transistor T8.
  • the gate of the data write transistor T4 is electrically connected to the first scan line GL1, the first electrode of the data write transistor T4 is electrically connected to the data line DL, and the second electrode of the data write transistor T4 is electrically connected to the first electrode plate of the storage capacitor Cst1.
  • the second electrode plate of the storage capacitor Cst is electrically connected to the first power line VDD.
  • the gate of the drive transistor T3 is electrically connected to the first electrode plate of the storage capacitor Cst, the first electrode of the drive transistor T3 is electrically connected to the first power line VDD, and the second electrode of the drive transistor T3 is electrically connected to the first anode of the first light-emitting unit EL1.
  • the gate of the first control transistor T8 is electrically connected to the second scan line GL2, the first electrode of the first control transistor T8 is electrically connected to the first anode of the first light-emitting unit EL1, and the second electrode of the first control transistor T8 is electrically connected to the second anode of the second light-emitting unit EL2.
  • the driving transistor T3, the data writing transistor T4 and the first control transistor T8 as P-type transistors, when the first scanning signal provided by the first scanning line GL1 is a low-level signal, the data writing transistor T4 is turned on, the storage capacitor Cst is charged, and the data signal transmitted by the data line DL is stored in the storage capacitor Cst.
  • the data signal stored in the storage capacitor Cst can control the conduction degree of the driving transistor T3 to drive the first light-emitting unit EL1 to emit light.
  • the first control transistor T8 When the second scanning signal provided by the second scanning line GL2 is a high-level signal, the first control transistor T8 is turned off, and the second light-emitting unit EL2 does not emit light; when the second scanning signal provided by the second scanning line GL2 is a low-level signal, the first control transistor T8 is turned on, and the second light-emitting unit EL2 can emit light together with the first light-emitting unit EL1.
  • the second scan signal provided by the second scan line GL2 can be continuously a high-level signal, so that the first control transistor T8 is turned off, and the driving transistor T3 can only drive the first light-emitting unit EL1 to emit light under the control of the data signal.
  • the second scan signal provided by the second scan line GL2 can be a low-level signal, and the first control transistor T8 is turned on, so that the driving transistor T3 can simultaneously drive the first light-emitting unit EL1 and the second light-emitting unit EL2 to emit light under the control of the data signal.
  • FIG6 is another equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure.
  • the pixel circuit may be an 8T1C structure.
  • the driving subcircuit 11 may include a driving transistor T3
  • the data writing subcircuit 12 may include a data writing transistor T4
  • the storage subcircuit 13 may include a storage capacitor Cst
  • the control subcircuit 14 may include a first control transistor T8.
  • the pixel circuit may also include: a first reset transistor T1, a second reset transistor T7, a threshold compensation transistor T2, a first light emission control transistor T5, and a second light emission control transistor T6.
  • the gate of the first reset transistor T1 is electrically connected to the first reset control line RST1
  • the first electrode of the first reset transistor T1 is electrically connected to the first initial signal line INIT1
  • the second electrode of the first reset transistor T1 is electrically connected to the first node N1.
  • the gate of the threshold compensation transistor T2 is electrically connected to the first scan line GL1
  • the first electrode of the threshold compensation transistor T2 is electrically connected to the first node N1
  • the second electrode of the threshold compensation transistor T2 is electrically connected to the third node N3.
  • the gate of the driving transistor T3 is electrically connected to the first node N1, the first electrode of the driving transistor T3 is electrically connected to the second node N2, and the second electrode of the driving transistor T3 is electrically connected to the third node N3.
  • the gate of the data writing transistor T4 is electrically connected to the first scan line GL1, the first electrode of the data writing transistor T4 is electrically connected to the data line DL, and the second electrode of the data writing transistor T4 is electrically connected to the second node N2.
  • the gate of the first light emission control transistor T5 is electrically connected to the light emission control line EML, the first electrode of the first light emission control transistor T5 is electrically connected to the first power supply line VDD, and the second electrode of the first light emission control transistor T5 is electrically connected to the second node N2.
  • the gate of the second light emission control transistor T6 is electrically connected to the light emission control line EML, the first electrode of the second light emission control transistor T6 is electrically connected to the third node N3, and the second electrode of the second light emission control transistor T6 is electrically connected to the fourth node N4.
  • the gate of the second reset transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the second reset transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the second reset transistor T7 is electrically connected to the fourth node N4.
  • the gate of the first control transistor T8 is electrically connected to the second scan line GL2, the first electrode of the first control transistor T8 is electrically connected to the fourth node N4, and the second electrode of the first control transistor T8 is electrically connected to the second anode of the second light emitting unit EL2.
  • the first electrode plate of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode of the storage capacitor Cst is electrically connected to the first power line VDD.
  • the first anode of the first light emitting unit EL1 is electrically connected to the fourth node N4, and the first cathode is electrically connected to the second power line VSS.
  • the first anode of the second light emitting unit EL2 is electrically connected to the second electrode of the first control transistor T8, and the second cathode is electrically connected to the second power line VSS.
  • the first node N1 is a connection point of the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3 and the storage capacitor Cst.
  • the second node N2 is a connection point of the driving transistor T3, the data writing transistor T4 and the first light emission control transistor T5.
  • the third node N3 is a connection point of the driving transistor T3, the threshold compensation transistor T2 and the second light emission control transistor T6.
  • the fourth node N4 is a connection point of the second light emission control transistor T6, the second reset transistor T7, the first control transistor T8 and the first anode of the first light emitting unit EL1.
  • the eight transistors of the pixel circuit are all P-type transistors.
  • the second reset control line RST2 can be connected to the first scan line GL1 to be input with the first scan signal.
  • the second scan line GL2 can continuously provide a high-level second scan signal, so that the first control transistor T8 is disconnected, and the second light-emitting unit EL2 is in a non-luminous state.
  • the second scan line GL2 can continuously provide a low-level second scan signal, so that the first control transistor T8 is turned on, and the second light-emitting unit EL2 can emit light together with the first light-emitting unit EL1.
  • the operation process of the pixel circuit may include:
  • the first stage is called the reset stage.
  • the first reset control signal provided by the first reset control line RST1 is a low-level signal, so that the first reset transistor T1 is turned on.
  • the first initial signal provided by the first initial signal line INIT1 can be provided to the first node N1 to initialize the first node N1 and clear the original data voltage in the storage capacitor Cst.
  • the first scan signal provided by the first scan line GL1 is a high-level signal
  • the light control signal provided by the light control line EML is a high-level signal, so that the data writing transistor T4, the threshold compensation transistor T2, the first light control transistor T5, the second light control transistor T6 and the second reset transistor T7 are turned off.
  • the first light-emitting unit EL1 does not emit light.
  • the second stage is called the data writing stage or the threshold compensation stage.
  • the first scanning signal provided by the first scanning line GL1 is a low level signal
  • the first reset control signal provided by the first reset control line RST1 and the light control signal provided by the light emitting control line EML are both high level signals
  • the data line DL outputs a data signal.
  • the driving transistor T3 since the first plate of the storage capacitor Cst is at a low level, the driving transistor T3 is turned on.
  • the first scanning signal is a low level signal, which turns on the threshold compensation transistor T2, the data writing transistor T4 and the second reset transistor T7.
  • the threshold compensation transistor T2 and the data writing transistor T4 are turned on, so that the data voltage output by the data line DL is provided to the first node N1 through the second node N2, the turned-on driving transistor T3, the third node N3, and the turned-on threshold compensation transistor T2, and the difference between the data voltage output by the data line DL and the threshold voltage of the driving transistor T3 is charged into the storage capacitor Cst, and the voltage of the first plate (i.e., the first node N1) of the storage capacitor Cst is Vdata-
  • the second reset transistor T7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is provided to the fourth node N4, and the fourth node N4 is initialized to ensure that the first light-emitting unit EL1 does not emit light.
  • the first reset control signal provided by the first reset control line RST1 is a high-level signal, which turns off the first reset transistor T1.
  • the light-emitting control signal provided by the light-emitting control signal line EML is a high-level signal, which turns off the first light-emitting control transistor T5 and the second light-emitting control transistor T6.
  • the third stage is called the light-emitting stage.
  • the light-emitting control signal provided by the light-emitting control signal line EML is a low-level signal, and the first scanning signal provided by the first scanning line GL1 and the first reset control signal provided by the first reset control line RST1 are high-level signals.
  • the light-emitting control signal provided by the light-emitting control signal line EML is a low-level signal, which turns on the first light-emitting control transistor T5 and the second light-emitting control transistor T6.
  • the first voltage signal output by the first power line VDD provides a driving voltage to the first anode of the first light-emitting unit EL1 through the turned-on first light-emitting control transistor T5, the driving transistor T3 and the second light-emitting control transistor T6, thereby driving the first light-emitting unit EL1 to emit light.
  • the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-
  • )-Vth] 2 K ⁇ [(Vdd-Vdata)] 2 ;
  • I is the driving current flowing through the driving transistor T3, that is, the driving current driving the light emitting element EL
  • K is a constant
  • Vgs is the voltage difference between the gate and the first electrode of the driving transistor T3
  • Vth is the threshold voltage of the driving transistor T3
  • Vdata is the data voltage output by the data line DL
  • Vdd is the first voltage signal output by the first power line VDD.
  • the driving current has nothing to do with the threshold voltage of the driving transistor T3. Therefore, the pixel circuit of this embodiment can better compensate for the threshold voltage of the driving transistor T3.
  • the above pixel circuit is only an example, and the present embodiment does not limit the structure of the pixel circuit.
  • the first light-emitting unit EL1 of the light-emitting element of the sub-pixel is lit, and the second light-emitting unit EL2 is not lit, which can limit the light-emitting area and light-emitting angle of the sub-pixel; in the sharing display mode, the first light-emitting unit EL1 and the second light-emitting unit EL2 of the light-emitting element of the sub-pixel can be lit at the same time, which can increase the light-emitting area and light-emitting angle of the sub-pixel.
  • This example can switch to achieve the anti-peeping effect and the sharing effect.
  • FIG7 is an example diagram of a partial cross-section along the Q-Q’ direction in FIG3.
  • FIG7 illustrates a partial cross-sectional structure of a first sub-pixel P1.
  • the display panel in a direction perpendicular to the display panel, may include: a base substrate 101, a display structure layer sequentially arranged on the base substrate 101, an encapsulation structure layer 104, a first shielding layer 105, a first protective layer 106, and a second shielding layer 107.
  • the display structure layer may include: a circuit structure layer 102 and a light-emitting structure layer 103 sequentially arranged on the base substrate 101.
  • the display panel may include other film layers, such as spacers, etc., which are not limited in the present disclosure.
  • the preparation process of the display panel is exemplarily described below with reference to FIG. 7.
  • the "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials.
  • Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition
  • coating can be any one or more of spraying, spin coating, and inkjet printing
  • etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure.
  • Thin film refers to a layer of thin film made of a certain material on a substrate by deposition, coating, or other processes. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the orthographic projection of A contains the orthographic projection of B means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • the manufacturing process of the display panel may include the following operations.
  • the substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the rigid substrate may include a glass substrate.
  • the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together.
  • the first flexible material layer and the second flexible material layer may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film.
  • the first inorganic material layer and the second inorganic material layer may be made of silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate.
  • the semiconductor layer may be made of amorphous silicon (a-Si). However, this embodiment is not limited to this.
  • the circuit structure layer 102 may include: transistors and storage capacitors of multiple pixel circuits.
  • FIG7 illustrates a structure of two transistors (e.g., a first transistor 201 and a second transistor 202) and a storage capacitor 203 in a pixel circuit as an example.
  • the first transistor 201 may be the driving transistor T3, the second reset transistor T7, or the second light-emitting control transistor T6 in the aforementioned pixel circuit
  • the second transistor 202 may be the first control transistor T8 in the aforementioned pixel circuit
  • the storage capacitor 203 may be the storage capacitor Cst in the aforementioned pixel circuit.
  • the circuit structure layer 102 may include: a buffer layer 210, a semiconductor layer, a first insulating layer 211, a first gate metal layer, a second insulating layer 212, a second gate metal layer, a third insulating layer 213, a first source and drain metal layer, and a fourth insulating layer 214, which are sequentially arranged on the base substrate 101.
  • a buffer film and a semiconductor film are sequentially deposited, and the semiconductor film is patterned by a patterning process to form a buffer layer 210 and a semiconductor layer disposed on the buffer layer 210.
  • the semiconductor layer may include at least: an active layer of the first transistor 201 and an active layer of the second transistor 202.
  • a first insulating film and a first conductive film are sequentially deposited on the base substrate 101 having the aforementioned structure, and the first conductive film is patterned by a patterning process to form a first insulating layer 211 and a first gate metal layer disposed on the first insulating layer 211.
  • the first gate metal layer may at least include: a gate of the first transistor 201, a gate of the second transistor 202, and a first plate of the storage capacitor 203.
  • the semiconductor layer after forming the first gate metal layer, can be conductorized using the first gate metal layer as a shield, the semiconductor layer in the area shielded by the first gate metal layer can form a channel region of the transistor, and the semiconductor layer in the area not shielded by the first gate metal layer can be conductorized, that is, the first region and the second region of the active layer of multiple transistors of the pixel circuit are both conductive.
  • a second insulating film and a second conductive film are sequentially deposited on the substrate substrate on which the aforementioned structure is formed, and the second conductive film is patterned by a patterning process to form a second insulating layer 212 and a second gate metal layer disposed on the second insulating layer 212.
  • the second gate metal layer may at least include: a second electrode plate of the storage capacitor 203.
  • the orthographic projection of the second electrode plate of the storage capacitor 203 on the substrate substrate may at least partially overlap with the orthographic projection of the first electrode plate on the substrate substrate.
  • a third insulating film is deposited on the substrate substrate having the aforementioned structure, and the third insulating film is patterned by a patterning process to form a third insulating layer 213.
  • the third insulating layer 213 may be provided with a plurality of vias.
  • the plurality of vias of the third insulating layer 213 may expose the surfaces of the semiconductor layer, the first gate metal layer, and the second gate metal layer, respectively.
  • a third conductive film is deposited on the substrate substrate forming the aforementioned structure, and the third conductive film is patterned by a patterning process to form a first source-drain metal layer on the third insulating layer 213.
  • the first source-drain metal layer may at least include: a first electrode and a second electrode of the first transistor 201, and a first electrode and a second electrode of the second transistor 202.
  • the second electrode of the first transistor 201 and the first electrode of the second transistor 202 may be an integrated structure.
  • a fourth insulating film is coated on the substrate substrate forming the aforementioned structure, and a fourth insulating layer 214 is formed by a patterning process.
  • the buffer layer 210, the first insulating layer 211, the second insulating layer 212 and the third insulating layer 213 may be inorganic insulating layers, and the fourth insulating layer 214 may be an organic insulating layer.
  • the buffer layer 210, the first insulating layer 211, the second insulating layer 212 and the third insulating layer 213 may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer.
  • the first insulating layer 211 and the second insulating layer 212 may be referred to as a gate insulating (GI) layer
  • the third insulating layer 213 may be referred to as an interlayer insulating (ILD) layer
  • the fourth insulating layer 214 may be referred to as a planar layer.
  • the first gate metal layer, the second gate metal layer and the first source and drain metal layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti, etc.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the semiconductor layer may be made of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.
  • a-IGZO amorphous indium gallium zinc oxide material
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • sexithiophene or polythiophene sexithiophene or polythiophene
  • the light emitting structure layer 103 may include a plurality of light emitting elements.
  • an anode film is deposited on a substrate substrate forming the aforementioned structure, and the anode film is patterned by a patterning process to form an anode layer.
  • the anode layer may include: a first anode 301a of a first light-emitting unit and a second anode 301b of a second light-emitting unit.
  • the first anode 301a and the second anode 301b may be independent of each other.
  • the planes where the first anode 301a and the second anode 301b are located may be flush.
  • the first anode 301a may be electrically connected to the second electrode of the first transistor 201 of the pixel circuit through a via hole opened in the fourth insulating layer 214
  • the second anode 301b may be electrically connected to the second electrode of the second transistor 202 of the pixel circuit through a via hole opened in the fourth insulating layer 214.
  • a pixel definition film is coated on the substrate substrate forming the aforementioned structure, and a pixel definition layer 304 is formed by masking, exposure and development processes.
  • the pixel definition layer 304 is formed with a plurality of pixel openings exposing the anode layer.
  • the plurality of pixel openings may include a first pixel opening and a second pixel opening.
  • the first pixel opening may expose at least a portion of the first anode 301a
  • the second pixel opening may expose at least a portion of the second anode 301b.
  • an organic light-emitting layer is formed in the pixel opening formed above.
  • a first organic light-emitting layer 302a is formed in the first pixel opening, and the first organic light-emitting layer 302a is connected to the first anode 301a;
  • a second organic light-emitting layer 302b is formed in the second pixel opening, and the second organic light-emitting layer 302b is connected to the second anode 301b.
  • the cathode layer may include a first cathode 303a of a first light-emitting unit and a second cathode 303b of a second light-emitting unit.
  • the first cathode 303a is connected to the first organic light-emitting layer 302a
  • the second cathode 303b is connected to the second organic light-emitting layer 302b.
  • the first cathode 303a and the second cathode 303b may be an integral structure.
  • the first organic light-emitting layer 302a may emit light of a corresponding color under the action of a voltage applied by the first anode 301a and the first cathode 303a; the second organic light-emitting layer 302b may emit light of a corresponding color under the action of a voltage applied by the second anode 301b and the second cathode 303b.
  • the first light-emitting unit and the second light-emitting unit of the first subpixel P1 may both be configured to emit red light.
  • the pixel definition layer 304 may be made of organic materials such as polyimide, acrylic, polyethylene terephthalate, or acrylate.
  • the pixel definition layer 304 may be black. By setting the black pixel definition layer 304, the reflected light and the refracted light in the film layer can be absorbed, thereby improving the light emitting effect of the light emitting element.
  • this embodiment is not limited to this.
  • the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).
  • HIL stacked hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • EML emitting layer
  • HBL hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • the first organic light-emitting layer 302a of the first light-emitting unit and the second organic light-emitting layer 302a of the second light-emitting unit may be isolated from each other. However, this embodiment is not limited to this.
  • the hole injection layers of all sub-pixels may be a common layer connected together
  • the electron injection layers of all sub-pixels may be a common layer connected together
  • the hole transport layers of all sub-pixels may be a common layer connected together
  • the electron transport layers of all sub-pixels may be a common layer connected together
  • the hole blocking layers of all sub-pixels may be a common layer connected together
  • the light-emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated
  • the electron blocking layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated.
  • the light emitting region of the light emitting unit may be an overlapping region of the anode, the organic light emitting layer, and the cathode exposed by the pixel opening of the pixel definition layer.
  • the light emitting region of the first light emitting unit may be an overlapping region of the first anode, the first organic light emitting layer, and the first cathode within the first pixel opening of the pixel definition layer.
  • the light emitting region of the second light emitting unit may be an overlapping region of the second anode, the second organic light emitting layer, and the second cathode within the second pixel opening of the pixel definition layer.
  • the encapsulation structure layer 104 is located on the side of the cathode layer away from the base substrate 101.
  • the encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together, wherein the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer may be arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.
  • the encapsulation structure layer 104 may be a stacked structure of inorganic material/organic material/inorganic material/organic material/inorganic material.
  • a black pigment is coated or a black chromium (Cr) film is deposited on the base substrate forming the aforementioned structure, and the black pigment or the black chromium film is patterned by a patterning process to form the first shielding layer 105.
  • the orthographic projection of the first shielding layer 105 on the base substrate 101 can be located within the orthographic projection range of the pixel definition layer 304 on the base substrate 101.
  • FIG8 is a schematic plan view of the first shielding layer of at least one embodiment of the present disclosure.
  • the orthographic projection of the first shielding layer 105 on the substrate substrate may not overlap with the orthographic projection of the light-emitting area of the light-emitting element of the first sub-pixel, the second sub-pixel, and the third sub-pixel on the substrate substrate.
  • the orthographic projection of the first shielding layer 105 on the substrate substrate may surround the orthographic projection of the first light-emitting unit P1-1 of the first sub-pixel, the first light-emitting unit P2-1 of the second sub-pixel, and the first light-emitting unit P3-1 of the third sub-pixel.
  • the orthographic projection of the first shielding layer 105 on the substrate substrate may surround the orthographic projection of the light-emitting area of the first light-emitting unit P1-1 of the first sub-pixel, the light-emitting area of the first light-emitting unit P2-1 of the second sub-pixel, and the light-emitting area of the first light-emitting unit P3-1 of the third sub-pixel.
  • the light-emitting area of the first light-emitting unit P1-1, the light-emitting area of the first light-emitting unit P2-1 of the second sub-pixel, and the light-emitting area of the first light-emitting unit P3-1 of the third sub-pixel may be surrounded by the first shielding layer 105.
  • the first shielding layer 105 may not be provided between adjacent second light-emitting units.
  • the emission angle of the first light-emitting unit can be limited, so that the emitted light of the first light-emitting unit is concentrated in the direction of the positive viewing angle, which is conducive to achieving an anti-peeping effect.
  • a first protective film is coated on the substrate forming the aforementioned structure, and a first protective (OC, Over Coat) layer 106 is formed by a patterning process.
  • the first protective layer 106 can be made of materials such as acrylic esters.
  • a black pigment is coated or a black chromium (Cr) film is deposited on the base substrate forming the aforementioned structure, and the black pigment or the black chromium film is patterned by a patterning process to form the second shielding layer 107.
  • Cr black chromium
  • the orthographic projection of the second shielding layer 107 on the substrate 101 may be located within the orthographic projection range of the pixel definition layer 304 on the substrate 101.
  • the orthographic projection of the second shielding layer 107 on the substrate may surround the first light-emitting unit, and may not overlap with the orthographic projections of the light-emitting regions of the first light-emitting unit and the second light-emitting unit on the substrate.
  • the orthographic projection of the second shielding layer 107 on the substrate may be located within the orthographic projection range of the first shielding layer 105 on the substrate.
  • the orthographic projection of the second shielding layer 107 on the substrate may overlap with the orthographic projection of the first shielding layer 105 on the substrate.
  • this embodiment is not limited to this.
  • two shielding layers are provided to surround the first light-emitting unit, so as to limit the emission angle of the first light-emitting unit, thereby facilitating the anti-peeping effect.
  • This embodiment does not limit the number of shielding layers. In other examples, the number of shielding layers may be greater than or equal to three, and a protective layer may be provided between adjacent shielding layers. In other examples, the shielding layer may surround the light-emitting element.
  • the structure of the display panel of the exemplary embodiment of the present disclosure and its preparation process are merely exemplary.
  • the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.
  • the display structure layer can also include a second source-drain metal layer located on the side of the first source-drain metal layer away from the substrate, and the second source-drain metal layer can include an anode connection electrode, and the first anode of the first light-emitting unit and the second anode of the second light-emitting unit can be electrically connected to the pixel circuit through the anode connection electrode, respectively.
  • the present disclosure is not limited here.
  • FIG9 is another partial cross-sectional example diagram along the Q-Q' direction in FIG3.
  • the display panel may include: a base substrate 101, a display structure layer, an encapsulation structure layer 104, a first shielding layer 105, a first protective layer 106, and a color filter layer 108 arranged sequentially on the base substrate 101.
  • the display structure layer may include: a circuit structure layer 102 and a light emitting structure layer 103 arranged sequentially on the base substrate 101.
  • the structures of the display structure layer, the encapsulation structure layer 104, the first shielding layer 105, and the first protective layer 106 can refer to the description of the aforementioned embodiment, so they are not repeated here.
  • the color filter layer 108 may be located on a side of the first protective layer 106 away from the base substrate 101.
  • the color filter layer 108 may include: a plurality of filter units arranged periodically and a black matrix 800 disposed between adjacent filter units.
  • the plurality of filter units may correspond one-to-one to the light-emitting elements of the plurality of sub-pixels.
  • the plurality of filter units may include a first filter unit 801, a second filter unit, and a third filter unit.
  • the first filter unit 801 may correspond to the light-emitting element of the first sub-pixel P1, the second filter unit may correspond to the light-emitting element of the second sub-pixel P2, and the third filter unit may correspond to the light-emitting element of the third sub-pixel P3.
  • the first filter unit 801 may be a red filter unit
  • the second filter unit may be a green filter unit
  • the third filter unit may be a blue filter unit.
  • the filter unit can allow a single color of light to pass through and absorb other colors of light.
  • the blue filter unit can allow blue light to pass through and absorb other colors of light
  • the red filter unit can allow red light to pass through and absorb other colors of light
  • the green filter unit can allow green light to pass through and absorb other colors of light.
  • At least one filter unit may include: a first sub-filter unit and a second sub-filter unit.
  • the orthographic projection of the filter unit on the substrate substrate may cover the orthographic projection of the light-emitting area of the corresponding light-emitting element on the substrate substrate.
  • the first filter unit 801 may include a first sub-filter unit 801a and a second sub-filter unit 801b.
  • the orthographic projection of the first sub-filter unit 801a on the substrate substrate 101 may cover the orthographic projection of the light-emitting area of the first light-emitting unit of the first sub-pixel on the substrate substrate 101; the orthographic projection of the second sub-filter unit 801b on the substrate substrate 101 may cover the orthographic projection of the light-emitting area of the second light-emitting unit of the first sub-pixel on the substrate substrate 101.
  • this embodiment is not limited to this.
  • the orthographic projection of a filter unit on the substrate substrate may cover the orthographic projection of the light-emitting area of the first light-emitting unit and the second light-emitting unit of the corresponding light-emitting element on the substrate substrate.
  • the color filter layer 108 can be prepared in the following manner: coating a black pigment or depositing a black chrome (Cr) film on the first protective layer 106, patterning the black pigment or the black chrome film through a patterning process to form a black matrix 800; then, forming a plurality of first filter units 801, a plurality of second filter units, and a plurality of third filter units in sequence.
  • a red filter unit 801 as a red filter unit as an example, a red resin is first coated on the first protective layer 106 on which the black matrix 800 has been formed, and after baking and curing, a red filter unit is formed by exposing and developing through a mask. The formation process of the green filter unit and the blue filter unit is similar, so it will not be repeated here.
  • the emission angle of the first light-emitting unit is limited, thereby facilitating the anti-peeping effect.
  • This embodiment does not limit the number of shielding layers.
  • at least two shielding layers may be provided between the encapsulation structure layer and the color filter layer, and a protective layer may be provided between adjacent shielding layers.
  • FIG10 is a schematic diagram of light emission of the cross-sectional structure along the R-R’ direction in FIG3.
  • FIG11 is a schematic diagram of light emission of the cross-sectional structure along the U-U’ direction in FIG3. Part of the film layers of the base substrate and the display structure layer are omitted in FIG10 and FIG11.
  • FIG10 is illustrated by taking the emission light of the first light-emitting unit P1-1 of the first sub-pixel P1 and the first light-emitting unit P2-1 of the second sub-pixel P2 as an example;
  • FIG11 is illustrated by taking the emission light of the second light-emitting unit P1-2 of the first sub-pixel P1 and the second light-emitting unit P2-2 of the second sub-pixel P2 as an example.
  • the emission light L1 of the first sub-pixel P1 can be represented by a dotted line with an arrow
  • the emission light L2 of the second sub-pixel P2 can be represented by a dotted line with an arrow
  • the light L3 absorbed by the film layer in the display panel can be represented by a solid line with an arrow.
  • the normal viewing angle direction may be a direction perpendicular to the plane where the display panel is located.
  • the oblique viewing angle direction may refer to a sight line direction other than the normal viewing angle direction.
  • the orthographic projection of the first shielding layer 105 on the base substrate can surround the light-emitting area of the first light-emitting unit P1-1.
  • the outgoing light of the first light-emitting unit P1-1 of the first sub-pixel P1 can be emitted in the normal viewing direction, and the outgoing light of the first light-emitting unit P1-1 in the right oblique viewing direction will be absorbed by the first shielding layer 105 and the black matrix 800 of the color filter layer 108, and the outgoing light of the first light-emitting unit P1-1 in the left oblique viewing direction will be absorbed by the first shielding layer 105 and the black matrix 800 of the color filter layer 108.
  • the outgoing light of the first light-emitting unit P2-1 of the second sub-pixel P2 can be emitted in the normal viewing direction, and the outgoing light in the oblique viewing direction will be absorbed by the first shielding layer 105 and the black matrix 800 of the color filter layer 108.
  • the emission angle of the light emitted by the first light emitting unit is limited by the first shielding layer 105 and the black matrix 800 of the color filter layer 108, which can improve the anti-peeping effect of the display panel along the first direction X.
  • no first shielding layer is provided between adjacent second light-emitting units (e.g., second light-emitting units P1-2 and P2-2).
  • the size of the black matrix 800 between adjacent second light-emitting units may be smaller than the size of the black matrix 800 between adjacent first light-emitting units.
  • the outgoing light of the second light-emitting unit P1-2 of the first subpixel P1 may be emitted not only in the direction of the normal viewing angle, but also in the direction of a partial oblique viewing angle.
  • the outgoing angle of the outgoing light of the second light-emitting unit in this example may be greater than the outgoing angle of the outgoing light of the first light-emitting unit.
  • the first light-emitting unit and the second light-emitting unit may be lit at the same time, and the outgoing angle of the outgoing light of the second light-emitting unit is greater than the outgoing angle of the outgoing light of the first light-emitting unit, which is conducive to achieving a shared display effect, thereby improving the user experience.
  • FIG. 12 is another partial cross-sectional example diagram along the Q-Q' direction in FIG. 3.
  • the display panel in a direction perpendicular to the display panel, the display panel may include: a substrate 101, a display structure layer sequentially arranged on the substrate 101, an encapsulation structure layer 104, a first shielding layer 105, a first protective layer 106, and a second shielding layer 107.
  • the display structure layer may include: a circuit structure layer 102 and a light emitting structure layer 103 sequentially arranged on the substrate 101.
  • the first anode 301a of the first light emitting unit P1-1 and the second anode 201b of the second light emitting unit P1-2 may not be located in the same plane.
  • the first anode 301a may be located on the side of the second anode 301b close to the substrate 101.
  • the thickness of the fourth insulating layer 214 on the side of the second anode 301b close to the substrate 101 may be greater than the thickness of the fourth insulating layer 214 on the side of the first anode 301b close to the substrate 101, so that the first anode 301a and the second anode 301b are not in the same plane.
  • the height of the pixel definition layer 304 around the second anode 301 b may be greater than the height of the pixel definition layer 304 around the first anode 301 a .
  • the height of the film layer may refer to the distance from the surface of the film layer away from the substrate to the plane where the substrate is located.
  • the thickness of the film layer may refer to the distance between the surface of the film layer away from the substrate and the surface close to the substrate.
  • the distance between the first anode 301a of the first light-emitting unit P1-1 and the light-emitting surface is greater than the distance between the second anode 301b of the second light-emitting unit P1-2 and the light-emitting surface, so that the emission angle range of the first light-emitting unit P1-1 is smaller than the emission angle range of the second light-emitting unit P1-2.
  • the emission light of the first light-emitting unit P1-1 is concentrated in the direction of the normal viewing angle, and the emission angle of the emission light of the second light-emitting unit P1-2 can be greater than the emission angle of the emission light of the first light-emitting unit P1-1.
  • the remaining structure of the display panel of this embodiment can refer to the description of the aforementioned embodiment, so it is not repeated here.
  • the emission angle of the second light-emitting unit can be increased. In this way, when the first light-emitting unit is lit, an anti-peeping display effect can be achieved, and when the first light-emitting unit and the second light-emitting unit are lit at the same time, a shared display effect can be achieved.
  • FIG. 13 is another partial cross-sectional example diagram along the Q-Q' direction in FIG. 3.
  • the display panel may include: a substrate 101, a display structure layer sequentially arranged on the substrate 101, an encapsulation structure layer 104, a first shielding layer 105, a light adjustment layer 110, a first protective layer 106, and a second shielding layer 107.
  • the display structure layer may include: a circuit structure layer 102 and a light emitting structure layer 103 sequentially arranged on the substrate 101.
  • a light adjustment layer 110 may be arranged on the side of the first shielding layer 105 away from the substrate 101.
  • the light adjustment layer 110 may include at least one lens unit 111.
  • the orthographic projection of the lens unit 111 on the substrate 101 may at least partially overlap with the orthographic projection of the light emitting area of the first light emitting unit P1-1 on the substrate.
  • the lens unit 111 may be a convex lens.
  • the orthographic projection of the lens unit 111 on the substrate 101 may cover the orthographic projection of the light emitting area of the first light emitting unit P1-1 on the substrate 101.
  • the lens unit 111 may include a plurality of sub-lens units arranged in an array, and the orthographic projections of the plurality of sub-lens units on the substrate may be located within the orthographic projection range of the light emitting region of the first light emitting unit on the substrate.
  • the refractive index of the light adjustment layer 110 may be greater than the refractive index of the first protective layer 106.
  • the remaining structures of the display panel of this embodiment may refer to the description of the aforementioned embodiment, so they will not be described in detail here.
  • a light adjustment layer is provided on the outgoing light path of the first light emitting unit, which is beneficial to improving the light output efficiency of the first light emitting unit, thereby ensuring the anti-peeping display effect when the first light emitting unit is lit.
  • FIG. 14 is another partial cross-sectional example diagram along the Q-Q' direction in FIG. 3.
  • the display panel may include: a substrate 101, a display structure layer sequentially arranged on the substrate 101, an encapsulation structure layer 104, a first shielding layer 105, a second protective layer 109, a first protective layer 106, and a second shielding layer 107.
  • the display structure layer may include: a circuit structure layer 102 and a light emitting structure layer 103 sequentially arranged on the substrate 101.
  • the second protective layer 109 may be located on a side of the first protective layer 106 close to the substrate 101.
  • the orthographic projection of the second protective layer 109 on the substrate substrate may cover the orthographic projection of the first shielding layer 105 on the substrate substrate.
  • the orthographic projection of the first protective layer 106 on the substrate substrate may cover the orthographic projection of the second protective layer 109 on the substrate substrate.
  • the orthographic projection of the second protective layer 109 on the substrate substrate may not overlap with the orthographic projection of the light emitting area of the first light emitting unit and the second light emitting unit on the substrate substrate.
  • the refractive index of the second protective layer 109 may be less than that of the first protective layer 106.
  • the second protective layer 109 and the first protective layer 106 of this example may form an efficiency enhancement structure (EES), and the emitted light of the first light-emitting unit may be refracted and totally reflected by the first protective layer 106 and the second protective layer 109, so that the emitted light is concentrated in the direction of the normal viewing angle, thereby achieving an anti-peeping display effect.
  • EES efficiency enhancement structure
  • the remaining structures of the display panel of this embodiment may refer to the description of the aforementioned embodiment, so they will not be described here in detail.
  • the ESS is formed by the first protective layer and the second protective layer, which is beneficial to improving the light extraction efficiency of the first light-emitting unit, thereby ensuring the anti-peeping display effect when the first light-emitting unit is lit.
  • FIG15 is another partial cross-sectional example diagram along the Q-Q’ direction in FIG3.
  • the display panel may include: a base substrate 101, a display structure layer sequentially arranged on the base substrate 101, an encapsulation structure layer 104, a first shielding layer 105, a light adjustment layer 110, a first protective layer 106, and a second shielding layer 107.
  • the first anode 301a of the first light-emitting unit P1-1 and the second anode 201b of the second light-emitting unit P1-2 are not located in the same plane.
  • the first anode 301a may be located on the side of the second anode 301b close to the base substrate 101.
  • the remaining structure of the display panel of this embodiment can refer to the description of the aforementioned embodiment, so it will not be repeated here.
  • the first anode of the first light-emitting unit and the second anode of the second light-emitting unit not to be located in the same plane, and the first anode being located on the side of the second anode close to the base substrate, it is beneficial to increase the emission angle of the second light-emitting unit, and by setting a light adjustment layer on the emission light path of the first light-emitting unit, it is beneficial to improve the light emission efficiency of the first light-emitting unit, thereby ensuring the anti-peeping display effect when the first light-emitting unit is lit.
  • FIG16 is another partial cross-sectional example diagram along the Q-Q’ direction in FIG3 .
  • the display panel may include: a base substrate 101, a display structure layer sequentially arranged on the base substrate 101, an encapsulation structure layer 104, a first shielding layer 105, a second protective layer 109, a first protective layer 106, and a second shielding layer 107.
  • the first anode 301a of the first light-emitting unit P1-1 and the second anode 201b of the second light-emitting unit P1-2 are not located in the same plane.
  • the first anode 301a may be located on the side of the second anode 301b close to the base substrate 101.
  • the remaining structure of the display panel of this embodiment can refer to the description of the aforementioned embodiment, so it will not be repeated here.
  • the first anode of the first light-emitting unit and the second anode of the second light-emitting unit are not located in the same plane, and the first anode is located on the side of the second anode close to the base substrate, it is beneficial to increase the emission angle of the second light-emitting unit, and the ESS is formed by the first protective layer and the second protective layer, which is beneficial to improve the light extraction efficiency of the first light-emitting unit, thereby ensuring the anti-peeping display effect when the first light-emitting unit is lit.
  • the above embodiments may be combined with each other.
  • the display panel may include a first protective layer, a second protective layer and a light adjustment layer, and the first anode of the first light-emitting unit and the second anode of the second light-emitting unit may not be located in the same plane.
  • this embodiment is not limited to this.
  • FIG17 is another schematic plan view of a sub-pixel of a display panel according to at least one embodiment of the present disclosure.
  • a plurality of sub-pixels in a display area of the display panel may be arranged in an array, for example, they may be arranged in sequence along a first direction X and a second direction Y.
  • the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 may be arranged periodically, and along the second direction Y, the sub-pixels emitting light of the same color may be arranged in sequence.
  • the light-emitting element of at least one sub-pixel may be divided into two light-emitting units along the first direction X.
  • the light-emitting element of the first sub-pixel P1 may include: a first light-emitting unit P1-1 and a second light-emitting unit P1-2 arranged along the first direction X;
  • the light-emitting element of the second sub-pixel P2 may include: a first light-emitting unit P2-1 and a second light-emitting unit P2-2 arranged along the first direction X;
  • the light-emitting element of the third sub-pixel P3 may include: a first light-emitting unit P3-1 and a second light-emitting unit P3-2 arranged along the first direction X.
  • the light-emitting area of the first light-emitting unit and the light-emitting area of the second light-emitting unit of at least one light-emitting element may be isolated from each other.
  • the area of the light-emitting area of the first light-emitting unit of at least one light-emitting element may be greater than the area of the light-emitting area of the second light-emitting unit.
  • the light-emitting area of the first light-emitting unit and the light-emitting area of the second light-emitting unit of at least one light-emitting element may be rectangles or rounded rectangles of different sizes. However, this embodiment is not limited to this. In other examples, the area of the light-emitting area of the first light-emitting unit of at least one light-emitting element may be less than or equal to the area of the light-emitting area of the second light-emitting unit.
  • the first light-emitting unit of the light-emitting element of at least one sub-pixel can be configured to emit light, and the second light-emitting unit can be configured not to emit light; in the sharing display mode, the second light-emitting unit can be configured to emit light along with the first light-emitting unit.
  • the first light emitting unit and the second light emitting unit of the sub-pixel emitting the same color light are alternately arranged along the first direction X, and alternately arranged along the second direction Y.
  • the arrangement order of the first light emitting unit P1-1 and the second light emitting unit P1-2 of a first sub-pixel P1 may be different from the arrangement order of the first light emitting unit P1-1 and the second light emitting unit P1-2 of the adjacent first sub-pixel P1.
  • the first light emitting unit P1-1 of a first sub-pixel P1 may be located on the left side of the second light emitting unit P1-2, and the first light emitting unit P1-1 of the adjacent first sub-pixel P1 in the first direction X may be located on the right side of the second light emitting unit P1-2.
  • the arrangement order of the first light emitting unit P1-1 and the second light emitting unit P1-2 of a first sub-pixel P1 may be different from the arrangement order of the first light emitting unit P1-1 and the second light emitting unit P1-2 of the adjacent first sub-pixel P1.
  • the first light emitting unit P1-1 of a first sub-pixel P1 may be located on the left side of the second light emitting unit P1-2, and the first light emitting unit P1-1 of the adjacent first sub-pixel P1 in the second direction Y may be located on the right side of the second light emitting unit P1-2.
  • the arrangement of the two light emitting units of the second sub-pixel P2 and the third sub-pixel P3 is the same as that of the two light emitting units of the first sub-pixel P1, so it will not be described in detail here.
  • FIG18 is a schematic diagram of light emission in the cross-sectional structure along the V-V’ direction in FIG17 in the anti-peeping display mode.
  • FIG19 is a schematic diagram of light emission in the cross-sectional structure along the V-V’ direction in FIG17 in the sharing display mode.
  • FIG20 is a schematic diagram of light emission in the cross-sectional structure along the O-O’ direction in FIG17 in the sharing display mode.
  • FIG21 is a schematic diagram of the cross-sectional structure along the V-V’ direction in FIG17. Part of the film layers of the base substrate and the display structure layer are omitted in FIG18 to FIG21.
  • FIG18 to FIG21 are illustrated by taking the emission light of the first sub-pixel P1 and the second sub-pixel P2 as an example.
  • the emission light L1 of the first sub-pixel P1 can be represented by a dotted line with an arrow
  • the emission light L2 of the second sub-pixel P2 can be represented by a dotted line with an arrow
  • the light L3 absorbed by the film layer in the display panel can be represented by a solid line with an arrow.
  • the display panel in a direction perpendicular to the display panel, may include: a substrate, and a display structure layer, an encapsulation structure layer 104, a third barrier layer 105a, a first protective layer 106, and a color filter layer 108a disposed on the substrate substrate.
  • the orthographic projection of the third barrier layer 105a of this example on the substrate substrate may not overlap with the orthographic projection of the light-emitting region of the light-emitting element on the substrate substrate, and the orthographic projection of the third barrier layer 105a on the substrate substrate may surround the light-emitting element.
  • the orthographic projection of the third barrier layer 105a on the substrate substrate may be located within the orthographic projection range of the pixel definition layer 304 on the substrate substrate.
  • this embodiment is not limited to this.
  • the orthographic projection of the third barrier layer on the substrate substrate may surround the orthographic projection of the light-emitting region of the first light-emitting unit of the light-emitting element on the substrate substrate.
  • the color filter layer 108a may include: a plurality of periodically arranged filter units (e.g., a first filter unit 801, a second filter unit 802, and a third filter unit 803), and a black matrix 800 disposed between adjacent filter units.
  • the first filter unit 801 may correspond to the light-emitting element of the first sub-pixel P1
  • the second filter unit 802 may correspond to the light-emitting element of the second sub-pixel P2
  • the third filter unit 803 may correspond to the light-emitting element of the third sub-pixel P3.
  • the orthographic projection of the filter unit on the substrate may cover the orthographic projection of the light-emitting area of the light-emitting element of the corresponding sub-pixel on the substrate.
  • the orthographic projection of the black matrix 800 of the color filter layer 108a on the substrate may be located within the orthographic projection range of the third barrier layer 105a on the substrate.
  • this embodiment is not limited to this.
  • the edge of the light-emitting region of the second light-emitting unit P1-2 of the first sub-pixel P1 close to the second sub-pixel P2 may be aligned with the edge of the black matrix 800 close to the first filter unit 801.
  • the orthographic projection of the edge of the first filter unit 801 away from the second filter unit 802 on the base substrate may overlap with the orthographic projection of the third shielding layer 105a on the base substrate.
  • the first light-emitting unit P1-1 of the first subpixel P1 can be configured to emit light
  • the second light-emitting unit P1-2 can be configured not to emit light
  • the outgoing light of the first light-emitting unit P1-1 can be emitted in the direction of the normal viewing angle, and the outgoing light of the first light-emitting unit P1-1 in the direction of the right oblique viewing angle will be absorbed by the black matrix 800 and the second filter unit 802 of the color filter layer 108a, and a part of the outgoing light of the first light-emitting unit P1-1 in the direction of the left oblique viewing angle can be emitted through the first filter unit 801, and the other part will be absorbed by the black matrix 800 and the third barrier layer 105a.
  • the outgoing angle of the outgoing light of the first light-emitting unit P1-1 in this example is limited by the black matrix 800 and the third barrier layer 105a of the color filter layer 108a.
  • the first light emitting unit P1-1 and the second light emitting unit P1-2 of the first sub-pixel P1 may both be configured to emit light.
  • the outgoing light of the first light emitting unit P1-1 and the second light emitting unit P1-2 may be emitted in the normal viewing direction.
  • the second light emitting unit P1-2 is located between the first light emitting unit P1-1 and the first light emitting unit P2-1 in the first direction X.
  • the outgoing light of the first light emitting unit P1-1 in the right oblique viewing direction will be absorbed by the black matrix 800 and the second filter unit 802 of the color filter layer 108a and the third barrier layer 105a, and a part of the outgoing light of the first light emitting unit P1-1 in the left oblique viewing direction may be emitted through the first filter unit 801, and the other part may be absorbed by the black matrix 800 and the third barrier layer 105a.
  • the shared display mode by lighting up the first light emitting unit P1-1 and the second light emitting unit P1-2 at the same time, the outgoing angle of the outgoing light of the light emitting element can be increased, thereby improving the shared display effect.
  • the outgoing light of the first light emitting unit P1-1 and the second light emitting unit P1-2 can be emitted in the normal viewing direction.
  • the first light emitting unit P1-1 is located between the second light emitting unit P1-2 and the second light emitting unit P2-2 in the first direction X.
  • the outgoing light of the first light emitting unit P1-1 and the second light emitting unit P1-2 in the left oblique viewing direction will be absorbed by the black matrix 800 and the second filter unit 802 of the color filter layer 108a and the third blocking layer 105a, and a part of the outgoing light of the first light emitting unit P1-1 and the second light emitting unit P1-2 in the right oblique viewing direction can be emitted through the first filter unit 801, and the other part will be absorbed by the black matrix 800 and the third blocking layer 105a.
  • the emission angle of the sub-pixel in the shared display mode is increased.
  • the sub-pixel can emit light alternately from the left and from the right in the first direction in the shared display mode, thereby improving the shared display effect and user experience.
  • the pixel definition layer 304 may include: a first pixel definition portion 3041 located between a first light-emitting unit and a second light-emitting unit (e.g., a first light-emitting unit P1-1 and a second light-emitting unit P1-2) of the same light-emitting element, and a second pixel definition portion 3042 located between adjacent light-emitting elements.
  • a length C2 of the first pixel definition portion 3041 along the first direction X may be less than a length C1 of the second pixel definition portion 3042 along the first direction X.
  • the spacing between adjacent light-emitting elements may be greater than the spacing between the first light-emitting unit and the second light-emitting unit of the same light-emitting element.
  • At least a portion of the edge of the black matrix 800 of the color filter layer 108a may be flush with a portion of the edge of the third barrier layer 105a.
  • the orthographic projection of the black matrix 800 on the substrate may be located within the orthographic projection range of the third barrier layer 105a on the substrate.
  • the orthographic projection of the filter unit of the color filter layer 108a on the substrate may cover the orthographic projection of the light-emitting area of the first light-emitting unit and the second light-emitting unit of the corresponding light-emitting element on the substrate.
  • the length of the first filter unit 801a along the first direction X may be greater than the sum of the length B1 of the light-emitting area of the first light-emitting unit P1-1 of the first sub-pixel P1 along the first direction X, the length B2 of the light-emitting area of the second light-emitting unit P1-2 along the first direction X, and the length C2 of the first pixel definition portion 3041 along the first direction X.
  • the length of the first filter unit 801a along the first direction may be equal to the sum of the length B1 of the light emitting area of the first light emitting unit P1-1 of the first sub-pixel P1 along the first direction X, the length B2 of the light emitting area of the second light emitting unit P1-2 along the first direction X, the length C2 of the first pixel defining portion 3041 along the first direction X, and the first length B3.
  • the first length B3 may be greater than or equal to the length B2 of the light emitting area of the second light emitting unit P1-2 along the first direction X.
  • the length of the first filter unit 801a along the first direction may be equal to B1+C2+B2+B2.
  • the size of the first light-emitting unit and the second light-emitting unit of the second sub-pixel and the size of the first light-emitting unit and the second light-emitting unit of the third sub-pixel may be substantially the same as the size of the first light-emitting unit and the second light-emitting unit of the first sub-pixel.
  • the size setting of the first filter unit in this example is conducive to improving the sharing display effect in the sharing display mode.
  • the description of the size of the second filter unit and the third filter unit is similar to that of the first filter unit, so it is not repeated here.
  • the thickness H2 of the first protective layer 106 may be greater than or equal to the difference between the sum of the length B1 of the light-emitting region of the first light-emitting unit P1-1 along the first direction X, the length B2 of the light-emitting region of the second light-emitting unit P1-2 along the first direction X, and the length C2 of the first pixel definition portion 3041 along the first direction X and the thickness of the encapsulation structure layer 104.
  • H2 may be greater than or equal to B1+B2+C2-E.
  • the thickness setting of the first protective layer in this example is conducive to increasing the emission angle of the first light-emitting unit and the second light-emitting unit in the shared display mode, thereby improving the shared display effect in the shared display mode.
  • FIG22 is another schematic diagram of a pixel circuit of at least one embodiment of the present disclosure.
  • the pixel circuit may include at least: a driving subcircuit 11, a data writing subcircuit 12, a storage subcircuit 13, and a control subcircuit 14.
  • the data writing subcircuit 12 may be electrically connected to the first scan line GL1, the data line DL, and the driving subcircuit 11, and configured to provide the driving subcircuit 11 with a data signal transmitted by the data line DL under the control of the first scan line GL1.
  • the driving subcircuit 11 may be electrically connected to the storage subcircuit 13, the data writing subcircuit 12, the control subcircuit 14, and the first light-emitting unit EL1, and configured to drive the first light-emitting unit EL1 to emit light.
  • the storage subcircuit 13 may be electrically connected to the driving subcircuit 11 and the first power line VDD.
  • the control subcircuit 14 may be electrically connected to the second scan line GL2, the first power line VDD, the driving subcircuit 11, the first light-emitting unit EL1, and the second light-emitting unit EL2, and configured to drive the second light-emitting unit EL2 to emit light together with the first light-emitting unit EL1, or drive the second light-emitting unit EL2 to emit light under the control of the second scan line GL2.
  • FIG23 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure.
  • the pixel circuit may be a 4T1C structure.
  • the driving subcircuit 11 may include a driving transistor T3
  • the data writing subcircuit 12 may include a data writing transistor T4
  • the storage subcircuit 13 may include a storage capacitor Cst
  • the control subcircuit 14 may include a first control transistor T8 and a second control transistor T9.
  • the gate of the data write transistor T4 is electrically connected to the first scan line GL1, the first electrode of the data write transistor T4 is electrically connected to the data line DL, and the second electrode of the data write transistor T4 is electrically connected to the first electrode plate of the storage capacitor Cst1.
  • the second electrode plate of the storage capacitor Cst is electrically connected to the first power line VDD.
  • the gate of the driving transistor T3 is electrically connected to the first electrode plate of the storage capacitor Cst, the first electrode of the driving transistor T3 is electrically connected to the first power line VDD, and the second electrode of the driving transistor T3 is electrically connected to the first anode of the first light-emitting unit EL1.
  • the gate of the first control transistor T8 is electrically connected to the second scan line GL2, the first electrode of the first control transistor T8 is electrically connected to the first anode of the first light-emitting unit EL1, and the second electrode of the first control transistor T8 is electrically connected to the second anode of the second light-emitting unit EL2.
  • the gate of the second control transistor T9 is electrically connected to the second scan line GL2, the first electrode of the second control transistor T9 is electrically connected to the first anode of the first light-emitting unit EL1, and the second electrode of the second control transistor T9 is electrically connected to the second anode of the second light-emitting unit EL2.
  • the transistor types of the first control transistor T8 and the second control transistor T9 may be different.
  • the first control transistor T8 may be a P-type transistor, and the second control transistor T9 may be an N-type transistor; or the first control transistor T8 may be an N-type transistor, and the second control transistor T9 may be a P-type transistor. This embodiment is not limited to this.
  • the second scanning signal provided by the second scanning line GL2 can be continuously a high-level signal, so that the first control transistor T8 is disconnected, and the driving transistor T3 can only drive the first light-emitting unit EL1 to emit light under the control of the data signal;
  • the second scanning signal is a high-level signal, so that the second control transistor T9 is turned on, and the second light-emitting unit EL2 is driven to emit light.
  • the second scan signal provided by the second scan line GL2 may be a low-level signal
  • the first control transistor T8 is turned on
  • the second control transistor T9 is turned off, so that the driving transistor T3 can drive the first light-emitting unit EL1 and the second light-emitting unit EL2 to emit light at the same time under the control of the data signal, that is, the second light-emitting unit EL2 can emit light together with the first light-emitting unit EL1.
  • the process of the pixel circuit of this embodiment driving the first light-emitting unit EL1 to emit light can refer to the description of the pixel circuit of the previous embodiment, so it is not repeated here.
  • This embodiment does not limit the structure of the control subcircuit.
  • the second control transistor and the first control transistor may be of the same type, the gate of the second control transistor may be electrically connected to the third scan line, and the third scan signal provided by the third scan line and the second scan signal provided by the second scan line may have opposite phases.
  • this embodiment does not limit this.
  • the arrangement of sub-pixels in the display area may be as shown in FIG3.
  • the light-emitting element of at least one sub-pixel may be divided into two light-emitting units (e.g., a first light-emitting unit and a second light-emitting unit).
  • FIG24 is a partial cross-sectional schematic diagram of a light-emitting element of at least one embodiment of the present disclosure.
  • FIG24 is a partial cross-sectional schematic diagram along the Q-Q' direction in FIG3.
  • FIG24 illustrates a partial cross-sectional structure of a first light-emitting unit and a second light-emitting unit of a first sub-pixel.
  • the display panel in a direction perpendicular to the display panel, may include: a base substrate 101, a display structure layer, an encapsulation structure layer 104, and a light blocking layer 120 sequentially arranged on the base substrate 101.
  • the display structure layer may include: a circuit structure layer 102 and a light emitting structure layer 103 sequentially arranged on the base substrate 101.
  • the light blocking layer 120 may be arranged on a side of the encapsulation structure layer 104 away from the base substrate 101.
  • a color filter layer may also be arranged on a side of the light blocking layer 120 away from the base substrate.
  • this embodiment is not limited to this.
  • the light-blocking layer 120 may include a plurality of light-blocking portions 121.
  • the orthographic projection of the light-blocking portion 121 on the base substrate 101 may cover the orthographic projection of the light-emitting area of the second light-emitting unit on the base substrate 101.
  • the first light-emitting unit of the light-emitting element may serve as a main light-emitting unit
  • the second light-emitting unit may serve as an auxiliary light-emitting unit.
  • the outgoing light of the second light-emitting unit along the front viewing direction will be absorbed by the light-blocking portion 121, and the outgoing light along the side viewing direction may be emitted.
  • the outgoing light L1 of the first sub-pixel P1 may be represented by a dotted line with an arrow, and the light L3 absorbed by the film layer in the display panel may be represented by a solid line with an arrow.
  • the material and preparation process of the light-blocking layer 120 are similar to those of the aforementioned first shielding layer, so they will not be described in detail here.
  • the first light-emitting unit of the light-emitting element can emit light in the full viewing direction
  • the second light-emitting unit of the light-emitting element is blocked by the light-blocking layer and can only emit light in the side viewing direction.
  • Users in the front viewing direction cannot see the display screen of the second light-emitting unit.
  • the second light-emitting units of multiple sub-pixels of the display panel can be lit in the anti-peeping display mode, users in the side viewing direction can see a white screen. In this way, only users in the front viewing direction can see the normal display screen, and users in the side viewing direction can see a white screen, thereby achieving an anti-peeping effect.
  • FIG25A is a schematic diagram of a monochrome screen of a display panel in an anti-peeping display mode according to at least one embodiment of the present disclosure.
  • FIG25B is a schematic diagram of a monochrome screen of a display panel in a sharing display mode according to at least one embodiment of the present disclosure.
  • the monochrome screen shown in FIG25A and FIG25B is a red screen.
  • FIG25A and FIG25B are illustrated by taking a pixel unit as an example.
  • the first light-emitting unit P1-1 and the second light-emitting unit P1-1 of the first sub-pixel P1 can be lit, for example, the first light-emitting unit P1-1 emits light under the drive of the driving transistor of the pixel circuit, and the second light-emitting unit P1-2 can emit light under the drive of the second control transistor.
  • the first light-emitting unit P2-1 of the second sub-pixel P2 and the first light-emitting unit P3-1 of the third sub-pixel P3 are configured not to emit light; the second light-emitting unit P2-2 of the second sub-pixel P2 and the second light-emitting unit P3-2 of the third sub-pixel P3 can be configured to emit light.
  • the anti-peeping display mode users in the front viewing direction can see the red screen, and users in the side viewing direction can see the white screen.
  • the first light emitting unit P1-1 of the first sub-pixel P1 is configured to emit light
  • the second light emitting unit P1-2 can be configured to emit light together with the first light emitting unit P1-1.
  • the first light emitting unit P1-1 and the second light emitting unit P1-2 can emit light under the drive of the driving transistor.
  • the first light emitting unit P2-1 and the second light emitting unit P2-2 of the second sub-pixel P2, and the first light emitting unit P3-1 and the second light emitting unit P3-2 of the third sub-pixel P3 do not emit light.
  • the display methods of the blue screen and the green screen are similar, so they are not repeated here.
  • FIG26A is a schematic diagram of a black screen of a display panel in an anti-peeping display mode according to at least one embodiment of the present disclosure.
  • FIG26B is a schematic diagram of a black screen of a display panel in a sharing display mode according to at least one embodiment of the present disclosure.
  • FIG26A and FIG26B are illustrated by taking a pixel unit as an example. As shown in FIG26A , in the anti-peeping display mode, the first light-emitting unit P1-1 of the first sub-pixel P1, the first light-emitting unit P2-1 of the second sub-pixel P2, and the first light-emitting unit P3-1 of the third sub-pixel P3 are all configured not to emit light.
  • the second light-emitting unit P1-2 of the first sub-pixel P1, the second light-emitting unit P2-2 of the second sub-pixel P2, and the second light-emitting unit P3-2 of the third sub-pixel P3 can all be configured to emit light. In this way, in the anti-peeping display mode, users in the front viewing direction can see a black screen, and users in the side viewing direction can see a white screen. As shown in FIG.
  • the first light-emitting unit P1-1 and the second light-emitting unit P1-2 of the first sub-pixel P1, the first light-emitting unit P2-1 and the second light-emitting unit P2-2 of the second sub-pixel P2, and the first light-emitting unit P3-1 and the second light-emitting unit P3-2 of the third sub-pixel P3 can all be configured not to emit light.
  • FIG27 is a schematic diagram of a white screen of a display panel in an anti-peeping display mode according to at least one embodiment of the present disclosure.
  • FIG27 is illustrated by taking a pixel unit as an example.
  • the first light-emitting unit P1-1 and the second light-emitting unit P1-2 of the first sub-pixel P1, the first light-emitting unit P2-1 and the second light-emitting unit P2-2 of the second sub-pixel P2, and the first light-emitting unit P3-1 and the second light-emitting unit P3-2 of the third sub-pixel P3 can all be configured to emit light.
  • the first light-emitting unit P1-1 and the second light-emitting unit P1-2 of the first sub-pixel P1, the first light-emitting unit P2-1 and the second light-emitting unit P2-2 of the second sub-pixel P2, and the first light-emitting unit P3-1 and the second light-emitting unit P3-2 of the third sub-pixel P3 can all be configured to emit light.
  • the display panel of this example controls the light-emitting state of the second light-emitting unit by setting a first control transistor and a second control transistor, and blocks the light-emitting area of the second light-emitting unit by a light-blocking layer, so that in the anti-peeping display mode, the second light-emitting unit can maintain the light-emitting state. In this way, users in the side viewing direction can only see a white picture, thereby achieving an anti-peeping effect.
  • This embodiment also provides a method for preparing a display panel, comprising: forming a display structure layer on a base substrate, the display structure layer comprising a plurality of sub-pixels. At least one of the plurality of sub-pixels comprises: a pixel circuit and a light-emitting element electrically connected to the pixel circuit.
  • the light-emitting element comprises: a first light-emitting unit and a second light-emitting unit; the light-emitting region of the first light-emitting unit is isolated from the light-emitting region of the second light-emitting unit.
  • the pixel circuit is configured to drive at least one of the first light-emitting unit and the second light-emitting unit to emit light in an anti-peeping display mode.
  • the method for manufacturing the display panel of this embodiment can refer to the description of the aforementioned embodiment, so it will not be described in detail here.
  • FIG28 is a schematic diagram of a display device of at least one embodiment of the present disclosure.
  • the present embodiment provides a display device 91, including a display panel 910 of the aforementioned embodiment.
  • the display panel 910 may be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate.
  • the display device 91 may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.
  • the present embodiment is not limited to this.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Optics & Photonics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示面板，包括：衬底基板(101)、以及设置在衬底基板(101)上的显示结构层，显示结构层包括多个子像素(P1、P2、P3)。至少一个子像素(P1、P2、P3)包括：像素电路以及与像素电路电连接的发光元件。发光元件包括：第一发光单元(P1-1、P2-1、P3-1)和第二发光单元(P1-2、P2-2、P3-2)。第一发光单元(P1-1、P2-1、P3-1)的发光区域与第二发光单元(P1-2、P2-2、P3-2)的发光区域相互隔离。像素电路配置为在防窥显示模式下驱动第一发光单元(P1-1、P2-1、P3-1)和第二发光单元(P1-2、P2-2、P3-2)中的至少之一发光。

Description

显示面板及其制备方法、显示装置 技术领域
本公开涉及但不限于显示技术领域，尤指一种显示面板及其制备方法、显示装置。
背景技术
随着显示技术的不断发展，人们对显示方式的需求越来越多样化。在一些显示应用的使用中，用户喜欢将资讯与旁人分享。在另一些应用的使用场景下，用户需要进行隐私保护，需要显示产品具有防窥功能，例如，用户在手机进行个人资料输入的场景、用户在处理公司机密资料的场景等。因此，显示分享与隐私切换逐渐成为显示产品的功能趋势。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示面板及其制备方法、显示装置。
一方面，本公开实施例提供一种显示面板，包括：衬底基板、以及设置在所述衬底基板上的显示结构层。所述显示结构层包括多个子像素。所述多个子像素中的至少一个子像素包括：像素电路以及与所述像素电路电连接的发光元件。所述发光元件包括：第一发光单元和第二发光单元；所述第一发光单元的发光区域与所述第二发光单元的发光区域相互隔离。所述像素电路配置为在防窥显示模式下驱动所述第一发光单元和所述第二发光单元中的至少之一发光。
在一些示例性实施方式中，所述像素电路配置为在所述防窥显示模式下仅驱动所述第一发光单元发光，在分享显示模式下驱动所述第二发光单元随同所述第一发光单元发光。
在一些示例性实施方式中，所述发光元件的第一发光单元的发光区域的 面积大于或等于第二发光单元的发光区域的面积。
在一些示例性实施方式中，显示面板还包括：位于所述显示结构层的出光侧的至少一个遮挡层，所述遮挡层在所述衬底基板的正投影与所述发光元件的第一发光单元和第二发光单元的发光区域在所述衬底基板的正投影没有交叠；所述遮挡层在所述衬底基板的正投影围绕在所述发光元件的第一发光单元在所述衬底基板的正投影的周围，或者，所述遮挡层在所述衬底基板的正投影围绕在所述发光元件在所述衬底基板的正投影的周围。
在一些示例性实施方式中，显示面板还包括：位于所述至少一个遮挡层远离所述衬底基板一侧的彩色滤光层，所述彩色滤光层包括：周期性排布的多个滤光单元以及位于相邻滤光单元之间的黑矩阵，所述多个滤光单元与所述多个子像素的发光元件一一对应。
在一些示例性实施方式中，所述多个滤光单元中的至少一个滤光单元在所述衬底基板的正投影覆盖对应子像素的发光元件在所述衬底基板的正投影。
在一些示例性实施方式中，显示面板还包括：位于所述至少一个遮挡层远离所述衬底基板一侧的光调节层，所述光调节层包括：至少一个透镜单元，所述至少一个透镜单元在所述衬底基板的正投影与所述发光元件的第一发光单元的发光区域在所述衬底基板的正投影至少部分交叠。
在一些示例性实施方式中，显示面板还包括：位于所述至少一个遮挡层远离所述衬底基板一侧的第一保护层和第二保护层；所述第二保护层位于所述第一保护层靠近所述衬底基板的一侧，所述第二保护层的折射率小于所述第一保护层的折射率，所述第二保护层在所述衬底基板的正投影与所述发光元件的发光区域没有交叠，所述第一保护层在所述衬底基板的正投影覆盖所述第二保护层在所述衬底基板的正投影。
在一些示例性实施方式中，所述显示结构层包括阳极层，所述阳极层包括所述发光元件的第一发光单元的第一阳极和第二发光单元的第二阳极，所述第一阳极和第二阳极均与所述像素电路电连接，所述第一阳极和所述第二阳极相互隔离；所述第一阳极和所述第二阳极所在平面齐平，或者，所述第二阳极位于所述第一阳极远离所述衬底基板的一侧。
在一些示例性实施方式中，所述显示结构层包括：阳极层以及位于所述 阳极层远离所述衬底基板一侧的像素定义层，所述像素定义层设置有暴露出所述阳极层的至少部分表面的多个像素开口，所述像素定义层为黑色。
在一些示例性实施方式中，所述至少一个子像素的发光元件的第一发光单元和第二发光单元之间的间距，小于相邻的出射不同颜色光的子像素的发光元件之间的间距。
在一些示例性实施方式中，所述多个子像素的发光元件阵列排布，出射相同颜色光的子像素的发光元件的第一发光单元和第二发光单元沿第一方向交替排布，且沿第二方向交替排布，所述第一方向和所述第二方向交叉。
在一些示例性实施方式中，所述像素电路至少包括：数据写入子电路、存储子电路、驱动子电路和控制子电路。所述数据写入子电路与数据线、第一扫描线和所述驱动子电路电连接，配置为在所述第一扫描线的控制下，向所述驱动子电路提供所述数据线传输的数据信号。所述驱动子电路与所述数据写入子电路、所述存储子电路、所述控制子电路和所述发光元件的第一发光单元电连接，配置为在数据信号的控制下，驱动所述第一发光单元发光。所述控制子电路与第二扫描线、所述驱动子电路、所述发光元件的第一发光单元和第二发光单元电连接，配置为在所述第二扫描线的控制下，控制所述第二发光单元随同所述第一发光单元发光。
在一些示例性实施方式中，所述控制子电路包括：第一控制晶体管；所述第一控制晶体管的栅极与所述第二扫描线电连接，第一极与所述第一发光单元电连接，第二极与所述第二发光单元电连接。
在一些示例性实施方式中，所述至少一个子像素的像素电路配置为在防窥显示模式下仅驱动所述第二发光单元发光，或者分别驱动所述第一发光单元和所述第二发光单元发光；在分享显示模式下驱动所述第二发光单元随同所述第一发光单元发光。
在一些示例性实施方式中，显示面板还包括：位于所述显示结构层的出光侧的阻光层，所述阻光层包括至少一个阻光部，所述阻光部在所述衬底基板的正投影覆盖所述第二发光单元的发光区域在所述衬底基板的正投影。
在一些示例性实施方式中，所述多个子像素包括出射第一颜色光的第一子像素、出射第二颜色光的第二子像素以及出射第三颜色光的第三子像素； 在所述防窥显示模式下，所述第一子像素、所述第二子像素和所述第三子像素的发光元件的第二发光单元均被配置为发光。
在一些示例性实施方式中，所述像素电路至少包括：数据写入子电路、存储子电路、驱动子电路和控制子电路。所述数据写入子电路与数据线、第一扫描线和所述驱动子电路电连接，配置为在所述第一扫描线的控制下，向所述驱动子电路提供所述数据线传输的数据信号。所述驱动子电路与所述数据写入子电路、所述存储子电路、所述控制子电路和所述发光元件的第一发光单元电连接，配置为在数据信号的控制下，驱动所述第一发光单元发光。所述控制子电路与第二扫描线、第一电源线、所述驱动子电路、所述发光元件的第一发光单元和第二发光单元电连接，配置为在所述第二扫描线的控制下，控制所述第二发光单元随同所述第一发光单元发光，或者，驱动所述第二发光单元发光。
在一些示例性实施方式中，所述控制子电路包括：第一控制晶体管和第二控制晶体管；所述第一控制晶体管的栅极与所述第二扫描线电连接，第一极与所述第一发光单元电连接，第二极与所述第二发光单元电连接；所述第二控制晶体管的栅极与所述第二扫描线电连接，第一极与所述第一电源线电连接，第二极与所述第二发光单元电连接；所述第二控制晶体管和所述第一控制晶体管的晶体管类型不同。
另一方面，本公开实施例提供一种显示装置，包括如上所述的显示面板。
另一方面，本公开实施例提供一种显示面板的制备方法，用于制备如上所述的显示面板。所述制备方法包括：在衬底基板形成显示结构层，所述显示结构层包括多个子像素。所述多个子像素中的至少一个子像素包括：像素电路以及与所述像素电路电连接的发光元件，所述发光元件包括：第一发光单元和第二发光单元；所述第一发光单元的发光区域与所述第二发光单元的发光区域相互隔离。所述像素电路配置为在防窥显示模式下驱动所述第一发光单元和所述第二发光单元中的至少之一发光。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开至少一实施例的显示面板的结构示意图；
图2为本公开至少一实施例的显示面板的平面结构示意图；
图3为本公开至少一实施例的显示面板的子像素的平面示意图；
图4为本公开至少一实施例的像素电路的示意图；
图5为本公开至少一实施例的像素电路的一种等效电路图；
图6为本公开至少一实施例的像素电路的另一等效电路图；
图7为图3中沿Q-Q’方向的局部剖面示例图；
图8为本公开至少一实施例的第一遮挡层的平面示意图；
图9为图3中沿Q-Q’方向的另一局部剖面示例图；
图10为图3中沿R-R’方向的剖面结构的光线出射示意图；
图11为图3中沿U-U’方向的剖面结构的光线出射示意图；
图12为图3中沿Q-Q’方向的另一局部剖面示例图；
图13为图3中沿Q-Q’方向的另一局部剖面示例图；
图14为图3中沿Q-Q’方向的另一局部剖面示例图；
图15为图3中沿Q-Q’方向的另一局部剖面示例图；
图16为图3中沿Q-Q’方向的另一局部剖面示例图；
图17为本公开至少一实施例的显示面板的子像素的另一平面示意图；
图18为图17中沿V-V’方向的剖面结构在防窥显示模式下的光线出射示意图；
图19为图17中沿V-V’方向的剖面结构在分享显示模式下的光线出射示意图；
图20为图17中沿O-O’方向的剖面结构在分享显示模式下的光线出射示 意图；
图21为图17中沿V-V’方向的剖面结构的示意图；
图22为本公开至少一实施例的像素电路的另一示意图；
图23为本公开至少一实施例的像素电路的等效电路图；
图24为本公开至少一实施例的发光元件的局部剖面示意图；
图25A为本公开至少一实施例的显示面板在防窥显示模式下的单色画面的示意图；
图25B为本公开至少一实施例的显示面板在分享显示模式下的单色画面的示意图；
图26A为本公开至少一实施例的显示面板在防窥显示模式下的黑色画面的示意图；
图26B为本公开至少一实施例的显示面板在分享显示模式下的黑色画面的示意图；
图27为本公开至少一实施例的显示面板在防窥显示模式下的白色画面的示意图；
图28为本公开至少一实施例的显示装置的示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为一种或多种形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例 子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”可以包括两个以及两个以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有一种或多种功能的元件等。
在本说明书中，晶体管是指至少包括栅电极(栅极)、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏极)与源电极(源电极端子、源区域或源极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本公开中，沟道区域是指电流主要流过的区域。
在本说明书中，为区分晶体管除栅电极之外的两极，将其中一个电极称为第一极，另一电极称为第二极，第一极可以为源极或者漏极，第二极可以为漏极或源极。另外，将晶体管的栅极可以称为控制极。在使用极性相反的 晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，可以包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，可以包括85°以上且95°以下的角度的状态。
在本说明书中，三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。在本说明书中，“大致相同”可以是指数值相差10％以内的情况。
为了实现显示产品的防窥功能，目前存在多种解决方案。例如，采用外挂式的防窥膜，通过将防窥膜手动挂在显示屏前实现防窥功能，不需要时可以手动取下防窥膜；又如，在显示屏前增加液晶层，借由液晶分子转向来限制出光角度实现防窥功能。然而，上述这些解决方案容易导致显示面板的结构复杂且增加显示面板的厚度，不利于提高用户体验。
本实施例提供一种显示面板，包括：衬底基板、以及设置在衬底基板上的显示结构层。显示结构层包括多个子像素。至少一个子像素包括：像素电路以及与像素电路电连接的发光元件。发光元件包括：第一发光单元和第二发光单元。第一发光单元的发光区域和第二发光单元的发光区域相互隔离。像素电路配置为在防窥显示模式下驱动第一发光单元和第二发光单元中的至少之一发光。
本实施例提供的显示面板，通过将子像素的发光元件划分为两个发光单元(即第一发光单元和第二发光单元)，并通过像素电路对第一发光单元和第二发光单元进行发光控制实现防窥效果。本实施例提供的显示面板通过对 显示面板的内部结构进行改进，可以在不增加显示面板的厚度条件下实现防窥显示效果，从而提高用户体验。
在一些示例性实施方式中，显示面板可以是有机发光二极管(OLED，Organic Light Emitting Diode)显示面板，或者可以是量子点发光二极管(QLED，Quantum Dot Light Emitting Diodes)显示面板，或者可以是等离子体显示装置(PDP)显示面板，或者可以是电泳显示(EPD)显示面板。本实施例对此并不限定。
在一些示例性实施方式中，显示面板可以包括防窥显示模式和分享显示模式。防窥显示模式可以满足用户需要进行隐私保护的显示需求，分享显示模式可以满足用户进行资讯共享场景下的显示需求。在一些示例中，显示面板可以设置切换按键，用户通过切换按键来切换显示面板的显示模式。然而，本实施例对此并不限定。在另一些示例中，可以采用声控、感应等触发方式来启动显示面板的显示模式切换。
在一些示例性实施方式中，像素电路可以配置为在防窥显示模式下仅驱动第一发光单元发光，在分享显示模式下驱动第二发光单元随同第一发光单元发光。在另一些示例中，像素电路可以配置为在防窥显示模式下仅驱动第二发光单元发光，或者驱动第一发光单元和第二发光单元分别发光，在分享显示模式下驱动第二发光单元随同第一发光单元发光。然而，本实施例对此并不限定。本示例通过对显示面板的内部结构进行改进，可以在不增加显示面板的厚度条件下实现防窥显示效果和分享显示效果，从而提高用户体验。
在一些示例性实施方式中，显示面板可以包括：位于显示结构层的出光侧的至少一个遮挡层，遮挡层在衬底基板的正投影与发光元件的第一发光单元和第二发光单元的发光区域在衬底基板的正投影可以没有交叠。遮挡层在衬底基板的正投影可以围绕在发光元件的第一发光单元在衬底基板的正投影的周围，或者，遮挡层在衬底基板的正投影可以围绕在发光元件在衬底基板的正投影的周围。在一些示例中，遮挡层的数目可以为两个，相邻遮挡层之间可以设置保护层。本示例通过设置至少一个遮挡层围绕在发光元件或发光元件的第一发光单元的周围，可以限制发光元件的第一发光单元的光线出射角度，从而有利于实现防窥显示效果。
在一些示例性实施方式中，显示面板还可以包括：位于至少一个遮挡层远离衬底基板一侧的彩色滤光层。彩色滤光层可以包括：周期性排布的多个滤光单元以及位于相邻滤光单元之间的黑矩阵，多个滤光单元与多个子像素的发光元件一一对应。本示例通过设置彩色滤光层，利用黑矩阵和滤光单元可以限制发光元件的光线出射角度，从而有利于实现防窥显示效果。
下面通过一些示例对本实施例的方案进行举例说明。
图1为本公开至少一实施例的显示面板的结构示意图。在一些示例中，如图1所示，显示面板可以包括：时序控制器20、数据驱动器40、栅极驱动电路以及子像素阵列10。栅极驱动电路可以包括至少一个驱动器，例如包括扫描驱动器30。时序控制器20、数据驱动器40和栅极驱动电路可以位于显示面板的显示区域外围的周边区域。位于显示区域的子像素阵列10可以包括规则排布的多个子像素PX。扫描驱动器30可以配置为沿扫描线将扫描信号提供到子像素PX；数据驱动器40可以配置为沿数据线将数据信号提供到子像素PX；时序控制器20可以配置为控制扫描驱动器30和数据驱动器40。
在一些示例中，时序控制器20可以将适于数据驱动器40的规格的灰度值和控制信号提供到数据驱动器40；时序控制器20可以将适于扫描驱动器30的规格的时钟信号、初始信号等提供到扫描驱动器30。数据驱动器40可以利用从时序控制器20接收的灰度值和控制信号来产生将提供到数据线D1至Dn的数据电压。例如，数据驱动器40可以利用时钟信号对灰度值进行采样，并且以子像素行为单位将与灰度值对应的数据信号施加到数据线D1至Dn。扫描驱动器30可以通过从时序控制器20接收的时钟信号、初始信号等来产生将提供到扫描线G1至Gm的扫描信号。例如，扫描驱动器30可以将具有导通电平脉冲的扫描信号顺序地提供到扫描线。在一些示例中，扫描驱动器30可以包括移位寄存器，可以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描初始信号传输到下一级电路的方式产生扫描信号。其中，n和m均为自然数。
在一些示例中，栅极驱动电路可以直接设置在衬底基板上。例如，栅极驱动器可以设置在显示区域左右两侧的周边区域。在一些示例中，栅极驱动器可以在形成子像素的工艺中与子像素一起形成。然而，本实施例对于栅极 驱动器的位置或形成方式并不限定。在一些示例中，栅极驱动器可以设置在单独的芯片或印刷电路板上，以连接到衬底基板上形成的焊盘或焊垫。
在一些示例中，数据驱动器40可以设置在单独的芯片或印刷电路板上，以通过衬底基板设置的信号接入引脚连接到子像素PX。例如，数据驱动器40可以采用玻璃上芯片、塑料上芯片、膜上芯片等形成设置，以连接到衬底基板上的信号接入引脚。时序控制器20可以与数据驱动器40分开设置或者与数据驱动器40一体设置。然而，本实施例对此并不限定。
图2为本公开至少一实施例的显示面板的平面结构示意图。在一些示例中，如图2所示，显示面板的显示区域可以包括以矩阵方式排布的多个像素单元P，多个像素单元P的至少一个可以包括出射第一颜色光的第一子像素P1、出射第二颜色光的第二子像素P2和出射第三颜色光的第三子像素P3。例如，第一颜色光可以为红光，第二颜色光可以为绿光，第三颜色光可以为蓝光。换言之，第一子像素P1可以为红色(R)子像素，第二子像素P2可以为绿色(G)子像素，第三子像素P3可以为蓝色(B)子像素。在另一些示例中，像素单元P可以包括四个子像素，例如包括红色子像素、绿色子像素、蓝色子像素和白色子像素。然而，本公开在此不做限定。
在一些示例中，像素单元P中的子像素的形状可以是矩形状、菱形、五边形或六边形。如图2所示，像素单元P中的子像素的形状可以为矩形状。例如，像素单元P包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列；像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形方式排列。然而，本公开在此不做限定。
在一些示例中，至少一个子像素可以包括像素电路和发光元件。例如，第一子像素P1、第二子像素P2和第三子像素P3均可以包括像素电路和发光元件。在一些示例中，像素电路可以包括多个晶体管和至少一个电容，例如，像素电路可以为3T1C结构、7T1C结构、5T1C结构、8T1C结构或者8T2C结构等，其中，上述电路结构中的T指的是薄膜晶体管，C指的是电容，T前面的数字代表电路中薄膜晶体管的数量，C前面的数字代表电路中电容的数量。
在一些示例中，第一子像素P1、第二子像素P2和第三子像素P3中的发 光元件分别与所在子像素的像素电路连接，发光元件可以被配置为响应所在子像素的像素电路输出的驱动电流发出相应亮度的光。例如，发光元件可以是有机发光二极管(OLED)，可以包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。然而，本实施例对此并不限定。例如，发光元件可以为微发光二极管(Micro-LED，Micro Light Emitting Diode)、或迷你二极管(Mini-LED)、或量子点发光二极管(QLED)。
图3为本公开至少一实施例的显示面板的子像素的平面示意图。在一些示例中，如图3所示，显示面板的显示区域内的多个子像素可以阵列排布，例如沿第一方向X依次排布，且沿第二方向Y依次排布。其中，第一方向X与第二方向Y可以位于同一平面内且相互交叉，例如，第一方向X可以垂直于第二方向Y。本示例中，沿第一方向X排布的多个子像素可以称为一行子像素，沿第二方向Y排布的多个子像素可以称为一列子像素。在一行子像素内，第一子像素P1、第二子像素P2和第三子像素P3可以周期性排布；一列子像素内可以排布多个出射相同颜色光的子像素。例如，多个第一子像素P1可以排布为一列，多个第二子像素P2可以排布为另一列，多个第三子像素P3可以排布为另一列。
在一些示例中，如图3所示，至少一个子像素的发光元件可以沿第二方向Y被划分为两个发光单元。例如，第一子像素P1的发光元件可以包括：沿第二方向Y排布的第一发光单元P1-1和第二发光单元P1-2；第二子像素P2的发光元件可以包括：沿第二方向Y排布的第一发光单元P2-1和第二发光单元P2-2；第三子像素P3的发光元件可以包括：沿第二方向Y排布的第一发光单元P3-1和第二发光单元P3-2。在第一方向X上，第一发光单元P1-1、P2-1和P3-1可以依次排布为一行，第二发光单元P1-2、P2-2和P3-2可以依次排布为一行。在第二方向Y上，第一发光单元P1-1和第二发光单元P1-2可以间隔排布，第一发光单元P2-1和第二发光单元P2-2可以间隔排布，第一发光单元P3-1和第二发光单元P3-2可以间隔排布。
在一些示例中，至少一个发光元件的发光区域可以包括所述发光元件的第一发光单元的发光区域和第二发光单元的发光区域。至少一个发光元件的第一发光单元的发光区域和第二发光单元的发光区域可以相互隔离。至少一 个发光元件的第一发光单元的发光区域的面积与第二发光单元的发光区域的面积可以大致相同。至少一个发光元件的第一发光单元的形状与第二发光单元的形状可以大致相同。然而，本实施例对此并不限定。例如，至少一个发光元件的两个发光单元的形状可以不同；又如，至少一个发光元件的两个发光单元的发光区域的面积可以不同，比如，第一发光单元的发光区域的面积可以大于第二发光单元的发光区域的面积。
图4为本公开至少一实施例的像素电路的示意图。在一些示例中，如图4所示，像素电路可以至少包括：驱动子电路11、数据写入子电路12、存储子电路13和控制子电路14。数据写入子电路12可以与第一扫描线GL1、数据线DL和驱动子电路11电连接，配置为在第一扫描线GL1的控制下，向驱动子电路11提供数据线DL传输的数据信号。驱动子电路11可以与存储子电路13、数据写入子电路12、控制子电路14和第一发光单元EL1电连接，配置为驱动第一发光单元EL1发光。存储子电路13可以与驱动子电路11和第一电源线VDD电连接。控制子电路14可以与第二扫描线GL2、驱动子电路11、第一发光单元EL1和第二发光单元EL2电连接，配置为在第二扫描线GL2的控制下，控制第二发光单元EL2随同第一发光单元EL1发光。
在一些示例中，第一发光单元EL1可以包括叠设的第一阳极、第一有机发光层和第一阴极。第二发光单元EL2可以包括叠设的第二阳极、第二有机发光层和第二阴极。第一发光单元EL1的第一阳极可以与驱动子电路11和控制子电路14电连接，第一阴极可以与第二电源线VSS电连接。第二发光单元EL2的第二阳极可以与控制子电路14电连接，第二阴极可以与第二电源线VSS电连接。
在一些示例中，第一电源线VDD可以配置为持续提供高电位的第一电压信号，第二电源线VSS可以配置为持续提供低电位的第二电压信号。第一电压信号大于第二电压信号。
在一些示例中，显示面板的周边区域设置的栅极驱动电路可以包括：第一扫描驱动器和第二扫描驱动器。第一扫描驱动器可以配置为给第一扫描线提供第一扫描信号，第二扫描驱动器可以配置为给第二扫描线提供第二扫描信号。
在一些示例中，像素电路的多个晶体管可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点。在一些示例中，可以将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示面板上，形成低温多晶氧化物显示面板，可以利用两者的优势，可以实现高分辨率(PPI，Pixel Per Inch)，低频驱动，可以降低功耗，可以提高显示品质。然而，本实施例对此并不限定。
图5为本公开至少一实施例的像素电路的一种等效电路图。在一些示例中，如图5所示，像素电路可以为3T1C结构。其中，驱动子电路11可以包括驱动晶体管T3，数据写入子电路12可以包括数据写入晶体管T4，存储子电路13可以包括存储电容Cst，控制子电路14可以包括第一控制晶体管T8。
在一些示例中，如图5所示，数据写入晶体管T4的栅极与第一扫描线GL1电连接，数据写入晶体管T4的第一极与数据线DL电连接，数据写入晶体管T4的第二极与存储电容Cst1的第一极板电连接。存储电容Cst的第二极板与第一电源线VDD电连接。驱动晶体管T3的栅极与存储电容Cst的第一极板电连接，驱动晶体管T3的第一极与第一电源线VDD电连接，驱动晶体管T3的第二极与第一发光单元EL1的第一阳极电连接。第一控制晶体管T8的栅极与第二扫描线GL2电连接，第一控制晶体管T8的第一极与第一发光单元EL1的第一阳极电连接，第一控制晶体管T8的第二极与第二发光单元EL2的第二阳极电连接。
在一些示例中，如图5所示，以驱动晶体管T3、数据写入晶体管T4和第一控制晶体管T8均为P型晶体管为例，当第一扫描线GL1提供的第一扫描信号为低电平信号，数据写入晶体管T4导通，对存储电容Cst进行充电，将数据线DL传输的数据信号存储在存储电容Cst中，存储电容Cst存储的数据信号可以控制驱动晶体管T3的导通程度，以驱动第一发光单元EL1发光。在第二扫描线GL2提供的第二扫描信号为高电平信号时，第一控制晶体管T8断开，第二发光单元EL2不发光；在第二扫描线GL2提供的第二扫描信 号为低电平信号时，第一控制晶体管T8导通，第二发光单元EL2可以随同第一发光单元EL1发光。
在一些示例中，如图5所示，在防窥显示模式下，第二扫描线GL2提供的第二扫描信号可以持续为高电平信号，使得第一控制晶体管T8断开，驱动晶体管T3在数据信号的控制下可以仅驱动第一发光单元EL1发光。在分享显示模式下，第二扫描线GL2提供的第二扫描信号可以为低电平信号，第一控制晶体管T8导通，使得驱动晶体管T3在数据信号的控制下可以同时驱动第一发光单元EL1和第二发光单元EL2发光。
图6为本公开至少一实施例的像素电路的另一等效电路图。在一些示例中，如图6所示，像素电路可以为8T1C结构。其中，驱动子电路11可以包括驱动晶体管T3，数据写入子电路12可以包括数据写入晶体管T4，存储子电路13可以包括存储电容Cst，控制子电路14可以包括第一控制晶体管T8。像素电路还可以包括：第一复位晶体管T1、第二复位晶体管T7、阈值补偿晶体管T2、第一发光控制晶体管T5和第二发光控制晶体管T6。
在一些示例中，如图6所示，第一复位晶体管T1的栅极与第一复位控制线RST1电连接，第一复位晶体管T1的第一极与第一初始信号线INIT1电连接，第一复位晶体管T1的第二极与第一节点N1电连接。阈值补偿晶体管T2的栅极与第一扫描线GL1电连接，阈值补偿晶体管T2的第一极与第一节点N1电连接，阈值补偿晶体管T2的第二极与第三节点N3电连接。驱动晶体管T3的栅极与第一节点N1电连接，驱动晶体管T3的第一极与第二节点N2电连接，驱动晶体管T3的第二极与第三节点N3电连接。数据写入晶体管T4的栅极与第一扫描线GL1电连接，数据写入晶体管T4的第一极与数据线DL电连接，数据写入晶体管T4的第二极与第二节点N2电连接。第一发光控制晶体管T5的栅极与发光控制线EML电连接，第一发光控制晶体管T5的第一极与第一电源线VDD电连接，第一发光控制晶体管T5的第二极与第二节点N2电连接。第二发光控制晶体管T6的栅极与发光控制线EML电连接，第二发光控制晶体管T6的第一极与第三节点N3电连接，第二发光控制晶体管T6的第二极与第四节点N4电连接。第二复位晶体管T7的栅极与第二复位控制线RST2电连接，第二复位晶体管T7的第一极与第二 初始信号线INIT2电连接，第二复位晶体管T7的第二极与第四节点N4电连接。第一控制晶体管T8的栅极与第二扫描线GL2电连接，第一控制晶体管T8的第一极与第四节点N4电连接，第一控制晶体管T8的第二极与第二发光单元EL2的第二阳极电连接。存储电容Cst的第一极板与第一节点N1电连接，存储电容Cst的第二极与第一电源线VDD电连接。第一发光单元EL1的第一阳极与第四节点N4电连接，第一阴极与第二电源线VSS电连接。第二发光单元EL2的第一阳极与第一控制晶体管T8的第二极电连接，第二阴极与第二电源线VSS电连接。
在一些示例中，第一节点N1为第一复位晶体管T1、阈值补偿晶体管T2、驱动晶体管T3和存储电容Cst的连接点。第二节点N2为驱动晶体管T3、数据写入晶体管T4和第一发光控制晶体管T5的连接点。第三节点N3为驱动晶体管T3、阈值补偿晶体管T2和第二发光控制晶体管T6的连接点。第四节点N4为第二发光控制晶体管T6、第二复位晶体管T7、第一控制晶体管T8和第一发光单元EL1的第一阳极的连接点。
在一些示例中，以像素电路的八个晶体管均为P型晶体管为例进行说明。其中，第二复位控制线RST2可以与第一扫描线GL1相连，以被输入第一扫描信号。在防窥显示模式下，第二扫描线GL2可以持续提供高电平的第二扫描信号，使得第一控制晶体管T8断开，第二发光单元EL2处于不发光状态。在分享显示模式下，第二扫描线GL2可以持续提供低电平的第二扫描信号，使得第一控制晶体管T8导通，第二发光单元EL2可以随同第一发光单元EL1发光。
在一些示例中，以防窥显示模式下，第一控制晶体管T8断开为例，像素电路的工作过程可以包括：
第一阶段，称为复位阶段，第一复位控制线RST1提供的第一复位控制信号为低电平信号，使得第一复位晶体管T1导通，第一初始信号线INIT1提供的第一初始信号可以被提供至第一节点N1，对第一节点N1进行初始化，清除存储电容Cst中原有数据电压。第一扫描线GL1提供的第一扫描信号为高电平信号，发光控制线EML提供的发光控制信号为高电平信号，使数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控 制晶体管T6以及第二复位晶体管T7断开。此阶段第一发光单元EL1不发光。
第二阶段，称为数据写入阶段或者阈值补偿阶段。第一扫描线GL1提供的第一扫描信号为低电平信号，第一复位控制线RST1提供的第一复位控制信号和发光控制线EML提供的发光控制信号均为高电平信号，数据线DL输出数据信号。此阶段由于存储电容Cst的第一极板为低电平，因此，驱动晶体管T3导通。第一扫描信号为低电平信号，使阈值补偿晶体管T2、数据写入晶体管T4和第二复位晶体管T7导通。阈值补偿晶体管T2和数据写入晶体管T4导通，使得数据线DL输出的数据电压经过第二节点N2、导通的驱动晶体管T3、第三节点N3、导通的阈值补偿晶体管T2提供至第一节点N1，并将数据线DL输出的数据电压与驱动晶体管T3的阈值电压之差充入存储电容Cst，存储电容Cst的第一极板(即第一节点N1)的电压为Vdata-|Vth|，其中，Vdata为数据线DL输出的数据电压，Vth为驱动晶体管T3的阈值电压。第二复位晶体管T7导通，使得第二初始信号线INIT2提供的第二初始信号提供至第四节点N4，对第四节点N4进行初始化，确保第一发光单元EL1不发光。第一复位控制线RST1提供的第一复位控制信号为高电平信号，使第一复位晶体管T1断开。发光控制信号线EML提供的发光控制信号为高电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6断开。
第三阶段，称为发光阶段。发光控制信号线EML提供的发光控制信号为低电平信号，第一扫描线GL1提供的第一扫描信号和第一复位控制线RST1提供的第一复位控制信号为高电平信号。发光控制信号线EML提供的发光控制信号为低电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6导通，第一电源线VDD输出的第一电压信号通过导通的第一发光控制晶体管T5、驱动晶体管T3和第二发光控制晶体管T6向第一发光单元EL1的第一阳极提供驱动电压，驱动第一发光单元EL1发光。
在像素电路的驱动过程中，流过驱动晶体管T3的驱动电流由其栅极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata-|Vth|，因而驱动晶体管T3的驱动电流为：
I＝K×(Vgs-Vth) 2＝K×[(Vdd-Vdata+|Vth|)-Vth] 2＝K×[(Vdd-Vdata)] 2；
其中，I为流过驱动晶体管T3的驱动电流，也就是驱动发光元件EL的 驱动电流，K为常数，Vgs为驱动晶体管T3的栅极和第一极之间的电压差，Vth为驱动晶体管T3的阈值电压，Vdata为数据线DL输出的数据电压，Vdd为第一电源线VDD输出的第一电压信号。
由上式中可以看到驱动电流与驱动晶体管T3的阈值电压无关。因此，本实施例的像素电路可以较好地补偿驱动晶体管T3的阈值电压。
上述像素电路仅为示例。本实施例对于像素电路的结构并不限定。
在本示例中，在防窥显示模式下，子像素的发光元件的第一发光单元EL1被点亮，第二发光单元EL2不被点亮，可以限制子像素的出光面积和出光角度；在分享显示模式下，子像素的发光元件的第一发光单元EL1和第二发光单元EL2可以同时被点亮，可以增加子像素的出光面积和出光角度。本示例可以切换实现防窥效果和分享效果。
图7为图3中沿Q-Q’方向的局部剖面示例图。图7示意了一个第一子像素P1的局部剖面结构。在一些示例中，如图7所示，在垂直于显示面板的方向上，显示面板可以包括：衬底基板101、依次设置在衬底基板101上的显示结构层、封装结构层104、第一遮挡层105、第一保护层106和第二遮挡层107。显示结构层可以包括：依次设置在衬底基板101上的电路结构层102和发光结构层103。在一些可能的实现方式中，显示面板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
下面参照图7对显示面板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在衬底基板上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内” 或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在一些示例中，显示面板的制备过程可以包括如下操作。
(1)、提供衬底基板101。在一些示例中，衬底基板101可以为柔性基底，或者可以是刚性基底。例如，刚性基底可以包括玻璃基板。柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高衬底基板的抗水氧能力，半导体层的材料可以采用非晶硅(a-Si)。然而，本实施例对此并不限定。
(2)、形成电路结构层102。在一些示例中，电路结构层102可以包括：多个像素电路的晶体管和存储电容。图7中以一个像素电路的两个晶体管(例如第一晶体管201和第二晶体管202)和一个存储电容203的结构为例进行示意。例如，第一晶体管201可以为前述像素电路中的驱动晶体管T3、第二复位晶体管T7或第二发光控制晶体管T6，第二晶体管202可以为前述像素电路中的第一控制晶体管T8，存储电容203可以为前述像素电路中的存储电容Cst。
在一些示例中，如图7所示，电路结构层102可以包括：依次设置在衬底基板101上的缓冲层210、半导体层、第一绝缘层211、第一栅金属层、第二绝缘层212、第二栅金属层、第三绝缘层213、第一源漏金属层以及第四绝缘层214。
在一些示例中，如图7所示，在形成前述结构的衬底基板101上，依次沉积缓冲薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成缓冲层210和设置在缓冲层210上的半导体层。例如，半导体层至少可以包括：第一晶体管201的有源层和第二晶体管202的有源层。
随后，在形成前述结构的衬底基板101上，依次沉积第一绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成第一绝缘层211和设置在第一绝缘层211上的第一栅金属层。例如，第一栅金属层至少 可以包括：第一晶体管201的栅极、第二晶体管202的栅极和存储电容203的第一极板。
在一些示例中，在形成第一栅金属层后，可以利用第一栅金属层作为遮挡，对半导体层进行导体化处理，被第一栅金属层遮挡区域的半导体层可以形成晶体管的沟道区域，未被第一栅金属层遮挡区域的半导体层可以被导体化，即像素电路的多个晶体管的有源层的第一区和第二区均被导电化。
随后，在形成前述结构的衬底基板上，依次沉积第二绝缘薄膜和第二导电薄膜，通过图案化工艺对第二导电薄膜进行图案化，形成第二绝缘层212和设置在第二绝缘层212上的第二栅金属层。例如，第二栅金属层至少可以包括：存储电容203的第二极板。其中，存储电容203的第二极板在衬底基板的正投影与第一极板在衬底基板的正投影可以至少部分交叠。
随后，在形成前述结构的衬底基板上，沉积第三绝缘薄膜，通过图案化工艺对第三绝缘薄膜进行图案化，形成第三绝缘层213。第三绝缘层213可以开设有多个过孔。例如，第三绝缘层213的多个过孔可以分别暴露出半导体层、第一栅金属层和第二栅金属层的表面。
随后，在形成前述结构的衬底基板上，沉积第三导电薄膜，通过图案化工艺对第三导电薄膜进行图案化，在第三绝缘层213上形成第一源漏金属层。例如，第一源漏金属层至少可以包括：第一晶体管201的第一极和第二极、第二晶体管202的第一极和第二极。例如，第一晶体管201的第二极和第二晶体管202的第一极可以为一体结构。随后，在形成前述结构的衬底基板上，涂覆第四绝缘薄膜，通过图案化工艺形成第四绝缘层214。
在一些示例中，缓冲层210、第一绝缘层211、第二绝缘层212和第三绝缘层213可以为无机绝缘层，第四绝缘层214可以为有机绝缘层。例如，缓冲层210、第一绝缘层211、第二绝缘层212和第三绝缘层213可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。其中，第一绝缘层211和第二绝缘层212可称之为栅绝缘(GI)层，第三绝缘层213可称之为层间绝缘(ILD)层，第四绝缘层214可称之为平坦层。第一栅金属层、第二栅金属层和第一源漏金属层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo) 中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。半导体层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。
(3)、形成发光结构层103。在一些示例中，发光结构层103可以包括多个发光元件。
在一些示例中，在形成前述结构的衬底基板上沉积阳极薄膜，通过图案化工艺对阳极薄膜进行图案化，形成阳极层。例如，阳极层可以包括：第一发光单元的第一阳极301a和第二发光单元的第二阳极301b。第一阳极301a和第二阳极301b可以相互独立。第一阳极301a和第二阳极301b所在平面可以齐平。第一阳极301a可以通过第四绝缘层214开设的过孔与像素电路的第一晶体管201的第二极电连接，第二阳极301b可以通过第四绝缘层214开设的过孔与像素电路的第二晶体管202的第二极电连接。
随后，在形成前述结构的衬底基板上涂覆像素定义薄膜，通过掩膜、曝光和显影工艺形成像素定义层304。像素定义层304形成有暴露出阳极层的多个像素开口。例如，多个像素开口可以包括第一像素开口和第二像素开口。第一像素开口可以暴露出第一阳极301a的至少部分，第二像素开口可以暴露出第二阳极301b的至少部分。
随后，在前述形成的像素开口内形成有机发光层。例如，在第一像素开口内形成第一有机发光层302a，第一有机发光层302a与第一阳极301a连接；在第二像素开口内形成第二有机发光层302b，第二有机发光层302b与第二阳极301b连接。
随后，沉积阴极薄膜，通过图案化工艺对阴极薄膜进行图案化，形成阴极层。例如，阴极层可以包括第一发光单元的第一阴极303a和第二发光单元的第二阴极303b。第一阴极303a与第一有机发光层302a连接，第二阴极303b与第二有机发光层302b连接。第一阴极303a和第二阴极303b可以为一体结构。第一有机发光层302a在第一阳极301a和第一阴极303a施加电压的作用 下可以出射相应颜色的光线；第二有机发光层302b在第二阳极301b和第二阴极303b施加电压的作用下可以出射相应颜色的光线。例如，第一子像素P1的第一发光单元和第二发光单元可以均配置为出射红光。
在一些示例中，像素定义层304可以采用聚酰亚胺、亚克力、聚对苯二甲酸乙二醇酯或丙烯酸酯类等有机材料。例如，像素定义层304可以为黑色。通过设置黑色的像素定义层304可以吸收膜层内的反射光和折射光，改善发光元件的出光效果。然而，本实施例对此并不限定。
在一些示例中，有机发光层可以包括叠设的空穴注入层(HIL，Hole Injection Layer)、空穴传输层(HTL，Hole Transport Layer)、电子阻挡层(EBL，Electron Block Layer)、发光层(EML，Emitting Layer)、空穴阻挡层(HBL，Hole Block Layer)、电子传输层(ETL，Electron Transport Layer)和电子注入层(EIL，Electron Injection Layer)。在一些示例中，第一发光单元的第一有机发光层302a和第二发光单元的第二有机发光层302a可以相互隔离。然而，本实施例对此并不限定。例如，在一些示例中，所有子像素的空穴注入层可以是连接在一起的共通层，所有子像素的电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层可以是连接在一起的共通层，所有子像素的电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，相邻子像素的电子阻挡层可以有少量的交叠，或者可以是隔离的。
在一些示例中，发光单元的发光区域可以为像素定义层的像素开口暴露出的阳极与有机发光层和阴极的交叠区域。例如，第一发光单元的发光区域可以为像素定义层的第一像素开口内的第一阳极、第一有机发光层和第一阴极的交叠区域。第二发光单元的发光区域可以为像素定义层的第二像素开口内的第二阳极、第二有机发光层和第二阴极的交叠区域。
(4)、形成封装结构层104。在一些示例中，封装结构层104位于阴极层远离衬底基板101的一侧。封装结构层104可以包括叠设的第一封装层、第二封装层和第三封装层，其中，第一封装层和第三封装层可采用无机材料，第二封装层可采用有机材料，第二封装层可以设置在第一封装层和第三封装 层之间，可以保证外界水汽无法进入发光结构层103。在另一些示例中，封装结构层104可以采用无机材料/有机材料/无机材料/有机材料/无机材料的叠层结构。
(5)、形成第一遮挡层105。在一些示例中，在形成前述结构的衬底基板上涂覆黑色颜料或沉积黑铬(Cr)薄膜，通过图案化工艺对黑色颜料或黑铬薄膜进行图案化，形成第一遮挡层105。如图7所示，第一遮挡层105在衬底基板101的正投影可以位于像素定义层304在衬底基板101的正投影范围内。
图8为本公开至少一实施例的第一遮挡层的平面示意图。在一些示例中，如图8所示，第一遮挡层105在衬底基板的正投影与第一子像素、第二子像素和第三子像素的发光元件的发光区域在衬底基板的正投影可以没有交叠。第一遮挡层105在衬底基板的正投影可以围绕在第一子像素的第一发光单元P1-1、第二子像素的第一发光单元P2-1和第三子像素的第一发光单元P3-1的正投影的四周。例如，第一遮挡层105在衬底基板的正投影可以围绕在第一子像素的第一发光单元P1-1的发光区域、第二子像素的第一发光单元P2-1的发光区域和第三子像素的第一发光单元P3-1的发光区域的正投影的四周。换言之，第一发光单元P1-1的发光区域、第二子像素的第一发光单元P2-1的发光区域和第三子像素的第一发光单元P3-1的发光区域的四周可以由第一遮挡层105包围。相邻第二发光单元之间可以没有设置第一遮挡层105。本示例通过设置第一遮挡层105围绕在第一发光单元的周边，可以限制第一发光单元的出射角度，使得第一发光单元的出射光线向正视角方向集中出射，有利于实现防窥效果。
(6)、形成第一保护层106。在一些示例中，在形成前述结构的衬底基板上涂覆第一保护薄膜，通过图案化工艺形成第一保护(OC，Over Coat)层106。在一些示例中，第一保护层106可以采用丙烯酸酯类等材料。
(7)、形成第二遮挡层107。在一些示例中，在形成前述结构的衬底基板上涂覆黑色颜料或沉积黑铬(Cr)薄膜，通过图案化工艺对黑色颜料或黑铬薄膜进行图案化，形成第二遮挡层107。
在一些示例中，第二遮挡层107在衬底基板101的正投影可以位于像素 定义层304在衬底基板101的正投影范围内。第二遮挡层107在衬底基板的正投影可以围绕在第一发光单元的周围，并与第一发光单元和第二发光单元的发光区域在衬底基板的正投影可以没有交叠。例如，第二遮挡层107在衬底基板的正投影可以位于第一遮挡层105在衬底基板的正投影范围内。比如，第二遮挡层107在衬底基板的正投影可以与第一遮挡层105在衬底基板的正投影重合。然而，本实施例对此并不限定。
本示例通过设置两个遮挡层(即第一遮挡层105和第二遮挡层107)对第一发光单元进行围绕，可以限制第一发光单元的出射角度，从而有利于实现防窥效果。本实施例对于遮挡层的数目并不限定。在另一些示例中，遮挡层的数目可以大于或等于三个，相邻遮挡层之间可以设置保护层。在另一些示例中，遮挡层可以对发光元件进行围绕。
本公开示例性实施例的显示面板的结构及其制备过程仅仅是一种示例性说明。在一些示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，显示结构层还可以包括位于第一源漏金属层远离衬底基板一侧的第二源漏金属层，第二源漏金属层可以包括阳极连接电极，第一发光单元的第一阳极和第二发光单元的第二阳极可以分别通过阳极连接电极与像素电路电连接。然而，本公开在此不做限定。
图9为图3中沿Q-Q’方向的另一局部剖面示例图。在一些示例中，如图9所示，在垂直于显示面板的方向上，显示面板可以包括：衬底基板101、依次设置在衬底基板101上的显示结构层、封装结构层104、第一遮挡层105、第一保护层106和彩色滤光层108。显示结构层可以包括：依次设置在衬底基板101上的电路结构层102和发光结构层103。关于显示结构层、封装结构层104、第一遮挡层105和第一保护层106的结构可以参照前述实施例的说明，故于此不再赘述。
在一些示例中，如图9所示，彩色滤光层108可以位于第一保护层106远离衬底基板101的一侧。彩色滤光层108可以包括：周期性排布的多个滤光单元和设置在相邻滤光单元之间的黑矩阵800。多个滤光单元可以与多个子像素的发光元件一一对应。例如，多个滤光单元可以包括第一滤光单元801、第二滤光单元和第三滤光单元。第一滤光单元801可以与第一子像素P1的 发光元件对应，第二滤光单元可以与第二子像素P2的发光元件对应，第三滤光单元可以与第三子像素P3的发光元件对应。例如，第一滤光单元801可以为红色滤光单元，第二滤光单元可以为绿色滤光单元，第三滤光单元可以为蓝色滤光单元。
在本实施例中，滤光单元可以使单一颜色光通过并吸收其他颜色光。例如，蓝色滤光单元可以让蓝光通过并吸收其他颜色光，红色滤光单元可以让红光通过并吸收其他颜色光，绿色滤光单元可以让绿光通过并吸收其他颜色光。
在一些示例中，至少一个滤光单元可以包括：第一子滤光单元和第二子滤光单元。滤光单元在衬底基板的正投影可以覆盖对应的发光元件的发光区域在衬底基板的正投影。例如，如图9所示，第一滤光单元801可以包括第一子滤光单元801a和第二子滤光单元801b。第一子滤光单元801a在衬底基板101的正投影可以覆盖第一子像素的第一发光单元的发光区域在衬底基板101的正投影；第二子滤光单元801b在衬底基板101的正投影可以覆盖第一子像素的第二发光单元的发光区域在衬底基板101的正投影。然而，本实施例对此并不限定。在另一些示例中，一个滤光单元在衬底基板的正投影可以覆盖对应的发光元件的第一发光单元和第二发光单元的发光区域在衬底基板的正投影。
在一些示例中，在制备完成第一保护层106之后，可以通过以下方式制备彩色滤光层108：在第一保护层106上涂覆黑色颜料或沉积黑铬(Cr)薄膜，通过图案化工艺对黑色颜料或黑铬薄膜进行图案化处理，形成黑矩阵800；随后，依次形成多个第一滤光单元801、多个第二滤光单元和多个第三滤光单元。以第一滤光单元801为红色滤光单元为例，先在已形成黑矩阵800的第一保护层106上涂覆红色树脂，经烘烤固化后，通过掩模曝光、显影，形成红色滤光单元。关于绿色滤光单元和蓝色滤光单元的形成过程类似，故于此不再赘述。
在本示例中，通过设置一个遮挡层(即第一遮挡层)和彩色滤光层，限制第一发光单元的出射角度，从而有利于实现防窥效果。本实施例对于遮挡层的数目并不限定。在另一些示例中，在封装结构层和彩色滤光层之间可以 设置至少两个遮挡层，相邻遮挡层之间可以设置保护层。
图10为图3中沿R-R’方向的剖面结构的光线出射示意图。图11为图3中沿U-U’方向的剖面结构的光线出射示意图。图10和图11中省略示意了衬底基板和显示结构层的部分膜层。图10以第一子像素P1的第一发光单元P1-1和第二子像素P2的第一发光单元P2-1的出射光线为例进行示意；图11以第一子像素P1的第二发光单元P1-2和第二子像素P2的第二发光单元P2-2的出射光线为例进行示意。其中，第一子像素P1的出射光线L1可以采用带箭头的虚线表示，第二子像素P2的出射光线L2可以采用带箭头的点划线表示，被显示面板内的膜层吸收的光线L3可以采用带箭头的实线表示。
在本示例中，正视角方向可以为垂直于显示面板所在平面的方向。斜视角方向可以指除正视角方向以外的视线方向。
在一些示例中，如图3和图10所示，第一遮挡层105在衬底基板的正投影可以围绕在第一发光单元P1-1的发光区域的周围。第一子像素P1的第一发光单元P1-1的出射光线可以沿正视角方向射出，第一发光单元P1-1向右侧斜视角方向的出射光线会被第一遮挡层105和彩色滤光层108的黑矩阵800吸收，第一发光单元P1-1向左侧斜视角方向的出射光线会被第一遮挡层105和彩色滤光层108的黑矩阵800吸收。同理，第二子像素P2的第一发光单元P2-1的出射光线可以沿正视角方向射出，斜视角方向的出射光线会被第一遮挡层105和彩色滤光层108的黑矩阵800吸收。在本示例中，在第一发光单元被点亮时，第一发光单元的出射光线的出射角度被第一遮挡层105和彩色滤光层108的黑矩阵800所限制，可以提高显示面板沿第一方向X的防窥效果。
在一些示例中，如图3和图11所示，相邻第二发光单元(例如第二发光单元P1-2和P2-2)之间没有设置第一遮挡层。相邻第二发光单元之间的黑矩阵800的尺寸可以小于相邻第一发光单元之间的黑矩阵800的尺寸。第一子像素P1的第二发光单元P1-2的出射光线不仅可以沿正视角方向射出，还可以沿部分斜视角方向射出。本示例中的第二发光单元的出射光线的出射角度可以大于第一发光单元的出射光线的出射角度。在显示面板的分享显示模式下，第一发光单元和第二发光单元可以被同时点亮，且第二发光单元的出 射光线的出射角度大于第一发光单元的出射光线的出射角度，有利于实现分享显示效果，从而提高用户体验。
图12为图3中沿Q-Q’方向的另一局部剖面示例图。在一些示例中，如图12所示，在垂直于显示面板的方向上，显示面板可以包括：衬底基板101、依次设置在衬底基板101上的显示结构层、封装结构层104、第一遮挡层105、第一保护层106和第二遮挡层107。显示结构层可以包括：依次设置在衬底基板101上的电路结构层102和发光结构层103。在本示例中，第一发光单元P1-1的第一阳极301a和第二发光单元P1-2的第二阳极201b可以没有位于同一平面内。第一阳极301a可以位于第二阳极301b靠近衬底基板101的一侧。第二阳极301b靠近衬底基板101一侧的第四绝缘层214的厚度可以大于第一阳极301b靠近衬底基板101一侧的第四绝缘层214的厚度，如此一来，使得第一阳极301a和第二阳极301b不处于同一平面内。第二阳极301b周边的像素定义层304的高度可以大于第一阳极301a周边的像素定义层304的高度。
在本实施例中，膜层的高度可以指膜层远离衬底基板一侧的表面至衬底基板所在平面的距离。膜层的厚度可以指膜层远离衬底基板一侧的表面与靠近衬底基板一侧的表面之间的距离。
在一些示例中，如图3和图12所示，第一发光单元P1-1的第一阳极301a与出光面(例如第一保护层106远离衬底基板101一侧的表面)之间的距离，大于第二发光单元P1-2的第二阳极301b与出光面之间的距离，使得第一发光单元P1-1的出射角度范围小于第二发光单元P1-2的出射角度范围。第一发光单元P1-1的出射光线向正视角方向集中，第二发光单元P1-2的出射光线的出射角度可以大于第一发光单元P1-1的出射光线的出射角度。本实施例的显示面板的其余结构可以参照前述实施例的说明，故于此不再赘述。
在本示例中，通过设置第一发光单元的第一阳极和第二发光单元的第二阳极不位于同一平面，且第一阳极位于第二阳极靠近衬底基板的一侧，可以有利于增加第二发光单元的出射角度。如此一来，在第一发光单元被点亮时可以实现防窥显示效果，在第一发光单元和第二发光单元同时被点亮时可以实现分享显示效果。
图13为图3中沿Q-Q’方向的另一局部剖面示例图。在一些示例中，如图13所示，在垂直于显示面板的方向上，显示面板可以包括：衬底基板101、依次设置在衬底基板101上的显示结构层、封装结构层104、第一遮挡层105、光调节层110、第一保护层106和第二遮挡层107。显示结构层可以包括：依次设置在衬底基板101上的电路结构层102和发光结构层103。在本示例中，第一遮挡层105远离衬底基板101一侧可以设置光调节层110。光调节层110可以包括至少一个透镜单元111。透镜单元111在衬底基板101的正投影可以与第一发光单元P1-1的发光区域在衬底基板的正投影至少部分交叠。例如，透镜单元111可以为一个凸透镜。透镜单元111在衬底基板101的正投影可以覆盖第一发光单元P1-1的发光区域在衬底基板101的正投影。在另一些示例中，透镜单元111可以包括阵列排布的多个子透镜单元，多个子透镜单元在衬底基板的正投影可以位于第一发光单元的发光区域在衬底基板的正投影范围内。在一些示例中，光调节层110的折射率可以大于第一保护层106的折射率。本实施例的显示面板的其余结构可以参照前述实施例的说明，故于此不再赘述。
本示例通过在第一发光单元的出射光线路径上设置光调节层，有利于提高第一发光单元的出光效率，从而保证第一发光单元被点亮时的防窥显示效果。
图14为图3中沿Q-Q’方向的另一局部剖面示例图。在一些示例中，如图14所示，在垂直于显示面板的方向上，显示面板可以包括：衬底基板101、依次设置在衬底基板101上的显示结构层、封装结构层104、第一遮挡层105、第二保护层109、第一保护层106和第二遮挡层107。显示结构层可以包括：依次设置在衬底基板101上的电路结构层102和发光结构层103。在本示例中，第二保护层109可以位于第一保护层106靠近衬底基板101的一侧。第二保护层109在衬底基板的正投影可以覆盖第一遮挡层105在衬底基板的正投影。第一保护层106在衬底基板的正投影可以覆盖第二保护层109在衬底基板的正投影。第二保护层109在衬底基板的正投影与第一发光单元和第二发光单元的发光区域在衬底基板的正投影可以没有交叠。第二保护层109的折射率可以小于第一保护层106的折射率。本示例的第二保护层109和第一 保护层106可以形成出光效率增强结构(EES，Efficiency Enhance Structure)，第一发光单元的出射光线会在第一保护层106和第二保护层109发生折射和全反射，使得出射光线向正视角方向集中出射，从而实现防窥显示效果。本实施例的显示面板的其余结构可以参照前述实施例的说明，故于此不再赘述。
本示例通过第一保护层和第二保护层形成ESS，有利于提高第一发光单元的出光效率，从而保证第一发光单元被点亮时的防窥显示效果。
图15为图3中沿Q-Q’方向的另一局部剖面示例图。在一些示例中，如图15所示，在垂直于显示面板的方向上，显示面板可以包括：衬底基板101、依次设置在衬底基板101上的显示结构层、封装结构层104、第一遮挡层105、光调节层110、第一保护层106和第二遮挡层107。本示例中，第一发光单元P1-1的第一阳极301a和第二发光单元P1-2的第二阳极201b没有位于同一平面内。第一阳极301a可以位于第二阳极301b靠近衬底基板101的一侧。本实施例的显示面板的其余结构可以参照前述实施例的说明，故于此不再赘述。
在本示例中，通过设置第一发光单元的第一阳极和第二发光单元的第二阳极不位于同一平面，且第一阳极位于第二阳极靠近衬底基板的一侧，可以有利于增加第二发光单元的出射角度，而且通过在第一发光单元的出射光线路径上设置光调节层，有利于提高第一发光单元的出光效率，从而保证第一发光单元被点亮时的防窥显示效果。
图16为图3中沿Q-Q’方向的另一局部剖面示例图。在一些示例中，如图16所示，在垂直于显示面板的方向上，显示面板可以包括：衬底基板101、依次设置在衬底基板101上的显示结构层、封装结构层104、第一遮挡层105、第二保护层109、第一保护层106和第二遮挡层107。本示例中，第一发光单元P1-1的第一阳极301a和第二发光单元P1-2的第二阳极201b没有位于同一平面内。第一阳极301a可以位于第二阳极301b靠近衬底基板101的一侧。本实施例的显示面板的其余结构可以参照前述实施例的说明，故于此不再赘述。
在本示例中，通过设置第一发光单元的第一阳极和第二发光单元的第二阳极不位于同一平面，且第一阳极位于第二阳极靠近衬底基板的一侧，可以有利于增加第二发光单元的出射角度，而且通过第一保护层和第二保护层形 成ESS，有利于提高第一发光单元的出光效率，从而保证第一发光单元被点亮时的防窥显示效果。
在另一些示例中，上述实施例可以相互组合。例如，显示面板可以包括第一保护层、第二保护层和光调节层，第一发光单元的第一阳极和第二发光单元的第二阳极可以不位于同一平面。然而，本实施例对此并不限定。
图17为本公开至少一实施例的显示面板的子像素的另一平面示意图。在一些示例中，如图17所示，显示面板的显示区域内的多个子像素可以阵列排布，例如可以分别沿第一方向X和第二方向Y依次排布。沿第一方向X上，第一子像素P1、第二子像素P2和第三子像素P3可以周期性排布，沿第二方向Y上，出射相同颜色光的子像素依次排布。
在一些示例中，如图17所示，至少一个子像素的发光元件可以沿第一方向X被划分为两个发光单元。例如，第一子像素P1的发光元件可以包括：沿第一方向X排布的第一发光单元P1-1和第二发光单元P1-2；第二子像素P2的发光元件可以包括：沿第一方向X排布的第一发光单元P2-1和第二发光单元P2-2；第三子像素P3的发光元件可以包括：沿第一方向X排布的第一发光单元P3-1和第二发光单元P3-2。其中，至少一个发光元件的第一发光单元的发光区域和第二发光单元的发光区域可以相互隔离。至少一个发光元件的第一发光单元的发光区域的面积可以大于第二发光单元的发光区域的面积。至少一个发光元件的第一发光单元的发光区域和第二发光单元的发光区域可以为尺寸不同的矩形或圆角矩形。然而，本实施例对此并不限定。在另一些示例中，至少一个发光元件的第一发光单元的发光区域的面积可以小于或等于第二发光单元的发光区域的面积。
在一些示例中，在防窥显示模式下，至少一个子像素的发光元件的第一发光单元可以被配置为发光，第二发光单元可以被配置为不发光；在分享显示模式下，第二发光单元可以被配置为随同第一发光单元发光。
在一些示例中，如图17所示，出射相同颜色光的子像素的第一发光单元和第二发光单元沿第一方向X交替排布，且沿第二方向Y交替排布。其中，在第一方向X上，一个第一子像素P1的第一发光单元P1-1和第二发光单元P1-2的排布顺序与相邻的第一子像素P1的第一发光单元P1-1和第二发光单 元P1-2的排布顺序可以不同。例如，一个第一子像素P1的第一发光单元P1-1可以位于第二发光单元P1-2的左侧，在第一方向X上相邻的第一子像素P1的第一发光单元P1-1可以位于第二发光单元P1-2的右侧。在第二方向Y上，一个第一子像素P1的第一发光单元P1-1和第二发光单元P1-2的排布顺序与相邻的第一子像素P1的第一发光单元P1-1和第二发光单元P1-2的排布顺序可以不同。例如，一个第一子像素P1的第一发光单元P1-1可以位于第二发光单元P1-2的左侧，在第二方向Y上相邻的第一子像素P1的第一发光单元P1-1可以位于第二发光单元P1-2的右侧。关于第二子像素P2和第三子像素P3的两个发光单元的排布方式与第一子像素P1的两个发光单元的排布方式相同，故于此不再赘述。
图18为图17中沿V-V’方向的剖面结构在防窥显示模式下的光线出射示意图。图19为图17中沿V-V’方向的剖面结构在分享显示模式下的光线出射示意图。图20为图17中沿O-O’方向的剖面结构在分享显示模式下的光线出射示意图。图21为图17中沿V-V’方向的剖面结构的示意图。图18至图21中省略示意了衬底基板和显示结构层的部分膜层。图18至图21中以第一子像素P1和第二子像素P2的出射光线为例进行示意。其中，第一子像素P1的出射光线L1可以采用带箭头的虚线表示，第二子像素P2的出射光线L2可以采用带箭头的点划线表示，被显示面板内的膜层吸收的光线L3可以采用带箭头的实线表示。
在一些示例中，如图18至图21所示，在垂直于显示面板的方向上，显示面板可以包括：衬底基板、以及设置在衬底基板上的显示结构层、封装结构层104、第三阻挡层105a、第一保护层106和彩色滤光层108a。本示例的第三阻挡层105a在衬底基板的正投影与发光元件的发光区域在衬底基板的正投影可以没有交叠，第三阻挡层105a在衬底基板的正投影可以围绕在发光元件的周围。例如，第三阻挡层105a在衬底基板的正投影可以位于像素定义层304在衬底基板的正投影范围内。然而，本实施例对此并不限定。在另一些示例中，第三阻挡层在衬底基板的正投影可以围绕在发光元件的第一发光单元的发光区域在衬底基板的正投影的四周。
在一些示例中，如图18至图21所示，彩色滤光层108a可以包括：周期 性排布的多个滤光单元(例如包括第一滤光单元801、第二滤光单元802和第三滤光单元803)、以及设置在相邻滤光单元之间的黑矩阵800。第一滤光单元801可以与第一子像素P1的发光元件对应，第二滤光单元802可以与第二子像素P2的发光元件对应，第三滤光单元803可以与第三子像素P3的发光元件对应。滤光单元在衬底基板的正投影可以覆盖对应子像素的发光元件的发光区域在衬底基板的正投影。彩色滤光层108a的黑矩阵800在衬底基板的正投影可以位于第三阻挡层105a在衬底基板的正投影范围内。然而，本实施例对此并不限定。
在一些示例中，如图18至图21所示，以第一子像素P1为例进行说明，在第一方向X上，第一子像素P1的第二发光单元P1-2的发光区域靠近第二子像素P2的边缘与黑矩阵800靠近第一滤光单元801的边缘可以对齐。第一滤光单元801远离第二滤光单元802的边缘在衬底基板的正投影可以与第三遮挡层105a在衬底基板的正投影存在交叠。
在一些示例中，如图17和图18所示，在防窥显示模式下，第一子像素P1的第一发光单元P1-1可以被配置为发光，第二发光单元P1-2可以被配置为不发光。第一发光单元P1-1的出射光线可以沿正视角方向射出，第一发光单元P1-1向右侧斜视角方向的出射光线会被彩色滤光层108a的黑矩阵800和第二滤光单元802吸收，第一发光单元P1-1向左侧斜视角方向的出射光线的一部分可以通过第一滤光单元801射出，另一部分会被黑矩阵800和第三阻挡层105a吸收。本示例的第一发光单元P1-1的出射光线的出射角度受限于彩色滤光层108a的黑矩阵800和第三阻挡层105a。
在一些示例中，如图19所示，在分享显示模式下，第一子像素P1的第一发光单元P1-1和第二发光单元P1-2可以均被配置为发光。第一发光单元P1-1和第二发光单元P1-2的出射光线可以沿正视角方向射出。第二发光单元P1-2在第一方向X上位于第一发光单元P1-1和第一发光单元P2-1之间。第一发光单元P1-1向右侧斜视角方向的出射光线会被彩色滤光层108a的黑矩阵800和第二滤光单元802以及第三阻挡层105a吸收，第一发光单元P1-1向左侧斜视角方向的出射光线的一部分可以通过第一滤光单元801射出，另一部分会被黑矩阵800和第三阻挡层105a吸收。在分享显示模式下，通过同 时点亮第一发光单元P1-1和第二发光单元P1-2，可以增加发光元件的出射光线的出射角度，从而提高分享显示效果。
在一些示例中，如图20所示，在分享显示模式下，第一发光单元P1-1和第二发光单元P1-2的出射光线可以沿正视角方向射出。第一发光单元P1-1在第一方向X上位于第二发光单元P1-2和第二发光单元P2-2之间。第一发光单元P1-1和第二发光单元P1-2向左侧斜视角方向的出射光线会被彩色滤光层108a的黑矩阵800和第二滤光单元802以及第三阻挡层105a吸收，第一发光单元P1-1和第二发光单元P1-2向右侧斜视角方向的出射光线的一部分可以通过第一滤光单元801射出，另一部分会被黑矩阵800和第三阻挡层105a吸收。
本示例中，相较于防窥显示模式，子像素在分享显示模式下的出射角度得到增加。通过设置子像素的第一发光单元和第二发光单元沿第一方向交替排布且沿第二方向交替排布，可以使得分享显示模式下，子像素在第一方向上实现左发射光和右发射光交替，从而提高分享显示效果，提高用户体验。
在一些示例中，如图21所示，像素定义层304可以包括：位于同一发光元件的第一发光单元和第二发光单元(例如第一发光单元P1-1和第二发光单元P1-2)之间的第一像素定义部3041、以及位于相邻发光元件之间的第二像素定义部3042。第一像素定义部3041沿第一方向X的长度C2可以小于第二像素定义部3042沿第一方向X的长度C1。换言之，相邻发光元件之间的间距可以大于同一发光元件的第一发光单元和第二发光单元之间的间距。
在一些示例中，如图21所示，彩色滤光层108a的黑矩阵800的至少部分边缘可以与第三阻挡层105a的部分边缘齐平。黑矩阵800在衬底基板的正投影可以位于第三阻挡层105a在衬底基板的正投影范围内。彩色滤光层108a的滤光单元在衬底基板的正投影可以覆盖对应的发光元件的第一发光单元和第二发光单元的发光区域在衬底基板的正投影。在一些示例中，第一滤光单元801a沿第一方向X的长度可以大于第一子像素P1的第一发光单元P1-1的发光区域沿第一方向X的长度B1、第二发光单元P1-2的发光区域沿第一方向X的长度B2以及第一像素定义部3041沿第一方向X的长度C2之和。例如，第一滤光单元801a沿第一方向的长度可以等于第一子像素P1的第一 发光单元P1-1的发光区域沿第一方向X的长度B1、第二发光单元P1-2的发光区域沿第一方向X的长度B2、第一像素定义部3041沿第一方向X的长度C2以及第一长度B3之和。第一长度B3可以大于或等于第二发光单元P1-2的发光区域沿第一方向X的长度B2。例如，第一滤光单元801a沿第一方向的长度可以等于B1+C2+B2+B2。
在一些示例中，第二子像素的第一发光单元和第二发光单元的尺寸、第三子像素的第一发光单元和第二发光单元的尺寸可以与第一子像素的第一发光单元和第二发光单元的尺寸大致相同。本示例的第一滤光单元的尺寸设置有利于改善分享显示模式下的分享显示效果。关于第二滤光单元和第三滤光单元的尺寸描述与第一滤光单元的描述类似，故于此不再赘述。
在一些示例中，如图21所示，第一保护层106的厚度H2可以大于或等于第一发光单元P1-1的发光区域沿第一方向X的长度B1、第二发光单元P1-2的发光区域沿第一方向X的长度B2、第一像素定义部3041沿第一方向X的长度C2之和与封装结构层104的厚度之差。换言之，H2可以大于或等于B1+B2+C2-E。本示例的第一保护层的厚度设置有利于增加第一发光单元和第二发光单元在分享显示模式下的出射角度，从而改善分享显示模式下的分享显示效果。
图22为本公开至少一实施例的像素电路的另一示意图。在一些示例中，如图22所示，像素电路可以至少包括：驱动子电路11、数据写入子电路12、存储子电路13和控制子电路14。数据写入子电路12可以与第一扫描线GL1、数据线DL和驱动子电路11电连接，配置为在第一扫描线GL1的控制下，向驱动子电路11提供数据线DL传输的数据信号。驱动子电路11可以与存储子电路13、数据写入子电路12、控制子电路14和第一发光单元EL1电连接，配置为驱动第一发光单元EL1发光。存储子电路13可以与驱动子电路11和第一电源线VDD电连接。控制子电路14可以与第二扫描线GL2、第一电源线VDD、驱动子电路11、第一发光单元EL1和第二发光单元EL2电连接，配置为在第二扫描线GL2的控制下，驱动第二发光单元EL2随同第一发光单元EL1发光，或者驱动第二发光单元EL2发光。
图23为本公开至少一实施例的像素电路的等效电路图。在一些示例中， 如图23所示，像素电路可以为4T1C结构。其中，驱动子电路11可以包括驱动晶体管T3，数据写入子电路12可以包括数据写入晶体管T4，存储子电路13可以包括存储电容Cst，控制子电路14可以包括第一控制晶体管T8和第二控制晶体管T9。
在一些示例中，如图23所示，数据写入晶体管T4的栅极与第一扫描线GL1电连接，数据写入晶体管T4的第一极与数据线DL电连接，数据写入晶体管T4的第二极与存储电容Cst1的第一极板电连接。存储电容Cst的第二极板与第一电源线VDD电连接。驱动晶体管T3的栅极与存储电容Cst的第一极板电连接，驱动晶体管T3的第一极与第一电源线VDD电连接，驱动晶体管T3的第二极与第一发光单元EL1的第一阳极电连接。第一控制晶体管T8的栅极与第二扫描线GL2电连接，第一控制晶体管T8的第一极与第一发光单元EL1的第一阳极电连接，第一控制晶体管T8的第二极与第二发光单元EL2的第二阳极电连接。第二控制晶体管T9的栅极与第二扫描线GL2电连接，第二控制晶体管T9的第一极与第一发光单元EL1的第一阳极电连接，第二控制晶体管T9的第二极与第二发光单元EL2的第二阳极电连接。
在一些示例中，第一控制晶体管T8和第二控制晶体管T9的晶体管类型可以不同。例如，第一控制晶体管T8可以为P型晶体管，第二控制晶体管T9可以为N型晶体管；或者，第一控制晶体管T8可以为N型晶体管，第二控制晶体管T9可以为P型晶体管。本实施例对此并不限定。
在一些示例中，如图23所示，以驱动晶体管T3、数据写入晶体管T4和第一控制晶体管T8均为P型晶体管，第二控制晶体管T9为N型晶体管为例。在防窥显示模式下，第二扫描线GL2提供的第二扫描信号可以持续为高电平信号，使得第一控制晶体管T8断开，驱动晶体管T3在数据信号的控制下可以仅驱动第一发光单元EL1发光；第二扫描信号为高电平信号，使得第二控制晶体管T9导通，驱动第二发光单元EL2发光。
在一些示例中，在分享显示模式下，第二扫描线GL2提供的第二扫描信号可以为低电平信号，第一控制晶体管T8导通，第二控制晶体管T9断开，使得驱动晶体管T3在数据信号的控制下可以同时驱动第一发光单元EL1和第二发光单元EL2发光，即第二发光单元EL2可以随同第一发光单元EL1 发光。关于本实施例的像素电路驱动第一发光单元EL1发光的过程可以参照前述实施例的像素电路的描述，故于此不再赘述。
本实施例对于控制子电路的结构并不限定。在另一些示例中，第二控制晶体管和第一控制晶体管的类型可以相同，第二控制晶体管的栅极可以与第三扫描线电连接，第三扫描线提供的第三扫描信号和第二扫描线提供的第二扫描信号的相位可以相反。然而，本实施例对此并不限定。
在一些示例中，显示区域的子像素的排布方式可以如图3所示。至少一个子像素的发光元件可以被划分为两个发光单元(例如，第一发光单元和第二发光单元)。图24为本公开至少一实施例的发光元件的局部剖面示意图。例如图24为图3中沿Q-Q’方向的局部剖面示意图。图24示意了第一子像素的第一发光单元和第二发光单元的局部剖面结构。
在一些示例中，如图24所示，在垂直于显示面板的方向上，显示面板可以包括：衬底基板101、依次设置在衬底基板101的显示结构层、封装结构层104和阻光层120。显示结构层可以包括：依次设置在衬底基板101上的电路结构层102和发光结构层103。阻光层120可以设置在封装结构层104远离衬底基板101的一侧。在一些示例中，在阻光层120远离衬底基板一侧还可以设置彩色滤光层。然而，本实施例对此并不限定。
在一些示例中，如图24所示，阻光层120可以包括多个阻光部121。阻光部121在衬底基板101的正投影可以覆盖第二发光单元的发光区域在衬底基板101的正投影。在本示例中，发光元件的第一发光单元可以作为主要发光单元，第二发光单元可以作为辅助发光单元。由于第二发光单元的发光区域被阻光部121覆盖，第二发光单元沿正视角方向的出射光线会被阻光部121吸收，沿侧视角方向的出射光线可以射出。在图24中，第一子像素P1的出射光线L1可以采用带箭头的虚线表示，被显示面板内的膜层吸收的光线L3可以采用带箭头的实线表示。在一些示例中，阻光层120的材料和制备过程与前述的第一遮挡层类似，故于此不再赘述。
在本示例中，发光元件的第一发光单元可以向全视角方向射出光线，发光元件的第二发光单元被阻光层遮挡，仅可以沿侧视角方向射出光线。正视角方向的用户无法看到第二发光单元的显示画面。通过设置显示面板的多个 子像素的第二发光单元在防窥显示模式下均被点亮，可以使得侧视角用户看到白色画面。如此一来，仅在正视角方向的用户才能看到正常显示画面，在侧视角方向的用户都看到白色画面，从而达到防窥效果。
图25A为本公开至少一实施例的显示面板在防窥显示模式下的单色画面的示意图。图25B为本公开至少一实施例的显示面板在分享显示模式下的单色画面的示意图。图25A和图25B所示的单色画面为红色画面。图25A和图25B以一个像素单元为例进行示意。如图25A所示，在防窥显示模式下，第一子像素P1的第一发光单元P1-1和第二发光单元P1-1可以被点亮，例如，第一发光单元P1-1在像素电路的驱动晶体管的驱动下发光，第二发光单元P1-2可以在第二控制晶体管的驱动下发光。第二子像素P2的第一发光单元P2-1和第三子像素P3的第一发光单元P3-1被配置为不发光；第二子像素P2的第二发光单元P2-2和第三子像素P3的第二发光单元P3-2可以被配置为发光。如此一来，在防窥显示模式下，正视角方向的用户可以看到红色画面，侧视角方向的用户可以看到白色画面。如图25B所示，在分享显示模式下，第一子像素P1的第一发光单元P1-1被配置为发光，第二发光单元P1-2可以被配置为随同第一发光单元P1-1发光。例如，第一发光单元P1-1和第二发光单元P1-2可以在驱动晶体管的驱动下发光。第二子像素P2的第一发光单元P2-1和第二发光单元P2-2、第三子像素P3的第一发光单元P3-1和第二发光单元P3-2均不发光。关于蓝色画面和绿色画面的显示方式类似，故于此不再赘述。
图26A为本公开至少一实施例的显示面板在防窥显示模式下的黑色画面的示意图。图26B为本公开至少一实施例的显示面板在分享显示模式下的黑色画面的示意图。图26A和图26B以一个像素单元为例进行示意。如图26A所示，在防窥显示模式下，第一子像素P1的第一发光单元P1-1、第二子像素P2的第一发光单元P2-1、第三子像素P3的第一发光单元P3-1均被配置为不发光。第一子像素P1的第二发光单元P1-2、第二子像素P2的第二发光单元P2-2和第三子像素P3的第二发光单元P3-2可以均被配置为发光。如此一来，在防窥显示模式下，正视角方向的用户可以看到黑色画面，侧视角方向的用户可以看到白色画面。如图26B所示，在分享显示模式下，第一子像 素P1的第一发光单元P1-1和第二发光单元P1-2、第二子像素P2的第一发光单元P2-1和第二发光单元P2-2、第三子像素P3的第一发光单元P3-1和第二发光单元P3-2可以均被配置为不发光。
图27为本公开至少一实施例的显示面板在防窥显示模式下的白色画面的示意图。图27以一个像素单元为例进行示意。如图27所示，在防窥显示模式下，第一子像素P1的第一发光单元P1-1和第二发光单元P1-2、第二子像素P2的第一发光单元P2-1和第二发光单元P2-2、第三子像素P3的第一发光单元P3-1和第二发光单元P3-2可以均被配置为发光。如此一来，在防窥显示模式下，正视角方向的用户可以看到白色画面，侧视角方向的用户可以看到白色画面。在分享显示模式下，第一子像素P1的第一发光单元P1-1和第二发光单元P1-2、第二子像素P2的第一发光单元P2-1和第二发光单元P2-2、第三子像素P3的第一发光单元P3-1和第二发光单元P3-2可以均被配置为发光。
本示例的显示面板通过设置第一控制晶体管和第二控制晶体管来控制第二发光单元的发光状态，并通过阻光层对第二发光单元的发光区域进行遮挡，使得防窥显示模式下，第二发光单元可以保持发光状态，如此一来，侧视角方向的用户只能看到白色画面，从而实现防窥效果。
本实施例还提供一种显示面板的制备方法，包括：在衬底基板形成显示结构层，显示结构层包括多个子像素。多个子像素中的至少一个子像素包括：像素电路以及与像素电路电连接的发光元件。发光元件包括：第一发光单元和第二发光单元；第一发光单元的发光区域与第二发光单元的发光区域相互隔离。像素电路配置为在防窥显示模式下驱动第一发光单元和第二发光单元中的至少之一发光。
关于本实施例的显示面板的制备方法可以参照前述实施例的说明，故于此不再赘述。
图28为本公开至少一实施例的显示装置的示意图。在一些示例中，如图28所示，本实施例提供一种显示装置91，包括前述实施例的显示面板910。在一些示例中，显示面板910可以为OLED显示基板、QLED显示基板、Micro-LED显示基板、或者Mini-LED显示基板。显示装置91可以为：手机、 平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。然而，本实施例对此并不限定。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (21)

  1. 一种显示面板，包括：衬底基板、以及设置在所述衬底基板上的显示结构层，所述显示结构层包括多个子像素；所述多个子像素中的至少一个子像素包括：像素电路以及与所述像素电路电连接的发光元件，所述发光元件包括：第一发光单元和第二发光单元；所述第一发光单元的发光区域与所述第二发光单元的发光区域相互隔离；所述像素电路配置为在防窥显示模式下驱动所述第一发光单元和所述第二发光单元中的至少之一发光。
  2. 根据权利要求1所述的显示面板，其中，所述像素电路配置为在所述防窥显示模式下仅驱动所述第一发光单元发光，在分享显示模式下驱动所述第二发光单元随同所述第一发光单元发光。
  3. 根据权利要求1或2所述的显示面板，其中，所述发光元件的第一发光单元的发光区域的面积大于或等于第二发光单元的发光区域的面积。
  4. 根据权利要求1至3中任一项所述的显示面板，还包括：位于所述显示结构层的出光侧的至少一个遮挡层，所述遮挡层在所述衬底基板的正投影与所述发光元件的第一发光单元和第二发光单元的发光区域在所述衬底基板的正投影没有交叠；所述遮挡层在所述衬底基板的正投影围绕在所述发光元件的第一发光单元在所述衬底基板的正投影的周围，或者，所述遮挡层在所述衬底基板的正投影围绕在所述发光元件在所述衬底基板的正投影的周围。
  5. 根据权利要求4所述的显示面板，还包括：位于所述至少一个遮挡层远离所述衬底基板一侧的彩色滤光层，所述彩色滤光层包括：周期性排布的多个滤光单元以及位于相邻滤光单元之间的黑矩阵，所述多个滤光单元与所述多个子像素的发光元件一一对应。
  6. 根据权利要求5所述的显示面板，其中，所述多个滤光单元中的至少一个滤光单元在所述衬底基板的正投影覆盖对应子像素的发光元件在所述衬底基板的正投影。
  7. 根据权利要求4至6中任一项所述的显示面板，还包括：位于所述至少一个遮挡层远离所述衬底基板一侧的光调节层，所述光调节层包括：至少一个透镜单元，所述至少一个透镜单元在所述衬底基板的正投影与所述发光 元件的第一发光单元的发光区域在所述衬底基板的正投影至少部分交叠。
  8. 根据权利要求4至7中任一项所述的显示面板，还包括：位于所述至少一个遮挡层远离所述衬底基板一侧的第一保护层和第二保护层；所述第二保护层位于所述第一保护层靠近所述衬底基板的一侧，所述第二保护层的折射率小于所述第一保护层的折射率，所述第二保护层在所述衬底基板的正投影与所述发光元件的发光区域没有交叠，所述第一保护层在所述衬底基板的正投影覆盖所述第二保护层在所述衬底基板的正投影。
  9. 根据权利要求1至8中任一项所述的显示面板，其中，所述显示结构层包括阳极层，所述阳极层包括所述发光元件的第一发光单元的第一阳极和第二发光单元的第二阳极，所述第一阳极和第二阳极均与所述像素电路电连接，所述第一阳极和所述第二阳极相互隔离；所述第一阳极和所述第二阳极所在平面齐平，或者，所述第二阳极位于所述第一阳极远离所述衬底基板的一侧。
  10. 根据权利要求1至9中任一项所述的显示面板，其中，所述显示结构层包括：阳极层以及位于所述阳极层远离所述衬底基板一侧的像素定义层，所述像素定义层设置有暴露出所述阳极层的至少部分表面的多个像素开口，所述像素定义层为黑色。
  11. 根据权利要求1至10中任一项所述的显示面板，其中，所述至少一个子像素的发光元件的第一发光单元和第二发光单元之间的间距，小于相邻的出射不同颜色光的子像素的发光元件之间的间距。
  12. 根据权利要求1至11中任一项所述的显示面板，其中，所述多个子像素的发光元件阵列排布，出射相同颜色光的子像素的发光元件的第一发光单元和第二发光单元沿第一方向交替排布，且沿第二方向交替排布，所述第一方向和所述第二方向交叉。
  13. 根据权利要求1至12中任一项所述的显示面板，其中，所述像素电路至少包括：数据写入子电路、存储子电路、驱动子电路和控制子电路；
    所述数据写入子电路与数据线、第一扫描线和所述驱动子电路电连接，配置为在所述第一扫描线的控制下，向所述驱动子电路提供所述数据线传输的数据信号；
    所述驱动子电路与所述数据写入子电路、所述存储子电路、所述控制子电路和所述发光元件的第一发光单元电连接，配置为在数据信号的控制下，驱动所述第一发光单元发光；
    所述控制子电路与第二扫描线、所述驱动子电路、所述发光元件的第一发光单元和第二发光单元电连接，配置为在所述第二扫描线的控制下，控制所述第二发光单元随同所述第一发光单元发光。
  14. 根据权利要求13所述的显示面板，其中，所述控制子电路包括：第一控制晶体管；所述第一控制晶体管的栅极与所述第二扫描线电连接，第一极与所述第一发光单元电连接，第二极与所述第二发光单元电连接。
  15. 根据权利要求1所述的显示面板，其中，所述至少一个子像素的像素电路配置为在防窥显示模式下仅驱动所述第二发光单元发光，或者分别驱动所述第一发光单元和所述第二发光单元发光；在分享显示模式下驱动所述第二发光单元随同所述第一发光单元发光。
  16. 根据权利要求15所述的显示面板，还包括：位于所述显示结构层的出光侧的阻光层，所述阻光层包括至少一个阻光部，所述阻光部在所述衬底基板的正投影覆盖所述第二发光单元的发光区域在所述衬底基板的正投影。
  17. 根据权利要求16所述的显示面板，其中，所述多个子像素包括出射第一颜色光的第一子像素、出射第二颜色光的第二子像素以及出射第三颜色光的第三子像素；在所述防窥显示模式下，所述第一子像素、所述第二子像素和所述第三子像素的发光元件的第二发光单元均被配置为发光。
  18. 根据权利要求15至17中任一项所述的显示面板，其中，所述像素电路至少包括：数据写入子电路、存储子电路、驱动子电路和控制子电路；
    所述数据写入子电路与数据线、第一扫描线和所述驱动子电路电连接，配置为在所述第一扫描线的控制下，向所述驱动子电路提供所述数据线传输的数据信号；
    所述驱动子电路与所述数据写入子电路、所述存储子电路、所述控制子电路和所述发光元件的第一发光单元电连接，配置为在数据信号的控制下，驱动所述第一发光单元发光；
    所述控制子电路与第二扫描线、第一电源线、所述驱动子电路、所述发光元件的第一发光单元和第二发光单元电连接，配置为在所述第二扫描线的控制下，控制所述第二发光单元随同所述第一发光单元发光，或者，驱动所述第二发光单元发光。
  19. 根据权利要求18所述的显示面板，其中，所述控制子电路包括：第一控制晶体管和第二控制晶体管；所述第一控制晶体管的栅极与所述第二扫描线电连接，第一极与所述第一发光单元电连接，第二极与所述第二发光单元电连接；所述第二控制晶体管的栅极与所述第二扫描线电连接，第一极与所述第一电源线电连接，第二极与所述第二发光单元电连接；所述第二控制晶体管和所述第一控制晶体管的晶体管类型不同。
  20. 一种显示装置，包括如权利要求1至19中任一项所述的显示面板。
  21. 一种显示面板的制备方法，用于制备如权利要求1至19中任一项所述的显示面板，所述制备方法包括：
    在衬底基板形成显示结构层，所述显示结构层包括多个子像素；所述多个子像素中的至少一个子像素包括：像素电路以及与所述像素电路电连接的发光元件，所述发光元件包括：第一发光单元和第二发光单元；所述第一发光单元的发光区域与所述第二发光单元的发光区域相互隔离；所述像素电路配置为在防窥显示模式下驱动所述第一发光单元和所述第二发光单元中的至少之一发光。
PCT/CN2022/130594 2022-11-08 2022-11-08 显示面板及其制备方法、显示装置 WO2024098247A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/130594 WO2024098247A1 (zh) 2022-11-08 2022-11-08 显示面板及其制备方法、显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/130594 WO2024098247A1 (zh) 2022-11-08 2022-11-08 显示面板及其制备方法、显示装置

Publications (1)

Publication Number Publication Date
WO2024098247A1 true WO2024098247A1 (zh) 2024-05-16

Family

ID=91031728

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/130594 WO2024098247A1 (zh) 2022-11-08 2022-11-08 显示面板及其制备方法、显示装置

Country Status (1)

Country Link
WO (1) WO2024098247A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108897169A (zh) * 2018-07-25 2018-11-27 京东方科技集团股份有限公司 发光模组及其控制方法、显示装置
CN214226938U (zh) * 2021-01-07 2021-09-17 昆山龙腾光电股份有限公司 一种防窥显示面板
CN114333609A (zh) * 2021-12-31 2022-04-12 厦门天马微电子有限公司 显示面板和显示装置
CN115241397A (zh) * 2022-07-08 2022-10-25 京东方科技集团股份有限公司 一种显示面板及显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108897169A (zh) * 2018-07-25 2018-11-27 京东方科技集团股份有限公司 发光模组及其控制方法、显示装置
CN214226938U (zh) * 2021-01-07 2021-09-17 昆山龙腾光电股份有限公司 一种防窥显示面板
CN114333609A (zh) * 2021-12-31 2022-04-12 厦门天马微电子有限公司 显示面板和显示装置
CN115241397A (zh) * 2022-07-08 2022-10-25 京东方科技集团股份有限公司 一种显示面板及显示装置

Similar Documents

Publication Publication Date Title
US20220376024A1 (en) Display Substrate and Manufacturing Method Therefor, and Display Apparatus
US9299949B2 (en) Display panel and display device
WO2022037055A1 (zh) 显示面板及显示装置
KR20220129999A (ko) 디스플레이 기판 및 디스플레이 디바이스
US20200321409A1 (en) Display panel, display device and method for driving display panel
WO2022056907A1 (zh) 显示基板及显示装置
US20210391402A1 (en) Display Substrate, Preparation Method Therefor and Display Apparatus
US11961471B2 (en) Display substrate and display device
US20230030891A1 (en) Display substrate and display device
WO2023028944A1 (zh) 显示基板及显示装置
US12016232B2 (en) Display substrate and preparation method thereof, and display apparatus
WO2022226994A1 (zh) 显示面板和显示装置
WO2023246379A1 (zh) 显示基板及其制备方法、显示装置
WO2023020441A1 (zh) 显示基板及显示装置
WO2024098247A1 (zh) 显示面板及其制备方法、显示装置
WO2022174420A1 (zh) 显示面板和显示装置
CN118318262A (zh) 显示面板及其制备方法、显示装置
WO2023016335A1 (zh) 显示基板及显示装置
US20230232672A1 (en) Display substrate, method for manufacturing the same and display device
WO2024000317A9 (zh) 显示面板及显示装置
WO2024113224A1 (zh) 显示面板和显示装置
WO2022226801A1 (zh) 显示基板及其制备方法、显示装置
WO2023283768A1 (zh) 显示基板及其制备方法、显示装置
WO2023184163A1 (zh) 显示基板及显示装置
WO2023000215A1 (zh) 显示基板及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22964723

Country of ref document: EP

Kind code of ref document: A1