WO2022193712A1 - 显示面板、显示装置 - Google Patents

显示面板、显示装置 Download PDF

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Publication number
WO2022193712A1
WO2022193712A1 PCT/CN2021/131784 CN2021131784W WO2022193712A1 WO 2022193712 A1 WO2022193712 A1 WO 2022193712A1 CN 2021131784 W CN2021131784 W CN 2021131784W WO 2022193712 A1 WO2022193712 A1 WO 2022193712A1
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WO
WIPO (PCT)
Prior art keywords
light
emitting unit
base substrate
pixel
sub
Prior art date
Application number
PCT/CN2021/131784
Other languages
English (en)
French (fr)
Inventor
陈义鹏
石领
刘珂
卢辉
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/922,508 priority Critical patent/US20230269985A1/en
Publication of WO2022193712A1 publication Critical patent/WO2022193712A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/02—Constructional features of telephone sets
    • H04M1/0202—Portable telephone sets, e.g. cordless phones, mobile phones or bar type handsets
    • H04M1/026—Details of the structure or mounting of specific components
    • H04M1/0266—Details of the structure or mounting of specific components for a display module assembly
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • a display panel generally includes a high-pixel area and a low-pixel area, and the area where the low-pixel area is located can be used to integrate sensor devices such as cameras and earpieces.
  • the display panel is generally only provided with light emitting units in the low pixel area, while the pixel driving circuit for driving the light emitting units in the low pixel area is arranged in the circuit integration area between the high pixel area and the low pixel area, thereby increasing the low The transmittance of the pixel area.
  • the circuit integration area in the display panel may form a non-display area.
  • a display panel including a first display area and a second display area, the display panel further includes: a plurality of first pixel islands and a plurality of transparent bridge line segments, The first pixel island is located in the first display area, and the first pixel island includes: at least one first light-emitting unit, at least one first pixel driving circuit, a plurality of first signal line segments, and the first pixel driving circuit is connected to The first light-emitting units are arranged in a one-to-one correspondence, and the first pixel driving circuit is configured to provide a driving current to the corresponding first light-emitting units.
  • a plurality of transparent bridge line segments are located in the first display area, and at least part of the transparent bridge line segments are used to connect first signal line segments in different first pixel islands through via holes.
  • the display panel further includes a base substrate, and the first pixel island is located on one side of the base substrate.
  • the plurality of first signal line segments include a first sub-signal line segment and a second sub-signal line segment, the first sub-signal line segment extends along a first direction on the orthographic projection of the base substrate; the second sub-signal line segment is on the substrate
  • the orthographic projection of the base substrate extends along a second direction, the first direction and the second direction intersecting.
  • the plurality of transparent bridging line segments include a first transparent bridging line segment and a second transparent bridging line segment, the first transparent bridging line segment includes a first sub transparent bridging line segment, and the first sub transparent bridging line segment is located in the first display area,
  • the first sub-transparent bridge line segments are used to connect the first sub-signal line segments in different first pixel islands through via holes.
  • the plurality of second transparent bridge line segments include second sub transparent bridge line segments, the second sub transparent bridge line segments are located in the first display area, and the second sub transparent bridge line segments are used to connect different first pixel islands through vias the second sub-signal segment in .
  • the display panel further includes a plurality of second light emitting units, a plurality of second pixel driving circuits, and a plurality of second signal line segments.
  • a plurality of second light-emitting units are located in the second display area; a plurality of second pixel driving circuits are located in the second display area, and a plurality of the second pixel driving circuits and the plurality of the second light-emitting units are located
  • the second pixel driving circuit is used to provide a driving current to the corresponding second light-emitting unit;
  • a plurality of second signal line segments are located in the second display area, and are used to provide the second pixel driving circuit with a driving current.
  • a signal; at least part of the transparent bridge line segment is used to connect the first signal line segment and the second signal line segment through a via hole.
  • the plurality of second signal line segments include: a third sub-signal line segment and a fourth sub-signal line segment, and the orthographic projection of the third sub-signal line segment on the base substrate is along the first Extending in one direction; the orthographic projection of the fourth sub-signal line segment on the base substrate extends along the second direction.
  • the plurality of first transparent bridging line segments further include third sub-transparent bridging line segments, the third sub-transparent bridging line segments are located in the first display area, and the third sub-transparent bridging line segments are used to connect the first sub-transparent bridging line segments through via holes
  • the plurality of second transparent bridge line segments further include a fourth sub-transparent bridge line segment, the fourth sub-transparent bridge line segment is located in the first display area, and the fourth sub-transparent bridge line segment is located in the first display area.
  • the bridge line segment is used to connect the second sub-signal line segment and the fourth sub-signal line segment through a via hole.
  • the interconnected first transparent bridge line segment and the first sub-signal line segment form a first extension line
  • the interconnected second transparent bridge line segment and the second sub-signal segment The signal line segment forms a second extension line; the first extension line is bent and extended on the orthographic projection of the base substrate, the first extension line is on the orthographic projection of the base substrate and the second extension line is on the The intersection point of the orthographic projection of the base substrate is located at the intersection of the orthographic projection of the second sub-signal line segment on the base substrate and the orthographic projection of the first transparent bridge line segment on the base substrate.
  • the interconnected first transparent bridge line segment and the first sub-signal line segment form a first extension line
  • the interconnected second transparent bridge line segment and the second sub-signal segment The signal line segment forms a second extension line; the second extension line is bent and extended on the orthographic projection of the base substrate, the first extension line is on the orthographic projection of the base substrate, and the second extension line is on the The intersection point of the orthographic projection of the base substrate is located at the intersection of the orthographic projection of the first sub-signal line segment on the base substrate and the orthographic projection of the second transparent bridge line segment on the base substrate.
  • first sub-signal line segments there are multiple first sub-signal line segments, and multiple second sub-signal line segments;
  • the multiple first sub-signal line segments include gate driving signal lines, enable One or more of a signal line, an initial signal line, and a reset signal line;
  • the plurality of second sub-signal line segments include one or more of a data line and a power supply line.
  • the first pixel island includes a first connection line; in the first pixel island, the first sub-signal line segment includes a gate driving signal line and a reset signal line, and the gate drive signal line and the reset signal line with the same timing signal are connected through the first connection line; the gate drive signal line and the reset signal line connected through the first connection line Among the lines, only one signal line is connected to other corresponding signal lines through the first transparent bridge line segment.
  • the first pixel island includes a second connection line; in the first pixel island, the first sub-signal line segment includes n initial signal lines, where n is greater than 1 A positive integer of , the n initial signal lines in the first pixel island are electrically connected through the second connection line; among the n initial signal lines connected by the second connection line, there are m initial signal lines The line is connected to other corresponding signal lines through the first transparent bridge line segment, wherein m is a positive integer less than or equal to n and greater than 0.
  • the display panel further includes: a base substrate, a first pixel driving circuit, and a second pixel driving circuit, where the first pixel driving circuit is located in the first display area; the second pixel driving circuit The circuit is located in the second display area.
  • the orthographic projection area of the first pixel driving circuit on the base substrate is smaller than the orthographic projection area of the second pixel driving circuit on the base substrate.
  • the display panel further includes: a base substrate, a first pixel driving circuit, and a second pixel driving circuit, where the first pixel driving circuit is located in the first display area; the second pixel driving circuit The circuit is located in the second display area.
  • the gap between the orthographic projections of the adjacent two first pixel driving circuits on the base substrate is smaller than the distance between the orthographic projections of the adjacent two second pixel driving circuits on the base substrate. gap between.
  • the display panel further includes a base substrate, and the first pixel island is located on one side of the base substrate; the first pixel island includes at least one first light-emitting unit and At least one first pixel driving circuit corresponding to the first light-emitting unit, the first pixel driving circuit is used to provide a driving current to the first light-emitting unit corresponding to it; wherein, in the same first pixel island Among them, there is at least one orthographic projection of the first light-emitting unit on the base substrate that at least partially overlaps with the orthographic projection of the corresponding first pixel driving circuit on the base substrate.
  • the display panel further includes: a plurality of second light-emitting units, and a plurality of second pixel driving circuits corresponding to the second light-emitting units one-to-one, the second pixel driving circuits The circuit is used to provide a driving current to the corresponding second light-emitting unit;
  • the plurality of second light-emitting units include: a first R light-emitting unit, a first G light-emitting unit, and a first B light-emitting unit; wherein, the first R light-emitting unit
  • the light-emitting unit, the first G light-emitting unit, and the first B light-emitting unit are alternately distributed in sequence along the same light-emitting unit row, and in the same light-emitting unit row, two along the column are arranged between the first R light-emitting unit and the first B light-emitting unit.
  • the first G light-emitting units distributed in the directions, in adjacent light-emitting unit rows, light-emitting units of the same color are located in different light-emitting unit columns, and in two light-emitting unit rows separated by a light-emitting unit row, light-emitting units of the same color are located in the same light-emitting unit row.
  • a row of light emitting units; the first pixel island includes: a second R light emitting unit, a second G light emitting unit, a third G light emitting unit, and a second B light emitting unit.
  • the second G light-emitting unit is located in the first light-emitting unit row, and the second R light-emitting unit and the second B light-emitting unit are located in the same first pixel island.
  • the second light emitting unit row is adjacently arranged, the third G light emitting unit is located in the third light emitting unit row, and the second light emitting unit row is located between the first light emitting unit row and the third light emitting unit row;
  • the second B light-emitting unit is located in the first light-emitting unit column, the second G light-emitting unit and the third G light-emitting unit are located in the second light-emitting unit column, the second R light-emitting unit is located in the third light-emitting unit column, and the The second light emitting cell column is located between the first light emitting cell column and the third light emitting cell column.
  • the second R light-emitting unit and the second G light-emitting unit are located in a first light-emitting unit row
  • the second B light-emitting unit is located in a second light-emitting unit row
  • the third light-emitting unit is located in a second light-emitting unit row.
  • the G light-emitting unit is located in the third light-emitting unit row, the second light-emitting unit row is located between the first light-emitting unit row and the third light-emitting unit row; the second R light-emitting unit is located in the first light-emitting unit column, The second B light-emitting unit is located in the second light-emitting unit column, the second G light-emitting unit and the third G light-emitting unit are located in the third light-emitting unit column, and the second light-emitting unit column is located in the first light-emitting unit column and between the third light-emitting unit columns.
  • the second R light-emitting unit, the second G light-emitting unit, and the second B light-emitting unit are located in a first light-emitting unit row, and the third G light-emitting unit is located in a second light-emitting unit row,
  • the first light-emitting unit row and the second light-emitting unit row are arranged adjacently;
  • the second R light-emitting unit is located in the first light-emitting unit column, the second G light-emitting unit is located in the second light-emitting unit column, and the second light-emitting unit is located in the second light-emitting unit column.
  • Two B light-emitting units are located in the third light-emitting unit column, and the third G light-emitting unit is located in the fourth light-emitting unit column, wherein the first light-emitting unit column, the second light-emitting unit column, the third light-emitting unit column, and the fourth light-emitting unit column
  • the cell columns are sequentially distributed in the row direction.
  • the second R light-emitting unit, the second G light-emitting unit, and the third G light-emitting unit are located in the first light-emitting unit row, and the second B light-emitting unit is located in the second light-emitting unit
  • the first light emitting unit row and the second light emitting unit row are arranged adjacent to each other; the second R light emitting unit is located in the first light emitting unit column, the second B light emitting unit is located in the second light emitting unit column, so
  • the second G light-emitting unit and the third G light-emitting unit are located in a third light-emitting unit column, and the second light-emitting unit column is located between the first light-emitting unit column and the third light-emitting unit column.
  • the display panel further includes: a base substrate and a color filter layer, the first pixel island is located on one side of the base substrate, and the first pixel island includes at least one the first light-emitting unit.
  • the color filter layer is located on the side of the first pixel island away from the base substrate; the color filter layer includes a plurality of first structure parts located in the first display area, and a plurality of the first structure parts are connected with the first structure part.
  • the first structure part includes: a first light-shielding part and a first light-filtering part, at least one opening is formed on the first light-shielding part, and the opening on the first light-shielding part is the same as that in the first pixel island.
  • the first light-emitting units are arranged in a one-to-one correspondence; the first filter portion is located in the opening of the first light-shielding portion, and the first filter portion covers the corresponding first light-emitting unit by orthographic projection on the base substrate Orthographic projection of the base substrate.
  • the display panel further includes: a plurality of second light emitting units located in the second display area
  • the color filter layer further includes a second structure located in the second display area part
  • the second structure part comprises: a second shading part and a second filter part, a plurality of openings are formed on the second shading part, the openings on the second shading part and the second light emitting unit One-to-one correspondence
  • the second filter portion is located in the opening of the second light-shielding portion, and the second filter portion is orthographically projected on the base substrate to cover the corresponding second light-emitting unit on the substrate. Orthographic projection of the base substrate.
  • the pixel density of the first display area is less than or equal to the pixel density of the second display area.
  • the display panel further includes: a base substrate and a second light emitting unit, the first pixel island is located on one side of the base substrate; the second light emitting unit is located on the first light emitting unit Two display areas; in light-emitting units of the same color, the orthographic projection area of the first light-emitting unit on the base substrate is less than or equal to the orthographic projection area of the second light-emitting unit on the base substrate.
  • a display device which includes: the above-mentioned display panel and a sensing device, the sensing device being directly opposite to a first display area of the display panel.
  • FIG. 1 is a schematic diagram of a partial structure of a display panel in the related art
  • FIG. 2 is a schematic structural diagram of an exemplary embodiment of a display panel of the present disclosure
  • Fig. 3 is a partial enlarged view in Fig. 2;
  • FIG. 4 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • FIG. 5 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • FIG. 6 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • FIG. 7 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • Fig. 8 is the structural layout of the active layer in Fig. 3;
  • FIG. 9 is a structural layout of the first gate layer in FIG. 3;
  • FIG. 10 is a structural layout of the second gate layer in FIG. 3;
  • FIG. 11 is a structural layout of the first source-drain layer in FIG. 3;
  • Fig. 12 is the structural layout of the transparent conductive layer in Fig. 3;
  • FIG. 13 is a structural layout of the second source-drain layer in FIG. 3;
  • FIG. 14 is a layout of the stacked structure of the active layer, the first gate layer, the second gate layer, the first source and drain layers, the transparent conductive layer, and the second active and drain layers in FIG. 3;
  • FIG. 15 is a schematic diagram of a circuit structure of a pixel driving circuit in an exemplary embodiment of a display panel of the present disclosure
  • FIG. 16 is a timing diagram of each node in a driving method of the pixel driving circuit of FIG. 15;
  • Fig. 17 is a partial enlarged view of the first pixel island in the C region in Fig. 3;
  • Fig. 18 is the structural layout of the active layer in Fig. 17;
  • FIG. 19 is a structural layout of the first gate layer in FIG. 17;
  • FIG. 20 is a structural layout of the second gate in FIG. 17;
  • FIG. 21 is a structural layout of the first source-drain layer in FIG. 17;
  • Fig. 22 is the structural layout of the transparent conductive layer in Fig. 17;
  • FIG. 23 is a structural layout of the second source-drain layer in FIG. 17;
  • FIG. 24 is a stacked layout of the active layer and the first gate layer in FIG. 17;
  • FIG. 25 is a stacked layout of the active layer, the first gate layer, and the second gate layer in FIG. 17;
  • FIG. 26 is a stacked layout of the active layer, the first gate layer, the second gate layer, and the first source and drain layers in FIG. 17;
  • FIG. 27 is a stacked layout of the active layer, the first gate layer, the second gate layer, the first source and drain layers, and the transparent conductive layer in FIG. 17;
  • FIG. 28 is a cross-sectional view of an exemplary embodiment of a display panel of the present disclosure taken along the dotted line D in FIG. 17 .
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • FIG. 1 it is a schematic diagram of a partial structure of a display panel in the related art.
  • the display panel includes a low pixel density region 01 and a circuit integration region 02 , and the circuit integration region 02 may be located between the high pixel density region (not shown) and the low pixel density region 01 .
  • a plurality of light emitting units 03 may be integrated in the low pixel density area 01
  • a plurality of pixel driving circuits 04 may be integrated in the circuit integration area 02 .
  • the pixel driving circuit 04 can be used to provide a driving current to the light-emitting unit 03 through the transmission line 05 .
  • the display panel may have greater light transmittance in the low pixel density region 01 .
  • the circuit integration area 02 does not emit light
  • the display panel will have a non-light emitting area in the circuit integration area 02, thereby affecting the display effect.
  • the integration density of the transmission line 05 is limited by the process, the diameter of the low pixel density region 01 cannot be too large.
  • FIG. 2 is a schematic structural diagram of an exemplary embodiment of the display panel of the present disclosure
  • FIG. 3 is a partial enlarged view of FIG. 2 .
  • the display panel includes a first display area 1 and a second display area 2, and the display panel may further include: a plurality of first pixel islands 3 and a plurality of transparent bridge line segments 5, and the first pixel islands 3 are located in the In the first display area 1, the first pixel island 3 may include a plurality of first signal line segments 41; a plurality of transparent bridge line segments 5 are located in the first display area 1, and at least part of the transparent bridge line segments 5 are used for passing through the The holes are connected to the first signal line segments 41 in different first pixel islands 3 .
  • Sensor devices such as a camera, an earpiece, and an infrared sensor can be correspondingly set at the location of the first display area.
  • the first pixel island may include at least one first light-emitting unit and at least one first pixel driving circuit, the first pixel driving circuit and the first light-emitting unit are arranged in a one-to-one correspondence, and the first pixel driving circuit It is used to provide a driving current to the corresponding first light-emitting unit.
  • the first signal line segment may include one or more of a data line, a power supply line, a gate driving signal line, an initial signal line, a reset signal line, and an enable signal line.
  • the transparent bridge wire segment 5 can be used to connect the same kind of signal signal wires.
  • the present disclosure arranges the first pixel driving circuit for driving the first light-emitting unit in the first display area, thereby avoiding the existence of a circuit integration area that does not emit light in the display panel;
  • the transparent bridge line segments in the area are connected to the first signal line segments on different pixel islands, so that the light transmittance of the first display area can be increased;
  • the diameter of the first display area in the display panel is not limited.
  • the display area is set to any image, such as circle, ellipse, rectangle, etc.
  • the display panel further includes a base substrate 0 , and the first pixel island 3 is located on one side of the base substrate 0 .
  • the plurality of first signal line segments 41 may include a first sub-signal line segment 411 and a second sub-signal line segment 412.
  • the orthographic projection of the first sub-signal line segment 411 on the base substrate 0 extends along the first direction X; the second sub-signal line segment 411 extends along the first direction X;
  • the orthographic projection of the sub-signal line segment 412 on the base substrate 0 extends along a second direction Y, and the first direction X and the second direction Y intersect.
  • the first direction may be a row direction
  • the second direction may be a row direction. for the column direction.
  • the plurality of transparent bridge line segments 5 may include a first transparent bridge line segment 51 and a second transparent bridge line segment 52
  • the first transparent bridge line segment 51 may include a first sub transparent bridge line segment 511
  • the first sub transparent bridge line segment 511 may Located in the first display area 1, the first sub-transparent bridge line segments 511 can be used to connect the first sub-signal line segments 411 in different first pixel islands through via holes.
  • the plurality of second transparent bridge line segments 52 may include second sub transparent bridge line segments 522, the second sub transparent bridge line segments 522 may be located in the first display area 1, and the second sub transparent bridge line segments 522 may be used to pass
  • the via holes connect the second sub-signal line segments 412 in different first pixel islands.
  • the display panel may further include a plurality of second light-emitting units 7 , a plurality of second pixel driving circuits, and a plurality of second signal line segments 42 .
  • a plurality of second light-emitting units 7 may be located in the second display area 2; a plurality of second pixel driving circuits are located in the second display area 2, and a plurality of the second pixel driving circuits and the plurality of the The two light-emitting units 7 are arranged in a one-to-one correspondence, and the second pixel driving circuit is used to provide a driving current to the corresponding second light-emitting unit 7 .
  • the orthographic projection area of the second light emitting unit on the base substrate may be equal to the orthographic projection area of the first light emitting unit on the base substrate.
  • a plurality of second signal line segments 42 are located in the second display area 2 for providing signals to the second pixel driving circuit. At least part of the transparent bridge line segment 5 is used to connect the first signal line segment 41 and the second signal line segment 42 through via holes.
  • the second signal line segment may include one or more of a data line, a power supply line, a gate driving signal line, an initial signal line, a reset signal line, and an enable signal line.
  • the transparent bridge line segment 5 can connect the first signal line segment 41 and the second signal line segment 42 for the same kind.
  • the plurality of second signal line segments 42 may include: a third sub-signal line segment 423 and a fourth sub-signal line segment 424 , and the orthographic projection of the third sub-signal line segment 423 on the base substrate 0 may be along the The first direction X extends; the orthographic projection of the fourth sub-signal line segment 424 on the base substrate 0 may extend along the second direction Y.
  • the plurality of first transparent bridge line segments 51 may further include third sub transparent bridge line segments 513, the third sub transparent bridge line segments 513 may be located in the first display area 1, and the third sub transparent bridge line segments 513 may be used for
  • the first sub-signal line segment 411 in the first display area 1 and the third sub-signal line segment 423 in the second display area are connected through via holes;
  • the plurality of second transparent bridge line segments 52 may also include a fourth sub-transparent bridge line segment 524, a fourth sub-transparent bridge line segment 524 may be located in the first display area 1, and the fourth sub-transparent bridge line segment 524 may be used to connect the second sub-signal line segment 412 and the fourth sub-signal through a via hole Line segment 424.
  • the pixel density of the first display area 1 may be smaller than the pixel density of the second display area 2, wherein the area of the first display area may be X, the first display area
  • the pixel density of the display area 1 is lower than that of the second display area 2, which can be understood as: the number of pixel units within the X area range in the second display area is smaller than the number of pixel units in the first display area.
  • the number of pixel units in the area X in the second display area may be four times the number of pixel units in the first display area.
  • the pixel density of the first display area 1 may also be equal to the pixel density of the second display area 2.
  • the pixel density of the first display area may be reduced by reducing the first pixel in the first display area.
  • the layout area of the circuit and the first light-emitting unit increases the light transmittance of the first display area. That is, in light-emitting units of the same color, the orthographic projection area of the first light-emitting unit on the base substrate may be smaller than the orthographic projection area of the second light-emitting unit on the base substrate.
  • the orthographic projections of the transparent bridge line segment, the first signal line segment, and the second signal line segment on the base substrate can be extended straight or bent.
  • the transparent bridge line segment may be located on the same conductive layer.
  • the first transparent bridge line segment 51 and the first sub-signal line segment 411 connected to each other may form a first extension line 61
  • the first extension line 61 can transmit signals on the first sub-signal line segment 411
  • the second transparent bridge line segment 52 and the second sub-signal line segment 412 connected to each other can form a second extension line 62
  • the second extension line 62 Signals on the second sub-signal line segment 412 can be transmitted.
  • the first extension line 61 can be bent and extended on the orthographic projection of the base substrate 0 , the first extension line 61 is on the orthographic projection of the base substrate and the second extension line 62 is on the base substrate
  • the intersection point of the orthographic projection is located at the intersection of the orthographic projection of the second sub-signal line segment 412 on the base substrate and the orthographic projection of the first transparent bridge line segment 51 on the base substrate.
  • This arrangement may make the transparent bridge line segments extending along the first direction X and the transparent bridge line segments extending along the second direction Y disjoint. It should be understood that, in other exemplary embodiments, the first extension line 61 may also extend straight on the orthographic projection of the base substrate 0 .
  • the interconnected first transparent bridge line segment and the first sub-signal line segment may form a first extension line
  • the interconnected second transparent bridge line segment and all The second sub-signal line segment can form a second extension line
  • the second extension line can be bent and extended on the orthographic projection of the base substrate
  • the first extension line is on the orthographic projection of the base substrate and the first extension line.
  • the intersection point of the orthographic projection of the two extension lines on the base substrate may be located at the intersection of the orthographic projection of the first sub-signal line segment on the base substrate and the orthographic projection of the second transparent bridge line segment on the base substrate.
  • the arrangement can also make the transparent bridging line segments extending in the first direction X and the transparent bridging line segments extending in the second direction Y disjoint. It should be understood that, in other exemplary embodiments, the second extension line may also extend along a straight line on the orthographic projection of the base substrate.
  • the plurality of second light-emitting units 7 may include: a first R light-emitting unit R1, a first G light-emitting unit G1, and a first B light-emitting unit B1; wherein, The first R light-emitting unit R1, the first G light-emitting unit G1, and the first B light-emitting unit B1 are alternately distributed along the same light-emitting unit row, and in the same light-emitting unit row, the first R light-emitting unit R1 and the first B light-emitting unit B1 There are two first G light-emitting units G1 distributed along the column direction.
  • the second light-emitting units in the second display area are distributed in an RGGB pixel structure. It should be understood that, in other exemplary embodiments, the second light-emitting units in the second display area may also be distributed in other pixel structures, such as Real RGB pixel structures.
  • At least one first light emitting unit in the first pixel island may include: a second R light emitting unit R2 , a second G light emitting unit G2 , and a third G light emitting unit Unit G3, second B light-emitting unit B2.
  • the second G light-emitting unit G2 may be located in the first light-emitting unit row, and the second R light-emitting unit R2 and the second B light-emitting unit B2 may emit light in the second light-emitting unit row.
  • the cell rows are arranged adjacent to each other, the third G light-emitting cell G3 may be located in a third light-emitting cell row, and the second light-emitting cell row may be located between the first light-emitting cell row and the third light-emitting cell row.
  • the second B light-emitting unit B2 may be located in the first light-emitting unit column
  • the second G light-emitting unit G2 and the third G light-emitting unit G3 may be located in the second light-emitting unit column
  • the second R light-emitting unit R2 may be located in the first light-emitting unit column.
  • the second light emitting unit column may be located between the first light emitting unit column and the third light emitting unit column.
  • the second G light emitting unit G2 and the third G light emitting unit G3 may be spaced by one light emitting unit row.
  • the first pixel island 3 may further include other numbers of light-emitting units, and the light-emitting units in the first pixel island 3 may also have other pixel structure arrangements.
  • FIG. 4 it is a schematic structural diagram of another exemplary embodiment of the display panel of the present disclosure.
  • the second R light-emitting unit R2 and the second G light-emitting unit G2 are located in the first light-emitting unit row
  • the second B light-emitting unit B2 is located in the second light-emitting unit row
  • the second light-emitting unit B2 is located in the second light-emitting unit row.
  • the three G light-emitting units G3 are located in the third light-emitting unit row, the second light-emitting unit row is located between the first light-emitting unit row and the third light-emitting unit row; the second R light-emitting unit R2 is located in the first light-emitting unit row cell column, the second B light-emitting unit B2 is located in the second light-emitting unit column, the second G light-emitting unit G2 and the third G light-emitting unit G3 are located in the third light-emitting unit column, and the second light-emitting unit column is located in the between the first light emitting unit column and the third light emitting unit column.
  • the second G light emitting unit G2 and the third G light emitting unit G3 may be spaced by one light emitting unit row.
  • the pixel driving circuits in the first pixel island are distributed in a two-by-two array.
  • the aperture ratio of the first display area can reach 71.5%, and the light transmittance can reach 38.55%.
  • FIG. 5 it is a schematic structural diagram of another exemplary embodiment of the display panel of the present disclosure.
  • the second R light-emitting unit R2, the second G light-emitting unit G2, and the second B light-emitting unit B2 may be located in the first light-emitting unit row, and the third G light-emitting unit G3 may be located in the second light-emitting unit row Unit row, the first light emitting unit row and the second light emitting unit row are arranged adjacently;
  • the second R light emitting unit R2 is located in the first light emitting unit column, and the second G light emitting unit G2 is located in the second light emitting unit
  • the second B light-emitting unit B2 is located in the third light-emitting unit column, the third G light-emitting unit G3 is located in the fourth light-emitting unit column, wherein the first light-emitting unit column, the second light-emitting unit column, the third light-emitting unit column.
  • the second G light emitting unit G2 and the third G light emitting unit G3 are arranged adjacently, that is, in the column direction, the second G light emitting unit G2 and the third G light emitting unit G3 are not spaced apart from the rows of light emitting units.
  • the pixel driving circuits in the first pixel island are sequentially distributed in the row direction.
  • the aperture ratio of the first display area can reach 72.04%, and the light transmittance can reach 38.84%.
  • FIG. 6 it is a schematic structural diagram of another exemplary embodiment of the display panel of the present disclosure.
  • the second R light-emitting unit R2, the second G light-emitting unit G2, and the third G light-emitting unit G3 are located in the first light-emitting unit row, wherein the second G light-emitting unit G2 and the third G light-emitting unit G3 are in the lining.
  • the area of the orthographic projection of the base substrate is small, and the second G light-emitting unit G2 and the third G light-emitting unit G3 may be considered to be located in the same light-emitting unit row.
  • the second B light-emitting unit B2 is located in the second light-emitting unit row, and the first light-emitting unit row and the second light-emitting unit row are arranged adjacently; the second R light-emitting unit R2 is located in the first light-emitting unit column, so The second B light-emitting unit B2 is located in the second light-emitting unit column, the second G light-emitting unit G2 and the third G light-emitting unit G3 are located in the third light-emitting unit column, and the second light-emitting unit column is located in the first light-emitting unit between the column and the third column of light emitting units.
  • the pixel driving circuits in the first pixel island are distributed in a two-by-two array.
  • the aperture ratio of the first display area can reach 75.67%, and the light transmittance can reach 40.8%.
  • the first pixel island 3 may include one RGGB pixel unit, and one RGGB pixel unit may include one R sub-pixel, two G sub-pixels, and one B sub-pixel. It should be understood that, in other exemplary embodiments, the first pixel island 3 may also include other numbers of pixel units, each pixel unit may also include other numbers of sub-pixel units, and the sub-pixel units in the same pixel unit It can also be arranged in other forms, for example, the pixel units in the first pixel island can be distributed in a Real RGB arrangement.
  • FIG. 7 it is a schematic structural diagram of another exemplary embodiment of the display panel of the present disclosure.
  • the display panel may further include a color filter layer 8, and the color filter layer 8 may be located on the side of the first pixel island 3 away from the base substrate 0;
  • a plurality of first structure parts 81 in the area, the plurality of first structure parts 81 are arranged in a one-to-one correspondence with a plurality of the first pixel islands 3, and the first structure parts 81 are covered by orthographic projection on the base substrate
  • the orthographic projection of the corresponding first pixel island 3 on the base substrate, and at least one side or corner of the first structure portion 81 on the orthographic projection of the base substrate is arc-shaped.
  • the first structure portion 81 may include: a first light-shielding portion 811 and a first filter portion 812, wherein the first light-shielding portion 811 may be formed of a light-shielding material layer, for example, the first light-shielding portion 811 may be made of black light resist layer.
  • the first filter part 812 may use a color filter film.
  • At least one opening is formed on the first light-shielding portion 811 , and the opening on the first light-shielding portion 811 is arranged in a one-to-one correspondence with the first light-emitting units in the first pixel island 3 ; the first filter portion 812 is located in the In the opening of the first light shielding portion 811, the orthographic projection of the first filter portion 812 on the base substrate may be completely coincident with the orthographic projection of the corresponding opening of the first light shielding portion 811 on the base substrate, and the The orthographic projection of the first filter portion 812 on the base substrate can cover the orthographic projection of the corresponding first light-emitting unit on the base substrate, and the color of the first filter portion 812 can be the same as the corresponding light emission.
  • the cells are the same color.
  • the conductive structure of the pixel driving circuit in the first pixel island can be shielded by the first structure portion 81 , thereby avoiding the glare phenomenon caused by the diffraction of the elongated leads in the pixel driving circuit.
  • the orthographic projection of the first structural portion 81 on the base substrate may be in the shape of a water drop. It should be understood that in other exemplary embodiments, the orthographic projection of the first structural portion 81 on the base substrate Other structures such as rounded rectangles are also possible.
  • the plurality of first structure parts 81 can be distributed at intervals from each other, so as to increase the transmittance of the first display area.
  • the first filter part 812 can prevent the display panel from reflecting light. It should be understood that, in other exemplary embodiments, the filter portion may not be provided in the opening in the first light shielding portion 811 , and the display panel may avoid light reflection through the polarizer.
  • the color filter layer 8 may further include a second structure portion 82 located in the second display area 2 , and the second structure portion 82 may include: a second light shielding part 821 and second filter part 822, wherein the second light shielding part 821 may be formed by a light shielding material layer, for example, the second light shielding part 821 may be formed by a black photoresist layer.
  • the second filter portion 822 may use a color filter film.
  • a plurality of openings are formed on the second light-shielding portion 821 , and the openings on the second light-shielding portion 821 are arranged in a one-to-one correspondence with the second light-emitting units; the second light-shielding portion 822 is located in the second light-shielding portion 821 In the opening, the orthographic projection of the second filter portion 822 on the base substrate may completely coincide with the orthographic projection of the corresponding opening on the second light shielding portion 821 on the base substrate, and the second filter portion 822 The orthographic projection on the base substrate may cover the orthographic projection of the corresponding second light-emitting unit on the base substrate.
  • the second light shielding portion 821 and the first light shielding portion 811 may be integrally formed, that is, the second light shielding portion 821 and the first light shielding portion 811 may be formed through a single patterning process.
  • the same-color filter parts in the first filter part 812 and the second filter part 822 may be formed by one patterning process.
  • the second structure portion 82 may be an integral structure, and the second structure portion 82 may cover the second display area. Similarly, the second filter portion 822 may also prevent the display panel from reflecting light.
  • the display panel may include a circuit layer for forming a pixel driving circuit, and the circuit layer may include an active layer, a first gate layer, a second gate layer, a first source/drain layer, a transparent conductive layer, and a second source/drain layer .
  • Figure 8 is the structural layout of the active layer in Figure 3
  • Figure 9 is the structural layout of the first gate layer in Figure 3
  • FIG. 12 is the structural layout of the transparent conductive layer in FIG. 3
  • FIG. 13 is the structural layout of the second source and drain layer in FIG. 3
  • Laminated structure layout of the active layer, the first gate layer, the second gate layer, the first source and drain layers, the transparent conductive layer, and the second source and drain layers are stacked in sequence.
  • other film layers may also be disposed between the above-mentioned adjacent film layers, for example, an insulating layer may be disposed between the above-mentioned adjacent film layers.
  • the first signal line segment 41 and the second signal line segment 42 may be located in the first source-drain layer or the second source-drain layer, and the transparent bridge line segment 5 may be located in the transparent conductive layer.
  • the above-mentioned active layer, first gate layer, second gate layer, first source/drain layer, transparent conductive layer, and second source/drain layer may form the above-mentioned first A pixel driving circuit 31 and a second pixel driving circuit 32 .
  • the area of the orthographic projection of the first pixel driving circuit 31 on the base substrate may be smaller than the area of the orthographic projection of the second pixel driving circuit 32 on the base substrate. This arrangement can reduce the light-shielding area of the first display area 1 by the first pixel driving circuit 31 , thereby improving the light transmittance of the first display area 1 .
  • the area of the orthographic projection of the pixel driving circuit on the substrate can be understood as the area of a partially circumscribed rectangle of the active layer in the pixel driving circuit, and the length and width of the circumscribed rectangle are parallel to the row and column directions respectively.
  • the circumscribed rectangle corresponding to the first pixel driving circuit 31 is A
  • the circumscribing rectangle corresponding to the second pixel driving circuit 32 is B.
  • the gap between the orthographic projections of two adjacent first pixel driving circuits 31 on the base substrate is smaller than that where two adjacent second pixel driving circuits 32 are located.
  • the gap between the orthographic projections of the base substrates For example, as shown in FIG. 14 , in the row direction, the gap between the orthographic projections of two adjacent first pixel driving circuits 31 on the base substrate is smaller than that between two adjacent second pixel driving circuits 32 in the The gap between the orthographic projections of the substrate substrate.
  • This arrangement can further reduce the layout area of the pixel driving circuit in the first pixel island, thereby increasing the light transmittance of the first display area.
  • the distance between adjacent pixel driving circuits in the row direction can be understood as the distance between adjacent edges of the above circumscribed rectangles of adjacent pixel driving circuits in the row direction.
  • the same first pixel island there are at least one orthographic projection of the first light-emitting unit on the base substrate and the corresponding first pixel driving circuit on the substrate
  • the orthographic projections of the base substrate are at least partially coincident.
  • This setting can increase the area of the light-transmitting area of the first display area, thereby increasing the light transmittance of the first display area. For example, as shown in FIG.
  • the orthographic projection of the second R light-emitting unit R2 on the base substrate at least partially overlaps with the orthographic projection of the corresponding first pixel driving circuit on the base substrate;
  • the second B The orthographic projection of the light-emitting unit B2 on the base substrate at least partially overlaps with the orthographic projection of the corresponding first pixel driving circuit on the base substrate;
  • the second G light-emitting unit G2 is on the positive side of the base substrate.
  • the projection is at least partially coincident with the orthographic projection of the corresponding first pixel driving circuit on the base substrate.
  • FIG. 15 it is a schematic diagram of a circuit structure of a pixel driving circuit in an exemplary embodiment of the display panel of the present disclosure.
  • both the first pixel driving circuit and the second pixel driving circuit may be of this circuit structure.
  • the pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C.
  • the first pole of the first transistor T1 is connected to the node N, the second pole is connected to the initial signal terminal Vinit, and the gate is connected to the reset signal terminal Re1; the first pole of the second transistor T2 is connected to the first pole of the driving transistor T3, and the second pole
  • the gate is connected to the gate driving signal terminal Gate; the gate of the driving transistor T3 is connected to the node N; the first pole of the fourth transistor T4 is connected to the data signal terminal Da, and the second pole is connected to the second pole of the driving transistor T3, The gate is connected to the gate driving signal terminal Gate;
  • the first pole of the fifth transistor T5 is connected to the first power supply signal terminal VDD, the second pole is connected to the second pole of the driving transistor T3, and the gate is connected to the enable signal terminal EM;
  • the sixth transistor The first pole of T6 is connected to the first pole of the driving transistor T3, the gate is connected to the enable signal terminal EM; the first pole of the seventh transistor T7 is connected to the initial signal terminal Vinit, the second pole is connected
  • the capacitor C is connected between the gate of the driving transistor T3 and the first power signal terminal VDD.
  • the pixel driving circuit may be connected to a light-emitting unit OLED for driving the light-emitting unit OLED to emit light, and the light-emitting unit OLED may be connected between the second pole of the sixth transistor T6 and the second power terminal VSS.
  • the transistors T1-T7 may all be P-type transistors.
  • FIG. 16 it is a timing diagram of each node in a driving method of the pixel driving circuit of FIG. 15 .
  • Gate represents the timing of the gate drive signal terminal Gate
  • Re1 represents the timing of the reset signal terminal Re1
  • Re2 represents the timing of the reset signal terminal Re2
  • EM represents the timing of the enable signal terminal EM
  • Da represents the timing of the data signal terminal Da.
  • the driving method of the pixel driving circuit may include a reset stage t1, a compensation stage t2, and a light-emitting stage t3.
  • the reset signal terminal Re1 outputs a low level signal
  • the first transistor T1 is turned on
  • the initial signal terminal Vinit inputs an initial signal to the node N.
  • the compensation stage t2 the reset signal terminal Re2 and the gate driving signal terminal Gate output a low-level signal, the fourth transistor T4, the second transistor T2, and the seventh transistor T7 are turned on, and the data signal terminal Da outputs a driving signal to the node N write voltage Vdata+Vth, where Vdata is the voltage of the driving signal, Vth is the threshold voltage of the driving transistor T3, and the initial signal terminal Vinit inputs the initial signal to the second pole of the sixth transistor T6.
  • Light-emitting stage t3 the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata+Vth stored in the capacitor C.
  • the driving transistor output current formula I ( ⁇ WCox/2L)(Vgs-Vth) 2 , where ⁇ is the carrier mobility; Cox is the gate capacitance per unit area, W is the channel width of the driving transistor, and L drives The length of the transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor.
  • the output current I ( ⁇ WCox/2L)(Vdata+Vth ⁇ Vdd ⁇ Vth) 2 of the driving transistor in the pixel driving circuit of the present disclosure.
  • the pixel driving circuit can avoid the influence of the threshold value of the driving transistor on its output current.
  • the structure of the first pixel island is described in detail below in this exemplary embodiment by using a partial enlarged view of the location of the first pixel island.
  • Figure 17 is a partial enlarged view of the first pixel island in the C area in Figure 3
  • Figure 18 is the structural layout of the active layer in Figure 17
  • Figure 19 is the first gate layer in Figure 17
  • 20 is the structural layout of the second gate in FIG. 17
  • FIG. 21 is the structural layout of the first source and drain layer in FIG. 17
  • FIG. 22 is the structural layout of the transparent conductive layer in FIG. 17
  • FIG. 17 is the structure layout of the second source and drain layer
  • FIG. 24 is the stacked layout of the active layer and the first gate layer in FIG. 17, and FIG. 25 is the active layer, the first gate layer, and the second gate in FIG. 17.
  • Layer stacking layout FIG.
  • FIG. 26 is the stacking layout of the active layer, the first gate layer, the second gate layer, and the first source and drain layers in FIG. 17
  • FIG. 27 is the active layer and the first gate in FIG. 17 .
  • the active layer may include a first active part 101 , a second active part 102 , a third active part 103 , a fourth active part 104 , a fifth active part 105 , The sixth active part 106 and the seventh active part 107 .
  • the first active part 101 is used to form the channel part of the first transistor T1
  • the second active part 102 is used to form the channel part of the second transistor T2
  • the third active part 103 is used to form the driving transistor T3
  • the fourth active part 104 is used to form the channel part of the fourth transistor T4
  • the fifth active part 105 is used to form the channel part of the fifth transistor T5
  • the sixth active part 106 is used to form the channel part of the fifth transistor T5.
  • the channel portion of the sixth transistor T6 and the seventh active portion 107 are used to form the channel portion of the seventh transistor T7.
  • the first gate layer may include a reset signal line Re, a gate driving signal line Gate, an enable signal line EM, and a conductive portion 203 .
  • the reset signal line Re, the gate driving signal line Gate, and the enable signal line EM may form the above-mentioned first sub-signal line segment.
  • the reset signal line Re can be used to provide the reset signal terminal Re1 and the reset signal terminal Re2 in FIG. 15. As shown in FIGS.
  • the first pixel island 3 includes three reset signal lines Re, and the reset signal in the middle position
  • the line Re may be used to provide the reset signal terminal Re2 in the pixel driving circuit of the upper row and the reset signal terminal Re1 of the pixel driving circuit of the next row in the first pixel island.
  • the gate driving signal line Gate can be used to provide the gate driving signal terminal in FIG. 15
  • the enable signal line EM can be used to provide the enable signal terminal in FIG. 15 .
  • the partial structure of the reset signal line may be used to form the gates of the first transistor T1 and the seventh transistor T7.
  • Part of the structure of the gate driving signal line Gate may be used to form the gates of the second transistor T2 and the fourth transistor T4.
  • Part of the structure of the enable signal line EM may form gates of the fifth transistor T5 and the sixth transistor T6.
  • the conductive portion 203 can be used to form the gate of the driving transistor T3 and an electrode of the capacitor C.
  • the second gate layer may include an initial signal line Vint and a conductive portion 301 , and the initial signal line Vint may be used to provide the initial signal terminal in FIG. 15 .
  • the conductive portion 301 may be used to form another electrode of the capacitor C. As shown in FIG. Wherein, an opening 3011 is formed on the conductive portion 301 .
  • the first source-drain layer may include a data line Da, a plurality of conductive parts 401 , a conductive part 402 , a conductive part 403 , a conductive part 404 , a conductive part 405 , and a conductive part 406 .
  • the data line Da can form the above-mentioned second sub-signal line segment, and the data line Da can be used to provide the data signal terminal in FIG. 15 .
  • the plurality of conductive parts 401 can be respectively connected to two ends of the reset signal line Re, two ends of the enable signal line EM, two ends of part of the gate driving signal line Gate, and part of the initial signal line through via holes (black squares in the figure).
  • the conductive part 402 may be used to connect the initial signal line Vinit and the active layer on one side of the first active part 101 through via holes respectively, so as to connect the second electrode of the first transistor T1 and the initial signal terminal.
  • the conductive part 403 may be used to connect the active layer on one side of the first active part 101 and the conductive part 203 through vias respectively, so as to connect the first electrode of the first transistor T1 and the gate of the driving transistor T3.
  • the via hole for connecting the conductive portion 403 and the conductive portion 203 penetrates through the opening 3011 on the conductive portion 301 to prevent the conductive portion 403 from being short-circuited with the conductive portion 301 .
  • the conductive portion 404 is used to connect the conductive portion 301 and the active layer on one side of the fifth active portion 105 through vias respectively, so as to connect the first electrode of the fifth transistor T5 and an electrode of the capacitor C.
  • the conductive part 405 may be used to connect the active layer on one side of the seventh active part 107 through a via hole, so as to connect the second electrode of the seventh transistor.
  • the conductive portion 406 is used to connect the initial signal line Vinit and the active layer on the side of the seventh active portion 107 through via holes respectively, so as to connect the first electrode of the seventh transistor T7 and the initial signal terminal.
  • the transparent conductive layer may include a plurality of first sub-transparent bridge line segments 511 , a plurality of second sub-transparent bridge line segments 522 , a conductive portion 501 and a conductive portion 502 .
  • the conductive portion 501 is connected to the conductive portion 404 through a via hole
  • the conductive portion 502 is connected to the conductive portion 405 through a via hole.
  • the plurality of first sub-transparent bridge line segments 511 can be respectively connected to the initial signal line, the gate driving signal line, the reset signal line, the enable signal line and other signal lines extending in the row direction through the conductive portion 401 .
  • the second sub-transparent bridge line segment 522 may be connected to the data signal line through the conductive portion 401 .
  • the second source-drain layer may include a power line VDD and a conductive portion 601.
  • the power line VDD may be connected to the second sub-transparent bridge line segment 522 through a via hole.
  • the power line VDD may be connected to a conductive portion through a via hole.
  • Section 501 is used to connect the first power supply terminal VDD in FIG. 15 with the fifth transistor T5 and an electrode of the capacitor.
  • the conductive part 601 can be connected to the conductive part 502 through a via hole, and the conductive part 601 can be used to connect the anode of the light emitting unit.
  • the power line VDD may form the above-mentioned second sub-signal line segment.
  • the first source-drain layer may further include a first connection line 407 .
  • the first connection line 407 can be respectively connected to the gate driving signal line Gate in the pixel driving circuit in the previous row and the reset signal line Re in the pixel driving circuit in the next row through the via hole, wherein the gate driving circuit in the pixel driving circuit in the previous row
  • the driving signal line Gate can provide a gate driving signal to the first transistor T1 in the pixel driving circuit of the upper row
  • the reset signal line Re in the pixel driving circuit of the next row can provide the gate driving signal to the seventh transistor T7 in the pixel driving circuit of the upper row.
  • the reset signal terminal Re2 and the gate driving signal terminal Gate have the same timing.
  • the pixel driving circuit in the previous row can provide the gate driving signal through the reset signal line Re in the next row, so that the pixel driving circuit in this row can drive
  • the gate driving signal line Gate in the circuit may not be connected with other signal lines through a transparent bridge line segment.
  • this setting can reduce the number of transparent bridge line segments in the first display area, thereby increasing the light transmittance of the first display area; on the other hand, this setting can increase the layout space of the first display area to facilitate layout design.
  • the first source-drain layer may further include second connection lines 408 , and the second connection lines 408 may be respectively connected to a plurality of initial signal lines Vinit in the first pixel island through via holes.
  • the initial signal lines Vinit may not be connected with other signal lines through transparent bridge line segments.
  • the first pixel island may include three initial signal lines Vinit, and one initial signal line Vinit in the middle may not be connected to other signal lines through a transparent bridge line segment.
  • this setting can reduce the transparent signal lines in the first display area, thereby increasing the light transmittance of the first display area; on the other hand, this setting can also reduce the impedance loading (RC loading) of the initial signal line Vinit.
  • RC loading impedance loading
  • the first pixel island may include one first sub-pixel driving circuit 311 in the first row and three second sub-pixel driving circuits 312 in the second row.
  • the first sub-pixel driving circuit 311 and the first sub-pixel driving circuit 311 The second sub-pixel driving circuits 312 located in the middle of the two rows are located in the same column.
  • the first pixel island may include three data lines Da, and the data lines Da located on both sides of the first pixel island may be bent and extended in the column direction, wherein the two data lines may be offset along the position of the first sub-pixel driving circuit 311 Bend.
  • the first pixel island may include three power supply lines VDD, and the power supply lines VDD located on both sides of the first pixel island may be bent and extended in the column direction, wherein the two power supply lines VDD may be biased along the direction of the first sub-pixel driving circuit 311 . Bent position.
  • This arrangement can reduce the area of the first pixel island, thereby increasing the light transmittance of the first display area.
  • the orthographic projections of the power supply line VDD and the data line Da on the same side of the first pixel island at least partially overlap, and this arrangement can further reduce the area of the first pixel island.
  • the display panel may further include: a buffer layer 801 , a first insulating layer 802 , a second insulating layer 803 , a dielectric layer 804 , a passivation layer 805 , a first planarization layer 806 , a second planarization layer 807 , and an anode layer 701 .
  • the passivation layer 805, the transparent conductive layer, the first flat layer 806, the second source/drain layer, the second flat layer 807, and the anode layer 701 may be stacked in sequence.
  • the first insulating layer 802 and the second insulating layer 803 may be silicon oxide layers, and the dielectric layer 804 may be silicon nitride layers. Both the passivation layer and the buffer layer can be silicon oxide layers.
  • the first gate layer, the second gate layer, the first source-drain layer, and the second source-drain layer can all be formed by at least one metal layer.
  • the first gate layer, the second gate layer, the first source-drain layer, and the second source-drain layer can all be formed by stacking the first titanium layer, the aluminum layer, and the second titanium layer in sequence.
  • the transparent conductive layer may be an indium tin oxide layer.
  • the base substrate may be formed of an insulating material, for example, the base substrate may include a first polyimide (PI) layer, a first silicon oxide (SiO) layer, an amorphous silicon layer, a second polyimide layer that are arranged in sequence (PI) layer, second silicon dioxide layer.
  • PI polyimide
  • SiO silicon oxide
  • PI polyimide
  • a plurality of power supply lines in the second source-drain layer may be connected to each other. Therefore, as shown in FIG. 3 , part of the power supply line VDD located in the second display area can be disconnected in the first display area.
  • this setting can reduce the impedance loading (RC loading) of the power line VDD; on the other hand, this setting can reduce the number of transparent bridge line segments in the first display area, thereby increasing the light transmittance of the first display area.
  • the present exemplary embodiment also provides a display device, which includes: the above-mentioned display panel and a sensing device, wherein the sensing device is directly opposite to the first display area of the display panel.
  • the display device may be a display device such as a mobile phone or a tablet computer.

Abstract

本公开涉及显示技术领域，提出一种显示面板、显示装置，显示面板包括第一显示区和第二显示区，显示面板还包括：多个第一像素岛、多条透明桥接线段，第一像素岛位于第一显示区，第一像素岛包括至少一个第一发光单元、至少一个第一像素驱动电路、多条透明桥接线段，第一像素驱动电路与第一发光单元一一对应设置，第一像素驱动电路用于向与其对应的第一发光单元提供驱动电流。多条透明桥接线段位于第一显示区，第一信号线段用于向第一像素驱动电路提供信号。至少部分透明桥接线段用于通过过孔连接不同第一像素岛中的第一信号线段。该显示面板的第一显示区具有较大的透光率。

Description

显示面板、显示装置
相关申请的交叉引用
本申请要求于2021年3月16日递交的、名称为《显示面板、显示装置》的中国专利申请第202110282322.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板、显示装置。
背景技术
相关技术中，显示面板一般包括高像素区和低像素区，低像素区所在区域可以用于集成摄像头、听筒等传感器件。相关技术中，显示面板一般仅在低像素区设置发光单元，同时将用于驱动低像素区中发光单元的像素驱动电路设置于高像素区和低像素区之间的电路集成区，从而增加低像素区的透过率。然而，该显示面板中的电路集成区会形成不显示区域。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
根据本公开的一个方面，提供一种显示面板，其中，所述显示面板包括第一显示区和第二显示区，所述显示面板还包括：多个第一像素岛、多条透明桥接线段，所述第一像素岛位于所述第一显示区，所述第一像素岛包括：至少一个第一发光单元、至少一个第一像素驱动电路、多条第一信号线段，第一像素驱动电路与所述第一发光单元一一对应设置，所述第一像素驱动电路用于向与其对应的所述第一发光单元提供驱动电流。多条透明桥接线段位于所述第一显示区，至少部分所述透明桥接线段用于通过过孔连接不同所述第一像素岛中的第一信号线段。
本公开一种示例性实施例中，所述显示面板还包括衬底基板，所述第一像素岛位于所述衬底基板的一侧。多条所述第一信号线段包括第一子信号线段、第二子信号线段，第一子信号线段在所述衬底基板的正投影沿第一方向延伸；第二子信号线段在所述衬底基板的正投影沿第二方向延伸，所述第一方向和所述第二方向相交。多条所述透明桥接线段包括第一透明桥接线段和第二透明桥接线段，所述第一透明桥接线段包括第一子透明桥接线段，第一子透明桥接线段，位于所述第一显示区，所述第一子透明桥接线段用于通过过孔连接不同第一像素岛中的第一子信号线段。多条所述第二透明桥接线段包括第二子透明桥接线 段，第二子透明桥接线段位于所述第一显示区，所述第二子透明桥接线段用于通过过孔连接不同第一像素岛中的第二子信号线段。
本公开一种示例性实施例中，所述显示面板还包括多个第二发光单元、多个第二像素驱动电路、多条第二信号线段。多个第二发光单元位于所述第二显示区；多个第二像素驱动电路位于所述第二显示区，多个所述第二像素驱动电路与所述多个所述第二发光单元一一对应设置，所述第二像素驱动电路用于向与其对应的第二发光单元提供驱动电流；多条第二信号线段位于所述第二显示区，用于向所述第二像素驱动电路提供信号；至少部分所述透明桥接线段用于通过过孔连接所述第一信号线段和所述第二信号线段。
本公开一种示例性实施例中，多条所述第二信号线段包括：第三子信号线段、第四子信号线段，第三子信号线段在所述衬底基板的正投影沿所述第一方向延伸；第四子信号线段在所述衬底基板的正投影沿所述第二方向延伸。多条所述第一透明桥接线段还包括第三子透明桥接线段，第三子透明桥接线段位于所述第一显示区，所述第三子透明桥接线段用于通过过孔连接所述第一子信号线段和所述第三子信号线段；多条所述第二透明桥接线段还包括第四子透明桥接线段，第四子透明桥接线段位于所述第一显示区，所述第四子透明桥接线段用于通过过孔连接所述第二子信号线段和所述第四子信号线段。
本公开一种示例性实施例中，相互连接的所述第一透明桥接线段和所述第一子信号线段形成第一延伸线，相互连接的所述第二透明桥接线段和所述第二子信号线段形成第二延伸线；所述第一延伸线在所述衬底基板正投影弯折延伸，所述第一延伸线在所述衬底基板正投影和所述第二延伸线在所述衬底基板正投影的交点位于所述第二子信号线段在所述衬底基板正投影和所述第一透明桥接线段在所述衬底基板正投影的交点上。
本公开一种示例性实施例中，相互连接的所述第一透明桥接线段和所述第一子信号线段形成第一延伸线，相互连接的所述第二透明桥接线段和所述第二子信号线段形成第二延伸线；所述第二延伸线在所述衬底基板正投影弯折延伸，所述第一延伸线在所述衬底基板正投影和所述第二延伸线在所述衬底基板正投影的交点位于所述第一子信号线段在所述衬底基板正投影和所述第二透明桥接线段在所述衬底基板正投影的交点上。
本公开一种示例性实施例中，所述第一子信号线段为多条，所述第二子信号线段为多条；多条所述第一子信号线段包括栅极驱动信号线、使能信号线、初始信号线、复位信号线中的一种或多种；多条所述第二子信号线段包括数据线、电源线中的一种或多种。
本公开一种示例性实施例中，至少部分所述第一像素岛包括第一连接线；在该第一像素岛中，所述第一子信号线段包括栅极驱动信号线和复位信号线，且具有同一时序信号的 所述栅极驱动信号线和所述复位信号线通过所述第一连接线连接；在通过所述第一连接线连接的所述栅极驱动信号线和所述复位信号线中，仅有一条信号线通过所述第一透明桥接线段和与其对应的其他信号线连接。
本公开一种示例性实施例中，至少部分所述第一像素岛包括第二连接线；在该第一像素岛中，所述第一子信号线段包括n条初始信号线，n为大于1的正整数，该第一像素岛中的n条初始信号线通过所述第二连接线电连接；在通过所述第二连接线连接的n条所述初始信号线中，存在m条初始信号线通过所述第一透明桥接线段和与其对应的其他信号线连接，其中，m为小于等于n且大于0的正整数。
本公开一种示例性实施例中，所述显示面板还包括：衬底基板、第一像素驱动电路、第二像素驱动电路，第一像素驱动电路位于所述第一显示区；第二像素驱动电路位于所述第二显示区。其中，所述第一像素驱动电路在所述衬底基板正投影的面积小于所述第二像素驱动电路在所述衬底基板正投影的面积。
本公开一种示例性实施例中，所述显示面板还包括：衬底基板、第一像素驱动电路、第二像素驱动电路，第一像素驱动电路位于所述第一显示区；第二像素驱动电路位于所述第二显示区。其中，在至少一个方向上，相邻两所述第一像素驱动电路在所述衬底基板正投影之间的间隙小于相邻两所述第二像素驱动电路在所述衬底基板正投影之间的间隙。
本公开一种示例性实施例中，所述显示面板还包括衬底基板，所述第一像素岛位于所述衬底基板的一侧；所述第一像素岛包括至少一个第一发光单元和与所述第一发光单元对应的至少一个第一像素驱动电路，所述第一像素驱动电路用于向与其对应的所述第一发光单元提供驱动电流；其中，在同一所述第一像素岛中，至少存在一个所述第一发光单元在所述衬底基板的正投影和与其对应的所述第一像素驱动电路在所述衬底基板的正投影至少部分重合。
本公开一种示例性实施例中，所述显示面板还包括：多个第二发光单元，以及与所述第二发光单元一一对应的多个第二像素驱动电路，所述第二像素驱动电路用于向与其对应的所述第二发光单元提供驱动电流；多个所述第二发光单元包括：第一R发光单元、第一G发光单元、第一B发光单元；其中，第一R发光单元、第一G发光单元、第一B发光单元沿同一发光单元行依次交替分布，且在同一发光单元行中，第一R发光单元和第一B发光单元之间设置有两个沿列方向分布的第一G发光单元，在相邻发光单元行中，同一颜色的发光单元位于不同的发光单元列，在相间隔一发光单元行的两发光单元行中，同一颜色的发光单元位于同一发光单元列；所述第一像素岛包括：第二R发光单元、第二G发光 单元、第三G发光单元、第二B发光单元。
本公开一种示例性实施例中，在同一所述第一像素岛中，所述第二G发光单元位于第一发光单元行，所述第二R发光单元和所述第二B发光单元在第二发光单元行上相邻设置，所述第三G发光单元位于第三发光单元行，所述第二发光单元行位于所述第一发光单元行和所述第三发光单元行之间；所述第二B发光单元位于第一发光单元列，所述第二G发光单元和第三G发光单元位于第二发光单元列，所述第二R发光单元位于第三发光单元列，所述第二发光单元列位于所述第一发光单元列和所述第三发光单元列之间。
本公开一种示例性实施例中，所述第二R发光单元和所述第二G发光单元位于第一发光单元行，所述第二B发光单元位于第二发光单元行，所述第三G发光单元位于第三发光单元行，所述第二发光单元行位于所述第一发光单元行和所述第三发光单元行之间；所述第二R发光单元位于第一发光单元列，所述第二B发光单元位于第二发光单元列，所述第二G发光单元和第三G发光单元位于第三发光单元列，所述第二发光单元列位于所述第一发光单元列和所述第三发光单元列之间。
本公开一种示例性实施例中，所述第二R发光单元、第二G发光单元、第二B发光单元位于第一发光单元行，所述第三G发光单元位于第二发光单元行，所述第一发光单元行和所述第二发光单元行相邻设置；所述第二R发光单元位于第一发光单元列，所述第二G发光单元位于第二发光单元列，所述第二B发光单元位于第三发光单元列，所述第三G发光单元位于第四发光单元列，其中，所述第一发光单元列、第二发光单元列、第三发光单元列、第四发光单元列在行方向上依次分布。
本公开一种示例性实施例中，所述第二R发光单元、所述第二G发光单元、第三G发光单元位于第一发光单元行，所述第二B发光单元位于第二发光单元行，所述第一发光单元行和所述第二发光单元行相邻设置；所述第二R发光单元位于第一发光单元列，所述第二B发光单元位于第二发光单元列，所述第二G发光单元、第三G发光单元位于第三发光单元列，所述第二发光单元列位于所述第一发光单元列和所述第三发光单元列之间。
本公开一种示例性实施例中，所述显示面板还包括：衬底基板、彩膜层，所述第一像素岛位于所述衬底基板的一侧，所述第一像素岛包括至少一个第一发光单元。所述彩膜层位于所述第一像素岛背离所述衬底基板的一侧；所述彩膜层包括位于第一显示区的多个第一结构部，多个所述第一结构部与多个所述第一像素岛一一对应设置，所述第一结构部在所述衬底基板正投影覆盖与其对应的所述第一像素岛在所述衬底基板的正投影，且所述第一结构部在所述衬底基板正投影的至少一边或一角为弧形。所述第一结构部包括：第一遮 光部、第一滤光部，所述第一遮光部上形成有至少一个开口，所述第一遮光部上的开口与所述第一像素岛中的第一发光单元一一对应设置；第一滤光部位于所述第一遮光部的开口内，所述第一滤光部在所述衬底基板正投影覆盖与其对应的所述第一发光单元在所述衬底基板的正投影。
本公开一种示例性实施例中，所述显示面板还包括：多个位于所述第二显示区的第二发光单元，所述彩膜层还包括位于所述第二显示区的第二结构部，所述第二结构部包括：第二遮光部、第二滤光部，所述第二遮光部上形成有多个开口，所述第二遮光部上的开口与所述第二发光单元一一对应设置；第二滤光部位于所述第二遮光部的开口内，所述第二滤光部在所述衬底基板正投影覆盖与其对应的所述第二发光单元在所述衬底基板的正投影。
本公开一种示例性实施例中，所述第一显示区的像素密度小于等于第二显示区的像素密度。
本公开一种示例性实施例中，所述显示面板还包括：衬底基板、第二发光单元，所述第一像素岛位于所述衬底基板的一侧；第二发光单元位于所述第二显示区；在同一颜色的发光单元中，所述第一发光单元在所述衬底基板的正投影面积小于等于所述第二发光单元在所述衬底基板的正投影面积。
根据本公开的一个方面，提供一种显示装置，该显示装置包括：上述的显示面板和传感器件，所述传感器件与所述显示面板的第一显示区正对。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中显示面板的部分结构示意图；
图2为本公开显示面板一种示例性实施例的结构示意图；
图3为图2中的局部放大图；
图4为本公开显示面板另一种示例性实施例的结构示意图；
图5为本公开显示面板另一种示例性实施例的结构示意图；
图6为本公开显示面板另一种示例性实施例的结构示意图；
图7为本公开显示面板另一种示例性实施例的结构示意图；
图8为图3中有源层的结构版图；
图9为图3中第一栅极层的结构版图；
图10为图3中第二栅极层的结构版图；
图11为图3中第一源漏层的结构版图；
图12为图3中透明导电层的结构版图；
图13为图3中第二源漏层的结构版图；
图14为图3中有源层、第一栅极层、第二栅极层、第一源漏层、透明导电层、第二有源漏层的层叠结构版图；
图15为本公开显示面板一种示例性实施例中像素驱动电路的电路结构示意图；
图16为图15像素驱动电路一种驱动方法中各节点的时序图；
图17为图3中C区域中第一像素岛的局部放大图；
图18为图17中有源层的结构版图；
图19为图17中第一栅极层的结构版图；
图20为图17中第二栅极的结构版图；
图21为图17中第一源漏层的结构版图；
图22为图17中透明导电层的结构版图；
图23为图17中第二源漏层的结构版图；
图24为图17中有源层和第一栅极层的层叠版图；
图25为图17中有源层、第一栅极层、第二栅极层的层叠版图；
图26为图17中有源层、第一栅极层、第二栅极层、第一源漏层的层叠版图；
图27为图17中有源层、第一栅极层、第二栅极层、第一源漏层、透明导电层的层叠版图；
图28为本公开显示面板一种示例性实施例沿图17中虚线D的剖视图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
如图1所示，为相关技术中显示面板的部分结构示意图。该显示面板包括低像素密度区01和电路集成区02，电路集成区02可以位于高像素密度区(未画出)和低像素密度区01之间。低像素密度区01中可以集成有多个发光单元03，电路集成区02中可以集成有多个像素驱动电路04。其中，像素驱动电路04可以用于通过传输线05向发光单元03提供驱动电流。该显示面板在低像素密度区01可以具有较大的透光率。然而，由于电路集成区02不发光，因而该显示面板会在电路集成区02出现不发光区域，从而影响显示效果。此外，由于传输线05的集成密度受到工艺制程的限制，低像素密度区01的直径不能过大。
基于此，本示例性实施例提供一种显示面板，如图2、3所示，图2为本公开显示面板一种示例性实施例的结构示意图，图3为图2中的局部放大图。所述显示面板包括第一显示区1和第二显示区2，所述显示面板还可以包括：多个第一像素岛3、多条透明桥接线段5，所述第一像素岛3位于所述第一显示区1，所述第一像素岛3可以包括多条第一信号线段41；多条透明桥接线段5位于所述第一显示区1，至少部分所述透明桥接线段5用于通过过孔连接不同所述第一像素岛3中的第一信号线段41。第一显示区所在位置可以对应设置摄像头、听筒、红外传感器等传感器件。
本示例性实施例中，所述第一像素岛可以包括至少一个第一发光单元和至少一个第一像素驱动电路，第一像素驱动电路和第一发光单元一一对应设置，第一像素驱动电路用于向与其对应的第一发光单元提供驱动电流。第一信号线段可以包括数据线、电源线、栅极驱动信号线、初始信号线、复位信号线、使能信号线中的一种或多种。透明桥接线段5可以用于连接同种信号信号线。一方面，本公开将用于驱动第一发光单元的第一像素驱动电路设置于第一显示区，从而避免了显示面板存在不发光的电路集成区；另一方面，本公开通过位于第一显示区的透明桥接线段连接不同像素岛上的第一信号线段，从而可以增加第一显示区的透光率；再一方面，该显示面板中第一显示区的直径不受限制，此外，第一显示区设置为任意图像，例如圆形、椭圆形、矩形等。
本示例性实施例中，如图3所示，所述显示面板还包括衬底基板0，所述第一像素岛3位于所述衬底基板0的一侧。多条所述第一信号线段41可以包括第一子信号线段411、第二子信号线段412，第一子信号线段411在所述衬底基板0的正投影沿第一方向X延伸；第二子信号线段412在所述衬底基板0的正投影沿第二方向Y延伸，所述第一方向X和所述第二方向Y相交，例如，第一方向可以为行方向，第二方向可以为列方向。多条所述透明桥接线段5可以包括第一透明桥接线段51和第二透明桥接线段52，所述第一透明桥接线段51可以包括第一子透明桥接线段511，第一子透明桥接线段511可以位于所述第一显示区1，所述第一子透明桥接线段511可以用于通过过孔连接不同第一像素岛中的第一子信号线段411。多条所述第二透明桥接线段52可以包括第二子透明桥接线段522，第二子 透明桥接线段522可以位于所述第一显示区1，所述第二子透明桥接线段522可以用于通过过孔连接不同第一像素岛中的第二子信号线段412。
本示例性实施例中，如图2、3所示，所述显示面板还可以包括多个第二发光单元7、多个第二像素驱动电路、多条第二信号线段42。多个第二发光单元7可以位于所述第二显示区2；多个第二像素驱动电路位于所述第二显示区2，多个所述第二像素驱动电路与所述多个所述第二发光单元7一一对应设置，所述第二像素驱动电路用于向与其对应的第二发光单元7提供驱动电流。第二发光单元在衬底基板的正投影面积可以等于第一发光单元在衬底基板正投影的面积。多条第二信号线段42位于所述第二显示区2，用于向所述第二像素驱动电路提供信号。至少部分所述透明桥接线段5用于通过过孔连接所述第一信号线段41和所述第二信号线段42。其中，第二信号线段可以包括数据线、电源线、栅极驱动信号线、初始信号线、复位信号线、使能信号线中的一种或多种。透明桥接线段5可以连接用于同种的第一信号线段41和所述第二信号线段42。
如图3所示，多条所述第二信号线段42可以包括：第三子信号线段423、第四子信号线段424，第三子信号线段423在所述衬底基板0的正投影可以沿所述第一方向X延伸；第四子信号线段424在所述衬底基板0的正投影可以沿所述第二方向Y延伸。多条所述第一透明桥接线段51还可以包括第三子透明桥接线段513，第三子透明桥接线段513可以位于所述第一显示区1，所述第三子透明桥接线段513可以用于通过过孔连接第一显示区1中的第一子信号线段411和第二显示区中的第三子信号线段423；多条所述第二透明桥接线段52还可以包括第四子透明桥接线段524，第四子透明桥接线段524可以位于所述第一显示区1，所述第四子透明桥接线段524可以用于通过过孔连接所述第二子信号线段412和所述第四子信号线段424。
本示例性实施例中，如图3所示，所述第一显示区1的像素密度可以小于第二显示区2的像素密度，其中，第一显示区的面积可以为X，所述第一显示区1的像素密度小于第二显示区2的像素密度，可以理解为：第二显示区中X面积范围内的像素单元个数小于第一显示区中的像素单元个数。例如，第二显示区中X面积范围内的像素单元个数可以为第一显示区中像素单元个数的四倍。应该理解的是，在其他示例性实施例中，所述第一显示区1的像素密度还可以等于第二显示区2的像素密度，相应的，可以通过缩小第一显示区中第一像素驱动电路和第一发光单元的布图面积，增加第一显示区的透光率。即在同一颜色的发光单元中，所述第一发光单元在所述衬底基板的正投影面积可以小于所述第二发光单元在所述衬底基板的正投影面积。本公开中，透明桥接线段、第一信号线段、第二信号线段在衬底基板的正投影可以直线延伸也可以弯折延伸。
本示例性实施例中，透明桥接线段可以位于同一导电层，如图3所示，相互连接的所述第一透明桥接线段51和所述第一子信号线段411可以形成第一延伸线61，第一延伸线61能够传输第一子信号线段411上的信号，相互连接的所述第二透明桥接线段52和所述第二子信号线段412可以形成第二延伸线62，第二延伸线62能够传输第二子信号线段412 上的信号。所述第一延伸线61在所述衬底基板0正投影可以弯折延伸，所述第一延伸线61在所述衬底基板正投影和所述第二延伸线62在所述衬底基板正投影的交点位于所述第二子信号线段412在所述衬底基板正投影和所述第一透明桥接线段51在所述衬底基板正投影的交点上。该设置可以使得沿第一方向X延伸的透明桥接线段和沿第二方向Y延伸的透明桥接线段不相交。应该理解的是，在其他示例性实施例中，所述第一延伸线61在所述衬底基板0正投影也可以直线延伸。
应该理解的是，在其他示例性实施例中，相互连接的所述第一透明桥接线段和所述第一子信号线段可以形成第一延伸线，相互连接的所述第二透明桥接线段和所述第二子信号线段可以形成第二延伸线；所述第二延伸线在所述衬底基板正投影可以弯折延伸，所述第一延伸线在所述衬底基板正投影和所述第二延伸线在所述衬底基板正投影的交点可以位于所述第一子信号线段在所述衬底基板正投影和所述第二透明桥接线段在所述衬底基板正投影的交点上。该设置同样可以使得沿第一方向X延伸的透明桥接线段和沿第二方向Y延伸的透明桥接线段不相交。应该理解的是，在其他示例性实施例中，第二延伸线在所述衬底基板正投影也可以沿直线延伸。
本示例性实施例中，如图2、3所示，多个所述第二发光单元7可以包括：第一R发光单元R1、第一G发光单元G1、第一B发光单元B1；其中，第一R发光单元R1、第一G发光单元G1、第一B发光单元B1沿同一发光单元行依次交替分布，且在同一发光单元行中，第一R发光单元R1和第一B发光单元B1之间设置有两个沿列方向分布的第一G发光单元G1，在相邻发光单元行中，同一颜色的发光单元位于不同的发光单元列，在相间隔一发光单元行的两发光单元行中，同一颜色的发光单元位于同一发光单元列。即第二显示区中的第二发光单元以RGGB像素结构分布。应该理解的是，在其他示例性实施例中第二显示区中的第二发光单元还可以以其他像素结构分布，例如Real RGB像素结构分布。
本示例性实施例中，如图2、3所示，所述第一像素岛中的至少一个第一发光单元可以包括：第二R发光单元R2、第二G发光单元G2、第三G发光单元G3、第二B发光单元B2。其中，在同一所述第一像素岛中，所述第二G发光单元G2可以位于第一发光单元行，所述第二R发光单元R2和所述第二B发光单元B2可以在第二发光单元行上相邻设置，所述第三G发光单元G3可以位于第三发光单元行，所述第二发光单元行可以位于所述第一发光单元行和所述第三发光单元行之间。所述第二B发光单元B2可以位于第一发光单元列，所述第二G发光单元G2和第三G发光单元G3可以位于第二发光单元列，所述第二R发光单元R2可以位于第三发光单元列，所述第二发光单元列可以位于所述第一发光单元列和所述第三发光单元列之间。在列方向上，第二G发光单元G2和第三G发光单元G3之间可以间隔一个发光单元行。其中，第一显示区中第一像素岛在该像素结构排布下，第一显示区的开口率可以达到67.89％，透光率可以达到36.61％。
应该理解的是，在其他示例性实施例中，第一像素岛3中还可以包括其他数量的发光单元，第一像素岛3中发光单元还可以有其他的像素结构排布方式。例如，如图4所示， 为本公开显示面板另一种示例性实施例的结构示意图。在第一显示区1中，所述第二R发光单元R2和所述第二G发光单元G2位于第一发光单元行，所述第二B发光单元B2位于第二发光单元行，所述第三G发光单元G3位于第三发光单元行，所述第二发光单元行位于所述第一发光单元行和所述第三发光单元行之间；所述第二R发光单元R2位于第一发光单元列，所述第二B发光单元B2位于第二发光单元列，所述第二G发光单元G2和第三G发光单元G3位于第三发光单元列，所述第二发光单元列位于所述第一发光单元列和所述第三发光单元列之间。在列方向上，第二G发光单元G2和第三G发光单元G3之间可以间隔一个发光单元行。相应的，在该像素结构分布中，第一像素岛中的像素驱动电路成二乘二阵列分布。其中，第一显示区中第一像素岛在该像素结构排布下，第一显示区的开口率可以达到71.5％，透光率可以达到38.55％。
再例如，如图5所示，为本公开显示面板另一种示例性实施例的结构示意图。在第一显示区1中，所述第二R发光单元R2、第二G发光单元G2、第二B发光单元B2可以位于第一发光单元行，所述第三G发光单元G3位于第二发光单元行，所述第一发光单元行和所述第二发光单元行相邻设置；所述第二R发光单元R2位于第一发光单元列，所述第二G发光单元G2位于第二发光单元列，所述第二B发光单元B2位于第三发光单元列，所述第三G发光单元G3位于第四发光单元列，其中，所述第一发光单元列、第二发光单元列、第三发光单元列、第四发光单元列在行方向上依次分布。在列方向上，第二G发光单元G2和第三G发光单元G3相邻设置，即在列方向上，第二G发光单元G2和第三G发光单元G3不间隔发光单元行。相应的，在该像素结构分布中，第一像素岛中的像素驱动电路在行方向依次分布。其中，第一显示区中第一像素岛在该像素结构排布下，第一显示区的开口率可以达到72.04％，透光率可以达到38.84％。
再例如，如图6所示，为本公开显示面板另一种示例性实施例的结构示意图。所述第二R发光单元R2、所述第二G发光单元G2、第三G发光单元G3位于第一发光单元行，其中，所述第二G发光单元G2、第三G发光单元G3在衬底基板正投影的面积较小，所述第二G发光单元G2、第三G发光单元G3可以认为位于同一发光单元行。所述第二B发光单元B2位于第二发光单元行，所述第一发光单元行和所述第二发光单元行相邻设置；所述第二R发光单元R2位于第一发光单元列，所述第二B发光单元B2位于第二发光单元列，所述第二G发光单元G2、第三G发光单元G3位于第三发光单元列，所述第二发光单元列位于所述第一发光单元列和所述第三发光单元列之间。相应的，在该像素结构分布中，第一像素岛中的像素驱动电路成二乘二阵列分布。其中，第一显示区中第一像素岛在该像素结构排布下，第一显示区的开口率可以达到75.67％，透光率可以达到40.8％。
如图3、4、5、6所示，第一像素岛3可以包括有一个RGGB像素单元，一个RGGB像素单元可以包括一个R子像素、两个G子像素、一个B子像素。应该理解的是，在其他示例性实施例中，第一像素岛3还可以包括其他数量的像素单元，每个像素单元还可以包括其他数量的子像素单元，且同一像素单元中的子像素单元还可以以其他形式排布，例 如，第一像素岛中的像素单元可以以Real RGB排布方式分布。
本示例性实施例中，如图7所示，为本公开显示面板另一种示例性实施例的结构示意图。所述显示面板还可以包括彩膜层8，所述彩膜层8可以位于所述第一像素岛3背离所述衬底基板0的一侧；所述彩膜层8可以包括位于第一显示区的多个第一结构部81，多个所述第一结构部81与多个所述第一像素岛3一一对应设置，所述第一结构部81在所述衬底基板正投影覆盖与其对应的所述第一像素岛3在所述衬底基板的正投影，且所述第一结构部81在所述衬底基板正投影的至少一边或一角为弧形。其中，所述第一结构部81可以包括：第一遮光部811、第一滤光部812，其中，第一遮光部811可以由遮光材料层形成，例如，第一遮光部811可以由黑色光刻胶层。第一滤光部812可以采用彩色滤光膜。所述第一遮光部811上形成有至少一个开口，所述第一遮光部811上的开口与所述第一像素岛3中的第一发光单元一一对应设置；第一滤光部812位于所述第一遮光部811的开口内，所述第一滤光部812在所述衬底基板正投影可以和第一遮光部811上与其对应的开口在衬底基板正投影完全重合，且所述第一滤光部812在所述衬底基板正投影可以覆盖与其对应的所述第一发光单元在所述衬底基板的正投影，第一滤光部812的颜色可以和与其对应的发光单元的颜色相同。该设置可以通过第一结构部81遮挡第一像素岛中像素驱动电路的导电结构，从而避免像素驱动电路中细长引线由于衍射产生的炫光现象。如图7所示，第一结构部81在所述衬底基板正投影可以为水滴形状，应该理解的是，在其他示例性实施例中，第一结构部81在所述衬底基板正投影还可以圆角矩形等其他结构。多个第一结构部81可以相互间隔分布，从而有利于增加第一显示区的透过率。其中，第一滤光部812可以避免显示面板反光。应该理解的是，在其他示例性实施例中，第一遮光部811中的开口内也可以不设置滤光部，同时该显示面板可以通过偏光片避免反光。
本示例性实施例中，如图7所示，所述彩膜层8还可以包括位于所述第二显示区2的第二结构部82，所述第二结构部82可以包括：第二遮光部821、第二滤光部822，其中，第二遮光部821可以由遮光材料层形成，例如，第二遮光部821可以由黑色光刻胶层。第二滤光部822可以采用彩色滤光膜。所述第二遮光部821上形成有多个开口，所述第二遮光部821上的开口与所述第二发光单元一一对应设置；第二滤光部822位于所述第二遮光部821的开口内，所述第二滤光部822在所述衬底基板正投影可以和第二遮光部821上与其对应的开口在衬底基板的正投影完全重合，所述第二滤光部822在所述衬底基板正投影可以覆盖与其对应的所述第二发光单元在所述衬底基板的正投影。其中，第二遮光部821和第一遮光部811可以一体成型，即第二遮光部821和第一遮光部811可以通过一次构图工艺形成。第一滤光部812和第二滤光部822中的同色滤光部可以通过一次构图工艺形成。第二结构部82可以为一个整体结构，第二结构部82可以覆盖于第二显示区，同样的，第二滤光部822也可以避免显示面板反光。
该显示面板可以包括用于形成像素驱动电路的电路层，电路层可以包括有源层、第一栅极层、第二栅极层、第一源漏层、透明导电层、第二源漏层。如图8-14所示，图8为图 3中有源层的结构版图，图9为图3中第一栅极层的结构版图，图10为图3中第二栅极层的结构版图，图11为图3中第一源漏层的结构版图，图12为图3中透明导电层的结构版图，图13为图3中第二源漏层的结构版图，图14为图3中有源层、第一栅极层、第二栅极层、第一源漏层、透明导电层、第二源漏层的层叠结构版图。其中，衬底基板、有源层、第一栅极层、第二栅极层、第一源漏层、透明导电层、第二源漏层依次层叠设置。其中，上述相邻膜层之间还可以设置有其他膜层，例如，上述相邻膜层之间可以设置绝缘层。其中，第一信号线段41、第二信号线段42可以位于第一源漏层或第二源漏层，透明桥接线段5可以位于透明导电层。
本示例性实施例中，如图14所示，上述有源层、第一栅极层、第二栅极层、第一源漏层、透明导电层、第二源漏层可以形成上述的第一像素驱动电路31和第二像素驱动电路32。其中，所述第一像素驱动电路31在所述衬底基板正投影的面积可以小于所述第二像素驱动电路32在所述衬底基板正投影的面积。该设置可以降低第一像素驱动电路31对第一显示区1的遮光面积，从而提高第一显示区1的透光率。需要说明的是，像素驱动电路在衬底基板正投影的面积可以理解为，像素驱动电路中有源层部分外切矩形的面积，且该外切矩形的长宽分别与行列方向平行。例如，如图8所示，第一像素驱动电路31对应的外切矩形为A，第二像素驱动电路32对应的外切矩形为B。
本示例性实施例中，在至少一个方向上，相邻两所述第一像素驱动电路31在所述衬底基板正投影之间的间隙小于相邻两所述第二像素驱动电路32在所述衬底基板正投影之间的间隙。例如，如图14所示，在行方向上，相邻两所述第一像素驱动电路31在所述衬底基板正投影之间的间隙小于相邻两所述第二像素驱动电路32在所述衬底基板正投影之间的间隙。该设置可以进一步减小第一像素岛中像素驱动电路的布图面积，从而增加第一显示区的透光率。需要说明的是，相邻像素驱动电路在行方向上的距离可以理解为，相邻像素驱动电路的上述外切矩形在行方向上相邻边沿之间的距离。
本示例性实施例中，在同一所述第一像素岛中，至少存在一个所述第一发光单元在所述衬底基板的正投影和与其对应的所述第一像素驱动电路在所述衬底基板的正投影至少部分重合。该设置可以增加第一显示区透光区域的面积，从而增加第一显示区的透光率。例如，如图3所示，第二R发光单元R2在所述衬底基板的正投影和与其对应的所述第一像素驱动电路在所述衬底基板的正投影至少部分重合；第二B发光单元B2在所述衬底基板的正投影和与其对应的所述第一像素驱动电路在所述衬底基板的正投影至少部分重合；第二G发光单元G2在所述衬底基板的正投影和与其对应的所述第一像素驱动电路在所述衬底基板的正投影至少部分重合。
如图15所示，为本公开显示面板一种示例性实施例中像素驱动电路的电路结构示意图。其中，第一像素驱动电路和第二像素驱动电路均可以为该电路结构。该像素驱动电路可以包括：第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、电容C。其中，第一晶体管T1的第一极连接节点N， 第二极连接初始信号端Vinit，栅极连接复位信号端Re1；第二晶体管T2第一极连接驱动晶体管T3的第一极，第二极连接节点N；栅极连接栅极驱动信号端Gate；驱动晶体管T3的栅极连接节点N；第四晶体管T4的第一极连接数据信号端Da，第二极连接驱动晶体管T3的第二极，栅极连接栅极驱动信号端Gate；第五晶体管T5的第一极连接第一电源信号端VDD，第二极连接驱动晶体管T3的第二极，栅极连接使能信号端EM；第六晶体管T6第一极连接驱动晶体管T3的第一极，栅极连接使能信号端EM；第七晶体管T7的第一极连接初始信号端Vinit，第二极连接第六晶体管T6的第二极，栅极连接复位信号端Re2。电容C连接于驱动晶体管T3的栅极和第一电源信号端VDD之间。该像素驱动电路可以连接一发光单元OLED，用于驱动该发光单元OLED发光，发光单元OLED可以连接于第六晶体管T6的第二极和第二电源端VSS之间。其中，晶体管T1-T7可以均为P型晶体管。
如图16所示，为图15像素驱动电路一种驱动方法中各节点的时序图。其中，Gate表示栅极驱动信号端Gate的时序，Re1表示复位信号端Re1的时序，Re2表示复位信号端Re2的时序，EM表示使能信号端EM的时序，Da表示数据信号端Da的时序。该像素驱动电路的驱动方法可以包括复位阶段t1、补偿阶段t2，发光阶段t3。在复位阶段t1：复位信号端Re1输出低电平信号，第一晶体管T1导通，初始信号端Vinit向节点N输入初始信号。在补偿阶段t2：复位信号端Re2、栅极驱动信号端Gate输出低电平信号，第四晶体管T4、第二晶体管T2、第七晶体管T7导通，同时数据信号端Da输出驱动信号以向节点N写入电压Vdata+Vth，其中Vdata为驱动信号的电压，Vth为驱动晶体管T3的阈值电压，初始信号端Vinit向第六晶体管T6的第二极输入初始信号。发光阶段t3：使能信号端EM输出低电平信号，第六晶体管T6、第五晶体管T5导通，驱动晶体管T3在电容C存储的电压Vdata+Vth作用下发光。根据驱动晶体管输出电流公式I＝(μWCox/2L)(Vgs-Vth) 2，其中，μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电压。本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth) 2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。
以下本示例性实施例通过第一像素岛所在位置的局部放大图对第一像素岛的结构进行详细说明。
如图17-27所示，图17为图3中C区域中第一像素岛的局部放大图，图18为图17中有源层的结构版图，图19为图17中第一栅极层的结构版图，图20为图17中第二栅极的结构版图，图21为图17中第一源漏层的结构版图，图22为图17中透明导电层的结构版图，图23为图17中第二源漏层的结构版图，图24为图17中有源层和第一栅极层的层叠版图，图25为图17中有源层、第一栅极层、第二栅极层的层叠版图，图26为图17中有源层、第一栅极层、第二栅极层、第一源漏层的层叠版图，图27为图17中有源层、第一栅极层、第二栅极层、第一源漏层、透明导电层的层叠版图。
如图17、18、24所示，有源层可以包括第一有源部101、第二有源部102、第三有源 部103、第四有源部104、第五有源部105、第六有源部106、第七有源部107。其中，第一有源部101用于形成第一晶体管T1的沟道部，第二有源部102用于形成第二晶体管T2的沟道部，第三有源部103用于形成驱动晶体管T3的沟道部，第四有源部104用于形成第四晶体管T4的沟道部，第五有源部105用于形成第五晶体管T5的沟道部，第六有源部106用于形成第六晶体管T6的沟道部，第七有源部107用于形成第七晶体管T7的沟道部。
如图17、19、24所示，第一栅极层可以包括复位信号线Re、栅极驱动信号线Gate、使能信号线EM、导电部203。其中，复位信号线Re、栅极驱动信号线Gate、使能信号线EM可以形成上述的第一子信号线段。复位信号线Re可以用于提供图15中的复位信号端Re1和复位信号端Re2，如图19、24所示，该第一像素岛3包括有三条复位信号线Re，处于中间位置的复位信号线Re可以用于提供该第一像素岛中上一行像素驱动电路中的复位信号端Re2和下一行像素驱动电路中的复位信号端Re1。栅极驱动信号线Gate可以用于提供图15中的栅极驱动信号端，使能信号线EM可以用于提供图15中的使能信号端。其中，复位信号线的部分结构可以用于形成第一晶体管T1和第七晶体管T7的栅极。栅极驱动信号线Gate的部分结构可以用于形成第二晶体管T2和第四晶体管T4的栅极。使能信号线EM的部分结构可以形成第五晶体管T5和第六晶体管T6的栅极。导电部203可以用于形成驱动晶体管T3的栅极和电容C的一电极。
如图17、20、25所示，第二栅极层可以包括初始信号线Vint、导电部301，初始信号线Vint可以用于提供图15中的初始信号端。导电部301可以用于形成电容C的另一电极。其中，导电部301上形成有开口3011。
如图17、21、26所示，第一源漏层可以包括数据线Da、多个导电部401、导电部402、导电部403、导电部404、导电部405、导电部406。数据线Da可以形成上述的第二子信号线段，数据线Da可以用于提供图15中的数据信号端。多个导电部401可以分别通过过孔(图中黑色方块)连接于复位信号线Re的两端、使能信号线EM的两端、部分栅极驱动信号线Gate的两端、部分初始信号线Vinit的两端。导电部402可以用于分别通过过孔连接初始信号线Vinit和第一有源部101一侧的有源层，以连接第一晶体管T1的第二极和初始信号端。导电部403可以用于分别通过过孔连接第一有源部101一侧的有源层和导电部203，以连接第一晶体管T1的第一极和驱动晶体管T3的栅极。其中，用于连接导电部403和导电部203的过孔贯穿于导电部301上的开口3011内，以避免导电部403与导电部301短接。导电部404用于分别通过过孔连接导电部301和第五有源部105一侧的有源层，以连接第五晶体管T5的第一极和电容C的一电极。导电部405可以用于通过过孔连接第七有源部107一侧的有源层，以连接第七晶体管的第二极。导电部406用于分别通过过孔连接初始信号线Vinit和第七有源部107一侧的有源层，以连接第七晶体管T7的第一极和初始信号端。
如图17、22、27所示，透明导电层可以包括多条第一子透明桥接线段511、多条第二子透明桥接线段522、导电部501和导电部502。其中，导电部501通过过孔与导电部404 连接，导电部502通过过孔与导电部405连接。多条第一子透明桥接线段511可以分别通过导电部401与初始信号线、栅极驱动信号线、复位信号线、使能信号线等行方向延伸的信号线连接。第二子透明桥接线段522可以通过导电部401与数据信号线连接。
如图17、23所示，第二源漏层可以包括电源线VDD、导电部601，电源线VDD可以通过过孔连接第二子透明桥接线段522，此外，电源线VDD可以通过过孔连接导电部501，以连接图15中的第一电源端VDD和第五晶体管T5、电容的一电极。导电部601可以通过过孔连接导电部502，导电部601可以用于连接发光单元的阳极。电源线VDD可以形成上述的第二子信号线段。
如图17、21、26所示，第一源漏层还可以包括第一连接线407。其中，第一连接线407可以分别通过过孔连接上一行像素驱动电路中的栅极驱动信号线Gate和下一行像素驱动电路中的复位信号线Re，其中，上一行像素驱动电路中的栅极驱动信号线Gate可以向上一行像素驱动电路中的第一晶体管T1提供栅极驱动信号，下一行像素驱动电路中的复位信号线Re可以向上一行像素驱动电路中的第七晶体管T7提供栅极驱动信号，如图16可知，复位信号端Re2与栅极驱动信号端Gate具有相同的时序，因此，上一行像素驱动电路可以通过下一行中的复位信号线Re提供栅极驱动信号，从而本行像素驱动电路中的栅极驱动信号线Gate可以不通过透明桥接线段与其他信号线连接。一方面，该设置可以降低第一显示区中透明桥接线段的数量，从而增加第一显示区的透光率；另一方面，该设置可以增加第一显示区的布图空间，以便于布图设计。
如图17、21、26所示，第一源漏层还可以包括第二连接线408，第二连接线408可以分别通过过孔与第一像素岛中的多条初始信号线Vinit连接。在同一第一像素岛中，至少部分初始信号线Vinit可以不通过透明桥接线段与其他信号线连接。例如，如图21、26所示，第一像素岛可以包括三条初始信号线Vinit，位于中间的一条初始信号线Vinit可以不通过透明桥接线段与其他信号线连接。一方面，该设置可以减小第一显示区中的透明信号线，从而增加第一显示区的透光率；另一方面，该设置也可以降低初始信号线Vinit的阻抗负载(RC loading)。
如图17所示，第一像素岛可以包括位于第一行的一个第一子像素驱动电路311和位于第二行的三个第二子像素驱动电路312，第一子像素驱动电路311和第二行中位于中间位置的第二子像素驱动电路312位于同一列。第一像素岛可以包括三条数据线Da，位于第一像素岛两侧的数据线Da可以在列方向上弯折延伸，其中，该两条数据线可以沿偏向第一子像素驱动电路311的位置弯折。第一像素岛可以包括三条电源线VDD，位于第一像素岛两侧的电源线VDD可以在列方向上弯折延伸，其中，该两条电源线VDD可以沿偏向第一子像素驱动电路311的位置弯折。该设置可以减小第一像素岛的面积，从而增加第一显示区的透光率。如图17所示，位于第一像素岛同一侧的电源线VDD和数据线Da在衬底基板的正投影至少部分重合，该设置可以进一步降低第一像素岛的面积。
如图28所示，为本公开显示面板一种示例性实施例沿图17中虚线D的部分剖视图， 该剖视图仅画出了图17中沿虚线D剖视的部分结构。该显示面板还可以包括：缓冲层801、第一绝缘层802、第二绝缘层803、介电层804、钝化层805、第一平坦层806、第二平坦层807、阳极层701。其中，衬底基板0、缓冲层801、有源层、第一绝缘层802、第一栅极层、第二绝缘层803、第二栅极层、介电层804、第一源漏层、钝化层805、透明导电层、第一平坦层806、第二源漏层、第二平坦层807、阳极层701可以依次层叠设置。
其中，第一绝缘层802、第二绝缘层803可以为氧化硅层，介电层804可以为氮化硅层。钝化层、缓冲层均可以为氧化硅层。第一栅极层、第二栅极层、第一源漏层、第二源漏层均可以通过至少一层金属层形成。例如，第一栅极层、第二栅极层、第一源漏层、第二源漏层均可以通过第一钛层、铝层、第二钛层依次层叠形成。透明导电层可以为氧化铟锡层。衬底基板可以通过绝缘材料形成，例如，衬底基板可以包括依次设置的第一聚酰亚胺(PI)层、第一氧化硅(SiO)层、非晶硅层、第二聚酰亚胺(PI)层、第二氧化硅层。
本示例性实施例中，第二源漏层中的多条电源线可以相互连接。从而如图3所示，位于第二显示区中的部分电源线VDD可以在第一显示区断开。一方面，该设置可以降低电源线VDD的阻抗负载(RC loading)；另一方面，该设置可以降低第一显示区中透明桥接线段的数量，从而增加第一显示区的透光率。
本示例性实施例还提供一种显示装置，该显示装置包括：上述的显示面板和传感器件，所述传感器件与所述显示面板的第一显示区正对。其中，该显示装置可以为手机、平板电脑等显示装置。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (21)

  1. 一种显示面板，其中，所述显示面板包括第一显示区和第二显示区，所述显示面板还包括：
    多个第一像素岛，所述第一像素岛位于所述第一显示区，所述第一像素岛包括：
    至少一个第一发光单元；
    至少一个第一像素驱动电路，与所述第一发光单元一一对应设置，所述第一像素驱动电路用于向与其对应的所述第一发光单元提供驱动电流；
    多条第一信号线段，用于向所述第一像素驱动电路提供信号；
    多条透明桥接线段，位于所述第一显示区，至少部分所述透明桥接线段用于通过过孔连接不同所述第一像素岛中的第一信号线段。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    衬底基板，所述第一像素岛位于所述衬底基板的一侧；
    多条所述第一信号线段包括：
    第一子信号线段，在所述衬底基板的正投影沿第一方向延伸；
    第二子信号线段，在所述衬底基板的正投影沿第二方向延伸，所述第一方向和所述第二方向相交；
    多条所述透明桥接线段包括第一透明桥接线段和第二透明桥接线段，所述第一透明桥接线段包括：
    第一子透明桥接线段，位于所述第一显示区，所述第一子透明桥接线段用于通过过孔连接不同第一像素岛中的第一子信号线段；
    多条所述第二透明桥接线段包括：
    第二子透明桥接线段，位于所述第一显示区，所述第二子透明桥接线段用于通过过孔连接不同第一像素岛中的第二子信号线段。
  3. 根据权利要求2所述的显示面板，其中，所述显示面板还包括：
    多个第二发光单元，位于所述第二显示区；
    多个第二像素驱动电路，位于所述第二显示区，多个所述第二像素驱动电路与所述多个所述第二发光单元一一对应设置，所述第二像素驱动电路用于向与其对应的第二发光单元提供驱动电流；
    多条第二信号线段，位于所述第二显示区，用于向所述第二像素驱动电路提供信号；
    至少部分所述透明桥接线段用于通过过孔连接所述第一信号线段和所述第二信号线段。
  4. 根据权利要求3所述的显示面板，其中，
    多条所述第二信号线段包括：
    第三子信号线段，在所述衬底基板的正投影沿所述第一方向延伸；
    第四子信号线段，在所述衬底基板的正投影沿所述第二方向延伸；
    多条所述第一透明桥接线段还包括：
    第三子透明桥接线段，位于所述第一显示区，所述第三子透明桥接线段用于通过过孔连接所述第一子信号线段和所述第三子信号线段；
    多条所述第二透明桥接线段还包括：
    第四子透明桥接线段，位于所述第一显示区，所述第四子透明桥接线段用于通过过孔连接所述第二子信号线段和所述第四子信号线段。
  5. 根据权利要求2-4任一项所述的显示面板，其中，相互连接的所述第一透明桥接线段和所述第一子信号线段形成第一延伸线，相互连接的所述第二透明桥接线段和所述第二子信号线段形成第二延伸线；
    所述第一延伸线在所述衬底基板正投影和所述第二延伸线在所述衬底基板正投影的交点位于所述第二子信号线段在所述衬底基板正投影和所述第一透明桥接线段在所述衬底基板正投影的交点上。
  6. 根据权利要求2-4任一项所述的显示面板，其中，相互连接的所述第一透明桥接线段和所述第一子信号线段形成第一延伸线，相互连接的所述第二透明桥接线段和所述第二子信号线段形成第二延伸线；
    所述第一延伸线在所述衬底基板正投影和所述第二延伸线在所述衬底基板正投影的交点位于所述第一子信号线段在所述衬底基板正投影和所述第二透明桥接线段在所述衬底基板正投影的交点上。
  7. 根据权利要求2所述的显示面板，其中，所述第一子信号线段为多条，所述第二子信号线段为多条；
    多条所述第一子信号线段包括栅极驱动信号线、使能信号线、初始信号线、复位信号线中的一种或多种；
    多条所述第二子信号线段包括数据线、电源线中的一种或多种。
  8. 根据权利要求7所述的显示面板，其中，至少部分所述第一像素岛包括第 一连接线；
    在该第一像素岛中，所述第一子信号线段包括栅极驱动信号线和复位信号线，具有同一时序信号的所述栅极驱动信号线和所述复位信号线通过所述第一连接线连接；
    在通过所述第一连接线连接的所述栅极驱动信号线和所述复位信号线中，仅有一条信号线通过所述第一透明桥接线段和与其对应的其他信号线连接。
  9. 根据权利要求7所述的显示面板，其中，至少部分所述第一像素岛包括第二连接线；
    在该第一像素岛中，所述第一子信号线段包括n条初始信号线，n为大于1的正整数，该第一像素岛中的n条初始信号线通过所述第二连接线电连接；
    在通过所述第二连接线连接的n条所述初始信号线中，存在m条初始信号线通过所述第一透明桥接线段和与其对应的其他信号线连接，其中，m为小于等于n且大于0的正整数。
  10. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    衬底基板；
    第一像素驱动电路，位于所述第一显示区；
    第二像素驱动电路，位于所述第二显示区；
    其中，所述第一像素驱动电路在所述衬底基板正投影的面积小于所述第二像素驱动电路在所述衬底基板正投影的面积。
  11. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    衬底基板；
    第一像素驱动电路，位于所述第一显示区；
    第二像素驱动电路，位于所述第二显示区；
    其中，在至少一个方向上，相邻两所述第一像素驱动电路在所述衬底基板正投影之间的间隙小于相邻两所述第二像素驱动电路在所述衬底基板正投影之间的间隙。
  12. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    衬底基板，所述第一像素岛位于所述衬底基板的一侧；
    其中，在同一所述第一像素岛中，至少存在一个所述第一发光单元在所述衬底基板的正投影和与其对应的所述第一像素驱动电路在所述衬底基板的正投影至少 部分重合。
  13. 根据权利要求3所述的显示面板，其中，多个所述第二发光单元包括：第一R发光单元、第一G发光单元、第一B发光单元；
    其中，第一R发光单元、第一G发光单元、第一B发光单元沿同一发光单元行依次交替分布，且在同一发光单元行中，第一R发光单元和第一B发光单元之间设置有两个沿列方向分布的第一G发光单元，在相邻发光单元行中，同一颜色的发光单元位于不同的发光单元列，在相间隔一发光单元行的两发光单元行中，同一颜色的发光单元位于同一发光单元列；
    所述第一像素岛中的第一发光单元包括：第二R发光单元、第二G发光单元、第三G发光单元、第二B发光单元。
  14. 根据权利要求13所述的显示面板，其中，在同一所述第一像素岛中，所述第二G发光单元位于第一发光单元行，所述第二R发光单元和所述第二B发光单元在第二发光单元行上相邻设置，所述第三G发光单元位于第三发光单元行，所述第二发光单元行位于所述第一发光单元行和所述第三发光单元行之间；
    所述第二B发光单元位于第一发光单元列，所述第二G发光单元和第三G发光单元位于第二发光单元列，所述第二R发光单元位于第三发光单元列，所述第二发光单元列位于所述第一发光单元列和所述第三发光单元列之间。
  15. 根据权利要求13所述的显示面板，其中，所述第二R发光单元和所述第二G发光单元位于第一发光单元行，所述第二B发光单元位于第二发光单元行，所述第三G发光单元位于第三发光单元行，所述第二发光单元行位于所述第一发光单元行和所述第三发光单元行之间；
    所述第二R发光单元位于第一发光单元列，所述第二B发光单元位于第二发光单元列，所述第二G发光单元和第三G发光单元位于第三发光单元列，所述第二发光单元列位于所述第一发光单元列和所述第三发光单元列之间。
  16. 根据权利要求13所述的显示面板，其中，所述第二R发光单元、第二G发光单元、第二B发光单元位于第一发光单元行，所述第三G发光单元位于第二发光单元行，所述第一发光单元行和所述第二发光单元行相邻设置；
    所述第二R发光单元位于第一发光单元列，所述第二G发光单元位于第二发光单元列，所述第二B发光单元位于第三发光单元列，所述第三G发光单元位于第四发光单元列，其中，所述第一发光单元列、第二发光单元列、第三发光单元列、 第四发光单元列在行方向上依次分布。
  17. 根据权利要求13所述的显示面板，其中，所述第二R发光单元、所述第二G发光单元、第三G发光单元位于第一发光单元行，所述第二B发光单元位于第二发光单元行，所述第一发光单元行和所述第二发光单元行相邻设置；
    所述第二R发光单元位于第一发光单元列，所述第二B发光单元位于第二发光单元列，所述第二G发光单元、第三G发光单元位于第三发光单元列，所述第二发光单元列位于所述第一发光单元列和所述第三发光单元列之间。
  18. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    衬底基板，所述第一像素岛位于所述衬底基板的一侧；
    彩膜层，所述彩膜层位于所述第一像素岛背离所述衬底基板的一侧；
    所述彩膜层包括位于第一显示区的多个第一结构部，多个所述第一结构部与多个所述第一像素岛一一对应设置，所述第一结构部在所述衬底基板正投影覆盖与其对应的所述第一像素岛在所述衬底基板的正投影，且所述第一结构部在所述衬底基板正投影的至少一边或一角为弧形；
    所述第一结构部包括：
    第一遮光部，所述第一遮光部上形成有至少一个开口，所述第一遮光部上的开口与所述第一像素岛中的第一发光单元一一对应设置；
    第一滤光部，位于所述第一遮光部的开口内，所述第一滤光部在所述衬底基板正投影覆盖与其对应的所述第一发光单元在所述衬底基板的正投影。
  19. 根据权利要求18所述的显示面板，其中，所述显示面板还包括：多个位于所述第二显示区的第二发光单元，所述彩膜层还包括位于所述第二显示区的第二结构部，所述第二结构部包括：
    第二遮光部，所述第二遮光部上形成有多个开口，所述第二遮光部上的开口与所述第二发光单元一一对应设置；
    第二滤光部，位于所述第二遮光部的开口内，所述第二滤光部在所述衬底基板正投影覆盖与其对应的所述第二发光单元在所述衬底基板的正投影。
  20. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    衬底基板，所述第一像素岛位于所述衬底基板的一侧；
    第二发光单元，位于所述第二显示区；
    所述第一显示区的像素密度小于等于第二显示区的像素密度；
    在同一颜色的发光单元中，所述第一发光单元在所述衬底基板的正投影面积小于等于所述第二发光单元在所述衬底基板的正投影面积。
  21. 一种显示装置，其中，包括：
    权利要求1-20任一项所述的显示面板；
    传感器件，所述传感器件与所述显示面板的第一显示区正对。
PCT/CN2021/131784 2021-03-16 2021-11-19 显示面板、显示装置 WO2022193712A1 (zh)

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CN115942838A (zh) * 2021-08-16 2023-04-07 京东方科技集团股份有限公司 显示面板及其制作方法和显示装置
CN113793856B (zh) * 2021-09-13 2024-05-07 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN113870759B (zh) * 2021-09-27 2023-12-22 京东方科技集团股份有限公司 一种显示面板及其驱动方法、显示设备
WO2023155138A1 (zh) * 2022-02-18 2023-08-24 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN115152031B (zh) * 2022-05-30 2023-09-01 京东方科技集团股份有限公司 显示基板及显示装置
CN115020461A (zh) * 2022-05-31 2022-09-06 京东方科技集团股份有限公司 显示基板及显示装置

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