WO2024000442A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024000442A1
WO2024000442A1 PCT/CN2022/102925 CN2022102925W WO2024000442A1 WO 2024000442 A1 WO2024000442 A1 WO 2024000442A1 CN 2022102925 W CN2022102925 W CN 2022102925W WO 2024000442 A1 WO2024000442 A1 WO 2024000442A1
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WO
WIPO (PCT)
Prior art keywords
transistor
base substrate
line
gate
orthographic projection
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PCT/CN2022/102925
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English (en)
French (fr)
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WO2024000442A9 (zh
Inventor
张跳梅
承天一
杨中流
蒋志亮
胡明
邱海军
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/102925 priority Critical patent/WO2024000442A1/zh
Priority to CN202280002069.0A priority patent/CN117836842A/zh
Publication of WO2024000442A1 publication Critical patent/WO2024000442A1/zh
Publication of WO2024000442A9 publication Critical patent/WO2024000442A9/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • the display panel In LTPO (Low temperature polycrystalline TFT+Oxide TFT) technology, the display panel generally includes a first gate layer, a second gate layer, and a third gate layer that are stacked in sequence.
  • the second gate layer is located on the first gate. layer and the third gate layer.
  • the first gate layer is used to form the gate of the P-type transistor
  • the second gate layer is used to form the bottom gate of the N-type transistor
  • the third gate layer is used to form the top gate of the N-type transistor.
  • the structure of the three-layer gate layer is relatively complex and requires multiple masks to be formed.
  • a display panel includes a pixel driving circuit, the pixel driving circuit includes a first type transistor and a second type transistor.
  • the display panel further includes: a substrate, a third An active layer, a second active layer, and a first conductive layer.
  • a first active layer is located on one side of the base substrate, and at least part of the structure of the first active layer is used to form a channel region of the first type transistor; a second active layer is located on the first The side of the active layer facing away from the base substrate, at least part of the structure of the second active layer is used to form the channel region of the second type transistor; the first conductive layer is located on the first active layer Between the second active layer and the second active layer, a partial structure of the first conductive layer is used to form the gate of the first type transistor, and a partial structure of the first conductive layer is used to form the second type transistor. The bottom gate of the transistor.
  • the pixel driving circuit further includes a driving transistor and an eighth transistor.
  • the first electrode of the eighth transistor is connected to the third initial signal line, and the second electrode of the eighth transistor is connected to the third initial signal line.
  • the pixel driving circuit further includes a capacitor
  • the first conductive layer includes a first conductive part
  • the first conductive part is used to form a first electrode of the capacitor.
  • the display panel further includes: a second conductive layer located on a side of the second active layer facing away from the base substrate; the second conductive layer includes a third conductive portion; the third conductive layer
  • the orthographic projection of the conductive part on the base substrate and the orthographic projection of the first conductive part on the base substrate at least partially overlap, and the third conductive part is used to form the second electrode of the capacitor.
  • part of the structure of the second conductive layer is also used to form the top gate of the second type transistor.
  • the pixel driving circuit further includes a driving transistor, a first transistor, and a second transistor.
  • the driving transistor is the first type transistor, and the first transistor and the second transistor are The second type transistor; the first electrode of the first transistor is connected to the first initial signal line, the second electrode of the first transistor is connected to the gate electrode of the driving transistor, and the first electrode of the second transistor is The gate electrode of the driving transistor is connected, the second electrode of the second transistor is connected to the second electrode of the driving transistor, the first electrode of the capacitor is connected to the gate electrode of the driving transistor;
  • the first active The layer includes: a third active part, the third active part is used to form a channel region of the driving transistor;
  • the second active layer includes: a first active part and a second active part, so The first active part is used to form a channel region of the first transistor, and the second active part is used to form a channel region of the second transistor;
  • the first conductive layer includes: a first conductive layer part, a first gate line, a first reset signal line
  • the pixel driving circuit further includes a fourth transistor, the first electrode of the fourth transistor is connected to the data line, and the second electrode of the fourth transistor is connected to the third electrode of the driving transistor.
  • the fourth transistor is the first type transistor;
  • the first active layer further includes a fourth active part, the fourth active part is used to form a channel region of the fourth transistor ;
  • the first conductive layer further includes: a second gate line, the orthographic projection of the second gate line on the base substrate covers the orthographic projection of the fourth active part on the base substrate, The partial structure of the second gate line is used to form the gate of the fourth transistor; wherein, the orthographic projection of the first gate line on the base substrate, the orthographic projection of the second gate line on the substrate The orthographic projection on the base substrate and the orthographic projection of the first reset signal line on the base substrate both extend along the first direction; the orthographic projection of the second gate line on the base substrate is located on the The orthographic projection of the first gate line on the base substrate is away from the orthographic projection of
  • the first gate line includes a plurality of first gate line segments, and the orthographic projections of the plurality of first gate line segments in the same first gate line on the substrate are Extending along the first direction and distributed at intervals along the first direction;
  • the second active layer also includes a fifteenth active part, the fifteenth active part is connected to the first active part and between the second active parts;
  • the first conductive layer further includes: a second conductive part, the orthographic projection of the second conductive part on the base substrate extends along the second direction and is located at Between the orthographic projections of two adjacent first gate line segments in the first direction on the base substrate, the second direction intersects the first direction, and the second conductive parts are respectively connected to the A fifteenth active part and the first conductive part;
  • the display panel further includes: a third conductive layer, the third conductive layer is located on a side of the second conductive layer facing away from the base substrate, the third conductive layer
  • the three conductive layers include a first gate connection line, an orthographic projection of the first gate
  • the first gate line includes a plurality of first gate line segments, and the orthographic projections of the plurality of first gate line segments in the same first gate line on the substrate are Extending along the first direction and distributed at intervals along the first direction;
  • the second active part further includes a fifteenth active part, the fifteenth active part is connected to the first active part and between the second active parts;
  • the display panel further includes: a third conductive layer, the third conductive layer is located on a side of the second conductive layer facing away from the base substrate, the third conductive layer includes A first gate connection line segment, a fourth bridge portion, an orthographic projection of the fourth bridge portion on the base substrate extends along a second direction, the second direction intersects the first direction, and the The fourth bridge portion connects the fifteenth active portion and the first conductive portion through via holes respectively; wherein, the orthographic projection of the fourth bridge portion on the base substrate and the first gate line segment The orthographic projections on the base substrate intersect, and the orthographic projections of the first gate connection line segments
  • the first gate line includes a plurality of first gate line segments, and the orthographic projections of the plurality of first gate line segments in the same first gate line on the substrate are Extending along the first direction and distributed at intervals along the first direction;
  • the second conductive layer includes a third gate line, and the orthographic projection of the third gate line on the substrate is along the first
  • the third gate line extends in the direction, and the third gate line connects multiple first gate line segments in the same first gate line through via holes.
  • the display panel further includes: a third conductive layer, the third conductive layer is located on a side of the second conductive layer facing away from the base substrate, the third conductive layer includes: A tenth bridge portion, the tenth bridge portion is connected between the fourth active portion and the third active portion; the orthographic projection of the first gate line on the base substrate and the The orthographic projections of the tenth bridge portion on the base substrate intersect.
  • the third gate line includes a plurality of third gate line segments, and the plurality of third gate line segments in the same third gate line are located on the front surface of the substrate.
  • the projection extends along the first direction and is distributed at intervals along the first direction;
  • the display panel also includes: a third conductive layer, the third conductive layer is located on a side of the second conductive layer away from the base substrate , the third conductive layer includes a first gate connection line, the orthographic projection of the first gate connection line on the base substrate extends along the first direction, and the first gate connection line Multiple third gate line segments in the same third gate line are respectively connected through via holes.
  • the sheet resistance of the third conductive layer is less than the sheet resistance of the first conductive layer; the sheet resistance of the third conductive layer is less than the sheet resistance of the second conductive layer.
  • the display panel further includes: a buffer layer and a second insulating layer, the buffer layer is located between the first conductive layer and the second active layer; a second insulating layer, is located between the second active layer and the second conductive layer; wherein the thickness of the second insulating layer between the first conductive portion and the third conductive portion is smaller than that of the second type transistor The thickness of the second insulating layer between the top gate and the bottom gate; and/or the thickness of the buffer layer between the first conductive part and the third conductive part is smaller than the top gate of the second type transistor The thickness of the buffer layer between the bottom gate and the bottom gate.
  • the display panel further includes a fan-out area and a plurality of data lines
  • the first conductive layer further includes: a first data fan-out line, and the first data fan-out line is located in the fan-out area. area, the first data fan-out line is connected to the corresponding data line
  • the second conductive layer also includes: a second data fan-out line, the second data fan-out line is located in the fan-out area, and the second data The fanout line is connected to the corresponding data line.
  • the pixel driving circuit includes a driving transistor and a fourth transistor.
  • the first electrode of the fourth transistor is connected to the data line, and the second electrode of the fourth transistor is connected to the driving transistor.
  • the first electrode of the capacitor is connected to the gate of the driving transistor, and the second electrode of the capacitor is connected to the third power line;
  • the first active layer includes a third active part, a fourth Active part, nineteenth active part, the third active part is used to form a channel region of the driving transistor, and the fourth active part is used to form a channel region of the fourth transistor,
  • the nineteenth active part is connected between the third active part and the fourth active part, and the orthographic projection of the nineteenth active part on the base substrate is in the first direction
  • the size is larger than the size of the orthogonal projection of the fourth active part on the base substrate in the first direction;
  • the second conductive layer includes a third conductive part and a fourth conductive part, and the third conductive part Three conductive parts are used to form the second electrode of the capacitor, the fourth conductive part is
  • the display panel includes: a light-emitting unit located in the display area, and the pixel driving circuit includes: a driving transistor, a first transistor, a seventh transistor, and an eighth transistor; the pixel driving circuit
  • the first electrode of the light-emitting unit is connected to the first electrode of the light-emitting unit, and the second electrode of the light-emitting unit is connected to the first power line;
  • the first stage of the first transistor is connected to the first initial signal line, and the second electrode of the first transistor is connected to The gate electrode of the driving transistor;
  • the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit;
  • the third electrode of the eighth transistor is One pole is connected to the third initial signal line, and the second pole of the eighth transistor is connected to the first pole of the driving transistor;
  • the display panel also includes: a plurality of first signal lines, a plurality of second signal lines, and a plurality of second signal lines.
  • a plurality of first signal lines are located in the display area of the display panel, and the orthographic projection of the first signal line on the substrate extends along the first direction; a plurality of second signal lines are located in the display area of the display panel. , and the orthographic projection of the second signal line on the base substrate extends along a second direction, the second direction intersects the first direction, and at least part of the second signal line is connected to it through a via hole At least part of the first signal line intersected by orthographic projection on the base substrate; the first signal line includes the first power line, the first initial signal line, the second initial signal line , at least one of the third initial signal lines, the same second signal line is connected to the same first signal line, and the second signal line is connected to the first power line, the first At least one of the initial signal line, the second initial signal line, and the third initial signal line.
  • the pixel driving circuit further includes a fourth transistor, a driving transistor, and a fifth transistor.
  • the first electrode of the fifth transistor is connected to the third power line, and the fifth transistor has a first electrode connected to the third power line.
  • the second electrode is connected to the first electrode of the driving transistor, the first electrode of the fourth transistor is connected to the data line, and the second electrode of the fourth transistor is connected to the first electrode of the driving transistor;
  • the display panel also includes : a fourth conductive layer, the fourth conductive layer is located on the side of the second active layer facing away from the base substrate, the fourth conductive layer includes the data line, the third power line, and the second signal line;
  • the orthographic projection of the data line on the base substrate and the orthographic projection of the third power line on the base substrate extend along the second direction, and in the same column of pixel driving circuits,
  • the orthographic projection of the second signal line located on the fourth conductive layer on the substrate is located on the orthographic projection of the data line on the substrate and the third power line is located on the substrate. between orthographic projections on the base substrate.
  • the display panel includes a plurality of repeating units distributed in an array along a first direction and a second direction, and the first direction and the second direction intersect; each of the repeating units It includes two pixel driving circuits distributed along the first direction, and the two pixel driving circuits in the same repeating unit are arranged in mirror symmetry.
  • the first direction is a row direction
  • the second direction is a column direction
  • the pixel driving circuit includes a driving transistor
  • the first electrode of the capacitor is connected to the driving transistor.
  • the gate electrode, the second electrode of the capacitor is connected to the third power line;
  • the display panel also includes: a fourth conductive layer, the fourth conductive layer is located on the side of the second conductive layer away from the base substrate, so The fourth conductive layer includes the third power line, and each column of the pixel driving circuit is provided with one third power line.
  • the third power line includes: a first extension part, a second extension part, a third Extension part, the second extension part is connected between the first extension part and the third extension part; the dimension of the orthographic projection of the second extension part on the substrate substrate in the row direction is larger than that of the third extension part.
  • the size of the orthographic projection of an extension portion on the base substrate in the row direction, and the size of the orthogonal projection of the second extension portion on the base substrate in the row direction is larger than that of the third extension portion.
  • the display panel includes a plurality of the pixel driving circuits, the plurality of pixel driving circuits are array-distributed along a first direction and a second direction, and the first direction and the second direction are arrayed.
  • the pixel driving circuit also includes a fifth transistor, the first pole of the fifth transistor is connected to the third power line, and the second pole of the fifth transistor is connected to the first pole of the driving transistor, so
  • the display panel further includes: a third conductive layer and a fourth conductive layer, the third conductive layer is located on a side of the second conductive layer facing away from the base substrate, the third conductive layer includes a power connection line, and the The orthographic projection of the power connection line on the base substrate extends along the first direction.
  • the power connection line is connected to a plurality of the third conductive parts through via holes, and the power connection line is connected to the same power connection line.
  • the orthographic projections of the plurality of third conductive parts on the base substrate are spaced apart along the first direction; the fourth conductive layer is located on the side of the third conductive layer facing away from the base substrate, the The fourth conductive layer includes the third power line, an orthographic projection of the third power line on the substrate extends along the second direction, and the third power line is connected to the third power line on the substrate.
  • the orthographic projection on the substrate intersects the power connection lines.
  • the display panel further includes a light-emitting unit
  • the pixel driving circuit further includes: a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;
  • the first pole of the four transistors is connected to the data line
  • the second pole of the fourth transistor is connected to the first pole of the driving transistor
  • the first pole of the fifth transistor is connected to the third power line
  • the first pole of the fifth transistor is connected to the third power line.
  • the second electrode is connected to the first electrode of the driving transistor; the first electrode of the sixth transistor is connected to the second electrode of the driving transistor; the second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit ;
  • the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit;
  • the first electrode of the eighth transistor is connected to the third initial signal line, the second pole of the eighth transistor is connected to the first pole of the driving transistor;
  • the fourth, fifth, sixth, seventh and eighth transistors are the first type transistors;
  • the first type transistor is a P-type transistor, and the second type transistor is an N-type transistor.
  • a display device which includes the above-mentioned display panel.
  • Figure 1 is a schematic structural diagram of a pixel driving circuit in an exemplary embodiment of the display panel of the present disclosure
  • Figure 2 is a structural layout of a display panel in an exemplary embodiment of the present disclosure
  • Figure 3 is a structural layout of the first active layer in Figure 2;
  • Figure 4 is a structural layout of the first conductive layer in Figure 2;
  • Figure 5 is a structural layout of the second active layer in Figure 2;
  • Figure 6 is a structural layout of the second conductive layer in Figure 2;
  • Figure 7 is a structural layout of the third conductive layer in Figure 2;
  • Figure 8 is a structural layout of the fourth conductive layer in Figure 2;
  • Figure 9 is a structural layout of the first active layer and the first conductive layer in Figure 2;
  • Figure 10 is a structural layout of the first active layer, the first conductive layer, and the second active layer in Figure 2;
  • Figure 11 is a structural layout of the first active layer, the first conductive layer, the second active layer, and the second conductive layer in Figure 2;
  • Figure 12 is a structural layout of the first active layer, the first conductive layer, the second active layer, the second conductive layer and the third conductive layer in Figure 2;
  • Figure 13 is a partial cross-sectional view of the display panel shown in Figure 2 taken along the dotted line AA;
  • Figure 14 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • Figure 15 is a structural layout of the third conductive layer in Figure 14;
  • Figure 16 is a structural layout of the fourth conductive layer in Figure 14;
  • Figure 17 is a structural layout of the first active layer, the first conductive layer, the second active layer, the second conductive layer and the third conductive layer in Figure 14;
  • Figure 18 is a structural layout of a display panel in an exemplary embodiment of the present disclosure.
  • Figure 19 is a structural layout of the first active layer in Figure 18;
  • Figure 20 is a structural layout of the first conductive layer in Figure 18;
  • Figure 21 is a structural layout of the second active layer in Figure 18;
  • Figure 22 is a structural layout of the second conductive layer in Figure 18;
  • Figure 23 is a structural layout of the third conductive layer in Figure 18;
  • Figure 24 is a structural layout of the fourth conductive layer in Figure 18;
  • Figure 25 is a structural layout of the first active layer and the first conductive layer in Figure 18;
  • Figure 26 is a structural layout of the first active layer, the first conductive layer, and the second active layer in Figure 18;
  • Figure 27 is a structural layout of the first active layer, the first conductive layer, the second active layer, and the second conductive layer in Figure 18;
  • Figure 28 is a structural layout of the first active layer, the first conductive layer, the second active layer, the second conductive layer and the third conductive layer in Figure 18;
  • Figure 29 is a partial cross-sectional view of the display panel shown in Figure 18 taken along the dotted line AA;
  • Figure 30 is a schematic structural diagram of a display panel in another exemplary embodiment of the present disclosure.
  • Figure 31 is a schematic structural diagram of a display panel in another exemplary embodiment of the present disclosure.
  • FIG. 32 is a structural layout of the first active layer in FIG. 31 .
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments. To those skilled in the art.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C.
  • the first electrode of the fourth transistor T4 is connected to the data signal terminal Da
  • the second electrode is connected to the first electrode of the driving transistor T3, and the gate electrode is connected to the second gate driving signal terminal G2
  • the first electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T3.
  • a power supply terminal VDD the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the gate of the driving transistor T3 is connected to the node N; the first electrode of the second transistor T2 is connected to the node N, and the second electrode of the second transistor T2 is connected to the node N.
  • the first electrode of the sixth transistor T6 is connected to the second electrode of the drive transistor T3, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7.
  • the gate is connected to the enable signal terminal EM
  • the first pole of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate is connected to the second reset signal terminal Re2
  • the second pole of the first transistor T1 is connected to the node N
  • the gate of the seventh transistor T7 is connected to the second initial signal terminal Vinit2.
  • One pole is connected to the first initial signal terminal Vinit1, the gate is connected to the first reset signal terminal Re1;
  • the first electrode of the capacitor C is connected to the node N, the second electrode is connected to the first power supply terminal VDD, and the first pole of the eighth transistor T8 is connected to the node N.
  • the pixel driving circuit can be connected to a light-emitting unit OLED for driving the light-emitting unit OLED to emit light.
  • the light-emitting unit OLED can be connected between the second pole of the sixth transistor T6 and the second power terminal VSS.
  • the first transistor T1 and the second transistor T2 may be N-type transistors; the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be P-type transistors. .
  • the pixel driving circuit driving method may include a reset phase, a data writing phase, and a light emitting phase.
  • the reset phase the first reset signal terminal Re1 outputs a high-level signal
  • the second reset signal terminal Re2 outputs a low-level signal
  • the first transistor T1 and the eighth transistor T8 are turned on
  • the first initial signal terminal Vinit1 inputs to the node N
  • the first initial signal and the third initial signal terminal Vinit3 input the third initial signal to the first electrode of the driving transistor T3.
  • the first gate drive signal terminal G1 outputs a high-level signal
  • the second gate drive signal terminal G2 outputs a low-level signal
  • the second transistor T2 and the fourth transistor T4 are turned on, and at the same time the data signal terminal Da outputs the data signal to write the compensation voltage Vdata+Vth to the node N, where Vdata is the voltage of the data signal, and Vth is the threshold voltage of the driving transistor T3.
  • Light-emitting stage The enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in the capacitor C.
  • the pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.
  • I is the output current of the driving transistor;
  • ⁇ is the carrier mobility;
  • Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, and Vgs is the gate-source voltage of the driving transistor. Difference, Vth is the threshold voltage of the drive transistor.
  • This exemplary embodiment also provides a display panel, which may include a base substrate, a first active layer, a first conductive layer, a second active layer, a second conductive layer, a third conductive layer, and a layer arranged in sequence. layer and a fourth conductive layer, wherein an insulating layer may be provided between the adjacent layers.
  • Figure 2 is a structural layout of a display panel according to an exemplary embodiment of the present disclosure.
  • Figure 3 is a structural layout of the first active layer in Figure 2.
  • Figure 4 is a structural layout of the first conductive layer in Figure 2.
  • Figure 5 is the structural layout of the second active layer in Figure 2
  • Figure 6 is the structural layout of the second conductive layer in Figure 2
  • Figure 7 is the structural layout of the third conductive layer in Figure 2
  • Figure 8 is the structural layout of the fourth conductive layer in Figure 2.
  • Figure 9 is the structural layout of the first active layer and the first conductive layer in Figure 2.
  • Figure 10 is the first active layer, the first conductive layer and the first conductive layer in Figure 2.
  • Figure 11 is the structural layout of the first active layer, the first conductive layer, the second active layer, and the second conductive layer in Figure 2.
  • Figure 12 is the first active layer in Figure 2.
  • the display panel may include the pixel driving circuit shown in FIG. 1 .
  • the first active layer may be used to form a channel region of the first type of transistor, and the second active layer may be used to form a channel region of the second type of transistor.
  • the first type transistor may be a P-type transistor, and the second type transistor may be an N-type transistor.
  • this exemplary embodiment does not provide a second gate layer, that is, part of the structure of the first conductive layer can be used to form the gate of the first type transistor, and part of the structure of the first conductive layer can be used to form the gate of the first type transistor.
  • Bottom gate of type II transistor This setting can reduce the number of masks in the display panel production process and simplify the structure of the display panel.
  • the first active layer may include a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, and a seventh active portion. 77.
  • the third active part 73 may be used to form a channel region of the driving transistor T3;
  • the fourth active part 74 may be used to form a channel region of the fourth transistor T4;
  • the fifth active part 75 may be used to form a channel region of the fourth transistor T4.
  • the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion Part 78 is used to form the channel region of the eighth transistor T8.
  • the first active layer also includes: a ninth active part 79, a tenth active part 710, an eleventh active part 711, a twelfth active part 712, a thirteenth active part 713, a seventeenth active part
  • the source part 717 , the eighteenth active part 718 , the nineteenth active part 719 , and the twentieth active part 720 are examples of the eighth active part 710.
  • the ninth active part 79 is connected to an end of the fifth active part 75 away from the third active part 73 .
  • the tenth active part 710 is connected between the sixth active part 76 and the seventh active part 77
  • the eleventh active part 711 is connected between the sixth active part 76 and the third active part 73
  • the The twelve active parts 712 are connected to one end of the fourth active part 74 away from the third active part 73
  • the thirteenth active part 713 is connected to one end of the seventh active part 77 away from the sixth active part 76 .
  • the seventeenth active part 717 and the eighteenth active part 718 are connected to both ends of the eighth active part 78 respectively, and the nineteenth active part 719 is connected between the fourth active part 74 and the fifth active part 75 between.
  • the size of the nineteenth active portion 719 in the first direction X in the orthographic projection on the base substrate is larger than the size of the fourth active portion 74 in the first direction X in the orthographic projection on the base substrate.
  • the twentieth active part 720 is connected between the nineteenth active part 719 and the fifth active part 75 .
  • the first active layer may be formed of polysilicon material.
  • the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be a P-type low-temperature polysilicon film. transistor.
  • the first conductive layer may include: a first conductive part 11, a second gate line G2, an enable signal line EM, a second reset signal line Re2, a second conductive part 12, a first Gate line 1G1 and first reset signal line 1Re1.
  • the second gate line G2 can be used to provide the second gate drive signal terminal in Figure 1;
  • the enable signal line EM can be used to provide the enable signal terminal in Figure 1;
  • the second reset signal line Re2 can be used to provide the enable signal terminal in Figure 1
  • the first gate line 1G1 is used to provide the first gate drive signal terminal in FIG. 1, and the first reset signal line 1Re1 is used to provide the first reset signal terminal in FIG. 1.
  • the orthographic projection of the enable signal line EM on the base substrate, the orthographic projection of the first reset signal line 1Re1 on the base substrate, the orthographic projection of the second reset signal line Re2 on the base substrate, the first gate line 1G1 on Both the orthographic projection on the base substrate and the orthographic projection of the second gate line G2 on the base substrate can extend along the first direction X.
  • the orthographic projection of a structure on the base substrate extends along a certain direction. It can be understood that the orthographic projection of the structure on the base substrate extends straightly or in a bend along the direction.
  • the second gate line G2 may have multiple second gate line segments G22.
  • the orthographic projections of the multiple second gate line segments G22 in the same second gate line G2 on the substrate extend along the first direction X and are spaced apart along the first direction X.
  • the orthographic projection of the second gate line segment G22 on the base substrate covers the orthographic projection of the fourth active part 74 on the base substrate, and part of the structure of the second gate line segment G22 is used to form the gate of the fourth transistor T4.
  • the orthographic projection of the enable signal line EM on the base substrate covers the orthographic projection of the fifth active part 75 on the base substrate and the orthographic projection of the sixth active part 76 on the base substrate.
  • the enable signal line EM Part of the structure may be used to form the gate of the fifth transistor T5, and another part of the structure of the enable signal line EM may be used to form the gate of the sixth transistor T6.
  • the orthographic projection of the second reset signal line Re2 on the base substrate can cover the orthographic projection of the seventh active part 77 on the base substrate and the orthographic projection of the eighth active part 78 on the base substrate.
  • the second reset signal Part of the structure of the line Re2 may be used to form the gate of the seventh transistor T7, and another part of the structure of the second reset signal line Re2 may be used to form the gate of the eighth transistor T8.
  • the orthographic projection of the first conductive portion 11 on the base substrate covers the orthographic projection of the third active portion 73 on the base substrate.
  • the first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first capacitor C. electrode.
  • the first gate line 1G1 includes a plurality of first gate line segments 1G11.
  • the orthographic projections of the plurality of first gate line segments 1G11 in the same first gate line 1G1 on the substrate are spaced apart along the first direction X and extend along the first direction X.
  • the display panel can use the first conductive layer as a mask to conduct conduction processing on the first active layer, that is, the area of the first active layer covered by the first conductive layer can form the channel region of the transistor, and the first Areas of the active layer not covered by the first conductive layer form conductor structures.
  • the second active layer may include a first active portion 81, a second active portion 82, a fourteenth active portion 814, a fifteenth active portion 815, a sixteenth active portion Active part 816.
  • the first active part 81 is used to form a channel region of the first transistor T1
  • the second active part 82 is used to form a channel region of the second transistor T2.
  • the fifteenth active part 815 is connected between the first active part 81 and the second active part 82 .
  • the fourteenth active part 814 is connected to an end of the first active part 81 away from the fifteenth active part 815
  • the sixteenth active part 816 is connected to an end of the second active part 82 away from the first active part 81 .
  • the second active layer may be formed of indium gallium zinc oxide, and accordingly, the first transistor T1 and the second transistor T2 may be N-type metal oxide thin film transistors.
  • the orthographic projection of the first gate line 1G1 on the base substrate can cover the orthographic projection of the second active part 82 on the base substrate, and part of the structure of the first gate line 1G1 can be used to form the bottom gate of the second transistor.
  • the orthographic projection of the first reset signal line 1Re1 on the base substrate can cover the orthographic projection of the first active part 81 on the base substrate, and part of the structure of the first reset signal line 1Re1 can be used to form the bottom of the first transistor T1 gate.
  • the second conductive layer may include: a third reset signal line 2Re1 , a third gate line 2G1 , a third conductive part 23 , and a fourth conductive part 24 .
  • the third reset signal line 2Re1 may be used to provide the first reset signal terminal in FIG. 1
  • the third gate line 2G1 may be used to provide the first gate drive signal terminal in FIG. 1 .
  • the third reset signal line 2Re1 may include a plurality of third reset signal line segments 2Re11.
  • the orthographic projections of the plurality of third reset signal line segments 2Re11 in the same third reset signal line 2Re1 on the substrate are distributed at intervals along the first direction X and along Extending in the first direction
  • the third gate line 2G1 may include a plurality of third gate line segments 2G11.
  • the orthographic projections of the plurality of third gate line segments 2G11 in the same third gate line 2G1 on the substrate are spaced apart along the first direction X and are distributed along the first direction X.
  • the orthographic projection of the third gate line segment 2G11 on the base substrate can cover the orthographic projection of the second active part 72 on the base substrate, and part of the structure of the third gate line segment 2G11 can be used to form the top of the second transistor T2. gate.
  • the orthographic projection of the third conductive part 23 on the base substrate and the orthographic projection of the first conductive part 11 on the base substrate at least partially overlap, and the third conductive part 23 is used to form the second electrode of the capacitor C.
  • the fourth conductive part 24 is connected to the third conductive part 23.
  • the orthographic projection of the fourth conductive part 24 on the base substrate may at least partially overlap with the orthographic projection of the nineteenth active part 719 on the base substrate.
  • the fourth conductive part 24 is connected to the third conductive part 23.
  • the orthographic projection of the conductive portion 24 on the base substrate may be located between the orthographic projections of adjacent third gate line segments 2G11 on the base substrate in the first direction X.
  • the fourth conductive part 24 and the nineteenth active part 719 may form a parasitic capacitance.
  • the data signal input to the second electrode of the fourth transistor T4 may be stored in the parasitic capacitance.
  • the data signal stored in the parasitic capacitance can continue to input the compensation voltage to the node N through the driving transistor T3. This setting can fully write the compensation voltage to node N in a short data writing phase, so that a higher refresh frequency of the display panel can be achieved.
  • a plurality of third conductive parts 23 distributed in the first direction X may be connected to each other.
  • the display panel can use the second conductive layer as a mask to perform conductive treatment on the second active layer, that is, the area covered by the second conductive layer in the second active layer can form the channel region of the transistor. Areas of the active layer not covered by the second conductive layer form conductor structures.
  • the third conductive layer may include a first bridge portion 31, a second bridge portion 32, a third bridge portion 33, a fourth bridge portion 34, a sixth bridge portion 36, and a seventh bridge portion. 37.
  • the eighth bridge portion 38 the first initial signal line Vinit1, the second initial signal line Vinit2, the third initial signal line Vinit3, the first power line VSS1, the first gate connection line 3G1, and the second gate connection line 3G2 , the first reset connection line 3Re1, the second reset connection line 3Re2, and the power connection line 3VDD.
  • the orthographic projection of the first initial signal line Vinit1 on the base substrate, the orthographic projection of the second initial signal line Vinit2 on the base substrate, the orthographic projection of the third initial signal line Vinit3 on the base substrate, and the first power line VSS1 The orthographic projection on the base substrate, the orthographic projection of the first gate connection line 3G1 on the base substrate, the orthographic projection of the second gate connection line 3G2 on the base substrate, the first reset connection line 3Re1 on the base substrate
  • the orthographic projection on the substrate, the orthographic projection of the second reset connection line 3Re2 on the substrate, and the orthographic projection of the power connection line 3VDD on the substrate can all extend along the first direction X.
  • the orthographic projection of the second conductive portion 12 on the base substrate intersects the orthographic projection of the first gate connection line 3G1 on the base substrate.
  • the first initial signal line Vinit1 is used to provide a first initial signal terminal
  • the second initial signal line Vinit2 is used to provide a second initial signal terminal
  • the third initial signal line Vinit3 is used to provide a third initial signal terminal.
  • the first bridge portions 31 located in the same pixel row may be connected to the same power connection line 3VDD.
  • the power connection line 3VDD can be connected to a plurality of third conductive portions 23 located in the same pixel row through the via holes H.
  • the black squares indicate the positions of the via holes.
  • the first bridge part 31 may be connected to the ninth active part 79 through a via hole to connect the first electrode of the fifth transistor and the second electrode of the capacitor C.
  • the second bridge portion 32 may be connected to the tenth active portion 710 through a via hole to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.
  • the third bridge portion 33 can be connected to the eleventh active portion 711 and the sixteenth active portion 816 through via holes respectively to connect the second electrode of the second transistor T2, the first electrode of the sixth transistor T6, and the driving transistor T3. the second pole.
  • the fourth bridge portion 34 can be connected to the second conductive portion 12 and the first conductive portion 11 through via holes respectively, and the seventh bridge portion 37 can be connected to the second conductive portion 12 and the fifteenth active portion 815 through via holes respectively to connect The first electrode of the second transistor T2 and the gate electrode of the driving transistor.
  • an opening 231 is formed on the third conductive part 23 , and the orthographic projection of the via hole connected between the first conductive part 11 and the fourth bridge part 34 on the substrate is located at the position of the opening 231 on the substrate.
  • the conductive structure in the via hole and the third conductive portion 23 are insulated from each other.
  • the eighth bridge portion 38 can be connected to the seventeenth active portion 717 and the twentieth active portion 720 through via holes respectively, so as to connect the second electrode of the eighth transistor and the first electrode of the driving transistor terminal.
  • the first initial signal line Vinit1 may be connected to the fourteenth active part 814 through a via hole to connect the first initial signal terminal and the first pole of the first transistor T1.
  • the second initial signal line Vinit2 may be connected to the thirteenth active part 713 through a via hole to connect the second initial signal terminal and the first electrode of the seventh transistor.
  • the third initial signal line Vinit3 is connected to the eighteenth active part 718 through a via hole to connect the first electrode of the eighth transistor and the third initial signal terminal.
  • the first gate connection lines 3G1 may be respectively connected to the third gate line segments 2G11 located in the same third gate line 2G1 through via holes, and connected to the first gate line segments 1G11 located in the same first gate line 1G1 through via holes.
  • the second gate connection lines 3G2 may be respectively connected to the second gate line segments G22 located in the same second gate line G2 through via holes.
  • the first reset connection line 3Re1 can be connected to the first reset signal line segment 1Re11 located in the same first reset signal line 1Re1 through via holes respectively, and can be connected to the third reset signal line segment located in the same third reset signal line 2Re1 through via holes respectively. 2Re11.
  • the second reset connection line 3Re2 may be connected to the second reset signal line Re2 through a plurality of via holes.
  • the sheet resistance of the third conductive layer may be smaller than the sheet resistance of the first conductive layer and the second conductive layer.
  • the first gate connection line 3G1 can reduce the own resistance of the gate line connected to the second transistor T2, thereby improving the response speed of the second transistor T2.
  • the second gate connection line 3G2 can reduce the own resistance of the gate line connected to the fourth transistor T4, thereby improving the response speed of the fourth transistor T4.
  • the first reset connection line 3Re1 can reduce the own resistance of the gate line connected to the first transistor T1, thereby improving the response speed of the first transistor T1.
  • the second reset connection line 3Re2 can reduce the own resistance of the gate line connected to the seventh transistor and the eighth transistor, thereby improving the response speed of the seventh transistor and the eighth transistor.
  • the fourth conductive layer may include a plurality of third power lines VDD, a plurality of data lines Da, a second power line VSS2 , and a ninth bridge portion 49 .
  • the orthographic projection of the third power line VDD on the base substrate, the orthographic projection of the data line Da on the base substrate, and the orthographic projection of the second power line VSS2 on the base substrate can all extend along the second direction Y.
  • the second direction Y intersects the first direction X.
  • the second direction Y may be the column direction
  • the first direction X may be the row direction.
  • the third power line VDD can be used to provide the first power terminal
  • the data line Da can be used to provide the data signal terminal
  • the second power line VSS2 can be used to provide the second power terminal.
  • each column of pixel driving circuits can be provided with a third power line VDD correspondingly.
  • the third power line VDD can be connected to the power connection line 3VDD through a via hole to connect the first electrode of the fifth transistor and the first power supply terminal.
  • the third power line VDD and the power connection line 3VDD can form a grid structure to reduce the voltage difference between the first power terminals at different positions of the display panel, thereby improving display uniformity of the display panel.
  • the data line Da may be connected to the sixth bridge portion 36 through a via hole to connect the first electrode of the fourth transistor and the data signal terminal.
  • the ninth bridge part 49 may be connected to the second bridge part 32 through a via hole to connect the second pole of the seventh transistor.
  • the second power line VSS2 can be connected to the first power line VSS1 that intersects it through a via hole to form a grid structure.
  • the first power line VSS1 and the second power line VSS2 can be connected to the common electrode layer in the display panel.
  • the common electrode layer is In forming the second electrode of the light-emitting unit, the first power supply line VSS1 and the second power supply line VSS2 forming a grid structure can reduce the voltage difference between different locations on the common electrode layer.
  • the orthographic projection of the third power line VDD on the base substrate can cover the orthographic projection of the first active part 81 on the base substrate and the orthographic projection of the second active part 82 on the base substrate.
  • the third power line VDD The influence of light on the characteristics of the first transistor T1 and the second transistor T2 can be reduced.
  • the orthographic projection of the third power line VDD on the base substrate can cover the orthographic projection of the fourth bridge portion 34 on the base substrate, and the third power line VDD can be used to shield the noise of other signals on the fourth bridge portion 34 interference, thereby improving the stability of the gate voltage of the driving transistor T3.
  • the first initial signal line Vinit1, the second initial signal line Vinit2, the third initial signal line Vinit3, and the first power line VSS1 may also be located on other conductive layers, or the first initial signal line Vinit2 may be located on other conductive layers.
  • the signal line Vinit1, the second initial signal line Vinit2, the third initial signal line Vinit3, and the first power line VSS1 may be formed in parallel by multiple conductive layers.
  • the first initial signal line Vinit1, the second initial signal line Vinit2, the third initial signal line Vinit3, and the first power line VSS1 may also be located on the first active layer, the first conductive layer, the second conductive layer, and the second active layer. Any one or more layers in the source layer.
  • FIG. 13 it is a partial cross-sectional view of the display panel shown in FIG. 2 taken along the dotted line AA.
  • the display panel may also include a first insulating layer 91 , a buffer layer 92 , a second insulating layer 93 , a dielectric layer 94 , a passivation layer 95 , and a planarization layer 96 .
  • the third conductive layer, the passivation layer 95, the flat layer 96, and the fourth conductive layer are stacked in sequence.
  • the thickness of the buffer layer 92 may be greater than the thickness of the second insulation layer 93 .
  • the first insulating layer 91 and the second insulating layer 93 may have a single-layer structure or a multi-layer structure, and the material of the first insulating layer 91 and the second insulating layer 93 may be at least one of silicon nitride, silicon oxide, and silicon oxynitride.
  • the buffer layer 92 may include at least one of a silicon oxide layer and a silicon nitride layer.
  • the buffer layer may include a silicon oxide layer and a silicon nitride layer, and the silicon nitride layer is located between the first conductive layer and the silicon oxide layer. The capacity of the capacitor can be increased by thinning the buffer layer.
  • the thickness of the silicon oxide layer can be 700 angstroms-3000 angstroms
  • the thickness of the silicon oxide layer can be 700 angstroms, 1500 angstroms, 2500 angstroms, 3000 angstroms, etc.
  • the thickness of the silicon nitride layer can be 700 angstroms-2000 angstroms. Angstrom
  • the thickness of the silicon nitride layer can be 700 angstrom, 1500 angstrom, 2000 angstrom, etc.
  • the thickness of the silicon oxide layer can be 700 angstroms - 1500 angstroms
  • the thickness of the silicon oxide layer can be 700 angstroms, 1100 angstroms, 1500 angstroms, etc.
  • the thickness of the silicon nitride layer can be 700 angstroms - 1000 angstroms.
  • the thickness of the silicon nitride layer can be 700 angstroms, 900 angstroms, 1000 angstroms, etc.
  • the capacity of the capacitor can be increased by removing the silicon oxide layer between the two electrode plates of the capacitor.
  • the dielectric layer 94 can be a silicon nitride layer;
  • the passivation layer 95 can be a silicon oxide layer;
  • the material of the flat layer 96 can be an organic material, such as polyimide (PI), polyethylene terephthalate (PET). ), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG) and other materials.
  • the base substrate 90 may include a glass substrate, a barrier layer, and a polyimide layer that are stacked in sequence.
  • the barrier layer may be an inorganic material.
  • the material of the first conductive layer and the second conductive layer may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or laminate.
  • the material of the third conductive layer and the fourth conductive layer may include metal materials, for example, it may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or laminate, or it may be titanium/aluminum /titanium lamination.
  • the display panel may further include an electrode layer located on the side of the fourth conductive layer facing away from the base substrate, a pixel defining layer located on the side of the electrode layer facing away from the base substrate, and a luminescent material layer located on the side of the pixel defining layer facing away from the base substrate,
  • the common electrode layer is located on a side of the light-emitting material layer facing away from the base substrate.
  • the display panel may further include a fan-out area
  • the first conductive layer may include: a first data fan-out line located in the fan-out area, the first data fan-out line being connected to the corresponding data line
  • the second conductive layer may further include: a second data fan-out line located in the fan-out area, and the second data fan-out line is connected to the corresponding data line.
  • the data fan-out lines in the fan-out area are simultaneously provided on the first conductive layer and the second conductive layer.
  • the integration level of the data fan-out lines can be improved; on the other hand, due to the large distance between the first conductive layer and the second conductive layer in the present disclosure, this arrangement can reduce signal crosstalk between the data fan-out lines.
  • the second insulating layer 93 may have a patterned structure.
  • the second insulating layer 93 may be located only between the second active layer and the second conductive layer.
  • the second insulating layer 93 may not be disposed between the third conductive part 23 and the first conductive part 11. This arrangement can reduce the distance between the third conductive part 23 and the first conductive part 11, thereby increasing the capacity of the capacitor C. It should be understood that in other exemplary embodiments, the thickness of the local second insulating layer 93 and/or the buffer layer 92 between the third conductive part 23 and the first conductive part 11 may also be reduced. The distance between the third conductive part 23 and the first conductive part 11.
  • the distance between the third conductive part 23 and the first conductive part 11 in the thickness direction of the display panel may be smaller than the distance between the third gate line 2G1 and the first gate line 1G1 in the thickness direction of the display panel.
  • the thickness of one layer is to reduce the distance between the fourth conductive part 24 and the nineteenth active part 719 , thereby increasing the capacity of the capacitor formed by the fourth conductive part 24 and the nineteenth active part 719 .
  • the distance between the fourth conductive part 24 and the nineteenth active part 719 in the thickness direction of the display panel is smaller than the distance between the fourth conductive part 24 and the third active part 73 in the thickness direction of the display panel, wherein the distance between the fourth conductive part 24 and the nineteenth active part 719 in the thickness direction of the display panel is The thickness direction is perpendicular to the base substrate.
  • Figure 14 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • FIG. 15 is a structural layout of the third conductive layer in FIG. 14
  • FIG. 16 is a structural layout of the fourth conductive layer in FIG. 14 .
  • FIG. 17 is a structural layout of the first active layer, the first conductive layer, the second active layer, the second conductive layer and the third conductive layer in FIG. 14 .
  • the fourth conductive layer in the display panel shown in Figure 14 also includes a fourth initial signal line 4Vinit1 and a fifth initial signal line 4Vinit2.
  • the orthographic projection of the fifth initial signal line 4Vinit2 on the base substrate extends along the second direction Y.
  • the fourth initial signal line 4Vinit1 can be connected through a via hole to the first initial signal line Vinit1 that intersects its orthographic projection on the base substrate.
  • the fourth initial signal line 4Vinit1 and the first initial signal line Vinit1 form a grid structure, thereby reducing the display The voltage difference between the first initial signal terminals in the pixel driving circuit at different positions on the panel.
  • the fifth initial signal line 4Vinit2 can be connected through a via hole to the second initial signal line Vinit2 that intersects its orthographic projection on the base substrate.
  • the fifth initial signal line 4Vinit2 and the second initial signal line Vinit2 form a grid structure, thereby reducing the display
  • the voltage difference between the second initial signal terminals in the pixel driving circuit at different positions on the panel may be provided with a second power line VSS2, a fourth initial signal line 4Vinit1, and a fifth initial signal line 4Vinit2.
  • the fourth conductive layer may also include a sixth initial line, and the sixth initial line may be connected to a third initial signal line that intersects it through a via hole to reduce pixel density at different locations on the display panel. The voltage difference between the third initial signal terminal in the drive circuit.
  • This exemplary embodiment also provides another display panel.
  • the display panel may also include a base substrate, a first active layer, a first conductive layer, a second active layer, a second conductive layer, and a third layer that are stacked in sequence. Three conductive layers and a fourth conductive layer, wherein an insulating layer may be provided between the above adjacent levels.
  • Figure 18 is a structural layout of the display panel in an exemplary embodiment of the present disclosure.
  • Figure 19 is a structural layout of the first active layer in Figure 18.
  • Figure 20 is a structural layout of the first conductive layer in Figure 18.
  • Figure 21 is the structural layout of the second active layer in Figure 18
  • Figure 22 is the structural layout of the second conductive layer in Figure 18
  • Figure 23 is the structural layout of the third conductive layer in Figure 18
  • Figure 24 is the structural layout of the fourth conductive layer in Figure 18.
  • Figure 25 is the structural layout of the first active layer and the first conductive layer in Figure 18.
  • Figure 26 is the first active layer, the first conductive layer and the first conductive layer in Figure 18.
  • Figure 27 is the structural layout of the first active layer, the first conductive layer, the second active layer, and the second conductive layer in Figure 18.
  • Figure 28 is the first active layer in Figure 18.
  • the display panel may include a plurality of pixel driving circuits shown in FIG. 1 .
  • the plurality of pixel driving circuits may include a first pixel driving circuit P1 and a second pixel driving circuit P2 adjacently distributed in the first direction X, and the first pixel driving circuit P1 and the second pixel driving circuit P2 It can be set up with mirror symmetry on the mirror symmetry plane BB.
  • the mirror symmetry plane BB may be perpendicular to the base substrate.
  • the orthographic projection of the first pixel driving circuit P1 on the base substrate and the orthographic projection of the second pixel driving circuit P2 on the base substrate can be arranged symmetrically with the intersection line of the mirror symmetry plane BB and the base substrate as the symmetry axis.
  • the first pixel driving circuit P1 and the second pixel driving circuit P2 may form a repeating unit, and the display panel may include a plurality of repeating units distributed in an array in the first direction X and the second direction Y.
  • the first active layer may include a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, and a seventh active portion. 77.
  • the third active part 73 may be used to form a channel region of the driving transistor T3;
  • the fourth active part 74 may be used to form a channel region of the fourth transistor T4;
  • the fifth active part 75 may be used to form a channel region of the fourth transistor T4.
  • the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion Part 78 is used to form the channel region of the eighth transistor T8.
  • the first active layer also includes: a ninth active part 79, a tenth active part 710, an eleventh active part 711, a twelfth active part 712, a thirteenth active part 713, a seventeenth active part The source part 717 , the eighteenth active part 718 , and the twentieth active part 720 .
  • the ninth active part 79 is connected to an end of the fifth active part 75 away from the third active part 73 .
  • the tenth active part 710 is connected between the sixth active part 76 and the seventh active part 77
  • the eleventh active part 711 is connected between the sixth active part 76 and the third active part 73
  • the The twelve active parts 712 are connected to one end of the fourth active part 74 away from the third active part 73
  • the thirteenth active part 713 is connected to one end of the seventh active part 77 away from the sixth active part 76
  • the seventeenth active part 717 and the eighteenth active part 718 are connected to both ends of the eighth active part 78 respectively
  • the twentieth active part 720 is connected between the third active part 73 and the fifth active part 75 between.
  • the first active layer may be formed of polysilicon material.
  • the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be a P-type low-temperature polysilicon film. transistor.
  • the first conductive layer may include: a first conductive portion 11, a second gate line G2, an enable signal line EM, a second reset signal line Re2, a first gate line 1G1, a first Reset signal line 1Re1.
  • the second gate line G2 can be used to provide the second gate drive signal terminal in Figure 1;
  • the enable signal line EM can be used to provide the enable signal terminal in Figure 1;
  • the second reset signal line Re2 can be used to provide the enable signal terminal in Figure 1
  • the first gate line 1G1 is used to provide the first gate drive signal terminal in FIG. 1, and the first reset signal line 1Re1 is used to provide the first reset signal terminal in FIG. 1.
  • the orthographic projection of the enable signal line EM on the base substrate, the orthographic projection of the first reset signal line 1Re1 on the base substrate, the orthographic projection of the second reset signal line Re2 on the base substrate, the first gate line 1G1 on Both the orthographic projection on the base substrate and the orthographic projection of the second gate line G2 on the base substrate can extend along the first direction X.
  • the second gate line G2 may include a plurality of second gate line segments G22.
  • the orthographic projections of the plurality of second gate line segments G22 in the same second gate line G2 on the substrate are spaced apart along the first direction X and are distributed along the first direction X.
  • the orthographic projection of the second gate line segment G22 on the base substrate covers the orthographic projection of the fourth active part 74 on the base substrate, and part of the structure of the second gate line segment G22 is used to form the gate of the fourth transistor T4.
  • the orthographic projection of the enable signal line EM on the base substrate covers the orthographic projection of the fifth active part 75 on the base substrate and the orthographic projection of the sixth active part 76 on the base substrate.
  • the enable signal line EM Part of the structure may be used to form the gate of the fifth transistor T5, and another part of the structure of the enable signal line EM may be used to form the gate of the sixth transistor T6.
  • the orthographic projection of the second reset signal line Re2 on the base substrate can cover the orthographic projection of the seventh active part 77 on the base substrate and the orthographic projection of the eighth active part 78 on the base substrate.
  • the second reset signal Part of the structure of the line Re2 may be used to form the gate of the seventh transistor T7, and another part of the structure of the second reset signal line Re2 may be used to form the gate of the eighth transistor T8.
  • the orthographic projection of the first conductive portion 11 on the base substrate covers the orthographic projection of the third active portion 73 on the base substrate.
  • the first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first capacitor C. electrode.
  • the first gate line 1G1 includes a plurality of first gate line segments 1G11.
  • the orthographic projections of the plurality of first gate line segments 1G11 in the same first gate line 1G1 on the substrate are spaced apart along the first direction X and extend along the first direction X.
  • the display panel can use the first conductive layer as a mask to conduct conduction processing on the first active layer, that is, the area of the first active layer covered by the first conductive layer can form the channel region of the transistor, and the first Areas of the active layer not covered by the first conductive layer form conductor structures.
  • the second active layer may include a first active portion 81, a second active portion 82, a fourteenth active portion 814, a fifteenth active portion 815, a sixteenth active portion Active part 816.
  • the first active part 81 is used to form a channel region of the first transistor T1
  • the second active part 82 is used to form a channel region of the second transistor T2.
  • the fifteenth active part 815 is connected between the first active part 81 and the second active part 82 .
  • the fourteenth active part 814 is connected to an end of the first active part 81 away from the fifteenth active part 815
  • the sixteenth active part 816 is connected to an end of the second active part 82 away from the first active part 81 .
  • the second active layer may be formed of indium gallium zinc oxide, and accordingly, the first transistor T1 and the second transistor T2 may be N-type metal oxide thin film transistors.
  • the orthographic projection of the first gate line 1G1 on the base substrate can cover the orthographic projection of the second active part 82 on the base substrate, and part of the structure of the first gate line 1G1 can be used to form the bottom gate of the second transistor T2.
  • the orthographic projection of the first reset signal line 1Re1 on the base substrate can cover the orthographic projection of the first active part 81 on the base substrate, and part of the structure of the first reset signal line 1Re1 can be used to form the bottom of the first transistor T1 gate.
  • the second conductive layer may include: a third reset signal line 2Re1 , a third gate line 2G1 , and a third conductive portion 23 .
  • the third reset signal line 2Re1 may be used to provide the first reset signal terminal in FIG. 1
  • the third gate line 2G1 may be used to provide the first gate drive signal terminal in FIG. 1 .
  • the orthographic projection of the third reset signal line 2Re1 on the base substrate can cover the orthographic projection of the first active part 71 on the base substrate, and part of the structure of the third reset signal line 2Re1 can be used to form the top of the first transistor T1.
  • the third gate line 2G1 may include a plurality of third gate line segments 2G11.
  • the orthographic projections of the plurality of third gate line segments 2G11 in the same third gate line 2G1 on the substrate are spaced apart along the first direction X and are distributed along the first direction X.
  • the orthographic projection of the third gate line segment 2G11 on the base substrate can cover the orthographic projection of the second active part 72 on the base substrate, and part of the structure of the third gate line segment 2G11 can be used to form the top of the second transistor T2. gate.
  • the orthographic projection of the third conductive part 23 on the base substrate and the orthographic projection of the first conductive part 11 on the base substrate at least partially overlap, and the third conductive part 23 is used to form the second electrode of the capacitor C. In adjacent repeating units, adjacent third conductive portions may be connected.
  • the display panel can use the second conductive layer as a mask to perform conductive treatment on the second active layer, that is, the area covered by the second conductive layer in the second active layer can form the channel region of the transistor. Areas of the active layer not covered by the second conductive layer form conductor structures.
  • the third conductive layer may include a first bridge portion 31, a second bridge portion 32, a third bridge portion 33, a fourth bridge portion 34, a sixth bridge portion 36, and an eighth bridge portion. 38.
  • Both the orthographic projection of the line segment 3G11 on the base substrate and the orthographic projection of the second gate connection line 3G2 on the base substrate can extend along the first direction X.
  • the first initial signal line Vinit1 is used to provide a first initial signal terminal
  • the second initial signal line Vinit2 is used to provide a second initial signal terminal
  • the third initial signal line Vinit3 is used to provide a third initial signal terminal.
  • the first bridge portion 31 can be connected to the ninth active portion 79 and the third conductive portion 23 through via holes respectively, so as to connect the first electrode of the fifth transistor and the second electrode of the capacitor C.
  • the second bridge portion 32 may be connected to the tenth active portion 710 through a via hole to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.
  • the third bridge portion 33 can be connected to the eleventh active portion 711 and the sixteenth active portion 816 through via holes respectively to connect the second electrode of the second transistor T2, the first electrode of the sixth transistor T6, and the driving transistor T3. the second pole.
  • the fourth bridge portion 34 can be connected to the fifteenth active portion 815 and the first conductive portion 11 through via holes respectively, so as to connect the first electrode of the second transistor T2 and the gate electrode of the driving transistor. As shown in FIGS. 22 and 28 , an opening 231 is formed on the third conductive part 23 , and the orthographic projection of the via hole connected between the first conductive part 11 and the fourth bridge part 34 on the substrate is located on the substrate. Within the orthographic projection on the base substrate, the conductive structure in the via hole and the third conductive portion 23 are insulated from each other.
  • the eighth bridge portion 38 can be connected to the seventeenth active portion 717 and the twentieth active portion 720 through via holes respectively to connect the second pole of the eighth transistor and the first pole of the driving transistor terminal.
  • the first initial signal line Vinit1 may be connected to the fourteenth active part 814 through a via hole to connect the first initial signal terminal and the first pole of the first transistor T1.
  • the second initial signal line Vinit2 may be connected to the thirteenth active part 713 through a via hole to connect the second initial signal terminal and the first electrode of the seventh transistor.
  • the third initial signal line Vinit3 is connected to the eighteenth active part 718 through a via hole to connect the first electrode of the eighth transistor and the third initial signal terminal.
  • the orthographic projection of the fourth bridge portion 34 on the base substrate may intersect the orthographic projection of the first gate line segment 1G11 on the base substrate, and the orthographic projection of the first gate connection line segment 3G11 on the base substrate is located in the first direction.
  • the first gate connection line segments 3G11 may be connected to the first gate line segments 1G11 adjacent in the first direction X through via holes respectively, and may be connected to the third gate line segments 2G11 adjacent in the first direction X through via holes respectively.
  • the second gate connection line 3G2 may connect multiple second gate line segments G22 located in the same second gate line G2 through via holes respectively.
  • the sheet resistance of the third conductive layer may be smaller than the sheet resistance of the first conductive layer and the second conductive layer.
  • the first gate connection line segment 3G11 can reduce the own resistance of the gate line connected to the second transistor T2, thereby improving the response speed of the second transistor T2.
  • the second gate connection line 3G2 can reduce the own resistance of the gate line connected to the fourth transistor T4, thereby improving the response speed of the fourth transistor T4.
  • the eighth bridge portion 38 may include a sub-bridge portion 381 , and the orthographic projection of the sub-bridge portion 381 on the substrate may extend along the first direction X and be located on the second reset signal line Re2 on the substrate. For orthographic projection, this setting can improve the transmittance of the display panel.
  • the fourth conductive layer may include a plurality of third power lines VDD, a plurality of data lines Da, a sixth initial signal line 4Vinit3, and a ninth bridge portion 49.
  • the orthographic projection of the third power line VDD on the base substrate, the orthographic projection of the data line Da on the base substrate, and the orthographic projection of the sixth initial signal line 4Vinit3 on the base substrate can all extend along the second direction Y.
  • the third power line VDD can be used to provide the first power terminal
  • the data line Da can be used to provide the data signal terminal.
  • each column of pixel driving circuits can be provided with a third power line VDD, a sixth initial signal line 4Vinit3, and a data line Da.
  • the third power line VDD may be connected to the first bridge portion 31 through a via hole to connect the first pole of the fifth transistor and the first power terminal.
  • the third power line VDD may include a first extension part VDD1, a second extension part VDD2, and a third extension part VDD3.
  • the second extension part VDD2 is connected between the first extension part VDD1 and the third extension part VDD3.
  • the second extension part The size of the orthographic projection of VDD2 on the base substrate in the first direction X may be larger than the size of the orthogonal projection of the first extension VDD1 on the base substrate in the first direction
  • the size of the orthographic projection of the extending portion VDD2 on the base substrate in the first direction X may be larger than the size of the third extending portion VDD3 on the base substrate in the first direction X.
  • the orthographic projection of the second extension part VDD2 on the base substrate can cover the orthographic projection of the first active part 81 on the base substrate and the orthographic projection of the second active part 82 on the base substrate.
  • the second extension part VDD2 The influence of light on the characteristics of the first transistor T1 and the second transistor T2 can be reduced.
  • the orthographic projection of the third power line VDD on the base substrate can cover the orthographic projection of the fourth bridge portion 34 on the base substrate, and the third power line VDD can be used to shield the noise of other signals on the fourth bridge portion 34 interference, thereby improving the stability of the gate voltage of the driving transistor T3.
  • the second extension portions VDD2 in two adjacent pixel driving circuits can be connected to each other, so that the third power line VDD and the third conductive portion 23 can form a grid structure, and the power lines of the grid structure can Reduce the voltage drop on the power signal across it.
  • the data line Da may be connected to the sixth bridge portion 36 through a via hole to connect the first electrode of the fourth transistor and the data signal terminal.
  • the ninth bridge part 49 may be connected to the second bridge part 32 through a via hole to connect the second pole of the seventh transistor.
  • the sixth initial signal line Vinit3 may be connected to the third initial signal line Vinit3 that intersects it through via holes to form a grid structure.
  • the orthographic projection of the sixth initial signal line 4Vinit3 on the base substrate may be located between the orthographic projection of the data line Da on the base substrate and the orthographic projection of the third power line VDD on the base substrate.
  • the sixth initial signal line 4Vinit3 can be used to shield signal interference between the data line Da and the third power line VDD.
  • FIG. 29 it is a partial cross-sectional view of the display panel shown in FIG. 18 taken along the dotted line AA.
  • the display panel may also include a first insulating layer 91 , a buffer layer 92 , a second insulating layer 93 , a dielectric layer 94 , a passivation layer 95 , and a planarization layer 96 .
  • the third conductive layer, the passivation layer 95, the flat layer 96, and the fourth conductive layer are stacked in sequence.
  • the thickness of the buffer layer 92 may be greater than the thickness of the second insulation layer 93 .
  • the first insulating layer 91 and the second insulating layer 93 may have a single-layer structure or a multi-layer structure, and the material of the first insulating layer 91 and the second insulating layer 93 may be at least one of silicon nitride, silicon oxide, and silicon oxynitride.
  • the buffer layer 92 may include at least one of a silicon oxide layer and a silicon nitride layer; the dielectric layer 94 may be a silicon nitride layer; the passivation layer 95 may be a silicon oxide layer; the material of the flat layer 96 may be organic Materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG) and other materials.
  • the base substrate 90 may include a glass substrate, a barrier layer, and a polyimide layer that are stacked in sequence.
  • the barrier layer may be an inorganic material.
  • the material of the first conductive layer and the second conductive layer may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or laminate.
  • the material of the third conductive layer and the fourth conductive layer may include metal materials, for example, it may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or laminate, or it may be titanium/aluminum /titanium lamination.
  • the display panel may further include an electrode layer located on the side of the fourth conductive layer facing away from the base substrate, a pixel defining layer located on the side of the electrode layer facing away from the base substrate, and a luminescent material layer located on the side of the pixel defining layer facing away from the base substrate,
  • the common electrode layer is located on a side of the light-emitting material layer facing away from the base substrate.
  • the second insulating layer 93 may have a patterned structure.
  • the second insulating layer 93 may be located only between the second active layer and the second conductive layer.
  • the second insulating layer 93 may not be disposed between the third conductive part 23 and the first conductive part 11. This arrangement can reduce the distance between the third conductive part 23 and the first conductive part 11, thereby increasing the capacity of the capacitor C.
  • the thickness of the local second insulating layer 93 and/or the buffer layer 92 between the third conductive part 23 and the first conductive part 11 may also be reduced.
  • the distance between the third conductive part 23 and the first conductive part 11 in the thickness direction of the display panel may be smaller than the distance between the third gate line 2G1 and the first gate line 1G1 in the thickness direction of the display panel.
  • FIG. 30 it is a schematic structural diagram of a display panel in another exemplary embodiment of the present disclosure.
  • the third gate line 2G1 in the display panel shown in FIG. 30 extends continuously in the first direction X, that is, the third gate line 2G1 is not disconnected.
  • the third gate line 2G1 can connect multiple first gate line segments 1G11 located in the same first gate line 1G1 through via holes.
  • Figure 31 is a schematic structural diagram of a display panel in another exemplary embodiment of the present disclosure
  • Figure 32 is a structural layout of the first active layer in Figure 31.
  • a break D1 is formed between the fourth active part 74 and the third active part 73 in the display panel shown in Figure 31, and the third conductive layer includes a tenth bridge part 310,
  • the tenth bridge portion 310 is connected between the fourth active portion 74 and the third active portion 73 through a via hole.
  • the first gate line 1G1 continuously extends in the first direction X
  • the third gate line 2G1 continuously extends in the first direction X.
  • the orthographic projection of the first gate line 1G1 on the base substrate is located within the orthographic projection of the fracture D1 on the base substrate, and intersects with the orthographic projection of the tenth bridge portion 310 on the base substrate.
  • the orthographic projection of the third gate line 2G1 on the base substrate is located within the orthographic projection of the break D1 on the base substrate, and intersects with the orthographic projection of the tenth bridge portion 310 on the base substrate.
  • the black square drawn on the side of the third conductive layer facing away from the base substrate indicates that the third conductive layer is connected to other elements on the side facing the base substrate.
  • the black square drawn on the side of the fourth conductive layer facing away from the base substrate indicates the via holes at other levels connecting the fourth conductive layer to the side facing the base substrate.
  • the black square only represents the location of the via hole. Different via holes represented by black squares at different positions can penetrate different insulation layers.
  • the scale of the drawings in this disclosure can be used as a reference in the actual process, but is not limited thereto, for example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line, It can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the figures described in this disclosure are only structural schematic diagrams.
  • the first, second and other qualifiers are only used to define different structure names and have no specific order meaning.
  • the same structural layer can be formed through one patterning process.
  • This exemplary embodiment also provides a display device, which includes the above-mentioned display panel.
  • the display device can be a display device such as a mobile phone, a tablet computer, or a television.

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Abstract

一种显示面板及显示装置，显示面板包括像素驱动电路，像素驱动电路包括第一类型晶体管和第二类型晶体管，显示面板还包括：衬底基板(90)、第一有源层、第二有源层、第一导电层，第一有源层位于衬底基板(90)的一侧，第一有源层的至少部分结构用于形成第一类型晶体管的沟道区；第二有源层位于第一有源层背离衬底基板(90)的一侧，第二有源层的至少部分结构用于形成第二类型晶体管的沟道区；第一导电层位于第一有源层和第二有源层之间，第一导电层的部分结构用于形成第一类型晶体管的栅极，第一导电层的部分结构用于形成第二类型晶体管的底栅。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
在LTPO(Low temperature polycrystalline TFT+Oxide TFT)技术中，显示面板一般包括依次层叠设置的第一栅极层、第二栅极层、第三栅极层，第二栅极层位于第一栅极层和第三栅极层之间。第一栅极层用于形成P型晶体管的栅极，第二栅极层用于形成N型晶体管的底栅，第三栅极层用于形成N型晶体管的顶栅。然而，三层栅极层的结构较为复杂，需要通过多次掩膜形成。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
根据本公开的一个方面，提供一种显示面板，所述显示面板包括像素驱动电路，所述像素驱动电路包括第一类型晶体管和第二类型晶体管，所述显示面板还包括：衬底基板、第一有源层、第二有源层、第一导电层。第一有源层位于所述衬底基板的一侧，所述第一有源层的至少部分结构用于形成所述第一类型晶体管的沟道区；第二有源层位于所述第一有源层背离所述衬底基板的一侧，所述第二有源层的至少部分结构用于形成所述第二类型晶体管的沟道区；第一导电层位于所述第一有源层和所述第二有源层之间，所述第一导电层的部分结构用于形成所述第一类型晶体管的栅极，所述第一导电层的部分结构用于形成所述第二类型晶体管的底栅。
本公开一种示例性实施例中，所述像素驱动电路还包括驱动晶体管、第八晶体管，所述第八晶体管的第一极连接第三初始信号线，所述第八晶 体管的第二极连接所述驱动晶体管的第一极。
本公开一种示例性实施例中，所述像素驱动电路还包括电容，所述第一导电层包括第一导电部，所述第一导电部用于形成所述电容的第一电极。所述显示面板还包括：第二导电层，第二导电层位于所述第二有源层背离所述衬底基板的一侧，所述第二导电层包括第三导电部，所述第三导电部在所述衬底基板上的正投影和所述第一导电部在所述衬底基板上的正投影至少部分交叠，所述第三导电部用于形成所述电容的第二电极；其中，所述第二导电层的部分结构还用于形成所述第二类型晶体管的顶栅。
本公开一种示例性实施例中，所述像素驱动电路还包括驱动晶体管、第一晶体管、第二晶体管，所述驱动晶体管为所述第一类型晶体管，所述第一晶体管、第二晶体管为所述第二类型晶体管；所述第一晶体管的第一极连接第一初始信号线，所述第一晶体管的第二极连接所述驱动晶体管的栅极，所述第二晶体管的第一极连接所述驱动晶体管的栅极，所述第二晶体管的第二极连接所述驱动晶体管的第二极，所述电容的第一电极连接所述驱动晶体管的栅极；所述第一有源层包括：第三有源部，所述第三有源部用于形成所述驱动晶体管的沟道区；所述第二有源层包括：第一有源部、第二有源部，所述第一有源部用于形成所述第一晶体管的沟道区，所述第二有源部用于形成所述第二晶体管的沟道区；所述第一导电层包括：第一导电部、第一栅线、第一复位信号线；其中，所述第一导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第一导电部用于形成所述驱动晶体管的栅极和所述电容的第一电极；所述第一复位信号线在所述衬底基板上的正投影覆盖所述第一有源部在所述衬底基板上的正投影，所述第一复位信号线的部分结构用于形成所述第一晶体管的底栅；所述第一栅线在所述衬底基板上的正投影覆盖所述第二有源部在所述衬底基板上的正投影，所述第一栅线的部分结构用于形成所述第二晶体管的底栅；所述第二导电层包括：第三导电部、第三栅线、第三复位信号线；其中，所述第三导电部在所述衬底基板上的正投影和所述第一导电部在所述衬底基板上的正投影至少部分交叠，所述第三导电部用于形成所述电容的第二电极；所述第三复位信号线在所述衬底基板上的正投影覆盖所述第一有源部在所述衬底基板上的正投影，所述第三复位信号线的 部分结构用于形成所述第一晶体管的顶栅；所述第三栅线在所述衬底基板上的正投影覆盖所述第二有源部在所述衬底基板上的正投影，所述第三栅线的部分结构用于形成所述第二晶体管的底栅。
本公开一种示例性实施例中，所述像素驱动电路还包括第四晶体管，所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极，所述第四晶体管为所述第一类型晶体管；所述第一有源层还包括第四有源部，所述第四有源部用于形成所述第四晶体管的沟道区；所述第一导电层还包括：第二栅线，所述第二栅线在所述衬底基板上的正投影覆盖所述第四有源部在所述衬底基板上的正投影，所述第二栅线的部分结构用于形成所述第四晶体管的栅极；其中，所述第一栅线在所述衬底基板上的正投影、所述第二栅线在所述衬底基板上的正投影、所述第一复位信号线在所述衬底基板上的正投影均沿第一方向延伸；所述第二栅线在所述衬底基板上的正投影位于所述第一栅线在所述衬底基板上的正投影远离所述第一导电部在所述衬底基板上的正投影的一侧；所述第一复位信号线在所述衬底基板上的正投影位于所述第二栅线在所述衬底基板上的正投影远离所述第一导电部在所述衬底基板上的正投影的一侧。
本公开一种示例性实施例中，所述第一栅线包括多条第一栅线段，同一所述第一栅线中多条所述第一栅线段在所述衬底基板上的正投影沿所述第一方向延伸且沿所述第一方向间隔分布；所述第二有源层还包括第十五有源部，所述第十五有源连接于所述第一有源部和所述第二有源部之间；所述第一导电层还包括：第二导电部，所述第二导电部在所述衬底基板上的正投影沿第二方向延伸，且位于在所述第一方向上相邻两所述第一栅线段在所述衬底基板上的正投影之间，所述第二方向和所述第一方向相交，所述第二导电部分别连接所述第十五有源部和所述第一导电部；所述显示面板还包括：第三导电层，第三导电层位于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括第一栅极连接线，所述第一栅极连接线在所述衬底基板上的正投影沿所述第一方向延伸且与所述第二导电部在所述衬底基板上的正投影相交，所述第一栅极连接线分别通过过孔连接同一所述第一栅线中的多条所述第一栅线段。
本公开一种示例性实施例中，所述第一栅线包括多条第一栅线段，同 一所述第一栅线中多条所述第一栅线段在所述衬底基板上的正投影沿所述第一方向延伸且沿所述第一方向间隔分布；所述第二有源部还包括第十五有源部，所述第十五有源连接于所述第一有源部和所述第二有源部之间；所述显示面板还包括：第三导电层，第三导电层位于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括第一栅极连接线段、第四桥接部，所述第四桥接部在所述衬底基板上的正投影沿第二方向延伸，所述第二方向和所述第一方向相交，且所述第四桥接部分别通过过孔连接所述第十五有源部和所述第一导电部；其中，所述第四桥接部在所述衬底基板上的正投影和所述第一栅线段在所述衬底基板上的正投影相交，所述第一栅极连接线段在所述衬底基板上的正投影位于在所述第一方向上相邻两所述第四桥接部在所述衬底基板上的正投影之间，且所述第一栅极连接线段连接于在所述第一方向上相邻的两所述第一栅线段之间。
本公开一种示例性实施例中，所述第一栅线包括多条第一栅线段，同一所述第一栅线中多条所述第一栅线段在所述衬底基板上的正投影沿所述第一方向延伸且沿所述第一方向间隔分布；所述第二导电层包括第三栅线，所述第三栅线在所述衬底基板上的正投影沿所述第一方向延伸，所述第三栅线通过过孔连接同一所述第一栅线中的多条所述第一栅线段。
本公开一种示例性实施例中，所述显示面板还包括：第三导电层，第三导电层位于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括第十桥接部，所述第十桥接部连接于所述第四有源部和所述第三有源部之间；所述第一栅线在所述衬底基板上的正投影和所述第十桥接部在所述衬底基板上的正投影相交。
本公开一种示例性实施例中，所述第三栅线包括多条第三栅线段，同一所述第三栅线中的多条所述第三栅线段在所述衬底基板上的正投影沿所述第一方向延伸且沿所述第一方向间隔分布；所述显示面板还包括：第三导电层，第三导电层位于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括第一栅极连接线，所述第一栅极连接线在所述衬底基板上的正投影沿所述第一方向延伸，且所述第一栅极连接线分别通过过孔连接同一所述第三栅线中的多条所述第三栅线段。
本公开一种示例性实施例中，所述第三导电层的方块电阻小于所述第 一导电层的方块电阻；所述第三导电层的方块电阻小于所述第二导电层的方块电阻。
本公开一种示例性实施例中，所述显示面板还包括：缓冲层、第二绝缘层，缓冲层位于所述第一导电层和所述第二有源层之间；第二绝缘层，位于所述第二有源层和所述第二导电层之间；其中，所述第一导电部和所述第三导电部之间所述第二绝缘层的厚度小于所述第二类型晶体管顶栅和底栅之间所述第二绝缘层的厚度；和/或，所述第一导电部和所述第三导电部之间所述缓冲层的厚度小于所述第二类型晶体管顶栅和底栅之间所述缓冲层的厚度。
本公开一种示例性实施例中，所述显示面板还包括扇出区和多条数据线，所述第一导电层还包括：第一数据扇出线，第一数据扇出线位于所述扇出区，所述第一数据扇出线连接与其对应的所述数据线；所述第二导电层还包括：第二数据扇出线，第二数据扇出线位于所述扇出区，所述第二数据扇出线连接与其对应的所述数据线。
本公开一种示例性实施例中，所述像素驱动电路包括驱动晶体管、第四晶体管，所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极，所述电容的第一电极连接所述驱动晶体管的栅极，所述电容的第二电极连接第三电源线；所述第一有源层包括第三有源部、第四有源部、第十九有源部，所述第三有源部用于形成所述驱动晶体管的沟道区，所述第四有源部用于形成所述第四晶体管的沟道区，所述第十九有源部连接于所述第三有源部和所述第四有源部之间，所述十九有源部在所述衬底基板上的正投影在第一方向上的尺寸大于所述第四有源部在所述衬底基板上的正投影在所述第一方向上的尺寸；所述第二导电层包括第三导电部、第四导电部，所述第三导电部用于形成所述电容的第二电极，所述第四导电部连接所述第三导电部，所述第四导电部在所述衬底基板上的正投影与所述第十九有源部在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述显示面板包括：位于显示区的发光单元，所述像素驱动电路包括：驱动晶体管、第一晶体管、第七晶体管、第八晶体管；所述像素驱动电路连接所述发光单元的第一电极，所述发光 单元的第二电极连接第一电源线；所述第一晶体管的第一级连接第一初始信号线，所述第一晶体管的第二极连接所述驱动晶体管的栅极；所述第七晶体管的第一极连接第二初始信号线，所述第七晶体管的第二极连接所述发光单元的第一电极；所述第八晶体管的第一极连接第三初始信号线，所述第八晶体管的第二极连接所述驱动晶体管的第一极；所述显示面板还包括：多条第一信号线、多条第二信号线，多条第一信号线位于所述显示面板的显示区，所述第一信号线在所述衬底基板上的正投影沿第一方向延伸；多条第二信号线位于所述显示面板的显示区，且所述第二信号线在所述衬底基板上的正投影沿第二方向延伸，所述第二方向与所述第一方向相交，至少部分所述第二信号线通过过孔连接与其在所述衬底基板上的正投影相交的至少部分所述第一信号线；所述第一信号线包括所述第一电源线、所述第一初始信号线、所述第二初始信号线、所述第三初始信号线中的至少一种，同一所述第二信号线连接同一种所述第一信号线，且所述第二信号线连接所述第一电源线、所述第一初始信号线、所述第二初始信号线、所述第三初始信号线中的至少一种。
本公开一种示例性实施例中，所述像素驱动电路还包括第四晶体管、驱动晶体管、第五晶体管，所述第五晶体管的第一极连接第三电源线，所述第五晶体管的第二极连接所述驱动晶体管的第一极，所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极；所述显示面板还包括：第四导电层，第四导电层位于所述第二有源层背离所述衬底基板的一侧，所述第四导电层包括所述数据线、第三电源线、第二信号线；其中，所述数据线在所述衬底基板上的正投影、所述第三电源线在所述衬底基板上的正投影沿所述第二方向延伸，且在同一列像素驱动电路中，位于所述第四导电层的所述第二信号线在所述衬底基板上的正投影位于所述数据线在所述衬底基板上的正投影和所述第三电源线在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述显示面板包括沿第一方向和第二方向阵列分布的多个重复单元，所述第一方向和所述第二方向相交；每个所述重复单元包括沿所述第一方向分布的两个所述像素驱动电路，同一所述重复单元中两个所述像素驱动电路镜像对称设置。
本公开一种示例性实施例中，所述第一方向为行方向，所述第二方向为列方向，所述像素驱动电路包括驱动晶体管，所述电容的第一电极连接所述驱动晶体管的栅极，所述电容的第二电极连接第三电源线；所述显示面板还包括：第四导电层，第四导电层位于所述第二导电层背离所述衬底基板的一侧，所述第四导电层包括所述第三电源线，每列所述像素驱动电路对应设置一条所述第三电源线，所述第三电源线包括：第一延伸部、第二延伸部、第三延伸部，所述第二延伸部连接于所述第一延伸部和所述第三延伸部之间；所述第二延伸部在所述衬底基板上的正投影在行方向上的尺寸大于第一延伸部在所述衬底基板上的正投影在行方向上的尺寸，且所述第二延伸部在所述衬底基板上的正投影在行方向上的尺寸大于所述第三延伸部在所述衬底基板上的正投影在行方向上的尺寸；其中，在同一所述重复单元中，相邻两所述第三电源线中的第二延伸部相连接，在行方向上相邻的两所述重复单元中相邻两所述第三导电部相连接。
本公开一种示例性实施例中，所述显示面板包括多个所述像素驱动电路，多个所述像素驱动电路沿第一方向和第二方向阵列分布，所述第一方向和所述第二方向相交；所述像素驱动电路还包括第五晶体管，所述第五晶体管的第一极连接第三电源线，所述第五晶体管的第二极连接所述驱动晶体管的第一极，所述显示面板还包括：第三导电层、第四导电层，第三导电层位于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括电源连接线，所述电源连接线在所述衬底基板上的正投影沿所述第一方向延伸，所述电源连接线分别通过过孔连接多个所述第三导电部，且与同一所述电源连接线连接的多个所述第三导电部在所述衬底基板上的正投影沿所述第一方向间隔分布；第四导电层位于所述第三导电层背离所述衬底基板的一侧，所述第四导电层包括所述第三电源线，所述第三电源线在所述衬底基板上的正投影沿所述第二方向延伸，且所述第三电源线连接与其在所述衬底基板上的正投影相交的所述电源连接线。
本公开一种示例性实施例中，所述显示面板还包括发光单元，所述像素驱动电路还包括：第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管；所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极；所述第五晶体管的第一极连接第三电 源线，所述第五晶体管的第二极连接所述驱动晶体管的第一极；所述第六晶体管的第一极连接所述驱动晶体管的第二极，所述第六晶体管的第二极连接所述发光单元的第一电极；所述第七晶体管的第一极连接第二初始信号线，所述第七晶体管的第二极连接所述发光单元的第一电极；所述第八晶体管的第一极连接第三初始信号线，所述第八晶体管的第二极连接所述驱动晶体管的第一极；所述第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管为所述第一类型晶体管；所述第一类型晶体管为P型晶体管，所述第二类型晶体管为N型晶体管。
根据本公开的一个方面，提供一种显示装置，其中，包括上述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
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图1为本公开显示面板一种示例性实施例中像素驱动电路的结构示意图；
图2为本公开显示面板一种示例性实施例中的结构版图；
图3为图2中第一有源层的结构版图；
图4为图2中第一导电层的结构版图；
图5为图2中第二有源层的结构版图；
图6为图2中第二导电层的结构版图；
图7为图2中第三导电层的结构版图；
图8为图2中第四导电层的结构版图；
图9为图2中第一有源层、第一导电层的结构版图；
图10为图2中第一有源层、第一导电层、第二有源层的结构版图；
图11为图2中第一有源层、第一导电层、第二有源层、第二导电层的结构版图；
图12为图2中第一有源层、第一导电层、第二有源层、第二导电层、第三导电层的结构版图；
图13为图2所示显示面板沿虚线AA剖开的部分剖视图；
图14为本公开显示面板另一种示例性实施例的结构示意图；
图15为图14中第三导电层的结构版图；
图16为图14中第四导电层的结构版图；
图17为图14中第一有源层、第一导电层、第二有源层、第二导电层、第三导电层的结构版图；
图18为本公开显示面板一种示例性实施例中的结构版图；
图19为图18中第一有源层的结构版图；
图20为图18中第一导电层的结构版图；
图21为图18中第二有源层的结构版图；
图22为图18中第二导电层的结构版图；
图23为图18中第三导电层的结构版图；
图24为图18中第四导电层的结构版图；
图25为图18中第一有源层、第一导电层的结构版图；
图26为图18中第一有源层、第一导电层、第二有源层的结构版图；
图27为图18中第一有源层、第一导电层、第二有源层、第二导电层的结构版图；
图28为图18中第一有源层、第一导电层、第二有源层、第二导电层、第三导电层的结构版图；
图29为图18所示显示面板沿虚线AA剖开的部分剖视图；
图30为本公开显示面板另一种示例性实施例中的结构示意图；
图31为本公开显示面板另一种示例性实施例中的结构示意图；
图32为图31中第一有源层的结构版图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以 多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
如图1所示，为本公开显示面板一种示例性实施例中像素驱动电路的结构示意图。该像素驱动电路可以包括：驱动晶体管T3、第一晶体管T1、第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、电容C。其中，第四晶体管T4的第一极连接数据信号端Da，第二极连接驱动晶体管T3的第一极，栅极连接第二栅极驱动信号端G2；第五晶体管T5的第一极连接第一电源端VDD，第二极连接驱动晶体管T3的第一极，栅极连接使能信号端EM；驱动晶体管T3的栅极连接节点N；第二晶体管T2的第一极连接节点N，第二极连接驱动晶体管T3的第二极，栅极连接第一栅极驱动信号端G1；第六晶体管T6的第一极连接驱动晶体管T3的第二极，第二极连接第七晶体管T7的第二极，栅极连接使能信号端EM，第七晶体管T7的第一极连接第二初始信号端Vinit2，栅极连接第二复位信号端Re2；第一晶体管T1的第二极连接节点N，第一极连接第一初始信号端Vinit1，栅极连接第一复位信号端Re1；电容C的第一电极连接节点N，第二电极连接第一电源端VDD，第八晶体管T8的第一极连接第三初始信号线Vinit3，第二极连接驱动晶体管的第一极，栅极连接第二复位信号端Re2。该像素驱动电路可以连接一发光单元OLED，用于驱动该发光单元OLED发光，发光单元OLED可以连接于第六晶体管T6的第二极和第二电源端VSS之间。其中，第一晶体管T1和第二晶体管T2可以为N型晶体管；驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8可以为P型晶体管。
该像素驱动电路驱动方法可以包括复位阶段、数据写入阶段、发光阶段。在复位阶段，第一复位信号端Re1输出高电平信号，第二复位信号端Re2输出低电平信号，第一晶体管T1和第八晶体管T8导通，第一初始信 号端Vinit1向节点N输入第一初始信号，第三初始信号端Vinit3向驱动晶体管T3的第一极输入第三初始信号。在数据写入阶段，第一栅极驱动信号端G1输出高电平信号，第二栅极驱动信号端G2输出低电平信号，第二晶体管T2、第四晶体管T4导通，同时数据信号端Da输出数据信号以向节点N写入补偿电压Vdata+Vth，其中Vdata为数据信号的电压，Vth为驱动晶体管T3的阈值电压。发光阶段：使能信号端EM输出低电平信号，第六晶体管T6、第五晶体管T5导通，驱动晶体管T3在电容C存储的补偿电压Vdata+Vth作用下驱动发光单元发光。本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth) 2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。其中，I为驱动晶体管输出电流；μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电压。
本示例性实施例还提供一种显示面板，该显示面板可以包括依次层叠设置的衬底基板、第一有源层、第一导电层、第二有源层、第二导电层、第三导电层、第四导电层，其中，上述相邻层级之间可以设置有绝缘层。如图2-12所示，图2为本公开显示面板一种示例性实施例中的结构版图，图3为图2中第一有源层的结构版图，图4为图2中第一导电层的结构版图，图5为图2中第二有源层的结构版图，图6为图2中第二导电层的结构版图，图7为图2中第三导电层的结构版图，图8为图2中第四导电层的结构版图，图9为图2中第一有源层、第一导电层的结构版图，图10为图2中第一有源层、第一导电层、第二有源层的结构版图，图11为图2中第一有源层、第一导电层、第二有源层、第二导电层的结构版图，图12为图2中第一有源层、第一导电层、第二有源层、第二导电层、第三导电层的结构版图。该显示面板可以包括图1所示的像素驱动电路。
本示例性实施例中，第一有源层可以用于形成第一类型的晶体管的沟道区，第二有源层可以用于形成第二类型的晶体管的沟道区。第一类型晶体管可以为P型晶体管，第二类型晶体管可以为N型晶体管。本示例性实施例相较于相关技术没有设置第二栅极层，即第一导电层的部分结构可以用于形成第一类型晶体管的栅极，第一导电层的部分结构可以用于形成第 二类型晶体管的底栅。该设置可以减少显示面板制作过程中的掩膜次数，简化显示面板的结构。
如图2、3、9所示，第一有源层可以包括第三有源部73、第四有源部74、第五有源部75、第六有源部76、第七有源部77、第八有源部78。其中，第三有源部73可以用于形成驱动晶体管T3的沟道区；第四有源部74可以用于形成第四晶体管T4的沟道区；第五有源部75可以用于形成第五晶体管T5的沟道区；第六有源部76可以用于形成第六晶体管T6的沟道区；第七有源部77可以用于形成第七晶体管T7的沟道区；第八有源部78用于形成第八晶体管T8的沟道区。第一有源层还包括：第九有源部79、第十有源部710、第十一有源部711、第十二有源部712、第十三有源部713、第十七有源部717、第十八有源部718、第十九有源部719、第二十有源部720。其中，第九有源部79连接于第五有源部75远离第三有源部73的一端。第十有源部710连接于第六有源部76和第七有源部77之间，第十一有源部711连接于第六有源部76和第三有源部73之间，第十二有源部712连接于第四有源部74远离第三有源部73的一端，第十三有源部713连接于第七有源部77远离第六有源部76的一端，第十七有源部717和第十八有源部718分别连接于第八有源部78的两端，第十九有源部719连接于第四有源部74和第五有源部75之间。第十九有源部719在衬底基板上的正投影在第一方向X上的尺寸大于第四有源部74在衬底基板上的正投影在第一方向X上的尺寸。第二十有源部720连接于第十九有源部719和第五有源部75之间。第一有源层可以由多晶硅材料形成，相应的，驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8可以为P型的低温多晶硅薄膜晶体管。
如图2、4、9所示，第一导电层可以包括：第一导电部11、第二栅线G2、使能信号线EM、第二复位信号线Re2、第二导电部12、第一栅线1G1、第一复位信号线1Re1。第二栅线G2可以用于提供图1中第二栅极驱动信号端；使能信号线EM可以用于提供图1中的使能信号端；第二复位信号线Re2可以用于提供图1中的第二复位信号端；第一栅线1G1用于提供图1中的第一栅极驱动信号端，第一复位信号线1Re1用于提供图1中的第一复位信号端。使能信号线EM在衬底基板上的正投影、第一复位信号线1Re1 在衬底基板上的正投影、第二复位信号线Re2在衬底基板上的正投影、第一栅线1G1在衬底基板上的正投影、第二栅线G2在衬底基板上的正投影均可以沿第一方向X延伸。本示例性实施例中，一结构在衬底基板上的正投影沿某一方向延伸，可以理解为，该结构在衬底基板上的正投影沿该方向直线延伸或弯折延伸。第二栅线G2可以多条第二栅线段G22，同一第二栅线G2中多条第二栅线段G22在衬底基板上的正投影沿第一方向X延伸且沿第一方向X间隔分布，第二栅线段G22在衬底基板上的正投影覆盖第四有源部74在衬底基板上的正投影，第二栅线段G22的部分结构用于形成第四晶体管T4的栅极。使能信号线EM在衬底基板上的正投影覆盖第五有源部75在衬底基板上的正投影、第六有源部76在衬底基板上的正投影，使能信号线EM的部分结构可以用于形成第五晶体管T5的栅极，使能信号线EM的另外部分结构可以用于形成第六晶体管T6的栅极。第二复位信号线Re2在衬底基板上的正投影可以覆盖第七有源部77在衬底基板上的正投影、第八有源部78在衬底基板上的正投影，第二复位信号线Re2的部分结构可以用于形成第七晶体管T7的栅极，第二复位信号线Re2的另外部分结构可以用于形成第八晶体管T8的栅极。第一导电部11在衬底基板上的正投影覆盖第三有源部73在衬底基板上的正投影，第一导电部11可以用于形成驱动晶体管T3的栅极和电容C的第一电极。第一栅线1G1包括多条第一栅线段1G11，同一第一栅线1G1中多条第一栅线段1G11在衬底基板上的正投影沿第一方向X间隔分布且沿第一方向X延伸。此外，该显示面板可以利用第一导电层为掩膜对第一有源层进行导体化处理，即第一有源层中被第一导电层覆盖的区域可以形成晶体管的沟道区，第一有源层中未被第一导电层覆盖的区域形成导体结构。
如图2、5、10所示，第二有源层可以包括第一有源部81、第二有源部82、第十四有源部814、第十五有源部815、第十六有源部816。第一有源部81用于形成第一晶体管T1的沟道区，第二有源部82用于形成第二晶体管T2的沟道区。第十五有源部815连接于第一有源部81和第二有源部82之间。第十四有源部814连接于第一有源部81远离第十五有源部815的一端，第十六有源部816连接于第二有源部82远离第一有源部81的一端。其中，第二有源层可以由氧化铟镓锌形成，相应的，第一晶体管 T1、第二晶体管T2可以为N型的金属氧化物薄膜晶体管。第一栅线1G1在衬底基板上的正投影可以覆盖第二有源部82在衬底基板上的正投影，第一栅线1G1的部分结构可以用于形成第二晶体管的底栅。第一复位信号线1Re1在衬底基板上的正投影可以覆盖第一有源部81在衬底基板上的正投影，第一复位信号线1Re1的部分结构可以用于形成第一晶体管T1的底栅。
如图2、6、11所示，第二导电层可以包括：第三复位信号线2Re1、第三栅线2G1、第三导电部23、第四导电部24。其中，第三复位信号线2Re1可以用于提供图1中的第一复位信号端，第三栅线2G1可以用于提供图1中的第一栅极驱动信号端。第三复位信号线2Re1可以包括多条第三复位信号线段2Re11，同一第三复位信号线2Re1中多条第三复位信号线段2Re11在衬底基板上的正投影沿第一方向X间隔分布且沿第一方向X延伸，第三复位信号线段2Re11在衬底基板上的正投影可以覆盖第一有源部71在衬底基板上的正投影，第三复位信号线段2Re11的部分结构可以用于形成第一晶体管T1的顶栅。第三栅线2G1可以包括多条第三栅线段2G11，同一第三栅线2G1中多条第三栅线段2G11在衬底基板上的正投影沿第一方向X间隔分布且沿第一方向X延伸，第三栅线段2G11在衬底基板上的正投影可以覆盖第二有源部72在衬底基板上的正投影，第三栅线段2G11的部分结构可以用于形成第二晶体管T2的顶栅。第三导电部23在衬底基板上的正投影和第一导电部11在衬底基板上的正投影至少部分交叠，第三导电部23用于形成电容C的第二电极。第四导电部24连接于第三导电部23，第四导电部24在衬底基板上的正投影可以和第十九有源部719在衬底基板上的正投影至少部分交叠，第四导电部24在衬底基板上的正投影可以位于在第一方向X上相邻第三栅线段2G11在衬底基板上的正投影之间。第四导电部24和第十九有源部719可以形成寄生电容，在数据写入阶段，向第四晶体管T4第二极输入的数据信号可以存储于该寄生电容中，当数据写入阶段结束时，存储于该寄生电容中的数据信号还可以持续通过驱动晶体管T3向节点N输入补偿电压。该设置可以在较短的数据写入阶段充分地向节点N写入补偿电压，从而可以实现显示面板较高的刷新频率。应该理解的是，在其他示例性实施例中，在第一方向X上分布的多 个第三导电部23可以相互连接。此外，该显示面板可以利用第二导电层为掩膜对第二有源层进行导体化处理，即第二有源层中被第二导电层覆盖的区域可以形成晶体管的沟道区，第二有源层中未被第二导电层覆盖的区域形成导体结构。
如图2、7、12所示，第三导电层可以包括第一桥接部31、第二桥接部32、第三桥接部33、第四桥接部34、第六桥接部36、第七桥接部37、第八桥接部38、第一初始信号线Vinit1、第二初始信号线Vinit2、第三初始信号线Vinit3、第一电源线VSS1、第一栅极连接线3G1、第二栅极连接线3G2、第一复位连接线3Re1、第二复位连接线3Re2、电源连接线3VDD。第一初始信号线Vinit1在衬底基板上的正投影、第二初始信号线Vinit2在衬底基板上的正投影、第三初始信号线Vinit3在衬底基板上的正投影、第一电源线VSS1在衬底基板上的正投影、第一栅极连接线3G1在衬底基板上的正投影、第二栅极连接线3G2在衬底基板上的正投影、第一复位连接线3Re1在衬底基板上的正投影、第二复位连接线3Re2在衬底基板上的正投影、电源连接线3VDD在衬底基板上的正投影均可以沿第一方向X延伸。第二导电部12在衬底基板上的正投影和第一栅极连接线3G1在衬底基板上的正投影相交。第一初始信号线Vinit1用于提供第一初始信号端，第二初始信号线Vinit2用于提供第二初始信号端，第三初始信号线Vinit3用于提供第三初始信号端。位于同一像素行的第一桥接部31可以连接于同一条电源连接线3VDD。电源连接线3VDD可以分别通过过孔H连接位于同一像素行中的多个第三导电部23，黑色方块表示过孔的位置。第一桥接部31可以通过过孔连接第九有源部79，以连接第五晶体管的第一极和电容C的第二电极。第二桥接部32可以通过过孔连接第十有源部710，以连接第六晶体管T6的第二极和第七晶体管T7的第二极。第三桥接部33可以分别通过过孔连接第十一有源部711、第十六有源部816，以连接第二晶体管T2的第二极、第六晶体管T6的第一极、驱动晶体管T3的第二极。第四桥接部34可以分别通过过孔连接第二导电部12、第一导电部11，第七桥接部37可以分别通过过孔连接第二导电部12和第十五有源部815，以连接第二晶体管T2的第一极和驱动晶体管的栅极。如图6、12所示，第三导电部23上形成有开口231，连接于第一导电部11和第四桥接部34 之间的过孔在衬底基板上的正投影位于开口231在衬底基板上的正投影以内，以使该过孔内的导电结构与第三导电部23相互绝缘。第八桥接部38可以分别通过过孔连接第十七有源部717和第二十有源部720，以连接第八晶体管的第二极和驱动晶体管端第一极。第一初始信号线Vinit1可以通过过孔连接第十四有源部814，以连接第一初始信号端和第一晶体管T1的第一极。第二初始信号线Vinit2可以通过过孔连接第十三有源部713，以连接第二初始信号端和第七晶体管的第一极。第三初始信号线Vinit3通过过孔连接第十八有源部718，以连接第八晶体管的第一极和第三初始信号端。第一栅极连接线3G1可以分别通过过孔连接位于同一第三栅线2G1中的第三栅线段2G11，且通过过孔连接位于同一第一栅线1G1中的第一栅线段1G11。第二栅极连接线3G2可以分别通过过孔连接位于同一第二栅线G2中的第二栅线段G22。第一复位连接线3Re1可以分别通过过孔连接位于同一第一复位信号线1Re1中的第一复位信号线段1Re11，且分别通过过孔连接位于同一第三复位信号线2Re1中的第三复位信号线段2Re11。第二复位连接线3Re2可以通过多个过孔连接第二复位信号线Re2。本示例性实施例中，第三导电层的方块电阻可以小于第一导电层、第二导电层的方块电阻。第一栅极连接线3G1可以降低第二晶体管T2所连接栅线的自身电阻，从而提高第二晶体管T2的响应速度。第二栅极连接线3G2可以降低第四晶体管T4所连接栅线的自身电阻，从而提高第四晶体管T4的响应速度。第一复位连接线3Re1可以降低第一晶体管T1所连接栅线的自身电阻，从而提高第一晶体管T1的响应速度。第二复位连接线3Re2可以降低第七晶体管、第八晶体管所连接栅线的自身电阻，从而提高第七晶体管和第八晶体管的响应速度。
如图2、8所示，第四导电层可以包括多条第三电源线VDD、多条数据线Da、第二电源线VSS2、第九桥接部49。其中，第三电源线VDD在衬底基板上的正投影、数据线Da在衬底基板上的正投影、第二电源线VSS2在衬底基板上的正投影均可以沿第二方向Y延伸。第二方向Y和第一方向X相交，例如，第二方向Y可以为列方向，第一方向X可以为行方向。第三电源线VDD可以用于提供第一电源端，数据线Da可以用于提供数据信号端，第二电源线VSS2可以用于提供第二电源端。如图2、8所示，每列像 素驱动电路可以对应设置一条第三电源线VDD，第三电源线VDD可以通过过孔连接电源连接线3VDD，以连接第五晶体管的第一极和第一电源端。第三电源线VDD和电源连接线3VDD可以形成网格结构，以降低显示面板不同位置上第一电源端之间的电压差，从而提高显示面板的显示均一性。数据线Da可以通过过孔连接第六桥接部36，以连接第四晶体管的第一极和数据信号端。第九桥接部49可以通过过孔连接第二桥接部32，以连接第七晶体管的第二极。第二电源线VSS2可以通过过孔连接与其相交的第一电源线VSS1以形成网格结构，第一电源线VSS1和第二电源线VSS2可以与显示面板中的公共电极层连接，公共电极层用于形成发光单元的第二电极，形成网格结构的第一电源线VSS1和第二电源线VSS2可以降低公共电极层上不同位置之间电压差。第三电源线VDD在衬底基板上的正投影可以覆盖第一有源部81在衬底基板上的正投影、第二有源部82在衬底基板上的正投影，第三电源线VDD可以降低光照对第一晶体管T1、第二晶体管T2的特性影响。此外，第三电源线VDD在衬底基板上的正投影可以覆盖第四桥接部34在衬底基板上的正投影，第三电源线VDD可以用于屏蔽其他信号对第四桥接部34的噪音干扰，从而提高驱动晶体管T3栅极电压的稳定性。
应该理解的是，在其他示例性实施例中，第一初始信号线Vinit1、第二初始信号线Vinit2、第三初始信号线Vinit3、第一电源线VSS1还可以位于其他导电层，或者第一初始信号线Vinit1、第二初始信号线Vinit2、第三初始信号线Vinit3、第一电源线VSS1可以通过多层导电层并联形成。例如，第一初始信号线Vinit1、第二初始信号线Vinit2、第三初始信号线Vinit3、第一电源线VSS1还可以位于第一有源层、第一导电层、第二导电层、第二有源层中任意一层或多层。
如图13所示，为图2所示显示面板沿虚线AA剖开的部分剖视图。该显示面板还可以包括第一绝缘层91、缓冲层92、第二绝缘层93、介电层94、钝化层95、平坦层96。其中，衬底基板90、第一有源层、第一绝缘层91、第一导电层、缓冲层92、第二有源层、第二绝缘层93、第二导电层、介电层94、第三导电层、钝化层95、平坦层96、第四导电层依次层叠设置。缓冲层92的厚度可以大于第二绝缘层93的厚度。第一绝缘层91、 第二绝缘层93可以为单层结构或多层结构，且第一绝缘层91、第二绝缘层93的材料可以为氮化硅，氧化硅，氮氧化硅中的至少一种；缓冲层92可以包括氧化硅层、氮化硅层中的至少一种。本示例性实施例中，缓冲层可以包括氧化硅层和氮化硅层，氮化硅层位于第一导电层和氧化硅层之间。通过减薄缓冲层可以提高电容的容量。例如，氧化硅层的厚度可以为700埃-3000埃，氧化硅层的厚度可以为700埃、1500埃、2500埃、3000埃等，相应的，氮化硅层的厚度可以为700埃-2000埃，氮化硅层的厚度可以为700埃、1500埃、2000埃等。再例如，氧化硅层的厚度可以为700埃-1500埃，氧化硅层的厚度可以为700埃、1100埃、1500埃等，相应的，氮化硅层的厚度可以为700埃-1000埃，氮化硅层的厚度可以为700埃、900埃1000埃等。此外，还可以通过去除电容两电极板之间的氧化硅层以提高电容的容量。介电层94可以氮化硅层；钝化层95可以为氧化硅层；平坦层96的材料可以为有机材料，例如聚酰亚胺(PI)、聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)、硅-玻璃键合结构(SOG)等材料。衬底基板90可以包括依次层叠设置的玻璃基板、阻挡层、聚酰亚胺层，阻挡层可以为无机材料。第一导电层、第二导电层的材料可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等。第三导电层、第四导电层的材料可以包括金属材料，例如可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层。该显示面板还可以包括位于第四导电层背离衬底基板一侧的电极层、位于电极层背离衬底基板一侧的像素限定层、位于像素限定层背离衬底基板一侧的发光材料层，公共电极层位于发光材料层背离衬底基板的一侧。
本示例性实施例中，显示面板还可以包括扇出区，第一导电层可以包括：位于扇出区的第一数据扇出线，第一数据扇出线连接与其对应的所述数据线；所述第二导电层还可以包括：位于扇出区的第二数据扇出线，所述第二数据扇出线连接与其对应的所述数据线。本公开将扇出区的数据扇出线同时设置于第一导电层和第二导电层。一方面可以提高数据扇出线的集成度；另一方面，由于本公开中第一导电层和第二导电层之间间距较大，从而该设置可以降低数据扇出线之间的信号串扰。
本示例性实施例中，第二绝缘层93可以为图案化结构，例如，第二 绝缘层93可以仅位于第二有源层和第二导电层之间。第三导电部23和第一导电部11之间可以不设置第二绝缘层93，该设置可以降低第三导电部23和第一导电部11之间的距离，从而提高电容C的容量。应该理解的是，在其他示例性实施例中，也可以通过减小第三导电部23和第一导电部11之间局部的第二绝缘层93和/或缓冲层92的厚度，以减小第三导电部23和第一导电部11之间之间的距离。例如，第三导电部23和第一导电部11在显示面板厚度方向上的距离可以小于第三栅线2G1和第一栅线1G1在显示面板厚度方向上的距离。同理，在其他示例性实施例中，也可以通过减小第四导电部24和第十九有源部719之间局部的第一绝缘层91、缓冲层92、第二绝缘层93中至少一层的厚度，以减小第四导电部24和第十九有源部719之间的距离，从而提高第四导电部24和第十九有源部719形成电容的容量。例如，第四导电部24和第十九有源部719在显示面板厚度方向上的距离小于第四导电部24和第三有源部73在显示面板厚度方向上的距离，其中，显示面板的厚度方向与衬底基板垂直。
如图14-17所示，图14为本公开显示面板另一种示例性实施例的结构示意图。图15为图14中第三导电层的结构版图，图16为图14中第四导电层的结构版图。图17为图14中第一有源层、第一导电层、第二有源层、第二导电层、第三导电层的结构版图。
图14所示显示面板与图2所示显示面板区别在于：图14所示显示面板中的第四导电层还包括第四初始信号线4Vinit1、第五初始信号线4Vinit2，第四初始信号线4Vinit1、第五初始信号线4Vinit2在衬底基板上的正投影均沿第二方向Y延伸。第四初始信号线4Vinit1可以通过过孔连接与其在衬底基板上正投影相交的第一初始信号线Vinit1，第四初始信号线4Vinit1和第一初始信号线Vinit1形成网格结构，从而可以降低显示面板不同位置像素驱动电路中第一初始信号端之间的电压差。第五初始信号线4Vinit2可以通过过孔连接与其在衬底基板上正投影相交的第二初始信号线Vinit2，第五初始信号线4Vinit2和第二初始信号线Vinit2形成网格结构，从而可以降低显示面板不同位置像素驱动电路中第二初始信号端之间的电压差。本示例性实施例中，如图14所示，每相邻三列像素驱动电路可以对应设置一条第二电源线VSS2、一条第四初始信号线 4Vinit1、一条第五初始信号线4Vinit2。
应该理解的是，在其他示例性实施例中，第四导电层还可以包括第六初始线，第六初始线可以通过过孔连接与其相交的第三初始信号线，以降低显示面板不同位置像素驱动电路中第三初始信号端之间的电压差。
本示例性实施例还提供另一种显示面板，该显示面板同样可以包括依次层叠设置的衬底基板、第一有源层、第一导电层、第二有源层、第二导电层、第三导电层、第四导电层，其中，上述相邻层级之间可以设置有绝缘层。如图18-28所示，图18为本公开显示面板一种示例性实施例中的结构版图，图19为图18中第一有源层的结构版图，图20为图18中第一导电层的结构版图，图21为图18中第二有源层的结构版图，图22为图18中第二导电层的结构版图，图23为图18中第三导电层的结构版图，图24为图18中第四导电层的结构版图，图25为图18中第一有源层、第一导电层的结构版图，图26为图18中第一有源层、第一导电层、第二有源层的结构版图，图27为图18中第一有源层、第一导电层、第二有源层、第二导电层的结构版图，图28为图18中第一有源层、第一导电层、第二有源层、第二导电层、第三导电层的结构版图。该显示面板可以包括多个图1所示的像素驱动电路。如图18所示，多个像素驱动电路中可以包括在第一方向X上相邻分布第一像素驱动电路P1和第二像素驱动电路P2，第一像素驱动电路P1和第二像素驱动电路P2可以以镜像对称面BB镜像对称设置。其中，镜像对称面BB可以垂直于衬底基板。且第一像素驱动电路P1在衬底基板上的正投影和第二像素驱动电路P2在衬底基板上的正投影可以以镜像对称面BB与衬底基板的交线为对称轴对称设置。其中，第一像素驱动电路P1和第二像素驱动电路P2可以形成一重复单元，该显示面板可以包括在第一方向X和第二方向Y上阵列分布的多个重复单元。
如图18、19、25所示，第一有源层可以包括第三有源部73、第四有源部74、第五有源部75、第六有源部76、第七有源部77、第八有源部78。其中，第三有源部73可以用于形成驱动晶体管T3的沟道区；第四有源部74可以用于形成第四晶体管T4的沟道区；第五有源部75可以用于形成第五晶体管T5的沟道区；第六有源部76可以用于形成第六晶体管T6的沟道区；第七有源部77可以用于形成第七晶体管T7的沟道区；第八有源部 78用于形成第八晶体管T8的沟道区。第一有源层还包括：第九有源部79、第十有源部710、第十一有源部711、第十二有源部712、第十三有源部713、第十七有源部717、第十八有源部718、第二十有源部720。其中，第九有源部79连接于第五有源部75远离第三有源部73的一端。第十有源部710连接于第六有源部76和第七有源部77之间，第十一有源部711连接于第六有源部76和第三有源部73之间，第十二有源部712连接于第四有源部74远离第三有源部73的一端，第十三有源部713连接于第七有源部77远离第六有源部76的一端，第十七有源部717和第十八有源部718分别连接于第八有源部78的两端，第二十有源部720连接于第三有源部73和第五有源部75之间。第一有源层可以由多晶硅材料形成，相应的，驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8可以为P型的低温多晶硅薄膜晶体管。
如图18、20、25所示，第一导电层可以包括：第一导电部11、第二栅线G2、使能信号线EM、第二复位信号线Re2、第一栅线1G1、第一复位信号线1Re1。第二栅线G2可以用于提供图1中第二栅极驱动信号端；使能信号线EM可以用于提供图1中的使能信号端；第二复位信号线Re2可以用于提供图1中的第二复位信号端；第一栅线1G1用于提供图1中的第一栅极驱动信号端，第一复位信号线1Re1用于提供图1中的第一复位信号端。使能信号线EM在衬底基板上的正投影、第一复位信号线1Re1在衬底基板上的正投影、第二复位信号线Re2在衬底基板上的正投影、第一栅线1G1在衬底基板上的正投影、第二栅线G2在衬底基板上的正投影均可以沿第一方向X延伸。第二栅线G2可以包括多条第二栅线段G22，同一第二栅线G2中多条第二栅线段G22在衬底基板上的正投影沿第一方向X间隔分布且沿第一方向X延伸，第二栅线段G22在衬底基板上的正投影覆盖第四有源部74在衬底基板上的正投影，第二栅线段G22的部分结构用于形成第四晶体管T4的栅极。使能信号线EM在衬底基板上的正投影覆盖第五有源部75在衬底基板上的正投影、第六有源部76在衬底基板上的正投影，使能信号线EM的部分结构可以用于形成第五晶体管T5的栅极，使能信号线EM的另外部分结构可以用于形成第六晶体管T6的栅极。第二复位信号线Re2在衬底基板上的正投影可以覆盖第七有源部77在衬底基板上 的正投影、第八有源部78在衬底基板上的正投影，第二复位信号线Re2的部分结构可以用于形成第七晶体管T7的栅极，第二复位信号线Re2的另外部分结构可以用于形成第八晶体管T8的栅极。第一导电部11在衬底基板上的正投影覆盖第三有源部73在衬底基板上的正投影，第一导电部11可以用于形成驱动晶体管T3的栅极和电容C的第一电极。第一栅线1G1包括多条第一栅线段1G11，同一第一栅线1G1中多条第一栅线段1G11在衬底基板上的正投影沿第一方向X间隔分布且沿第一方向X延伸。此外，该显示面板可以利用第一导电层为掩膜对第一有源层进行导体化处理，即第一有源层中被第一导电层覆盖的区域可以形成晶体管的沟道区，第一有源层中未被第一导电层覆盖的区域形成导体结构。
如图18、21、26所示，第二有源层可以包括第一有源部81、第二有源部82、第十四有源部814、第十五有源部815、第十六有源部816。第一有源部81用于形成第一晶体管T1的沟道区，第二有源部82用于形成第二晶体管T2的沟道区。第十五有源部815连接于第一有源部81和第二有源部82之间。第十四有源部814连接于第一有源部81远离第十五有源部815的一端，第十六有源部816连接于第二有源部82远离第一有源部81的一端。其中，第二有源层可以由氧化铟镓锌形成，相应的，第一晶体管T1、第二晶体管T2可以为N型的金属氧化物薄膜晶体管。第一栅线1G1在衬底基板上的正投影可以覆盖第二有源部82在衬底基板上的正投影，第一栅线1G1的部分结构可以用于形成第二晶体管T2的底栅。第一复位信号线1Re1在衬底基板上的正投影可以覆盖第一有源部81在衬底基板上的正投影，第一复位信号线1Re1的部分结构可以用于形成第一晶体管T1的底栅。
如图18、22、27所示，第二导电层可以包括：第三复位信号线2Re1、第三栅线2G1、第三导电部23。其中，第三复位信号线2Re1可以用于提供图1中的第一复位信号端，第三栅线2G1可以用于提供图1中的第一栅极驱动信号端。第三复位信号线2Re1在衬底基板上的正投影可以覆盖第一有源部71在衬底基板上的正投影，第三复位信号线2Re1的部分结构可以用于形成第一晶体管T1的顶栅。第三栅线2G1可以包括多条第三栅线段2G11，同一第三栅线2G1中多条第三栅线段2G11在衬底基板上的正投 影沿第一方向X间隔分布且沿第一方向X延伸，第三栅线段2G11在衬底基板上的正投影可以覆盖第二有源部72在衬底基板上的正投影，第三栅线段2G11的部分结构可以用于形成第二晶体管T2的顶栅。第三导电部23在衬底基板上的正投影和第一导电部11在衬底基板上的正投影至少部分交叠，第三导电部23用于形成电容C的第二电极。在相邻重复单元中，相邻第三导电部可以相连接。此外，该显示面板可以利用第二导电层为掩膜对第二有源层进行导体化处理，即第二有源层中被第二导电层覆盖的区域可以形成晶体管的沟道区，第二有源层中未被第二导电层覆盖的区域形成导体结构。
如图18、23、28所示，第三导电层可以包括第一桥接部31、第二桥接部32、第三桥接部33、第四桥接部34、第六桥接部36、第八桥接部38、第一初始信号线Vinit1、第二初始信号线Vinit2、第三初始信号线Vinit3、第一栅极连接线段3G11、第二栅极连接线3G2。第一初始信号线Vinit1在衬底基板上的正投影、第二初始信号线Vinit2在衬底基板上的正投影、第三初始信号线Vinit3在衬底基板上的正投影、第一栅极连接线段3G11在衬底基板上的正投影、第二栅极连接线3G2在衬底基板上的正投影均可以沿第一方向X延伸。第一初始信号线Vinit1用于提供第一初始信号端，第二初始信号线Vinit2用于提供第二初始信号端，第三初始信号线Vinit3用于提供第三初始信号端。第一桥接部31可以分别通过过孔连接第九有源部79、第三导电部23，以连接第五晶体管的第一极和电容C的第二电极。第二桥接部32可以通过过孔连接第十有源部710，以连接第六晶体管T6的第二极和第七晶体管T7的第二极。第三桥接部33可以分别通过过孔连接第十一有源部711、第十六有源部816，以连接第二晶体管T2的第二极、第六晶体管T6的第一极、驱动晶体管T3的第二极。第四桥接部34可以分别通过过孔连接第十五有源部815、第一导电部11，以连接第二晶体管T2的第一极和驱动晶体管的栅极。如图22、28所示，第三导电部23上形成有开口231，连接于第一导电部11和第四桥接部34之间的过孔在衬底基板上的正投影位于开口231在衬底基板上的正投影以内，以使该过孔内的导电结构与第三导电部23相互绝缘。第八桥接部38可以分别通过过孔连接第十七有源部717和第二十有源部720，以连接第八晶 体管的第二极和驱动晶体管端第一极。第一初始信号线Vinit1可以通过过孔连接第十四有源部814，以连接第一初始信号端和第一晶体管T1的第一极。第二初始信号线Vinit2可以通过过孔连接第十三有源部713，以连接第二初始信号端和第七晶体管的第一极。第三初始信号线Vinit3通过过孔连接第十八有源部718，以连接第八晶体管的第一极和第三初始信号端。第四桥接部34在衬底基板上的正投影可以和第一栅线段1G11在衬底基板上的正投影相交，第一栅极连接线段3G11在衬底基板上的正投影位于在第一方向X上相邻两第四桥接部34在衬底基板上的正投影之间。第一栅极连接线段3G11可以分别通过过孔连接在第一方向X上相邻的第一栅线段1G11，以及分别通过过孔连接在第一方向X上相邻的第三栅线段2G11。第二栅极连接线3G2可以分别通过过孔连接位于同一第二栅线G2中的多条第二栅线段G22。本示例性实施例中，第三导电层的方块电阻可以小于第一导电层、第二导电层的方块电阻。第一栅极连接线段3G11可以降低第二晶体管T2所连接栅线的自身电阻，从而提高第二晶体管T2的响应速度。第二栅极连接线3G2可以降低第四晶体管T4所连接栅线的自身电阻，从而提高第四晶体管T4的响应速度。如图23所示，第八桥接部38可以包括子桥接部381，子桥接部381在衬底基板上的正投影可以沿第一方向X延伸，且位于第二复位信号线Re2在衬底基板上的正投影上，该设置可以提高显示面板的透过率。
如图18、24所示，第四导电层可以包括多条第三电源线VDD、多条数据线Da、第六初始信号线4Vinit3、第九桥接部49。其中，第三电源线VDD在衬底基板上的正投影、数据线Da在衬底基板上的正投影、第六初始信号线4Vinit3在衬底基板上的正投影均可以沿第二方向Y延伸。第三电源线VDD可以用于提供第一电源端，数据线Da可以用于提供数据信号端。如图18、24所示，每列像素驱动电路可以对应设置一条第三电源线VDD、一条第六初始信号线4Vinit3、一条数据线Da。第三电源线VDD可以通过过孔连接第一桥接部31，以连接第五晶体管的第一极和第一电源端。第三电源线VDD可以包括第一延伸部VDD1、第二延伸部VDD2、第三延伸部VDD3，第二延伸部VDD2连接于第一延伸部VDD1和第三延伸部VDD3之间，第二延伸部VDD2在所述衬底基板上的正投影在第一方向X上的尺寸可以大于 第一延伸部VDD1在所述衬底基板上的正投影在第一方向X上的尺寸，且所述第二延伸部VDD2在所述衬底基板上的正投影在第一方向X上的尺寸可以大于所述第三延伸部VDD3在所述衬底基板上的正投影在第一方向X上的尺寸。第二延伸部VDD2在衬底基板上的正投影可以覆盖第一有源部81在衬底基板上的正投影、第二有源部82在衬底基板上的正投影，第二延伸部VDD2可以降低光照对第一晶体管T1、第二晶体管T2的特性影响。此外，第三电源线VDD在衬底基板上的正投影可以覆盖第四桥接部34在衬底基板上的正投影，第三电源线VDD可以用于屏蔽其他信号对第四桥接部34的噪音干扰，从而提高驱动晶体管T3栅极电压的稳定性。此外，在同一重复单元中，相邻两像素驱动电路中第二延伸部VDD2可以相互连接，从而第三电源线VDD和第三导电部23可以形成网格结构，该网格结构的电源线可以降低其上电源信号的压降。数据线Da可以通过过孔连接第六桥接部36，以连接第四晶体管的第一极和数据信号端。第九桥接部49可以通过过孔连接第二桥接部32，以连接第七晶体管的第二极。第六初始信号线4Vinit3可以通过过孔连接与其相交的第三初始信号线Vinit3以形成网格结构。在同一列像素驱动电路中，第六初始信号线4Vinit3在衬底基板上的正投影可以位于数据线Da在衬底基板上的正投影和第三电源线VDD在衬底基板上的正投影之间，第六初始信号线4Vinit3可以用于屏蔽数据线Da和第三电源线VDD之间的信号干扰。
如图29所示，为图18所示显示面板沿虚线AA剖开的部分剖视图。该显示面板还可以包括第一绝缘层91、缓冲层92、第二绝缘层93、介电层94、钝化层95、平坦层96。其中，衬底基板90、第一有源层、第一绝缘层91、第一导电层、缓冲层92、第二有源层、第二绝缘层93、第二导电层、介电层94、第三导电层、钝化层95、平坦层96、第四导电层依次层叠设置。缓冲层92的厚度可以大于第二绝缘层93的厚度。第一绝缘层91、第二绝缘层93可以为单层结构或多层结构，且第一绝缘层91、第二绝缘层93的材料可以为氮化硅，氧化硅，氮氧化硅中的至少一种；缓冲层92可以包括氧化硅层、氮化硅层中的至少一种；介电层94可以氮化硅层；钝化层95可以为氧化硅层；平坦层96的材料可以为有机材料，例如聚酰亚胺(PI)、聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)、 硅-玻璃键合结构(SOG)等材料。衬底基板90可以包括依次层叠设置的玻璃基板、阻挡层、聚酰亚胺层，阻挡层可以为无机材料。第一导电层、第二导电层的材料可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等。第三导电层、第四导电层的材料可以包括金属材料，例如可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层。该显示面板还可以包括位于第四导电层背离衬底基板一侧的电极层、位于电极层背离衬底基板一侧的像素限定层、位于像素限定层背离衬底基板一侧的发光材料层，公共电极层位于发光材料层背离衬底基板的一侧。
本示例性实施例中，第二绝缘层93可以为图案化结构，例如，第二绝缘层93可以仅位于第二有源层和第二导电层之间。第三导电部23和第一导电部11之间可以不设置第二绝缘层93，该设置可以降低第三导电部23和第一导电部11之间的距离，从而提高电容C的容量。应该理解的是，在其他示例性实施例中，也可以通过减小第三导电部23和第一导电部11之间局部的第二绝缘层93和/或缓冲层92的厚度，以减小第三导电部23和第一导电部11之间之间的距离。例如，第三导电部23和第一导电部11在显示面板厚度方向上的距离可以小于第三栅线2G1和第一栅线1G1在显示面板厚度方向上的距离。
如图30所示，为本公开显示面板另一种示例性实施例中的结构示意图。相比于图18所示显示面板，图30所示显示面板中的第三栅线2G1在第一方向X上连续延伸，即第三栅线2G1没有断开。第三栅线2G1可以通过过孔连接位于同一第一栅线1G1中的多条第一栅线段1G11。
如图31、32所示，图31为本公开显示面板另一种示例性实施例中的结构示意图，图32为图31中第一有源层的结构版图。相比于图18所示显示面板，图31所示显示面板中的第四有源部74和第三有源部73之间形成有断口D1，第三导电层包括有第十桥接部310，第十桥接部310通过过孔连接于第四有源部74和第三有源部73之间。第一栅线1G1在第一方向X上连续延伸，第三栅线2G1在第一方向X上连续延伸。第一栅线1G1在衬底基板上的正投影位于断口D1在衬底基板上的正投影内，且与第十桥接部310在衬底基板上的正投影相交。第三栅线2G1在衬底基板上的正 投影位于断口D1在衬底基板上的正投影内，且与第十桥接部310在衬底基板上的正投影相交。
需要说明的是，如图2、12、18、28、30、31所示，画于第三导电层背离衬底基板一侧的黑色方块表示第三导电层连接面向衬底基板一侧的其他层级的过孔；画于第四导电层背离衬底基板一侧的黑色方块表示第四导电层连接面向衬底基板一侧的其他层级的过孔。该黑色方块仅表示过孔的位置，不同位置黑色方块所表示的不同过孔可以贯穿于不同绝缘层。
需要说明的是，本公开中的附图比例可以作为实际工艺中的参考，但不限于此，例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图。此外，第一、第二等限定词仅用于限定不同的结构名称，其并没有特定顺序的含义。本公开中同一结构层可以通过一次构图工艺形成。
本示例性实施例还提供一种显示装置，其中，包括上述的显示面板。该显示装置可以为手机、平板电脑、电视等显示装置。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (21)

  1. 一种显示面板，其中，所述显示面板包括像素驱动电路，所述像素驱动电路包括第一类型晶体管和第二类型晶体管，所述显示面板还包括：
    衬底基板；
    第一有源层，位于所述衬底基板的一侧，所述第一有源层的至少部分结构用于形成所述第一类型晶体管的沟道区；
    第二有源层，位于所述第一有源层背离所述衬底基板的一侧，所述第二有源层的至少部分结构用于形成所述第二类型晶体管的沟道区；
    第一导电层，位于所述第一有源层和所述第二有源层之间，所述第一导电层的部分结构用于形成所述第一类型晶体管的栅极，所述第一导电层的部分结构用于形成所述第二类型晶体管的底栅。
  2. 根据权利要求1所述的显示面板，其中，所述像素驱动电路还包括驱动晶体管、第八晶体管，所述第八晶体管的第一极连接第三初始信号线，所述第八晶体管的第二极连接所述驱动晶体管的第一极。
  3. 根据权利要求1所述的显示面板，其中，所述像素驱动电路还包括电容，所述第一导电层包括第一导电部，所述第一导电部用于形成所述电容的第一电极；
    所述显示面板还包括：
    第二导电层，位于所述第二有源层背离所述衬底基板的一侧，所述第二导电层包括第三导电部，所述第三导电部在所述衬底基板上的正投影和所述第一导电部在所述衬底基板上的正投影至少部分交叠，所述第三导电部用于形成所述电容的第二电极；
    其中，所述第二导电层的部分结构还用于形成所述第二类型晶体管的顶栅。
  4. 根据权利要求3所述的显示面板，其中，所述像素驱动电路还包括驱动晶体管、第一晶体管、第二晶体管，所述驱动晶体管为所述第一类型晶体管，所述第一晶体管、第二晶体管为所述第二类型晶体管；
    所述第一晶体管的第一极连接第一初始信号线，所述第一晶体管的第二极连接所述驱动晶体管的栅极，所述第二晶体管的第一极连接所述驱动晶体管的栅极，所述第二晶体管的第二极连接所述驱动晶体管的第二极， 所述电容的第一电极连接所述驱动晶体管的栅极；
    所述第一有源层包括：第三有源部，所述第三有源部用于形成所述驱动晶体管的沟道区；
    所述第二有源层包括：第一有源部、第二有源部，所述第一有源部用于形成所述第一晶体管的沟道区，所述第二有源部用于形成所述第二晶体管的沟道区；
    所述第一导电层包括：第一导电部、第一栅线、第一复位信号线；
    其中，所述第一导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第一导电部用于形成所述驱动晶体管的栅极和所述电容的第一电极；
    所述第一复位信号线在所述衬底基板上的正投影覆盖所述第一有源部在所述衬底基板上的正投影，所述第一复位信号线的部分结构用于形成所述第一晶体管的底栅；
    所述第一栅线在所述衬底基板上的正投影覆盖所述第二有源部在所述衬底基板上的正投影，所述第一栅线的部分结构用于形成所述第二晶体管的底栅；
    所述第二导电层包括：第三导电部、第三栅线、第三复位信号线；
    其中，所述第三导电部在所述衬底基板上的正投影和所述第一导电部在所述衬底基板上的正投影至少部分交叠，所述第三导电部用于形成所述电容的第二电极；
    所述第三复位信号线在所述衬底基板上的正投影覆盖所述第一有源部在所述衬底基板上的正投影，所述第三复位信号线的部分结构用于形成所述第一晶体管的顶栅；
    所述第三栅线在所述衬底基板上的正投影覆盖所述第二有源部在所述衬底基板上的正投影，所述第三栅线的部分结构用于形成所述第二晶体管的底栅。
  5. 根据权利要求4所述的显示面板，其中，所述像素驱动电路还包括第四晶体管，所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极，所述第四晶体管为所述第一类型晶体管；
    所述第一有源层还包括第四有源部，所述第四有源部用于形成所述第四晶体管的沟道区；
    所述第一导电层还包括：第二栅线，所述第二栅线在所述衬底基板上的正投影覆盖所述第四有源部在所述衬底基板上的正投影，所述第二栅线的部分结构用于形成所述第四晶体管的栅极；
    其中，所述第一栅线在所述衬底基板上的正投影、所述第二栅线在所述衬底基板上的正投影、所述第一复位信号线在所述衬底基板上的正投影均沿第一方向延伸；
    所述第二栅线在所述衬底基板上的正投影位于所述第一栅线在所述衬底基板上的正投影远离所述第一导电部在所述衬底基板上的正投影的一侧；
    所述第一复位信号线在所述衬底基板上的正投影位于所述第二栅线在所述衬底基板上的正投影远离所述第一导电部在所述衬底基板上的正投影的一侧。
  6. 根据权利要求5所述的显示面板，其中，所述第一栅线包括多条第一栅线段，同一所述第一栅线中多条所述第一栅线段在所述衬底基板上的正投影沿所述第一方向延伸且沿所述第一方向间隔分布；
    所述第二有源层还包括第十五有源部，所述第十五有源连接于所述第一有源部和所述第二有源部之间；
    所述第一导电层还包括：第二导电部，所述第二导电部在所述衬底基板上的正投影沿第二方向延伸，且位于在所述第一方向上相邻两所述第一栅线段在所述衬底基板上的正投影之间，所述第二方向和所述第一方向相交，所述第二导电部分别连接所述第十五有源部和所述第一导电部；
    所述显示面板还包括：
    第三导电层，位于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括第一栅极连接线，所述第一栅极连接线在所述衬底基板上的正投影沿所述第一方向延伸且与所述第二导电部在所述衬底基板上的正投影相交，所述第一栅极连接线分别通过过孔连接同一所述第一栅线中的多条所述第一栅线段。
  7. 根据权利要求5所述的显示面板，其中，所述第一栅线包括多条 第一栅线段，同一所述第一栅线中多条所述第一栅线段在所述衬底基板上的正投影沿所述第一方向延伸且沿所述第一方向间隔分布；
    所述第二有源部还包括第十五有源部，所述第十五有源连接于所述第一有源部和所述第二有源部之间；
    所述显示面板还包括：
    第三导电层，位于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括第一栅极连接线段、第四桥接部，所述第四桥接部在所述衬底基板上的正投影沿第二方向延伸，所述第二方向和所述第一方向相交，且所述第四桥接部分别通过过孔连接所述第十五有源部和所述第一导电部；
    其中，所述第四桥接部在所述衬底基板上的正投影和所述第一栅线段在所述衬底基板上的正投影相交，所述第一栅极连接线段在所述衬底基板上的正投影位于在所述第一方向上相邻两所述第四桥接部在所述衬底基板上的正投影之间，且所述第一栅极连接线段连接于在所述第一方向上相邻的两所述第一栅线段之间。
  8. 根据权利要求5所述的显示面板，其中，所述第一栅线包括多条第一栅线段，同一所述第一栅线中多条所述第一栅线段在所述衬底基板上的正投影沿所述第一方向延伸且沿所述第一方向间隔分布；
    所述第二导电层包括第三栅线，所述第三栅线在所述衬底基板上的正投影沿所述第一方向延伸，所述第三栅线通过过孔连接同一所述第一栅线中的多条所述第一栅线段。
  9. 根据权利要求5所述的显示面板，其中，所述显示面板还包括：
    第三导电层，位于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括第十桥接部，所述第十桥接部连接于所述第四有源部和所述第三有源部之间；
    所述第一栅线在所述衬底基板上的正投影和所述第十桥接部在所述衬底基板上的正投影相交。
  10. 根据权利要求5所述的显示面板，其中，所述第三栅线包括多条第三栅线段，同一所述第三栅线中的多条所述第三栅线段在所述衬底基板上的正投影沿所述第一方向延伸且沿所述第一方向间隔分布；
    所述显示面板还包括：
    第三导电层，位于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括第一栅极连接线，所述第一栅极连接线在所述衬底基板上的正投影沿所述第一方向延伸，且所述第一栅极连接线分别通过过孔连接同一所述第三栅线中的多条所述第三栅线段。
  11. 根据权利要求5-7、9、10任一项所述的显示面板，其中，所述第三导电层的方块电阻小于所述第一导电层的方块电阻；
    所述第三导电层的方块电阻小于所述第二导电层的方块电阻。
  12. 根据权利要求3所述的显示面板，其中，所述显示面板还包括：
    缓冲层，位于所述第一导电层和所述第二有源层之间；
    第二绝缘层，位于所述第二有源层和所述第二导电层之间；
    其中，所述第一导电部和所述第三导电部之间所述第二绝缘层的厚度小于所述第二类型晶体管顶栅和底栅之间所述第二绝缘层的厚度；
    和/或，所述第一导电部和所述第三导电部之间所述缓冲层的厚度小于所述第二类型晶体管顶栅和底栅之间所述缓冲层的厚度。
  13. 根据权利要求3所述的显示面板，其中，所述显示面板还包括扇出区和多条数据线，所述第一导电层还包括：
    第一数据扇出线，位于所述扇出区，所述第一数据扇出线连接与其对应的所述数据线；
    所述第二导电层还包括：
    第二数据扇出线，位于所述扇出区，所述第二数据扇出线连接与其对应的所述数据线。
  14. 根据权利要求3所述的显示面板，其中，所述像素驱动电路包括驱动晶体管、第四晶体管，所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极，所述电容的第一电极连接所述驱动晶体管的栅极，所述电容的第二电极连接第三电源线；
    所述第一有源层包括第三有源部、第四有源部、第十九有源部，所述第三有源部用于形成所述驱动晶体管的沟道区，所述第四有源部用于形成所述第四晶体管的沟道区，所述第十九有源部连接于所述第三有源部和所述第四有源部之间，所述十九有源部在所述衬底基板上的正投影在第一方 向上的尺寸大于所述第四有源部在所述衬底基板上的正投影在所述第一方向上的尺寸；
    所述第二导电层包括第三导电部、第四导电部，所述第三导电部用于形成所述电容的第二电极，所述第四导电部连接所述第三导电部，所述第四导电部在所述衬底基板上的正投影与所述第十九有源部在所述衬底基板上的正投影至少部分交叠。
  15. 根据权利要求1所述的显示面板，其中，所述显示面板包括：位于显示区的发光单元，所述像素驱动电路包括：驱动晶体管、第一晶体管、第七晶体管、第八晶体管；
    所述像素驱动电路连接所述发光单元的第一电极，所述发光单元的第二电极连接第一电源线；
    所述第一晶体管的第一级连接第一初始信号线，所述第一晶体管的第二极连接所述驱动晶体管的栅极；
    所述第七晶体管的第一极连接第二初始信号线，所述第七晶体管的第二极连接所述发光单元的第一电极；
    所述第八晶体管的第一极连接第三初始信号线，所述第八晶体管的第二极连接所述驱动晶体管的第一极；
    所述显示面板还包括：
    多条第一信号线，位于所述显示面板的显示区，所述第一信号线在所述衬底基板上的正投影沿第一方向延伸；
    多条第二信号线，位于所述显示面板的显示区，且所述第二信号线在所述衬底基板上的正投影沿第二方向延伸，所述第二方向与所述第一方向相交，至少部分所述第二信号线通过过孔连接与其在所述衬底基板上的正投影相交的至少部分所述第一信号线；
    所述第一信号线包括所述第一电源线、所述第一初始信号线、所述第二初始信号线、所述第三初始信号线中的至少一种，同一所述第二信号线连接同一种所述第一信号线，且所述第二信号线连接所述第一电源线、所述第一初始信号线、所述第二初始信号线、所述第三初始信号线中的至少一种。
  16. 根据权利要求15所述的显示面板，其中，所述像素驱动电路还 包括第四晶体管、驱动晶体管、第五晶体管，所述第五晶体管的第一极连接第三电源线，所述第五晶体管的第二极连接所述驱动晶体管的第一极，所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极；
    所述显示面板还包括：
    第四导电层，位于所述第二有源层背离所述衬底基板的一侧，所述第四导电层包括所述数据线、第三电源线、第二信号线；
    其中，所述数据线在所述衬底基板上的正投影、所述第三电源线在所述衬底基板上的正投影沿所述第二方向延伸，且在同一列像素驱动电路中，位于所述第四导电层的所述第二信号线在所述衬底基板上的正投影位于所述数据线在所述衬底基板上的正投影和所述第三电源线在所述衬底基板上的正投影之间。
  17. 根据权利要求3所述的显示面板，其中，所述显示面板包括沿第一方向和第二方向阵列分布的多个重复单元，所述第一方向和所述第二方向相交；
    每个所述重复单元包括沿所述第一方向分布的两个所述像素驱动电路，同一所述重复单元中两个所述像素驱动电路镜像对称设置。
  18. 根据权利要求17所述的显示面板，其中，所述第一方向为行方向，所述第二方向为列方向，所述像素驱动电路包括驱动晶体管，所述电容的第一电极连接所述驱动晶体管的栅极，所述电容的第二电极连接第三电源线；
    所述显示面板还包括：
    第四导电层，位于所述第二导电层背离所述衬底基板的一侧，所述第四导电层包括所述第三电源线，每列所述像素驱动电路对应设置一条所述第三电源线，所述第三电源线包括：第一延伸部、第二延伸部、第三延伸部，所述第二延伸部连接于所述第一延伸部和所述第三延伸部之间；
    所述第二延伸部在所述衬底基板上的正投影在行方向上的尺寸大于第一延伸部在所述衬底基板上的正投影在行方向上的尺寸，且所述第二延伸部在所述衬底基板上的正投影在行方向上的尺寸大于所述第三延伸部在所述衬底基板上的正投影在行方向上的尺寸；
    其中，在同一所述重复单元中，相邻两所述第三电源线中的第二延伸部相连接，在行方向上相邻的两所述重复单元中相邻两所述第三导电部相连接。
  19. 根据权利要求4所述的显示面板，其中，所述显示面板包括多个所述像素驱动电路，多个所述像素驱动电路沿第一方向和第二方向阵列分布，所述第一方向和所述第二方向相交；
    所述像素驱动电路还包括第五晶体管，所述第五晶体管的第一极连接第三电源线，所述第五晶体管的第二极连接所述驱动晶体管的第一极，所述显示面板还包括：
    第三导电层，位于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括电源连接线，所述电源连接线在所述衬底基板上的正投影沿所述第一方向延伸，所述电源连接线分别通过过孔连接多个所述第三导电部，且与同一所述电源连接线连接的多个所述第三导电部在所述衬底基板上的正投影沿所述第一方向间隔分布；
    第四导电层，位于所述第三导电层背离所述衬底基板的一侧，所述第四导电层包括所述第三电源线，所述第三电源线在所述衬底基板上的正投影沿所述第二方向延伸，且所述第三电源线连接与其在所述衬底基板上的正投影相交的所述电源连接线。
  20. 根据权利要求4所述的显示面板，其中，所述显示面板还包括发光单元，所述像素驱动电路还包括：第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管；
    所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极；
    所述第五晶体管的第一极连接第三电源线，所述第五晶体管的第二极连接所述驱动晶体管的第一极；
    所述第六晶体管的第一极连接所述驱动晶体管的第二极，所述第六晶体管的第二极连接所述发光单元的第一电极；
    所述第七晶体管的第一极连接第二初始信号线，所述第七晶体管的第二极连接所述发光单元的第一电极；
    所述第八晶体管的第一极连接第三初始信号线，所述第八晶体管的第 二极连接所述驱动晶体管的第一极；
    所述第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管为所述第一类型晶体管；
    所述第一类型晶体管为P型晶体管，所述第二类型晶体管为N型晶体管。
  21. 一种显示装置，其中，包括权利要求1-20任一项所述的显示面板。
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WO2021226807A1 (zh) * 2020-05-11 2021-11-18 京东方科技集团股份有限公司 显示面板及显示装置
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