WO2023201570A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023201570A1
WO2023201570A1 PCT/CN2022/087910 CN2022087910W WO2023201570A1 WO 2023201570 A1 WO2023201570 A1 WO 2023201570A1 CN 2022087910 W CN2022087910 W CN 2022087910W WO 2023201570 A1 WO2023201570 A1 WO 2023201570A1
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WIPO (PCT)
Prior art keywords
transistor
base substrate
conductive
orthographic projection
electrode
Prior art date
Application number
PCT/CN2022/087910
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English (en)
French (fr)
Inventor
赵攀
张竞文
蒋志亮
于子阳
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000799.7A priority Critical patent/CN117280409A/zh
Priority to PCT/CN2022/087910 priority patent/WO2023201570A1/zh
Publication of WO2023201570A1 publication Critical patent/WO2023201570A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • a pixel circuit in a display panel usually includes a driving transistor.
  • a driving transistor In order to make the driving transistor operate in the saturation region, a large cross-voltage needs to be applied between the source and drain of the driving transistor.
  • the display panel due to the large sheet resistance of the common electrode layer in the display panel, the display panel needs to provide a large power supply voltage to achieve normal driving, which in turn causes the display panel to consume large amounts of power.
  • a display panel including sub-pixel units distributed in an array along a first direction and a second direction, the first direction and the second direction intersect, and the
  • the sub-pixel unit includes a pixel drive circuit and a light-emitting unit.
  • the pixel drive circuit is connected to the first electrode of the light-emitting unit.
  • the pixel drive circuit includes a drive transistor and a capacitor.
  • the first electrode of the capacitor is connected to the first power line.
  • the second electrode of the capacitor is connected to the gate of the driving transistor.
  • the display panel also includes: a substrate, a second conductive layer, a fourth conductive layer, and a common electrode layer.
  • the second conductive layer is located on the substrate.
  • the second conductive layer includes a plurality of first conductive parts, the first conductive parts are arranged corresponding to the pixel driving circuit, and the first conductive parts are used to form the corresponding pixel driving circuit.
  • the first electrode of the capacitor in the circuit; the fourth conductive layer is located on the side of the second conductive layer facing away from the base substrate; the fourth conductive layer includes a plurality of the first power lines; the fourth conductive layer
  • the orthographic projection of a power line on the base substrate is spaced apart along the first direction and extends along the second direction, and the first conductive portion is connected to the first power line through a via hole;
  • a common electrode layer Located on a side of the fourth conductive layer facing away from the base substrate, the common electrode layer is used to form the second electrode of the light-emitting unit, and the first power line is connected to the common electrode layer through a via hole.
  • At least part of the first conductive parts distributed in the first direction are connected in sequence to form a first conductive line, and the first conductive line is connected to a plurality of the first power sources. Wire.
  • the plurality of first conductive parts distributed in the first direction form a plurality of first conductive lines spaced apart in the first direction; in the first Two first conductive lines adjacent in both one direction and the second direction are staggered in the first direction, and the two staggered first conductive lines jointly connect at least two first power sources. Wire.
  • the pixel driving circuit further includes a sixth transistor, the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the third electrode of the light-emitting unit.
  • One electrode, the sixth transistor is a P-type transistor, and the first power line is used to provide a low-level power signal.
  • the display panel further includes: an active layer located between the base substrate and the second conductive layer, the active layer includes a sixth active portion, the sixth active portion is In forming the channel region of the sixth transistor; the orthographic projection of the first power line on the base substrate at least partially overlaps the orthographic projection of the sixth active part on the base substrate. .
  • the first sub-active part is used to form the first channel region of the second transistor
  • the second sub-active part is used to form the second channel region of the second transistor; wherein, An orthographic projection of the second conductive portion on the base substrate and an orthographic projection of the third sub-active portion on the base substrate at least partially overlap.
  • the first electrode of the driving transistor is connected to a second power line, and the second conductive part is connected to the second power line through a via hole;
  • the second conductive layer includes a plurality of the second conductive part, the second conductive part is provided corresponding to the pixel driving circuit, and at least part of the second conductive part distributed in the first direction is connected in sequence to form a second conductive line;
  • the display panel also includes a plurality of second power lines, orthogonal projections of the plurality of second power lines on the base substrate are spaced apart along the first direction and extend along the second direction, the The second conductive wire is connected to a plurality of second power wires.
  • the pixel driving circuit further includes a first transistor, the first electrode of the first transistor is connected to the first initial signal line, and the second electrode is connected to the gate of the driving transistor;
  • the active layer further includes a first active part for forming a channel region of the first transistor and a third active part for forming the first transistor. The channel region of the drive transistor.
  • the display panel also includes: a first conductive layer located between the active layer and the second conductive layer; the first conductive layer includes: a first reset signal line, a gate line, a first Three conductive parts, the orthographic projection of the first reset signal line on the base substrate extends along the first direction and covers the orthographic projection of the first active part on the base substrate, the first The partial structure of the reset signal line is used to form the gate of the first transistor; the orthographic projection of the gate line on the substrate extends along the first direction and covers the second active part on the substrate.
  • Orthographic projection on the base substrate, part of the structure of the gate line is used to form the gate of the second transistor; orthographic projection of the third conductive part on the base substrate covers the third active part The orthographic projection on the base substrate, the third conductive part is used to form the gate of the driving transistor; wherein the orthographic projection of the first reset signal line on the base substrate is located on the The orthographic projection of the gate line on the base substrate is away from the side of the orthographic projection of the third conductive part on the base substrate, and the orthographic projection of the second conductive part on the base substrate is located on between the orthographic projection of the first reset signal line on the base substrate and the orthographic projection of the gate line on the base substrate.
  • the display panel further includes: a third conductive layer, the third conductive layer is located between the second conductive layer and the fourth conductive layer, the third conductive layer includes A first bridge portion is connected to the third conductive portion through a via hole and is connected to the first pole of the second transistor; the second conductive portion includes: a first sub-conductive portion, the third conductive portion is An orthographic projection of a sub-conductive portion on the base substrate extends along the first direction, and is located where the orthographic projection of the first bridge portion on the base substrate and the first reset signal line are located. between the orthographic projections on the substrate substrate.
  • the display panel further includes: a data line, and an orthographic projection of the data line on the substrate extends along the second direction.
  • the second conductive part further includes: a second sub-conductive part, the second sub-conductive part is connected to the first sub-conductive part, and the orthographic projection of the second sub-conductive part on the base substrate is along the The second direction extends and is located between the orthographic projection of the first bridge portion on the base substrate and the orthographic projection of the data line on the base substrate.
  • the driving transistor is connected to the second power line
  • the pixel driving circuit further includes a second transistor and a fourth transistor
  • the first electrode of the second transistor is connected to the first electrode of the driving transistor.
  • the gate electrode, the second electrode of the second transistor is connected to the second electrode of the driving transistor, the first electrode of the fourth transistor is connected to the data line, and the second electrode of the fourth transistor is connected to the driving transistor.
  • the display panel also includes: an active layer, a first conductive layer, and a third conductive layer.
  • the active layer is located between the base substrate and the second conductive layer.
  • the active layer includes a third active layer.
  • the third active part is used to form a channel region of the driving transistor;
  • the first conductive layer is located between the active layer and the second conductive layer, and the first conductive layer includes a third A conductive part, the orthographic projection of the third conductive part on the base substrate covers the orthographic projection of the third active part on the base substrate, and the third conductive part is used to form the driving The gate electrode of the transistor;
  • a third conductive layer is located between the second conductive layer and the fourth conductive layer, the third conductive layer includes a first bridge portion, the first bridge portion is connected to the The third conductive part is connected to the first electrode of the second transistor;
  • the second direction is the column direction.
  • the orthographic projection of the second power line on the base substrate is The second direction extends, the orthographic projection of the data line on the base substrate extends along the second direction, and the orthographic projection of the second power line on the base substrate is located on the data line.
  • the orthographic projection of the first power line on the base substrate is located on the The orthographic projection of the first bridge portion on the base substrate is away from the orthographic projection of the second power line on the base substrate; in the adjacent column pixel driving circuit, in the current column pixel driving circuit.
  • the orthographic projection of the first power line on the base substrate is located in the orthographic projection of the data line on the base substrate in the pixel driving circuit of the adjacent column and the first in the pixel driving circuit of this column.
  • the bridge portion is between orthographic projections on the base substrate.
  • the pixel driving circuit further includes a second transistor, the first electrode of the second transistor is connected to the gate of the driving transistor, and the second electrode is connected to the second electrode of the driving transistor. pole.
  • the display panel also includes: an active layer, a first conductive layer, and a third conductive layer. The active layer is located between the base substrate and the second conductive layer. The active layer includes a third active layer.
  • the third active part is used to form a channel region of the driving transistor;
  • the first conductive layer is located between the active layer and the second conductive layer, and the first conductive layer includes a third A conductive part, the orthographic projection of the third conductive part on the base substrate covers the orthographic projection of the third active part on the base substrate, and the third conductive part is used to form the driving The gate electrode of the transistor;
  • a third conductive layer is located between the second conductive layer and the fourth conductive layer, the third conductive layer includes a first bridge portion, the first bridge portion is connected to the The third conductive part is connected to the first electrode of the second transistor.
  • the pixel driving circuit further includes a first transistor and a seventh transistor.
  • the first electrode of the first transistor is connected to the first initial signal line, and the second electrode is connected to the driving transistor.
  • the gate electrode, the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode is connected to the first electrode of the light-emitting unit.
  • the display panel also includes: an active layer and a first conductive layer.
  • the active layer is located between the base substrate and the second conductive layer.
  • the active layer includes a first active portion, a seventh active layer, and a first conductive layer. A source part, the first active part is used to form a channel region of the first transistor, and the seventh active part is used to form a channel region of the seventh transistor.
  • the projection is away from the side of the forward projection of the third conductive part on the substrate; in the adjacent row of pixel driving circuits, the second initial signal line in the previous row of pixel driving circuits is on the substrate
  • the orthographic projection of the first initial signal line on the substrate in the pixel driving circuit of this row is on the substrate, and the first reset signal line of the pixel driving circuit of this row is on the substrate. between the orthographic projections.
  • the first active part includes a fourth sub-active part and a fifth sub-active part
  • the active layer further includes a layer connected to the fourth sub-active part and a fifth sub-active part.
  • the sixth sub-active part between the fifth sub-active parts; the orthographic projection of the second initial signal line on the base substrate in the pixel driving circuit of the previous row is the same as that of the pixel driving circuit of this row. Orthographic projections of the sixth sub-active portion on the base substrate at least partially overlap.
  • the display panel further includes: an active layer and a first conductive layer.
  • the active layer is located between the base substrate and the second conductive layer.
  • the active layer includes: a third active part, a fourth active part, a fifth active part, a sixth active part, A seventh active part, the third active part is used to form a channel region of the driving transistor, the fourth active part is used to form a channel region of the fourth transistor, and the fifth active part is used to form a channel region of the driving transistor.
  • the source part is used to form a channel region of the fifth transistor, the sixth active part is used to form a channel region of the sixth transistor, and the seventh active part is used to form the seventh transistor. channel area.
  • a first conductive layer is located between the active layer and the second conductive layer.
  • the first conductive layer includes: a gate line, an enable signal line, a second reset signal line, and a third conductive part.
  • the orthographic projection of the gate line on the base substrate extends along the first direction and covers the orthographic projection of the fourth active part on the base substrate, and part of the structure of the gate line is used to form The gate of the fourth transistor; the orthographic projection of the enable signal line on the base substrate extends along the first direction and covers the orthographic projection of the fifth active part on the base substrate.
  • a part of the structure of the enable signal line is used to form the gate of the fifth transistor, and another part of the enable signal line
  • the structure is used to form the gate of the sixth transistor; the orthographic projection of the second reset signal line on the substrate extends along the first direction and covers the seventh active portion on the substrate.
  • the orthographic projection on the substrate, part of the structure of the second reset signal line is used to form the gate of the seventh transistor; the orthographic projection of the third conductive part on the substrate covers all the The orthographic projection of the third active part on the base substrate, the third conductive part is used to form the gate of the driving transistor; wherein, in the same row of pixel driving circuits, the enable signal line
  • the orthographic projection on the base substrate is located between the orthographic projection of the third conductive portion on the base substrate and the orthographic projection of the second reset signal line on the base substrate.
  • Figure 1 is a schematic circuit structure diagram of a pixel driving circuit in an exemplary embodiment of the display panel of the present disclosure
  • Figure 9 is a structural layout of the second conductive layer in Figure 8.
  • Figure 11 is a structural layout of another exemplary embodiment of a display panel of the present disclosure.
  • Figure 13 is a structural layout of the second conductive layer and the fourth conductive layer in Figure 11;
  • Figure 15 is the structural layout of the active layer in Figure 14;
  • Figure 16 is a structural layout of the first conductive layer in Figure 14;
  • Figure 17 is a structural layout of the second conductive layer in Figure 14;
  • Figure 18 is a structural layout of the third conductive layer in Figure 14;
  • Figure 19 is a structural layout of the fourth conductive layer in Figure 14;
  • Figure 20 is a structural layout of the active layer and the first conductive layer in Figure 14;
  • Figure 21 is a structural layout of the active layer, the first conductive layer, and the second conductive layer in Figure 14;
  • Figure 22 is a structural layout of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in Figure 14;
  • Figure 23 is a partial cross-sectional view of the display panel shown in Figure 14 taken along the dotted line AA;
  • Figure 24 is a structural layout of a display panel in another exemplary embodiment of the present disclosure.
  • Figure 25 is a structural layout of the pixel electrode layer in Figure 24;
  • Figure 26 is a structural layout of a pixel electrode layer in another exemplary embodiment of the display panel of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments. To those skilled in the art.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C.
  • the first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1
  • the second electrode is connected to the node N
  • the gate is connected to the first reset signal terminal Re1
  • the first electrode of the second transistor T2 is connected to the gate of the driving transistor T3.
  • the second electrode of the driving transistor T3 is connected to the second electrode; the gate is connected to the gate driving signal terminal Gate; the gate of the driving transistor T3 is connected to the node N; the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, and the second electrode is connected to the data signal terminal Da.
  • the first electrode of the drive transistor T3, the gate is connected to the gate drive signal terminal Gate; the first electrode of the fifth transistor T5 is connected to the second power terminal VDD, the second electrode is connected to the first electrode of the drive transistor T3, and the gate is connected to the enable The signal terminal EM; the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, and the gate electrode is connected to the enable signal terminal EM; the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the second electrode is connected to the second initial signal terminal Vinit2.
  • the second electrode and gate of the six-transistor T6 are connected to the second reset signal terminal Re2.
  • the first electrode of the capacitor C is connected to the first power supply terminal VSS, and the second electrode of the capacitor C is connected to the gate of the driving transistor T3.
  • the pixel driving circuit can be connected to a light-emitting unit OLED.
  • the pixel driving circuit is used to drive the light-emitting unit OLED to emit light.
  • the first electrode of the light-emitting unit OLED can be connected to the second pole of the sixth transistor T6.
  • the second electrode of the light-emitting unit OLED can be Connect the first power terminal VSS.
  • the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may all be P-type transistors.
  • FIG. 2 it is a timing diagram of each node signal in a driving method of the pixel driving circuit shown in Figure 1.
  • Gate represents the timing of the Gate signal at the gate drive signal terminal
  • Re1 represents the timing of the Re1 signal at the first reset signal terminal
  • Re2 represents the timing of the Re2 signal at the second reset signal terminal
  • EM represents the timing of the EM signal at the enable signal terminal
  • Da Indicates the timing of the Da signal at the data signal end.
  • the driving method of the pixel driving circuit may include a reset phase t1, a compensation phase t2, and a light emitting phase t3.
  • the first reset signal terminal Re1 outputs a low-level signal
  • the first transistor T1 is turned on
  • the first initial signal terminal Vinit1 inputs the first initial signal to the node N.
  • the compensation phase t2 the second reset signal terminal Re2 and the gate drive signal terminal Gate output low-level signals
  • the fourth transistor T4, the second transistor T2, and the seventh transistor T7 are turned on, and at the same time, the data signal terminal Da outputs a data signal to Write voltage Vdata+Vth to node N, where Vdata is the voltage of the data signal, Vth is the threshold voltage of the driving transistor T3, and the second initial signal terminal Vinit2 inputs the second initial signal to the second pole of the sixth transistor T6.
  • the enable signal terminal EM outputs a low-level signal
  • the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the voltage Vdata+Vth of the node N.
  • the driving transistor output current formula I ( ⁇ WCox/2L)(Vgs-Vth)2, where ⁇ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, and L driver The length of the transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor.
  • the pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.
  • the display panel may be a sub-pixel unit.
  • the sub-pixel unit includes a pixel driving circuit and a light-emitting unit.
  • the pixel driving circuit is connected to the first electrode of the light-emitting unit.
  • the pixel driving circuit can be shown in Figure 1.
  • the display panel may also include a base substrate, a second conductive layer, a fourth conductive layer, and a common electrode layer that are stacked in sequence, as shown in Figures 3-7.
  • Figure 3 is an exemplary embodiment of the display panel of the present disclosure.
  • the common electrode layer 6 can be an integral structure, and the first power line VSS can be connected to the common electrode layer 6 through via holes in the edge wiring area of the display panel.
  • the first conductive portions 21 distributed in the first direction The first power cord are shown in Figures 11-13, Figure 11 is a structural layout of another exemplary embodiment of the display panel of the present disclosure, Figure 12 is a structural layout of the second conductive layer in Figure 11, and Figure 13 is a structural layout of the second conductive layer in Figure 11 Structural layout of the conductive layer and the fourth conductive layer.
  • the plurality of first conductive parts 21 distributed in the first direction X may form a plurality of first conductive lines D1 distributed in intervals in the first direction X.
  • the two first conductive lines D1 that are adjacent in the first direction X and the second direction Y may be staggered in the first direction X, that is, in the first direction
  • the orthographic projections of the two first conductive lines D1 that are adjacent in the direction Y on the substrate partially intersect in the area covered by infinite movement in the second direction Y.
  • the first conductive line D1 may connect two first power lines VSS. This arrangement can also cause the first power line VSS and the first conductive line D1 to form a grid structure.
  • the pixel driving circuit in the display panel can also have other structures, as long as the first electrode of the capacitor C in the pixel driving circuit and the common electrode of the light-emitting unit are connected to the same signal terminal, the All display panels can reduce the voltage drop caused by the resistance of the common electrode itself through the above solution.
  • the first transistor T1 and the second transistor T2 may also be N-type transistors. This arrangement can reduce the leakage current of the node N through the first transistor T1 and the second transistor T2.
  • the display panel may further include: an active layer, a first conductive layer, and a third conductive layer, wherein the substrate, the active layer, the first conductive layer, the second conductive layer, and the third conductive layer
  • the structure layer, the fourth conductive layer, and the common electrode are stacked in sequence, and an insulating layer can also be provided between the above structural layers.
  • Figure 14 is a structural layout of another exemplary embodiment of the display panel of the present disclosure.
  • Figure 15 is a structural layout of the active layer in Figure 14.
  • Figure 16 is a structural layout of the first conductive layer in Figure 14.
  • Figure 17 is the structural layout of the second conductive layer in Figure 14
  • Figure 18 is the structural layout of the third conductive layer in Figure 14
  • Figure 19 is the structural layout of the fourth conductive layer in Figure 14
  • Figure 20 is the structural layout of Figure 14
  • Figure 21 is the structural layout of the active layer, the first conductive layer and the second conductive layer in Figure 14.
  • Figure 22 is the structural layout of the active layer and the first conductive layer in Figure 14. , the structural layout of the second conductive layer and the third conductive layer.
  • the channel region of the sixth transistor T6 and the seventh active portion 77 are used to form the channel region of the seventh transistor T7.
  • the first active part 71 includes a fourth sub-active part 714 and a fifth sub-active part 715
  • the second active part 72 includes a first sub-active part 721 and a second sub-active part 722 .
  • the active layer may further include a sixth sub-active part 716 connected between the fourth sub-active part 714 and the fifth sub-active part 715, a sixth sub-active part 716 connected between the first sub-active part 721 and the second sub-active part.
  • the eleventh active part 711 between the parts 77, the twelfth active part 712 connected to the side of the fifth active part 75 away from the third active part 73, the seventh active part 77 connected to the side away from the sixth active part 73.
  • the first active layer may be formed of polysilicon material.
  • the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P. low temperature polysilicon thin film transistor.
  • the first conductive layer may include: a first reset signal line Re1 , a second reset signal line Re2 , a gate line Gate, an enable signal line EM, and a third conductive portion 13 .
  • the first reset signal line Re1 is used to provide the first reset signal terminal in Figure 1
  • the second reset signal line Re2 is used to provide the second reset signal terminal in Figure 1
  • the gate line Gate is used to provide the first reset signal terminal in Figure 1.
  • Gate drive signal terminal, enable signal line EM is used to provide the enable signal terminal in Figure 1.
  • the orthographic projection of the first reset signal line Re1 on the base substrate may extend along the first direction X and cover the orthographic projection of the first active part 71 on the base substrate, and a partial structure of the first reset signal line Re1 is used to form The gate of the first transistor T1.
  • the orthographic projection of the second reset signal line Re2 on the base substrate may extend along the first direction The gate of the seventh transistor T7.
  • the orthographic projection of the enable signal line EM on the base substrate may extend along the first direction X and cover the orthographic projection of the fifth active part 75 on the base substrate and the orthographic projection of the sixth active part 76 on the base substrate.
  • Projection shows that a part of the structure of the enable signal line EM is used to form the gate electrode of the fifth transistor T5, and another part of the structure of the enable signal line EM is used to form the gate electrode of the sixth transistor T6.
  • the orthographic projection of the gate line Gate on the base substrate extends along the first direction X and covers the orthographic projection of the second active part 72 on the base substrate and the orthographic projection of the fourth active part 74 on the base substrate.
  • Part of the structure of the gate line Gate is used to form the gate electrode of the second transistor T2 and another part of the structure of the gate line Gate is used to form the gate electrode of the fourth transistor T4.
  • the orthographic projection of the third conductive part 13 on the base substrate covers the orthographic projection of the third active part 73 on the base substrate, and the third conductive part 13 is used to form the gate of the driving transistor T3.
  • the third conductive part 13 may also share the second electrode of the capacitor C.
  • the orthographic projection of the third conductive part 13 on the base substrate may be located between the orthographic projection of the gate line Gate on the base substrate and the orthographic projection of the enable signal line EM on the base substrate.
  • the orthographic projection of the first reset signal line Re1 on the base substrate may be located on a side away from the orthographic projection of the gate line Gate on the base substrate and the orthographic projection of the third conductive part 13 on the base substrate.
  • the orthographic projection of the second reset signal line Re2 on the base substrate may be located on a side away from the orthographic projection of the enable signal line EM on the base substrate and the orthographic projection of the third conductive part 13 on the base substrate.
  • the second reset signal line Re2 in the pixel driving circuit of the previous row can be shared as the first reset signal line Re1 in the pixel driving circuit of this row. This arrangement can reduce the pixel driving time. The dimensions of the circuit in the second direction.
  • the display panel can use the first conductive layer as a mask to perform conductive treatment on the active layer, that is, the area in the active layer covered by the first conductive layer can form the channel area of the transistor, and the area in the active layer that is not covered by the first conductive layer can form a channel area of the transistor.
  • the area covered by the first conductive layer forms a conductor structure.
  • the second conductive layer may include a first initial signal line Vinit1 , a second initial signal line Vinit2 , a first conductive part 21 , and a second conductive part 22 .
  • the first initial signal line Vinit1 may be used to provide the first initial signal terminal in FIG. 1
  • the second initial signal line Vinit2 may be used to provide the second initial signal terminal in FIG. 1 .
  • Both the orthographic projection of the first initial signal line Vinit1 on the base substrate and the orthographic projection of the second initial signal line Vinit2 on the base substrate can extend along the first direction X.
  • the orthographic projection of the first conductive part 21 on the base substrate may at least partially overlap with the orthographic projection of the third conductive part 13 on the base substrate, and the first conductive part 21 may be used to form the first electrode of the capacitor C, where , a plurality of first conductive parts 21 distributed in the first direction X may be connected in sequence to form a first conductive line D1. A plurality of second conductive parts 22 distributed in the first direction X may be connected in sequence to form a second conductive line D2.
  • the orthographic projection of the second conductive portion 22 on the base substrate may be located between the orthographic projection of the first reset signal line Re1 on the base substrate and the gate line. Gate is between the orthographic projections on the base substrate.
  • the orthographic projection of the third conductive part 13 on the base substrate may be located between the orthographic projection of the first initial signal line Vinit1 on the base substrate and the second initial signal
  • the orthographic projection of line Vinit2 on the base substrate is between the orthographic projection of the first initial signal line Vinit1 on the base substrate and the orthographic projection of the first reset signal line Re1 on the base substrate.
  • the orthographic projection is away from the side of the orthographic projection of the third conductive portion 13 on the base substrate.
  • the orthographic projection of the second initial signal line Vinit2 in the previous row of pixel driving circuits on the substrate may be located at the first initial signal line Vinit1 in the current row of pixel driving circuits.
  • the second conductive part 22 may include a third sub-conductive part 223 , and the orthographic projection of the third sub-conductive part 223 on the substrate is the same as the third sub-active part 723 on the substrate.
  • the voltage change of the active part 723 causes the problem of leakage to the source and drain of the second transistor T2.
  • the orthographic projection of the second initial signal line Vinit2 in the previous row of pixel driving circuits on the substrate may at least partially overlap with the orthographic projection of the sixth sub-active part 716 in the current row of pixel driving circuits on the substrate, and the second The initial signal line Vinit2 can stabilize the voltage of the sixth sub-active part 716, thereby improving the problem of leakage to the source and drain of the first transistor T1 due to voltage changes of the sixth sub-active part 716.
  • the third conductive layer may include a second power line VDD, a first bridge portion 31, a second bridge portion 32, a third bridge portion 33, a fourth bridge portion 34, and a fifth bridge portion. 35.
  • the second power line VDD may be used to provide a second power terminal in the pixel driving circuit shown in FIG. 1 .
  • the orthographic projection of the second power line VDD on the base substrate may extend along the second direction, and the second power line VDD may be connected to the second conductive part 22 through a via hole to provide a stable voltage source to the second conductive part 22 . It should be understood that in other exemplary embodiments, a stable voltage source may also be provided to the second conductive part 22 through other signal lines.
  • the stable voltage source may be provided through the first power line VSS, the first initial signal line Vinit1, the second initial signal line VSS, and the second initial signal line Vinit1.
  • the signal line Vinit2 provides a stable voltage source to the second conductive part 22 .
  • the second power line VDD and the second conductive line D2 may also form a grid structure, thereby reducing the voltage drop caused by the resistance drop of the second power line VDD itself.
  • the second power line VDD may also be connected to the twelfth active part 712 through a via hole to connect the first pole and the second power terminal of the fifth transistor T5.
  • the first bridge portion 31 can be connected to the third conductive portion 13 and the eighth active portion 78 respectively through the via hole H to connect the gate electrode of the driving transistor T3 and the second electrode of the first transistor T1 and the first electrode of the second transistor T2. pole.
  • the first conductive part 21 may be provided with an opening 211
  • the orthographic projection of the via hole connected to the first bridge part 31 and the third conductive part 13 on the base substrate may be located on the opening 211 on the base substrate. within the orthographic projection on the via hole to prevent the conductive structure in the via hole from being connected to the first conductive portion 21 .
  • the second bridge portion 32 can be connected to the first conductive portion 21 through a via hole to connect the first electrode of the capacitor.
  • the third bridge part 33 may be connected to the thirteenth active part 713 and the second initial signal line Vinit2 through via holes respectively, so as to connect the first pole and the second initial signal terminal of the seventh transistor.
  • the fourth bridge part 34 may be connected to the tenth active part 710 and the first initial signal line Vinit1 through via holes respectively, so as to connect the first pole and the first initial signal terminal of the first transistor T1.
  • the fifth bridge portion 35 may be connected to the eleventh active portion 711 through a via hole to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.
  • the sixth bridge part 36 may be connected to the ninth active part 79 through a via hole to connect the first pole of the fourth transistor T4.
  • the second conductive part 22 may also include a first sub-conductive part 221.
  • the first sub-conductive part 221 is connected to the third sub-conductive part 223.
  • the first sub-conductive part 221 is on the lining.
  • the orthographic projection on the base substrate may extend along the first direction X and be located between the orthographic projection of the first bridge portion 31 on the base substrate and the orthographic projection of the first reset signal line Re1 on the base substrate, that is, The area covered by the orthographic projection of the first sub-conductive portion 221 on the base substrate moves infinitely in the second direction Y, and the area covered by the orthographic projection of the first bridge portion 31 on the base substrate moves infinitely in the second direction Y.
  • the first sub-conductive portion 221 can shield the noise influence of the first reset signal line Re1 on the first bridge portion 31 , thereby improving the stability of the node N voltage in the pixel driving circuit shown in FIG. 1 .
  • the area covered by the orthographic projection of the first sub-conductive portion 221 on the base substrate moving infinitely in the second direction Y can cover the orthographic projection of the first bridge portion 31 on the base substrate in the second direction Y. Move the covered area infinitely in direction Y.
  • the multiple columns of pixel driving circuits may also be provided with one first power line VSS corresponding to each other.
  • the first power line VSS may be connected to the second bridge portion 32 through a via hole to connect the first power terminal and the first electrode of the capacitor C.
  • the data line Da may be connected to the sixth bridge portion 36 through a via hole to connect the first pole of the fourth transistor T4 and the data signal terminal.
  • the fourth conductive layer may further include a fourth conductive part 44.
  • the fourth conductive part 44 is connected to the first power line VSS.
  • the orthographic projection of the fourth conductive part 44 on the base substrate may be consistent with the first power line VSS.
  • the orthographic projection of a bridge part 31 on the base substrate at least partially overlaps, and the fourth conductive part 44 can shield the noise influence of other signal lines on the first bridge part 31.
  • the orthographic projection of the fourth conductive portion 44 on the base substrate may cover the orthographic projection of the first bridge portion 31 on the base substrate.
  • the orthographic projection of the second power line VDD on the base substrate may be located between the orthographic projection of the data line Da on the base substrate and the orthographic projection of the first bridge portion 31 on the base substrate.
  • the orthographic projection of a power line VSS on the base substrate may be located on a side where the orthographic projection of the first bridge portion 31 on the base substrate is away from the orthographic projection of the second power line VDD on the base substrate.
  • the pixel driving circuit of this column The orthographic projection of the first power line VSS on the base substrate is located in the orthographic projection of the data line Da on the base substrate in the adjacent column pixel driving circuit and the orthogonal projection of the data line Da in the pixel driving circuit of this column.
  • the first bridge portion 31 is between orthographic projections on the base substrate.
  • the second power line VDD can shield the noise effect of the data line Da in the pixel driving circuit of this column on the first bridge part 31 in the pixel driving circuit of this column.
  • the second conductive part 22 may also be a second sub-conductive part 222.
  • the second sub-conductive part 222 is connected to the side of the first sub-conductive part 221 away from the third sub-conductive part 223.
  • the orthographic projection of the second sub-conductive portion 222 on the base substrate may extend along the second direction Y, and be located between the orthographic projection of the first bridge portion 31 on the base substrate and the data line Da on the base substrate.
  • the black square drawn on the side of the third conductive layer facing away from the base substrate represents the via hole through which the third conductive layer is connected to other levels on the side facing the base substrate;
  • the black squares on the side of the four conductive layers facing away from the base substrate represent the via holes of the fourth conductive layer connecting to other levels on the side facing the base substrate.
  • the black square only represents the location of the via hole. Different via holes represented by black squares at different positions can penetrate different insulation layers.
  • the display panel may further include a buffer layer 82, a first insulating layer 83, a second insulating layer 84, a first dielectric layer 85, a passivation layer 86, and a second dielectric layer 87, wherein the base substrate 81, the buffer layer 82. Active layer, first insulating layer 83, first conductive layer, second insulating layer 84, second conductive layer, first dielectric layer 85, third conductive layer, passivation layer 86, second dielectric layer 87.
  • the fourth conductive layers are stacked in sequence.
  • the first insulating layer 83 and the second insulating layer 84 can be silicon oxide layers
  • the first dielectric layer 85 and the second dielectric layer 87 can be silicon nitride layers
  • the passivation layer 86 and the buffer layer 82 can be made of silicon oxide. , silicon nitride, etc.
  • the base substrate 81 may include a glass substrate, a barrier layer, and a polyimide layer that are stacked in sequence.
  • the barrier layer may be an inorganic material.
  • the material of the first conductive layer and the second conductive layer may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or laminate.
  • the material of the third conductive layer and the fourth conductive layer may include metal materials, for example, it may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or laminate, or it may be titanium/aluminum /titanium lamination.
  • the display panel may further include a pixel electrode layer between the fourth conductive layer and the common electrode layer.
  • FIG. 24 is a structural layout of the display panel in another exemplary embodiment of the present disclosure
  • FIG. 25 is a structural layout of the pixel electrode layer in FIG. 24 .
  • the pixel electrode layer may include a plurality of electrode parts, and the electrode parts may be used to form the first electrode of the light-emitting unit.
  • the plurality of electrode parts include: a plurality of R electrode parts R, a plurality of G electrode parts G, and a plurality of B electrode parts. B.
  • the R electrode portion, the G electrode portion, the B electrode portion, and the G electrode portion are alternately distributed in the row direction; in the pixel driving circuits of two adjacent columns, multiple electrode portions are arranged alternately in the row direction.
  • the R electrode portions and the B electrode portions are connected to the same column pixel driving circuit, and the R electrode portions and the B electrode portions connected to the same column pixel driving circuit are alternately distributed in the column direction, and a plurality of The G electrode part is connected to another column of pixel driving circuits; the orthographic projection of the two G electrode parts connected to adjacent pixel driving circuit rows and connected to the same pixel driving circuit column on the base substrate in the column direction
  • the minimum distance S1 is smaller than the dimension S2 of the orthographic projection of the R electrode part on the base substrate in the column direction or the dimension S3 of the orthogonal projection of the B electrode part on the base substrate in the column direction.
  • the R electrode portion R and the B electrode portion B are hexagonal, and the G electrode portion G is pentagonal. It should be understood that in other exemplary embodiments, the R electrode portions R and B The corners of the electrode portions B and G can also be arc-shaped. This arrangement can improve the technical problem of color shift in the display panel.
  • the R electrode portion, the G electrode portion, the B electrode portion, and the G electrode portion are alternately distributed in the row direction; in the pixel driving circuits of two adjacent columns, multiple electrode portions are arranged alternately in the row direction.
  • the R electrode portion and the plurality of B electrode portions are connected to the pixel driving circuit of the same column, and the R electrode portion and the B electrode portion connected to the pixel driving circuit of the same column are alternately distributed in the column direction, and a plurality of the The G electrode portion is connected to another column of pixel driving circuits; the minimum distance in the column direction between two G electrode portions connected to adjacent pixel driving circuit rows and connected to the same pixel driving circuit column on the base substrate is S1 is larger than the size S2 of the orthographic projection of the R electrode portion on the base substrate in the column direction or the size S3 of the orthographic projection of the B electrode portion on the base substrate in the column direction.
  • the orthographic projection of the R electrode part on the base substrate and the pixel definition layer coincides with the orthographic projection of the corresponding opening on the base substrate
  • the G electrode part corresponds to the orthographic projection on the base substrate and the pixel definition layer.
  • the orthographic projections of the openings on the base substrate coincide with each other
  • the orthographic projections of the B electrode portions on the base substrate coincide with the orthographic projections of the corresponding openings on the pixel definition layer on the base substrate.
  • the scale of the drawings in this disclosure can be used as a reference in the actual process, but is not limited thereto, for example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line, It can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the figures described in this disclosure are only structural schematic diagrams.
  • the first, second and other qualifiers are only used to define different structure names and have no specific order meaning.
  • This exemplary embodiment also provides a display device, which includes the above-mentioned display panel.
  • the display device can be a display device such as a mobile phone, a tablet computer, or a television.

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Abstract

一种显示面板及显示装置，显示面板包括沿第一方向(X)和第二方向(Y)阵列分布的子像素单元，第一方向(X)和第二方向(Y)相交，子像素单元包括像素驱动电路和发光单元(OLED)，像素驱动电路连接发光单元(OLED)的第一电极，像素驱动电路包括驱动晶体管(T3)和电容(C)，电容(C)的第一电极连接第一电源线(VSS)，电容(C)的第二电极连接驱动晶体管(T3)的栅极，显示面板还包括：衬底基板(81)、第二导电层、第四导电层、公共电极层(6)，第二导电层位于衬底基板(81)的一侧，第二导电层包括多个第一导电部(21)，第一导电部(21)和像素驱动电路对应设置，第一导电部(21)用于形成与其对应的像素驱动电路中电容(C)的第一电极；第四导电层位于第二导电层背离衬底基板(81)的一侧，第四导电层包括多条第一电源线(VSS)，第一电源线(VSS)在衬底基板(81)上的正投影沿第一方向(X)间隔分布且沿第二方向(Y)延伸，第一导电部(21)通过过孔连接第一电源线(VSS)；公共电极层(6)位于第四导电层背离衬底基板(81)的一侧，公共电极层(6)用于形成发光单元(OLED)的第二电极，第一电源线(VSS)通过过孔连接公共电极层(6)。该显示面板可以降低由于公共电极层(6)自身电阻造成的压降。 (图3)

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
相关技术中，显示面板中的像素电路通常包括驱动晶体管，为使得驱动晶体管工作在饱和区，驱动晶体管的源漏极之间需要施加较大的跨压。然而，由于显示面板中公共电极层的方块电阻较大，从而导致显示面板需要提供较大的电源电压才能实现正常驱动，进而使得显示面板的功耗较大。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
根据本公开的一个方面，提供一种显示面板，其中，所述显示面板包括沿第一方向和第二方向阵列分布的子像素单元，所述第一方向和所述第二方向相交，所述子像素单元包括像素驱动电路和发光单元，所述像素驱动电路连接所述发光单元的第一电极，所述像素驱动电路包括驱动晶体管和电容，所述电容的第一电极连接第一电源线，所述电容的第二电极连接所述驱动晶体管的栅极，所述显示面板还包括：衬底基板、第二导电层、第四导电层、公共电极层，第二导电层位于所述衬底基板的一侧，所述第二导电层包括多个第一导电部，所述第一导电部和所述像素驱动电路对应设置，所述第一导电部用于形成与其对应的所述像素驱动电路中所述电容的第一电极；第四导电层位于所述第二导电层背离所述衬底基板的一侧，所述第四导电层包括多条所述第一电源线，所述第一电源线在所述衬底基板上的正投影沿所述第一方向间隔分布且沿所述第二方向延伸，所述第一导电部通过过孔连接所述第一电源线；公共电极层位于所述第四导电层背 离所述衬底基板的一侧，所述公共电极层用于形成所述发光单元的第二电极，所述第一电源线通过过孔连接所述公共电极层。
本公开一种示例性实施例中，在所述第一方向上分布的至少部分所述第一导电部依次连接以形成第一导电线，所述第一导电线连接多条所述第一电源线。
本公开一种示例性实施例中，在所述第一方向上分布的所有所述第一导电部依次连接以形成第一导电线，所述第一导电线连接每一条所述第一电源线。
本公开一种示例性实施例中，在所述第一方向上分布的多个所述第一导电部形成在所述第一方向上间隔分布多条所述第一导电线；在所述第一方向和所述第二方向上均相邻的两所述第一导电线在所述第一方向上交错分布，交错分布的两所述第一导电线共同连接至少两条所述第一电源线。
本公开一种示例性实施例中，所述像素驱动电路还包括第六晶体管，所述第六晶体管的第一极连接所述驱动晶体管的第二极，第二极连接所述发光单元的第一电极，所述第六晶体管为P型晶体管，所述第一电源线用于提供低电平电源信号。所述显示面板还包括：有源层，有源层位于所述衬底基板和所述第二导电层之间，所述有源层包括第六有源部，所述第六有源部用于形成所述第六晶体管的沟道区；所述第一电源线在所述衬底基板上的正投影与所述第六有源部在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极。所述第二导电层还包括：第二导电部，第二导电部连接一稳定电源端。所述显示面板还包括：有源层，有源层位于所述衬底基板和所述第二导电层之间，所述有源层包括：第二有源部、第三子有源部，所述第二有源部包括第一子有源部和第二子有源部，所述第三子有源部连接于所述第一子有源部和所述第二子有源部之间，所述第一子有源部用于形成所述第二晶体管的第一沟道区，所述第二子有源部用于形成所述第二晶体管的第二沟道区；其中，所述第二导电部在所述衬底基板上的正投影和所述第三子有源部在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述驱动晶体管的第一极连接第二电源线，所述第二导电部通过过孔连接所述第二电源线；所述第二导电层包括多个所述第二导电部，所述第二导电部与所述像素驱动电路对应设置，在所述第一方向上分布的至少部分所述第二导电部依次连接以形成第二导电线；所述显示面板还包括多条所述第二电源线，多条所述第二电源线在所述衬底基板上的正投影沿所述第一方向间隔分布且沿所述第二方向延伸，所述第二导电线连接多条所述第二电源线。
本公开一种示例性实施例中，所述像素驱动电路还包括第一晶体管，所述第一晶体管的第一极连接第一初始信号线，第二极连接所述驱动晶体管的栅极；所述有源层还包括第一有源部和第三有源部，所述第一有源部用于形成所述第一晶体管的沟道区，所述第三有源部用于形成所述驱动晶体管的沟道区。所述显示面板还包括：第一导电层，第一导电层位于所述有源层和所述第二导电层之间，所述第一导电层包括：第一复位信号线、栅线、第三导电部，第一复位信号线在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第一有源部在所述衬底基板上的正投影，所述第一复位信号线的部分结构用于形成所述第一晶体管的栅极；栅线在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第二有源部在所述衬底基板上的正投影，所述栅线的部分结构用于形成所述第二晶体管的栅极；所述第三导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第三导电部用于形成所述驱动晶体管的栅极；其中，所述第一复位信号线在所述衬底基板上的正投影位于所述栅线在所述衬底基板上的正投影远离所述第三导电部在所述衬底基板上的正投影的一侧，所述第二导电部在所述衬底基板上的正投影位于所述第一复位信号线在所述衬底基板上的正投影和所述栅线在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述显示面板还包括：第三导电层，第三导电层位于所述第二导电层和所述第四导电层之间，所述第三导电层包括第一桥接部，所述第一桥接部通过过孔连接所述第三导电部且连接所述第二晶体管的第一极；所述第二导电部包括：第一子导电部，所述第一子导电部在所述衬底基板上的正投影沿所述第一方向延伸，且位于所述第一 桥接部在所述衬底基板上的正投影和所述第一复位信号线在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述显示面板还包括：数据线，数据线在所述衬底基板上的正投影沿所述第二方向延伸。所述第二导电部还包括：第二子导电部，第二子导电部连接于所述第一子导电部，所述第二子导电部在所述衬底基板上的正投影沿所述第二方向延伸，且位于所述第一桥接部在所述衬底基板上的正投影和所述数据线在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述驱动晶体管连接第二电源线，所述像素驱动电路还包括第二晶体管，第四晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，所述第二晶体管的第二极连接所述驱动晶体管的第二极，所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极。所述显示面板还包括：有源层、第一导电层、第三导电层，有源层位于所述衬底基板和所述第二导电层之间，所述有源层包括第三有源部，所述第三有源部用于形成所述驱动晶体管的沟道区；第一导电层位于所述有源层和所述第二导电层之间，所述第一导电层包括第三导电部，所述第三导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第三导电部用于形成所述驱动晶体管的栅极；第三导电层位于所述第二导电层和所述第四导电层之间，所述第三导电层包括第一桥接部，所述第一桥接部通过过孔连接所述第三导电部且连接所述第二晶体管的第一极；所述第二方向为列方向，在同一列像素驱动电路中，所述第二电源线在所述衬底基板上的正投影沿所述第二方向延伸，所述数据线在所述衬底基板上的正投影沿所述第二方向延伸，且所述第二电源线在所述衬底基板上的正投影位于所述数据线在所述衬底基板上的正投影和所述第一桥接部在所述衬底基板上的正投影之间，所述第一电源线在所述衬底基板上的正投影位于所述第一桥接部在所述衬底基板上的正投影远离所述第二电源线在所述衬底基板上的正投影的一侧；在相邻列像素驱动电路中，本列像素驱动电路中的所述第一电源线在所述衬底基板上的正投影位于相邻列像素驱动电路中所述数据线在所述衬底基板上的正投影和本列像素驱动电路中所述第一桥接部在所述 衬底基板上的正投影之间。
本公开一种示例性实施例中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极。所述显示面板还包括：有源层、第一导电层、第三导电层，有源层位于所述衬底基板和所述第二导电层之间，所述有源层包括第三有源部，所述第三有源部用于形成所述驱动晶体管的沟道区；第一导电层位于所述有源层和所述第二导电层之间，所述第一导电层包括第三导电部，所述第三导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第三导电部用于形成所述驱动晶体管的栅极；第三导电层位于所述第二导电层和所述第四导电层之间，所述第三导电层包括第一桥接部，所述第一桥接部通过过孔连接所述第三导电部且连接所述第二晶体管的第一极。所述第四导电层还包括：第四导电部，第四导电部连接所述第一电源线，且所述第四导电部在所述衬底基板上的正投影与所述第一桥接部在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述像素驱动电路还包括第一晶体管、第七晶体管，所述第一晶体管的第一极连接第一初始信号线，第二极连接所述驱动晶体管的栅极，所述第七晶体管的第一极连接第二初始信号线，第二极连接所述发光单元的第一极。所述显示面板还包括：有源层、第一导电层，有源层位于所述衬底基板和所述第二导电层之间，所述有源层包括第一有源部、第七有源部，所述第一有源部用于形成所述第一晶体管的沟道区，所述第七有源部用于形成所述第七晶体管的沟道区。第一导电层位于所述有源层和所述第二导电层之间，所述第一导电层包括：第一复位信号线、第二复位信号线，第一复位信号线在所述衬底基板上的正投影沿所述第一方向延伸，且覆盖所述第一有源部在所述衬底基板上的正投影，所述第一复位信号线的部分结构用于形成所述第一晶体管的栅极；第二复位信号线在所述衬底基板上的正投影沿所述第一方向延伸，且覆盖所述第七有源部在所述衬底基板上的正投影，所述第二复位信号线的部分结构用于形成所述第七晶体管的栅极；其中，所述第一方向为行方向，在相邻行像素驱动电路中，上一行像素驱动电路中的所述第二复位信号线共用为本行像素驱动电路中的所述第一复位信号线。
本公开一种示例性实施例中，所述有源层还包括：第三有源部，所述第三有源部用于形成所述驱动晶体管的沟道区。所述第一导电层还包括：第三导电部，所述第三导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第三导电部用于形成所述驱动晶体管的栅极。所述第二导电层还包括：所述第一初始信号线、所述第二初始信号线，所述第一初始信号线在所述衬底基板上的正投影沿所述第一方向延伸；所述第二初始信号线在所述衬底基板上的正投影沿所述第一方向延伸。其中，在同一行像素驱动电路中，所述第三导电部在所述衬底基板上的正投影位于所述第一初始信号线在所述衬底基板上的正投影和所述第二初始信号线在所述衬底基板上的正投影之间，且所述第一初始信号线在所述衬底基板上的正投影位于所述第一复位信号线在所述衬底基板上的正投影远离所述第三导电部在所述衬底基板上的正投影的一侧；在相邻行像素驱动电路中，上一行像素驱动电路中的所述第二初始信号线在所述衬底基板上的正投影位于本行像素驱动电路中所述第一初始信号线在所述衬底基板上的正投影和本行像素驱动电路中所述第一复位信号线在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述第一有源部包括第四子有源部和第五子有源部，所述有源层还包括连接于所述第四子有源部和所述第五子有源部之间的第六子有源部；上一行像素驱动电路中所述第二初始信号线在所述衬底基板上的正投影与本行像素驱动电路中所述第六子有源部在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述像素驱动电路还包括第一晶体管、第二晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管；所述第一晶体管的第一极连接第一初始信号线，第二极连接所述驱动晶体管栅极；所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极；所述第四晶体管的第一极连接数据线，第二极连接所述驱动晶体管的第一极；所述第五晶体管的第一极连接第二电源线，第二极连接所述驱动晶体管的第一极；所述第六晶体管的第一极连接所述驱动晶体管的第二极，第二极连接所述发光单元的第一电极；所述第七晶体管的第一极连接第二初始信号线，第二极连接所述发光单元的第一电极； 所述第一晶体管、第二晶体管、驱动晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管均为P型晶体管。
本公开一种示例性实施例中，所述显示面板还包括：有源层、第一导电层。有源层位于所述衬底基板和所述第二导电层之间，所述有源层包括：第三有源部、第四有源部、第五有源部、第六有源部、第七有源部，所述第三有源部用于形成所述驱动晶体管的沟道区，所述第四有源部用于形成所述第四晶体管的沟道区，所述第五有源部用于形成所述第五晶体管的沟道区，所述第六有源部用于形成所述第六晶体管的沟道区，所述第七有源部用于形成所述第七晶体管的沟道区。第一导电层位于所述有源层和所述第二导电层之间，所述第一导电层包括：栅线、使能信号线、第二复位信号线、第三导电部。栅线在所述衬底基板上的正投影沿所述第一方向延伸，且覆盖所述第四有源部在所述衬底基板上的正投影，所述栅线的部分结构用于形成所述第四晶体管的栅极；使能信号线在所述衬底基板上的正投影沿所述第一方向延伸，且覆盖所述第五有源部在所述衬底基板上的正投影和所述第六有源部在所述衬底基板上的正投影，所述使能信号线的部分结构用于形成所述第五晶体管的栅极，且所述使能信号线的另外部分结构用于形成所述第六晶体管的栅极；第二复位信号线在所述衬底基板上的正投影沿所述第一方向延伸，且覆盖所述第七有源部在所述衬底基板上的正投影，所述第二复位信号线的部分结构用于形成所述第七晶体管的栅极；第三导电部所述第三导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第三导电部用于形成所述驱动晶体管的栅极；其中，在同一行像素驱动电路中，所述使能信号线在所述衬底基板上的正投影位于所述第三导电部在所述衬底基板上的正投影和所述第二复位信号线在所述衬底基板上的正投影之间。
根据本公开的一个方面，提供一种显示装置，其中，包括上述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合 本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开显示面板一种示例性实施例中像素驱动电路的电路结构示意图；
图2为图1所示像素驱动电路一种驱动方法中各节点的时序图；
图3为本公开显示面板一种示例性实施例的结构版图；
图4为图3中第二导电层的结构版图；
图5为图3中第四导电层的结构版图；
图6为图3中公共电极的结构版图；
图7为图3中第二导电层和第四导电层的结构版图；
图8为本公开显示面板另一种示例性实施例的结构版图；
图9为图8中第二导电层的结构版图；
图10为图8中第二导电层和第四导电层的结构版图；
图11为本公开显示面板另一种示例性实施例的结构版图；
图12为图11中第二导电层的结构版图；
图13为图11中第二导电层和第四导电层的结构版图；
图14为本公开显示面板另一种示例性实施例的结构版图；
图15为图14中有源层的结构版图；
图16为图14中第一导电层的结构版图；
图17为图14中第二导电层的结构版图；
图18为图14中第三导电层的结构版图；
图19为图14中第四导电层的结构版图；
图20为图14中有源层、第一导电层的结构版图；
图21为图14中有源层、第一导电层、第二导电层的结构版图；
图22为图14中有源层、第一导电层、第二导电层、第三导电层的结构版图；
图23为图14所示显示面板沿虚线AA剖开的部分剖视图；
图24为本公开显示面板另一种示例性实施例中的结构版图；
图25为图24中像素电极层的结构版图；
图26为本公开显示面板另一种示例性实施例中像素电极层的结构版图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
如图1所示，为本公开显示面板一种示例性实施例中像素驱动电路的电路结构示意图。该像素驱动电路可以包括：第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、电容C。其中，第一晶体管T1的第一极连接第一初始信号端Vinit1，第二极连接节点N，栅极连接第一复位信号端Re1；第二晶体管T2第一极连接驱动晶体管T3的栅极，第二极连接驱动晶体管T3的第二极；栅极连接栅极驱动信号端Gate；驱动晶体管T3的栅极连接节点N；第四晶体管T4的第一极连接数据信号端Da，第二极连接驱动晶体管T3的第一极，栅极连接栅极驱动信号端Gate；第五晶体管T5的第一极连接第二电源端VDD，第二极连接驱动晶体管T3的第一极，栅极连接使能信号端EM；第六晶体管T6第一极连接驱动晶体管T3的第二极，栅极连接使能信号端EM；第七晶体管T7的第一极连接第二初始信号端Vinit2，第二极连接第六晶体管T6的第二极，栅极连接第二复位信号端Re2。电容C的第一电极连接第一电源端VSS，电容C的第二电极连接驱动晶体管T3的栅极。该像素驱动电路可以连接一发光单元OLED，该像素驱动电路用于驱动该发光单元OLED发光，发光单元OLED的第一电极可以连接第六晶体管T6的第二极，发光单元OLED的第二电极可以连接第一电源端VSS。其中，第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管 T5、第六晶体管T6、第七晶体管T7可以均为P型晶体管。
如图2所示，为图1所示像素驱动电路一种驱动方法中各节点信号的时序图。其中，Gate表示栅极驱动信号端Gate信号的时序，Re1表示第一复位信号端Re1信号的时序，Re2表示第二复位信号端Re2信号的时序，EM表示使能信号端EM信号的时序，Da表示数据信号端Da信号的时序。该像素驱动电路的驱动方法可以包括复位阶段t1、补偿阶段t2，发光阶段t3。在复位阶段t1：第一复位信号端Re1输出低电平信号，第一晶体管T1导通，第一初始信号端Vinit1向节点N输入第一初始信号。在补偿阶段t2：第二复位信号端Re2、栅极驱动信号端Gate输出低电平信号，第四晶体管T4、第二晶体管T2、第七晶体管T7导通，同时数据信号端Da输出数据信号以向节点N写入电压Vdata+Vth，其中Vdata为数据信号的电压，Vth为驱动晶体管T3的阈值电压，第二初始信号端Vinit2向第六晶体管T6的第二极输入第二初始信号。在发光阶段t3：使能信号端EM输出低电平信号，第六晶体管T6、第五晶体管T5导通，驱动晶体管T3在节点N的电压Vdata+Vth作用下驱动发光单元发光。根据驱动晶体管输出电流公式I＝(μWCox/2L)(Vgs-Vth)2，其中，μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电压。本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth)2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。
本示例性实施例还提供一种显示面板，所述显示面板可以子像素单元，所述子像素单元包括像素驱动电路和发光单元，所述像素驱动电路连接所述发光单元的第一电极，该像素驱动电路可以如图1所示。该显示面板还可以包括依次层叠设置的衬底基板、第二导电层、第四导电层、公共电极层，如图3-7所示，图3为本公开显示面板一种示例性实施例的结构版图，图4为图3中第二导电层的结构版图，图5为图3中第四导电层的结构版图，图6为图3中公共电极的结构版图，图7为图3中第二导电层和第四导电层的结构版图。本示例性实施例中，该显示面板包括沿第一方向X和第二方向Y阵列分布的多个子像素单元，相应的，该显示面板包括沿第一 方向X和第二方向Y阵列分布的多个像素驱动电路。其中，第一方向X和第二方向Y相交，例如，第一方向X可以为行方向，第二方向Y可以为列方向。
如图3、4、7所示，所述第二导电层可以包括多个第一导电部21，所述第一导电部21和所述像素驱动电路对应设置，所述第一导电部21可以用于形成与其对应的所述像素驱动电路中所述电容C的第一电极。
如图3、5、7所示，所述第四导电层可以包括多条第一电源线VSS，第一电源线VSS可以提供图1中的第一电源端VSS。所述第一电源线VSS在所述衬底基板上的正投影可以沿所述第一方向X间隔分布且沿所述第二方向Y延伸，所述第一导电部21可以通过过孔H连接所述第一电源线VSS。其中，黑色方块表示过孔的位置，本示例性实施例仅对部分过孔位置进行了标注。在本示例性实施例中，某一结构在衬底基板上的正投影沿某一方向延伸，可以理解为，该结构在衬底基板上的正投影沿该方向直线延伸或弯折延伸。
如图3、6所示，公共电极层6可以为一整体结构，第一电源线VSS可以在显示面板的边沿走线区通过过孔与公共电极层6连接。
本示例性实施例中，第一电源线VSS的至少部分结构位于显示面板的显示区，第一电源线VSS可以降低由于公共电极层6自身电阻造成的压降，从而可以使得图1中第一电源端VSS和第二电源端VDD在保证驱动晶体管工作在饱和区的前提下，降低显示面板的功耗。此外，该显示面板将电容C的第一电极(第一导电部21)连接到第一电源线VSS，从而可以降低第一电源线VSS的自身电阻，进而可以进一步降低由于公共电极层6自身电阻造成的压降。
本示例性实施例中，如图8-10所示，图8为本公开显示面板另一种示例性实施例的结构版图，图9为图8中第二导电层的结构版图，图10为图8中第二导电层和第四导电层的结构版图。
本示例性实施例中，图8所示显示面板和图3所示显示面板区别在于，在所述第一方向X上分布的所有所述第一导电部21依次连接以形成第一导电线D1，所述第一导电线D1连接每一条所述第一电源线VSS。该设置可以使得第一电源线VSS和第一导电线D1形成网格结构，从而可以进一 步降低由于公共电极层6自身电阻造成的压降。
应该理解的是，在其他示例性实施例中，在所述第一方向X上分布的第一导电部21也可仅部分依次连接以形成第一导电线，所述第一导电线可以连接多条所述第一电源线。例如，如图11-13所示，图11为本公开显示面板另一种示例性实施例的结构版图，图12为图11中第二导电层的结构版图，图13为图11中第二导电层和第四导电层的结构版图。本示例性实施例中，在所述第一方向X上分布的多个所述第一导电部21可以形成在所述第一方向X上间隔分布多条所述第一导电线D1。在所述第一方向X和所述第二方向Y上均相邻的两第一导电线D1可以在所述第一方向X上交错分布，即在所述第一方向X和所述第二方向Y上均相邻的两第一导电线D1在衬底基板上的正投影在第二方向Y上无限移动所覆盖的区域部分相交。第一导电线D1可以连接两条第一电源线VSS。该设置同样可以使得第一电源线VSS和第一导电线D1形成网格结构。
应该理解的是，在其他示例性实施例中，该显示面板中的像素驱动电路还可以为其他结构，只要像素驱动电路中电容C的第一电极和发光单元的公共电极连接同一信号端，该显示面板均可以通过上述方案降低由于公共电极自身电阻造成的压降。例如，图1所示像素驱动电路中，第一晶体管T1、第二晶体管T2还可以为N型晶体管，该设置可以降低节点N通过第一晶体管T1和第二晶体管T2的漏电流。
本示例性实施例中，显示面板还可以包括：有源层、第一导电层、第三导电层，其中，衬底基板、有源层、第一导电层、第二导电层、第三导电层、第四导电层、公共电极依次层叠设置，且上述结构层之间还可以设置有绝缘层。如图14-22所示，图14为本公开显示面板另一种示例性实施例的结构版图，图15为图14中有源层的结构版图，图16为图14中第一导电层的结构版图，图17为图14中第二导电层的结构版图，图18为图14中第三导电层的结构版图，图19为图14中第四导电层的结构版图，图20为图14中有源层、第一导电层的结构版图，图21为图14中有源层、第一导电层、第二导电层的结构版图，图22为图14中有源层、第一导电层、第二导电层、第三导电层的结构版图。
如图14、15、20所示，有源层可以包括第一有源部71、第二有源部 72、第三有源部73、第四有源部74、第五有源部75、第六有源部76、第七有源部77。其中，第一有源部71用于形成第一晶体管T1的沟道区，第二有源部72用于形成第二晶体管T2的沟道区，第三有源部73用于形成驱动晶体管T3的沟道区，第四有源部74用于形成第四晶体管T4的沟道区，第五有源部75用于形成第五晶体管T5的沟道区，第六有源部76用于形成第六晶体管T6的沟道区，第七有源部77用于形成第七晶体管T7的沟道区。其中，第一有源部71包括第四子有源部714和第五子有源部715，第二有源部72包括第一子有源部721和第二子有源部722。有源层还可以包括连接于第四子有源部714和第五子有源部715之间的第六子有源部716、连接于第一子有源部721和第二子有源部722之间的第三子有源部723、连接于第二有源部72和第一有源部71之间的第八有源部78、连接于第四有源部74远离第三有源部73一侧的第九有源部79、连接于第一有源部71远离第二有源部72一侧的第十有源部710、连接于第六有源部76和第七有源部77之间的第十一有源部711、连接于第五有源部75远离第三有源部73一侧的第十二有源部712、连接于第七有源部77远离第六有源部76一侧的第十三有源部713。第一有源层可以由多晶硅材料形成，相应的，第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型的低温多晶硅薄膜晶体管。
如图14、16、20所示，第一导电层可以包括：第一复位信号线Re1、第二复位信号线Re2、栅线Gate、使能信号线EM、第三导电部13。其中，第一复位信号线Re1用于提供图1中的第一复位信号端，第二复位信号线Re2用于提供图1中的第二复位信号端，栅线Gate用于提供图1中的栅极驱动信号端，使能信号线EM用于提供图1中的使能信号端。第一复位信号线Re1在衬底基板上的正投影可以沿第一方向X延伸且覆盖第一有源部71在衬底基板上的正投影，第一复位信号线Re1的部分结构用于形成第一晶体管T1的栅极。第二复位信号线Re2在衬底基板上的正投影可以沿第一方向X延伸且覆盖第七有源部77在衬底基板上的正投影，第二复位信号线Re2的部分结构用于形成第七晶体管T7的栅极。使能信号线EM在衬底基板上的正投影可以沿第一方向X延伸且覆盖第五有源部75在衬底基 板上的正投影、第六有源部76在衬底基板上的正投影，使能信号线EM的部分结构用于形成第五晶体管T5的栅极，使能信号线EM的另外部分结构用于形成第六晶体管T6的栅极。栅线Gate在衬底基板上的正投影沿第一方向X延伸且覆盖第二有源部72在衬底基板上的正投影、第四有源部74在衬底基板上的正投影，栅线Gate的部分结构用于形成第二晶体管T2的栅极，栅线Gate的另外部分结构用于形成第四晶体管T4的栅极。第三导电部13在衬底基板上的正投影覆盖第三有源部73在衬底基板上的正投影，第三导电部13用于形成驱动晶体管T3的栅极。第三导电部13还可以共用为电容C的第二电极。其中，第三导电部13在衬底基板上的正投影可以位于栅线Gate在衬底基板上的正投影和使能信号线EM在衬底基板上的正投影之间。第一复位信号线Re1在衬底基板上的正投影可以位于栅线Gate在衬底基板上的正投影远离第三导电部13在衬底基板上的正投影的一侧。第二复位信号线Re2在衬底基板上的正投影可以位于使能信号线EM在衬底基板上的正投影远离第三导电部13在衬底基板上的正投影的一侧。在相邻行像素驱动电路中，上一行像素驱动电路中的所述第二复位信号线Re2可以共用为本行像素驱动电路中的所述第一复位信号线Re1，该设置可以减小像素驱动电路在第二方向上的尺寸。此外，该显示面板可以利用第一导电层为掩膜对有源层进行导体化处理，即有源层中被第一导电层覆盖的区域可以形成晶体管的沟道区，有源层中未被第一导电层覆盖的区域形成导体结构。
如图14、17、21所示，第二导电层可以包括第一初始信号线Vinit1、第二初始信号线Vinit2、第一导电部21、第二导电部22。第一初始信号线Vinit1可以用于提供图1中的第一初始信号端，第二初始信号线Vinit2可以用于提供图1中的第二初始信号端。第一初始信号线Vinit1在衬底基板上的正投影、第二初始信号线Vinit2在衬底基板上的正投影均可以沿第一方向X延伸。第一导电部21在衬底基板上的正投影可以与第三导电部13在衬底基板上的正投影至少部分交叠，第一导电部21可以用于形成电容C的第一电极，其中，在第一方向X上分布的多个第一导电部21可以依次连接以形成第一导电线D1。在第一方向X上分布的多个第二导电部22可以依次连接以形成第二导电线D2。在同一行像素驱动电路中，所 述第二导电部22在所述衬底基板上的正投影可以位于所述第一复位信号线Re1在所述衬底基板上的正投影和所述栅线Gate在所述衬底基板上的正投影之间。在同一行像素驱动电路中，第三导电部13在所述衬底基板上的正投影可以位于所述第一初始信号线Vinit1在所述衬底基板上的正投影和所述第二初始信号线Vinit2在所述衬底基板上的正投影之间，且所述第一初始信号线Vinit1在所述衬底基板上的正投影位于所述第一复位信号线Re1在所述衬底基板上的正投影远离所述第三导电部13在所述衬底基板上的正投影的一侧。在相邻行像素驱动电路中，上一行像素驱动电路中的所述第二初始信号线Vinit2在所述衬底基板上的正投影可以位于本行像素驱动电路中所述第一初始信号线Vinit1在所述衬底基板上的正投影和本行像素驱动电路中所述第一复位信号线Re1在所述衬底基板上的正投影之间，该设置可以进一步减小像素驱动电路在第二方向上的尺寸。如图14、17、21所示，第二导电部22可以包括的第三子导电部223，第三子导电部223在衬底基板上的正投影与第三子有源部723在衬底基板上的正投影至少部分交叠，第二导电部22可以连接一稳定电压源，第三子导电部223可以对第三子有源部723起到稳压作用，从而可以改善由于第三子有源部723电压变化产生向第二晶体管T2源漏极漏电的问题。上一行像素驱动电路中第二初始信号线Vinit2在衬底基板上的正投影可以与本行像素驱动电路中第六子有源部716在衬底基板上的正投影至少部分交叠，第二初始信号线Vinit2可以对第六子有源部716起到稳压作用，从而可以改善由于第六子有源部716电压变化产生向第一晶体管T1源漏极漏电的问题。
如图14、18、22所示，第三导电层可以包括第二电源线VDD、第一桥接部31、第二桥接部32、第三桥接部33、第四桥接部34、第五桥接部35、第六桥接部36。其中，第二电源线VDD可以用于提供图1所示像素驱动电路中的第二电源端。第二电源线VDD在衬底基板上的正投影可以沿第二方向延伸，第二电源线VDD可以通过过孔连接第二导电部22，以向第二导电部22提供稳定电压源。应该理解的是，在其他示例性实施例中，还可以通过其他信号线向第二导电部22提供稳定电压源，例如，可以通过第一电源线VSS、第一初始信号线Vinit1、第二初始信号线Vinit2向第二导 电部22提供稳定电压源。第二电源线VDD和第二导电线D2还可以形成网格结构，从而可以降低由于第二电源线VDD自身电阻降造成的压降。第二电源线VDD还可以通过过孔连接第十二有源部712，以连接第五晶体管T5的第一极和第二电源端。第一桥接部31可以分别通过过孔H连接第三导电部13和第八有源部78，以连接驱动晶体管T3的栅极和第一晶体管T1的第二极、第二晶体管T2的第一极。如图17所示，第一导电部21上可以设置有开口211，连接于第一桥接部31和第三导电部13的过孔在衬底基板上的正投影可以位于开口211在衬底基板上的正投影以内，以避免该过孔内的导电结构与第一导电部21连接。第二桥接部32可以通过过孔连接第一导电部21，以连接电容的第一电极。第三桥接部33可以分别通过过孔连接第十三有源部713和第二初始信号线Vinit2，以连接第七晶体管的第一极和第二初始信号端。第四桥接部34可以分别通过过孔连接第十有源部710和第一初始信号线Vinit1，以连接第一晶体管T1的第一极和第一初始信号端。第五桥接部35可以通过过孔连接第十一有源部711，以连接第六晶体管T6的第二极和第七晶体管T7的第二极。第六桥接部36可以通过过孔连接第九有源部79，以连接第四晶体管T4的第一极。如图14、17、18、22所示，第二导电部22还可以包括第一子导电部221，第一子导电部221连接于第三子导电部223，第一子导电部221在衬底基板上的正投影可以沿第一方向X延伸，且位于第一桥接部31在衬底基板上的正投影和所述第一复位信号线Re1在衬底基板上的正投影之间，即第一子导电部221在衬底基板上的正投影在第二方向Y上无限移动所覆盖区域和第一桥接部31在衬底基板上的正投影在第二方向Y上无限移动所覆盖区域至少部分相交，第一子导电部221可以屏蔽第一复位信号线Re1对第一桥接部31的噪音影响，从而提高图1所示像素驱动电路中节点N电压的稳定性。本示例性实施例中，第一子导电部221在衬底基板上的正投影在第二方向Y上无限移动所覆盖区域可以覆盖第一桥接部31在衬底基板上的正投影在第二方向Y上无限移动所覆盖区域。
如图14、19所示，第四导电层可以包括：第一电源线VSS、数据线Da、第七桥接部47。其中，第一电源线VSS用于提供图1所示像素驱动电路中的第一电源端，数据线Da用于提供图1所示像素驱动电路中的数据 信号端。第一电源线VSS在衬底基板上的正投影、数据线Da在衬底基板上的正投影均可以沿第二方向Y延伸。每列像素驱动电路可以对应设置一条第一电源线VSS和一条数据线Da。应该理解的是，在其他示例性实施例中，多列像素驱动电路也可以对应设置一条第一电源线VSS。第一电源线VSS可以通过过孔连接第二桥接部32，以连接第一电源端和电容C的第一电极。数据线Da可以通过过孔连接第六桥接部36，以连接第四晶体管T4的第一极和数据信号端。如图14、19所示，第四导电层还可以包括第四导电部44，第四导电部44连接于第一电源线VSS，第四导电部44在衬底基板上的正投影可以与第一桥接部31在衬底基板上的正投影至少部分交叠，第四导电部44可以屏蔽其他信号线对第一桥接部31的噪音影响。本示例性实施例中，第四导电部44在衬底基板上的正投影可以覆盖第一桥接部31在衬底基板上的正投影。如图14所示，第二电源线VDD在衬底基板上的正投影可以位于数据线Da在衬底基板上的正投影和第一桥接部31在衬底基板上的正投影之间，第一电源线VSS在衬底基板上的正投影可以位于第一桥接部31在衬底基板上的正投影远离第二电源线VDD在衬底基板上的正投影的一侧，本列像素驱动电路中的所述第一电源线VSS在所述衬底基板上的正投影位于相邻列像素驱动电路中所述数据线Da在所述衬底基板上的正投影和本列像素驱动电路中所述第一桥接部31在所述衬底基板上的正投影之间。第二电源线VDD可以屏蔽本列像素驱动电路中数据线Da对本列像素驱动电路中第一桥接部31的噪音影响，第一电源线VSS可以屏蔽相邻列像素驱动电路中数据线Da对本列像素驱动电路中第一桥接部31的噪音影响。第一电源线VSS在衬底基板上的正投影还可以与第六有源部76在衬底基板上的正投影至少部分交叠。本示例性实施例中，第一电源线VSS可以提供低电平电源信号，第一电源线VSS可以提高第六晶体管T6的响应速度。第一电源线VSS还可以通过过孔连接公共电极层。
如图14、17、18、22所示，第二导电部22还可以第二子导电部222，第二子导电部222连接于第一子导电部221远离第三子导电部223的一侧，第二子导电部222在衬底基板上的正投影可以沿第二方向Y延伸，且位于第一桥接部31在衬底基板上的正投影和所述数据线Da在衬底基板上的正投影之间，即第二子导电部222在衬底基板上的正投影在第一方向X上无 限移动所覆盖区域和第一桥接部31在衬底基板上的正投影在第一方向X上无限移动所覆盖区域至少部分相交，第二子导电部222可以屏蔽数据线Da对第一桥接部31的噪音影响。
需要说明的是，如图14、22所示，画于第三导电层背离衬底基板一侧的黑色方块表示第三导电层连接面向衬底基板一侧的其他层级的过孔；画于第四导电层背离衬底基板一侧的黑色方块表示第四导电层连接面向衬底基板一侧的其他层级的过孔。该黑色方块仅表示过孔的位置，不同位置黑色方块所表示的不同过孔可以贯穿于不同绝缘层。
如图23所示，为图14所示显示面板沿虚线AA剖开的部分剖视图。该显示面板还可以包括缓冲层82、第一绝缘层83、第二绝缘层84、第一介电层85、钝化层86、第二介电层87，其中，衬底基板81、缓冲层82、有源层、第一绝缘层83、第一导电层、第二绝缘层84、第二导电层、第一介电层85、第三导电层、钝化层86、第二介电层87、第四导电层依次层叠设置。第一绝缘层83、第二绝缘层84可以氧化硅层，第一介电层85、第二介电层87可以为氮化硅层，钝化层86、缓冲层82的材料可以为氧化硅、氮化硅等。衬底基板81可以包括依次层叠设置的玻璃基板、阻挡层、聚酰亚胺层，阻挡层可以为无机材料。第一导电层、第二导电层的材料可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等。第三导电层、第四导电层的材料可以包括金属材料，例如可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层。
该显示面板还可以包括位于第四导电层和公共电极层之间的像素电极层。如图24、25所示，图24为本公开显示面板另一种示例性实施例中的结构版图，图25为图24中像素电极层的结构版图。像素电极层可以包括多个电极部，电极部可以用于形成发光单元的第一电极，多个所述电极部包括：多个R电极部R、多个G电极部G、多个B电极部B，在连接于同一行像素驱动电路的多个电极部中，R电极部、G电极部、B电极部、G电极部在行方向上依次交替分布；在相邻两列像素驱动电路中，多个所述R电极部和多个所述B电极部连接于同一列像素驱动电路，且连接于同一列像素驱动电路的所述R电极部和B电极部在列方向上依次交替分布，多个 所述G电极部连接于另一列像素驱动电路；连接于相邻像素驱动电路行且连接于同一像素驱动电路列的两个G电极部在所述衬底基板上的正投影在列方向上的最小距离S1小于所述R电极部在所述衬底基板上的正投影在列方向的尺寸S2或者所述B电极部所述衬底基板上的正投影在列方向的尺寸S3。其中，该显示面板还可以包括位于电极层背离衬底基板一侧的像素定义层，R电极部在衬底基板上的正投影和像素定义层上与其对应的开口在衬底基板上的正投影重合，G电极部在衬底基板上的正投影和像素定义层上与其对应的开口在衬底基板上的正投影重合，B电极部在衬底基板上的正投影和像素定义层上与其对应的开口在衬底基板上的正投影重合。各个电极部可以通过过孔连接第七桥接部47，以连接第六晶体管T6的第二极。
如图24、25所述，R电极部R、B电极部B为六边形，G电极部G为五边形，应该理解的是，在其他示例性实施例中，R电极部R、B电极部B、G电极部G的边角还可以为弧形，该设置可以改善显示面板色偏的技术问题。
此外，在其他示例性实施例中，电极部还可以有他结构和分布方式，例如，如图26所示，为本公开显示面板另一种示例性实施例中像素电极层的结构版图。像素电极层可以包括多个电极部：R电极部R、G电极部G、B电极部B，各个电极部可以通过过孔连接第七桥接部47以连接第六晶体管的第二极。在连接于同一行像素驱动电路的多个电极部中，R电极部、G电极部、B电极部、G电极部在行方向上依次交替分布；在相邻两列像素驱动电路中，多个所述R电极部和多个所述B电极部连接于同一列像素驱动电路，且连接于同一列像素驱动电路的所述R电极部和B电极部在列方向上依次交替分布，多个所述G电极部连接于另一列像素驱动电路；连接于相邻像素驱动电路行且连接于同一像素驱动电路列的两个G电极部在所述衬底基板上的正投影在列方向上的最小距离S1大于所述R电极部在所述衬底基板上的正投影在列方向的尺寸S2或者所述B电极部所述衬底基板上的正投影在列方向的尺寸S3。其中，R电极部在衬底基板上的正投影和像素定义层上与其对应的开口在衬底基板上的正投影重合，G电极部在衬底基板上的正投影和像素定义层上与其对应的开口在衬底基板上的正 投影重合，B电极部在衬底基板上的正投影和像素定义层上与其对应的开口在衬底基板上的正投影重合。
需要说明的是，本公开中的附图比例可以作为实际工艺中的参考，但不限于此，例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图。此外，第一、第二等限定词仅用于限定不同的结构名称，其并没有特定顺序的含义。
本示例性实施例还提供一种显示装置，其中，包括上述的显示面板。该显示装置可以为手机、平板电脑、电视等显示装置。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (18)

  1. 一种显示面板，其中，所述显示面板包括沿第一方向和第二方向阵列分布的子像素单元，所述第一方向和所述第二方向相交，所述子像素单元包括像素驱动电路和发光单元，所述像素驱动电路连接所述发光单元的第一电极，所述像素驱动电路包括驱动晶体管和电容，所述电容的第一电极连接第一电源线，所述电容的第二电极连接所述驱动晶体管的栅极，所述显示面板还包括：
    衬底基板；
    第二导电层，位于所述衬底基板的一侧，所述第二导电层包括多个第一导电部，所述第一导电部和所述像素驱动电路对应设置，所述第一导电部用于形成与其对应的所述像素驱动电路中所述电容的第一电极；
    第四导电层，位于所述第二导电层背离所述衬底基板的一侧，所述第四导电层包括多条所述第一电源线，所述第一电源线在所述衬底基板上的正投影沿所述第一方向间隔分布且沿所述第二方向延伸，所述第一导电部通过过孔连接所述第一电源线；
    公共电极层，位于所述第四导电层背离所述衬底基板的一侧，所述公共电极层用于形成所述发光单元的第二电极，所述第一电源线通过过孔连接所述公共电极层。
  2. 根据权利要求1所述的显示面板，其中，在所述第一方向上分布的至少部分所述第一导电部依次连接以形成第一导电线，所述第一导电线连接多条所述第一电源线。
  3. 根据权利要求2所述的显示面板，其中，在所述第一方向上分布的所有所述第一导电部依次连接以形成第一导电线，所述第一导电线连接每一条所述第一电源线。
  4. 根据权利要求2所述的显示面板，其中，在所述第一方向上分布的多个所述第一导电部形成在所述第一方向上间隔分布多条所述第一导电线；
    在所述第一方向和所述第二方向上均相邻的两所述第一导电线在所述第一方向上交错分布，交错分布的两所述第一导电线共同连接至少两条所述第一电源线。
  5. 根据权利要求1所述的显示面板，其中，所述像素驱动电路还包括第六晶体管，所述第六晶体管的第一极连接所述驱动晶体管的第二极，第二极连接所述发光单元的第一电极，所述第六晶体管为P型晶体管，所述第一电源线用于提供低电平电源信号；
    所述显示面板还包括：
    有源层，位于所述衬底基板和所述第二导电层之间，所述有源层包括第六有源部，所述第六有源部用于形成所述第六晶体管的沟道区；
    所述第一电源线在所述衬底基板上的正投影与所述第六有源部在所述衬底基板上的正投影至少部分交叠。
  6. 根据权利要求1所述的显示面板，其中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极；
    所述第二导电层还包括：
    第二导电部，连接一稳定电源端；
    所述显示面板还包括：
    有源层，位于所述衬底基板和所述第二导电层之间，所述有源层包括：第二有源部、第三子有源部，所述第二有源部包括第一子有源部和第二子有源部，所述第三子有源部连接于所述第一子有源部和所述第二子有源部之间，所述第一子有源部用于形成所述第二晶体管的第一沟道区，所述第二子有源部用于形成所述第二晶体管的第二沟道区；
    其中，所述第二导电部在所述衬底基板上的正投影和所述第三子有源部在所述衬底基板上的正投影至少部分交叠。
  7. 根据权利要求6所述的显示面板，其中，所述驱动晶体管的第一极连接第二电源线，所述第二导电部通过过孔连接所述第二电源线；
    所述第二导电层包括多个所述第二导电部，所述第二导电部与所述像素驱动电路对应设置，在所述第一方向上分布的至少部分所述第二导电部依次连接以形成第二导电线；
    所述显示面板还包括多条所述第二电源线，多条所述第二电源线在所述衬底基板上的正投影沿所述第一方向间隔分布且沿所述第二方向延伸，所述第二导电线连接多条所述第二电源线。
  8. 根据权利要求6所述的显示面板，其中，所述像素驱动电路还包括第一晶体管，所述第一晶体管的第一极连接第一初始信号线，第二极连接所述驱动晶体管的栅极；
    所述有源层还包括第一有源部和第三有源部，所述第一有源部用于形成所述第一晶体管的沟道区，所述第三有源部用于形成所述驱动晶体管的沟道区；
    所述显示面板还包括：
    第一导电层，位于所述有源层和所述第二导电层之间，所述第一导电层包括：
    第一复位信号线，在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第一有源部在所述衬底基板上的正投影，所述第一复位信号线的部分结构用于形成所述第一晶体管的栅极；
    栅线，在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第二有源部在所述衬底基板上的正投影，所述栅线的部分结构用于形成所述第二晶体管的栅极；
    第三导电部，所述第三导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第三导电部用于形成所述驱动晶体管的栅极；
    其中，所述第一复位信号线在所述衬底基板上的正投影位于所述栅线在所述衬底基板上的正投影远离所述第三导电部在所述衬底基板上的正投影的一侧，所述第二导电部在所述衬底基板上的正投影位于所述第一复位信号线在所述衬底基板上的正投影和所述栅线在所述衬底基板上的正投影之间。
  9. 根据权利要求8所述的显示面板，其中，所述显示面板还包括：
    第三导电层，位于所述第二导电层和所述第四导电层之间，所述第三导电层包括第一桥接部，所述第一桥接部通过过孔连接所述第三导电部且连接所述第二晶体管的第一极；
    所述第二导电部包括：
    第一子导电部，所述第一子导电部在所述衬底基板上的正投影沿所述第一方向延伸，且位于所述第一桥接部在所述衬底基板上的正投影和所述 第一复位信号线在所述衬底基板上的正投影之间。
  10. 根据权利要求9所述的显示面板，其中，所述显示面板还包括：
    数据线，在所述衬底基板上的正投影沿所述第二方向延伸；
    所述第二导电部还包括：
    第二子导电部，连接于所述第一子导电部，所述第二子导电部在所述衬底基板上的正投影沿所述第二方向延伸，且位于所述第一桥接部在所述衬底基板上的正投影和所述数据线在所述衬底基板上的正投影之间。
  11. 根据权利要求1所述的显示面板，其中，所述驱动晶体管连接第二电源线，所述像素驱动电路还包括第二晶体管，第四晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，所述第二晶体管的第二极连接所述驱动晶体管的第二极，所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极；
    所述显示面板还包括：
    有源层，位于所述衬底基板和所述第二导电层之间，所述有源层包括第三有源部，所述第三有源部用于形成所述驱动晶体管的沟道区；
    第一导电层，位于所述有源层和所述第二导电层之间，所述第一导电层包括第三导电部，所述第三导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第三导电部用于形成所述驱动晶体管的栅极；
    第三导电层，位于所述第二导电层和所述第四导电层之间，所述第三导电层包括第一桥接部，所述第一桥接部通过过孔连接所述第三导电部且连接所述第二晶体管的第一极；
    所述第二方向为列方向，在同一列像素驱动电路中，所述第二电源线在所述衬底基板上的正投影沿所述第二方向延伸，所述数据线在所述衬底基板上的正投影沿所述第二方向延伸，且所述第二电源线在所述衬底基板上的正投影位于所述数据线在所述衬底基板上的正投影和所述第一桥接部在所述衬底基板上的正投影之间，所述第一电源线在所述衬底基板上的正投影位于所述第一桥接部在所述衬底基板上的正投影远离所述第二电源线在所述衬底基板上的正投影的一侧；
    在相邻列像素驱动电路中，本列像素驱动电路中的所述第一电源线在 所述衬底基板上的正投影位于相邻列像素驱动电路中所述数据线在所述衬底基板上的正投影和本列像素驱动电路中所述第一桥接部在所述衬底基板上的正投影之间。
  12. 根据权利要求1所述的显示面板，其中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极；
    所述显示面板还包括：
    有源层，位于所述衬底基板和所述第二导电层之间，所述有源层包括第三有源部，所述第三有源部用于形成所述驱动晶体管的沟道区；
    第一导电层，位于所述有源层和所述第二导电层之间，所述第一导电层包括第三导电部，所述第三导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第三导电部用于形成所述驱动晶体管的栅极；
    第三导电层，位于所述第二导电层和所述第四导电层之间，所述第三导电层包括第一桥接部，所述第一桥接部通过过孔连接所述第三导电部且连接所述第二晶体管的第一极；
    所述第四导电层还包括：
    第四导电部，连接所述第一电源线，且所述第四导电部在所述衬底基板上的正投影与所述第一桥接部在所述衬底基板上的正投影至少部分交叠。
  13. 根据权利要求1所述的显示面板，其中，所述像素驱动电路还包括第一晶体管、第七晶体管，所述第一晶体管的第一极连接第一初始信号线，第二极连接所述驱动晶体管的栅极，所述第七晶体管的第一极连接第二初始信号线，第二极连接所述发光单元的第一极；
    所述显示面板还包括：
    有源层，位于所述衬底基板和所述第二导电层之间，所述有源层包括第一有源部、第七有源部，所述第一有源部用于形成所述第一晶体管的沟道区，所述第七有源部用于形成所述第七晶体管的沟道区；
    第一导电层，位于所述有源层和所述第二导电层之间，所述第一导电层包括：
    第一复位信号线，在所述衬底基板上的正投影沿所述第一方向延伸，且覆盖所述第一有源部在所述衬底基板上的正投影，所述第一复位信号线的部分结构用于形成所述第一晶体管的栅极；
    第二复位信号线，在所述衬底基板上的正投影沿所述第一方向延伸，且覆盖所述第七有源部在所述衬底基板上的正投影，所述第二复位信号线的部分结构用于形成所述第七晶体管的栅极；
    其中，所述第一方向为行方向，在相邻行像素驱动电路中，上一行像素驱动电路中的所述第二复位信号线共用为本行像素驱动电路中的所述第一复位信号线。
  14. 根据权利要求13所述的显示面板，其中，所述有源层还包括；
    第三有源部，所述第三有源部用于形成所述驱动晶体管的沟道区；
    所述第一导电层还包括：
    第三导电部，所述第三导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第三导电部用于形成所述驱动晶体管的栅极；
    所述第二导电层还包括：
    所述第一初始信号线，在所述衬底基板上的正投影沿所述第一方向延伸；
    所述第二初始信号线，在所述衬底基板上的正投影沿所述第一方向延伸；
    其中，在同一行像素驱动电路中，所述第三导电部在所述衬底基板上的正投影位于所述第一初始信号线在所述衬底基板上的正投影和所述第二初始信号线在所述衬底基板上的正投影之间，且所述第一初始信号线在所述衬底基板上的正投影位于所述第一复位信号线在所述衬底基板上的正投影远离所述第三导电部在所述衬底基板上的正投影的一侧；
    在相邻行像素驱动电路中，上一行像素驱动电路中的所述第二初始信号线在所述衬底基板上的正投影位于本行像素驱动电路中所述第一初始信号线在所述衬底基板上的正投影和本行像素驱动电路中所述第一复位信号线在所述衬底基板上的正投影之间。
  15. 根据权利要求14所述的显示面板，其中，所述第一有源部包括 第四子有源部和第五子有源部，所述有源层还包括连接于所述第四子有源部和所述第五子有源部之间的第六子有源部；
    上一行像素驱动电路中所述第二初始信号线在所述衬底基板上的正投影与本行像素驱动电路中所述第六子有源部在所述衬底基板上的正投影至少部分交叠。
  16. 根据权利要求1所述的显示面板，其中，所述像素驱动电路还包括第一晶体管、第二晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管；
    所述第一晶体管的第一极连接第一初始信号线，第二极连接所述驱动晶体管栅极；
    所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极；
    所述第四晶体管的第一极连接数据线，第二极连接所述驱动晶体管的第一极；
    所述第五晶体管的第一极连接第二电源线，第二极连接所述驱动晶体管的第一极；
    所述第六晶体管的第一极连接所述驱动晶体管的第二极，第二极连接所述发光单元的第一电极；
    所述第七晶体管的第一极连接第二初始信号线，第二极连接所述发光单元的第一电极；
    所述第一晶体管、第二晶体管、驱动晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管均为P型晶体管。
  17. 根据权利要求16所述的显示面板，其中，所述显示面板还包括：
    有源层，位于所述衬底基板和所述第二导电层之间，所述有源层包括：第三有源部、第四有源部、第五有源部、第六有源部、第七有源部，所述第三有源部用于形成所述驱动晶体管的沟道区，所述第四有源部用于形成所述第四晶体管的沟道区，所述第五有源部用于形成所述第五晶体管的沟道区，所述第六有源部用于形成所述第六晶体管的沟道区，所述第七有源部用于形成所述第七晶体管的沟道区；
    第一导电层，位于所述有源层和所述第二导电层之间，所述第一导电 层包括：
    栅线，在所述衬底基板上的正投影沿所述第一方向延伸，且覆盖所述第四有源部在所述衬底基板上的正投影，所述栅线的部分结构用于形成所述第四晶体管的栅极；
    使能信号线，在所述衬底基板上的正投影沿所述第一方向延伸，且覆盖所述第五有源部在所述衬底基板上的正投影和所述第六有源部在所述衬底基板上的正投影，所述使能信号线的部分结构用于形成所述第五晶体管的栅极，且所述使能信号线的另外部分结构用于形成所述第六晶体管的栅极；
    第二复位信号线，在所述衬底基板上的正投影沿所述第一方向延伸，且覆盖所述第七有源部在所述衬底基板上的正投影，所述第二复位信号线的部分结构用于形成所述第七晶体管的栅极；
    第三导电部，所述第三导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第三导电部用于形成所述驱动晶体管的栅极；
    其中，在同一行像素驱动电路中，所述使能信号线在所述衬底基板上的正投影位于所述第三导电部在所述衬底基板上的正投影和所述第二复位信号线在所述衬底基板上的正投影之间。
  18. 一种显示装置，其中，包括权利要求1-17任一项所述的显示面板。
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