WO2022087852A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2022087852A1
WO2022087852A1 PCT/CN2020/124165 CN2020124165W WO2022087852A1 WO 2022087852 A1 WO2022087852 A1 WO 2022087852A1 CN 2020124165 W CN2020124165 W CN 2020124165W WO 2022087852 A1 WO2022087852 A1 WO 2022087852A1
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Prior art keywords
layer
base substrate
conductive
transistor
conductive portion
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PCT/CN2020/124165
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English (en)
French (fr)
Inventor
陈义鹏
石领
李文强
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/438,445 priority Critical patent/US20220310732A1/en
Priority to PCT/CN2020/124165 priority patent/WO2022087852A1/zh
Priority to CN202080002465.4A priority patent/CN115004374A/zh
Publication of WO2022087852A1 publication Critical patent/WO2022087852A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate, a manufacturing method thereof, and a display device.
  • the pixel driving circuit can be formed by using a low temperature polycrystalline oxide (LTPO) technology.
  • LTPO low temperature polycrystalline oxide
  • a pixel driving circuit is formed in a combined manner.
  • the LTPO technology usually forms an electrode of the capacitor in the pixel driving circuit through the conductive portion located in the source and drain layers.
  • the conductive part is connected to the gate of the driving transistor through the via hole, so as to realize the connection between the capacitor and the gate of the driving transistor.
  • the conductive portion has a large area, so that the gate of the driving transistor connected to the conductive portion is easily affected by noise.
  • an array substrate includes a pixel driving circuit, the pixel driving circuit includes a P-type driving transistor, an N-type first transistor, and a capacitor, and a first electrode of the first transistor The gate of the driving transistor is connected, and the first electrode of the capacitor is connected to the gate of the driving transistor, wherein the array substrate further comprises: a base substrate, a first conductive layer, a first dielectric layer, a first a buffer layer and a second conductive layer.
  • a first conductive layer is stacked on one side of the base substrate, the first conductive layer includes a first conductive portion, and the first conductive portion is configured as the gate of the driving transistor and the first conductive portion of the capacitor.
  • the first dielectric layer is stacked on the side of the first conductive layer away from the base substrate;
  • the first buffer layer is stacked on the side of the first dielectric layer away from the base substrate , the first buffer layer is provided with a slot, and the orthographic projection of the slot on the base substrate at least partially overlaps with the orthographic projection of the first conductive portion on the base substrate;
  • the second conductive layer The first buffer layer is stacked on the side of the first buffer layer away from the base substrate, the second conductive layer includes a second conductive part and a third conductive part, and the second conductive part is configured as the first transistor the gate;
  • the third conductive part is located at the bottom of the slot, and the orthographic projection of the third conductive part on the base substrate and the orthographic projection of the first conductive part on the base substrate at least partially coincide to form the second electrode of the capacitor.
  • the slot extends to a surface of the first dielectric layer, and the third conductive portion is located on a side of the first dielectric layer away from the base substrate.
  • the array substrate further includes: a third conductive layer stacked on a side of the second conductive layer away from the base substrate, including a fourth conductive layer.
  • a conductive part the fourth conductive part is electrically connected to the first conductive part through a first via hole passing through the third conductive part, and is insulated from the second conductive part; wherein, the fourth conductive part
  • the orthographic projection of the base substrate is located on the orthographic projection of the first conductive portion on the base substrate, and the orthographic projection area of the fourth conductive portion on the base substrate is smaller than that of the first conductive portion The orthographic projection area of the part on the base substrate.
  • the ratio of the orthographic projection area of the fourth conductive portion on the base substrate to the orthographic projection area of the first via hole on the base substrate is 1-1.5.
  • the ratio of the orthographic projection area of the fourth conductive portion on the base substrate to the orthographic projection area of the first conductive portion on the base substrate is 8%-15 %.
  • a second via hole is formed on the third conductive portion, and the second via hole extends through the first dielectric layer to a surface of the first conductive portion, so
  • the array substrate further includes a second dielectric layer, the second dielectric layer is stacked and disposed between the second conductive layer and the third conductive layer, and the first pass through is formed on the second dielectric layer.
  • a hole, the first via hole extends through the third conductive part to the surface of the first conductive part; and the orthographic projection of the first via hole on the base substrate is located at the second via hole within the orthographic projection of the base substrate.
  • the third conductive layer further includes a power supply line for providing a power supply voltage
  • the array substrate further includes a fourth conductive layer
  • the fourth conductive layer is stacked on the third conductive layer.
  • the side of the layer away from the base substrate, the fourth conductive layer includes a fifth conductive part connected to the power line, and the fifth conductive part covers the first conductive part in the orthographic projection of the base substrate The orthographic projection of the conductive portion on the base substrate.
  • the second conductive layer further includes a sixth conductive portion connected to the third conductive portion, and the sixth conductive portion is connected to the power line through a via hole.
  • the first buffer layer includes a first buffer layer and a first gate insulating layer.
  • the first buffer layer is stacked on the side of the first dielectric layer away from the base substrate; the first gate insulating layer is stacked on the side of the first buffer layer away from the base substrate.
  • the array substrate further includes: a first active layer, a second active layer, a second gate insulating layer, a barrier layer, a second buffer layer, a second dielectric layer, A passivation layer and a first gate insulating layer.
  • the barrier layer is stacked on one side of the base substrate; the second buffer layer is stacked on the side of the barrier layer away from the base substrate; the first active layer is stacked on the second buffer layer away from the On one side of the base substrate, the first active layer includes a first active part, and the first active part is configured as a channel region of the driving transistor; the second gate insulating layer is stacked on the the side of the first active layer away from the base substrate, wherein the first conductive layer is stacked on the side of the second gate insulating layer away from the base substrate; the second active layer The first buffer layer is stacked on the side of the first buffer layer away from the base substrate, and includes a second active part, the second active part is configured as a channel region of the first transistor; a first gate The insulating layer is stacked on the side of the second active layer away from the base substrate, wherein the second conductive layer is stacked on the side of the first gate insulating layer away from the base substrate; the first Two dielectric layers are stacked on the side of the second
  • the array substrate includes a non-display area, a strip-shaped groove located in the non-display area is formed on the array substrate, and the strip-shaped groove penetrates through the passivation layer, the second dielectric layer, and the passivation layer.
  • the electrical layer, the first buffer layer, the first dielectric layer, the second buffer layer, and the barrier layer extend to the surface of the base substrate;
  • the array substrate further includes a first flat layer, and the first flat layer is stacked on the a side of the passivation layer away from the base substrate, and fills the strip-shaped groove; wherein, the bendability of the material of the first flat layer is stronger than that of the passivation layer, the second dielectric layer, The bendability of the materials of the first buffer layer, the first dielectric layer, the second buffer layer and the barrier layer.
  • the thickness of the first dielectric layer in the stacking direction is 1200-1400 angstroms.
  • the array substrate further includes: an enable signal line, an initial signal line, an anode layer, a first reset signal line, a second reset signal line, a power supply line, a first gate line, a first Two gate lines and data lines, the second pole of the first transistor is connected to the second pole of the driving transistor, the gate is connected to the second gate line, and the pixel driving circuit further includes: a second transistor, a third transistor, fourth transistor, fifth transistor, sixth transistor.
  • the first electrode of the second transistor is connected to the data line, the second electrode is connected to the first electrode of the driving transistor, and the gate is connected to the first gate line; the first electrode of the third transistor is connected to the gate of the driving transistor pole, the second pole is connected to the initial signal line, the gate is connected to the second reset signal line; the first pole of the fourth transistor is connected to the power supply line, the second pole is connected to the first pole of the driving transistor, and the gate
  • the first pole of the fifth transistor is connected to the second pole of the driving transistor, the second pole is connected to the anode layer, and the gate is connected to the enable signal line; One pole is connected to the second pole of the fifth transistor, the second pole is connected to the initial signal line, and the gate is connected to the first reset signal line.
  • the driving transistor, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor are P-type low-temperature polysilicon transistors; the first transistor and the third transistor are N-type metal transistors oxide transistor.
  • a method for fabricating an array substrate includes a pixel driving circuit, the pixel driving circuit includes a P-type driving transistor, an N-type first transistor, and a capacitor, and the first transistor has a third One pole is connected to the gate of the driving transistor, and the first electrode of the capacitor is connected to the gate of the driving transistor.
  • the manufacturing method of the array substrate includes:
  • a first conductive layer is formed on one side of the base substrate, the first conductive layer includes a first conductive part, and the first conductive part is configured as the gate of the driving transistor and the first electrode of the capacitor ;
  • a first buffer layer is formed on the side of the first dielectric layer away from the base substrate, the first buffer layer is provided with a slot, and the slot is on the orthographic projection of the base substrate and the the orthographic projection of the first conductive portion on the base substrate at least partially overlaps;
  • a second conductive layer is formed on the side of the first buffer layer away from the first conductive layer, and the second conductive layer includes:
  • the second conductive portion is configured as a gate of the first transistor
  • the third conductive part is located at the bottom of the slot, and the orthographic projection of the third conductive part on the base substrate is the same as the orthographic projection of the first conductive part on the base substrate
  • the projections are at least partially coincident to form the second electrode of the capacitor.
  • a first buffer layer is formed on the side of the first dielectric layer away from the first conductive layer, including:
  • the etched first buffer material layer forms the first buffer layer.
  • the slot extends to a surface of the first dielectric layer, and the third conductive portion is located on a side of the first dielectric layer away from the base substrate. .
  • the method for fabricating the base substrate further includes:
  • a third conductive layer is formed on the side of the second conductive layer facing away from the base substrate, the third conductive layer includes a fourth conductive portion, and the fourth conductive portion passes through a pass through the third conductive portion.
  • the hole is electrically connected to the first conductive part;
  • the orthographic projection of the fourth conductive portion on the base substrate is located on the orthographic projection of the first conductive portion on the base substrate, and the fourth conductive portion is on the normal projection of the base substrate
  • the projected area is smaller than the orthographic projected area of the first conductive portion on the base substrate.
  • the method before the third conductive layer is formed on the side of the second conductive layer facing away from the base substrate, the method further includes:
  • a second dielectric layer is formed on the side of the second conductive layer away from the base substrate, and the second dielectric layer fills the second via hole;
  • a first via hole is formed on the second dielectric layer, the first via hole extends through the third conductive part to the surface of the first conductive part; and the first via hole is in the lining
  • the orthographic projection of the base substrate is located within the orthographic projection of the second via hole in the base substrate;
  • the fourth conductive portion fills the first via hole.
  • a display device which includes the above-mentioned array substrate.
  • FIG. 1 is a schematic diagram of a circuit structure of a pixel driving circuit of the present disclosure
  • FIG. 2 is a schematic structural diagram of an array substrate in the related art
  • FIG. 3 is a schematic structural diagram of an exemplary embodiment of the disclosed array substrate
  • FIG. 4a is a schematic structural diagram of another exemplary embodiment of the disclosed array substrate.
  • Figure 4b is a partial top view of Figure 3;
  • 4c is a partial top view of another exemplary embodiment of the disclosed array substrate.
  • 4d is a partial top view of another exemplary embodiment of the disclosed array substrate
  • FIG. 5 is a schematic structural diagram of another exemplary embodiment of the disclosed array substrate.
  • FIG. 6 is a schematic structural diagram of another exemplary embodiment of the disclosed array substrate.
  • FIG. 7 is a schematic structural diagram of another exemplary embodiment of the disclosed array substrate.
  • 8-14 are process flow diagrams of an exemplary embodiment of a method for fabricating an array substrate of the present disclosure.
  • 16 is a structural layout of the first conductive layer
  • 17 is a structural layout of the second active layer
  • 18 is a combined layout of the first active layer, the first conductive layer, and the second active layer;
  • 20 is a combined layout of the first active layer, the first conductive layer, the second active layer, and the second conductive layer;
  • 21 is a structural layout of the third conductive layer
  • 22 is a combined layout of the first active layer, the first conductive layer, the second active layer, the second conductive layer, and the third conductive layer;
  • 24 is a combined layout of the first active layer, the first conductive layer, the second active layer, the second conductive layer, the third conductive layer, and the fourth conductive layer;
  • Figure 25 is a structural layout of the anode layer
  • 26 is a combined layout of the first active layer, the first conductive layer, the second active layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the anode layer;
  • FIG. 27 is a timing diagram of each node in a driving method of the pixel driving circuit of FIG. 1;
  • FIG. 28 is a partial layout structure of the first conductive layer in FIG. 9;
  • FIG. 29 is a partial layout structure of the third conductive layer in FIG. 21;
  • Figure 30 is a partial layout structure in Figure 22;
  • FIG. 31 is a partial layout structure of FIG. 24 .
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the pixel driving circuit may include: a driving transistor DT, a second transistor T2, a first transistor T1, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a capacitor C.
  • the first pole of the second transistor T2 is connected to the data signal terminal Da, the second pole is connected to the first pole of the driving transistor DT, the gate is connected to the first gate driving signal terminal G1; the first pole of the fourth transistor T4 is connected to the first pole of the driving transistor DT.
  • a power supply terminal VDD the second pole is connected to the first pole of the driving transistor DT, and the gate is connected to the enable signal terminal EM; the gate of the driving transistor DT is connected to the node N, and the second pole is connected to the first pole of the fifth transistor T5;
  • the first pole of a transistor T1 is connected to the node N, the second pole is connected to the second pole of the driving transistor DT, the gate is connected to the second gate driving signal terminal G2;
  • the second pole of the fifth transistor T5 is connected to the first pole of the sixth transistor T6
  • One pole, the gate is connected to the enable signal terminal EM, the second pole of the sixth transistor T6 is connected to the initial signal terminal Vinit, the gate is connected to the first reset signal terminal Re1;
  • the first pole of the third transistor T3 is connected to the node N, the second The pole is connected to the initial signal terminal Vinit, the gate is connected to the second reset signal terminal Re2, and the capacitor C is connected between the first power terminal VDD and the node N.
  • the pixel driving circuit can be connected to a light-emitting unit OLED for driving the light-emitting unit OLED to emit light, and the light-emitting unit OLED is connected between the second pole of the fifth transistor T5 and the second power terminal VSS.
  • the first transistor T1 and the third transistor T3 may be N-type metal oxide transistors, and the N-type metal oxide transistor has a smaller leakage current, so that the node N can be prevented from passing through the first transistor T1 and the third transistor T3 in the light-emitting stage Leakage.
  • the driving transistor DT, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be low-temperature polysilicon transistors, and the low-temperature polysilicon transistors have higher carrier mobility, thereby facilitating the realization of A display device with high resolution, high response speed, high pixel density, and high aperture ratio.
  • the array substrate may include the pixel driving circuit shown in FIG. 1 .
  • the array substrate may include a base substrate 01, a barrier layer 02 on one side of the base substrate 01, a second buffer layer 03 on the side of the barrier layer away from the base substrate 01, and a second buffer layer 03 on the side away from the substrate
  • the first active layer (including the first active portion 04) on the side of the substrate 01, the first gate insulating layer 05 on the side of the first active layer away from the base substrate, and the backing liner on the first gate insulating layer
  • the first gate layer including the first gate portion 06) on the side of the base substrate, the first dielectric layer 07 on the side of the first gate layer away from the base substrate, and the first dielectric layer 07 on the side away from the substrate
  • the first buffer layer 08 on the side of the substrate 01, the second active layer (including the second active portion 09) on the side of the first buffer layer 08 away from the base substrate 01, and the second active
  • the first gate part 06 may be configured as the gate of the driving transistor, and the second gate part 0112 may be configured as the gate of the first transistor T1 or the third transistor T3.
  • the first conductive portion 013 is connected to the first gate portion 06 through a via hole.
  • the distance between the first source-drain layer and the second source-drain layer is small, so that the second conductive portion 015 can form the second electrode of the capacitor C, and at the same time, the second conductive portion 015 can cover the first conductive portion 013 to shield the noise influence of other signals on the first conductive part 013 .
  • the first conductive portion 013 needs to form the electrode of the capacitor, the first conductive portion 013 needs to be designed to have a larger area, so that in a limited plane space, the second conductive portion 015 is not easy to completely cover the first conductive portion 013, and further As a result, the first conductive portion 013 is easily disturbed by external noise.
  • the larger area of the first conductive portion 013 is also likely to form a larger parasitic capacitance with other structures. Under the coupling effect of the parasitic capacitance, the gate of the driving transistor is more susceptible to external noise interference.
  • the present exemplary embodiment provides an array substrate, where the array substrate includes a pixel driving circuit, and the pixel driving circuit may be as shown in FIG. 1 .
  • FIG. 3 it is a schematic structural diagram of an exemplary embodiment of an array substrate of the present disclosure.
  • the array substrate may include: a base substrate 1, a first conductive layer, a first dielectric layer 43, a first buffer layer 41, and a second conductive layer.
  • a first conductive layer is stacked on one side of the base substrate 1, and the first conductive layer may include a first conductive portion 13, and the first conductive portion 13 may be configured as the gate and the gate of the driving transistor.
  • the first electrode of the capacitor C; the first dielectric layer 43 can be stacked on the side of the first conductive layer away from the base substrate 1; the first buffer layer 41 can be stacked on the first dielectric layer.
  • the first buffer layer 41 On the side of the electrical layer 43 facing away from the base substrate 1 , the first buffer layer 41 is provided with a slot 411 , and the slot 411 is in the orthographic projection of the base substrate and the first conductive portion 13 .
  • the orthographic projections of the base substrate at least partially overlap; the second conductive layer is stacked on the side of the first buffer layer 41 away from the base substrate 1 , and the second conductive layer may include a second conductive portion 55 and a third conductive portion 721, the second conductive portion 55 is configured as the gate of the first transistor; the third conductive portion 721 is located at the bottom of the slot 411, and the third conductive portion
  • the orthographic projection of 721 on the base substrate 1 at least partially overlaps with the orthographic projection of the first conductive portion 13 on the base substrate, so as to form the second electrode of the capacitor.
  • the second conductive portion 55 may be located outside the slot 411 , that is, the orthographic projection of the second conductive portion 55 on the base substrate does not intersect with the orthographic projection of the slot 411 on the base substrate.
  • different structural portions in the same structural film layer can be formed through a single patterning process.
  • the A layer any structural film layer
  • the layer can include not only the part directly above the B layer, but also the part filled in the hollow area of the B layer, that is, the A layer can include the X part directly above the B layer and the X part formed by one patterning process or one deposition process.
  • the orthographic projection of the X part on the base substrate coincides with the orthographic projection of the B layer on the base substrate.
  • the first dielectric layer 43 includes not only the portion directly above the first conductive portion 13 but also other portions formed by the same deposition process; the second conductive layer may include not only the first buffer layer 41
  • the second conductive portion 55 directly above may further include a third conductive portion 721 formed with the second conductive portion 55 through one patterning process.
  • a slot 411 is provided on the first buffer layer 41 , and a third conductive portion 721 is provided at the bottom of the slot 411 .
  • the arrangement of the slot 411 reduces the distance between the third conductive portion 721 and the first conductive portion 13 , so that the third conductive portion 721 and the first conductive portion 13 can form two electrodes of the capacitor C.
  • the present exemplary embodiment does not need to design the first conductive portion 013 with a large area in the related art as a capacitor electrode, thereby reducing the noise impact of external signals on the gate of the driving transistor; on the other hand, the present exemplary embodiment
  • the provided array substrate may not be provided with the second source and drain layers in the related art, thereby simplifying the structure of the array substrate.
  • the pixel driving circuit may also have other structures, and the array substrate including the LTPO pixel driving circuit may adopt the above structure to form the capacitance of the corresponding pixel driving circuit.
  • the slot 411 may extend to the surface of the first dielectric layer 43 , that is, the bottom of the slot 411 may be formed through the first dielectric layer 43 , and the The third conductive portion 721 may be located on the side of the first dielectric layer 43 away from the base substrate 1 .
  • the first dielectric layer 43 located between the first conductive portion 13 and the third conductive portion 721 may serve as a dielectric layer of the parallel plate capacitor structure.
  • the slot 411 may also extend to other positions, for example, as shown in FIG. 4a , which is a schematic structural diagram of another exemplary embodiment of the array substrate of the present disclosure.
  • the slot 411 may extend into the first buffer layer 41 , that is, the bottom of the slot 411 is formed by part of the first buffer layer 41 .
  • FIG. 4 b which is a partial top view of FIG. 3
  • the orthographic projection area of the third conductive portion 721 on the base substrate is smaller than the orthographic projection area of the groove bottom of the slot 411 on the base substrate, and the third conductive portion 721 is located in the slot 411 bottom.
  • the orthographic projection area of the third conductive portion 721 on the base substrate may also be greater than or equal to the orthographic projection area of the bottom of the slot 411 on the base substrate. As shown in FIG.
  • FIG. 4c which is a partial top view of another exemplary embodiment of the array substrate of the present disclosure, wherein the orthographic projection area of the third conductive portion 721 on the base substrate is larger than the orthographic projection of the groove bottom of the slot 411 on the base substrate. area.
  • FIG. 4d which is a partial top view of another exemplary embodiment of an array substrate of the present disclosure, wherein the orthographic projection area of the third conductive portion 721 on the base substrate is equal to the orthographic projection of the bottom of the slot 411 on the base substrate. area.
  • FIG. 5 it is a schematic structural diagram of another exemplary embodiment of the array substrate of the present disclosure.
  • the array substrate may further include: a third conductive layer, the third conductive layer may be stacked on the side of the second conductive layer away from the base substrate 1, and the third conductive layer may include a fourth conductive layer.
  • the conductive portion 24 , the fourth conductive portion 24 can be electrically connected to the first conductive portion 13 through the first via hole 81 penetrating the third conductive portion 721 , and is insulated from the third conductive portion 721 .
  • the orthographic projection of the fourth conductive portion 24 on the base substrate 1 may be located on the orthographic projection of the first conductive portion 13 on the base substrate 1, and the fourth conductive portion 24 is located at the The orthographic projection area of the base substrate 1 may be smaller than the orthographic projection area of the first conductive portion 13 on the base substrate.
  • the fourth conductive part 24 is set to a smaller area.
  • this setting can reduce the parasitic capacitance between the fourth conductive part 24 and other conductive structures (such as data lines, anode layers, etc.), thereby The noise impact of other structures on the gate of the driving transistor can be reduced; on the other hand, this arrangement can facilitate the shielding of the fourth conductive portion 24 by the shielding layer, so as to further reduce the noise impact of other structures on the gate of the driving transistor.
  • the ratio of the orthographic projection area of the fourth conductive portion 24 on the base substrate 1 to the orthographic projection area of the first conductive portion 13 on the base substrate may be 4%-25%.
  • the ratio of the orthographic projection area of the fourth conductive portion 24 on the base substrate 1 to the orthographic projection area of the first conductive portion 13 on the base substrate may be 4%, 8%, 10%, Any of 12%, 15%, 20%, 25%.
  • the ratio of the orthographic projection area of the fourth conductive portion 24 on the base substrate 1 to the orthographic projection area of the first via hole 81 on the base substrate may be 1-2.5
  • the ratio of the orthographic projection area of the fourth conductive portion 24 on the base substrate 1 to the orthographic projection area of the first via hole 81 on the base substrate may be 1, 1.2, 1.3, 1.5 , 2.0, 2.3, 2.5, etc.
  • the orthographic projection area of the fourth conductive portion 24 on the base substrate 1 may also be slightly smaller than that of the first via 81 on the substrate Orthographic projected area of the base substrate.
  • a second via hole 82 may be formed on the third conductive portion 721 , and the second via hole 82 may extend through the first dielectric layer 43 to all the On the upper surface of the first conductive portion 13, the array substrate may further include a second dielectric layer 42, and the second dielectric layer 42 may be stacked between the second conductive layer and the third conductive layer, and fill the second via hole 2 .
  • the first via hole 81 may be formed on the second dielectric layer 42 , the first via hole 81 may extend through the third conductive portion 721 to the upper surface of the first conductive portion 13 , and the The orthographic projection of the first via hole 81 on the base substrate 1 is located within the orthographic projection of the second via hole 82 on the base substrate.
  • the fourth conductive portion 24 can be electrically connected to the first conductive portion 13 , and at the same time, the fourth conductive portion 24 can be insulated from the third conductive portion 721 .
  • the orthographic projection of the first via hole 81 on the base substrate 1 is located within the orthographic projection of the second via hole 82 on the base substrate
  • the first via The orthographic projection 81 of a via hole on the base substrate 1 is located on the orthographic projection of the second via hole 82 on the base substrate, and the first via hole is at the edge of 81 the orthographic projection of the base substrate 1
  • the third conductive layer may further include a power supply line 26 for supplying a power supply voltage
  • the array substrate may further include a passivation layer 49 , a first flat layer 47 , the fourth conductive layer.
  • the passivation layer 49 can be stacked on the side of the third conductive layer away from the base substrate 1, the first flat layer 47 can be stacked on the side of the passivation layer 49 away from the base substrate 1, and the fourth conductive layer
  • the layers may be stacked on the side of the first flat layer 47 away from the base substrate 1 , and the fourth conductive layer may include a fifth conductive portion 35 connected to the power line 26 , the fifth conductive portion 35
  • the orthographic projection on the base substrate may cover the orthographic projection of the first conductive portion on the base substrate.
  • the power line 26 can be used to provide the first power supply terminal VDD in FIG.
  • the fifth conductive portion 35 is connected to a stable voltage, and the orthographic projection of the fifth conductive portion 35 on the base substrate can cover all the The orthographic projection of the first conductive portion 13 on the base substrate, so that the fifth conductive portion 35 can serve as a shielding layer to shield the noise influence of other signals on the first conductive portion 13 .
  • the second conductive layer may further include a sixth conductive portion 722 connected to the third conductive portion 721 , and the sixth conductive portion 722 may be connected to the sixth conductive portion 722 through a via hole.
  • the power supply line 26 is connected, so that the second electrode of the capacitor is connected to the first power supply terminal VDD.
  • FIG. 5 is a cross-sectional view along a bending line on the layout structure of the array substrate.
  • the layout structure of the array substrate will be described in detail below.
  • FIG. 6 it is a schematic structural diagram of another exemplary embodiment of the array substrate of the present disclosure.
  • the array substrate may further include: a barrier layer 48 , a second buffer layer 44 , a first active layer, a second gate insulating layer 45 , a second active layer, and the first gate insulating layer 18 .
  • the two active layers, the first gate insulating layer 18 , the second conductive layer, the second dielectric layer 42 , the third conductive layer, the passivation layer 49 , the first flat layer 47 , and the fourth conductive layer are sequentially stacked.
  • the first active layer may include a first active part 53, and the first active part 53 may be configured as a channel region of the driving transistor DT.
  • the second active layer may include a second active part 62, and the second active part 62 may be configured as a channel region of the first transistor T1.
  • FIG. 7 it is a schematic structural diagram of another exemplary embodiment of the array substrate of the present disclosure.
  • the array substrate may include a non-display area 403 , a strip-shaped groove 121 located in the non-display area 403 is formed on the array substrate, and the strip-shaped groove 121 may penetrate the passivation layer 49 and the second dielectric layer 42 .
  • the first buffer layer 41 , the first dielectric layer 43 , the second gate insulating layer 45 , the second buffer layer 44 , and the barrier layer 48 extend to the surface of the base substrate 1 .
  • the first flat layer 47 can fill the strip grooves 121 .
  • the bendability of the material of the first flat layer 47 may be stronger than that of the passivation layer 49 , the second dielectric layer 42 , the first buffer layer 41 , the first dielectric layer 43 , and the second gate insulating layer 45 , the bendability of the materials of the second buffer layer 44 and the barrier layer 48 .
  • the first flat layer 47 can be made of organic materials
  • the barrier layer 48 can be made of inorganic materials.
  • the position of the strip groove 121 can be used as a bending area to bend the chip connected to the array substrate to the back of the array substrate.
  • the fourth conductive layer may further include signal lines 38 , and the signal lines 38 may be located in the non-display area 403 .
  • the array substrate may further include a second flat layer 19 , an anode layer 20 , and a pixel defining layer 401 , and the second flat layer 19 may be stacked on the fourth conductive layer away from the One side of the base substrate 1 ; the anode layer 20 can be stacked on the side of the second flat layer 19 away from the base substrate 1 ; the pixel defining layer 401 can be stacked on the side of the anode layer away from the base substrate 1 .
  • the anode layer 20 may be configured as the anode of the light emitting cell in FIG. 1; the pixel defining layer 401 may form the pixel opening for depositing the light emitting cell.
  • a support column 402 may also be provided, and the support column 402 may be used to support the mask.
  • the base substrate may include a first polyimide (PI) layer, a first silicon oxide (SiO) layer, an amorphous silicon layer, and a second polyimide (PI) layer that are stacked in sequence. layer, the second silicon dioxide layer.
  • the barrier layer 48 may be located on the side of the second silicon dioxide layer facing away from the first polyimide (PI) layer.
  • the thicknesses of the first polyimide (PI) layer and the second polyimide (PI) layer can both be 90000-110000 ⁇ 5% angstroms, such as 90000 angstroms, 95000 angstroms, 110000 angstroms; the thickness of the first silicon oxide layer
  • the thickness can be 5000-7000 angstroms, such as 5000 angstroms, 5500 angstroms, 7000 angstroms;
  • the thickness of the amorphous silicon layer can be 40-60 angstroms, for example, 40 angstroms, 45 angstroms, 60 angstroms;
  • the thickness of the second silicon dioxide layer can be It is 4500-6500 angstroms, such as 4500 angstroms, 5000 angstroms, 6500 angstroms.
  • the second buffer layer 44 may include a first silicon nitride (SiN) layer and a third silicon oxide layer that are stacked in sequence, and the first silicon nitride layer may be located on the third silicon oxide layer and the substrate between the substrates.
  • the thickness of the first silicon nitride layer may be 900-1100 angstroms, for example, 900 angstroms, 950 angstroms, and 1100 angstroms; the thickness of the third silicon oxide layer may be 2000-4000 angstroms, for example, 2000 angstroms, 2500 angstroms, and 4000 angstroms. .
  • the first active layer may be a polysilicon layer, and the thickness of the first active layer may be 400-600 angstroms, for example, 400 angstroms, 500 angstroms, and 600 angstroms.
  • the second gate insulating layer 45 can be a silicon oxide layer, and the thickness of the second gate insulating layer 45 can be 500-2000 angstroms, for example, 500 angstroms, 1500 angstroms, 2000 angstroms.
  • Both the first conductive layer and the second conductive layer can be molybdenum layers, and the thickness of the first conductive layer and the second conductive layer can be 1500-2500 angstroms, for example, 1500 angstroms, 2000 angstroms, and 2500 angstroms.
  • the first dielectric layer 43 may be a silicon nitride layer, and the thickness of the first dielectric layer 43 may be 1200-1400 angstroms, for example, 1200 angstroms, 1250 angstroms, 1300 angstroms, 1350 angstroms, 1400 angstroms.
  • the first buffer layer 41 can be a silicon oxide layer, and the thickness of the first buffer layer 41 can be 3000-5000 angstroms, for example, 3000 angstroms, 3500 angstroms, and 5000 angstroms.
  • the second active layer may be an indium gallium zinc oxide (IGZO) layer, and the thickness of the second active layer may be 300-500 angstroms, for example, 300 angstroms, 350 angstroms, and 500 angstroms.
  • the second gate insulating layer 45 may be a silicon oxide layer, and the thickness of the second gate insulating layer 45 may be 1000-2000 angstroms, for example, 1000 angstroms, 1500 angstroms, and 2000 angstroms.
  • the third conductive layer may include a first titanium layer, an aluminum layer, and a second titanium layer stacked in sequence, and the thicknesses of the first titanium layer and the second titanium layer may both be 300-700 angstroms, such as 300 angstroms, 450 angstroms, and 700 angstroms.
  • the thickness of the aluminum layer can be 4500-6500 angstroms, for example, 4500 angstroms, 5000 angstroms, and 6500 angstroms.
  • the second flat layer 19 may be a polyimide (PI) layer, and the thickness of the second flat layer 19 may be 10,000-20,000 angstroms, for example, 10,000 angstroms, 16,000 angstroms, and 20,000 angstroms.
  • PI polyimide
  • the pixel-defining layer 401 may be a polyimide (PI) layer, and the thickness of the pixel-defining layer 401 may be 10,000-20,000 angstroms, for example, 10,000 angstroms, 16,000 angstroms, and 20,000 angstroms.
  • the support posts 402 may be polyimide (PI) layers, and the thickness of the support posts 402 may be 10,000-20,000 angstroms, for example, 10,000 angstroms, 16,000 angstroms, and 20,000 angstroms.
  • the anode layer 20 may include a first indium tin oxide layer, a silver layer, and a second indium tin oxide layer that are stacked in sequence, and the thickness of the first indium tin oxide layer and the second indium tin oxide layer may be 50-100 angstroms, for example, 50 Angstroms, 80 angstroms, 100 angstroms, the thickness of the silver layer may be 500-1500 angstroms, for example, 500 angstroms, 800 angstroms, 1500 angstroms.
  • the above-mentioned structural film layer can also be of other materials and thicknesses, for example, the material of the dielectric layer and the passivation layer can also be silicon nitride or transparent organic resin and other materials, and the material of the flat layer can also be transparent Polyimide (CPI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN) and other materials.
  • the material of the conductive layer can also be metal materials such as copper and molybdenum.
  • An exemplary embodiment of the present disclosure further provides a method for fabricating an array substrate.
  • the array substrate may include a pixel driving circuit, and the pixel driving circuit may include a P-type driving transistor, an N-type first transistor, and a capacitor.
  • the first electrode of a transistor is connected to the gate of the driving transistor, the first electrode of the capacitor is connected to the gate of the driving transistor, and the manufacturing method of the array substrate includes:
  • Step S1 forming a base substrate
  • Step S2 forming a first conductive layer on one side of the base substrate, the first conductive layer includes a first conductive part, and the first conductive part is configured as the gate of the driving transistor and the capacitor. the first electrode;
  • Step S3 forming a first dielectric layer on the side of the first conductive layer away from the base substrate;
  • a first buffer layer is formed on the side of the first dielectric layer away from the base substrate, the first buffer layer is provided with a slot, and the slot is on the orthographic projection of the base substrate and the the orthographic projection of the first conductive portion on the base substrate at least partially overlaps;
  • Step S4 forming a second conductive layer on the side of the first buffer layer away from the first conductive layer, the second conductive layer comprising:
  • the second conductive portion is configured as a gate of the first transistor
  • the third conductive part is located at the bottom of the slot, and the orthographic projection of the third conductive part on the base substrate is the same as the orthographic projection of the first conductive part on the base substrate
  • the projections are at least partially coincident to form the second electrode of the capacitor.
  • the manufacturing method of the array substrate may further include: sequentially forming on the base substrate 1: a barrier layer 48, a second buffer layer 44, a first active layer, a second gate insulating layer 45, a first conductive layer, a first dielectric layer
  • the first active layer may include a first active portion 53
  • the first conductive layer may include a first conductive portion 13 configured as a gate of a driving transistor
  • the second active layer may include a second active portion 62.
  • the method for fabricating the array substrate may further include etching the first buffer material layer 041 and the first gate insulating material layer 018 through a patterning process to form the slot 411 .
  • the buffer material layer 041 forms a first buffer layer.
  • the slot 411 may extend to the first surface of the first dielectric layer 43, the third conductive portion may be located on the first surface of the first dielectric layer, and the first surface is The first dielectric layer faces a surface on one side of the first buffer layer.
  • the method for fabricating the array substrate may further include forming a second conductive layer through a patterning process, and the second conductive layer may include a second conductive portion 55 and a third conductive portion 721 configured as the gate of the first transistor, The third conductive portion 721 may be located at the bottom of the slot 411 .
  • the first gate insulating material layer 018 may also be patterned at the same time to form the first gate insulating layer 18 .
  • the method for fabricating the array substrate may also etch only any one of the first buffer material layer 041 and the first gate insulating material layer 018 through a patterning process to form the slot 411.
  • the method for fabricating the array substrate may further include: forming a second via hole 82 on the third conductive portion, and the second via hole 82 may extend through the first dielectric layer 43 to all the The surface of the first conductive portion 13 is described.
  • a second dielectric layer 42 is formed on the side of the second conductive layer away from the base substrate 1 , and the second dielectric layer 42 fills the second via holes 82 .
  • FIG. 11 the method for fabricating the array substrate may further include: forming a second via hole 82 on the third conductive portion, and the second via hole 82 may extend through the first dielectric layer 43 to all the The surface of the first conductive portion 13 is described.
  • a second dielectric layer 42 is formed on the side of the second conductive layer away from the base substrate 1 , and the second dielectric layer 42 fills the second via holes 82 .
  • the method for fabricating an array substrate may further include: forming a third conductive layer on the side of the second dielectric layer 42 away from the base substrate 1 , and the third conductive layer may include a fourth conductive layer.
  • the conductive part 24 , the fourth conductive part 24 can be electrically connected to the first conductive part 13 through the first via hole 81 .
  • the orthographic projection of the fourth conductive portion 24 on the base substrate 1 may be located on the orthographic projection of the first conductive portion 13 on the base substrate 1, and the fourth conductive portion 24 is located at the
  • the orthographic projection area of the base substrate may be smaller than the orthographic projection area of the first conductive portion 13 on the base substrate.
  • the present exemplary embodiment sets the fourth conductive part 24 to a smaller area.
  • this setting reduces the parasitic capacitance between the fourth conductive part 24 and other conductive structures (such as data lines, anode layers, etc.)
  • the noise impact of other conductive structures on the gate of the driving transistor is reduced; on the other hand, this arrangement facilitates the shielding of the fourth conductive portion 24 by the shielding layer, so as to further reduce the noise impact of other conductive structures on the gate of the driving transistor.
  • the orthographic projection area of the fourth conductive portion 24 on the base substrate 1 may be 4%-25% of the orthographic projection area of the first conductive portion 13 on the base substrate.
  • the ratio of the orthographic projection area of the fourth conductive portion 24 on the base substrate 1 to the orthographic projection area of the first conductive portion 13 on the base substrate may be 4%, 8%, 10%, Any of 12%, 15%, 20%, 25%.
  • the ratio of the orthographic projection area of the fourth conductive portion 24 on the base substrate 1 to the orthographic projection area of the first via hole 81 on the base substrate may be 1-2.5
  • the ratio of the orthographic projection area of the fourth conductive portion 24 on the base substrate 1 to the orthographic projection area of the first via hole 81 on the base substrate may be 1, 1.2, 1.3, 1.5 , 2.0, 2.3, 2.5, etc.
  • the method for fabricating an array substrate may further include: sequentially forming a second dielectric layer, a third conductive layer, a passivation layer, a first flat layer, a Four conductive layers, a second flat layer, an anode layer, and a pixel definition layer are formed to form the array substrate structure shown in FIG. 7 .
  • Figure 15 is the structural layout of the first active layer
  • Figure 16 is the structural layout of the first conductive layer
  • Figure 17 is the structural layout of the second active layer
  • Figure 18 is the first active layer Layer, the first conductive layer, the combined layout of the second active layer
  • Figure 19 is the structural layout of the second conductive layer
  • Figure 20 is the first active layer, the first conductive layer, the second active layer, the second conductive layer
  • Figure 21 is the structural layout of the third conductive layer
  • Figure 22 is the combined layout of the first active layer, the first conductive layer, the second active layer, the second conductive layer, and the third conductive layer
  • Figure 23 is the structural layout of the fourth conductive layer
  • FIG. 24 is the combined layout of the first active layer, the first conductive layer, the second active layer, the second conductive layer, the third conductive layer, and the fourth conductive layer
  • FIG. 25 is the structure layout of the anode layer
  • FIG. 26 is the combined layout of the first active layer, the first conductive layer, the second active layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the anode layer.
  • the first active layer may include the above-mentioned first active portion 53 , and in addition, the first active layer may further include: a third active portion 51 extending along the first direction Y1 and The fourth active part 52 , the third active part 51 and the fourth active part 52 may be distributed along the second direction X at intervals.
  • the first active part 53 may be connected between the third active part 51 and the fourth active part 52.
  • the third active portion 51 may include a first sub-active portion 511 and a second sub-active portion 514
  • the fourth active portion 52 may include a third sub-active portion 525 and a fourth sub-active portion 526.
  • the first active part 53 can be configured as the channel region of the driving transistor DT; the first sub-active part 511 can be configured as the channel region of the second transistor T2; the second sub-active part 514 can be configured as the channel region of the second transistor T2 is the channel region of the fourth transistor T4; the third sub-active part 525 may be configured as the channel region of the fifth transistor T5; the fourth sub-active part 526 may be configured as the channel region of the sixth transistor T6.
  • the first active layer may be a polysilicon material, and correspondingly, the driving transistor DT, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be P-type low temperature Polysilicon transistors.
  • the orthographic projection of the third conductive portion 721 on the base substrate and the orthographic projection of the fourth active portion 52 on the base substrate may not overlap, so as to avoid unnecessary generation of the third conductive portion 721 and the fourth active portion 52 parasitic capacitance.
  • the first conductive layer may include the above-mentioned first conductive portion 13 , and in addition, the first conductive layer may further include a first gate line 11 , a second gate line 12 , a third gate line 14 , a The fifth gate line 15 and the sixth gate line 16 .
  • the first grid line 11 may be located on one side of the first conductive portion 13 ; the second grid line 12 may be located on the side of the first grid line 11 away from the first conductive portion 13 ; the third grid line 14 may be Located on the side of the second grid line 12 away from the first conductive part 13; the fifth grid line 15 is located on the side of the first conductive part 13 away from the first grid line; the sixth grid line 16 is located on the fifth grid line 15 is away from the side of the first conductive portion 13 .
  • the first gate line 11 , the second gate line 12 , the third gate line 14 , the fifth gate line 15 , and the sixth gate line 16 may all extend along the second direction X.
  • the first gate line 11 may be used to provide the first gate driving signal terminal G1 in FIG.
  • the first gate line 11 may include a first gate part 113 ; the second gate line 12 may be used to provide the first gate line 11 in FIG. 1 .
  • the second gate driving signal terminal G2, the second gate line 12 may include a second gate portion 125; the third gate line 14 may be used as a second reset signal line for providing the second reset signal terminal Re2 in FIG.
  • the tri-gate line 14 may include a third gate part 143 ; the fifth gate line 15 may serve as an enable signal line for providing the enable signal terminal EM in FIG. 1 , and the fifth gate line 15 may include a fourth gate part 154 and the fifth gate part 155 ; the sixth gate line 16 can be used as the first reset signal line to provide the first reset signal terminal Re1 in FIG.
  • the sixth gate line 16 includes the sixth gate part 166 .
  • the first gate portion 113 may be configured as the gate of the second transistor T2, the second gate portion 125 may be configured as the first gate of the first transistor T1, and the third gate portion 143 may be configured as The first gate of the third transistor T3; the fourth gate part 154 may be configured as the gate of the fourth transistor T4; the fifth gate part 155 may be configured as the gate of the fifth transistor T5; the sixth gate Section 166 may be configured as the gate of sixth transistor T6.
  • the second active layer may include a plurality of active parts 6 extending along the first direction Y1 , the plurality of active parts 6 may be spaced apart along the second direction X, and the plurality of active parts 6 One-to-one correspondence with a plurality of pixel driving circuits.
  • the active part 6 may include the above-mentioned second active part 62 and fifth active part 63 , wherein the second active part 62 may form the channel region of the first transistor T1 , and the fifth active part 62 may form the channel region of the first transistor T1 .
  • the source part 63 may form a channel region of the third transistor T3.
  • the second conductive layer may include the aforementioned second conductive portion 55 , the third conductive portion 721 , and the sixth conductive portion 722 .
  • the second conductive layer may further include: a fourth gate line 74 , a fifth gate line 75 , and a sixth gate line 76 .
  • the fourth gate line 74 , the fifth gate line 75 , and the sixth gate line 76 can all extend along the second direction X.
  • the fourth gate line 74 can be connected with the second gate line 12 in the wiring area around the display area through vias; the fifth gate line 75 can be connected with the third gate line 14 in the routing area around the display area through vias.
  • the fourth gate line 74 may include the aforementioned second conductive portion 55, and the second conductive portion 55 may be configured as a second gate at the first transistor side.
  • the fifth gate line 75 may include a seventh gate part 753, and the seventh gate part 753 may form the second gate of the third transistor.
  • the sixth gate line 76 can be used as an initial signal line to provide the initial signal terminal Vinit in FIG. 1 .
  • the orthographic projection of the third conductive portion 721 on the base substrate may cover the orthographic projection of the first conductive portion 13 on the base substrate.
  • the sixth conductive portion 722 can be connected to the power line in the third conductive layer through a via hole.
  • the third conductive layer may include the above-mentioned power supply line 26 and the fourth conductive portion 24 .
  • the third conductive layer may further include: the first conductive line 21 , the seventh conductive portion 23 , the first conductive portion 23 , the The connection part 27 , the second connection part 28 , the third connection part 29 , and the fourth connection part 201 .
  • the first connection part 27 can be connected to the fourth active part 52 through the via hole 202 to connect the second pole of the sixth transistor, and the first connection part 27 is also connected to the sixth gate line 76 through the via hole 203, so that the The sixth gate line 76 provides the initial signal terminal to the second electrode of the sixth transistor.
  • first connection part 27 can also be connected to the active part 6 in the pixel driving circuit of the next row through the via hole and 204, so as to provide an initial signal to the third transistor in the pixel driving circuit of the next row through the sixth gate line 76 end.
  • the second connection part 28 may be connected to the fourth active part 52 through the via hole 205 to connect the second electrode of the fifth transistor.
  • the third connection part 29 is connected to the active part 6 through the via hole 206 to connect the second electrode of the first transistor, and the third connection part 29 can be connected to the fourth active part 52 through the via hole 207 to connect to the second electrode of the driving transistor pole, so that the second pole of the first transistor is connected to the second pole of the driving transistor.
  • the fourth connection part 201 may be connected to the third active part 51 through the via hole 208 to connect the first electrode of the second transistor.
  • the fourth conductive layer may include the aforementioned fifth conductive portion 35 , and in addition, the fourth conductive layer may further include the data line 31 and the fifth connection portion 32 .
  • the data line 31 can be connected to the fourth connection part 201 through the via hole 33 to connect to the first electrode of the second transistor T2.
  • the fifth conductive portion 35 may be connected to the power line 26 through the via hole 34 .
  • the fifth connection part 32 may be connected with the second connection part 28 through the via hole 36 to be connected with the second pole of the fifth transistor.
  • the sectional view shown in FIG. 5 can be cut along the dotted line A in the figure. It should be noted that some structures are omitted in FIG. 5 .
  • the anode layer may include a first anode part 87 , a second anode part 88 , and a third anode part 83 , and the first anode part 87 may be connected to the fifth connection part 32 through the via hole 84 to connect with the fifth connection part 32 .
  • the second pole of the fifth transistor is connected; the second anode part 88 can be connected to the fifth connection part 32 in another pixel driving circuit through the via hole 85; the third anode part 83 can be connected to another pixel driving circuit through the via hole 86 the fifth connecting part 32 .
  • G light-emitting units may be formed on the first anode portion 87 ; R light-emitting units may be formed on the second anode portion 88 ; and B light-emitting units may be formed on the third anode portion 83 .
  • FIG. 27 it is a timing diagram of each node in a driving method of the pixel driving circuit of FIG. 1 .
  • G1 represents the timing of the first gate driving signal terminal G1
  • G2 represents the timing of the second gate driving signal terminal G2
  • R represents the timing of the first reset signal terminal Re1
  • Re2 represents the timing of the second reset signal terminal Re2
  • N represents the timing of the node N
  • EM represents the timing of the enable signal terminal EM
  • Da represents the timing of the data signal terminal Da.
  • the driving method of the pixel driving circuit may include a reset stage t1, a compensation stage t2, and a light-emitting stage t3.
  • the first reset signal terminal Re1 outputs a low-level signal
  • the second reset signal terminal Re2 outputs a high-level signal
  • the third transistor T3 and the sixth transistor T6 are turned on
  • the initial signal terminal Vinit goes to the node N
  • the first The second pole of the five transistors T5 is input with an initialization signal.
  • the compensation stage t2 the first gate driving signal terminal G1 outputs a low-level signal, the second gate driving signal terminal G2 outputs a high-level signal, the second transistor T2 and the first transistor T1 are turned on, and the data signal terminal Da
  • the driving signal is output to write the voltage Vdata+Vth to the node N, where Vdata is the voltage of the driving signal and Vth is the threshold voltage of the driving transistor DT.
  • Light-emitting stage t3 the enable signal terminal EM outputs a low-level signal, the fourth transistor T4 and the fifth transistor T5 are turned on, and the driving transistor DT emits light under the action of the voltage Vdata+Vth stored in the capacitor C.
  • the drive transistor output current formula I ( ⁇ WCox/2L)(Vgs-Vth)2, where ⁇ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the drive transistor channel, and L drives The length of the transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor.
  • the output current I ( ⁇ WCox/2L)(Vdata+Vth ⁇ Vdd ⁇ Vth)2 of the drive transistor in the pixel drive circuit of the present disclosure.
  • the pixel driving circuit can avoid the influence of the threshold value of the driving transistor on its output current.
  • the second gate driving signal terminal G2 is lowered from a high level to a low level , that is, the gate of the first transistor T1 is lowered from a high level to a low level, the voltage of the first electrode of the first transistor T1 will decrease under the capacitive coupling effect, and the voltage of the node N connected to the first electrode of the first transistor T1 will also decrease. will be reduced accordingly.
  • the voltage drop of the node N ie, the gate of the driving transistor
  • the source driving circuit In order to ensure that the driving transistor outputs a normally required driving current, the source driving circuit needs to provide a data signal with a higher voltage value to the data signal terminal through the data line.
  • the voltage provided by the source driving circuit to the data line needs to be greater than 6.3V, but the maximum voltage provided by the existing source driving circuit to the data line is 6V, which cannot meet the Display requirements normally.
  • the second gate line 12 is disposed on the side of the first gate line 11 away from the first conductive portion 13 .
  • this arrangement increases the distance between the second gate line 12 and the first conductive part 13, reduces the lateral capacitance between the second gate line 12 and the first conductive part 13, and thus reduces the gate of the first transistor
  • the first gate line 11 and the first conductive part 13 can form a side capacitance, as shown in FIG. 2 , the second transistor ends at the compensation stage t2 Then, jump from low level to high level, so that the gate of the second transistor can pull up the gate of the driving transistor.
  • the array substrate provided by this exemplary embodiment reduces the size of the first gate line 11 and the The distance between the first conductive parts 13 increases the lateral capacitance between the first gate line 11 and the first conductive part 13, so that the pull-up effect of the gate of the second transistor on the gate of the driving transistor can be enhanced; on the other hand , the first gate line 11 is located between the first conductive part 13 and the second gate line 12, the first gate line 11 can play a certain shielding effect on the second gate line 12, thereby further reducing the first transistor gate to drive Pull-down effect of transistor gate.
  • the pull-up effect of the first gate line 11 on the first conductive portion 13 is stronger than the pull-down effect of the second gate line 12 on the first conductive portion 13 , so that the array substrate can offset the above to a certain extent.
  • the first gate line 11 may be located on one side of the first conductive portion 13 in the first direction Y1 and extend along the second direction X, and the first direction Y1 may intersect the second direction X, For example, the first direction Y1 and the second direction X may be perpendicular.
  • the first gate line 11 may include: a first extension part 111 and a second extension part 112 .
  • the orthographic projection of the first extension part 111 on the base substrate is located where at least part of the first conductive part 13 is located.
  • the orthographic projection of the base substrate is opposite to the first direction Y1; the orthographic projection of the second extension portion 112 on the base substrate and the orthographic projection of the first conductive portion 13 on the base substrate Misalignment in the first direction Y1.
  • Both the first direction and the second direction may be directions parallel to the plane of the base substrate.
  • the orthographic projection of the first extension portion 111 on the base substrate is opposite to the orthographic projection of at least part of the first conductive portion 13 on the base substrate in the first direction Y1" can be understood Therefore, the area covered by the orthographic projection of the first extending portion 111 on the base substrate moves infinitely along the first direction Y1 and the third direction Y2 and at least part of the first conductive portion 13 is on the base substrate.
  • the orthographic projection of the second extension portion 112 on the base substrate is staggered from the orthographic projection of the first conductive portion 13 on the base substrate in the first direction Y1 can be understood to mean that the The area covered by the infinite movement of the second extension portion 112 on the base substrate along the first direction Y1 and the third direction Y2 is the same as the orthographic projection of the first conductive portion 13 on the base substrate along the first direction Y1 and the third direction Y2.
  • the areas covered by infinite movement in the direction Y1 and the third direction Y2 do not intersect, and similarly, the first direction Y1 and the third direction Y2 are opposite.
  • the distance S1 between the orthographic projection of the first extending portion 111 on the base substrate and the orthographic projection of the first conductive portion 13 on the base substrate on the third direction Y2 may be smaller than all
  • the distance S1 between the orthographic projection of the first extension portion 111 on the base substrate and the orthographic projection of the first conductive portion 13 on the base substrate on the third direction Y2 may refer to, The edge of the extension portion 111 facing the first conductive portion 13 in the orthographic projection of the base substrate and the edge of the first conductive portion 13 facing the first extension portion 111 in the orthographic projection of the base substrate on the third direction Y2 distance.
  • the distance S2 between the orthographic projection of the second extending portion 112 on the base substrate and the orthographic projection of the first conductive portion 13 on the base substrate on the third direction Y2 may refer to the second extending portion 112 on the substrate.
  • the size of the orthographic projection of the first extension portion 111 on the base substrate in the second direction X may be equal to the size of the first conductive portion 13 on the base substrate The dimension of the orthographic projection in the second direction X.
  • This setting can greatly increase the capacitance value of the lateral capacitance formed by the first extension portion 111 and the first conductive portion 13, so as to further increase the pull-up effect of the first gate line on the gate of the driving transistor.
  • the second extension portion 112 may be configured as the gate of the second transistor. Since the orthographic projection of the second extending portion 112 on the base substrate on the third direction Y2 is far from the orthographic projection of the first conductive portion 13 on the base substrate, this design can sufficiently reserve the space for disposing the second transistor.
  • FIG. 29 is a partial layout structure of the third conductive layer in FIG. 21
  • FIG. 30 is a partial layout structure in FIG. 22
  • the third conductive layer may include: the above-mentioned fourth conductive portion 24 , the seventh conductive portion 23 , and the first conductive wire 21 .
  • the fourth conductive portion 24 is connected to the first conductive portion 13 through the first via hole 81 .
  • the seventh conductive part 23 can be configured as the first pole of the first transistor, and the orthographic projection of the first gate line 11 on the base substrate can be located on the fourth conductive part 24 in the The orthographic projection of the base substrate and the orthographic projection of the seventh conductive portion 23 are between the orthographic projection of the base substrate; the first conductive wire 21 is connected between the fourth conductive portion 24 and the seventh conductive portion 23 to The first electrode of the first transistor is connected to the gate of the driving transistor, the first conductive line 21 may extend along the first direction Y1, and the orthographic projection of the first conductive line 21 on the base substrate is connected to the first conductive line 21 .
  • a gate line 11 intersects at the orthographic projection of the base substrate.
  • a gate line 11 forms a parallel plate capacitor structure. Using the coupling effect of the parallel plate capacitance structure, the first gate line 11 can pull up the first conductive line 21 after the compensation phase of the pixel driving circuit is completed, because the first conductive line 21 is electrically connected to the first conductive portion 13 , that is, this arrangement can further enhance the pull-up effect of the first gate line 11 on the first conductive portion 13 .
  • the orthographic projection of the second grid line 12 on the base substrate may be located on the orthographic projection of the first grid line 11 on the base substrate
  • the projection and the orthographic projection of the seventh conductive portion 23 are between the base substrate;
  • the second gate line 12 may include a third extension portion 123 and a fourth extension portion 124 alternately connected in sequence along the second direction X , wherein the size of the orthographic projection of the third extension portion 123 on the base substrate in the first direction Y1 may be smaller than the size of the orthographic projection of the fourth extension portion 124 on the base substrate in the first direction Y1 size on .
  • the orthographic projection of the first conductive line 21 on the base substrate may intersect with the orthographic projection of the third extension portion 123 on the base substrate.
  • Part of the third extension part 123 and part of the first conductive line 21 may form a parallel plate capacitor structure. Based on the coupling effect of the parallel plate capacitance structure, the third extension portion 123 can pull down the first conductive line 21 after the compensation stage of the pixel driving circuit is completed. Since the first conductive line 21 is electrically connected to the first conductive portion 13, the The three extending portions 123 can pull down the first conductive portion 13 .
  • the size of the orthographic projection of the third extension portion 123 on the base substrate in the first direction Y1 is smaller than that of the fourth extension portion 124 in the orthographic projection of the base substrate in the first direction Y1.
  • the dimension in one direction Y1 that is, the present exemplary embodiment reduces the dimension of the third extension part 123 in the first direction Y1, thereby reducing the parallel plate formed by the third extension part 123 and the first conductive wire 21
  • the electrode area of the capacitor structure according to the calculation of the capacitance of the parallel plate capacitor, it can be known that the capacitance of the parallel plate capacitor structure is proportional to its electrode area, that is, the setting reduces the parallel plate capacitance formed by the third extension 123 and the first conductive line 21.
  • part of the fourth extension portion 124 may be configured as the first gate of the first transistor.
  • the channel region of the first transistor may extend along the first direction Y1, so that the channel region of the first transistor may have a larger length to reduce leakage current of the first transistor.
  • the orthographic projection of the power line 26 on the base substrate may intersect with the orthographic projection of the third extension 123 on the base substrate, and this arrangement can reduce the distance between the power line 26 and the second
  • the overlapping area of the gate lines reduces the capacitive coupling effect caused by the power supply line 26 to the second gate line 12 when the voltage fluctuates.
  • Figure 31 is a partial layout structure of Figure 24.
  • the power cord 26 may include a fifth extension portion 265, where the orthographic projection of the fifth extension portion 265 on the base substrate and the orthographic projection of at least part of the first conductive portion 13 on the base substrate are located there. Opposite in the second direction X, "the orthographic projection of the fifth extending portion 265 on the base substrate and the orthographic projection of at least part of the first conductive portion 13 on the base substrate are in the second direction.
  • the area covered by the infinite movement of the fifth extension portion 265 in the orthographic projection of the base substrate along the second direction and the opposite direction of the second direction is at least partially covered by the first conductive portion 13
  • the areas covered by the infinite movement of the orthographic projection of the base substrate along the second direction and the opposite direction of the second direction are completely coincident.
  • part of the orthographic projection of the data lines 31 on the base substrate may be located on the orthographic projection of the fifth extension portion 265 on the base substrate.
  • the fifth extension portion 265 since the fifth extension portion 265 is stacked between the data line 31 and the first conductive portion 13, and the fifth extension portion 265 receives a stable voltage, the fifth extension portion 265 can be used as a shielding layer to reduce the distance between the data line 31 and the first conductive portion 13.
  • the coupling capacitance between the conductive parts 13 reduces the coupling effect of the data line 31 to the first conductive part 13 .
  • the fifth conductive portion 35 may be connected to the power line 26 through the via hole 34 .
  • the R pixel unit, the G pixel unit, and the B pixel unit have different driving voltage intervals ( That is, the difference between the data signal voltage at the maximum brightness and the data signal voltage at the minimum brightness).
  • the source driver circuit needs to provide data signals of different driving voltage intervals to the R pixel unit, the G pixel unit, and the B pixel unit, and the source driver circuit needs to switch between different driving voltage intervals, so the source driver circuit needs to consume a lot of power. .
  • the width to length ratio of the channel region of the driving transistor in the R pixel driving circuit, the width to length ratio of the channel region of the driving transistor in the G pixel driving circuit, and the width to length of the channel region of the driving transistor in the G pixel driving circuit may not all be the same. That is, in the R pixel driving circuit, the G pixel driving circuit, and the B pixel driving circuit, the width to length ratio of the channel region of the driving transistor in at least one of the pixel driving circuits is not equal to the width and length of the channel region of the driving transistor in the other pixel driving circuits. Compare.
  • the width to length ratio of the channel region of the driving transistor in the R pixel driving circuit may be 3.5/40, and the width to length ratio of the channel region of the driving transistor in the B pixel driving circuit may be 3.5/25.
  • the channel region of the driving transistor in the B pixel unit is "Z" type
  • the channel region of the driving transistor in the R pixel unit and the channel region of the driving transistor in the G pixel unit are "S" type.
  • the channel region of the driving transistor in the R pixel driving circuit, the channel region of the driving transistor in the G pixel driving circuit, and the channel region of the driving transistor in the R pixel driving circuit have the same width to length ratio , this setting can reduce the difference in driving voltage between the R pixel unit, the G pixel unit, and the B pixel unit, thereby reducing the power consumption of the source driving circuit.
  • the present exemplary embodiment also provides a display device, wherein the display device may include the above-mentioned array substrate.
  • the display device may be a display device such as a mobile phone, a tablet computer, and a TV.

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Abstract

一种阵列基板及其制作方法、显示装置，阵列基板包括P型驱动晶体管（DT）、N型第一晶体管（T1）、电容（C）、衬底基板（1）、第一导电层、第一介电层（43）、第一缓冲层（41）、第二导电层，第一导电层层叠设置于衬底基板（1）的一侧，包括被配置为驱动晶体管（DT）的栅极和电容（C）的第一电极的第一导电部（13）；第一介电层（43）层叠设置于第一导电层背离衬底基板（1）的一侧；第一缓冲层（41）层叠设置于第一介电层（43）背离衬底基板（1）的一侧，且设置有开槽（411）；第二导电层层叠设置于第一缓冲层（41）背离衬底基板（1）的一侧，包括第二导电部（55）和第三导电部（721），第二导电部（55）被配置为第一晶体管（T1）的栅极；第三导电部（721）位于开槽（411）的底部，以形成电容（C）的第二电极。该阵列基板中，驱动晶体管（DT）的栅极具有较好的抗噪音干扰能力。

Description

阵列基板及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其制作方法、显示装置。
背景技术
相关技术中，像素驱动电路可以采用低温多晶氧化物(Low temperature polycrystalline oxide，LTPO)技术形成，低温多晶氧化物技术是通过将N型的金属氧化物晶体管和P型的低温多晶体硅晶体管相结合的方式形成像素驱动电路。
相关技术中，LTPO技术通常通过位于源漏层的导电部形成像素驱动电路中电容的一电极。该导电部通过过孔与驱动晶体管的栅极连接，以实现电容与驱动晶体管栅极连接。然而，为了形成电容结构，该导电部具有较大的面积，从而导致与该导电部连接的驱动晶体管栅极容易受到噪音的影响。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
根据本公开的一个方面，提供一种阵列基板，所述阵列基板包括像素驱动电路，所述像素驱动电路包括P型驱动晶体管、N型第一晶体管、电容，所述第一晶体管的第一极连接所述驱动晶体管的栅极，所述电容的第一电极连接所述驱动晶体管的栅极，其中，所述阵列基板还包括：衬底基板、第一导电层、第一介电层、第一缓冲层、第二导电层。第一导电层层叠设置于所述衬底基板的一侧，所述第一导电层包括第一导电部，所述第一导电部被配置为所述驱动晶体管的栅极和所述电容的第一电极；第一介电层层叠设置于所述第一导电层背离所述衬底基板的一侧；第一缓冲层层叠设置于所述第一介电层背离所述衬底基板的一侧，所述第一缓冲层上设置有开槽，所述开槽在所述衬底基板的正投影与所述第一导电部在所述衬底基板的正投影至少部分重合；第二导电层层叠设置于所述第一缓冲层背离所述衬底基板的一侧，所述第二导电层包括第二导电部和第三导电部，所述第二导电部被配置为所述第一晶体管的栅极；所述第三导电部位于所述开槽的底部，且所述第三导电部在所述衬底基板的正投影与所述第一导电部在所述衬底基板的正投影至少部分重合，以形成所述电容的第二电极。
本公开一种示例性实施例中，所述开槽延伸至所述第一介电层的表面，所述第三导电部位于所述第一介电层背离所述衬底基板的一侧。
本公开一种示例性实施例中，所述阵列基板还包括：第三导电层，所述第三导电层层叠设置于所述第二导电层背离所述衬底基板的一侧，包括第四导电部，所述第四导电部通 过贯穿所述第三导电部的第一过孔与所述第一导电部电连接，且与所述第二导电部绝缘；其中，所述第四导电部在所述衬底基板的正投影位于所述第一导电部在所述衬底基板的正投影上，且所述第四导电部在所述衬底基板的正投影面积小于所述第一导电部在所述衬底基板的正投影面积。
本公开一种示例性实施例中，所述第四导电部在所述衬底基板的正投影面积与所述第一过孔在所述衬底基板的正投影面积的比值为1-1.5。
本公开一种示例性实施例中，所述第四导电部在所述衬底基板的正投影面积与所述第一导电部在所述衬底基板的正投影面积的比值为8％-15％。
本公开一种示例性实施例中，所述第三导电部上形成有第二过孔，所述第二过孔贯穿所述第一介电层延伸至所述第一导电部的表面，所述阵列基板还包括第二介电层，第二介电层层叠设置于所述第二导电层和所述第三导电层之间，所述第二介电层上形成有所述第一过孔，所述第一过孔贯穿所述第三导电部延伸至所述第一导电部的表面；且所述第一过孔在所述衬底基板的正投影位于所述第二过孔在所述衬底基板的正投影以内。
本公开一种示例性实施例中，所述第三导电层还包括用于提供电源电压的电源线，所述阵列基板还包括第四导电层，第四导电层层叠设置于所述第三导电层背离所述衬底基板的一侧，所述第四导电层包括与所述电源线连接的第五导电部，所述第五导电部在所述衬底基板的正投影覆盖所述第一导电部在所述衬底基板的正投影。
本公开一种示例性实施例中，所述第二导电层还包括与所述第三导电部连接的第六导电部，所述第六导电部通过过孔与所述电源线连接。
本公开一种示例性实施例中，所述第一缓冲层包括第一缓冲层、第一栅极绝缘层。第一缓冲层层叠设置于所述第一介电层背离所述衬底基板的一侧；第一栅极绝缘层层叠设置于所述第一缓冲层背离所述衬底基板的一侧。
本公开一种示例性实施例中，所述阵列基板还包括：第一有源层、第二有源层、第二栅极绝缘层、阻挡层、第二缓冲层、第二介电层、钝化层、第一栅极绝缘层。阻挡层层叠设置于所述衬底基板的一侧；第二缓冲层层叠设置于所述阻挡层背离衬底基板的一侧；第一有源层层叠设置于所述第二缓冲层背离所述衬底基板的一侧，所述第一有源层包括第一有源部，所述第一有源部被配置为所述驱动晶体管的沟道区；第二栅极绝缘层层叠设置于所述第一有源层背离所述衬底基板的一侧，其中，所述第一导电层层叠设置于所述第二栅极绝缘层背离所述衬底基板的一侧；第二有源层层叠设置于所述第一缓冲层背离所述衬底基板的一侧，包括第二有源部，所述第二有源部被配置为所述第一晶体管的沟道区；第一栅极绝缘层层叠设置于所述第二有源层背离所述衬底基板的一侧，其中，第二导电层层叠设置于所述第一栅极绝缘层背离所述衬底基板的一侧；第二介电层层叠设置于所述第二有源层背离所述衬底基板的一侧，第二介电层层叠设置于所述第二导电层背离所述衬底基板的一侧，其中，第三导电层层叠设置于所述第二介电层背离所述衬底基板的一侧；钝化层层叠设置于所述第三导电层背离所述衬底基板的一侧。
本公开一种示例性实施例中，所述阵列基板包括非显示区，所述阵列基板上形成有位于非显示区的条形槽，所述条形槽贯穿所述钝化层、第二介电层、第一缓冲层、第一介电层、第二缓冲层、阻挡层延伸至所述衬底基板的表面；所述阵列基板还包括第一平坦层，第一平坦层层叠设置于所述钝化层背离所述衬底基板的一侧，且填充所述条形槽；其中，所述第一平坦层材料的可弯折性能强于所述钝化层、第二介电层、第一缓冲层、第一介电层、第二缓冲层、阻挡层材料的可弯折性能。
本公开一种示例性实施例中，所述第一介电层在层叠方向上的厚度为1200-1400埃。
本公开一种示例性实施例中，所述阵列基板还包括：使能信号线、初始信号线、阳极层、第一复位信号线、第二复位信号线、电源线、第一栅线、第二栅线、数据线，所述第一晶体管的第二极连接所述驱动晶体管的第二极，栅极连接所述第二栅线，所述像素驱动电路还包括：第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管。第二晶体管的第一极连接所述数据线，第二极连接所述驱动晶体管的第一极，栅极连接所述第一栅线；第三晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述初始信号线，栅极连接所述第二复位信号线；第四晶体管的第一极连接所述电源线，第二极连接所述驱动晶体管的第一极，栅极连接所述使能信号线；第五晶体管的第一极连接所述驱动晶体管的第二极，第二极连接所述阳极层，栅极连接所述使能信号线；第六晶体管的第一极连接所述第五晶体管的第二极，第二极连接所述初始信号线，栅极连接所述第一复位信号线。
本公开一种示例性实施例中，所述驱动晶体管、第二晶体管、第四晶体管、第五晶体管、第六晶体管为P型低温多晶硅晶体管；所述第一晶体管、第三晶体管为N型金属氧化物晶体管。
根据本公开的一个方面，提供一种阵列基板制作方法，所述阵列基板包括像素驱动电路，所述像素驱动电路包括P型驱动晶体管、N型第一晶体管、电容，所述第一晶体管的第一极连接所述驱动晶体管的栅极，所述电容的第一电极连接所述驱动晶体管的栅极，所述阵列基板制作方法包括：
形成衬底基板；
在所述衬底基板一侧形成第一导电层，所述第一导电层包括第一导电部，所述第一导电部被配置为所述驱动晶体管的栅极和所述电容的第一电极；
在所述第一导电层背离所述衬底基板的一侧形成第一介电层；
在所述第一介电层背离所述衬底基板的一侧形成第一缓冲层，所述第一缓冲层上设置有开槽，所述开槽在所述衬底基板的正投影与所述第一导电部在所述衬底基板的正投影至少部分重合；
在所述第一缓冲层背离所述第一导电层一侧形成第二导电层，所述第二导电层包括：
第二导电部，所述第二导电部被配置为所述第一晶体管的栅极；
第三导电部，所述第三导电部位于所述开槽的底部，且所述第三导电部在所述衬底基板的正投影与所述第一导电部在所述衬底基板的正投影至少部分重合，以形成所述电容的 第二电极。
在所述第一介电层背离所述第一导电层一侧形成第一缓冲层，包括：
在所述第一介电层背离所述衬底基板一侧形成第一缓冲材料层；
在所述第一缓冲材料层背离所述衬底基板一侧形成第一栅极绝缘材料层；
对所述第一缓冲材料层和第一栅极绝缘材料层进行刻蚀以形成所述开槽；
其中，刻蚀后的所述第一缓冲材料层形成所述第一缓冲层。
本公开一种示例性实施例中，所述开槽延伸至所述第一介电层的表面，所述第三导电部位于所述第一介电层背离所述衬底基板的一侧。。
本公开一种示例性实施例中，所述衬底基板制作方法还包括：
在所述第二导电层背离所述衬底基板的一侧形成第三导电层，所述第三导电层包括第四导电部，所述第四导电部通过贯穿所述第三导电部的过孔与所述第一导电部电连接；
其中，所述第四导电部在所述衬底基板的正投影位于所述第一导电部在所述衬底基板的正投影上，且所述第四导电部在所述衬底基板的正投影面积小于所述第一导电部在所述衬底基板的正投影面积。
本公开一种示例性实施例中，在所述第二导电层背离所述衬底基板的一侧形成第三导电层之前，还包括：
在所述第三导电部上形成第二过孔，所述第二过孔贯穿所述第一介电层延伸至所述第一导电部的表面；
在所述第二导电层背离所述衬底基板的一侧形成第二介电层，所述第二介电层填充所述第二过孔；
在所述第二介电层上形成第一过孔，所述第一过孔贯穿所述第三导电部延伸至所述第一导电部的表面；且所述第一过孔在所述衬底基板的正投影位于所述第二过孔在所述衬底基板的正投影以内；
其中，所述第四导电部填充所述第一过孔。
根据本公开的一个方面，提供一种显示装置，其中，包括上述的阵列基板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一种像素驱动电路的电路结构示意图；
图2为相关技术中一种阵列基板的结构示意图；
图3为本公开阵列基板一种示例性实施例的结构示意图；
图4a为本公开阵列基板另一种示例性实施例的结构示意图；
图4b为图3的部分俯视图；
图4c为本公开阵列基板另一种示例性实施例的部分俯视图；
图4d为本公开阵列基板另一种示例性实施例的部分俯视图；
图5为本公开阵列基板另一种示例性实施例的结构示意图；
图6为本公开阵列基板另一种示例性实施例的结构示意图；
图7为本公开阵列基板另一种示例性实施例的结构示意图；
图8-14为本公开阵列基板制作方法一种示例性实施例的工艺流程图；
图15为第一有源层的结构版图；
图16为第一导电层的结构版图；
图17为第二有源层的结构版图；
图18为第一有源层、第一导电层、第二有源层的结合版图；
图19为第二导电层的结构版图；
图20为第一有源层、第一导电层、第二有源层、第二导电层的结合版图；
图21为第三导电层的结构版图；
图22为第一有源层、第一导电层、第二有源层、第二导电层、第三导电层的结合版图；
图23为第四导电层的结构版图；
图24为第一有源层、第一导电层、第二有源层、第二导电层、第三导电层、第四导电层的结合版图；
图25为阳极层的结构版图；
图26为第一有源层、第一导电层、第二有源层、第二导电层、第三导电层、第四导电层、阳极层的结合版图；
图27为图1像素驱动电路一种驱动方法中各节点的时序图；
图28为图9中第一导电层的局部版图结构；
图29为图21中第三导电层的部分版图结构；
图30为图22中的部分版图结构；
图31为图24中的部分版图结构。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成区分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成区分/等之外还可存在另外的要素/组成区分/等。
如图1所示，为本公开一种像素驱动电路的电路结构示意图。该像素驱动电路可以包括：驱动晶体管DT、第二晶体管T2、第一晶体管T1、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、电容C。其中，第二晶体管T2的第一极连接数据信号端Da、第二极连接驱动晶体管DT的第一极，栅极连接第一栅极驱动信号端G1；第四晶体管T4的第一极连接第一电源端VDD，第二极连接驱动晶体管DT的第一极，栅极连接使能信号端EM；驱动晶体管DT的栅极连接节点N，第二极连接第五晶体管T5的第一极；第一晶体管T1的第一极连接节点N，第二极连接驱动晶体管DT的第二极，栅极连接第二栅极驱动信号端G2；第五晶体管T5的第二极连接第六晶体管T6的第一极，栅极连接使能信号端EM，第六晶体管T6的第二极连接初始信号端Vinit，栅极连接第一复位信号端Re1；第三晶体管T3的第一极连接节点N，第二极连接初始信号端Vinit，栅极连接第二复位信号端Re2，电容C连接于第一电源端VDD和节点N之间。该像素驱动电路可以连接一发光单元OLED，用于驱动该发光单元OLED发光，发光单元OLED连接于第五晶体管T5第二极和第二电源端VSS之间。其中，第一晶体管T1和第三晶体管T3可以为N型金属氧化物晶体管，N型金属氧化物晶体管具有较小的漏电流，从而可以避免发光阶段节点N通过第一晶体管T1和第三晶体管T3漏电。同时，驱动晶体管DT、第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6可以为低温多晶体硅晶体管，低温多晶硅晶体管具有较高的载流子迁移率，从而有利于实现高分辨率、高反应速度、高像素密度、高开口率的显示装置。
如图2所示，为相关技术中一种阵列基板的结构示意图，该阵列基板可以包括图1所示的像素驱动电路。其中，该阵列基板可以包括衬底基板01、位于衬底基板01一侧的阻挡层02、位于阻挡层背离衬底基板01一侧的第二缓冲层03、位于第二缓冲层03背离衬底基板01一侧的第一有源层(包括第一有源部04)、位于第一有源层背离衬底基板一侧 的第一栅极绝缘层05、位于第一栅极绝缘层背离衬底基板一侧的第一栅极层(包括第一栅极部06)、位于第一栅极层背离衬底基板一侧的第一介电层07、位于第一介电层07背离衬底基板01一侧的第一缓冲层08、位于第一缓冲层08背离衬底基板01一侧的第二有源层(包括第二有源部09)、位于第二有源层背离衬底基板一侧的第二栅极绝缘层(包括第一绝缘部0101和第二绝缘部0102)、位于第二栅极绝缘层背离衬底基板一侧的第二栅极层(包括第二栅极部0112和第三栅极部0111)、位于第二栅极层背离衬底基板一侧的第二介电层012、位于第二介电层012背离衬底基板的一侧的第一源漏层(包括第一导电部013)、位于第一源漏层背离衬底基板一侧的钝化层014、位于钝化层014背离衬底基板一侧的第二源漏层(包括第二导电部015)。其中，第一栅极部06可以被配置为驱动晶体管的栅极，第二栅极部0112可以被配置为第一晶体管T1或第三晶体管T3的栅极。第一导电部013通过过孔与第一栅极部06连接。相关技术中，第一源漏层和第二源漏层之间的距离较小，从而第二导电部015可以形成电容C的第二电极，同时，第二导电部015可以覆盖第一导电部013以屏蔽其他信号对第一导电部013的噪声影响。然而，由于第一导电部013需要形成电容的电极，第一导电部013需要设计成较大的面积，从而在有限的平面空间内，第二导电部015不易完全覆盖第一导电部013，进而造成第一导电部013容易受到外部噪音干扰。此外，较大面积的第一导电部013还容易与其他结构形成较大的寄生电容，在该寄生电容耦合效应下，驱动晶体管栅极更容易受到外部噪音干扰。
基于此，本示例性实施例提供一种阵列基板，所述阵列基板包括像素驱动电路，该像素驱动电路可以如图1所示。其中，如图3所示，为本公开阵列基板一种示例性实施例的结构示意图。所述阵列基板可以包括：衬底基板1、第一导电层、第一介电层43、第一缓冲层41、第二导电层。第一导电层层叠设置于所述衬底基板1的一侧，所述第一导电层可以包括第一导电部13，所述第一导电部13可以被配置为所述驱动晶体管的栅极和所述电容C的第一电极；第一介电层43可以层叠设置于所述第一导电层背离所述衬底基板1的一侧；第一缓冲层41可以层叠设置于所述第一介电层43背离所述衬底基板1的一侧，所述第一缓冲层41上设置有开槽411，所述开槽411在所述衬底基板的正投影与所述第一导电部13在所述衬底基板的正投影至少部分重合；第二导电层层叠设置于所述第一缓冲层41背离所述衬底基板1的一侧，所述第二导电层可以包括第二导电部55和第三导电部721，所述第二导电部55被配置为所述第一晶体管的栅极；所述第三导电部721位于所述开槽411的底部，且所述第三导电部721在所述衬底基板1的正投影与所述第一导电部13在所述衬底基板的正投影至少部分重合，以形成所述电容的第二电极。其中，第二导电部55可以位于开槽411的外部，即第二导电部55在衬底基板的正投影与开槽411在衬底基板的正投影不相交。
需要说明的是，本示例性实施例中，同一结构膜层(例如，第一导电层、第二导电层)中的不同结构部可以通过一次构图工艺形成。关于本公开中的描述：“A层(任一结构膜层)位于B层(任一结构膜层)背离衬底基板的一侧”，其中，当B层是图案化结构膜 层时，A层不仅可以包括位于B层正上方的部位，还可以包括填充于B层镂空区域的部分，即A层可以包括位于B层正上方的X部和与X部通过一次构图工艺或一次沉积工艺形成的其他结构部，X部在衬底基板的正投影与B层在衬底基板的正投影重合。例如，如图3所示，第一介电层43不仅包括位于第一导电部13正上方的部位还包括通过同一沉积工艺形成的其他部位；第二导电层不仅可以包括位于第一缓冲层41正上方的第二导电部55，还可以包括与第二导电部55通过一次构图工艺形成的第三导电部721。
本示例性实施例提供的阵列基板在第一缓冲层41上设置开槽411，同时在开槽411的槽底设置第三导电部721。开槽411的设置减小了第三导电部721和第一导电部13之间的距离，从而可以使得第三导电部721和第一导电部13形成电容C的两电极。一方面，本示例性实施例不需要设计相关技术中极大面积的第一导电部013作为电容电极，从而降低了外部信号对驱动晶体管栅极的噪声影响；另一方面，本示例性实施例提供的阵列基板可以不设置相关技术中的第二源漏层，从而可以简化阵列基板的结构。
应该理解的是，在其他示例性实施例中，像素驱动电路还可以为其他结构，包括有LTPO像素驱动电路的阵列基板均可以采用上述的结构以形成相应像素驱动电路的电容。
本示例性实施例中，如图3所示，所述开槽411可以延伸至所述第一介电层43的表面，即开槽411的底部可以通过第一介电层43形成，所述第三导电部721可以位于所述第一介电层43背离所述衬底基板1的一侧。其中，位于第一导电部13和第三导电部721之间的第一介电层43可以作为平行板电容结构的介电层。应该理解的是，在其他示例性实施例中，开槽411还可以延伸至其他位置，例如，如图4a所示，为本公开阵列基板另一种示例性实施例的结构示意图。开槽411可以延伸至第一缓冲层41内，即开槽411的底部由部分第一缓冲层41形成。如图4b所示，为图3的部分俯视图，第三导电部721在衬底基板正投影的面积小于开槽411槽底在衬底基板正投影的面积，且第三导电部721位于开槽411的底部。应该理解的是，在其他示例性实施例中，第三导电部721在衬底基板正投影的面积还可以大于或等于开槽411槽底在衬底基板正投影的面积。如图4c所示，为本公开阵列基板另一种示例性实施例的部分俯视图，其中，第三导电部721在衬底基板正投影的面积大于开槽411槽底在衬底基板正投影的面积。如图4d所示，为本公开阵列基板另一种示例性实施例的部分俯视图，其中，第三导电部721在衬底基板正投影的面积等于开槽411槽底在衬底基板正投影的面积。
本示例性实施例中，如图5所示，为本公开阵列基板另一种示例性实施例的结构示意图。所述阵列基板还可以包括：第三导电层，所述第三导电层可以层叠设置于所述第二导电层背离所述衬底基板1的一侧，所述第三导电层可以包括第四导电部24，所述第四导电部24可以通过贯穿所述第三导电部721的第一过孔81与所述第一导电部13电连接，且与所述第三导电部721绝缘。其中，所述第四导电部24在所述衬底基板1的正投影可以位于所述第一导电部13在所述衬底基板1的正投影上，且所述第四导电部24在所述衬底基板1的正投影面积可以小于所述第一导电部13在所述衬底基板的正投影面积。
本示例性实施例将第四导电部24设置为较小的面积，一方面，该设置可以降低第四导电部24与其他导电结构(例如数据线、阳极层等)之间的寄生电容，从而可以降低其他结构对驱动晶体管栅极的噪声影响；另一方面，该设置可以便于通过屏蔽层对第四导电部24进行屏蔽，以进一步降低其他结构对驱动晶体管栅极的噪声影响。其中，所述第四导电部24在所述衬底基板1的正投影面积与所述第一导电部13在所述衬底基板正投影面积的比值可以为4％-25％。例如，所述第四导电部24在所述衬底基板1的正投影面积与所述第一导电部13在所述衬底基板正投影面积的比值可以为4％、8％、10％、12％、15％、20％、25％中的任意一种。
本示例性实施例中，所述第四导电部24在所述衬底基板1的正投影面积与所述第一过孔81在所述衬底基板的正投影面积的比值可以为1-2.5，例如，所述第四导电部24在所述衬底基板1的正投影面积与所述第一过孔81在所述衬底基板的正投影面积的比值可以为1、1.2、1.3、1.5、2.0、2.3、2.5等。应该理解的是，在其他示例性实施例中，由于工艺误差等原因，所述第四导电部24在所述衬底基板1的正投影面积还可以略小于第一过孔81在所述衬底基板的正投影面积。
本示例性实施例中，如图5所示，所述第三导电部721上可以形成有第二过孔82，所述第二过孔82可以贯穿所述第一介电层43延伸至所述第一导电部13的上表面，所述阵列基板还可以包括第二介电层42，第二介电层42可以层叠设置于所述第二导电层和所述第三导电层之间，且填充该第二过孔2。所述第一过孔81可以形成于第二介电层42上，所述第一过孔81可以贯穿所述第三导电部721延伸至所述第一导电部13的上表面，且所述第一过孔在81所述衬底基板1的正投影位于所述第二过孔82在所述衬底基板的正投影以内。该设置即可以实现第四导电部24与第一导电部13电连接，同时可以实现第四导电部24与第三导电部721绝缘。其中，关于上述描述“所述第一过孔在81所述衬底基板1的正投影位于所述第二过孔82在所述衬底基板的正投影以内”，可以理解为，所述第一过孔在81所述衬底基板1的正投影位于所述第二过孔82在所述衬底基板的正投影上，且第一过孔在81所述衬底基板1正投影的边沿与第二过孔82在所述衬底基板正投影的边沿间隔有距离。
本示例性实施例中，如图5所示，所述第三导电层还可以包括用于提供电源电压的电源线26，所述阵列基板还可以包括钝化层49、第一平坦层47、第四导电层。钝化层49可以层叠设置于第三导电层背离所述衬底基板1的一侧，第一平坦层47可以层叠设置于钝化层49背离所述衬底基板1的一侧，第四导电层可以层叠设置于第一平坦层47背离所述衬底基板1的一侧，所述第四导电层可以包括与所述电源线26连接的第五导电部35，所述第五导电部35在所述衬底基板的正投影可以覆盖所述第一导电部在所述衬底基板的正投影。其中，电源线26可以用于提供图1中的第一电源端VDD，由于第五导电部35连接一稳定电压，且所述第五导电部35在所述衬底基板的正投影可以覆盖所述第一导电部13在所述衬底基板的正投影，从而第五导电部35可以作为屏蔽层屏蔽其他信号对第一 导电部13的噪声影响。
本示例性实施例中，如图5所示，所述第二导电层还可以包括与所述第三导电部721连接的第六导电部722，所述第六导电部722可以通过过孔与所述电源线26连接，从而实现电容的第二电极连接第一电源端VDD。
需要说明的是，电源线26可以沿一个方向延伸，图5中电源线26出现在两个不同位置的原因是，图5是在阵列基板版图结构上沿一弯折线的剖视图，该弯折线位置将在下文关于阵列基板版图结构中进行具体说明。
本示例性实施例中，如图6所示，为本公开阵列基板另一种示例性实施例的结构示意图。所述阵列基板还可以包括：阻挡层48、第二缓冲层44、第一有源层、第二栅极绝缘层45、第二有源层、第一栅极绝缘层18。其中，衬底基板1、阻挡层48、第二缓冲层44、第一有源层、第二栅极绝缘层45、第一导电层、第一介电层43、第一缓冲层41、第二有源层、第一栅极绝缘层18、第二导电层、第二介电层42、第三导电层、钝化层49、第一平坦层47、第四导电层依次层叠设置。其中，所述第一有源层可以包括第一有源部53，所述第一有源部53可以被配置为所述驱动晶体管DT的沟道区。所述第二有源层可以包括第二有源部62，所述第二有源部62可以被配置为所述第一晶体管T1的沟道区。
本示例性实施例中，如图7所示，为本公开阵列基板另一种示例性实施例的结构示意图。所述阵列基板可以包括非显示区403，所述阵列基板上形成有位于非显示区403的条形槽121，所述条形槽121可以贯穿所述钝化层49、第二介电层42、第一缓冲层41、第一介电层43、第二栅极绝缘层45、第二缓冲层44、阻挡层48延伸至所述衬底基板1的表面。第一平坦层47可以填充所述条形槽121内。其中，所述第一平坦层47材料的可弯折性能可以强于钝化层49、第二介电层42、第一缓冲层41、第一介电层43、第二栅极绝缘层45、第二缓冲层44、阻挡层48材料的可弯折性能。例如，第一平坦层47可以采用有机材料，钝化层49、第二介电层42、第一缓冲层41、第一介电层43、第二栅极绝缘层45、第二缓冲层44、阻挡层48可以采用无机材料。条形槽121所在位置可以作为弯折区域，以将与阵列基板连接的芯片弯折到阵列基板的背面。如图7所示，第四导电层还可以包括信号线38，信号线38可以位于非显示区403。
本示例性实施例中，如图7所示，该阵列基板还可以包括第二平坦层19、阳极层20、像素限定层401，第二平坦层19层叠可以设置于所述第四导电层背离衬底基板1的一侧；阳极层20可以层叠设置于第二平坦层19背离衬底基板1的一侧；像素限定层401可以层叠设置于阳极层背离衬底基板1的一侧。阳极层20可以被配置为图1中发光单元的阳极；像素限定层401可以形成用于沉积发光单元的像素开口。此外，像素限定层401背离衬底基板一侧还可以设置支撑柱402，支撑柱402可以用于支撑掩膜版。
本示例性实施例中，衬底基板可以包括依次层叠设置的第一聚酰亚胺(PI)层、第一氧化硅(SiO)层、非晶硅层、第二聚酰亚胺(PI)层、第二氧化硅层。阻挡层48可以位于第二氧化硅层背离第一聚酰亚胺(PI)层的一侧。第一聚酰亚胺(PI)层和第二聚酰亚 胺(PI)层的厚度均可以为90000-110000±5％埃，例如90000埃、95000埃、110000埃；第一氧化硅层的厚度可以为5000-7000埃，例如5000埃、5500埃、7000埃；非晶硅层的厚度可以为40-60埃，例如，40埃、45埃、60埃；第二氧化硅层的厚度可以为4500-6500埃，例如4500埃、5000埃、6500埃。
本示例性实施例中，第二缓冲层44可以包括依次层叠设置的第一氮化硅(SiN)层和第三氧化硅层，第一氮化硅层可以位于第三氧化硅层和衬底基板之间。第一氮化硅层的厚度可以为900-1100埃，例如900埃、950埃、1100埃，；第三氧化硅层的厚度可以为2000-4000埃，例如，2000埃、2500埃、4000埃。第一有源层可以为多晶硅层，第一有源层的厚度可以为400-600埃，例如，400埃、500埃、600埃。第二栅极绝缘层45可以为氧化硅层，第二栅极绝缘层45的厚度可以为500-2000埃，例如，500埃、1500埃、2000埃。第一导电层、第二导电层均可以为钼层，第一导电层、第二导电层均的厚度可以为1500-2500埃，例如1500埃、2000埃、2500埃。第一介电层43可以为氮化硅层，第一介电层43的厚度可以为1200-1400埃，例如，1200埃、1250埃、1300埃、1350埃、1400埃。第一缓冲层41可以为氧化硅层，第一缓冲层41的厚度可以为3000-5000埃，例如，3000埃、3500埃、5000埃。第二有源层可以为氧化铟镓锌(IGZO)层，第二有源层的厚度可以为300-500埃，例如，300埃、350埃、500埃。第二栅极绝缘层45可以为氧化硅层，第二栅极绝缘层45的厚度可以为1000-2000埃，例如，1000埃、1500埃、2000埃。第三导电层可以包括依次层叠的第一钛层、铝层、第二钛层，第一钛层、第二钛层的厚度均可以为300-700埃，例如300埃、450埃、700埃，铝层的厚度均可以为4500-6500埃，例如，4500埃、5000埃、6500埃。第二平坦层19可以为聚酰亚胺(PI)层，第二平坦层19的厚度可以为10000-20000埃，例如，10000埃、16000埃、20000埃。像素限定层401可以为聚酰亚胺(PI)层，像素限定层401的厚度可以为10000-20000埃，例如，10000埃、16000埃、20000埃。支撑柱402可以为聚酰亚胺(PI)层，支撑柱402的厚度可以为10000-20000埃，例如，10000埃、16000埃、20000埃。阳极层20可以包括依次层叠设置的第一氧化铟锡层、银层、第二氧化铟锡层，第一氧化铟锡层、第二氧化铟锡层的厚度可以为50-100埃，例如50埃、80埃、100埃，银层的厚度可以为500-1500埃，例如，500埃、800埃、1500埃。
应该理解的是，上述结构膜层还可以为其他材料和厚度，例如，介电层、钝化层的材料还可以为氮化硅或透明的有机树脂等材料，平坦层的材料还可以为透明聚酰亚胺(CPI)、聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)等材料。导电层的材料还可以为铜、钼等金属材料。
本公开一种示例性实施例还提供一种阵列基板制作方法，所述阵列基板可以包括像素驱动电路，所述像素驱动电路可以包括P型驱动晶体管、N型第一晶体管、电容，所述第一晶体管的第一极连接所述驱动晶体管的栅极，所述电容的第一电极连接所述驱动晶体管的栅极，所述阵列基板制作方法包括：
步骤S1：形成衬底基板；
步骤S2：在所述衬底基板一侧形成第一导电层，所述第一导电层包括第一导电部，所述第一导电部被配置为所述驱动晶体管的栅极和所述电容的第一电极；
步骤S3：在所述第一导电层背离所述衬底基板的一侧形成第一介电层；
在所述第一介电层背离所述衬底基板的一侧形成第一缓冲层，所述第一缓冲层上设置有开槽，所述开槽在所述衬底基板的正投影与所述第一导电部在所述衬底基板的正投影至少部分重合；
步骤S4：在所述第一缓冲层背离所述第一导电层一侧形成第二导电层，所述第二导电层包括：
第二导电部，所述第二导电部被配置为所述第一晶体管的栅极；
第三导电部，所述第三导电部位于所述开槽的底部，且所述第三导电部在所述衬底基板的正投影与所述第一导电部在所述衬底基板的正投影至少部分重合，以形成所述电容的第二电极。
如图8所示，为本公开阵列基板制作方法一种示例性实施例的工艺流程图。该阵列基板制作方法还可以包括：在衬底基板1上依次形成：阻挡层48、第二缓冲层44、第一有源层、第二栅极绝缘层45、第一导电层、第一介电层43、第一缓冲材料层041、第二有源层、第一栅极绝缘材料层018。其中，第一有源层可以包括有第一有源部53，第一导电层可以包括被配置为驱动晶体管栅极的第一导电部13，第二有源层可以包括有第二有源部62。
如图9、10所示，为本公开阵列基板制作方法一种示例性实施例的工艺流程图。如图9所示，该阵列基板制作方法还可以包括通过构图工艺对第一缓冲材料层041和第一栅极绝缘材料层018进行刻蚀以形成所述开槽411，刻蚀后的第一缓冲材料层041形成第一缓冲层。其中，所述开槽411可以延伸至所述第一介电层43的第一表面，所述第三导电部可以位于所述第一介电层的第一表面上，所述第一表面为所述第一介电层面向所述第一缓冲层一侧的表面。如图10所示，该阵列基板制作方法还可以包括通过构图工艺形成第二导电层，第二导电层可以包括被配置为第一晶体管栅极的第二导电部55和第三导电部721，第三导电部721可以位于开槽411底部。其中，在通过构图工艺形成第二导电层时，还可以同时对第一栅极绝缘材料层018进行图案化处理，以形成第一栅极绝缘层18。应该理解的是，在其他示例性实施例中，该阵列基板制作方法还可以通过构图工艺仅对第一缓冲材料层041和第一栅极绝缘材料层018中的任一层进行刻蚀以形成所述开槽411。
如图11、12、13、14所示，为本公开阵列基板制作方法一种示例性实施例的工艺流程图。如图11所示，该阵列基板制作方法还可以包括：在所述第三导电部上形成第二过孔82，所述第二过孔82可以贯穿所述第一介电层43延伸至所述第一导电部13的表面。如图12所示，在所述第二导电层背离所述衬底基板1的一侧形成第二介电层42，所述第二介电层42填充所述第二过孔82。如图13所示，在所述第二介电层42上形成所述第一 过孔81，所述第一过孔81贯穿所述第三导电部721延伸至所述第一导电部13的表面；且所述第一过孔81在所述衬底基板1的正投影位于所述第二过孔82在所述衬底基板的正投影以内。如图14所示，该阵列基板制作方法还可以包括：在所述第二介电层42背离所述衬底基板1的一侧形成第三导电层，所述第三导电层可以包括第四导电部24，所述第四导电部24可以通过第一过孔81与所述第一导电部13电连接。其中，所述第四导电部24在所述衬底基板1的正投影可以位于所述第一导电部13在所述衬底基板1的正投影上，且所述第四导电部24在所述衬底基板的正投影面积可以小于所述第一导电部13在所述衬底基板的正投影面积。
本示例性实施例将第四导电部24设置为较小的面积，一方面，该设置降低了第四导电部24与其他导电结构(例如数据线、阳极层等)之间的寄生电容，从而降低了其他导电结构对驱动晶体管栅极的噪声影响；另一方面，该设置便于通过屏蔽层对第四导电部24进行屏蔽，以进一步降低其他导电结构对驱动晶体管栅极的噪声影响。其中，所述第四导电部24在所述衬底基板1的正投影面积可以是所述第一导电部13在所述衬底基板正投影面积的4％-25％。例如，所述第四导电部24在所述衬底基板1的正投影面积与所述第一导电部13在所述衬底基板正投影面积的比值可以为4％、8％、10％、12％、15％、20％、25％中的任意一种。
本示例性实施例中，所述第四导电部24在所述衬底基板1的正投影面积与所述第一过孔81在所述衬底基板的正投影面积的比值可以为1-2.5，例如，所述第四导电部24在所述衬底基板1的正投影面积与所述第一过孔81在所述衬底基板的正投影面积的比值可以为1、1.2、1.3、1.5、2.0、2.3、2.5等。
本示例性实施例中，该阵列基板制作方法还可以包括：在第三导电层背离衬底基板一侧依次形成第二介电层、第三导电层、钝化层、第一平坦层、第四导电层、第二平坦层、阳极层、像素定义层，以形成图7所示的阵列基板结构。
以下本示例性实施例对阵列基板的整体结构进行详细说明。
如图15-26所示，图15为第一有源层的结构版图；图16为第一导电层的结构版图；图17为第二有源层的结构版图；图18为第一有源层、第一导电层、第二有源层的结合版图；图19为第二导电层的结构版图；图20为第一有源层、第一导电层、第二有源层、第二导电层的结合版图；图21为第三导电层的结构版图；图22为第一有源层、第一导电层、第二有源层、第二导电层、第三导电层的结合版图；图23为第四导电层的结构版图；图24为第一有源层、第一导电层、第二有源层、第二导电层、第三导电层、第四导电层的结合版图；图25为阳极层的结构版图；图26为第一有源层、第一导电层、第二有源层、第二导电层、第三导电层、第四导电层、阳极层的结合版图。
如图15、18所示，第一有源层可以包括上述的第一有源部53，此外，第一有源层还可以包括：有沿第一方向Y1延伸的第三有源部51和第四有源部52，第三有源部51和第四有源部52可以沿第二方向X间隔分布。第一有源部53可以连接于第三有源部51和第 四有源部52之间。其中，第三有源部51可以包括有第一子有源部511和第二子有源部514，第四有源部52可以包括有第三子有源部525和第四子有源部526。其中，第一有源部53可以被配置为驱动晶体管DT的沟道区；第一子有源部511可以被配置为第二晶体管T2的沟道区；第二子有源部514可以被配置为第四晶体管T4的沟道区；第三子有源部525可以被配置为第五晶体管T5的沟道区；第四子有源部526可以被配置为第六晶体管T6的沟道区。本示例性实施例中，第一有源层可以为多晶硅材料，相应的，所述驱动晶体管DT、第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6可以为P型低温多晶硅晶体管。其中，第三导电部721在衬底基板的正投影与第四有源部52在衬底基板的正投影可以不重合，从而避免第三导电部721与第四有源部52产生不必要的寄生电容。
如图18、16所示，第一导电层可以包括上述的第一导电部13，此外，第一导电层还可以包括第一栅线11、第二栅线12、第三栅线14、第五栅线15、第六栅线16。第一栅线11可以位于所述第一导电部13的一侧；第二栅线12可以位于所述第一栅线11远离所述第一导电部13的一侧；第三栅线14可以位于所述第二栅线12远离所述第一导电部13的一侧；第五栅线15位于第一导电部13远离第一栅线的一侧；第六栅线16位于第五栅线15远离第一导电部13的一侧。第一栅线11、第二栅线12、第三栅线14、第五栅线15、第六栅线16均可以沿第二方向X延伸。第一栅线11可以用于提供图1中的第一栅极驱动信号端G1，第一栅线11可以包括有第一栅极部113；第二栅线12可以用于提供图1中的第二栅极驱动信号端G2，第二栅线12可以包括第二栅极部125；第三栅线14可以作为第二复位信号线用于提供图1中的第二复位信号端Re2，第三栅线14可以包括第三栅极部143；第五栅线15可以作为使能信号线用于提供图1中的使能信号端EM，第五栅线15可以包括第四栅极部154和第五栅极部155；第六栅线16可以作为第一复位信号线用于提供图1中的第一复位信号端Re1，第六栅线16包括第六栅极部166。其中，第一栅极部113可以被配置为第二晶体管T2的栅极，第二栅极部125可以被配置为第一晶体管T1的第一栅极；第三栅极部143可以被配置为第三晶体管T3的第一栅极；第四栅极部154可以被配置为第四晶体管T4的栅极；第五栅极部155可以被配置为第五晶体管T5的栅极；第六栅极部166可以被配置为第六晶体管T6的栅极。
如图18、17所示，第二有源层可以包括沿第一方向Y1延伸的多个有源部6，多个有源部6可以沿第二方向X间隔分布，多个有源部6与多个像素驱动电路一一对应设置。如图10所示，有源部6可以包括上述的第二有源部62和第五有源部63，其中，第二有源部62可以形成第一晶体管T1的沟道区，第五有源部63可以形成第三晶体管T3的沟道区。
如图19、20所示，第二导电层可以包括上述的第二导电部55、第三导电部721、第六导电部722。第二导电层还可以包括：第四栅线74、第五栅线75、第六栅线76。第四栅线74、第五栅线75、第六栅线76均可沿第二方向X延伸。第四栅线74可以在显示区周边的走线区与第二栅线12通过过孔连接；第五栅线75可以在显示区周边的走线区与第 三栅线14通过过孔连接。第四栅线74可以包括上述的第二导电部55，第二导电部55可以被配置为第一晶体管端第二栅极。第五栅线75可以包括第七栅极部753，第七栅极部753可以形成第三晶体管的第二栅极。第六栅线76可以作为初始信号线用于提供图1中的初始信号端Vinit。第三导电部721在衬底基板的正投影可以覆盖第一导电部13在衬底基板的正投影。其中，第六导电部722可以通过过孔与第三导电层中的电源线连接。
如图21、22所示，第三导电层可以包括上述的电源线26、第四导电部24，此外，第三导电层还可以包括：第一导电线21、第七导电部23、第一连接部27、第二连接部28、第三连接部29、第四连接部201。第一连接部27可以通过过孔202与第四有源部52连接，以连接第六晶体管的第二极，第一连接部27还通过过孔203与第六栅线76连接，从而可以通过第六栅线76向第六晶体管的第二极提供初始信号端。此外，第一连接部27还可以通过过孔与204与下一行像素驱动电路中的有源部6连接，以通过该第六栅线76向下一行像素驱动电路中的第三晶体管提供初始信号端。第二连接部28可以通过过孔205与第四有源部52连接，以连接第五晶体管的第二极。第三连接部29通过过孔206连接有源部6，以连接第一晶体管的第二极，第三连接部29可以通过过孔207连接第四有源部52，以连接驱动晶体管的第二极，从而使得第一晶体管的第二极连接驱动晶体管的第二极。第四连接部201可以通过过孔208与第三有源部51连接，以连接第二晶体管的第一极。
如图23、24所示，第四导电层可以包括上述的第五导电部35，此外，第四导电层还可以包括数据线31、第五连接部32。其中，数据线31可以通过过孔33与第四连接部201连接，以连接第二晶体管T2的第一极。第五导电部35可以通过过孔34与电源线26连接。第五连接部32可以通过过孔36与第二连接部28连接，以与第五晶体管的第二极连接。如图24所示，沿图中虚线A可以剖切出如图5所示的剖视图。需要说明的是，图5中省略了部分结构。
如图25、26所示，阳极层可以包括第一阳极部87、第二阳极部88、第三阳极部83，第一阳极部87可以通过过孔84连接第五连接部32，以以与第五晶体管的第二极连接；第二阳极部88可以通过过孔85连接另一像素驱动电路中的第五连接部32；第三阳极部83可以通过过孔86连接另一像素驱动电路中的第五连接部32。第一阳极部87上可以形成G发光单元；第二阳极部88上可以形成R发光单元；第三阳极部83上可以形成B发光单元。
如图27所示，为图1像素驱动电路一种驱动方法中各节点的时序图。其中，G1表示第一栅极驱动信号端G1的时序，G2表示第二栅极驱动信号端G2的时序，R表示第一复位信号端Re1的时序，Re2表示第二复位信号端Re2的时序，N表示节点N的时序，EM表示使能信号端EM的时序，Da表示数据信号端Da的时序。该像素驱动电路的驱动方法可以包括复位阶段t1、补偿阶段t2，发光阶段t3。在复位阶段t1：第一复位信号端Re1输出低电平信号，第二复位信号端Re2输出高电平信号，第三晶体管T3、第六晶体管T6导通，初始信号端Vinit向节点N，第五晶体管T5的第二极输入初始化信号。在补偿阶段 t2：第一栅极驱动信号端G1输出低电平信号，第二栅极驱动信号端G2输出高电平信号，第二晶体管T2、第一晶体管T1导通，同时数据信号端Da输出驱动信号以向节点N写入电压Vdata+Vth，其中Vdata为驱动信号的电压，Vth为驱动晶体管DT的阈值电压。发光阶段t3：使能信号端EM输出低电平信号，第四晶体管T4、第五晶体管T5导通，驱动晶体管DT在电容C存储的电压Vdata+Vth作用下发光。根据驱动晶体管输出电流公式I＝(μWCox/2L)(Vgs-Vth)2，其中，μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电压。本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth)2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。
然而，由于第一晶体管T1的栅极和第一极之间存在寄生电容，如图2所示，在补偿阶段t2结束后，第二栅极驱动信号端G2由高电平降低为低电平，即第一晶体管T1的栅极由高电平降低为低电平，第一晶体管T1第一极的电压会在电容耦合效应下降低，与第一晶体管T1第一极连接的节点N电压也会相应降低。根据上述驱动晶体管输出电流公式可知，节点N(即驱动晶体管栅极)电压下降会影响驱动晶体管的输出电流。为了保证驱动晶体管输出正常所需的驱动电流，源极驱动电路需要通过数据线向数据信号端提供更高电压值的数据信号。通过仿真，上述像素驱动电路在显示灰阶0时，源极驱动电路向数据线提供的电压需要大于6.3V，但是现有的源极驱动电路向数据线提供的最大电压为6V，从而无法满足正常显示需求。
本示例性实施例中，如图16所示，本示例性实施例提供的阵列基板将第二栅线12设置于第一栅线11远离第一导电部13的一侧。一方面，该设置增加了第二栅线12和第一导电部13之间距离，减小了第二栅线12和第一导电部13之间的侧向电容，从而降低了第一晶体管栅极在补偿阶段结束后对驱动晶体管栅极的下拉作用；另一方面，第一栅线11和第一导电部13可以形成侧向电容，如图2所示，第二晶体管在补偿阶段t2结束后，从低电平跳变到高电平，从而第二晶体管的栅极可以对驱动晶体管的栅极产生上拉作用，本示例性实施例提供的阵列基板减小了第一栅线11和第一导电部13之间距离，增加了第一栅线11和第一导电部13之间的侧向电容，从而可以增强第二晶体管栅极对驱动晶体管栅极的上拉作用；再一方面，第一栅线11位于第一导电部13和第二栅线12之间，第一栅线11可以对第二栅线12起到一定的屏蔽作用，从而进一步降低第一晶体管栅极对驱动晶体管栅极的下拉作用。本示例性实施例中，第一栅线11对第一导电部13的上拉作用强于第二栅线12对第一导电部13的下拉作用，从而该阵列基板可以在一定程度上抵消上述中第一晶体管对驱动晶体管栅极的下拉作用。
如图28所示，为图9中第一导电层的局部版图结构。所述第一栅线11可以位于所述第一导电部13在第一方向Y1上的一侧，且沿第二方向X延伸，所述第一方向Y1可以和所述第二方向X相交，例如，所述第一方向Y1和所述第二方向X可以垂直。所述第一栅 线11可以包括：第一延伸部111、第二延伸部112，所述第一延伸部111在所述衬底基板的正投影与至少部分所述第一导电部13在所述衬底基板的正投影在所述第一方向Y1上相对；所述第二延伸部112在所述衬底基板的正投影与所述第一导电部13在所述衬底基板的正投影在所述第一方向Y1相错。第一方向和第二方向均可以为与衬底基板所在平面平行的方向。其中，“所述第一延伸部111在所述衬底基板的正投影与至少部分所述第一导电部13在所述衬底基板的正投影在所述第一方向Y1上相对”可以理解为，所述第一延伸部111在所述衬底基板的正投影沿第一方向Y1和第三方向Y2无限移动所覆盖的区域与至少部分所述第一导电部13在所述衬底基板的正投影沿第一方向Y1和第三方向Y2无限移动所覆盖的区域完全重合，其中，第一方向Y1和第三方向Y2相反。“所述第二延伸部112在所述衬底基板的正投影与所述第一导电部13在所述衬底基板的正投影在所述第一方向Y1相错”可以理解为，所述第二延伸部112在所述衬底基板的正投影沿第一方向Y1和第三方向Y2无限移动所覆盖的区域与所述第一导电部13在所述衬底基板的正投影沿第一方向Y1和第三方向Y2无限移动所覆盖的区域不相交，同样的，第一方向Y1和第三方向Y2相反。
本示例性实施例中，所述第一延伸部111在衬底基板的正投影与所述第一导电部13在衬底基板的正投影在所述第三方向Y2上的距离S1可以小于所述第二延伸部112在衬底基板的正投影与所述第一导电部13在衬底基板的正投影在所述第三方向Y2上的距离S2。如图28所示，所述第一延伸部111在衬底基板的正投影与所述第一导电部13在衬底基板的正投影在所述第三方向Y2上的距离S1可以指，第一延伸部111在衬底基板的正投影面向第一导电部13一侧的边沿与第一导电部13在衬底基板的正投影面向第一延伸部111一侧边沿在第三方向Y2上的距离。所述第二延伸部112在衬底基板的正投影与所述第一导电部13在衬底基板的正投影在所述第三方向Y2上的距离S2可以指，第二延伸部112在衬底基板的正投影面向第一导电部13一侧的边沿与第一导电部13在衬底基板的正投影面向第二延伸部112一侧边沿所在直线在第三方向Y2上的距离。该设置缩小了第一延伸部111与第一导电部13在第三方向上的距离，增加了第一延伸部111与第一导电部13的侧向电容，从而可以进一步增加了第一栅线对驱动晶体管栅极的上拉作用。
本示例性实施例中，如图28所示，所述第一延伸部111在衬底基板的正投影在所述第二方向X上的尺寸可以等于所述第一导电部13在衬底基板的正投影在所述第二方向X的尺寸。该设置可以极大的增加第一延伸部111和第一导电部13形成的侧向电容的电容值，以进一步增加了第一栅线对驱动晶体管栅极的上拉作用。
本示例性实施例中，至少部分所述第二延伸部112可以被配置为所述第二晶体管的栅极。由于第二延伸部112在衬底基板的正投影在第三方向Y2上与第一导电部13在衬底基板的正投影距离较大，该设计可以充分预留出设置第二晶体管的空间。
本示例性实施例中，如图29、30所示，图29为图21中第三导电层的部分版图结构，图30为图22中的部分版图结构。所述第三导电层可以包括：上述的第四导电部24、第 七导电部23、第一导电线21，所述第四导电部24通过第一过孔81与所述第一导电部13电连接；第七导电部23可以被配置为所述第一晶体管的第一极，所述第一栅线11在所述衬底基板的正投影可以位于所述第四导电部24在所述衬底基板的正投影和第七导电部23在所述衬底基板的正投影之间；第一导电线21连接于所述第四导电部24和所述第七导电部23之间，以使第一晶体管的第一极连接驱动晶体管的栅极，第一导电线21可以沿所述第一方向Y1延伸，所述第一导电线21在所述衬底基板的正投影与所述第一栅线11在所述衬底基板的正投影相交。其中，由于所述第一导电线21在所述衬底基板的正投影与所述第一栅线11在所述衬底基板的正投影相交，因此，部分第一导电线21可以与部分第一栅线11形成平行板电容结构。利用该平行板电容结构的耦合效应，第一栅线11可以在像素驱动电路补偿阶段结束后对第一导电线21起到上拉作用，由于第一导电线21与第一导电部13电连接，即该设置可以进一步增强第一栅线11对第一导电部13的上拉作用。
本示例性实施例中，如图28、29、30所示，所述第二栅线12在所述衬底基板的正投影可以位于所述第一栅线11在所述衬底基板的正投影和第七导电部23在所述衬底基板的正投影之间；所述第二栅线12可以包括沿所述第二方向X依次交替连接的第三延伸部123和第四延伸部124，其中，所述第三延伸部123在衬底基板的正投影在所述第一方向Y1上的尺寸可以小于所述第四延伸部124在衬底基板的正投影在所述第一方向Y1上的尺寸。所述第一导电线21在所述衬底基板的正投影可以与所述第三延伸部123在所述衬底基板的正投影相交。部分第三延伸部123可以与部分第一导电线21形成平行板电容结构。基于该平行板电容结构的耦合效应，第三延伸部123可以在像素驱动电路补偿阶段结束后对第一导电线21产生下拉作用，由于第一导电线21与第一导电部13电连接，第三延伸部123会对第一导电部13产生下拉作用。本示例性实施例中，所述第三延伸部123在衬底基板的正投影在所述第一方向Y1上的尺寸小于所述第四延伸部124在衬底基板的正投影在所述第一方向Y1上的尺寸，即本示例性实施例缩小了第三延伸部123在所述第一方向Y1上的尺寸，从而减小了第三延伸部123和第一导电线21所形成平行板电容结构的电极面积，根据平行板电容器的电容计算公可知，平行板电容结构的电容与其电极面积成正比，即该设置减小了第三延伸部123和第一导电线21所形成平行板电容结构的电容，从而降低了第三延伸部123对第一导电部13的下拉作用。其中，部分所述第四延伸部124可以被配置为所述第一晶体管的第一栅极。第一晶体管的沟道区可以沿第一方向Y1延伸，从而第一晶体管的沟道区可以具有较大的长度，以降低第一晶体管的漏电流。
本示例性实施例中，如图30所示，电源线26在衬底基板的正投影可以与第三延伸部123在衬底基板的正投影相交，该设置可以减小电源线26与第二栅线的交叠面积，从而减小电源线26在电压波动时对第二栅线12造成的电容耦合效应。
如图30、31所示，图31为图24中的部分版图结构。所述电源线26可以包括第五延伸部265，所述第五延伸部265在所述衬底基板的正投影与至少部分所述第一导电部13在所述衬底基板的正投影在所述第二方向X上相对，“所述第五延伸部265在所述衬底基 板的正投影与至少部分所述第一导电部13在所述衬底基板的正投影在所述第二方向X上相对”可以理解为，所述第五延伸部265在所述衬底基板的正投影沿第二方向和第二方向反方向无限移动所覆盖的区域与至少部分所述第一导电部13在所述衬底基板的正投影沿第二方向和第二方向反方向无限移动所覆盖的区域完全重合。且部分所述数据线31在所述衬底基板的正投影可以位于所述第五延伸部265在所述衬底基板的正投影上。其中，由于第五延伸部265层叠设置于数据线31和第一导电部13之间，且第五延伸部265接收一稳定电压，从而第五延伸部265可以作为屏蔽层降低数据线31和第一导电部13之间的耦合电容，进而降低数据线31对第一导电部13的耦合效应。其中，第五导电部35可以通过过孔34连接所述电源线26。
本示例性实施例中，当R像素单元、G像素单元、B像素单元中驱动晶体管沟道区的宽长比相同时，R像素单元、G像素单元、B像素单元具有不同的驱动电压区间(即最大亮度下数据信号电压与最低亮度下数据信号电压之差)。源极驱动电路需要向R像素单元、G像素单元、B像素单元提供不同驱动电压区间的数据信号，源极驱动电路需要在不同驱动电压区间之间切换，因而源极驱动电路需要消耗较大功率。本示例性实施例中，R像素驱动电路中驱动晶体管沟道区的宽长比、G像素驱动电路中驱动晶体管沟道区的宽长比以及G像素驱动电路中驱动晶体管沟道区的宽长比可以不全相同。即在R像素驱动电路、G像素驱动电路、B像素驱动电路中，至少有一种像素驱动电路中驱动晶体管沟道区的宽长比不等于其他种像素驱动电路中驱动晶体管沟道区的宽长比。例如，R像素驱动电路中驱动晶体管沟道区的宽长比可以为3.5/40，B像素驱动电路中驱动晶体管沟道区的宽长比可以为3.5/25。具体的，如图15所示，B像素单元中驱动晶体管沟道区为“Z”型，R像素单元中驱动晶体管沟道区和G像素单元中驱动晶体管沟道区为“S”型。根据仿真可以得出，相较于R像素驱动电路中驱动晶体管的沟道区、G像素驱动电路中驱动晶体管的沟道区、R像素驱动电路中驱动晶体管的沟道区具有相同的宽长比，该设置可以降低R像素单元、G像素单元、B像素单元之间驱动电压的差异，从而可以降低源极驱动电路的功率消耗。
本示例性实施例还提供一种显示装置，其中，所述显示装置可以包括上述的阵列基板。该显示装置可以为手机、平板电脑、电视等显示装置。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性远离并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (19)

  1. 一种阵列基板，所述阵列基板包括像素驱动电路，所述像素驱动电路包括P型驱动晶体管、N型第一晶体管、电容，所述第一晶体管的第一极连接所述驱动晶体管的栅极，所述电容的第一电极连接所述驱动晶体管的栅极，其中，所述阵列基板还包括：
    衬底基板；
    第一导电层，层叠设置于所述衬底基板的一侧，所述第一导电层包括第一导电部，所述第一导电部被配置为所述驱动晶体管的栅极和所述电容的第一电极；
    第一介电层，层叠设置于所述第一导电层背离所述衬底基板的一侧；
    第一缓冲层，层叠设置于所述第一介电层背离所述衬底基板的一侧，所述第一缓冲层上设置有开槽，所述开槽在所述衬底基板的正投影与所述第一导电部在所述衬底基板的正投影至少部分重合；
    第二导电层，层叠设置于所述第一缓冲层背离所述衬底基板的一侧，所述第二导电层包括：
    第二导电部，所述第二导电部被配置为所述第一晶体管的栅极；
    第三导电部，所述第三导电部至少部分位于所述开槽的底部，且所述第三导电部在所述衬底基板的正投影与所述第一导电部在所述衬底基板的正投影至少部分重合，以形成所述电容的第二电极。
  2. 根据权利要求1所述的阵列基板，其中，所述开槽延伸至所述第一介电层的表面，所述第三导电部位于所述第一介电层背离所述衬底基板的一侧。
  3. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括：
    第三导电层，所述第三导电层层叠设置于所述第二导电层背离所述衬底基板的一侧，包括第四导电部，所述第四导电部通过贯穿所述第三导电部的第一过孔与所述第一导电部电连接；
    其中，所述第四导电部在所述衬底基板的正投影位于所述第一导电部在所述衬底基板的正投影上，且所述第四导电部在所述衬底基板的正投影面积小于所述第一导电部在所述衬底基板的正投影面积。
  4. 根据权利要求3所述的阵列基板，其中，所述第四导电部在所述衬底基板的正投影面积与所述第一过孔在所述衬底基板的正投影面积的比值为1-1.5。
  5. 根据权利要求3所述的阵列基板，其中，所述第四导电部在所述衬底基板的正投影面积与所述第一导电部在所述衬底基板的正投影面积的比值为8％-15％。
  6. 根据权利要求3所述的阵列基板，其中，所述第三导电部上形成有第二过 孔，所述第二过孔贯穿所述第一介电层延伸至所述第一导电部的表面，所述阵列基板还包括：
    第二介电层，层叠设置于所述第二导电层和所述第三导电层之间，且填充所述第二过孔，所述第二介电层上形成有所述第一过孔，所述第一过孔贯穿所述第三导电部延伸至所述第一导电部的表面；且所述第一过孔在所述衬底基板的正投影位于所述第二过孔在所述衬底基板的正投影以内。
  7. 根据权利要求3所述的阵列基板，其中，所述第三导电层还包括用于提供电源电压的电源线，所述阵列基板还包括：
    第四导电层，层叠设置于所述第三导电层背离所述衬底基板的一侧，所述第四导电层包括与所述电源线连接的第五导电部，所述第五导电部在所述衬底基板的正投影覆盖所述第一导电部在所述衬底基板的正投影。
  8. 根据权利要求7所述的阵列基板，其中，所述第二导电层还包括与所述第三导电部连接的第六导电部，所述第六导电部通过过孔与所述电源线连接。
  9. 根据权利要求3所述的阵列基板，其中，所述阵列基板还包括：
    阻挡层，层叠设置于所述衬底基板的一侧；
    第二缓冲层，层叠设置于所述阻挡层背离衬底基板的一侧；
    第一有源层，层叠设置于所述第二缓冲层背离所述衬底基板的一侧，所述第一有源层包括第一有源部，所述第一有源部被配置为所述驱动晶体管的沟道区；
    第二栅极绝缘层，层叠设置于所述第一有源层背离所述衬底基板的一侧，其中，所述第一导电层层叠设置于所述第二栅极绝缘层背离所述衬底基板的一侧；
    第二有源层，层叠设置于所述第一缓冲层背离所述衬底基板的一侧，包括第二有源部，所述第二有源部被配置为所述第一晶体管的沟道区；
    第一栅极绝缘层，层叠设置于所述第二有源层背离所述衬底基板的一侧，其中，第二导电层层叠设置于所述第一栅极绝缘层背离所述衬底基板的一侧；
    第二介电层，层叠设置于所述第二导电层背离所述衬底基板的一侧，
    其中，第三导电层层叠设置于所述第二介电层背离所述衬底基板的一侧；
    钝化层，层叠设置于所述第三导电层背离所述衬底基板的一侧。
  10. 根据权利要求9所述的阵列基板，其中，所述阵列基板包括非显示区，所述阵列基板上形成有位于非显示区的条形槽，所述条形槽贯穿所述钝化层、第二介电层、第一缓冲层、第一介电层、第二栅极绝缘层、第二缓冲层、阻挡层延伸至所述衬底基板的表面；
    所述阵列基板还包括：
    第一平坦层，层叠设置于所述钝化层背离所述衬底基板的一侧，且填充所述条形槽；
    其中，所述第一平坦层材料的可弯折性能强于所述钝化层、第二介电层、第一缓冲层、第一介电层、第二缓冲层、阻挡层材料的可弯折性能。
  11. 根据权利要求1所述的阵列基板，其中，所述第一介电层在层叠方向上的厚度为1200-1400埃。
  12. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括：使能信号线、初始信号线、阳极层、第一复位信号线、第二复位信号线、电源线、第一栅线、第二栅线、数据线，所述第一晶体管的第二极连接所述驱动晶体管的第二极，栅极连接所述第二栅线，所述像素驱动电路还包括：
    第二晶体管，第一极连接所述数据线，第二极连接所述驱动晶体管的第一极，栅极连接所述第一栅线；
    第三晶体管，第一极连接所述驱动晶体管的栅极，第二极连接所述初始信号线，栅极连接所述第二复位信号线；
    第四晶体管，第一极连接所述电源线，第二极连接所述驱动晶体管的第一极，栅极连接所述使能信号线；
    第五晶体管，第一极连接所述驱动晶体管的第二极，第二极连接所述阳极层，栅极连接所述使能信号线；
    第六晶体管，第一极连接所述第五晶体管的第二极，第二极连接所述初始信号线，栅极连接所述第一复位信号线。
  13. 根据权利要求12所述的阵列基板，其中，
    所述驱动晶体管、第二晶体管、第四晶体管、第五晶体管、第六晶体管为P型低温多晶硅晶体管。
  14. 根据权利要求12所述的阵列基板，其中，所述第一晶体管、第三晶体管为N型金属氧化物晶体管。
  15. 一种阵列基板制作方法，其中，所述阵列基板包括像素驱动电路，所述像素驱动电路包括P型驱动晶体管、N型第一晶体管、电容，所述第一晶体管的第一极连接所述驱动晶体管的栅极，所述电容的第一电极连接所述驱动晶体管的栅极，所述阵列基板制作方法包括：
    形成衬底基板；
    在所述衬底基板一侧形成第一导电层，所述第一导电层包括第一导电部，所述第一导电部被配置为所述驱动晶体管的栅极和所述电容的第一电极；
    在所述第一导电层背离所述衬底基板的一侧形成第一介电层；
    在所述第一介电层背离所述衬底基板的一侧形成第一缓冲层，所述第一缓冲层上设置有开槽，所述开槽在所述衬底基板的正投影与所述第一导电部在所述衬底基板的正投影至少部分重合；
    在所述第一缓冲层背离所述第一导电层一侧形成第二导电层，所述第二导电层包括：
    第二导电部，所述第二导电部被配置为所述第一晶体管的栅极；
    第三导电部，所述第三导电部位于所述开槽的底部，且所述第三导电部在所述衬底基板的正投影与所述第一导电部在所述衬底基板的正投影至少部分重合，以形成所述电容的第二电极。
  16. 根据权利要求15所述的阵列基板制作方法，其中，在所述第一介电层背离所述第一导电层一侧形成第一缓冲层，包括：
    在所述第一介电层背离所述衬底基板一侧形成第一缓冲材料层；
    在所述第一缓冲材料层背离所述衬底基板一侧形成第一栅极绝缘材料层；
    对所述第一缓冲材料层和第一栅极绝缘材料层进行刻蚀以形成所述开槽。
  17. 根据权利要求14所述的阵列基板制作方法，所述衬底基板制作方法还包括：
    在所述第二导电层背离所述衬底基板的一侧形成第三导电层，所述第三导电层包括第四导电部，所述第四导电部通过贯穿所述第三导电部的过孔与所述第一导电部电连接；
    其中，所述第四导电部在所述衬底基板的正投影位于所述第一导电部在所述衬底基板的正投影上，且所述第四导电部在所述衬底基板的正投影面积小于所述第一导电部在所述衬底基板的正投影面积。
  18. 根据权利要求17所述的阵列基板制作方法，其中，在所述第二导电层背离所述衬底基板的一侧形成第三导电层之前，还包括：
    在所述第三导电部上形成第二过孔，所述第二过孔贯穿所述第一介电层延伸至所述第一导电部的表面；
    在所述第二导电层背离所述衬底基板的一侧形成第二介电层，所述第二介电层填充所述第二过孔；
    在所述第二介电层上形成第一过孔，所述第一过孔贯穿所述第三导电部延伸至所述第一导电部的表面，且所述第一过孔在所述衬底基板的正投影位于所述第二过孔在所述衬底基板的正投影以内；
    其中，所述第四导电部填充所述第一过孔。
  19. 一种显示装置，其中，包括权利要求1-14任一项所述的阵列基板。
PCT/CN2020/124165 2020-10-27 2020-10-27 阵列基板及其制作方法、显示装置 WO2022087852A1 (zh)

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