WO2022104584A1 - 阵列基板、显示装置 - Google Patents

阵列基板、显示装置 Download PDF

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Publication number
WO2022104584A1
WO2022104584A1 PCT/CN2020/129717 CN2020129717W WO2022104584A1 WO 2022104584 A1 WO2022104584 A1 WO 2022104584A1 CN 2020129717 W CN2020129717 W CN 2020129717W WO 2022104584 A1 WO2022104584 A1 WO 2022104584A1
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WIPO (PCT)
Prior art keywords
base substrate
orthographic projection
conductive
conductive portion
active
Prior art date
Application number
PCT/CN2020/129717
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English (en)
French (fr)
Inventor
徐元杰
王本莲
龙跃
杜丽丽
黄耀
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/129717 priority Critical patent/WO2022104584A1/zh
Priority to CN202080002847.7A priority patent/CN114830347A/zh
Priority to US17/607,493 priority patent/US20220352278A1/en
Publication of WO2022104584A1 publication Critical patent/WO2022104584A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate and a display device.
  • an OLED display panel generally includes a pixel driving circuit, and the pixel driving circuit includes a driving transistor and a capacitor.
  • the driving transistor can provide a driving current to the light-emitting unit through the charge in the capacitor during the light-emitting stage of the display panel.
  • the layout space for setting the capacitance is small, so that the capacitance cannot meet the required capacitance parameters.
  • an array substrate includes a pixel driving circuit
  • the pixel driving circuit includes a driving transistor, a capacitor connected to a gate of the driving transistor
  • the array substrate further includes: A base substrate, a first conductive layer, a second conductive layer, and a third conductive layer.
  • a first conductive layer located on one side of the base substrate, the first conductive layer includes: a first conductive part and a second conductive part, the first conductive part is used to form the gate of the driving transistor;
  • the orthographic projection of the second conductive portion on the base substrate does not intersect with the orthographic projection of the first conductive portion on the base substrate, and the second conductive portion is used to form part of the first electrode of the capacitor;
  • the second conductive layer is arranged on The side of the first conductive layer facing away from the base substrate, the second conductive layer includes a third conductive part, and the orthographic projection of the third conductive part on the base substrate is lined with the second conductive part
  • the orthographic projections of the base substrate at least partially overlap, and the third conductive portion is electrically connected to the first conductive portion, and the third conductive portion is used to form the second electrode of the capacitor;
  • the third conductive layer is disposed on the The side of the second conductive layer facing away from the base substrate, the third conductive layer includes a fourth
  • the orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the third conductive portion on the base substrate are distributed at intervals in the first direction, so
  • the third conductive layer further includes:
  • the first connection part extends along the first direction in the orthographic projection of the base substrate, the first connection part is electrically connected with the first conductive part through the via hole, and the first connection part passes through the through hole.
  • the hole is electrically connected to the third conductive portion.
  • the fourth conductive portion includes a first sub-conductive portion; an orthographic projection of the first sub-conductive portion on the base substrate and the third conductive portion on the substrate
  • the orthographic projections of the base substrate do not intersect, and the orthographic projection of the first sub-conducting portion on the base substrate at least partially coincides with the orthographic projection of the second conductive portion on the base substrate; the first sub-conducting portion at least partially overlaps.
  • the conductive portion is electrically connected to the second conductive portion through a via hole.
  • the third conductive layer further includes a power supply line, the power supply line extends along the first direction, and the third conductive portion is located on the power supply line in an orthographic projection of the base substrate On one side of the orthographic projection of the base substrate on the second direction, the first direction intersects the second direction; wherein the fourth conductive portion is electrically connected to the power line, and the first direction is electrically connected to the power line.
  • the orthographic projection of the four conductive parts on the base substrate is located on one side of the orthographic projection of the power supply line on the base substrate in the second direction.
  • the array substrate includes a plurality of the pixel driving circuits; the first conductive layer includes a plurality of the second conductive parts, and the plurality of the second conductive parts
  • the orthographic projections of the base substrate are spaced apart along the second direction.
  • the third conductive layer includes a plurality of the power supply lines, the plurality of the power supply lines are spaced along the second direction, and the plurality of the power supply lines include adjacent first power lines.
  • a power cord and a second power cord wherein the orthographic projection of the second power cord on the base substrate is located on one side of the orthographic projection of the first power cord on the base substrate in the second direction;
  • the second conductive portion is electrically connected to the first power supply line through the first sub-conductive portion, and the second conductive portion is connected to the second power supply line through a via hole.
  • the pixel driving circuit further includes a second transistor, a first electrode of the second transistor is connected to a first electrode of the driving crystal, and a second electrode is connected to a gate of the driving transistor
  • the first conductive layer further includes a first grid line, the orthographic projection of the first grid line on the base substrate extends along the second direction, and the first grid line is on the base substrate.
  • the orthographic projection is located between the orthographic projection of the first conductive part on the base substrate and the orthographic projection of the second conductive part on the base substrate, and part of the first gate line is used to form the second transistor gate.
  • the pixel driving circuit further includes a first transistor, a first electrode of the first transistor is connected to a second electrode of the second transistor, and the first conductive layer further includes a first transistor.
  • Two grid lines, the orthographic projection of the second grid line on the base substrate extends along the second direction, and the orthographic projection of the second grid line on the base substrate is located on the second conductive part on the The orthographic projection of the base substrate is on a side of the orthographic projection of the base substrate away from the first gate line, and a part of the second gate line is used to form the gate of the first transistor.
  • the array substrate further includes an active layer disposed between the base substrate and the first conductive layer, and the active layer includes a first conductive layer. an active part, wherein the orthographic projection of the first active part on the base substrate extends along the first direction, and the first active part is used for electrically connecting the second electrode of the second transistor and the The first electrode of the first transistor; wherein, the orthographic projection of the first active portion on the base substrate passes through the gap between the orthographic projections of the adjacent second conductive portions on the base substrate.
  • the third conductive layer further includes a fifth conductive portion, and the fifth conductive portion is electrically connected between the fourth conductive portion and the power line, and the power line includes a fifth conductive portion.
  • an edge, the fifth conductive part includes a second edge connected to the first edge, the first edge is on the orthographic projection of the base substrate and the second edge is on the positive side of the base substrate The included angle formed by the projection is less than 180°; the orthographic projection of the fifth conductive portion on the base substrate at least partially coincides with the orthographic projection of the first active portion on the base substrate.
  • the first conductive layer further includes: a sixth conductive part, the sixth conductive part extends along the first direction on the orthographic projection of the base substrate, and is connected to the a first gate line;
  • the active layer further includes a second active part, a third active part, and a fourth active part, and the orthographic projection of the second active part on the base substrate is located in the first active part
  • a gate line is on the orthographic projection of the base substrate, the second active part is used to form the first channel region of the second transistor;
  • the third active part is located on the orthographic projection of the base substrate
  • the sixth conductive part is on the orthographic projection of the base substrate, the third active part is used to form the second channel region of the second transistor;
  • the fourth active part is connected to the second between the active part and the third active part, and the orthographic projection of the fourth active part on the base substrate does not intersect with the orthographic projection of the first conductive layer on the base substrate;
  • the third conductive layer further includes a seventh conductive part, the seventh conductive part
  • the active layer further includes: a fifth active part, the fifth active part is connected between the third active part and the first active part, so The orthographic projection of the fifth active part on the base substrate does not intersect with the orthographic projection of the first conductive layer on the base substrate; and the fifth active part is on the normal projection of the base substrate The projection at least partially coincides with the orthographic projection of the first connection portion on the base substrate, and the fifth active portion is electrically connected to the first connection portion through a via hole.
  • the active layer further includes: a sixth active part, the sixth active part is strip-shaped on the orthographic projection of the base substrate and extends along the second direction , the sixth active part is used to form the channel region of the driving transistor.
  • the size of the sixth active portion on the base substrate orthographic projection in the first direction is the size of the first gate line on the base substrate orthographic projection on the base substrate. 1.1-1.5 times the size in the first direction.
  • the orthographic projection of the first conductive portion on the base substrate is a strip extending in the second direction, and the orthographic projection of the first conductive portion on the base substrate
  • the dimension in the second direction is 2.5-5 times the dimension in the first direction.
  • the active layer further includes: a seventh active part, an eighth active part, and a ninth active part.
  • the orthographic projection of the seventh active part on the base substrate is located on the orthographic projection of the second gate line on the base substrate, and is used to form the first channel region of the first transistor; Eighth, the orthographic projection of the active part on the base substrate is located on the orthographic projection of the second gate line on the base substrate, for forming the second channel region of the first transistor; ninth The active part is connected between the seventh active part and the eighth active part, and the orthographic projection of the ninth active part on the base substrate and the first conductive layer on the The orthographic projections of the base substrate do not intersect.
  • the third conductive layer further includes an eighth conductive portion, the eighth conductive portion is electrically connected to the power line, the power line includes a third edge, and the eighth conductive portion includes a third edge connected to the third edge.
  • the included angle formed by the orthographic projection of the third edge on the base substrate and the orthographic projection of the fourth edge on the base substrate is less than 180°;
  • the orthographic projection of the base substrate at least partially coincides with the orthographic projection of the ninth active portion on the base substrate.
  • the third conductive layer further includes a plurality of data lines, and the plurality of data lines are distributed at intervals along the second direction on the orthographic projection of the base substrate, and along the first extending in one direction; a plurality of the data lines includes a first data line, and the orthographic projection of the first data line on the base substrate is located at the orthographic projection of the second power line on the base substrate and the first data line on the base substrate.
  • Four conductive parts are between the orthographic projections of the base substrate; and the orthographic projection of the first data line on the base substrate at least partially overlaps with the orthographic projection of the second conductive part on the base substrate.
  • a display device including the above-mentioned array substrate.
  • FIG. 1 is a schematic diagram of a circuit structure of a pixel driving circuit of the present disclosure
  • FIG. 2 is a timing diagram of each node in a driving method of the pixel driving circuit of FIG. 1;
  • 3 is a structural layout of an array substrate in the related art
  • Fig. 4 is a partial cross-sectional view along dotted line A in Fig. 3;
  • FIG. 5 is a partial structural layout of an exemplary embodiment of the disclosed array substrate
  • Fig. 6 is a sectional view along dotted line A in Fig. 5;
  • Fig. 7 is the structural layout of the first conductive layer in Fig. 6;
  • Fig. 8 is the structural layout of the second conductive layer in Fig. 6;
  • Fig. 9 is the structural layout of the third conductive layer in Fig. 6;
  • Fig. 10 is the layout structure of the active layer in Fig. 6;
  • FIG. 11 is a structural layout of another exemplary embodiment of the disclosed array substrate.
  • Fig. 12 is the structural layout of the active layer in Fig. 11;
  • Fig. 13 is the structural layout of the first conductive layer in Fig. 11;
  • FIG. 14 is a structural layout of the second conductive layer in FIG. 11;
  • Fig. 15 is the structural layout of the third conductive layer in Fig. 11;
  • FIG. 16 is a structural layout of another exemplary embodiment of the disclosed array substrate.
  • FIG. 17 is a structural layout of the anode layer in FIG. 16 .
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C.
  • the first pole of the first transistor T1 is connected to the node N, the second pole is connected to the initialization signal terminal Vinit, and the gate is connected to the reset signal terminal Re; the first pole of the second transistor T2 is connected to the first pole of the driving transistor T3, and the second pole is connected
  • the gate is connected to the gate driving signal terminal Gate; the gate of the driving transistor T3 is connected to the node N; the first pole of the fourth transistor T4 is connected to the data signal terminal Da, and the second pole is connected to the second pole of the driving transistor T3, The gate is connected to the gate driving signal terminal Gate;
  • the first pole of the fifth transistor T5 is connected to the first power supply signal terminal VDD, the second pole is connected to the second pole of the driving transistor T3, and the gate is connected to the enable signal terminal EM;
  • the sixth transistor The first pole of T6 is connected to the first pole of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the first pole of the seventh transistor T7 is connected to the initialization signal terminal Vinit, and
  • the pixel driving circuit may be connected to a light-emitting unit OLED for driving the light-emitting unit OLED to emit light, and the light-emitting unit OLED may be connected between the second pole of the sixth transistor T6 and the second power terminal VSS.
  • the transistors T1-T7 may all be P-type transistors.
  • FIG. 2 it is a timing diagram of each node in a driving method of the pixel driving circuit of FIG. 1 .
  • Gate represents the timing of the gate driving signal terminal Gate
  • Re represents the timing of the reset signal terminal Re
  • EM represents the timing of the enable signal terminal EM
  • Da represents the timing of the data signal terminal Da.
  • the driving method of the pixel driving circuit may include a reset stage t1, a compensation stage t2, and a light-emitting stage t3.
  • the reset signal terminal Re outputs a low level signal
  • the first transistor T1 and the seventh transistor T7 are turned on
  • the initialization signal terminal Vinit inputs the initialization signal to the node N and the second pole of the sixth transistor T6.
  • the gate driving signal terminal Gate outputs a low level signal
  • the fourth transistor T4 and the second transistor T2 are turned on, and at the same time the data signal terminal Da outputs a driving signal to write the voltage Vdata+Vth to the node N, where Vdata is the voltage of the driving signal, and Vth is the threshold voltage of the driving transistor T3.
  • Light-emitting stage t3 the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata+Vth stored in the capacitor C.
  • the driving transistor output current formula I ( ⁇ WCox/2L)(Vgs-Vth) 2 , where ⁇ is the carrier mobility; Cox is the gate capacitance per unit area, W is the channel width of the driving transistor, and L drives The length of the transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor.
  • the output current I ( ⁇ WCox/2L)(Vdata+Vth ⁇ Vdd ⁇ Vth) 2 of the driving transistor in the pixel driving circuit of the present disclosure.
  • the pixel driving circuit can avoid the influence of the threshold value of the driving transistor on its output current.
  • FIG. 3 is a structural layout of an array substrate in the related art
  • FIG. 4 is a partial cross-sectional view taken along the dotted line A in FIG. 3
  • the array substrate shown in FIG. 3 can form the pixel driving circuit shown in FIG. 1 .
  • the array substrate includes a base substrate 01 , and the active layer (including the active portion 02 ) located on one side of the base substrate 01 is located on the active layer away from the substrate.
  • the active part 02 can form the channel region of the driving transistor T3 in FIG. 1
  • the gate part 04 can form the gate of the driving transistor T3 in FIG. 1
  • the gate part 06 and the gate part 04 can form the capacitor C.
  • the layout area of the gate portion 06 and the gate portion 04 is limited, and the capacitance value of the capacitor C often cannot reach the preset capacitance parameter.
  • FIG. 5 is a partial structural layout of an exemplary embodiment of an array substrate of the disclosure
  • FIG. 6 is a diagram 5 is a cross-sectional view along the dotted line A
  • FIG. 7 is a structural layout of the first conductive layer in FIG. 6
  • FIG. 8 is a structural layout of the second conductive layer in FIG. 6
  • FIG. 9 is a structural layout of the third conductive layer in FIG. 6
  • the array substrate may include a pixel driving circuit, and the pixel driving circuit may be as shown in FIG. 1 .
  • the array substrate may further include: a base substrate 0, a first conductive layer, a second conductive layer, and a third conductive layer.
  • the first conductive layer may be located on one side of the base substrate 0, and the first conductive layer may include: a first conductive part 11 and a second conductive part 12, and the first conductive part 11 may be used to form the The gate of the drive transistor T3; the orthographic projection of the second conductive portion 12 on the base substrate 0 may not intersect with the orthographic projection of the first conductive portion 11 on the base substrate 0, and the second conductive portion 12 may be
  • the second conductive layer may be disposed on the side of the first conductive layer away from the base substrate 0, the second conductive layer may include a third conductive portion 23, the third conductive layer
  • the orthographic projection of the conductive portion 23 on the base substrate may at least partially overlap with the orthographic projection of the second conductive portion on the base substrate, and the third conductive portion 23 is electrically connected to the first conductive portion 11 ,
  • the third conductive portion 23
  • the third conductive portion 23 may serve as the second electrode of the capacitor C, and the second conductive portion 12 and the fourth conductive portion 34 may serve as the first electrode of the capacitor C together.
  • the third conductive part 23 can form a parallel plate capacitor structure with the second conductive part 12 and the fourth conductive part 34 respectively, that is, the capacitor C can be composed of the above two parallel plate capacitor structures in parallel, so that the capacitor C has a larger capacitance value.
  • the pixel driving circuit in the array substrate of the present disclosure may also have other structures.
  • the pixel drive circuit includes a drive transistor and a capacitor connected to the gate of the drive transistor, the array substrate can implement a capacitor with a larger capacitance value through the above structure.
  • the array substrate may further include a first gate insulating layer 4 located between the first conductive layer and the second conductive layer, and a first gate insulating layer 4 located between the second conductive layer and the third conductive layer Dielectric layer 5 between layers.
  • the first gate insulating layer 4 may be a silicon oxide layer
  • the dielectric layer 5 may be a silicon nitride layer.
  • the first conductive layer, the second conductive layer, and the third conductive layer can all be formed by at least one metal layer.
  • the first conductive layer, the second conductive layer, and the third conductive layer can all be formed by stacking the first titanium layer, the aluminum layer, and the second titanium layer in sequence.
  • the base substrate may be formed of an insulating material, for example, the base substrate may include a first polyimide (PI) layer, a first silicon oxide (SiO) layer, an amorphous silicon layer, a second polyimide layer that are arranged in sequence (PI) layer, second silicon dioxide layer.
  • PI polyimide
  • SiO silicon oxide
  • PI polyimide
  • the orthographic projection of the first conductive portion 11 on the base substrate and the orthographic projection of the third conductive portion 23 on the base substrate may be in the first Distributed at intervals in one direction X.
  • the third conductive portion 23 may include a second sub-conductive portion 232, and the orthographic projection of the second sub-conductive portion 232 on the base substrate does not intersect with the orthographic projection of the fourth conductive portion 34 on the base substrate.
  • the third conductive layer may further include a first connection portion 31 .
  • the orthographic projection of the first connection portion 31 on the base substrate may extend along the first direction X, the first connection portion 31 may be electrically connected to the first conductive portion 11 through the via hole 92 , and the The first connecting portion 31 may be electrically connected to the second sub-conducting portion 232 through the via hole 91 .
  • the first conductive portion 11 is substantially used to connect the gate of the driving transistor T3 and the second electrode of the capacitor C.
  • the fourth conductive portion 34 may include a first sub-conductive portion 341 ; the orthographic projection of the first sub-conductive portion 341 on the base substrate It may be disjoint with the orthographic projection of the third conductive portion 23 on the base substrate, and the orthographic projection of the first sub-conductive portion 341 on the base substrate and the second conductive portion 12 on the The orthographic projections of the base substrate are at least partially coincident.
  • the first sub-conducting portion 341 may be electrically connected to the second conducting portion 12 through the via hole 93 , so as to realize the electrical connection between the fourth conducting portion 34 and the second conducting portion 12 .
  • the fourth conductive portion 34 and the second conductive portion 12 may also be connected by other structures, for example, the fourth conductive portion 34 may be electrically connected through a via hole passing through the third conductive portion 23 .
  • the second conductive portion 12 is connected and insulated from the third conductive portion 23 .
  • FIG. 10 is the layout structure of the active layer in FIG. 5 .
  • the array substrate may further include an active layer, and the active layer may be located between the base substrate and the first conductive layer.
  • the active layer may include: a sixth active part 66 , and the orthographic projection of the sixth active part 66 on the base substrate may be strip-shaped, and along the first Extending in two directions Y, the sixth active portion 66 may be used to form the channel region of the driving transistor T3.
  • the first conductive portion 11 may also be a strip-shaped structure extending along the second direction Y, and the orthographic projection of the first conductive portion 11 on the base substrate may cover the orthographic projection of the sixth active portion 66 on the base substrate.
  • the second direction Y may intersect with the first direction X, for example, the second direction Y may be perpendicular to the first direction.
  • the channel region of the driving transistor T3 is configured as a strip-shaped structure extending along the second direction, so that the size of the driving transistor T3 in the first direction can be reduced, so as to reserve space for use in the first direction X space for setting the capacitor C.
  • the sixth active portion 66 and the first conductive portion 11 may be in the form of a rectangle, a rectangle with rounded corners, or the like.
  • the size of the orthographic projection of the first conductive portion 11 on the base substrate in the second direction may be 2.5-5 times, for example, 2.2 times, 3.5 times, and 4 times the size of the first conductive portion 11 in the first direction. ,5 times.
  • the array substrate may further include a second gate insulating layer 7 located between the active layer and the first conductive layer, and the second gate insulating layer 7 may also be a silicon oxide layer.
  • FIG. 11 is a structural layout of another exemplary embodiment of the disclosed array substrate
  • FIG. 12 is the structure of the active layer in FIG. 11
  • FIG. 13 is the structural layout of the first conductive layer in FIG. 11
  • FIG. 14 is the structural layout of the second conductive layer in FIG. 11
  • FIG. 15 is the structural layout of the third conductive layer in FIG. 11 .
  • the array substrate shown in FIG. 11 may include any structure of the array substrate shown in FIGS. 5-10 .
  • the third conductive layer may further include a power supply line 321 , the power supply line 321 may extend along the first direction X, and the third conductive layer may The orthographic projection of the portion 23 on the base substrate may be located on one side in the second direction Y of the orthographic projection of the power supply line 321 on the base substrate.
  • the fourth conductive portion 34 may be electrically connected to the power line 321, and the orthographic projection of the fourth conductive portion 34 on the base substrate may be located at the front of the power line 321 on the base substrate. Projected on one side of the second direction Y.
  • the power line 321 can be used to provide the first power terminal signal VDD in FIG. 1 to provide the first electrode of the capacitor C with a power signal.
  • the array substrate may include a plurality of the pixel driving circuits; the first conductive layer may include a plurality of the second conductive parts 12 , and a plurality of all the pixel driving circuits may be included.
  • the orthographic projection of the second conductive parts 12 on the base substrate is distributed along the second direction Y at intervals.
  • FIGS. 11 and 13 the array substrate may include a plurality of the pixel driving circuits; the first conductive layer may include a plurality of the second conductive parts 12 , and a plurality of all the pixel driving circuits may be included.
  • the orthographic projection of the second conductive parts 12 on the base substrate is distributed along the second direction Y at intervals.
  • the third conductive layer may include a plurality of power supply lines, a plurality of the power supply lines may be distributed along the second direction Y at intervals, and a plurality of the power supply lines
  • the lines may include adjacent power lines 321 and 322, and the orthographic projection of the power lines 322 on the base substrate may be located in the second direction Y in the orthographic projection of the power lines 321 on the base substrate. side.
  • the second conductive portion 12 can be electrically connected to the power line 321 through the first sub-conductive portion 341 , and at the same time, the second conductive portion 12 can also be electrically connected to the power line 322 through the via hole 94 .
  • the second conductive portion 12 is connected to two adjacent power supply lines at the same time, so that the uniformity of the power supply voltage on the second conductive portion 12 can be improved.
  • the pixel driving circuit in the array substrate may further include a first transistor and a second transistor.
  • the first electrode of the second transistor is connected to the first electrode of the driving crystal, and the second electrode is connected to the gate of the driving transistor.
  • the first electrode of the first transistor is connected to the second electrode of the second transistor.
  • the first transistor may be the first transistor T1 as shown in FIG. 1
  • the second transistor may be the second transistor T2 as shown in FIG. 1 .
  • the first conductive layer may further include a first gate line 13 , and the first gate line 13 may be used to provide the gate driving signal terminal in FIG. 1 .
  • the orthographic projection of the first grid line 13 on the base substrate may extend along the second direction Y, and the orthographic projection of the first grid line 13 on the base substrate may be located at the first conductive portion 11 Between the orthographic projection of the base substrate and the orthographic projection of the second conductive portion 12 on the base substrate, part of the conductive portion 131 of the first gate line 13 may be used to form the second transistor T2 first gate.
  • the first conductive layer may further include a second gate line 14, and the second gate line 14 may be used to provide the reset signal terminal in FIG. 1 .
  • the orthographic projection of the second grid line 14 on the base substrate extends along the second direction Y, and the orthographic projection of the second grid line 14 on the base substrate may be located where the second conductive portion 12 is located
  • the orthographic projection of the base substrate is away from the orthographic projection of the first gate line 13 on the side of the base substrate, and part of the conductive portion 141 of the second gate line 14 can be used to form the first gate line of the first transistor T1.
  • a gate, and part of the conductive portion 142 of the second gate line 14 can be used to form the second gate of the first transistor T1.
  • the active layer may further include a first active part 61 , and the first active part 61 is along the orthographic projection of the base substrate along the Extending in the first direction X, the first active part 61 can be used to electrically connect the second pole of the second transistor T2 and the first pole of the first transistor T1; wherein, the first active part 61
  • the orthographic projection on the base substrate may penetrate through the gap between the orthographic projections of the adjacent second conductive parts 12 on the base substrate.
  • the original material for forming the active layer can be a semiconductor, and in the manufacturing process of the array substrate, the active layer can be conductively processed by using the first conductive layer as a mask, so as to separate the semiconductor structure outside the transistor channel region. into a conducting structure.
  • the second conductive parts 12 By arranging the second conductive parts 12 at intervals along the second direction Y, a gap for routing the first active parts 61 can be reserved between adjacent second conductive parts 12 .
  • the third conductive layer may further include a fifth conductive portion 35 , and the fifth conductive portion 35 may be connected to the fourth conductive portion 34 and the power line 321, the power line 321 may include a first edge 3211, the fifth conductive portion 35 may include a second edge 352 connected to the first edge 3211, and the first edge 3211 is on the substrate
  • the included angle formed by the orthographic projection of the substrate and the orthographic projection of the second edge 352 on the base substrate may be less than 180°. That is, the fifth conductive portion 35 may protrude from the power line 321 along the second direction Y.
  • the orthographic projection of the fifth conductive portion 35 on the base substrate at least partially overlaps with the orthographic projection of the first active portion 61 on the base substrate.
  • the fifth conductive part 35 and the first active part 61 can form a parallel plate capacitor structure, and the parallel plate capacitor structure can form a parallel structure with the parallel plate capacitor structure formed by the fourth conductive part 34 and the third conductive part 23, thereby , this setting can further increase the capacitance value of capacitor C.
  • the first conductive layer may further include: a sixth conductive portion 16 , and the orthographic projection of the sixth conductive portion 16 on the base substrate may be along the first conductive portion 16 .
  • a direction X extends and is connected to the first gate line 13 .
  • the sixth conductive portion 16 may extend toward the first direction X from the first gate line 13 .
  • the active layer may further include a second active part 62 , a third active part 63 , and a fourth active part 64 , and the second active part 62 is located at the bottom of the base substrate.
  • the orthographic projection is on the orthographic projection of the first gate line 13 on the base substrate, and the second active portion 62 can be used to form the first channel region of the second transistor T2; the third active portion
  • the orthographic projection of the portion 63 on the base substrate may be located on the orthographic projection of the sixth conductive portion 16 on the base substrate, and the third active portion 63 may be used to form the third active portion of the second transistor T2.
  • the fourth active part 64 may be connected between the second active part and the third active part, and the orthographic projection of the fourth active part 64 on the base substrate and the first active part
  • the orthographic projections of the base substrate of the conductive layer do not intersect. As shown in FIG.
  • the second transistor T2 has a double-gate structure, and the second transistor T2 with the double-gate structure has a smaller leakage current, thereby reducing the leakage current of the capacitor C passing through the second transistor during the light-emitting phase of the pixel driving circuit.
  • the fourth active part 64 is a conductor, parasitic capacitance is formed between the fourth active part 64 and part of the first gate line 13 and the sixth conductive part 16 .
  • the voltage on the first gate line 13 changes, Based on the bootstrap effect of the capacitance, the voltage of the fourth active part 64 will also change correspondingly, so that the fourth active part 64 leaks electricity to the source and drain of the second transistor T2, and finally causes the pixel driving circuit to drive abnormally.
  • the third conductive layer may further include a seventh conductive portion 37 , the seventh conductive portion 37 may be connected to the fourth conductive portion 34 , and the seventh conductive portion 37
  • the orthographic projection of the conductive portion 37 on the base substrate at least partially overlaps with the orthographic projection of the fourth active portion 64 on the base substrate.
  • This arrangement enables the seventh conductive portion 37 and the fourth active portion 64 to form a parallel plate capacitor structure. Since the seventh conductive portion 37 is connected to the power line, the seventh conductive portion 37 has a stable voltage, so that the seventh conductive portion 37 can inhibit the The potential of the fourth active portion 64 changes, thereby reducing the leakage current of the fourth active portion 64 to the source and drain of the second transistor T2.
  • the active layer may further include: a fifth active part 65 , and the fifth active part 65 may be connected to the third active part 63 and all the between the first active parts 61 .
  • the orthographic projection of the fifth active part 65 on the base substrate may extend in the second direction, and the orthographic projection of the fifth active part 65 on the base substrate is the same as the orthographic projection of the first conductive layer on the base substrate and the orthographic projection of the fifth active portion 65 on the base substrate at least partially coincides with the orthographic projection of the first connection portion 31 on the base substrate, and the fifth The active part 65 may be electrically connected to the first connection part 31 through the via hole 95 . This arrangement can make the second pole of the second transistor T2 electrically connected to the gate of the driving transistor.
  • the active layer may further include: a seventh active part 67 , an eighth active part 68 , and a ninth active part 69 .
  • the orthographic projection of the seventh active portion 67 on the base substrate may be located on the orthographic projection of the second gate line 14 on the base substrate, for forming the first trench of the first transistor T1 channel region;
  • the orthographic projection of the eighth active portion 68 on the base substrate may be located on the orthographic projection of the second gate line 14 on the base substrate, for forming the first transistor T1
  • the ninth active part 69 may be connected between the seventh active part 67 and the eighth active part 68 .
  • the orthographic projection of the ninth active portion 69 on the base substrate does not intersect with the orthographic projection of the first conductive layer on the base substrate, and the ninth active portion 69 is on the base substrate.
  • the orthographic projection may be located on the side of the orthographic projection of the second grid line 14 on the base substrate away from the orthographic projection of the first grid line 13 on the base substrate.
  • the first transistor T1 has a double-gate structure, and the first transistor T1 of the double-gate structure has a smaller leakage current, thereby reducing the leakage current of the capacitor C passing through the first transistor during the light-emitting phase of the pixel driving circuit.
  • the ninth active part 69 is a conductor, there is a parasitic capacitance between the ninth active part 69 and part of the second gate line 14.
  • the voltage on the second gate line 14 changes, the bootstrap effect based on the capacitance will occur.
  • the voltage of the ninth active part 69 will also change correspondingly, so that the ninth active part 69 leaks electricity to the source and drain of the first transistor T1 , and finally causes the pixel driving circuit to drive abnormally.
  • the third conductive layer may further include an eighth conductive portion 38 , and the eighth conductive portion 38 may be electrically connected to the power line 321 , and the power line 321 includes a first conductive portion 38 .
  • the eighth conductive part 38 includes a fourth edge 384 connected to the third edge 3213, the orthographic projection of the third edge 3213 on the base substrate and where the fourth edge 384 is located.
  • the included angle formed by the orthographic projection of the base substrate is less than 180°. That is, the eighth conductive portion 38 protrudes from the power line 321 along the second direction.
  • the orthographic projection of the eighth conductive portion 38 on the base substrate may at least partially overlap with the orthographic projection of the ninth active portion 69 on the base substrate.
  • This arrangement can make the eighth conductive part 38 and the ninth active part 69 form a parallel plate capacitor structure. Since the eighth conductive part 38 is connected to the power line, the eighth conductive part 38 has a stable voltage, so that the eighth conductive part 38 can inhibit the The potential of the ninth active portion 69 changes, thereby reducing the leakage current of the ninth active portion 69 to the source and drain of the first transistor T1.
  • the size of the sixth active portion 66 in the orthographic projection of the base substrate in the first direction X may be the size of the first gate line 13
  • the size of the orthographic projection of the base substrate in the first direction is 1.1-1.5 times, for example, 1.1 times, 1.3 times, 1.5 times.
  • the size of the first conductive portion 11 on the base substrate orthographic projection in the first direction may be the size of the first grid line 13 on the base substrate orthographic projection size in the first direction 1.5-2.5 times, eg, 1.5 times, 2 times, 2.5 times.
  • the array substrate provided in this exemplary embodiment can form the pixel driving circuit shown in FIG. 1 .
  • the array substrate may further include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.
  • the active layer may further include a tenth active part 610 , an eleventh active part 611 , a twelfth active part 612 , and a thirteenth active part 613 .
  • the tenth active part 610 can be used to form the channel region of the fourth transistor T4; the eleventh active part 611 can be used to form the channel region of the fifth transistor T5; the twelfth active part 612 can be used to form the channel region of the fifth transistor T5 For forming the channel region of the sixth transistor T6; the thirteenth active portion 613 may be used for forming the channel region of the seventh transistor.
  • the first conductive layer may further include a third gate line 17 , and the third gate line 17 may be used to provide the enable signal terminal in FIG. 1 .
  • the orthographic projection of the third grid line 17 on the base substrate may be located on the side of the orthographic projection of the first conductive portion 11 on the base substrate away from the orthographic projection of the first grid line 13 on the base substrate.
  • the first gate line 13 may further include a conductive portion 134, and the conductive portion 134 may be used to form the gate of the fourth transistor T4.
  • the third gate line 17 may include a conductive portion 175 and a conductive portion 176, the conductive portion 175 may be used to form the gate of the fifth transistor, and the conductive portion 176 may be used to form the gate of the sixth transistor.
  • the gate of the seventh transistor T7 may share the conductive portion 147 in the second gate line 14 corresponding to the next row of pixel units.
  • the third conductive layer may further include a second connection part 39 , a third connection part 310 , and a data line 311 .
  • the second connection part 39 can be connected to the active layer on the side of the eighth active part 68 through the via hole 96 to connect to the second pole of the first transistor T1 .
  • the third connection part 310 may connect the active layer between the twelfth active part 612 and the thirteenth active part 613 through the via hole 97 to connect the second electrode of the sixth transistor T6 and the first electrode of the seventh transistor T7 Diode.
  • the first pole of the seventh transistor T7 may be connected to the second connection part 39 in the next row of pixel units.
  • the data line 311 may be connected to the first electrode of the fourth transistor T4 through the via hole 98 .
  • the third conductive layer may include a plurality of data lines, for example, the third conductive layer may further include a data line 312, and the plurality of the data lines are on the base substrate
  • the orthographic projections of are spaced along the second direction Y and extend along the first direction X.
  • the orthographic projection of the data line 312 on the base substrate may be located between the orthographic projection of the power line 322 on the base substrate and the orthographic projection of the fourth conductive portion 34 on the base substrate.
  • the orthographic projection of the data line 312 on the base substrate at least partially overlaps with the orthographic projection of the second conductive portion 12 on the base substrate.
  • the array substrate may further include an anode layer, as shown in FIG. 17 , which is the structural layout of the anode layer in FIG. 16 .
  • the array substrate may adopt a GGRB pixel arrangement, and the anode layer may include a first anode part 81 , a second anode part 82 , a third anode part 83 , a fourth anode part 84 , and an anode wiring 85 .
  • the first anode portion 81 may form the anode of the R sub-pixel
  • the second anode portion 82 and the third anode portion 83 may form the anode of the G sub-pixel
  • the fourth anode portion 8 may form the anode of the B sub-pixel.
  • the first anode part 81 , the third anode part 83 , and the fourth anode part 84 can be connected to the third connection part 310 in the same row of pixel units through via holes to connect the second pole of the seventh transistor T7 in the row of pixel driving circuits .
  • the second anode part 82 may be connected to the third connection part 310 in the pixel unit of the adjacent upper row to connect the second electrode of the seventh transistor T7 in the pixel driving circuit of the adjacent upper row.
  • the anode traces 85 can be connected to the second connection parts 39 in the same row of pixel units for providing the initialization signal terminal Vinit shown in FIG. 1 .
  • the present exemplary embodiment also provides a display device including the above-mentioned array substrate.
  • the display device may be a display device such as a mobile phone, a tablet computer, and a TV.

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Abstract

一种阵列基板和显示装置，该阵列基板包括衬底基板、第一导电层、第二导电层、第三导电层。第一导电层位于衬底基板的一侧，包括用于形成驱动晶体管栅极的第一导电部、用于形成电容第一电极的第二导电部；第二导电层设置于第一导电层背离衬底基板的一侧，包括用于形成电容第二电极的第三导电部，第三导电部在衬底基板的正投影与第二导电层在衬底基板的正投影至少部分重合；第三导电层设置于第二导电层背离衬底基板的一侧，包括第四导电部，第四导电部在衬底基板的正投影与第三导电部衬底基板的正投影至少部分重合，且第四导电部与第二导电部电连接，用于形成电容的第一电极。该阵列基板中的电容具有较大的电容值。

Description

阵列基板、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板、显示装置。
背景技术
相关技术中，OLED显示面板一般包括有像素驱动电路，像素驱动电路包括有驱动晶体管和电容，驱动晶体管在显示面板发光阶段可以通过电容中的电荷向发光单元提供驱动电流。然而，在高像素密度的显示面板中，用于设置电容的版图空间较小，从而电容不能达到要求的电容参数。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
根据本公开的一个方面，提供一种阵列基板，其中，所述阵列基板包括像素驱动电路，所述像素驱动电路包括驱动晶体管、连接于所述驱动晶体管栅极的电容，该阵列基板还包括：衬底基板、第一导电层、第二导电层、第三导电层。第一导电层，位于所述衬底基板的一侧，所述第一导电层包括：第一导电部、第二导电部，所述第一导电部用于形成所述驱动晶体管的栅极；所述第二导电部在衬底基板正投影与所述第一导电部在衬底基板正投影不相交，所述第二导电部用于形成电容的部分第一电极；第二导电层设置于所述第一导电层背离所述衬底基板的一侧，第二导电层包括第三导电部，所述第三导电部在所述衬底基板的正投影与所述第二导电部在衬底基板的正投影至少部分重合，且所述第三导电部与所述第一导电部电连接，所述第三导电部用于形成所述电容的第二电极；第三导电层设置于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括第四导电部，所述第四导电部在所述衬底基板的正投影与所述第三导电部在所述衬底基板的正投影至少部分重合，且所述第四导电部与所述第二导电部电连接，所述第四导电部用于形成所述电容的部分第一电极。
本公开一种示例性实施例中，所述第一导电部在所述衬底基板的正投影和所述第三导电部在所述衬底基板的正投影在第一方向上间隔分布，所述第三导电层还包括：
第一连接部，在所述衬底基板的正投影沿所述第一方向延伸，所述第一连接部通过过孔与所述第一导电部电连接，且所述第一连接部通过过孔与所述第三导电部电连接。
本公开一种示例性实施例中，所述第四导电部包括第一子导电部；所述第一子导电部在所述衬底基板的正投影与所述第三导电部在所述衬底基板的正投影不相交，且所述第一 子导电部在所述衬底基板的正投影与所述第二导电部在所述衬底基板的正投影至少部分重合；所述第一子导电部通过过孔与所述第二导电部电连接。
本公开一种示例性实施例中，所述第三导电层还包括电源线，电源线沿所述第一方向延伸，所述第三导电部在所述衬底基板正投影位于所述电源线在所述衬底基板的正投影在第二方向的一侧，所述第一方向与所述第二方向相交；其中，所述第四导电部与所述电源线电连接，且所述第四导电部在所述衬底基板的正投影位于所述电源线在所述衬底基板正投影在所述第二方向的一侧。
本公开一种示例性实施例中，所述阵列基板包括多个所述像素驱动电路；所述第一导电层包括多个所述第二导电部，多个所述第二导电部在所述衬底基板的正投影沿所述第二方向间隔分布。
本公开一种示例性实施例中，所述第三导电层包括多条所述电源线，多条所述电源线沿所述第二方向间隔分布，多条所述电源线包括相邻的第一电源线和第二电源线，所述第二电源线在所述衬底基板的正投影位于所述第一电源线在所述衬底基板正投影在所述第二方向的一侧；所述第二导电部通过所述第一子导电部和所述第一电源线电连接，且所述第二导电部通过过孔和所述第二电源线连接。
本公开一种示例性实施例中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极连接所述驱动晶体的第一极，第二极连接所述驱动晶体管的栅极，所述第一导电层还包括第一栅线，第一栅线在所述衬底基板的正投影沿所述第二方向延伸，且所述第一栅线在所述衬底基板的正投影位于所述第一导电部在所述衬底基板正投影与所述第二导电部在所述衬底基板正投影之间，部分所述第一栅线用于形成所述第二晶体管的栅极。
本公开一种示例性实施例中，所述像素驱动电路还包括第一晶体管，所述第一晶体管的第一极连接所述第二晶体管的第二极，所述第一导电层还包括第二栅线，第二栅线在所述衬底基板的正投影沿所述第二方向延伸，且所述第二栅线在所述衬底基板正投影位于所述第二导电部在所述衬底基板正投影远离所述第一栅线在所述衬底基板正投影的一侧，部分所述第二栅线用于形成所述第一晶体管的栅极。
本公开一种示例性实施例中，所述阵列基板还包括有源层，所述有源层设置于所述衬底基板和所述第一导电层之间，所述有源层包括第一有源部，所述第一有源部在所述衬底基板的正投影沿所述第一方向延伸，所述第一有源部用于电连接所述第二晶体管第二极和所述第一晶体管的第一极；其中，所述第一有源部在所述衬底基板的正投影贯穿设置于相邻所述第二导电部在所述衬底基板正投影之间的间隙。
本公开一种示例性实施例中，所述第三导电层还包括第五导电部，第五导电部电连接于所述第四导电部和所述电源线之间，所述电源线包括第一边沿，所述第五导电部包括与所述第一边沿连接的第二边沿，所述第一边沿在所述衬底基板的正投影和所述第二边沿在所述衬底基板的正投影所成的夹角小于180°；所述第五导电部在所述衬底基板的正投影与所述第一有源部在所述衬底基板的正投影至少部分重合。
本公开一种示例性实施例中，所述第一导电层还包括：第六导电部，第六导电部在所述衬底基板的正投影沿所述第一方向延伸，且连接于所述第一栅线；所述有源层还包括第二有源部、第三有源部、第四有源部，所述第二有源部在所述衬底基板的正投影位于所述第一栅线在所述衬底基板的正投影上，所述第二有源部用于形成所述第二晶体管的第一沟道区；第三有源部在所述衬底基板正投影位于所述第六导电部在所述衬底基板的正投影上，所述第三有源部用于形成所述第二晶体管的第二沟道区；第四有源部连接于所述第二有源部和所述第三有源部之间，且所述第四有源部在所述衬底基板的正投影与所述第一导电层所述衬底基板的正投影均不相交；所述第三导电层还包括第七导电部，第七导电部连接所述第四导电部，且所述第七导电部在所述衬底基板的正投影与所述第四有源部在所述衬底基板的正投影至少部分重合。
本公开一种示例性实施例中，所述有源层还包括：第五有源部，第五有源部连接于所述第三有源部和所述第一有源部之间，所述第五有源部在所述衬底基板的正投影与所述第一导电层在所述衬底基板的正投影不相交；且所述第五有源部在所述衬底基板的正投影与所述第一连接部在所述衬底基板的正投影至少部分重合，且所述第五有源部通过过孔与所述第一连接部电连接。
本公开一种示例性实施例中，所述有源层还包括：第六有源部，第六有源部在所述衬底基板的正投影为条形，且沿所述第二方向延伸，所述第六有源部用于形成所述驱动晶体管的沟道区。
本公开一种示例性实施例中，所述第六有源部在所述衬底基板正投影在所述第一方向上的尺寸为所述第一栅线在所述衬底基板正投影在所述第一方向上尺寸的1.1-1.5倍。
本公开一种示例性实施例中，所述第一导电部在所述衬底基板的正投影为延伸所述第二方向延伸的条形，所述第一导电部在衬底基板的正投影在所述第二方向上的尺寸为其在所述第一方向上尺寸的2.5-5倍。
本公开一种示例性实施例中，所述有源层还包括：第七有源部、第八有源部、第九有源部。第七有源部在所述衬底基板的正投影位于所述所述第二栅线在所述衬底基板的正投影上，用于形成所述第一晶体管的第一沟道区；第八有源部在所述衬底基板的正投影位于所述所述第二栅线在所述衬底基板的正投影上，用于形成所述第一晶体管的第二沟道区；第九有源部连接于所述第七有源部和所述第八有源部之间，且所述第九有源部在所述衬底基板的正投影与所述第一导电层在所述衬底基板的正投影不相交。所述第三导电层还包括第八导电部，第八导电部电连接于所述电源线，所述电源线包括第三边沿，所述第八导电部包括与所述第三边沿连接的第四边沿，所述第三边沿在所述衬底基板的正投影和所述第四边沿在所述衬底基板的正投影所成的夹角小于180°；所述第八导电部在所述衬底基板的正投影与所述第九有源部在所述衬底基板的正投影至少部分重合。
本公开一种示例性实施例中，所述第三导电层还包括多条数据线，多条所述数据线在所述衬底基板的正投影沿所述第二方向间隔分布，且沿第一方向延伸；多条所述数据线包 括第一数据线，所述第一数据线在所述衬底基板的正投影位于所述第二电源线在所述衬底基板正投影和所述第四导电部在所述衬底基板正投影之间；且所述第一数据线在所述衬底基板的正投影和与所述第二导电部在所述衬底基板正投影至少部分重合。
根据本公开的一个方面，提供一种显示装置，该显示装置包括上述的阵列基板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一种像素驱动电路的电路结构示意图；
图2为图1像素驱动电路一种驱动方法中各节点的时序图；
图3为相关技术中阵列基板的结构版图；
图4为图3中沿虚线A的部分剖视图；
图5为本公开阵列基板一种示例性实施例的部分结构版图；
图6为图5中沿虚线A的剖视图；
图7为图6中第一导电层的结构版图；
图8为图6中第二导电层的结构版图；
图9为图6中第三导电层的结构版图；
图10为图6中有源层的版图结构；
图11为本公开阵列基板另一种示例性实施例的结构版图；
图12为图11中有源层的结构版图；
图13为图11中第一导电层的结构版图；
图14为图11中第二导电层的结构版图；
图15为图11中第三导电层的结构版图；
图16为本公开阵列基板另一种示例性实施例的结构版图；
图17为图16中阳极层的结构版图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完 整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成区分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成区分/等之外还可存在另外的要素/组成区分/等。
如图1所示，为本公开一种像素驱动电路的电路结构示意图。该像素驱动电路可以包括：第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、电容C。其中，第一晶体管T1的第一极连接节点N，第二极连接初始化信号端Vinit，栅极连接复位信号端Re；第二晶体管T2第一极连接驱动晶体管T3的第一极，第二极连接节点N；栅极连接栅极驱动信号端Gate；驱动晶体管T3的栅极连接节点N；第四晶体管T4的第一极连接数据信号端Da，第二极连接驱动晶体管T3的第二极，栅极连接栅极驱动信号端Gate；第五晶体管T5的第一极连接第一电源信号端VDD，第二极连接驱动晶体管T3的第二极，栅极连接使能信号端EM；第六晶体管T6第一极连接驱动晶体管T3的第一极，栅极连接使能信号端EM；第七晶体管T7的第一极连接初始化信号端Vinit，第二极连接第六晶体管T6的第二极。该像素驱动电路可以连接一发光单元OLED，用于驱动该发光单元OLED发光，发光单元OLED可以连接于第六晶体管T6的第二极和第二电源端VSS之间。其中，晶体管T1-T7可以均为P型晶体管。
如图2所示，为图1像素驱动电路一种驱动方法中各节点的时序图。其中，Gate表示栅极驱动信号端Gate的时序，Re表示复位信号端Re的时序，EM表示使能信号端EM的时序，Da表示数据信号端Da的时序。该像素驱动电路的驱动方法可以包括复位阶段t1、补偿阶段t2，发光阶段t3。在复位阶段t1：复位信号端Re输出低电平信号，第一晶体管T1、第七晶体管T7导通，初始化信号端Vinit向节点N，第六晶体管T6的第二极输入初始化信号。在补偿阶段t2：栅极驱动信号端Gate输出低电平信号，第四晶体管T4、第二晶体管T2导通，同时数据信号端Da输出驱动信号以向节点N写入电压Vdata+Vth，其中Vdata为驱动信号的电压，Vth为驱动晶体管T3的阈值电压。发光阶段t3：使能信号端EM输出低电平信号，第六晶体管T6、第五晶体管T5导通，驱动晶体管T3在电容C存储的电压Vdata+Vth作用下发光。根据驱动晶体管输出电流公式I＝(μWCox/2L)(Vgs-Vth) 2，其中，μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电 压。本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth) 2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。
如图3、4所示，图3为相关技术中阵列基板的结构版图，图4为图3中沿虚线A的部分剖视图。图3所示的阵列基板可以形成图1所示的像素驱动电路。其中，如图3、4所示，在相关技术中，阵列基板包括衬底基板01，位于于衬底基板01一侧的有源层(包括有源部02)，位于有源层背离衬底基板一侧的第一栅极绝缘层03、位于第一栅极绝缘层03背离衬底基板一侧的第一栅极层(包括栅极部04)、位于第一栅极层背离衬底基板一侧的第二栅极绝缘层05、位于第二栅极绝缘层05背离衬底基板一侧的第二栅极层(包括栅极部06)。其中，有源部02可以形成图1中驱动晶体管T3的沟道区，栅极部04可以形成图1中驱动晶体管T3的栅极，栅极部06和栅极部04可以形成图1中的电容C。然而，栅极部06和栅极部04的版图面积有限，电容C的电容值往往不能达到预设的电容参数。
基于此，本示例性实施例提供一种阵列基板，如图5、6、7、8、9所示，图5为本公开阵列基板一种示例性实施例的部分结构版图，图6为图5中沿虚线A的剖视图，图7为图6中第一导电层的结构版图，图8为图6中第二导电层的结构版图，图9为图6中第三导电层的结构版图。其中，所述阵列基板可以包括像素驱动电路，所述像素驱动电路可以如图1所示。该阵列基板还可以包括：衬底基板0、第一导电层、第二导电层、第三导电层。第一导电层可以位于所述衬底基板0的一侧，所述第一导电层可以包括：第一导电部11、第二导电部12，所述第一导电部11可以用于形成所述驱动晶体管T3的栅极；所述第二导电部12在衬底基板0的正投影可以与所述第一导电部11在衬底基板0正投影不相交，所述第二导电部12可以用于形成电容C的部分第一电极；第二导电层可以设置于所述第一导电层背离所述衬底基板0的一侧，第二导电层可以包括第三导电部23，所述第三导电部23在所述衬底基板的正投影可以与所述第二导电部在衬底基板的正投影至少部分重合，且所述第三导电部23与所述第一导电部11电连接，所述第三导电部23可以用于形成所述电容C的第二电极；第三导电层可以设置于所述第二导电层背离所述衬底基板0的一侧，所述第三导电层可以包括第四导电部34，所述第四导电部34在所述衬底基板的正投影可以与所述第三导电部23衬底基板的正投影至少部分重合，且所述第四导电部34可以与所述第二导电部12电连接，所述第四导电部34可以用于形成所述电容C的部分第一电极。
本示例性实施例中，第三导电部23可以作为电容C的第二电极，第二导电部12和第四导电部34可以共同作为电容C的第一电极。第三导电部23可以分别与第二导电部12、第四导电部34形成平行板电容结构，即电容C可以由上述两个平行板电容结构并联组成，从而电容C具有较大的电容值。
应该理解的是，在其他示例性实施例中，本公开阵列基板中的像素驱动电路还可以为其他结构。只要像素驱动电路中包括有驱动晶体管以及连接于该驱动晶体管栅极的电容， 阵列基板均可以通过上述结构实现较大电容值的电容。
本示例性实施例中，如图6所示，该阵列基板还可以包括位于第一导电层和第二导电层之间的第一栅极绝缘层4，以及位于第二导电层和第三导电层之间的介电层5。其中，第一栅极绝缘层4可以为氧化硅层，介电层5可以为氮化硅层。第一导电层、第二导电层、第三导电层均可以通过至少一层金属层形成。例如，第一导电层、第二导电层、第三导电层均可以通过第一钛层、铝层、第二钛层依次层叠形成。衬底基板可以通过绝缘材料形成，例如，衬底基板可以包括依次设置的第一聚酰亚胺(PI)层、第一氧化硅(SiO)层、非晶硅层、第二聚酰亚胺(PI)层、第二氧化硅层。
本示例性实施例中，如图5、6所示，所述第一导电部11所述衬底基板的正投影和所述第三导电部23在所述衬底基板的正投影可以在第一方向X上间隔分布。第三导电部23可以包括有第二子导电部232，第二子导电部232在衬底基板的正投影与第四导电部34在衬底基板的正投影不相交。所述第三导电层还可以包括第一连接部31。第一连接部31在所述衬底基板的正投影可以沿所述第一方向X延伸，所述第一连接部31可以通过过孔92与所述第一导电部11电连接，且所述第一连接部31可以通过过孔91与第二子导电部232电连接。结合图1，第一导电部11实质用于连接驱动晶体管T3的栅极和电容C的第二电极。
本示例性实施例中，如图5、6、8所示，所述第四导电部34可以包括第一子导电部341；所述第一子导电部341在所述衬底基板的正投影可以与所述第三导电部23在所述衬底基板的正投影不相交，且所述第一子导电部341在所述衬底基板的正投影与所述第二导电部12在所述衬底基板的正投影至少部分重合。所述第一子导电部341可以通过过孔93与所述第二导电部12电连接，从而实现第四导电部34和第二导电部12电连接。应该理解的是，在其他示例性实施例中，第四导电部34和第二导电部12还可以通过其他结构连接，例如，第四导电部34可以通过贯穿第三导电部23的过孔电连接第二导电部12，且与第三导电部23绝缘。
本示例性实施例中，如图5、6、10所示，图10为图5中有源层的版图结构。本示例性实施例中，该阵列基板还可以包括有源层，有源层可以位于衬底基板和第一导电层之间。如图5、6、10所示，所述有源层可以包括：第六有源部66，第六有源部66在所述衬底基板的正投影可以为条形，且沿所述第二方向Y延伸，所述第六有源部66可以用于形成所述驱动晶体管T3的沟道区。第一导电部11也可以为沿第二方向Y延伸的条形结构，第一导电部11在衬底基板的正投影可以覆盖第六有源部66在衬底基板的正投影。其中，第二方向Y可以与第一方向X相交，例如，第二方向Y可以与第一方向垂直。本示例性实施例将驱动晶体管T3的沟道区设置为沿第二方向延伸的条形结构，从而可以减小驱动晶体管T3在第一方向的尺寸，以便在第一方向X上预留出用于设置电容C的空间。具体的，第六有源部66和第一导电部11可以为矩形、圆角矩形等结构。所述第一导电部11在衬底基板的正投影在所述第二方向上的尺寸可以为其在所述第一方向上尺寸的2.5-5倍， 例如，2.2倍、3.5倍、4倍、5倍。此外，如图6所示，该阵列基板还可以包括位于有源层和第一导电层之间第二栅极绝缘层7，第二栅极绝缘层7同样可以为氧化硅层。
本示例性实施例中，如图11、12、13、14、15所示，图11为本公开阵列基板另一种示例性实施例的结构版图，图12为图11中有源层的结构版图，图13为图11中第一导电层的结构版图，图14为图11中第二导电层的结构版图，图15为图11中第三导电层的结构版图。
图11所示的阵列基板可以包括图5-10所示阵列基板的任意结构。基于图5-10所示的阵列基板，如图11、15所示，所述第三导电层还可以包括电源线321，电源线321可以沿所述第一方向X延伸，所述第三导电部23在所述衬底基板正投影可以位于所述电源线321在所述衬底基板的正投影在第二方向Y的一侧。其中，所述第四导电部34可以与所述电源线321电连接，且所述第四导电部34在所述衬底基板的正投影可以位于所述电源线321在所述衬底基板正投影在所述第二方向Y的一侧。该电源线321可以用于提供图1中的第一电源端信号VDD，以向电容C的第一电极提供电源信号。
本示例性实施例中，如图11、13所示，所述阵列基板可以包括多个所述像素驱动电路；所述第一导电层可以包括多个所述第二导电部12，多个所述第二导电部12在所述衬底基板的正投影沿所述第二方向Y间隔分布。本示例性实施例中，如图11、15所示，所述第三导电层可以包括多条电源线，多条所述电源线可以沿所述第二方向Y间隔分布，多条所述电源线可以包括相邻的电源线321和电源线322，所述电源线322在所述衬底基板的正投影可以位于所述电源线321在所述衬底基板正投影在所述第二方向Y的一侧。所述第二导电部12可以通过上述的第一子导电部341和电源线321电连接，同时，所述第二导电部12还可以通过过孔94和电源线322电连接。第二导电部12同时与相邻的两条电源线连接，从而可以改善第二导电部12上电源电压的均匀性。
本示例性实施例中，该阵列基板中的像素驱动电路还可以包括第一晶体管和第二晶体管。所述第二晶体管的第一极连接所述驱动晶体的第一极，第二极连接所述驱动晶体管的栅极。所述第一晶体管的第一极连接所述第二晶体管的第二极。例如，该第一晶体管可以为如图1中所示的第一晶体管T1，该第二晶体管可以为如图1中所示的第二晶体管T2。如图11、13所示，所述第一导电层还可以包括第一栅线13，第一栅线13可以用于提供图1中的栅极驱动信号端。第一栅线13在所述衬底基板的正投影可以沿所述第二方向Y延伸，且所述第一栅线13在所述衬底基板的正投影可以位于所述第一导电部11在所述衬底基板正投影与所述第二导电部12在所述衬底基板正投影之间，所述第一栅线13的部分导电部131可以用于形成所述第二晶体管T2的第一栅极。所述第一导电层还可以包括第二栅线14，第二栅线14可以用于提供图1中的复位信号端。第二栅线14在所述衬底基板的正投影沿所述第二方向Y延伸，且所述第二栅线14在所述衬底基板正投影可以位于所述第二导电部12在所述衬底基板正投影远离所述第一栅线13在所述衬底基板正投影的一侧，所述第二栅线14的部分导电部141可以用于形成所述第一晶体管T1的第一栅极， 所述第二栅线14的部分导电部142可以用于形成所述第一晶体管T1的第二栅极。
本示例性实施例中，如图11、12所示，所述有源层还可以包括第一有源部61，所述第一有源部61在所述衬底基板的正投影沿所述第一方向X延伸，所述第一有源部61可以用于电连接所述第二晶体管T2第二极和所述第一晶体管T1的第一极；其中，所述第一有源部61在所述衬底基板的正投影可以贯穿设置于相邻所述第二导电部12在所述衬底基板正投影之间的间隙。其中，形成有源层的原始材料可以为半导体，该阵列基板在制作过程中，可以通过第一导电层为掩膜版对有源层进行导体化处理，从而将晶体管沟道区以外的半导体结构转化为导通结构。将第二导电部12沿第二方向Y间隔设置，可以在相邻第二导电部12之间预留出用于走线第一有源部61的间隙。
本示例性实施例中，如图11、15所示，所述第三导电层还可以包括第五导电部35，第五导电部35可以连接于所述第四导电部34和所述电源线321之间，所述电源线321可以包括第一边沿3211，所述第五导电部35可以包括与所述第一边沿3211连接的第二边沿352，所述第一边沿3211在所述衬底基板的正投影和所述第二边沿352在所述衬底基板的正投影所成的夹角可以小于180°。即第五导电部35可以沿第二方向Y凸起于电源线321。其中，所述第五导电部35在所述衬底基板的正投影与所述第一有源部61在所述衬底基板的正投影至少部分重合。第五导电部35和第一有源部61可以形成平行板电容结构，且该平行板电容结构可以与第四导电部34、第三导电部23所形成的平行板电容结构形成并联结构，从而，该设置可以进一步增加电容C的电容值。
本示例性实施例中，如图11、13所示，所述第一导电层还可以包括：第六导电部16，第六导电部16在所述衬底基板的正投影可以沿所述第一方向X延伸，且连接于所述第一栅线13。具体的，如图13所示，第六导电部16可以自第一栅线13向第一方向X延伸。如图12所示，所述有源层还可以包括第二有源部62、第三有源部63、第四有源部64，所述第二有源部62在所述衬底基板的正投影位于所述第一栅线13在所述衬底基板的正投影上，所述第二有源部62可以用于形成所述第二晶体管T2的第一沟道区；第三有源部63在所述衬底基板正投影可以位于所述第六导电部16在所述衬底基板的正投影上，所述第三有源部63可以用于形成所述第二晶体管T2的第二沟道区。第四有源部64可以连接于所述第二有源部和所述第三有源部之间，且所述第四有源部64在所述衬底基板的正投影与所述第一导电层所述衬底基板的正投影均不相交。如图11所示，第二晶体管T2为双栅结构，双栅结构的第二晶体管T2具有较小的漏电流，从而可以降低像素驱动电路在发光阶段，电容C通过第二晶体管的漏电流。然而，由于第四有源部64为导体，第四有源部64与部分第一栅线13、第六导电部16之间形成寄生电容，当第一栅线13上的电压发生变化时，基于电容的自举效应，第四有源部64的电压也会发生相应的变化，从而导致第四有源部64向第二晶体管T2的源漏极漏电，最终导致像素驱动电路驱动异常。
本示例性实施例中，如图11、15所示，所述第三导电层还可以包括第七导电部37，第七导电部37可以连接所述第四导电部34，且所述第七导电部37在所述衬底基板的正 投影与所述第四有源部64在所述衬底基板的正投影至少部分重合。该设置可以使得第七导电部37与第四有源部64形成平行板电容结构，由于第七导电部37连接电源线，第七导电部37具有稳定的电压，从而第七导电部37可以抑制第四有源部64的电位变化，从而降低第四有源部64向第二晶体管T2源漏极的漏电流。
本示例性实施例中，如图11、12所示，所述有源层还可以包括：第五有源部65，第五有源部65可以连接于所述第三有源部63和所述第一有源部61之间。第五有源部65在衬底基板正投影可以沿第二方向延伸，且所述第五有源部65在所述衬底基板的正投影与所述第一导电层在所述衬底基板的正投影不相交；且所述第五有源部65在所述衬底基板的正投影与所述第一连接部31在所述衬底基板的正投影至少部分重合，且所述第五有源部65可以通过过孔95与所述第一连接部31电连接。该设置可以使得第二晶体管T2的第二极电连接驱动晶体管的栅极。
本示例性实施例中，如图11、12、15所示，所述有源层还可以包括：第七有源部67、第八有源部68、第九有源部69。第七有源部67在所述衬底基板的正投影可以位于所述所述第二栅线14在所述衬底基板的正投影上，用于形成所述第一晶体管T1的第一沟道区；第八有源部68在所述衬底基板的正投影可以位于所述所述第二栅线14在所述衬底基板的正投影上，用于形成所述第一晶体管T1的第二沟道区；第九有源部69可以连接于所述第七有源部67和所述第八有源部68之间。所述第九有源部69在所述衬底基板的正投影与所述第一导电层在所述衬底基板的正投影不相交，且第九有源部69在所述衬底基板的正投影可以位于第二栅线14在衬底基板正投影远离第一栅线13在衬底基板正投影的一侧。同样的，第一晶体管T1为双栅结构，双栅结构的第一晶体管T1具有较小的漏电流，从而可以降低像素驱动电路在发光阶段，电容C通过第一晶体管的漏电流。然而，由于第九有源部69为导体，第九有源部69与部分第二栅线14之间存在寄生电容，当第二栅线14上的电压发生变化时，基于电容的自举效应，第九有源部69的电压也会发生相应变化，从而导致第九有源部69向第一晶体管T1的源漏极漏电，最终导致像素驱动电路驱动异常。
本示例性实施例中，如图15所示，所述第三导电层还可以包括第八导电部38，第八导电部38可以电连接于所述电源线321，所述电源线321包括第三边沿3213，所述第八导电部38包括与所述第三边沿3213连接的第四边沿384，所述第三边沿3213在所述衬底基板的正投影和所述第四边沿384在所述衬底基板的正投影所成的夹角小于180°。即第八导电部38沿第二方向凸起于电源线321。所述第八导电部38在所述衬底基板的正投影可以与所述第九有源部69在所述衬底基板的正投影至少部分重合。该设置可以使得第八导电部38与第九有源部69形成平行板电容结构，由于第八导电部38连接电源线，第八导电部38具有稳定的电压，从而第八导电部38可以抑制第九有源部69的电位变化，从而降低第九有源部69向第一晶体管T1源漏极的漏电流。
本示例性实施例中，如图10、12所示，所述第六有源部66在所述衬底基板正投影在 所述第一方向X上的尺寸可以为所述第一栅线13在所述衬底基板正投影在所述第一方向上尺寸的1.1-1.5倍，例如，1.1倍、1.3倍、1.5倍。所述第一导电部11在所述衬底基板正投影在所述第一方向上的尺寸可以为所述第一栅线13在所述衬底基板正投影在所述第一方向上尺寸的1.5-2.5倍，例如，1.5倍、2倍、2.5倍。
如图11所示，本示例性实施例提供的阵列基板可以形成如图1所示的像素驱动电路。该阵列基板还可以包括第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7。
如图12所示，有源层还可以包括第十有源部610、第十一有源部611、第十二有源部612、第十三有源部613。其中，第十有源部610可以用于形成第四晶体管T4的沟道区；第十一有源部611可以用于形成第五晶体管T5的沟道区；第十二有源部612可以用于形成第六晶体管T6的沟道区；第十三有源部613可以用于形成第七晶体管的沟道区。
如图13所示，所述第一导电层还可以包括第三栅线17，第三栅线17可以用于提供图1中的使能信号端。第三栅线17在衬底基板的正投影可以位于第一导电部11在衬底基板正投影远离第一栅线13在衬底基板正投影的一侧。第一栅线13还可以包括导电部134，导电部134可以用于形成第四晶体管T4的栅极。第三栅线17可以包括导电部175和导电部176，导电部175可以用于形成第五晶体管的栅极，导电部176可以用于形成第六晶体管的栅极。其中，第七晶体管T7的栅极可以共用下一行像素单元对应第二栅线14中的导电部147。
如图15所示，第三导电层还可以包括第二连接部39、第三连接部310、数据线311。其中，第二连接部39可以通过过孔96连接第八有源部68一侧的有源层以连接第一晶体管T1的第二极。第三连接部310可以通过过孔97连接第十二有源部612和第十三有源部613之间的有源层，以连接第六晶体管T6的第二极和第七晶体管T7的第二极。第七晶体管T7的第一极可以连接下一行像素单元中的第二连接部39。数据线311可以通过过孔98与第四晶体管T4的第一极连接。如图15所示，本示例性实施例中，所述第三导电层可以包括多条数据线，例如第三导电层还可以包括数据线312，多条所述数据线在所述衬底基板的正投影沿所述第二方向Y间隔分布，且沿第一方向X延伸。图15中数据线312在所述衬底基板的正投影可以位于电源线322在所述衬底基板正投影和所述第四导电部34在所述衬底基板正投影之间。如图11所示，所述数据线312在所述衬底基板的正投影和与所述第二导电部12在所述衬底基板正投影至少部分重合。
如图16所示，为本公开阵列基板另一种示例性实施例的结构版图。该阵列基板还可以包括阳极层，如图17所示，为图16中阳极层的结构版图。其中，该阵列基板可以采用GGRB像素排布方式，阳极层可以包括第一阳极部81、第二阳极部82、第三阳极部83、第四阳极部84、阳极走线85。其中，第一阳极部81可以形成R子像素的阳极，第二阳极部82和第三阳极部83可以形成G子像素的阳极，第四阳极部8可以形成B子像素的阳极。第一阳极部81、第三阳极部83、第四阳极部84可以通过过孔连接同一行像素单元中的第三连接部310，以连接该行像素驱动电路中第七晶体管T7的第二极。第二阳极部82 可以连接相邻上一行像素单元中的第三连接部310，以连接该相邻上一行像素驱动电路中第七晶体管T7的第二极。阳极走线85可以连接同一行像素单元中的第二连接部39，用于提供图1中所示的初始化信号端Vinit。
本示例性实施例还提供一种显示装置，该显示装置包括上述的阵列基板。该显示装置可以为手机、平板电脑、电视等显示装置。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性远离并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (18)

  1. 一种阵列基板，其中，所述阵列基板包括像素驱动电路，所述像素驱动电路包括驱动晶体管、连接于所述驱动晶体管栅极的电容，该阵列基板还包括：
    衬底基板；
    第一导电层，位于所述衬底基板的一侧，所述第一导电层包括：
    第一导电部，所述第一导电部用于形成所述驱动晶体管的栅极；
    第二导电部，所述第二导电部在衬底基板正投影与所述第一导电部在衬底基板正投影不相交，所述第二导电部用于形成电容的部分第一电极；
    第二导电层，设置于所述第一导电层背离所述衬底基板的一侧，包括：
    第三导电部，所述第三导电部在所述衬底基板的正投影与所述第二导电部在衬底基板的正投影至少部分重合，且所述第三导电部与所述第一导电部电连接，所述第三导电部用于形成所述电容的第二电极；
    第三导电层，设置于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括：
    第四导电部，所述第四导电部在所述衬底基板的正投影与所述第三导电部在所述衬底基板的正投影至少部分重合，且所述第四导电部与所述第二导电部电连接，所述第四导电部用于形成所述电容的部分第一电极。
  2. 根据权利要求1所述的阵列基板，其中，所述第一导电部在所述衬底基板的正投影和所述第三导电部在所述衬底基板的正投影在第一方向上间隔分布，所述第三导电层还包括：
    第一连接部，在所述衬底基板的正投影沿所述第一方向延伸，所述第一连接部通过过孔与所述第一导电部电连接，且所述第一连接部通过过孔与所述第三导电部电连接。
  3. 根据权利要求2所述的阵列基板，其中，所述第四导电部包括第一子导电部；
    所述第一子导电部在所述衬底基板的正投影与所述第三导电部在所述衬底基板的正投影不相交，且所述第一子导电部在所述衬底基板的正投影与所述第二导电部在所述衬底基板的正投影至少部分重合；
    所述第一子导电部通过过孔与所述第二导电部电连接。
  4. 根据权利要求3所述的阵列基板，其中，所述第三导电层还包括：
    电源线，沿所述第一方向延伸，所述第三导电部在所述衬底基板正投影位于所述电源线在所述衬底基板的正投影在第二方向的一侧，所述第一方向与所述第二方向相交；
    其中，所述第四导电部与所述电源线电连接，且所述第四导电部在所述衬底基板的正投影位于所述电源线在所述衬底基板正投影在所述第二方向的一侧。
  5. 根据权利要求4所述的阵列基板，其中，所述阵列基板包括多个所述像素驱动电路；
    所述第一导电层包括多个所述第二导电部，多个所述第二导电部在所述衬底基板的正投影沿所述第二方向间隔分布。
  6. 根据权利要求5所述的阵列基板，其中，
    所述第三导电层包括多条所述电源线，多条所述电源线沿所述第二方向间隔分布，多条所述电源线包括相邻的第一电源线和第二电源线，所述第二电源线在所述衬底基板的正投影位于所述第一电源线在所述衬底基板正投影在所述第二方向的一侧；
    所述第二导电部通过所述第一子导电部和所述第一电源线电连接，且所述第二导电部通过过孔和所述第二电源线连接。
  7. 根据权利要求5所述的阵列基板，其中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极连接所述驱动晶体的第一极，第二极连接所述驱动晶体管的栅极，所述第一导电层还包括：
    第一栅线，在所述衬底基板的正投影沿所述第二方向延伸，且所述第一栅线在所述衬底基板的正投影位于所述第一导电部在所述衬底基板正投影与所述第二导电部在所述衬底基板正投影之间，部分所述第一栅线用于形成所述第二晶体管的栅极。
  8. 根据权利要求7所述的阵列基板，其中，所述像素驱动电路还包括第一晶体管，所述第一晶体管的第一极连接所述第二晶体管的第二极，所述第一导电层还包括：
    第二栅线，在所述衬底基板的正投影沿所述第二方向延伸，且所述第二栅线在所述衬底基板正投影位于所述第二导电部在所述衬底基板正投影远离所述第一栅线在所述衬底基板正投影的一侧，部分所述第二栅线用于形成所述第一晶体管的栅极。
  9. 根据权利要求8所述的阵列基板，其中，所述阵列基板还包括有源层，所述有源层设置于所述衬底基板和所述第一导电层之间，所述有源层包括：
    第一有源部，所述第一有源部在所述衬底基板的正投影沿所述第一方向延伸，所述第一有源部用于电连接所述第二晶体管第二极和所述第一晶体管的第一极；
    其中，所述第一有源部在所述衬底基板的正投影贯穿设置于相邻所述第二导电部在所述衬底基板正投影之间的间隙。
  10. 根据权利要求9所述的阵列基板，其中，所述第三导电层还包括：
    第五导电部，连接于所述第四导电部和所述电源线之间，所述电源线包括第一边沿，所述第五导电部包括与所述第一边沿连接的第二边沿，所述第一边沿在所述衬底基板的正投影和所述第二边沿在所述衬底基板的正投影所成的夹角小于180°；
    所述第五导电部在所述衬底基板的正投影与所述第一有源部在所述衬底基板的正投影至少部分重合。
  11. 根据权利要求9所述的阵列基板，其中，所述第一导电层还包括：
    第六导电部，所述第六导电部在所述衬底基板的正投影沿所述第一方向延伸，且连接于所述第一栅线；
    所述有源层还包括：
    第二有源部，所述第二有源部在所述衬底基板的正投影位于所述第一栅线在所述衬底基板的正投影上，所述第二有源部用于形成所述第二晶体管的第一沟道区；
    第三有源部，在所述衬底基板正投影位于所述第六导电部在所述衬底基板的正投影上，所述第三有源部用于形成所述第二晶体管的第二沟道区；
    第四有源部，连接于所述第二有源部和所述第三有源部之间，且所述第四有源部在所述衬底基板的正投影与所述第一导电层所述衬底基板的正投影均不相交；
    所述第三导电层还包括：
    第七导电部，连接所述第四导电部，且所述第七导电部在所述衬底基板的正投影与所述第四有源部在所述衬底基板的正投影至少部分重合。
  12. 根据权利要求11所述的阵列基板，其中，所述有源层还包括：
    第五有源部，连接于所述第三有源部和所述第一有源部之间，所述第五有源部在所述衬底基板的正投影与所述第一导电层在所述衬底基板的正投影不相交；
    且所述第五有源部在所述衬底基板的正投影与所述第一连接部在所述衬底基板的正投影至少部分重合，且所述第五有源部通过过孔与所述第一连接部电连接。
  13. 根据权利要求9所述的阵列基板，其中，所述有源层还包括：
    第六有源部，用于形成所述驱动晶体管的沟道区，所述第六有源部在所述衬底基板的正投影为条形，且沿所述第二方向延伸。
  14. 根据权利要求13所述的阵列基板，其中，所述第六有源部在所述衬底基板正投影在所述第一方向上的尺寸为所述第一栅线在所述衬底基板正投影在所述第一方向上尺寸的1.1-1.5倍。
  15. 根据权利要求13所述的阵列基板，其中，所述第一导电部在所述衬底基板的正投影为延伸所述第二方向延伸的条形，所述第一导电部在衬底基板的正投影在所述第二方向上的尺寸为其在所述第一方向上尺寸的2.5-5倍。
  16. 根据权利要求9所述的阵列基板，其中，所述有源层还包括：
    第七有源部，在所述衬底基板的正投影位于所述所述第二栅线在所述衬底基板的正投影上，用于形成所述第一晶体管的第一沟道区；
    第八有源部，在所述衬底基板的正投影位于所述所述第二栅线在所述衬底基板的正投影上，用于形成所述第一晶体管的第二沟道区；
    第九有源部，连接于所述第七有源部和所述第八有源部之间，且所述第九有源 部在所述衬底基板的正投影与所述第一导电层在所述衬底基板的正投影不相交；
    所述第三导电层还包括：
    第八导电部，电连接于所述电源线；
    所述电源线包括第三边沿，所述第八导电部包括与所述第三边沿连接的第四边沿，所述第三边沿在所述衬底基板的正投影和所述第四边沿在所述衬底基板的正投影所成的夹角小于180°；
    所述第八导电部在所述衬底基板的正投影与所述第九有源部在所述衬底基板的正投影至少部分重合。
  17. 根据权利要求6所述的阵列基板，其中，所述第三导电层还包括多条数据线，多条所述数据线在所述衬底基板的正投影沿所述第二方向间隔分布，且沿第一方向延伸；
    多条所述数据线包括第一数据线，所述第一数据线在所述衬底基板的正投影位于所述第二电源线在所述衬底基板正投影和所述第四导电部在所述衬底基板正投影之间；
    且所述第一数据线在所述衬底基板的正投影和与所述第二导电部在所述衬底基板正投影至少部分重合。
  18. 一种显示装置，其中，包括权利要求1-17任一项所述的阵列基板。
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