WO2023230871A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

Info

Publication number
WO2023230871A1
WO2023230871A1 PCT/CN2022/096331 CN2022096331W WO2023230871A1 WO 2023230871 A1 WO2023230871 A1 WO 2023230871A1 CN 2022096331 W CN2022096331 W CN 2022096331W WO 2023230871 A1 WO2023230871 A1 WO 2023230871A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
base substrate
orthographic projection
active
shielding
Prior art date
Application number
PCT/CN2022/096331
Other languages
English (en)
French (fr)
Other versions
WO2023230871A9 (zh
Inventor
张跳梅
宋江
徐元杰
陈军涛
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280001587.0A priority Critical patent/CN117501855A/zh
Priority to PCT/CN2022/096331 priority patent/WO2023230871A1/zh
Publication of WO2023230871A1 publication Critical patent/WO2023230871A1/zh
Publication of WO2023230871A9 publication Critical patent/WO2023230871A9/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • display panels need to integrate circuit structures such as pixel driving circuits, gate driving circuits, and detection circuits, so that the display panel requires a large layout space to install the above circuit structures.
  • a display panel includes a pixel driving circuit including a transistor, and the display panel further includes: a base substrate, a first active layer, a shielding layer, the first active layer is located on one side of the base substrate, and at least part of the structure of the first active layer is used to form the channel region of the transistor; the shielding layer is located on the base substrate and the Between the first active layers, the shielding layer is a conductive layer, and the shielding layer includes a plurality of independently arranged shielding parts, and at least some of the different shielding parts are used to receive different signals.
  • the pixel driving circuit includes a driving transistor and a first transistor.
  • the first electrode of the first transistor is connected to the first initial signal line, and the second electrode is connected to the gate of the driving transistor. ;
  • the first initial signal line is included in the plurality of shielding parts.
  • the first active layer includes a first active part and a third sub-active part, and the first active part is used to form a channel region of the first transistor.
  • the first active part includes a first sub-active part and a second sub-active part, the third sub-active part is connected to the first sub-active part and the second sub-active part between;
  • the first initial signal line includes a first extension portion, and the orthographic projection of the first extension portion on the base substrate is the same as the orthogonal projection of the third sub-active portion on the base substrate. The projections at least partially overlap.
  • the display panel further includes: a first conductive layer, the first conductive layer is located on a side of the first active layer away from the base substrate, the first conductive layer It includes a first reset signal line, and the orthographic projection of the first reset signal line on the base substrate extends along the first direction and covers the orthographic projection of the first active part on the base substrate, so The partial structure of the first reset signal line is used to form the gate of the first transistor; the first initial signal line includes a second extension part, and the orthographic projection of the second extension part on the base substrate At least partially overlaps with the orthographic projection of the first reset signal line on the substrate.
  • the display panel further includes: a fourth conductive layer, the fourth conductive layer is located on a side of the first active layer away from the base substrate, the fourth conductive layer including a first initial connection line; wherein the orthographic projection of the first initial signal line on the base substrate extends along the first direction, and the orthographic projection of the first initial connection line on the base substrate extends along The second direction extends, the first direction and the second direction intersect, and the first initial connection line is connected to the first initial signal line that intersects its orthographic projection on the base substrate through a via hole.
  • the display panel further includes a light-emitting unit
  • the pixel driving circuit includes a seventh transistor, the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode is connected to the The first electrode of the light-emitting unit; the plurality of shielding parts include the second initial signal line.
  • the pixel driving circuit further includes a driving transistor and a sixth transistor.
  • the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the light-emitting transistor.
  • the first electrode of the unit; the first active layer includes a sixth active part and a seventh active part, the sixth active part is used to form a channel region of the sixth transistor, and the seventh active part
  • the active part is used to form the channel region of the seventh transistor;
  • the display panel also includes: a first conductive layer, the first conductive layer is located on a side of the first active layer facing away from the base substrate.
  • the first conductive layer includes: an enable signal line and a second reset signal line, the orthographic projection of the enable signal line on the base substrate extends along the first direction and covers the sixth active
  • the orthographic projection of the second reset signal line on the base substrate, and the partial structure of the enable signal line is used to form the gate of the sixth transistor;
  • the orthographic projection of the second reset signal line on the base substrate Extending along the first direction and covering the orthographic projection of the seventh active part on the base substrate, part of the structure of the second reset signal line is used to form the gate of the seventh transistor; wherein, the The orthographic projection of the second initial signal line on the base substrate is located between the orthographic projection of the enable signal line on the base substrate and the orthogonal projection of the second reset signal line on the base substrate. between projections.
  • the display panel further includes: a fourth conductive layer, the fourth conductive layer is located on a side of the first active layer away from the base substrate, the fourth conductive layer including a second initial connection line; wherein the orthographic projection of the second initial signal line on the substrate substrate extends along the first direction, and the orthographic projection of the second initial connection line on the substrate substrate extends along The second direction extends, the first direction and the second direction intersect, and the second initial connection line is connected to the second initial signal line that intersects its orthographic projection on the base substrate through a via hole.
  • the pixel driving circuit includes a driving transistor, the first active layer includes a third active part, and the third active part is used to form a channel of the driving transistor. area; the plurality of shielding parts includes a first shielding part, the first shielding part is connected to a stable voltage source, and the orthographic projection of the first shielding part on the base substrate covers the third The orthographic projection of the source part on the base substrate.
  • the pixel driving circuit further includes a capacitor, a first electrode of the capacitor is connected to the gate of the driving transistor, and a second electrode of the capacitor is connected to a power line;
  • the display panel It also includes: a first conductive layer, the first conductive layer is located on a side of the first active layer facing away from the base substrate, the first conductive layer includes a first conductive portion, the first conductive portion is located on the side of the first active layer facing away from the base substrate.
  • the orthographic projection on the base substrate covers the orthographic projection of the third active portion on the base substrate, and the first conductive portion is used to form the gate of the driving transistor and the first capacitor of the capacitor.
  • Electrode; the power line forms the stable voltage source, and the first shielding portion is used to form the second electrode of the capacitor.
  • the display panel further includes: a fourth conductive layer, the fourth conductive layer is located on a side of the first conductive layer facing away from the base substrate, the fourth conductive layer includes: The power line, the orthographic projection of the power line on the base substrate extends along the second direction; the display panel includes a plurality of pixel drivers distributed in an array in the first direction and the second direction. In the circuit, the first direction and the second direction intersect, a plurality of the first shielding parts distributed in the first direction are connected, and the power line is connected to the first shielding parts through a via hole.
  • the power cord includes a third extension part, a fourth extension part, and a fifth extension part connected between the third extension part and the fourth extension part, so
  • the dimension of the orthogonal projection of the fifth extension part on the base substrate in the first direction is greater than the dimension of the orthogonal projection of the third extension part on the base substrate in the first direction
  • the size of the orthogonal projection of the fifth extension part on the base substrate in the first direction is greater than the size of the orthogonal projection of the fourth extension part on the base substrate in the first direction, and the first direction intersects with the second direction
  • the orthographic projection of the fifth extension portion on the base substrate at least partially overlaps with the orthographic projection of the first conductive portion on the base substrate, and the fifth extension portion intersects with the second direction
  • At least part of the structure of the extension is used to form the second electrode of the capacitor.
  • the pixel driving circuit further includes a second transistor, a first electrode of the second transistor is connected to the gate of the driving transistor, and a second electrode of the second transistor is connected to the gate of the driving transistor.
  • the first active layer further includes a second active part and a sixth sub-active part, the second active part is used to form a channel region of the second transistor,
  • the second active part includes a fourth sub-active part and a fifth sub-active part, and the sixth sub-active part is connected between the fourth sub-active part and the fifth sub-active part.
  • the shielding layer further includes a second shielding part, the second shielding part is connected to the first shielding part, the first shielding part includes a first edge, and the second shielding part includes a second edge, The first edge and the second edge are connected, and the angle between the orthographic projection of the first edge on the base substrate and the orthographic projection of the second edge on the base substrate Less than 180°, the orthographic projection of the second shielding portion on the base substrate at least partially overlaps the orthographic projection of the sixth sub-active portion on the base substrate.
  • the pixel driving circuit further includes a first transistor and a second transistor.
  • the first electrode of the first transistor is connected to the first initial signal line, and the second electrode is connected to the driving transistor.
  • a gate electrode, the first electrode of the second transistor is connected to the gate electrode of the driving transistor, and the second electrode is connected to the second electrode of the driving transistor;
  • the first active layer also includes a first active part, a third Two active parts and an eighth active part, the first active part is used to form a channel region of the first transistor, and the second active part is used to form a channel region of the second transistor.
  • the eighth active part is connected between the first active part and the second active part;
  • the shielding layer further includes a third shielding part, the third shielding part is connected to the A shielding part, the first shielding part includes a first edge, the third shielding part includes a third edge, the first edge and the third edge are connected, and the first edge is on the substrate
  • the angle between the orthographic projection of the third edge on the base substrate and the orthographic projection of the third edge on the base substrate is less than 180°, and the orthographic projection of the third shielding portion on the base substrate and the orthographic projection of the third edge on the base substrate are less than 180°.
  • Orthographic projections of the eight active parts on the base substrate at least partially overlap.
  • the pixel driving circuit further includes a first transistor and a second transistor.
  • the first electrode of the first transistor is connected to the first initial signal line, and the second electrode is connected to the driving transistor.
  • a gate electrode, the first electrode of the second transistor is connected to the gate electrode of the driving transistor, and the second electrode is connected to the second electrode of the driving transistor;
  • the first active layer also includes a first active part, a third two active parts, a sixth sub-active part, and an eighth active part.
  • the first active part is used to form a channel region of the first transistor, and the second active part is used to form the channel region of the first transistor.
  • the channel region of the second transistor, the second active part includes a fourth sub-active part and a fifth sub-active part, the sixth sub-active part is connected to the fourth sub-active part and the between the fifth sub-active parts, the eighth active part is connected between the first active part and the second active part;
  • the display panel also includes a first conductive layer, the A first conductive layer is located on a side of the first active layer facing away from the substrate.
  • the first conductive layer includes a first conductive portion and a first gate line. The first conductive portion is on the substrate.
  • the orthographic projection on the substrate covers the orthographic projection of the third active part on the substrate, and the orthographic projection of the first gate line on the substrate extends along the first direction and covers the third Orthographic projection of two active parts on the base substrate;
  • the shielding layer also includes a second shielding part, a third shielding part, and a first connecting part, and the second shielding part is connected to the first shielding part , the orthographic projection of the second shielding part on the base substrate at least partially overlaps the orthographic projection of the sixth sub-active part on the base substrate;
  • the third shielding part is connected to the The first shielding part, the orthographic projection of the third shielding part on the base substrate at least partially overlaps the orthographic projection of the eighth active part on the base substrate;
  • the first connection The part is connected between the second shielding part and the third shielding part in the adjacent pixel driving circuit in the first direction, and the orthographic projection of the first connection part on the base substrate is located at The orthographic projection of the first gate line on the base substrate is away from the ortho
  • the display panel further includes a display area and a frame area located around the display area, part of the shielding part is located in the display area, and part of the shielding part is located in the frame area.
  • the pixel driving circuit includes a plurality of transistors, and the plurality of shielding parts includes a constant voltage shielding part corresponding to the transistor, and the constant voltage shielding part is located on the substrate
  • the orthographic projection on the substrate and the orthographic projection of the corresponding channel region of the transistor on the substrate at least partially overlap; at least partially different constant voltage shielding portions are used to receive different power supply voltages.
  • the pixel driving circuit includes an N-type transistor and a P-type transistor;
  • the plurality of constant voltage shielding parts include a positive pressure shielding part and a negative pressure shielding part, and the positive voltage shielding part is used to receive a positive power supply voltage, and the negative voltage shielding part is used to receive a negative power supply voltage;
  • the orthographic projection of the positive voltage shielding part on the base substrate is consistent with the P-type transistor channel region on the The orthographic projections on the base substrate at least partially overlap, and the orthographic projection of the negative pressure shielding portion on the base substrate at least partially intersects the orthographic projection of the N-type transistor channel region on the base substrate.
  • the display panel further includes a light-emitting unit
  • the pixel driving circuit includes a driving transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor.
  • the four transistors, the fifth transistor, the sixth transistor, and the seventh transistor are P-type transistors; the first electrode of the fourth transistor is connected to the data line, and the second electrode is connected to the first electrode of the driving transistor; the fifth transistor The first pole of the sixth transistor is connected to the first power terminal, and the second pole is connected to the first pole of the driving transistor; the first pole of the sixth transistor is connected to the second pole of the driving transistor, and the second pole is connected to the light-emitting unit.
  • the plurality of constant voltage shielding parts include a plurality of positive voltage shielding parts
  • the plurality of positive pressure shielding parts include: a first positive pressure shielding part, a second positive pressure shielding part, and a third positive pressure shielding part
  • the first positive pressure shielding part is on the positive side of the base substrate.
  • the projection covers the orthographic projection of the driving transistor channel region on the base substrate; the orthographic projection of the second positive pressure shielding portion on the base substrate covers the fifth transistor channel region on the base substrate.
  • the orthographic projection on the base substrate, the orthographic projection of the sixth transistor channel region on the base substrate; the orthographic projection of the third positive pressure shielding portion on the base substrate covers the fourth transistor trench.
  • the two positive voltage shielding parts are used to receive a positive voltage
  • the third positive voltage shielding part is used to receive a positive voltage that is greater than the positive voltage that the first positive voltage shielding part is used to receive.
  • the display panel includes a high-density integration area and a low-density integration area, and the density of transistors in the high-density integration area is greater than the density of transistors in the low-density integration area; the high-density integration area
  • the density integration area includes a first high-density integration area and a second high-density integration area, and the second high-density integration area is located on a side of the first high-density integration area away from the low-density integration area; in the pixel Among the constant voltage shielding parts corresponding to the same transistor in the drive circuit, the absolute value of the voltage received by the constant voltage shielding part located in the first high-density integration area is greater than the constant voltage located in the second high-density integration area.
  • the shield is used to receive the absolute value of the voltage.
  • a display device which includes the above-mentioned display panel.
  • Figure 1 is a schematic circuit structure diagram of a pixel driving circuit in an exemplary embodiment of the display panel of the present disclosure
  • Figure 2 is a timing diagram of signals on each node in a driving method of the pixel driving circuit shown in Figure 1;
  • Figure 3 is a structural layout of a display panel in an exemplary embodiment of the present disclosure
  • Figure 4 is the structural layout of the occlusion layer in Figure 3;
  • Figure 5 is a structural layout of the first active layer in Figure 3;
  • Figure 6 is a structural layout of the first conductive layer in Figure 3;
  • Figure 7 is a structural layout of the fourth conductive layer in Figure 3.
  • Figure 8 is a structural layout of the fifth conductive layer in Figure 3.
  • Figure 9 is a structural layout of the occlusion layer and the first active layer in Figure 3;
  • Figure 10 is a structural layout of the shielding layer, the first active layer, and the first conductive layer in Figure 3;
  • Figure 11 is a structural layout of the shielding layer, the first active layer, the first conductive layer, and the fourth conductive layer in Figure 3;
  • Figure 12 is a partial cross-sectional view of the display panel shown in Figure 3 taken along the dotted line AA;
  • Figure 13 is a structural layout of another exemplary embodiment of a display panel of the present disclosure.
  • Figure 14 is the structural layout of the occlusion layer in Figure 13;
  • Figure 15 is a structural layout of the barrier layer and the first active layer in Figure 13;
  • Figure 16 is a structural layout of another exemplary embodiment of a display panel of the present disclosure.
  • Figure 17 is a structural layout of the fourth conductive layer in Figure 16;
  • Figure 18 is a structural layout of the fifth conductive layer in Figure 16;
  • Figure 19 is a structural layout of the shielding layer, the first active layer, the first conductive layer, and the fourth conductive layer in Figure 16;
  • Figure 20 is a structural layout of another exemplary embodiment of a display panel of the present disclosure.
  • Figure 21 is the structural layout of the occlusion layer in Figure 20;
  • Figure 22 is a structural layout of the fourth conductive layer in Figure 20;
  • Figure 23 is a structural layout of the shielding layer, the first active layer, the first conductive layer, and the fourth conductive layer in Figure 20;
  • Figure 24 is a structural layout of another exemplary embodiment of a display panel of the present disclosure.
  • Figure 25 is a structural layout of the fourth conductive layer in Figure 24;
  • Figure 26 is a structural layout of the fifth conductive layer in Figure 24;
  • Figure 27 is a structural layout of the shielding layer, the first active layer, the first conductive layer, and the fourth conductive layer in Figure 24;
  • Figure 28 is a schematic structural diagram of an exemplary embodiment of a display panel of the present disclosure.
  • Figure 29 is a schematic circuit structure diagram of a pixel driving circuit in another exemplary embodiment of the display panel of the present disclosure.
  • Figure 30 is a timing diagram of each node in a driving method of the pixel driving circuit in Figure 29;
  • Figure 31 is a structural layout of a display panel in another exemplary embodiment of the present disclosure.
  • Figure 32 is the structural layout of the occlusion layer in Figure 31;
  • Figure 33 is a structural layout of the first active layer in Figure 31;
  • Figure 34 is a structural layout of the first conductive layer in Figure 31;
  • Figure 35 is a structural layout of the second conductive layer in Figure 31;
  • Figure 36 is a structural layout of the second active layer in Figure 31;
  • Figure 37 is a structural layout of the third conductive layer in Figure 31;
  • Figure 38 is a structural layout of the fourth conductive layer in Figure 31;
  • Figure 39 is the structural layout of the fifth conductive layer in Figure 27;
  • Figure 40 is a structural layout of the occlusion layer and the first active layer in Figure 31;
  • Figure 41 is a structural layout of the shielding layer, the first active layer, and the first conductive layer in Figure 31;
  • Figure 42 is a structural layout of the shielding layer, the first active layer, the first conductive layer, and the second conductive layer in Figure 31;
  • Figure 43 is a structural layout of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in Figure 31;
  • Figure 44 is a structural layout of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer and the third conductive layer in Figure 31;
  • Figure 45 is a structural layout of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer and the fourth conductive layer in Figure 31;
  • Figure 46 is a structural layout of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer in Figure 31;
  • Figure 47 is a partial cross-sectional view along the dotted line BB in Figure 31;
  • Figure 48 is another exemplary structural schematic diagram of a display panel of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments. To those skilled in the art.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C.
  • the first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, the second electrode is connected to the node N, and the gate is connected to the first reset signal terminal Re1; the first electrode of the second transistor T2 is connected to the node N, and the second electrode is connected to the node N.
  • the second pole of the drive transistor T3; the gate is connected to the first gate drive signal terminal G1; the gate of the drive transistor T3 is connected to the node N; the first pole of the fourth transistor T4 is connected to the data signal terminal Da, and the second pole is connected to the drive transistor
  • the first electrode of T3, the gate is connected to the first gate drive signal terminal G1; the first electrode of the fifth transistor T5 is connected to the first power terminal VDD, the second electrode is connected to the first electrode of the drive transistor T3, and the gate is connected to the enable The signal terminal EM; the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, and the gate electrode is connected to the enable signal terminal EM; the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the second electrode is connected to the second initial signal terminal Vinit2.
  • the second electrode and gate of the six-transistor T6 are connected to the second reset signal terminal Re2.
  • the capacitor C is connected between the gate of the driving transistor T3 and the first power terminal VDD.
  • the pixel driving circuit can be connected to a light-emitting unit OLED.
  • the pixel driving circuit is used to drive the light-emitting unit OLED to emit light.
  • the light-emitting unit OLED can be connected between the second pole of the sixth transistor T6 and the second power terminal VSS.
  • the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may all be P-type transistors.
  • FIG. 2 it is a timing diagram of signals on each node in a driving method of the pixel driving circuit shown in Figure 1.
  • G1 represents the timing diagram of the signal on the first gate drive signal terminal G1
  • Re1 represents the timing diagram of the signal on the first reset signal terminal Re1
  • Re2 represents the timing diagram of the signal on the second reset signal terminal Re2
  • EM represents enable
  • Da represents the timing diagram of the signal on the data signal terminal Da.
  • the driving method of the pixel driving circuit may include a reset phase t1, a compensation phase t2, and a light emitting phase t3.
  • the first reset signal terminal Re1 outputs a low-level signal
  • the first transistor T1 is turned on
  • the first initial signal terminal Vinit1 inputs the first initial signal to the node N.
  • the compensation phase t2 the second reset signal terminal Re2 and the first gate drive signal terminal G1 output low-level signals
  • the fourth transistor T4, the second transistor T2, and the seventh transistor T7 are turned on, and the data signal terminal Da outputs data at the same time.
  • the signal writes voltage Vdata+Vth to node N, where Vdata is the voltage of the data signal, Vth is the threshold voltage of the driving transistor T3, and the second initial signal terminal Vini2 inputs the second initial signal to the second pole of the sixth transistor T6.
  • the enable signal terminal EM outputs a low-level signal
  • the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the voltage Vdata+Vth of the node N.
  • the driving transistor output current formula I ( ⁇ WCox/2L)(Vgs-Vth)2, where ⁇ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, and L driver The length of the transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor.
  • the pixel driving circuit can avoid the influence of the driving transistor threshold on its output current. It should be understood that in other exemplary embodiments, the pixel driving circuit may also have other driving methods. For example, the first transistor T1 and the seventh transistor T7 may both be turned on during the reset phase.
  • This exemplary embodiment also provides a display panel, which may include a base substrate, a shielding layer, a first active layer, a first conductive layer, a fourth conductive layer, and a fifth conductive layer that are stacked in sequence, wherein , an insulating layer may be provided between the above adjacent levels.
  • a display panel which may include a base substrate, a shielding layer, a first active layer, a first conductive layer, a fourth conductive layer, and a fifth conductive layer that are stacked in sequence, wherein , an insulating layer may be provided between the above adjacent levels.
  • Figure 3 is a structural layout of a display panel in an exemplary embodiment of the present disclosure.
  • Figure 4 is a structural layout of the shielding layer in Figure 3.
  • Figure 5 is a structural layout of the first active layer in Figure 3.
  • Figure 6 is the structural layout of the first conductive layer in Figure 3
  • Figure 7 is the structural layout of the fourth conductive layer in Figure 3
  • Figure 8 is the structural layout of the fifth conductive layer in Figure 3
  • Figure 9 is the structural layout of Figure 3
  • Figure 10 is the structural layout of the shielding layer, the first active layer and the first conductive layer in Figure 3.
  • Figure 11 is the structural layout of the shielding layer and the first active layer in Figure 3.
  • the display panel may include a plurality of pixel driving circuits shown in FIG. 1 .
  • the shielding layer may be a conductive layer, and the shielding layer may include a plurality of first initial signal lines Vinit1, second initial signal lines Vinit2, first shielding parts 61, second shielding parts 62, Three shielding parts 63.
  • the orthographic projection of the first initial signal line Vinit1 on the base substrate and the orthographic projection of the second initial signal line Vinit2 on the base substrate can both extend along the first direction X.
  • the first initial signal line Vinit1 may be used to provide the first initial signal terminal in FIG. 1
  • the second initial signal line Vinit2 may be used to provide the second initial signal terminal in FIG. 1 .
  • the first shielding part 61 is connected to the second shielding part 62 and the third shielding part 63 respectively.
  • the first shielding parts 61 spaced apart in the first direction X may be connected in sequence.
  • the first shielding part 61 may include a first edge 611
  • the second shielding part 62 may include a second edge 622
  • the third shielding part 63 may include a third edge 633 .
  • the first edge 611 and the second edge 622 are connected, and the angle between the orthographic projection of the first edge 611 on the base substrate and the orthographic projection of the second edge 622 on the base substrate may be less than 180°, for example, the first The angle included between the orthographic projection of the edge 611 on the base substrate and the orthographic projection of the second edge 622 on the base substrate may be 90°.
  • the first edge 611 and the third edge 633 are connected, and the angle between the orthographic projection of the first edge 611 on the base substrate and the orthographic projection of the third edge 633 on the base substrate may be less than 180°, for example, the first The angle included between the orthographic projection of the edge 611 on the base substrate and the orthographic projection of the third edge 633 on the base substrate may be 90°.
  • the first active layer may include a first active portion 71, a second active portion 72, a third active portion 73, a fourth active portion 74, and a fifth active portion. 75.
  • the sixth active part 76 and the seventh active part 77 are used to form the first active part 71 and the second active part 72 .
  • the first active part 71 is used to form the channel region of the first transistor T1
  • the second active part 72 is used to form the channel region of the second transistor T2
  • the third active part 73 is used to form the driving transistor T3.
  • the fourth active part 74 is used to form the channel region of the fourth transistor T4
  • the fifth active part 75 is used to form the channel region of the fifth transistor T5
  • the sixth active part 76 is used to form the channel region of the fourth transistor T4.
  • the channel region of the sixth transistor T6 and the seventh active portion 77 are used to form the channel region of the seventh transistor T7.
  • the first active part 71 may include a first sub-active part 711 and a second sub-active part 712, and the first active layer further includes a layer connected to the first sub-active part 711 and the second sub-active part 712. The third sub-active part 713 between them.
  • the second active part 72 may include a fourth sub-active part 724 and a fifth sub-active part 725 , and the first active layer further includes a layer connected between the fourth sub-active part 724 and the fifth sub-active part 725 The sixth sub-active part 726.
  • the first active layer may further include an eighth active part 78, a ninth active part 79, a tenth active part 710, a fourteenth active part 714, a fifteenth active part 715, a sixteenth active part Department 716.
  • the eighth active part 78 is connected between the first active part 71 and the second active part 72
  • the ninth active part 79 is connected to one end of the fifth active part 75 and the third active part 73
  • the tenth active part 79 is connected to one end of the third active part 73 .
  • the source part 710 is connected between the sixth active part 76 and the seventh active part 77 , the sixteenth active part 716 is connected to an end of the fourth active part 74 away from the third active part 73 , and the fourteenth active part 710 has The source part 714 is connected to an end of the seventh active part 77 away from the sixth active part 76 , and the fifteenth active part 715 is connected to an end of the first active part 71 away from the second active part 72 .
  • the first active layer may be formed of polysilicon material.
  • the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P. low temperature polysilicon thin film transistor.
  • the first conductive layer may include a first reset signal line Re1, a first gate line G1, an enable signal line EM, a second reset signal line Re2, and a first conductive portion 11.
  • the orthographic projection of Re2 on the base substrate may extend along the first direction X.
  • the orthographic projection of a certain structure on the base substrate extends along a certain direction. It can be understood that the orthographic projection of the structure on the base substrate extends straightly or in a bend along the direction.
  • the orthographic projection of the first reset signal line Re1 on the base substrate can cover the orthographic projection of the first active part 71 on the base substrate, and part of the structure of the first reset signal line Re1 can be used to form the gate of the first transistor T1 pole, the first reset signal line Re1 may be used to provide the first reset signal terminal in the pixel driving circuit shown in FIG. 1 .
  • the orthographic projection of the second reset signal line Re2 on the base substrate can cover the orthographic projection of the seventh active part 77 on the base substrate, and part of the structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7 pole, the second reset signal line Re2 may be used to provide a second reset signal terminal in the pixel driving circuit shown in FIG. 1 .
  • the orthographic projection of the first gate line G1 on the base substrate can cover the orthographic projection of the second active portion 72 on the base substrate and the orthographic projection of the fourth active portion 74 on the base substrate.
  • the first gate line G1 Part of the structure of the first gate line G1 may be used to form the gate of the second transistor T2.
  • Another part of the structure of the first gate line G1 may be used to form the gate of the fourth transistor T4.
  • the first gate line G1 may be used to provide the pixel shown in FIG. 1
  • the orthographic projection of the enable signal line EM on the base substrate can cover the orthographic projection of the fifth active part 75 on the base substrate and the orthographic projection of the sixth active part 76 on the base substrate.
  • the enable signal line EM Part of the structure of can be used to form the gate of the fifth transistor T5, and another part of the structure of the enable signal line EM can be used to form the gate of the sixth transistor T6.
  • the enable signal line EM can be used to provide the pixel shown in Figure 1
  • the enable signal terminal in the drive circuit can cover the orthographic projection of the third active part 73 on the base substrate, and the first conductive part 11 can be used to form the gate of the driving transistor T3 and the third capacitor C.
  • the display panel can use the first conductive layer as a mask to conduct conduction processing on the first active layer, that is, the area of the first active layer covered by the first conductive layer can form the channel region of the transistor, and the first Areas of the active layer not covered by the first conductive layer form conductor structures.
  • the orthographic projection of the first shielding part 61 on the substrate may be the same as the orthographic projection of the third active part 73 on the substrate.
  • Overlapping, for example, the orthographic projection of the first shielding part 61 on the base substrate can cover the orthographic projection of the third active part 73 on the base substrate, and the first shielding part 61 can be connected to a stable voltage source, for example, A shielding part 61 can be connected to the first power terminal VDD, the first initial signal terminal Vinit1, the second initial signal terminal Vinit2, etc. in FIG. 1 .
  • the first shielding part 61 may be used to shield the noise influence of other signals on the driving transistor T3.
  • the first shielding part 61 When the first shielding part 61 is connected to the first power terminal VDD, the first shielding part 61 may also be used to form the second electrode of the capacitor C.
  • the orthographic projection of the second shielding portion 62 on the base substrate and the orthographic projection of the sixth sub-active portion 726 on the base substrate at least partially overlap, and the second shielding portion 62 can play a role in affecting the sixth sub-active portion 726
  • the voltage stabilizing effect can reduce the leakage current of the sixth sub-active part 726 to the source and drain of the second transistor caused by the voltage fluctuation of the sixth sub-active part 726 .
  • the orthographic projection of the third shielding part 63 on the base substrate may at least partially overlap with the orthographic projection of the eighth active part 78 on the base substrate, and the third shielding part 63 may stabilize the eighth active part 78 .
  • the first initial signal line Vinit1 includes a first extension part Vinit11 and a second extension part Vinit12 .
  • the orthographic projection of the first extension part Vinit11 on the substrate can be the same as the third sub-active part 713 on the substrate.
  • the orthographic projections on the substrate at least partially overlap, and the first extension part Vinit11 can stabilize the voltage of the third sub-active part 713, thereby reducing the voltage fluctuation of the third sub-active part 713 due to the voltage fluctuation of the third sub-active part.
  • the source part 713 leaks current to the source and drain of the first transistor.
  • the orthographic projection of the second extension part Vinit12 on the base substrate may at least partially overlap with the orthographic projection of the first reset signal line Re1 on the base substrate, thereby improving the transmittance of the display panel.
  • the fourth conductive layer may include a first initial connection line 4Vinit1, a power line VDD, a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, and a fourth bridge portion 44.
  • the orthographic projection of the first initial connection line 4Vinit1 on the base substrate and the orthographic projection of the power line VDD on the base substrate can both extend along the second direction Y, and the second direction Y can intersect the first direction X, for example , the second direction Y may be the column direction, and the first direction X may be the row direction.
  • the first initial connection line Vinit1 can be connected to the first initial signal line Vinit1 and the fifteenth active part 715 through the via hole H respectively, so as to connect the first initial signal terminal and the first electrode of the first transistor.
  • the black square in the attached figure indicates the location of the via hole.
  • the first initial connection line 4Vinit1 and the first initial signal line Vinit1 may form a grid structure, and the grid structure may reduce the voltage difference between the first initial signal terminals at different positions of the display panel.
  • the power line VDD can provide the first power terminal, and the power line VDD can be connected to the first shielding portion 61 and the ninth active portion 79 through via holes respectively to connect the second electrode of the capacitor, the first power terminal, and the third of the fifth transistor.
  • the power line VDD may include a third extension part VDD3, a fourth extension part VDD4, and a fifth extension part VDD5.
  • the fifth extension part VDD5 is connected to the third extension part VDD3 and the fourth extension part.
  • the size of the orthographic projection of the fifth extension part VDD5 on the base substrate in the first direction X is greater than the size of the orthogonal projection of the third extension part VDD3 on the base substrate in the first direction X.
  • the fifth The size of the orthogonal projection of the extension portion VDD5 on the base substrate in the first direction X is greater than the size of the orthogonal projection of the fourth extension portion VDD4 on the base substrate in the first direction X.
  • the orthographic projection of the fifth extension portion VDD5 on the base substrate can also at least partially overlap with the orthographic projection of the first conductive portion 11 on the base substrate.
  • the fifth extension portion VDD5 can also be used to form the second electrode of the capacitor C.
  • the area of the orthographic projection of the first conductive part 11 on the base substrate is S1
  • the overlapping area of the orthographic projection of the first conductive part 11 on the base substrate and the orthographic projection of the fifth extension part VDD5 on the base substrate is S2, S2/S1 can be greater than or equal to 60%, for example, S2/S1 can be equal to 60%, 70%, 80%, 90%, 100%, etc.
  • the power line VDD and the first shielding portion 61 may also form a grid structure. This arrangement can reduce the voltage difference between the first power terminals at different positions of the display panel.
  • the first bridge portion 41 can be connected to the second initial signal line Vinit2 and the fourteenth active portion 714 through via holes respectively to connect the first pole of the seventh transistor and the second initial signal. end.
  • the second bridge portion 42 may be connected to the tenth active portion 710 through a via hole to connect the second pole of the sixth transistor and the second pole of the seventh transistor.
  • the third bridge part 43 may be connected to the sixteenth active part 716 through a via hole to connect the first electrode of the fourth transistor.
  • the fourth bridge portion 44 can connect the eighth active portion 78 and the first conductive portion 11 through via holes respectively to connect the first electrode of the second transistor T2, the second electrode of the first transistor T1, and the gate electrode of the driving transistor T3. .
  • the fifth conductive layer may include a fifth bridge part 55 and a data line Da.
  • the data line Da may be used to provide the data signal terminal in FIG. 1 .
  • the fifth bridge portion 55 can be connected to the second bridge portion 42 through a via hole to connect the second electrode of the sixth transistor, and the fifth bridge portion 55 can also be connected to the first electrode of the light-emitting unit.
  • the orthographic projection of the data line Da on the base substrate may extend along the second direction Y, and the data line Da may be connected to the third bridge portion 43 through a via hole to connect the first electrode of the fourth transistor and the data signal terminal.
  • the black square drawn on the side of the fourth conductive layer facing away from the base substrate represents the via hole through which the fourth conductive layer is connected to other levels on the side facing the base substrate;
  • the black square on the side of the fifth conductive layer facing away from the base substrate indicates that the fifth conductive layer is connected to the via holes of other levels on the side facing the base substrate;
  • the black square drawn on the side of the electrode layer facing away from the base substrate indicates that the electrode layer is connected on the side facing the substrate.
  • the black square only represents the location of the via hole. Different via holes represented by black squares at different positions can penetrate different insulation layers.
  • the display panel may also include a buffer layer 91 , an insulating layer 92 , a dielectric layer 93 , a passivation layer 94 , and a first planar layer 95 .
  • the base substrate, the shielding layer, the buffer layer 91, the first active layer, the insulating layer 92, the first conductive layer, the dielectric layer 93, the fourth conductive layer, the passivation layer 94, the first planar layer 95, the Five conductive layers are stacked in sequence.
  • the buffer layer 91 may include a silicon oxide layer and a silicon nitride layer.
  • the insulating layer 92 can be a single-layer structure or a multi-layer structure.
  • the material of the insulating layer 92 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride;
  • the dielectric layer 93 can be a silicon nitride layer;
  • the passivation layer 94 may be a silicon oxide layer;
  • the material of the first flat layer 95 may be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate ( PEN), silicon-glass bonding structure (SOG) and other materials;
  • the substrate substrate 90 may include a glass substrate, a barrier layer, and a polyimide layer that are stacked in sequence, and the barrier layer may be an inorganic material.
  • the material of the first conductive layer may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or a laminate.
  • the material of the fourth conductive layer and the fifth conductive layer may include metal materials, for example, it may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or laminate, or it may be titanium/aluminum /titanium lamination.
  • the display panel may further include a second flat layer, an electrode layer, and a pixel definition layer, the second flat layer is located on a side of the fifth conductive layer facing away from the base substrate, and the electrode layer is located on a side of the second flat layer facing away from the base substrate, The pixel definition layer is located on a side of the electrode layer facing away from the base substrate.
  • the scale of the drawings in this disclosure can be used as a reference in the actual process, but is not limited thereto, for example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line, It can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the figures described in this disclosure are only structural schematic diagrams.
  • the first, second and other qualifiers are only used to define different structure names and have no specific order meaning.
  • Figure 13 is a structural layout of another exemplary embodiment of the display panel of the present disclosure.
  • Figure 14 is a structural layout of the blocking layer in Figure 13.
  • Figure 15 is a diagram of the blocking layer and the first active layer in Figure 13. The structural layout of the source layer.
  • the first active layer may further include a seventeenth active part 717 connected between the second active part 72 and the sixth active part 76 , and
  • the orthographic projection of the seventeenth active portion 717 on the base substrate extends along the second direction Y, where the seventeenth active portion 717 is the equipotential point of the second electrode of the driving transistor.
  • the difference between the display panel shown in FIG. 13 and the display panel shown in FIG. 3 is that in the display panel shown in FIG. 13 , there is a break D1 between adjacent first shielding parts 61 in the first direction X, that is, in the first direction X Adjacent first shielding parts 61 are not directly connected.
  • the shielding layer includes a first connection part 64 , and the first connection part 64 is connected between the third shielding part 63 and the second shielding part 62 in adjacent pixel driving circuits located in the same row.
  • the orthographic projection of the first connection portion 64 on the base substrate may be located away from the orthographic projection of the first gate line G1 on the base substrate and away from the first conductive portion 11 on the base substrate. The side of the orthographic projection.
  • the orthographic projection of the first connecting portion 64 on the base substrate does not overlap with the orthographic projection of the seventeenth active portion 717 on the base substrate.
  • two first shielding portions 61 adjacent in the first direction X can be connected through the first connecting portion 64 .
  • other structures of the display panel shown in FIG. 14 may be the same as those of the display panel shown in FIG. 3 .
  • Figure 16 is a structural layout of another exemplary embodiment of the display panel of the present disclosure
  • Figure 17 is a structural layout of the fourth conductive layer in Figure 16
  • Figure 18 is a fifth conductive layer in Figure 16
  • the structural layout of FIG. 19 is the structural layout of the shielding layer, the first active layer, the first conductive layer, and the fourth conductive layer in FIG. 16 .
  • the fifth conductive layer may also include a second initial connection line 5Vinit2.
  • the orthographic projection of the second initial connection line 5Vinit2 on the base substrate may extend along the second direction Y.
  • the second initial connection line 5Vinit2 can be connected to the first bridge portion 41 through a via hole to connect the second initial signal line Vinit2.
  • the second initial connection line 5Vinit2 and the second initial signal line Vinit2 can form a grid structure, and the grid structure can Reduce the voltage difference between the second initial signal terminals at different positions of the display panel.
  • Other structures of the display panel shown in FIG. 16 may be the same as those of the display panel shown in FIG. 3 .
  • Figure 20 is a structural layout of another exemplary embodiment of the display panel of the present disclosure
  • Figure 21 is a structural layout of the shielding layer in Figure 20
  • Figure 22 is a structure of the fourth conductive layer in Figure 20 Layout
  • Figure 23 is a structural layout of the shielding layer, the first active layer, the first conductive layer, and the fourth conductive layer in Figure 20.
  • the fourth conductive layer also includes a second initial connection line 4Vinit2.
  • two adjacent columns of pixel driving circuits may be provided with a first initial connection line 4Vinit1 and a second initial connection line 4Vinit2 correspondingly.
  • the fourth conductive layer may also include a sixth bridge part 46 , the first initial connection line 4Vinit1 may be connected to the first initial signal line Vinit1 through the sixth bridge part 46 , and the second initial connection line 4Vinit2 may be connected through the first bridge part 41 Connect to the second initial signal line Vinit2 via hole.
  • Other structures of the display panel shown in FIG. 20 may be the same as those of the display panel shown in FIG. 3 .
  • Figure 24 is a structural layout of another exemplary embodiment of the display panel of the present disclosure
  • Figure 25 is a structural layout of the fourth conductive layer in Figure 24
  • Figure 26 is a fifth conductive layer in Figure 25
  • the structural layout of FIG. 27 is the structural layout of the shielding layer, the first active layer, the first conductive layer, and the fourth conductive layer in FIG. 24 .
  • the difference between the display panel shown in Figure 24 and the display panel shown in Figure 3 is that in the display panel shown in Figure 24, the power line VDD is not provided on the fourth conductive layer, and a seventh bridge portion 47 is added to the fourth conductive layer.
  • the seventh bridge portion 47 is connected to the first shielding part 61 through a via hole.
  • the fifth conductive layer in the display panel shown in Figure 24 is added with a power line VDD and a second initial connection line 5Vinit2.
  • the power line VDD is connected to the seventh bridge portion 47 through a via hole to connect the second electrode of the capacitor.
  • the orthographic projection of the power line VDD on the base substrate can also cover the orthographic projection of the fourth bridge portion 44 on the base substrate.
  • the power line VDD can shield the noise interference of other signals on the fourth bridge portion 44, thereby reducing the energy consumption of the driving transistor T3. Gate voltage fluctuations.
  • the second initial connection line 5Vinit2 is connected to the first bridge portion 41 through a via hole, so that the second initial connection line 5Vinit2 can form a grid structure with the second initial signal line Vinit2.
  • the grid structure can reduce the voltage difference between the second initial signal terminals at different positions of the display panel.
  • Other structures of the display panel shown in FIG. 24 may be the same as those of the display panel shown in FIG. 3 .
  • This exemplary embodiment uses a shielding layer to form part of the signal lines and device structures in the display panel, thereby improving the integration of the display panel.
  • this display panel forms the second electrode of the capacitor through the first shielding part 61 and the fifth extension part VDD5, and this display panel does not need to provide a second gate layer.
  • the second shielding part 62 and the third shielding part 63 are directly connected to the first shielding part 61.
  • the second shielding part 62 and the third shielding part 63 do not need to connect the power lines through via holes, thereby reducing the number of via holes.
  • the shielding layer may also include other independently provided shielding parts, and the shielding parts may also be used to form other signal lines and device structures.
  • the PI layer (polyimide) in the base substrate is prone to generate a negative electrostatic field, and the negative electrostatic field will cause the threshold of the transistor to be forward biased.
  • this negative electrostatic field can easily cause a positive shift in the threshold of the driving transistor, and a positive shift in the threshold of the driving transistor can cause undesirable phenomena such as greening of the display panel's copper rods during testing.
  • the above-mentioned first shielding part 61 can shield the influence of the above-mentioned negative electrostatic field on the threshold of the driving transistor T3.
  • the shielding layer can be a light-shielding structure, and the shielding layer can avoid the impact of light on the characteristics of the transistor.
  • the forward bias of the threshold value of the driving transistor T3 will increase the driving current under the same gray scale, which may easily cause the display panel to appear green.
  • the above-mentioned first shielding part 61 can receive a positive power supply voltage, and the positive electric field generated by the first shielding part 61 will cause the threshold of the driving transistor to be negatively biased, thereby reducing the risk of greening of the display panel.
  • threshold voltages of other transistors in the pixel driving circuit may also shift, resulting in problems such as transistor leakage current.
  • the leakage current of the first transistor T1 and the second transistor T2 may cause defects such as flickering of the display panel
  • the leakage current of the sixth transistor T6 may cause defects such as a four-split display panel.
  • the shielding layer may also include other shielding parts, and the orthographic projections of other shielding parts on the base substrate may respectively cover at least part of the structures of the orthographic projections of other transistor channel regions on the base substrate.
  • Other shielding parts may be provided independently or may be at least partially connected. Wherein, the shielding part is provided independently, and it can be understood that the shielding part is not connected to other shielding parts.
  • the shielding portion below the P-type transistor can receive a positive power supply voltage, and the positive electric field formed by the shielding portion can negatively bias the threshold of the P-type transistor, thereby reducing the turn-off leakage current of the P-type transistor.
  • the shielding part below the N-type transistor can be connected to a negative power supply voltage.
  • the negative electric field formed by the shielding part can forward-bias the threshold of the N-type transistor, thereby reducing the turn-off leakage current of the N-type transistor.
  • the first transistor and the second transistor in FIG. 1 may be N-type transistors, a shielding part may be provided below the first transistor and the second transistor, and the shielding part below the first transistor and the second transistor may receive a negative power supply voltage.
  • the magnitude of the power supply voltage received by the shielding part may be determined by the working state of the transistor.
  • the fourth transistor T4 and the seventh transistor T7 are in a forward-biased state for a long time
  • the fifth transistor T5 and the sixth transistor T6 are in a negative-biased state for a long time.
  • the positive voltage received by the lower shielding portion may be greater than the positive voltage received by the shielding portion located below the fifth transistor T5 and the sixth transistor T6.
  • the voltage received by the shielding portion located below the fourth transistor T4 and the seventh transistor T7 may be 6.6V
  • the voltage received by the shielding portion located below the fifth transistor T5 and the sixth transistor T6 may be 2.6V.
  • the extent to which the shielding portion receives the supply voltage may be affected by the size of the transistor.
  • the aspect ratio of the channel region of the driving transistor is greater than the aspect ratio of the channel region of the fifth transistor T5
  • the voltage received by the shielding portion below the driving transistor can be greater than the voltage received by the shielding portion below the fifth transistor T5.
  • the voltage received by the shielding portion below the driving transistor T5 The voltage received by the shielding part may be 4.6V.
  • the magnitude of the supply voltage received by the shielding portion may be affected by the location of the transistor.
  • the display panel may include a high-density integration region H and a low-density integration region L.
  • the density of transistors in the high-density integration region H is greater than the density of transistors in the low-density integration region L.
  • the high-density integration area includes a first high-density integration area H1 and a second high-density integration area H2.
  • the second high-density integration area H2 is located away from the first high-density integration area H1 and away from the low-density integration area L. side.
  • the absolute value of the voltage received by the shielding portion located in the first high-density integrated region H1 is greater than that in the second high-density integrated region H2
  • the shield is used to receive the absolute value of the voltage.
  • the shielding portion corresponding to the driving transistor in the pixel driving circuit is used to receive a positive power supply voltage greater than that corresponding to the driving transistor in the second high-density integration region H2.
  • the shield is used to receive the positive supply voltage.
  • the shielding portion corresponding to the first transistor in the pixel driving circuit in the shielding portion corresponding to the first transistor in the pixel driving circuit, the shielding portion corresponding to the first transistor in the first high-density integration region H1 is used to receive The negative power supply voltage is less than the positive power supply voltage that the shielding portion corresponding to the first transistor in the second high-density integration region H2 is used to receive.
  • the low-density integration area L may be a frame area of the display panel, an under-screen camera integration area, a light-transmitting area in the display area, etc.
  • the density of transistors in the low-density integration area L may be zero.
  • the pixel driving circuit in the display panel may also have other structures.
  • FIG. 29 it is a schematic circuit structure diagram of a pixel driving circuit in another exemplary embodiment of the display panel of the present disclosure.
  • the pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C.
  • the difference from the pixel driving circuit shown in FIG. 1 is that the first transistor and the second transistor in the pixel driving circuit shown in FIG. 29 are N-type transistors.
  • FIG. 30 it is a timing diagram of each node in a driving method of the pixel driving circuit in Figure 29.
  • G1 represents the timing of the first gate drive signal terminal G1
  • G2 represents the timing of the second gate drive signal terminal G2
  • Re1 represents the timing of the first reset signal terminal Re1
  • Re2 represents the timing of the second reset signal terminal Re2.
  • EM represents the timing of the enable signal terminal EM
  • Da represents the timing of the data signal terminal Da.
  • the driving method of the pixel driving circuit may include a first reset stage t1, a compensation stage t2, a second reset stage t3, and a light emitting stage t4.
  • the first reset phase t1 the first reset signal terminal Re1 outputs a high level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to the node N.
  • the compensation stage t2 the first gate drive signal terminal G1 outputs a high-level signal, the second gate drive signal terminal G2 outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and at the same time the data signal terminal Da Output the driving signal to write the voltage Vdata+Vth (that is, the sum of the voltages Vdata and Vth) to the node N, where Vdata is the voltage of the data signal, and Vth is the threshold voltage of the driving transistor T3.
  • the second reset The signal terminal Re2 outputs a low-level signal
  • the seventh transistor T7 is turned on
  • the second initial signal terminal Vinit2 inputs an initial signal to the second pole of the sixth transistor T6.
  • Light-emitting stage t4 The enable signal terminal EM outputs a low-level signal
  • the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the voltage Vdata+Vth stored in the capacitor C.
  • the driving transistor output current formula is as follows:
  • I is the output current of the driving transistor
  • ⁇ is the carrier mobility
  • Cox is the gate capacitance per unit area
  • W is the width of the driving transistor channel
  • L is the length of the driving transistor channel
  • Vgs is the gate-source voltage of the driving transistor.
  • Difference is the threshold voltage of the driving transistor.
  • the output current of the driving transistor in the pixel driving circuit of the present disclosure I ( ⁇ WCox/2L)(Vdata+Vth-Vdd-Vth)2.
  • the pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.
  • This exemplary embodiment also provides another display panel, which may include a base substrate, a shielding layer, a first active layer, a first conductive layer, a second conductive layer, and a second active layer that are stacked in sequence. , a third conductive layer, a fourth conductive layer, a fifth conductive layer, and an electrode layer, wherein an insulating layer may be provided between the above layers.
  • Figure 31 is a structural layout of another exemplary embodiment of the display panel of the present disclosure
  • Figure 32 is a structural layout of the shielding layer in Figure 31
  • Figure 33 is a first active layer in Figure 31
  • the structural layout of Figure 34 is the structural layout of the first conductive layer in Figure 31.
  • Figure 35 is the structural layout of the second conductive layer in Figure 31.
  • Figure 36 is the structural layout of the second active layer in Figure 31.
  • Figure 37 is The structural layout of the third conductive layer in Figure 31.
  • Figure 38 is the structural layout of the fourth conductive layer in Figure 31.
  • Figure 39 is the structural layout of the fifth conductive layer in Figure 27.
  • Figure 40 is the shielding layer and the first conductive layer in Figure 31.
  • Figure 41 is the structural layout of the shielding layer, the first active layer, and the first conductive layer in Figure 31.
  • Figure 42 is the structural layout of the shielding layer, the first active layer, the first conductive layer, and the first conductive layer in Figure 31.
  • Figure 43 is the structural layout of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in Figure 31.
  • Figure 44 is the shielding layer, The structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer.
  • Figure 45 shows the shielding layer, the first active layer, the first conductive layer, The structural layout of the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer;
  • Figure 46 shows the shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the fourth conductive layer in Figure 31 The structural layout of the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer.
  • the display panel may include a plurality of pixel driving circuits shown in FIG. 29 .
  • the plurality of pixel driving circuits may include a first pixel driving circuit P1 and a second pixel driving circuit P2 adjacently distributed in the row direction X.
  • the first pixel driving circuit P1 and the second pixel driving circuit P2 may be Mirror symmetry setup.
  • the first pixel driving circuit P1 and the second pixel driving circuit P2 may form a repeating unit, and the display panel may include a plurality of repeating units distributed in an array in the row direction X and the column direction Y.
  • the shielding layer may include a positive pressure shielding part BSM1 and a negative pressure shielding part BSM2.
  • the positive voltage shielding part BSM1 is used to receive the positive power supply voltage
  • the negative voltage shielding part BSM2 is used to receive the negative power supply voltage.
  • Both the orthographic projection of the positive pressure shielding portion BSM1 on the base substrate and the orthographic projection of the negative pressure shielding portion BSM2 on the base substrate can extend along the column direction Y.
  • the negative pressure shielding parts BSM2 adjacent in the row direction X may be connected to each other, or may be provided independently of each other.
  • Positive pressure shielding portions BSM1 adjacent in the row direction X may be connected to each other or may be provided independently of each other.
  • the shielding layer may be a conductive structure, for example, the shielding layer may be a molybdenum layer.
  • the first active layer may include a third active part 73 , a fourth active part 74 , a fifth active part 75 , a sixth active part 76 , a seventh active part 76 , and a third active part 74 .
  • the third active part 73 may be used to form a channel region of the driving transistor T3; the fourth active part 74 may be used to form a channel region of the fourth transistor T4; and the fifth active part 75 may be used to form a channel region of the fourth transistor T4.
  • the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion
  • the first active portion 78 is connected to the side of the fifth active portion 75 away from the third active portion 73 , and the ninth active portion 79 is connected to the eighth active portion 78 of the first pixel driving circuit P1 and the second pixel driving circuit P2 between the eighth active part 78 .
  • the tenth active part 710 is connected between the sixth active part 76 and the seventh active part 77 , and the eleventh active part 711 is connected between the sixth active part 76 and the third active part 73 .
  • the eighth active part 78 can be used to form the first pole of the fifth transistor.
  • the eighth active part in two adjacent pixel driving circuits is connected through the ninth active part 79, so that The voltage difference between the first power terminals in the adjacent pixel driving circuits can be reduced.
  • the orthographic projection of the positive pressure shielding part BSM1 on the base substrate can be the same as the orthographic projection of the third active part 73 on the base substrate and the orthographic projection of the fourth active part 74 on the base substrate.
  • the orthographic projection of the fifth active part 75 on the base substrate and the orthographic projection of the seventh active part 77 on the base substrate at least partially overlap, for example, the orthographic projection of the positive pressure shielding part BSM1 on the base substrate It can cover the orthographic projection of the third active part 73 on the base substrate, the orthographic projection of the fourth active part 74 on the base substrate, the orthographic projection of the fifth active part 75 on the base substrate, and the seventh active part 75 on the base substrate.
  • the first active layer may be formed of polysilicon material.
  • the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type low-temperature polysilicon thin film transistors.
  • the first conductive layer may include: a first conductive portion 11, a second gate line G2, an enable signal line EM, and a second reset signal line Re2.
  • the second gate line G2 can be used to provide the second gate drive signal terminal in Figure 29;
  • the enable signal line EM can be used to provide the enable signal terminal in Figure 29;
  • the second reset signal line Re2 can be used to provide the enable signal terminal in Figure 29 The second reset signal terminal in .
  • the orthographic projection of the second gate line G2 on the base substrate, the orthographic projection of the enable signal line EM on the base substrate, and the orthographic projection of the second reset signal line Re2 on the base substrate may all extend along the row direction X.
  • the orthographic projection of the second gate line G2 on the base substrate covers the orthographic projection of the fourth active part 74 on the base substrate, and part of the structure of the second gate line G2 is used to form the gate of the fourth transistor.
  • the orthographic projection of the enable signal line EM on the base substrate covers the orthographic projection of the fifth active part 75 on the base substrate and the orthographic projection of the sixth active part 76 on the base substrate.
  • the enable signal line EM Part of the structure may be used to form gates of the fifth transistor T5 and the sixth transistor T6 respectively.
  • the orthographic projection of the second reset signal line Re2 on the base substrate can cover the orthographic projection of the seventh active part 77 on the base substrate, and part of the structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7 pole.
  • the orthographic projection of the first conductive portion 11 on the base substrate covers the orthographic projection of the third active portion 73 on the base substrate.
  • the first conductive portion 11 can be used to form the gate electrode of the driving transistor T3 and the first electrode of the capacitor. .
  • the second gate line G2 in the pixel driving circuit of this row can be multiplexed as the second reset signal line Re2 in the pixel driving circuit of the previous row.
  • the display panel can use the first conductive layer as a mask to conduct conduction processing on the first active layer, that is, the area of the first active layer covered by the first conductive layer can form the channel region of the transistor, and the first Areas of the active layer not covered by the first conductive layer form conductor structures.
  • the second conductive layer may include: a first initial signal line Vinit1 , a third reset signal line 2Re1 , a third gate line 2G1 , and a plurality of second conductive parts 22 .
  • the first initial signal line Vinit1 is used to provide the first initial signal terminal in Figure 29
  • the third reset signal line 2Re1 can be used to provide the first reset signal terminal in Figure 29
  • the third gate line 2G1 can be used to provide The first gate drive signal terminal in Figure 29.
  • the orthographic projection of the first initial signal line Vinit1 on the base substrate, the orthographic projection of the third reset signal line 2Re1 on the base substrate, and the orthographic projection of the third gate line 2G1 on the base substrate can all extend along the row direction X .
  • the second conductive layer may further include a plurality of third connection portions 23 .
  • the third connection portions 23 are connected between two adjacent second conductive portions 22 in the row direction.
  • adjacent second conductive portions 22 may also be connected.
  • the second active layer may include an active part 81, and the active part 81 may include a connected first active part 811, a second active part 812, a twelfth active part
  • the first active part 811 may be used to form the channel region of the first transistor; the second active part 812 may be used to form the channel region of the second transistor T2; the twelfth active part 813 is connected to the The second active part 812 is at one end away from the first active part 811 .
  • the second active layer may be formed of indium gallium zinc oxide, and accordingly, the first transistor T1 and the second transistor T2 may be N-type metal oxide thin film transistors.
  • the orthographic projection of the third gate line 2G1 on the base substrate can cover the orthographic projection of the second active part 812 on the base substrate, and part of the structure of the third gate line 2G1 can be used to form the bottom gate of the second transistor.
  • the orthographic projection of the third reset signal line 2Re1 on the base substrate can cover the orthographic projection of the first active part 811 on the base substrate, and part of the structure of the third reset signal line 2Re1 can be used to form the bottom of the first transistor T1 gate.
  • the front projection of the negative pressure shielding part BSM2 on the base substrate may overlap with the front projection of the first active part 811 on the base substrate and the front projection of the second active part 812 on the base substrate, for example, negative
  • the orthographic projection of the blocking portion BSM2 on the base substrate can cover the orthographic projection of the first active portion 811 on the base substrate and the orthographic projection of the second active portion 812 on the base substrate.
  • the third conductive layer may include a first reset signal line 3Re1 and a first gate line 3G1. Both the orthographic projection of the first reset signal line 3Re1 on the base substrate and the orthographic projection of the first gate line 3G1 on the base substrate can extend along the row direction X.
  • the first reset signal line 3Re1 can be used to provide the first reset signal terminal in FIG. 29
  • the orthographic projection of the first reset signal line 3Re1 on the base substrate can cover the orthographic projection of the first active part 811 on the base substrate.
  • part of the structure of the first reset signal line 3Re1 can be used to form the top gate of the first transistor T1, and at the same time, the first reset signal line 3Re1 can be connected to the third reset signal line 2Re1 through a via hole located in the edge wiring area of the display panel.
  • the first gate line 3G1 may be used to provide the first gate driving signal terminal in FIG. 29 , and the orthographic projection of the first gate line 3G1 on the base substrate may cover the orthographic projection of the second active part 812 on the base substrate.
  • part of the structure of the first gate line 3G1 can be used to form the top gate of the second transistor T2, and at the same time, the first gate line 3G1 can be connected to the third gate line 2G1 through a via hole located in the edge wiring area of the display panel. As shown in FIGS.
  • the orthographic projection of the first conductive part 11 on the base substrate may be located between the orthographic projection of the first gate line 3G1 on the base substrate and Between the orthographic projection of the enable signal line EM on the substrate substrate; the orthographic projection of the first reset signal line 3Re1 on the substrate substrate may be located between the first gate line 3G1 on the substrate substrate The orthographic projection is away from the side of the orthographic projection of the first conductive part 11 on the base substrate.
  • the orthographic projection of the second gate line G2 on the base substrate may be located between the orthographic projection of the first gate line 3G1 on the base substrate and the orthographic projection of the first reset signal line 3Re1 on the base substrate.
  • the orthographic projection of the second reset signal line Re2 on the base substrate may be located away from the orthographic projection of the enable signal line EM on the base substrate and away from the first conductive portion 11 on the base substrate. side of the orthographic projection.
  • the display panel can use the third conductive layer as a mask to perform conductive processing on the second active layer, that is, the area in the second active layer covered by the third conductive layer can form the channel region of the transistor. Areas of the active layer not covered by the third conductive layer form conductor structures.
  • the fourth conductive layer may include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, and a sixth bridge portion. 46.
  • the first bridge portion 41 can be connected to the third connection portion 23 through two via holes H, and connected to the ninth active portion 79 through the via holes to connect the first electrode of the fifth transistor and the second electrode of the capacitor C.
  • the black squares represent the positions of the via holes, and this exemplary embodiment only labels some of the via holes.
  • the first bridge portion 41 may be mirror symmetrical with a mirror symmetry plane of the first pixel driving circuit P1 and the second pixel driving circuit P2.
  • the second bridge portion 42 may be connected to the tenth active portion 710 through a via hole to connect the second electrode of the sixth transistor T6 and the first electrode of the seventh transistor T7.
  • the third bridge portion 43 can be connected to the eleventh active portion 711 and the twelfth active portion 813 respectively through via holes to connect the second electrode of the second transistor T2, the first electrode of the sixth transistor T6, and the driving transistor T3. the second pole.
  • the fourth bridge portion 44 can be connected to the second active layer and the first conductive portion 11 between the first active portion 811 and the second active portion 812 respectively through via holes to connect the first electrode and the first conductive portion 11 of the second transistor T2. Gate of the drive transistor. As shown in FIG. 35 , an opening 221 is formed on the second conductive part 22 , and the orthographic projection of the via hole connected between the first conductive part 11 and the fourth bridge part 44 on the base substrate is located at the position of the opening 221 on the base substrate. Within the orthographic projection on the through hole, the conductive structure in the via hole and the second conductive portion 22 are insulated from each other.
  • the fifth bridge portion 45 can be connected to the second active layer on the side of the first active portion 811 away from the second active portion 812 and the first initial signal line Vinit1 through via holes respectively, so as to connect the second electrode of the first transistor and the first initial signal line Vinit1.
  • the first initial signal terminal Among the two adjacent repeating units in the row direction, two adjacent pixel driving circuits may share the same fifth bridge portion 45 .
  • the sixth bridge portion 46 may be connected to the first active layer on the side of the fourth active portion 74 away from the third active portion 73 through a via hole to connect the first electrode of the fourth transistor.
  • the second initial signal line Vinit2 can be used to provide the second initial signal terminal in FIG. 29 .
  • the second initial signal line Vinit2 can connect the first active part of the seventh active part 77 away from the sixth active part 76 through a via hole.
  • the source layer is used to connect the second electrode of the seventh transistor and the second initial signal terminal.
  • the fifth conductive layer may include a plurality of power lines VDD, a plurality of data lines Da, and a seventh bridge portion 57 .
  • the orthographic projection of the power line VDD on the base substrate and the orthographic projection of the data line Da on the base substrate can both extend along the column direction Y.
  • the power line VDD can be used to provide the first power terminal in Figure 29, and the data line Da can be used to provide the data signal terminal in Figure 29.
  • each column of pixel driving circuits can be provided with a corresponding power line.
  • the power line VDD in the first pixel driving circuit P1 can be connected to the first bridge portion 41 through a via hole, and the power line VDD in the second pixel driving circuit P2 can be connected to the first bridge portion 41 through a via hole.
  • VDD can be connected to the same first bridge portion 41 through a via hole, thereby connecting the first pole of the fifth transistor and the first power terminal.
  • the data line Da may be connected to the sixth bridge portion 46 through a via hole to connect the first electrode of the fourth transistor and the data signal terminal.
  • the seventh bridge portion 57 may be connected to the second bridge portion 42 through a via hole to connect the first pole of the seventh transistor.
  • the power line VDD may include a first extension part VDD1, a second extension part VDD2, and a third extension part VDD3.
  • the second extension part VDD2 is connected between the first extension part VDD1 and the third extension part VDD3.
  • the size of the orthographic projection of the second extension part VDD2 on the base substrate in the row direction X may be larger than the size of the orthogonal projection of the first extension part VDD1 on the base substrate in the row direction
  • the size of the orthographic projection of the second extending portion VDD2 on the base substrate in the row direction X may be larger than the size of the orthogonal projection of the third extending portion VDD3 on the base substrate in the row direction X.
  • the orthographic projection of the second extension part VDD2 on the base substrate can cover the orthographic projection of the first active part 811 on the base substrate and the orthographic projection of the second active part 812 on the base substrate.
  • the second extension part VDD2 The influence of light on the characteristics of the first transistor T1 and the second transistor T2 can be reduced.
  • the second extension portions VDD2 in the two adjacent pixel driving circuits can be connected to each other, so that the power supply line VDD and the second conductive portion 22 can form a grid structure, and the power lines of the grid structure can be connected to each other. It can reduce the voltage drop of the power signal on it.
  • the electrode layer may include a plurality of electrode parts, and the plurality of electrode parts include: a plurality of R electrode parts R, a plurality of G electrode parts G, and a plurality of B electrode parts B.
  • the display panel may include a first insulating layer 91, a second insulating layer 92, a third insulating layer 93, a fourth insulating layer 94, a fifth insulating layer 95, a first dielectric layer 96, a first flat layer 97, a second Flat layer 98.
  • the second active layer, the fifth insulating layer 95, the third conductive layer, the first dielectric layer 96, the fourth conductive layer, the first planar layer 97, the fifth conductive layer, the second planar layer 98, and the electrode layer are stacked in sequence. set up.
  • the first insulating layer 91 , the second insulating layer 92 , the third insulating layer 93 , the fourth insulating layer 94 and the fifth insulating layer 95 can be a single-layer structure or a multi-layer structure, and the first insulating layer 91 and the second insulating layer 92.
  • the material of the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the first dielectric layer 96 can be silicon nitride.
  • the material of the first flat layer 97 and the second flat layer 98 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG) and other materials.
  • the base substrate 90 may include a glass substrate, a barrier layer, and a polyimide layer that are stacked in sequence.
  • the barrier layer may be an inorganic material.
  • the material of the first conductive layer, the second conductive layer, and the third conductive layer may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or a laminate.
  • the material of the fourth conductive layer and the fifth conductive layer may include metal materials, for example, it may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or laminate, or it may be titanium/ Aluminum/titanium stack.
  • the display panel may include a display area AA and a frame area B located around the display area.
  • the above-mentioned shielding portion may also be provided in the frame area B.
  • the frame area B may include a first frame area B1 for integrating the gate driving circuit, and a fan-out area B2 for fan-out data lines.
  • the shielding portion located in the first frame region B1 can form a signal line or device structure in the gate drive circuit, and the shielding portion located in the fan-out region B2 can be used to form a fan-out line of the data line.
  • the shielding portion located in the frame area B can be used to form signal lines or device structures in the detection circuit. This setting can evenly distribute the shielding layer on the substrate, so that problems such as uneven etching and poor control of process parameters will not be caused during the process.
  • This exemplary embodiment also provides a display device, which includes the above-mentioned display panel.
  • the display device can be a display device such as a mobile phone, a tablet computer, or a television.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种显示面板及显示装置，显示面板包括像素驱动电路，像素驱动电路包括晶体管，显示面板还包括：衬底基板（90）、第一有源层、遮挡层，第一有源层位于衬底基板（90）的一侧，第一有源层的至少部分结构用于形成晶体管沟道区；遮挡层位于衬底基板（90）和第一有源层之间，遮挡层为导电层，遮挡层包括多个独立设置的遮挡部，至少部分不同的遮挡部用于接收不同的信号。该显示面板具有较高的集成度。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
相关技术中，显示面板需要集成像素驱动电路、栅极驱动电路、检测电路等电路结构，从而导致显示面板需要较大的版图空间设置上述电路结构。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
根据本公开的一个方面，提供一种显示面板，其中，所述显示面板包括像素驱动电路，所述像素驱动电路包括晶体管，所述显示面板还包括：衬底基板、第一有源层、遮挡层，第一有源层位于所述衬底基板的一侧，所述第一有源层的至少部分结构用于形成所述晶体管的沟道区；遮挡层位于所述衬底基板和所述第一有源层之间，所述遮挡层为导电层，所述遮挡层包括多个独立设置的遮挡部，至少部分不同的所述遮挡部用于接收不同的信号。
本公开一种示例性实施例中，所述像素驱动电路包括驱动晶体管、第一晶体管，所述第一晶体管的第一极连接第一初始信号线，第二极连接所述驱动晶体管的栅极；多个所述遮挡部中包括所述第一初始信号线。
本公开一种示例性实施例中，所述第一有源层包括第一有源部、第三子有源部，所述第一有源部用于形成所述第一晶体管的沟道区，所述第一有源部包括第一子有源部和第二子有源部，所述第三子有源部连接于所述第一子有源部和所述第二子有源部之间；所述第一初始信号线包括第一延伸部，所述第一延伸部在所述衬底基板上的正投影与所述第三子有源部在 所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述显示面板还包括：第一导电层，第一导电层位于所述第一有源层背离所述衬底基板的一侧，所述第一导电层包括第一复位信号线，所述第一复位信号线在所述衬底基板上的正投影沿第一方向延伸且覆盖所述第一有源部在所述衬底基板上的正投影，所述第一复位信号线的部分结构用于形成所述第一晶体管的栅极；所述第一初始信号线包括第二延伸部，所述第二延伸部在所述衬底基板上的正投影与所述第一复位信号线在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述显示面板还包括：第四导电层，第四导电层位于所述第一有源层背离所述衬底基板的一侧，所述第四导电层包括第一初始连接线；其中，所述第一初始信号线在所述衬底基板上的正投影沿第一方向延伸，所述第一初始连接线在所述衬底基板上的正投影沿第二方向延伸，所述第一方向和所述第二方向相交，且所述第一初始连接线通过过孔连接与其在所述衬底基板上正投影相交的所述第一初始信号线。
本公开一种示例性实施例中，所述显示面板还包括发光单元，所述像素驱动电路包括第七晶体管，所述第七晶体管的第一极连接第二初始信号线，第二极连接所述发光单元的第一电极；多个所述遮挡部中包括所述第二初始信号线。
本公开一种示例性实施例中，所述像素驱动电路还包括驱动晶体管、第六晶体管，所述第六晶体管的第一极连接所述驱动晶体管的第二极，第二极连接所述发光单元的第一电极；所述第一有源层包括第六有源部、第七有源部，所述第六有源部用于形成所述第六晶体管的沟道区，所述第七有源部用于形成所述第七晶体管的沟道区；所述显示面板还包括：第一导电层，所述第一导电层位于所述第一有源层背离所述衬底基板的一侧，所述第一导电层包括：使能信号线、第二复位信号线，所述使能信号线在所述衬底基板上的正投影沿第一方向延伸且覆盖所述第六有源部在所述衬底基板上的正投影，所述使能信号线的部分结构用于形成所述第六晶体管的栅极；所述第二复位信号线在所述衬底基板上的正投影沿第一方向延伸且覆盖所述第七有源部在所述衬底基板上的正投影，所述第二复位信号线 的部分结构用于形成所述第七晶体管的栅极；其中，所述第二初始信号线在所述衬底基板上的正投影位于所述使能信号线在所述衬底基板上的正投影和所述第二复位信号线在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述显示面板还包括：第四导电层，第四导电层位于所述第一有源层背离所述衬底基板的一侧，所述第四导电层包括第二初始连接线；其中，所述第二初始信号线在所述衬底基板上的正投影沿第一方向延伸，所述第二初始连接线在所述衬底基板上的正投影沿第二方向延伸，所述第一方向和所述第二方向相交，且所述第二初始连接线通过过孔连接与其在所述衬底基板上正投影相交的所述第二初始信号线。
本公开一种示例性实施例中，所述像素驱动电路包括驱动晶体管，所述第一有源层包括第三有源部，所述第三有源部用于形成所述驱动晶体管的沟道区；多个所述遮挡部中包括第一遮挡部，所述第一遮挡部连接一稳定电压源，且所述第一遮挡部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影。
本公开一种示例性实施例中，所述像素驱动电路还包括电容，所述电容的第一电极连接所述驱动晶体管的栅极，所述电容的第二电极连接电源线；所述显示面板还包括：第一导电层，第一导电层位于所述第一有源层背离所述衬底基板的一侧，所述第一导电层包括第一导电部，所述第一导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第一导电部用于形成所述驱动晶体管的栅极和所述电容的第一电极；所述电源线形成所述稳定电压源，所述第一遮挡部用于形成所述电容的第二电极。
本公开一种示例性实施例中，所述显示面板还包括：第四导电层，第四导电层位于所述第一导电层背离所述衬底基板的一侧，所述第四导电层包括所述电源线，所述电源线在所述衬底基板上的正投影沿第二方向延伸；所述显示面板包括在第一方向和所述第二方向上阵列分布的多个所述像素驱动电路，所述第一方向和所述第二方向相交，在所述第一方向上分布的多个所述第一遮挡部相连接，所述电源线通过过孔连接所述第一遮挡部。
本公开一种示例性实施例中，所述电源线包括第三延伸部、第四延伸 部，以及连接于所述第三延伸部和所述第四延伸部之间的第五延伸部，所述第五延伸部在所述衬底基板上的正投影在第一方向上的尺寸大于所述第三延伸部在所述衬底基板上的正投影在第一方向上的尺寸，所述第五延伸部在所述衬底基板上的正投影在第一方向上的尺寸大于所述第四延伸部在所述衬底基板上的正投影在第一方向上的尺寸，所述第一方向和所述第二方向相交；所述第五延伸部在所述衬底基板上的正投影与所述第一导电部在所述衬底基板上的正投影至少部分交叠，所述第五延伸部的至少部分结构用于形成所述电容的第二电极。
本公开一种示例性实施例中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，所述第二晶体管的第二极连接所述驱动晶体管的第二极；所述第一有源层还包括第二有源部、第六子有源部，所述第二有源部用于形成所述第二晶体管的沟道区，所述第二有源部包括第四子有源部和第五子有源部，所述第六子有源部连接于所述第四子有源部和所述第五子有源部之间；所述遮挡层还包括第二遮挡部，所述第二遮挡部连接于所述第一遮挡部，所述第一遮挡部包括第一边沿，所述第二遮挡部包括第二边沿，所述第一边沿和所述第二边沿连接，且所述第一边沿在所述衬底基板上的正投影与所述第二边沿在所述衬底基板上的正投影之间的夹角小于180°，所述第二遮挡部在所述衬底基板上的正投影与所述第六子有源部在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述像素驱动电路还包括第一晶体管、第二晶体管，所述第一晶体管的第一极连接第一初始信号线，第二极连接所述驱动晶体管的栅极，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极；所述第一有源层还包括第一有源部、第二有源部、第八有源部，所述第一有源部用于形成所述第一晶体管的沟道区，所述第二有源部用于形成所述第二晶体管的沟道区，所述第八有源部连接于所述第一有源部和所述第二有源部之间；所述遮挡层还包括第三遮挡部，所述第三遮挡部连接于所述第一遮挡部，所述第一遮挡部包括第一边沿，所述第三遮挡部包括第三边沿，所述第一边沿和所述第三边沿连接，且所述第一边沿在所述衬底基板上的正投影与所述第三边沿 在所述衬底基板上的正投影之间的夹角小于180°，所述第三遮挡部在所述衬底基板上的正投影与所述第八有源部在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述像素驱动电路还包括第一晶体管、第二晶体管，所述第一晶体管的第一极连接第一初始信号线，第二极连接所述驱动晶体管的栅极，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极；所述第一有源层还包括第一有源部、第二有源部、第六子有源部、第八有源部，所述第一有源部用于形成所述第一晶体管的沟道区，所述第二有源部用于形成所述第二晶体管的沟道区，所述第二有源部包括第四子有源部和第五子有源部，所述第六子有源部连接于所述第四子有源部和所述第五子有源部之间，所述第八有源部连接于所述第一有源部和所述第二有源部之间；所述显示面板还包括第一导电层，所述第一导电层位于所述第一有源层背离所述衬底基板的一侧，所述第一导电层包括第一导电部和第一栅线，所述第一导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第一栅线在所述衬底基板上的正投影沿第一方向延伸且覆盖所述第二有源部在所述衬底基板上的正投影；所述遮挡层还包括第二遮挡部、第三遮挡部、第一连接部，所述第二遮挡部连接于所述第一遮挡部，所述第二遮挡部在所述衬底基板上的正投影与所述第六子有源部在所述衬底基板上的正投影至少部分交叠；所述第三遮挡部连接于所述第一遮挡部，所述第三遮挡部在所述衬底基板上的正投影与所述第八有源部在所述衬底基板上的正投影至少部分交叠；所述第一连接部连接于在所述第一方向上相邻像素驱动电路中所述第二遮挡部和所述第三遮挡部之间，且所述第一连接部在所述衬底基板上的正投影位于所述第一栅线在所述衬底基板上的正投影远离所述第一导电部在所述衬底基板上的正投影的一侧。
本公开一种示例性实施例中，所述显示面板还包括显示区和位于显示区周围的边框区，部分所述遮挡部位于所述显示区，部分所述遮挡部位于所述边框区。
本公开一种示例性实施例中，所述像素驱动电路包括多个晶体管，多个所述遮挡部中包括与所述晶体管对应的恒压遮挡部，所述恒压遮挡部在 所述衬底基板上的正投影和与其对应的所述晶体管的沟道区在所述衬底基板上的正投影至少部分交叠；至少部分不同的所述恒压遮挡部用于接收不同的电源电压。
本公开一种示例性实施例中，所述像素驱动电路包括N型晶体管和P型晶体管；多个所述恒压遮挡部中包括正压遮挡部和负压遮挡部，所述正压遮挡部用于接收正的电源电压，所述负压遮挡部用于接收负的电源电压；所述正压遮挡部在所述衬底基板上的正投影与所述P型晶体管沟道区在所述衬底基板上的正投影至少部分交叠，所述负压遮挡部在所述衬底基板上的正投影与所述N型晶体管沟道区在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述显示面板还包括发光单元，所述像素驱动电路包括驱动晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管，所述驱动晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管为P型晶体管；所述第四晶体管的第一极连接数据线，第二极连接所述驱动晶体管的第一极；所述第五晶体管的第一极连接第一电源端，第二极连接所述驱动晶体管的第一极；所述第六晶体管的第一极连接所述驱动晶体管的第二极，第二极连接所述发光单元的第一电极；所述第七晶体管的第一极连接第二初始信号线，第二极连接所述发光单元的第一电极；多个所述恒压遮挡部中包括多个正压遮挡部，多个所述正压遮挡部中包括：第一正压遮挡部、第二正压遮挡部、第三正压遮挡部，所述第一正压遮挡部在所述衬底基板上的正投影覆盖所述驱动晶体管沟道区在所述衬底基板上的正投影；所述第二正压遮挡部在所述衬底基板上的正投影覆盖所述第五晶体管沟道区在所述衬底基板上的正投影、第六晶体管沟道区在所述衬底基板上的正投影；所述第三正压遮挡部在所述衬底基板上的正投影覆盖所述第四晶体管沟道区在所述衬底基板上的正投影、第七晶体管沟道区在所述衬底基板上的正投影；其中，所述第一正压遮挡部用于接收的正电压大于所述第二正压遮挡部用于接收的正电压，所述第三正压遮挡部用于接收的正电压大于所述第一正压遮挡部用于接收的正电压。
本公开一种示例性实施例中，所述显示面板包括高密度集成区和低密度集成区，所述高密度集成区中晶体管的密度大于所述低密度集成区中晶 体管的密度；所述高密度集成区包括第一高密度集成区和第二高密度集成区，所述第二高密度集成区位于所述第一高密度集成区远离所述低密度集成区的一侧；在所述像素驱动电路中同一晶体管对应的恒压遮挡部中，位于所述第一高密度集成区中的恒压遮挡部用于接收的电压的绝对值大于位于所述第二高密度集成区中的恒压遮挡部用于接收的电压的绝对值。
根据本公开的一个方面，提供一种显示装置，其中，包括上述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开显示面板一种示例性实施例中像素驱动电路的电路结构示意图；
图2为图1所示像素驱动电路一种驱动方法中各节点上信号的时序图；
图3为本公开显示面板一种示例性实施例中的结构版图；
图4为图3中遮挡层的结构版图；
图5为图3中第一有源层的结构版图；
图6为图3中第一导电层的结构版图；
图7为图3中第四导电层的结构版图；
图8为图3中第五导电层的结构版图；
图9为图3中遮挡层、第一有源层的结构版图；
图10为图3中遮挡层、第一有源层、第一导电层的结构版图；
图11为图3中遮挡层、第一有源层、第一导电层、第四导电层的结构版图；
图12为图3所示显示面板沿虚线AA剖开的部分剖视图；
图13为本公开显示面板另一种示例性实施例的结构版图；
图14为图13中遮挡层的结构版图；
图15为图13中阻挡层和第一有源层的结构版图；
图16为本公开显示面板另一种示例性实施例的结构版图；
图17为图16中第四导电层的结构版图；
图18为图16中第五导电层的结构版图；
图19为图16中遮挡层、第一有源层、第一导电层、第四导电层的结构版图；
图20为本公开显示面板另一种示例性实施例的结构版图；
图21为图20中遮挡层的结构版图；
图22为图20中第四导电层的结构版图；
图23为图20中遮挡层、第一有源层、第一导电层、第四导电层的结构版图；
图24为本公开显示面板另一种示例性实施例的结构版图；
图25为图24中第四导电层的结构版图；
图26为图24中第五导电层的结构版图；
图27为图24中遮挡层、第一有源层、第一导电层、第四导电层的结构版图；
图28为本公开显示面板一种示例性实施例的结构示意图；
图29为本公开显示面板另一种示例性实施例中像素驱动电路的电路结构示意图；
图30为图29中像素驱动电路一种驱动方法中各节点的时序图；
图31为本公开显示面板另一种示例性实施例中的结构版图；
图32为图31中遮挡层的结构版图；
图33为图31中第一有源层的结构版图；
图34为图31中第一导电层的结构版图；
图35为图31中第二导电层的结构版图；
图36为图31中第二有源层的结构版图；
图37为图31中第三导电层的结构版图；
图38为图31中第四导电层的结构版图；
图39为27中第五导电层的结构版图；
图40为图31中遮挡层、第一有源层的结构版图；
图41为图31中遮挡层、第一有源层、第一导电层的结构版图；
图42为图31中遮挡层、第一有源层、第一导电层、第二导电层的结构版图；
图43为图31中遮挡层、第一有源层、第一导电层、第二导电层、第二有源层的结构版图；
图44为图31中遮挡层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层的结构版图；
图45为图31中遮挡层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层的结构版图；
图46为图31中遮挡层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层、第五导电层的结构版图；
图47为图31中沿虚线BB的部分剖视图；
图48为本公开显示面板另一种示例性的结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
如图1所示，为本公开显示面板一种示例性实施例中像素驱动电路的电路结构示意图。该像素驱动电路可以包括：第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、电容C。其中，第一晶体管T1的第一极连接第一初始信号端Vinit1，第二极连接节点N，栅极连接第一复位信号端Re1；第二晶体 管T2第一极连接节点N，第二极连接驱动晶体管T3的第二极；栅极连接第一栅极驱动信号端G1；驱动晶体管T3的栅极连接节点N；第四晶体管T4的第一极连接数据信号端Da，第二极连接驱动晶体管T3的第一极，栅极连接第一栅极驱动信号端G1；第五晶体管T5的第一极连接第一电源端VDD，第二极连接驱动晶体管T3的第一极，栅极连接使能信号端EM；第六晶体管T6第一极连接驱动晶体管T3的第二极，栅极连接使能信号端EM；第七晶体管T7的第一极连接第二初始信号端Vinit2，第二极连接第六晶体管T6的第二极，栅极连接第二复位信号端Re2。电容C连接于驱动晶体管T3的栅极和第一电源端VDD之间。该像素驱动电路可以连接一发光单元OLED，该像素驱动电路用于驱动该发光单元OLED发光，发光单元OLED可以连接于第六晶体管T6的第二极和第二电源端VSS之间。其中，第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以均为P型晶体管。
如图2所示，为图1所示像素驱动电路一种驱动方法中各节点上信号的时序图。其中，G1表示第一栅极驱动信号端G1上信号的时序图，Re1表示第一复位信号端Re1上信号的时序图，Re2表示第二复位信号端Re2上信号的时序图，EM表示使能信号端EM上信号的时序图，Da表示数据信号端Da上信号的时序图。该像素驱动电路的驱动方法可以包括复位阶段t1、补偿阶段t2，发光阶段t3。在复位阶段t1：第一复位信号端Re1输出低电平信号，第一晶体管T1导通，第一初始信号端Vinit1向节点N输入第一初始信号。在补偿阶段t2：第二复位信号端Re2、第一栅极驱动信号端G1输出低电平信号，第四晶体管T4、第二晶体管T2、第七晶体管T7导通，同时数据信号端Da输出数据信号以向节点N写入电压Vdata+Vth，其中Vdata为数据信号的电压，Vth为驱动晶体管T3的阈值电压，第二初始信号端Vini2向第六晶体管T6的第二极输入第二初始信号。在发光阶段t3：使能信号端EM输出低电平信号，第六晶体管T6、第五晶体管T5导通，驱动晶体管T3在节点N的电压Vdata+Vth作用下驱动发光单元发光。根据驱动晶体管输出电流公式I＝(μWCox/2L)(Vgs-Vth)2，其中，μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动 晶体管阈值电压。本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth)2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。应该理解的是，在其他示例性实施例中，该像素驱动电路还可以有其他驱动方法，例如，第一晶体管T1和第七晶体管T7可以均在复位阶段导通。
本示例性实施例还提供一种显示面板，该显示面板可以包括依次层叠设置的衬底基板、遮挡层、第一有源层、第一导电层、第四导电层、第五导电层，其中，上述相邻层级之间可以设置有绝缘层。如图3-11所示，图3为本公开显示面板一种示例性实施例中的结构版图，图4为图3中遮挡层的结构版图，图5为图3中第一有源层的结构版图，图6为图3中第一导电层的结构版图，图7为图3中第四导电层的结构版图，图8为图3中第五导电层的结构版图，图9为图3中遮挡层、第一有源层的结构版图，图10为图3中遮挡层、第一有源层、第一导电层的结构版图，图11为图3中遮挡层、第一有源层、第一导电层、第四导电层的结构版图。该显示面板可以包括多个图1所示的像素驱动电路。
如图3、4、9所示，遮挡层可以为导电层，遮挡层可以包括多个第一初始信号线Vinit1、第二初始信号线Vinit2、第一遮挡部61、第二遮挡部62、第三遮挡部63。其中，第一初始信号线Vinit1在衬底基板上的正投影、第二初始信号线Vinit2在衬底基板上的正投影均可以沿第一方向X延伸。第一初始信号线Vinit1可以同于提供图1中的第一初始信号端，第二初始信号线Vinit2可以用于提供图1中的第二初始信号端。第一遮挡部61分别与第二遮挡部62、第三遮挡部63连接。且在第一方向X上间隔设置的第一遮挡部61可以依次连接。第一遮挡部61可以包括第一边沿611，第二遮挡部62可以包括第二边沿622，第三遮挡部63可以包括第三边沿633。第一边沿611和第二边沿622连接，第一边沿611在衬底基板上的正投影和第二边沿622在衬底基板上的正投影之间的夹角可以小于180°，例如，第一边沿611在衬底基板上的正投影和第二边沿622在衬底基板上的正投影之间的夹角可以为90°。第一边沿611和第三边沿633连接，第一边沿611在衬底基板上的正投影和第三边沿633在衬底基板上的正投影之间的夹角可以小于180°，例如，第一边沿611在衬底基板上 的正投影和第三边沿633在衬底基板上的正投影之间的夹角可以为90°。
如图3、5、9所示，第一有源层可以包括第一有源部71、第二有源部72、第三有源部73、第四有源部74、第五有源部75、第六有源部76、第七有源部77。其中，第一有源部71用于形成第一晶体管T1的沟道区，第二有源部72用于形成第二晶体管T2的沟道区，第三有源部73用于形成驱动晶体管T3的沟道区，第四有源部74用于形成第四晶体管T4的沟道区，第五有源部75用于形成第五晶体管T5的沟道区，第六有源部76用于形成第六晶体管T6的沟道区，第七有源部77用于形成第七晶体管T7的沟道区。其中，第一有源部71可以包括第一子有源部711和第二子有源部712，第一有源层还包括连接于第一子有源部711和第二子有源部712之间的第三子有源部713。第二有源部72可以包括第四子有源部724、第五子有源部725，第一有源层还包括连接于第四子有源部724和第五子有源部725之间的第六子有源部726。第一有源层还可以包括第八有源部78、第九有源部79、第十有源部710、第十四有源部714、第十五有源部715、第十六有源部716。第八有源部78连接于第一有源部71和第二有源部72之间，第九有源部79连接于第五有源部75第三有源部73的一端，第十有源部710连接于第六有源部76和第七有源部77之间，第十六有源部716连接于第四有源部74远离第三有源部73的一端，第十四有源部714连接于第七有源部77远离第六有源部76的一端，第十五有源部715连接于第一有源部71远离第二有源部72的一端。第一有源层可以由多晶硅材料形成，相应的，第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型的低温多晶硅薄膜晶体管。
如图3、6、10所示，第一导电层可以包括第一复位信号线Re1、第一栅线G1、使能信号线EM、第二复位信号线Re2、第一导电部11。其中，第一复位信号线Re1在衬底基板上的正投影、第一栅线G1在衬底基板上的正投影、使能信号线EM在衬底基板上的正投影、第二复位信号线Re2在衬底基板上的正投影均可以沿第一方向X延伸。在本示例性实施例中，某一结构在衬底基板上的正投影沿某一方向延伸，可以理解为，该结构在衬底基板上的正投影沿该方向直线延伸或弯折延伸。第一复位信号线Re1 在衬底基板上的正投影可以覆盖第一有源部71在衬底基板上的正投影，第一复位信号线Re1的部分结构可以用于形成第一晶体管T1的栅极，第一复位信号线Re1可以用于提供图1所示像素驱动电路中的第一复位信号端。第二复位信号线Re2在衬底基板上的正投影可以覆盖第七有源部77在衬底基板上的正投影，第二复位信号线Re2的部分结构可以用于形成第七晶体管T7的栅极，第二复位信号线Re2可以用于提供图1所示像素驱动电路中的第二复位信号端。第一栅线G1在衬底基板上的正投影可以覆盖第二有源部72在衬底基板上的正投影、第四有源部74在衬底基板上的正投影，第一栅线G1的部分结构可以用于形成第二晶体管T2的栅极，第一栅线G1的另外部分结构可以用于形成第四晶体管T4的栅极，第一栅线G1可以用于提供图1所示像素驱动电路中的第一栅极驱动信号端。使能信号线EM在衬底基板上的正投影可以覆盖第五有源部75在衬底基板上的正投影、第六有源部76在衬底基板上的正投影，使能信号线EM的部分结构可以用于形成第五晶体管T5的栅极，使能信号线EM的另外部分结构可以用于形成第六晶体管T6的栅极，使能信号线EM可以用于提供图1所示像素驱动电路中的使能信号端。第一导电部11在衬底基板上的正投影可以覆盖第三有源部73在衬底基板上的正投影，第一导电部11可以用于形成驱动晶体管T3的栅极和电容C的第一电极。此外，该显示面板可以利用第一导电层为掩膜对第一有源层进行导体化处理，即第一有源层中被第一导电层覆盖的区域可以形成晶体管的沟道区，第一有源层中未被第一导电层覆盖的区域形成导体结构。
本示例性实施例中，如图3、4、6、9、10所示，第一遮挡部61在衬底基板上的正投影可以与第三有源部73在衬底基板上的正投影交叠，例如，第一遮挡部61在衬底基板上的正投影可以覆盖第三有源部73在衬底基板上的正投影，第一遮挡部61可以连接一稳定电压源，例如，第一遮挡部61可以连接图1中的第一电源端VDD、第一初始信号端Vinit1、第二初始信号端Vinit2等。第一遮挡部61可以用于屏蔽其他信号对驱动晶体管T3的噪音影响。当第一遮挡部61连接第一电源端VDD时，第一遮挡部61还可以用于形成电容C的第二电极。第二遮挡部62在衬底基板上的正投影和第六子有源部726在衬底基板上的正投影至少部分交叠，第二遮 挡部62可以对第六子有源部726起到稳压作用，从而可以降低由于第六子有源部726电压波动而产生的第六子有源部726向第二晶体管源漏极的漏电流。第三遮挡部63在衬底基板上的正投影可以与第八有源部78在衬底基板上的正投影至少部分交叠，第三遮挡部63可以对第八有源部78起到稳压作用，从而可以降低驱动晶体管T3栅极的电压波动。如图4所示，第一初始信号线Vinit1包括第一延伸部Vinit11和第二延伸部Vinit12，第一延伸部Vinit11在衬底基板上的正投影可以与第三子有源部713在衬底基板上的正投影至少部分交叠，第一延伸部Vinit11可以对第三子有源部713起到稳压作用，从而可以降低由于第三子有源部713电压波动而产生的第三子有源部713向第一晶体管源漏极的漏电流。第二延伸部Vinit12在衬底基板上的正投影可以与第一复位信号线Re1在衬底基板上的正投影至少部分交叠，从而可以提高显示面板的透过率。
如图3、7、11所示，第四导电层可以包括第一初始连接线4Vinit1，电源线VDD、第一桥接部41、第二桥接部42、第三桥接部43、第四桥接部44。其中，第一初始连接线4Vinit1在衬底基板上的正投影、电源线VDD在衬底基板上的正投影均可以沿第二方向Y延伸，第二方向Y可以与第一方向X相交，例如，第二方向Y可以为列方向，第一方向X可以为行方向。第一初始连接线4Vinit1可以分别通过过孔H连接第一初始信号线Vinit1、第十五有源部715，以连接第一初始信号端和第一晶体管的第一极。其中，附图中黑色方块表示过孔的位置。本示例性实施例中，第一初始连接线4Vinit1和第一初始信号线Vinit1可以形成网格结构，该网格结构可以降低显示面板不同位置上第一初始信号端之间的电压差。电源线VDD可以提供第一电源端，电源线VDD可以分别通过过孔连接第一遮挡部61、第九有源部79，以连接电容的第二电极、第一电源端、第五晶体管的第一极。如图3、7、11所示，电源线VDD可以包括第三延伸部VDD3、第四延伸部VDD4、第五延伸部VDD5，第五延伸部VDD5连接于第三延伸部VDD3和第四延伸部VDD4之间，第五延伸部VDD5在衬底基板上的正投影在第一方向X上的尺寸大于第三延伸部VDD3在衬底基板上的正投影在第一方向X上的尺寸，第五延伸部VDD5在衬底基板上的正投影在第一方向X上的尺寸大于第四延伸部VDD4在衬底基板上的正投影在第一方向X上的尺寸。 第五延伸部VDD5在衬底基板上的正投影还可以与第一导电部11在衬底基板上的正投影至少部分交叠，第五延伸部VDD5也可以用于形成电容C的第二电极。第一导电部11在衬底基板上的正投影的面积为S1，第一导电部11在衬底基板上的正投影和第五延伸部VDD5在衬底基板上的正投影的交叠面积为S2，S2/S1可以大于等于60％，例如，S2/S1可以等于60％、70％、80％、90％、100％等。电源线VDD和第一遮挡部61也可以形成网格结构，该设置可以降低显示面板不同位置上第一电源端之间的电压差。
如图3、7、11所示，第一桥接部41可以分别通过过孔连接第二初始信号线Vinit2、第十四有源部714，以连接第七晶体管的第一极和第二初始信号端。第二桥接部42可以通过过孔连接第十有源部710，以连接第六晶体管的第二极和第七晶体管的第二极。第三桥接部43可以通过过孔连接第十六有源部716，以连接第四晶体管的第一极。第四桥接部44可以分别通过过孔连接第八有源部78和第一导电部11，以连接第二晶体管T2的第一极、第一晶体管T1的第二极、驱动晶体管T3的栅极。
如图3、8所示，第五导电层可以包括第五桥接部55、数据线Da，数据线Da可以用于提供图1中的数据信号端。第五桥接部55可以通过过孔连接第二桥接部42，以连接第六晶体管的第二极，第五桥接部55还可以连接发光单元的第一电极。数据线Da在衬底基板上的正投影可以沿第二方向Y延伸，数据线Da可以通过过孔连接第三桥接部43，以连接第四晶体管的第一极和数据信号端。
需要说明的是，如图3、11所示，画于第四导电层背离衬底基板一侧的黑色方块表示第四导电层连接面向衬底基板一侧的其他层级的过孔；画于第五导电层背离衬底基板一侧的黑色方块表示第五导电层连接面向衬底基板一侧的其他层级的过孔；画于电极层背离衬底基板一侧的黑色方块表示电极层连接面向衬底基板一侧的其他层级的过孔。该黑色方块仅表示过孔的位置，不同位置黑色方块所表示的不同过孔可以贯穿于不同绝缘层。
如图12所示，为图3所示显示面板沿虚线AA剖开的部分剖视图。该显示面板还可以包括缓冲层91、绝缘层92、介电层93、钝化层94、第一平坦层95。其中，衬底基板、遮挡层、缓冲层91、第一有源层、绝缘层92、第一导电层、介电层93、第四导电层、钝化层94、第一平坦层95、 第五导电层依次层叠设置。缓冲层91可以包括氧化硅层和氮化硅层。绝缘层92可以为单层结构或多层结构，绝缘层92的材料可以为氮化硅、氧化硅、氮氧化硅中的至少一种；介电层93可以为氮化硅层；钝化层94可以为氧化硅层；第一平坦层95的材料可以为有机材料，例如聚酰亚胺(PI)、聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)、硅-玻璃键合结构(SOG)等材料；衬底基板90可以包括依次层叠设置的玻璃基板、阻挡层、聚酰亚胺层，阻挡层可以为无机材料。第一导电层的材料可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等。第四导电层、第五导电层的材料可以包括金属材料，例如可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层。该显示面板还可以包括第二平坦层、电极层、像素定义层，第二平坦层位于第五导电层背离衬底基板的一侧，电极层位于第二平坦层背离衬底基板的一侧，像素定义层位于电极层背离衬底基板的一侧。
需要说明的是，本公开中的附图比例可以作为实际工艺中的参考，但不限于此，例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图。此外，第一、第二等限定词仅用于限定不同的结构名称，其并没有特定顺序的含义。
如图13-15所示，图13为本公开显示面板另一种示例性实施例的结构版图，图14为图13中遮挡层的结构版图，图15为图13中阻挡层和第一有源层的结构版图。
如图14、15所示，第一有源层还可以包括第十七有源部717，第十七有源部717连接于第二有源部72和第六有源部76之间，且第十七有源部717在衬底基板上的正投影沿第二方向Y延伸，其中，第十七有源部717为驱动晶体管第二极的等电位点。图13所示显示面板与图3所示显示面板区别在于，图13所示显示面板中，在第一方向X上相邻第一遮挡部61之间具有断口D1，即在第一方向X上相邻第一遮挡部61没有直接连接。断口D1在衬底基板上的正投影和第十七有源部717在衬底基板上的正投影相交。该设置可以降低第十七有源部717和遮挡层之间的寄生电容，从 而可以改善显示面板残影的问题。如图14所示，遮挡层包括有第一连接部64，第一连接部64连接于位于同一行的相邻像素驱动电路中第三遮挡部63和第二遮挡部62之间。第一连接部64在所述衬底基板上的正投影可以位于所述第一栅线G1在所述衬底基板上的正投影远离所述第一导电部11在所述衬底基板上的正投影的一侧。即第一连接部64在衬底基板上的正投影与第十七有源部717在衬底基板上的正投影不交叠。本示例性实施例可以通过第一连接部64连接在第一方向X上相邻的两第一遮挡部61。此外，图14所示显示面板的其他结构可以与图3所示显示面板相同。
如图16-19所示，图16为本公开显示面板另一种示例性实施例的结构版图，图17为图16中第四导电层的结构版图，图18为图16中第五导电层的结构版图，图19为图16中遮挡层、第一有源层、第一导电层、第四导电层的结构版图。
图16所示显示面板与图3所示显示面板区别在于，图16所示显示面板中，第五导电层还可以包括第二初始连接线5Vinit2。第二初始连接线5Vinit2在衬底基板上的正投影可以沿第二方向Y延伸。第二初始连接线5Vinit2可以通过过孔连接第一桥接部41，以连接第二初始信号线Vinit2，第二初始连接线5Vinit2和第二初始信号线Vinit2可以形成网格结构，该网格结构可以降低显示面板不同位置上第二初始信号端之间的电压差。图16所示显示面板的其他结构可以与图3所示显示面板相同。
如图20-23所示，图20为本公开显示面板另一种示例性实施例的结构版图，图21为图20中遮挡层的结构版图，图22为图20中第四导电层的结构版图，图23为图20中遮挡层、第一有源层、第一导电层、第四导电层的结构版图。
图20所示显示面板与图3所示显示面板区别在于，图20所示显示面板中，第四导电层还包括第二初始连接线4Vinit2。其中，相邻两列像素驱动电路可以对应设置一条第一初始连接线4Vinit1和一条第二初始连接线4Vinit2。第四导电层还可以包括第六桥接部46，第一初始连接线4Vinit1可以通过第六桥接部46与第一初始信号线Vinit1过孔连接，第二初始连接线4Vinit2可以通过第一桥接部41与第二初始信号线Vinit2过孔连接。图20所示显示面板的其他结构可以与图3所示显示面板相同。
如图24-27所示，图24为本公开显示面板另一种示例性实施例的结构版图，图25为图24中第四导电层的结构版图，图26为图25中第五导电层的结构版图，图27为图24中遮挡层、第一有源层、第一导电层、第四导电层的结构版图。
图24所示显示面板与图3所示显示面板区别在于，图24所示显示面板中，第四导电层没有设置电源线VDD，第四导电层增设了第七桥接部47，第七桥接部47通过过孔连接第一遮挡部61。图24所示显示面板中第五导电层增设了电源线VDD和第二初始连接线5Vinit2。电源线VDD通过过孔连接第七桥接部47，以连接电容的第二电极。电源线VDD在衬底基板上的正投影还可以覆盖第四桥接部44在衬底基板上的正投影，电源线VDD可以屏蔽其他信号对第四桥接部44的噪音干扰，从而降低驱动晶体管T3栅极的电压波动。第二初始连接线5Vinit2通过过孔连接第一桥接部41，从而第二初始连接线5Vinit2可以与第二初始信号线Vinit2形成网格结构。该网格结构可以降低显示面板不同位置上第二初始信号端的电压差。图24所示显示面板的其他结构可以与图3所示显示面板相同。
本示例性实施例利用遮挡层形成显示面板中的部分信号线和器件结构，从而提高了显示面板的集成度。此外，该显示面板相比于相关技术中的显示面板，该显示面板通过第一遮挡部61和第五延伸部VDD5形成电容的第二电极，该显示面板不需要设置第二栅极层。该显示面板中第二遮挡部62和第三遮挡部63直接连接第一遮挡部61，第二遮挡部62和第三遮挡部63不需要通过过孔连接电源线，从而减少了过孔的数量。应该理解的是，遮挡层还可以包括其他独立设置的遮挡部，遮挡部还可以用于形成其他信号线和器件结构。
相关技术中，衬底基板中的PI层(聚酰亚胺)容易产生负静电场，负静电场会使得晶体管的阈值正偏。例如，该负静电场容易导致驱动晶体管阈值正向偏移，驱动晶体管阈值正向偏移会导致显示面板铜棒测试发绿等不良现象。上述的第一遮挡部61可以屏蔽上述负静电场对驱动晶体管T3的阈值影响。此外，遮挡层可以为遮光结构，遮挡层可以避免光照对晶体管特性的影响。
相关技术中，驱动晶体管T3阈值正偏会增加相同灰阶下的驱动电流， 从而容易导致显示面板显示发绿。本示例性实施例中，上述的第一遮挡部61可以接收一正电源电压，第一遮挡部61产生的正电场会使得驱动晶体管的阈值负偏，从而降低了显示面板发绿的风险。
应该理解的是，在其他示例性实施例中，像素驱动电路中其他晶体管的阈值电压也会发生阈值漂移，从而导致晶体管漏电流等问题。例如，在图1中，第一晶体管T1、第二晶体管T2的漏电流会导致显示面板闪烁等不良，第六晶体管T6的漏电流会导致显示面板四分屏等不良。本示例性实施例中，遮挡层还可以包括其他遮挡部，其他遮挡部在衬底基板上的正投影可以分别覆盖其他晶体管沟道区在衬底基板上的正投影的至少部分结构。其他遮挡部可以独立设置也可以至少部分连接。其中，遮挡部独立设置，可以理解为该遮挡部与其他遮挡部不连接。
多个独立设置的遮挡部可以接收不同的电源电压，遮挡部接收电源电压的大小可以受晶体管的类型影响。例如，P型晶体管下方的遮挡部可以接收正的电源电压，遮挡部形成的正电场可以使得P型晶体管的阈值负偏，从而降低P型晶体管的关断漏电流。N型晶体管下方的遮挡部可以连接一负的电源电压，遮挡部形成的负电场可以使得N型晶体管的阈值正偏，从而降低N型晶体管的关断漏电流。例如，图1中第一晶体管和第二晶体管可以为N型晶体管，第一晶体管和第二晶体管下方可以设置有遮挡部，第一晶体管和第二晶体管下方的遮挡部可以接收负的电源电压。
此外，遮挡部接收电源电压的大小可以受到晶体管的工作状态决定。例如，本示例性实施例中，由于第四晶体管T4和第七晶体管T7长期处于正偏状态，第五晶体管T5和第六晶体管T6长期处于负偏状态，位于第四晶体管T4和第七晶体管T7下方遮挡部接收的正电压可以大于位于第五晶体管T5和第六晶体管T6下方遮挡部接收的正电压。例如，位于第四晶体管T4和第七晶体管T7下方遮挡部接收的电压可以为6.6V，位于第五晶体管T5和第六晶体管T6下方遮挡部接收的电压可以为2.6V。
此外，遮挡部接收电源电压的大小可以受到晶体管的尺寸影响。例如，驱动晶体管沟道区的长宽比大于第五晶体管T5沟道区的长宽比，驱动晶体管下方遮挡部接收的电压可以大于第五晶体管T5下方遮挡部接收的电压，例如，驱动晶体管下方遮挡部接收的电压可以为4.6V。
此外，遮挡部接收电源电压的大小可以受到晶体管所处的位置影响。显示面板中不同区域晶体管的密度存在差异，靠近低密度晶体管区域的晶体管的阈值容易发生偏移。如图28所示，为本公开显示面板一种示例性实施例的结构示意图。显示面板可以包括高密度集成区H和低密度集成区L，所述高密度集成区H中晶体管的密度大于所述低密度集成区L中晶体管的密度。所述高密度集成区包括第一高密度集成区H1和第二高密度集成区H2，所述第二高密度集成区H2位于所述第一高密度集成区H1远离所述低密度集成区L的一侧。在所述像素驱动电路中同一晶体管对应的遮挡部中，位于所述第一高密度集成区H1中的遮挡部用于接收的电压的绝对值大于位于所述第二高密度集成区H2中的遮挡部用于接收的电压的绝对值。例如，在所述像素驱动电路中驱动晶体管对应的遮挡部中，第一高密度集成区H1中驱动晶体管对应的遮挡部用于接收的正电源电压大于第二高密度集成区H2中驱动晶体管对应的遮挡部用于接收的正电源电压。再例如，当图1中第一晶体管为N型晶体管时，在所述像素驱动电路中第一晶体管对应的遮挡部中，第一高密度集成区H1中第一晶体管对应的遮挡部用于接收的负电源电压小于第二高密度集成区H2中第一晶体管对应的遮挡部用于接收的正电源电压。
本示例性实施例中，低密度集成区L可以为显示面板的边框区、屏下摄像头集成区、显示区中的透光区等。低密度集成区L中晶体管的密度可以为零。
本示例性实施例中，显示面板中像素驱动电路还可以为其他结构。如图29所示，为本公开显示面板另一种示例性实施例中像素驱动电路的电路结构示意图。该像素驱动电路可以包括：驱动晶体管T3、第一晶体管T1、第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、电容C。与图1所示像素驱动电路区别在于，图29所示像素驱动电路中的第一晶体管和第二晶体管为N型晶体管。
如图30所示，为图29中像素驱动电路一种驱动方法中各节点的时序图。其中，G1表示第一栅极驱动信号端G1的时序，G2表示第二栅极驱动信号端G2的时序，Re1表示第一复位信号端Re1的时序，Re2表示第二复位信号端Re2的时序，EM表示使能信号端EM的时序，Da表示数据信号端 Da的时序。该像素驱动电路的驱动方法可以包括第一复位阶段t1、补偿阶段t2，第二复位阶段t3、发光阶段t4。在第一复位阶段t1：第一复位信号端Re1输出高电平信号，第一晶体管T1导通，第一初始信号端Vinit1向节点N输入初始信号。在补偿阶段t2：第一栅极驱动信号端G1输出高电平信号，第二栅极驱动信号端G2输出低电平信号，第四晶体管T4、第二晶体管T2导通，同时数据信号端Da输出驱动信号以向节点N写入电压Vdata+Vth(即电压Vdata与Vth之和)，其中Vdata为数据信号的电压，Vth为驱动晶体管T3的阈值电压，在第二复位阶段t3，第二复位信号端Re2输出低电平信号，第七晶体管T7导通，第二初始信号端Vinit2向第六晶体管T6的第二极输入初始信号。发光阶段t4：使能信号端EM输出低电平信号，第六晶体管T6、第五晶体管T5导通，驱动晶体管T3在电容C存储的电压Vdata+Vth作用下驱动发光单元发光。
驱动晶体管输出电流公式如下：
I＝(μWCox/2L)(Vgs-Vth)2
其中，I为驱动晶体管输出电流；μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电压。
根据上述驱动晶体管输出电流公式，将本公开像素驱动电路中驱动晶体管的栅极电压Vdata+Vth和源极电压Vdd带入上述公式可以得到：本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth)2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。
本示例性实施例还提供另一种显示面板，该显示面板可以包括依次层叠设置的衬底基板、遮挡层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层、第五导电层、电极层，其中，上述层级之间可以设置有绝缘层。如图31-46所示，图31为本公开显示面板另一种示例性实施例中的结构版图，图32为图31中遮挡层的结构版图，图33为图31中第一有源层的结构版图，图34为图31中第一导电层的结构版图，图35为图31中第二导电层的结构版图，图36为图31中第二有源层的结构版图，图37为图31中第三导电层的结构版图，图38为图31 中第四导电层的结构版图，图39为27中第五导电层的结构版图，图40为图31中遮挡层、第一有源层的结构版图，图41为图31中遮挡层、第一有源层、第一导电层的结构版图，图42为图31中遮挡层、第一有源层、第一导电层、第二导电层的结构版图，图43为图31中遮挡层、第一有源层、第一导电层、第二导电层、第二有源层的结构版图，图44为图31中遮挡层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层的结构版图，图45为图31中遮挡层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层的结构版图；图46为图31中遮挡层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层、第五导电层的结构版图。该显示面板可以包括多个图29所示的像素驱动电路。如图46所示，多个像素驱动电路中可以包括在行方向X上相邻分布第一像素驱动电路P1和第二像素驱动电路P2，第一像素驱动电路P1和第二像素驱动电路P2可以镜像对称设置。其中，第一像素驱动电路P1和第二像素驱动电路P2可以形成一重复单元，该显示面板可以包括在行方向X和列方向Y上阵列分布的多个重复单元。
如图31、32、40所示，遮挡层可以包括正压遮挡部BSM1和负压遮挡部BSM2。正压遮挡部BSM1用于接收正的电源电压，负压遮挡部BSM2用于接收负的电源电压。正压遮挡部BSM1在衬底基板上的正投影和负压遮挡部BSM2在衬底基板上的正投影均可以沿列方向Y延伸。其中，在行方向X上相邻的负压遮挡部BSM2可以相互连接，也可以相互独立设置。在行方向X上相邻的正压遮挡部BSM1可以相互连接，也可以相互独立设置。遮挡层可以为导体结构，例如，遮挡层可以为钼层。
如图31、33、40、41所示，第一有源层可以包括第三有源部73、第四有源部74、第五有源部75、第六有源部76、第七有源部77、第八有源部78、第九有源部79、第十有源部710、第十一有源部711。其中，第三有源部73可以用于形成驱动晶体管T3的沟道区；第四有源部74可以用于形成第四晶体管T4的沟道区；第五有源部75可以用于形成第五晶体管T5的沟道区；第六有源部76可以用于形成第六晶体管T6的沟道区；第七有源部77可以用于形成第七晶体管T7的沟道区；第八有源部78连接于第五有源部75远离第三有源部73的一侧，第九有源部79连接于第一像 素驱动电路P1中第八有源部78和第二像素驱动电路P2中第八有源部78之间。第十有源部710连接于第六有源部76和第七有源部77之间，第十一有源部711连接于第六有源部76和第三有源部73之间。其中，第八有源部78可以用于形成第五晶体管的第一极，本示例性实施例中，通过第九有源部79连接相邻两像素驱动电路中的第八有源部，从而可以降低该相邻像素驱动电路中第一电源端的电压差。如图40所示，正压遮挡部BSM1在衬底基板上的正投影可以与第三有源部73在衬底基板上的正投影、第四有源部74在衬底基板上的正投影、第五有源部75在衬底基板上的正投影、第七有源部77在衬底基板上的正投影至少部分交叠，例如，正压遮挡部BSM1在衬底基板上的正投影可以覆盖第三有源部73在衬底基板上的正投影、第四有源部74在衬底基板上的正投影、第五有源部75在衬底基板上的正投影、第七有源部77在衬底基板上的正投影。第一有源层可以由多晶硅材料形成，相应的，驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型的低温多晶硅薄膜晶体管。
如图31、34、41所示，第一导电层可以包括：第一导电部11、第二栅线G2、使能信号线EM、第二复位信号线Re2。第二栅线G2可以用于提供图29中第二栅极驱动信号端；使能信号线EM可以用于提供图29中的使能信号端；第二复位信号线Re2可以用于提供图29中的第二复位信号端。第二栅线G2在衬底基板上的正投影、使能信号线EM在衬底基板上的正投影、第二复位信号线Re2在衬底基板上的正投影均可以沿行方向X延伸。第二栅线G2在衬底基板上的正投影覆盖第四有源部74在衬底基板上的正投影，第二栅线G2的部分结构用于形成第四晶体管的栅极。使能信号线EM在衬底基板上的正投影覆盖第五有源部75在衬底基板上的正投影、第六有源部76在衬底基板上的正投影，使能信号线EM的部分结构可以分别用于形成第五晶体管T5、第六晶体管T6的栅极。第二复位信号线Re2在衬底基板上的正投影可以覆盖第七有源部77在衬底基板上的正投影，第二复位信号线Re2的部分结构可以用于形成第七晶体管T7的栅极。第一导电部11在衬底基板上的正投影覆盖第三有源部73在衬底基板上的正投影，第一导电部11可以用于形成驱动晶体管T3的栅极和电容的第一电 极。如图41所示，本行像素驱动电路中的第二栅线G2可以复用为上一行像素驱动电路中的第二复位信号线Re2。该设置可以提高像素驱动电路的集成度，降低像素驱动电路的布图面积。此外，该显示面板可以利用第一导电层为掩膜对第一有源层进行导体化处理，即第一有源层中被第一导电层覆盖的区域可以形成晶体管的沟道区，第一有源层中未被第一导电层覆盖的区域形成导体结构。
如图31、35、42所示，第二导电层可以包括：第一初始信号线Vinit1、第三复位信号线2Re1、第三栅线2G1、多个第二导电部22。其中，第一初始信号线Vinit1用于提供图29中的第一初始信号端，第三复位信号线2Re1可以用于提供图29中的第一复位信号端，第三栅线2G1可以用于提供图29中的第一栅极驱动信号端。第一初始信号线Vinit1在衬底基板上的正投影、第三复位信号线2Re1在衬底基板上的正投影、第三栅线2G1在衬底基板上的正投影均可以沿行方向X延伸。如图35所示，第二导电层还可以包括多个第三连接部23，在同一重复单元中，第三连接部23连接于在行方向上相邻的两第二导电部22之间。此外，在其他示例性实施例中，在行方向上相邻的重复单元中，相邻第二导电部22也可以相连接。
如图31、36、43所示，第二有源层可以包括有源部81，有源部81可以包括相连接的第一有源部811、第二有源部812、第十二有源部813，第一有源部811可以用于形成第一晶体管的沟道区；第二有源部812可以用于形成第二晶体管T2的沟道区；第十二有源部813连接于第二有源部812远离第一有源部811的一端。其中，第二有源层可以由氧化铟镓锌形成，相应的，第一晶体管T1、第二晶体管T2可以为N型的金属氧化物薄膜晶体管。第三栅线2G1在衬底基板上的正投影可以覆盖第二有源部812在衬底基板上的正投影，第三栅线2G1的部分结构可以用于形成第二晶体管的底栅。第三复位信号线2Re1在衬底基板上的正投影可以覆盖第一有源部811在衬底基板上的正投影，第三复位信号线2Re1的部分结构可以用于形成第一晶体管T1的底栅。负压遮挡部BSM2在衬底基板上的正投影可以与第一有源部811在衬底基板上的正投影、第二有源部812在衬底基板上的正投影交叠，例如，负压遮挡部BSM2在衬底基板上的正投影可以覆盖第一有源部811在衬底基板上的正投影、第二有源部812在衬底基板 上的正投影。
如图31、37、44所示，第三导电层可以包括第一复位信号线3Re1、第一栅线3G1。第一复位信号线3Re1在衬底基板上的正投影、第一栅线3G1在衬底基板上的正投影均可以沿行方向X延伸。第一复位信号线3Re1可以用于提供图29中的第一复位信号端，第一复位信号线3Re1在衬底基板上的正投影可以覆盖第一有源部811在衬底基板上的正投影，第一复位信号线3Re1的部分结构可以用于形成第一晶体管T1的顶栅，同时，第一复位信号线3Re1可以通过位于显示面板边沿走线区的过孔连接第三复位信号线2Re1。第一栅线3G1可以用于提供图29中的第一栅极驱动信号端，第一栅线3G1在衬底基板上的正投影可以覆盖第二有源部812在衬底基板上的正投影，第一栅线3G1的部分结构可以用于形成第二晶体管T2的顶栅，同时，第一栅线3G1可以通过位于显示面板边沿走线区的过孔连接第三栅线2G1。如图31、44所示，在同一像素驱动电路中，第一导电部11在所述衬底基板上的正投影可以位于所述第一栅线3G1在所述衬底基板上的正投影和所述使能信号线EM在所述衬底基板上的正投影之间；第一复位信号线3Re1在所述衬底基板上的正投影可以位于第一栅线3G1在所述衬底基板上的正投影远离所述第一导电部11在所述衬底基板上的正投影的一侧。第二栅线G2在衬底基板上的正投影可以位于第一栅线3G1在所述衬底基板上的正投影和第一复位信号线3Re1在所述衬底基板上的正投影之间。第二复位信号线Re2在所述衬底基板上的正投影可以位于所述使能信号线EM在所述衬底基板上的正投影远离所述第一导电部11在所述衬底基板上的正投影的一侧。此外，该显示面板可以利用第三导电层为掩膜对第二有源层进行导体化处理，即第二有源层中被第三导电层覆盖的区域可以形成晶体管的沟道区，第二有源层中未被第三导电层覆盖的区域形成导体结构。
如图31、38、45所示，第四导电层可以包括第一桥接部41、第二桥接部42、第三桥接部43、第四桥接部44、第五桥接部45、第六桥接部46、第二初始信号线Vinit2。其中，第一桥接部41可以通过两个过孔H连接第三连接部23，且通过过孔连接第九有源部79，以连接第五晶体管的第一极和电容C的第二电极。需要说明的是，本示例性实施例中黑色方块表 示过孔的位置，本示例性实施例仅对部分过孔进行了标注。第一桥接部41可以以第一像素驱动电路P1和第二像素驱动电路P2的镜像对称面镜像对称。第二桥接部42可以通过过孔连接第十有源部710，以连接第六晶体管T6的第二极和第七晶体管T7的第一极。第三桥接部43可以分别通过过孔连接第十一有源部711、第十二有源部813，以连接第二晶体管T2的第二极、第六晶体管T6的第一极、驱动晶体管T3的第二极。第四桥接部44可以分别通过过孔连接第一有源部811和第二有源部812之间的第二有源层、第一导电部11，以连接第二晶体管T2的第一极和驱动晶体管的栅极。如图35所示，第二导电部22上形成有开口221，连接于第一导电部11和第四桥接部44之间的过孔在衬底基板上的正投影位于开口221在衬底基板上的正投影以内，以使该过孔内的导电结构与第二导电部22相互绝缘。第五桥接部45可以分别通过过孔连接第一有源部811远离第二有源部812一侧的第二有源层、第一初始信号线Vinit1，以连接第一晶体管的第二极和第一初始信号端。其中，在行方向上相邻的两重复单元中，相邻两像素驱动电路可以共用同一第五桥接部45。第六桥接部46可以通过过孔连接第四有源部74远离第三有源部73一侧的第一有源层，以连接第四晶体管的第一极。第二初始信号线Vinit2可以用于提供图29中的第二初始信号端，第二初始信号线Vinit2可以通过过孔连接第七有源部77远离第六有源部76一侧的第一有源层，以连接第七晶体管的第二极和第二初始信号端。
如图31、39、46所示，第五导电层可以包括多条电源线VDD、多条数据线Da、第七桥接部57。其中，电源线VDD在衬底基板上的正投影、数据线Da在衬底基板上的正投影均可以沿列方向Y延伸。电源线VDD可以用于提供图29中的第一电源端，数据线Da可以用于提供图29中的数据信号端。如图31所示，每列像素驱动电路可以对应设置一条电源线，第一像素驱动电路P1中的电源线VDD可以通过过孔连接第一桥接部41，第二像素驱动电路P2中的电源线VDD可以通过过孔连接同一第一桥接部41，从而连接第五晶体管的第一极和第一电源端。数据线Da可以通过过孔连接第六桥接部46，以连接第四晶体管的第一极和数据信号端。第七桥接部57可以通过过孔连接第二桥接部42，以连接第七晶体管的第一极。如图 39所示，电源线VDD可以包括第一延伸部VDD1、第二延伸部VDD2、第三延伸部VDD3，第二延伸部VDD2连接于第一延伸部VDD1和第三延伸部VDD3之间，第二延伸部VDD2在所述衬底基板上的正投影在行方向X上的尺寸可以大于第一延伸部VDD1在所述衬底基板上的正投影在行方向X上的尺寸，且所述第二延伸部VDD2在所述衬底基板上的正投影在行方向X上的尺寸可以大于所述第三延伸部VDD3在所述衬底基板上的正投影在行方向X上的尺寸。第二延伸部VDD2在衬底基板上的正投影可以覆盖第一有源部811在衬底基板上的正投影、第二有源部812在衬底基板上的正投影，第二延伸部VDD2可以降低光照对第一晶体管T1、第二晶体管T2的特性影响。在行方向上相邻的两重复单元中，相邻两像素驱动电路中第二延伸部VDD2可以相互连接，从而电源线VDD和第二导电部22可以形成网格结构，该网格结构的电源线可以降低其上电源信号的压降。
如图31所示，电极层可以包括多个电极部，多个所述电极部包括：多个R电极部R、多个G电极部G、多个B电极部B。
如图47所示，为图31中沿虚线BB的部分剖视图。该显示面板可以包括第一绝缘层91、第二绝缘层92、第三绝缘层93、第四绝缘层94、第五绝缘层95、第一介电层96、第一平坦层97、第二平坦层98。其中，衬底基板90、遮光层、第一绝缘层91、第一有源层、第二绝缘层92、第一导电层、第三绝缘层93、第二导电层、第四绝缘层94、第二有源层、第五绝缘层95、第三导电层、第一介电层96、第四导电层、第一平坦层97、第五导电层、第二平坦层98、电极层依次层叠设置。第一绝缘层91、第二绝缘层92、第三绝缘层93、第四绝缘层94、第五绝缘层95可以为单层结构或多层结构，且第一绝缘层91、第二绝缘层92、第三绝缘层93、第四绝缘层94、第五绝缘层95的材料可以为氮化硅，氧化硅，氮氧化硅中的至少一种；第一介电层96可以为氮化硅层；第一平坦层97、第二平坦层98的材料可以为有机材料，例如聚酰亚胺(PI)、聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)、硅-玻璃键合结构(SOG)等材料。衬底基板90可以包括依次层叠设置的玻璃基板、阻挡层、聚酰亚胺层，阻挡层可以为无机材料。第一导电层、第二导电层、第三导电层的材料可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等。 第四导电层、第五导电层的材料可以包括金属材料，例如，可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层。
如图48所示，为本公开显示面板另一种示例性的结构示意图。该显示面板可以包括显示区AA和位于显示区周围的边框区B。边框区B中也可以设置有上述的遮挡部。例如，边框区B可以包括用于集成栅极驱动电路的第一边框区B1，用于扇出数据线的扇出区B2。位于第一边框区B1的遮挡部可以形成栅极驱动电路中的信号线或者器件结构，位于扇出区B2的遮挡部可以用于形成数据线的扇出线。此外，位于边框区B的遮挡部可以用于形成检测电路中的信号线或者器件结构。该设置可以将遮挡层均匀的分布在基板上，从而在工艺过程中不会造成刻蚀不均，工艺参数不好管控等问题。
本示例性实施例还提供一种显示装置，其中，包括上述的显示面板。该显示装置可以为手机、平板电脑、电视等显示装置。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (21)

  1. 一种显示面板，其中，所述显示面板包括像素驱动电路，所述像素驱动电路包括晶体管，所述显示面板还包括：
    衬底基板；
    第一有源层，位于所述衬底基板的一侧，所述第一有源层的至少部分结构用于形成所述晶体管的沟道区；
    遮挡层，位于所述衬底基板和所述第一有源层之间，所述遮挡层为导电层，所述遮挡层包括多个独立设置的遮挡部，至少部分不同的所述遮挡部用于接收不同的信号。
  2. 根据权利要求1所述的显示面板，其中，所述像素驱动电路包括驱动晶体管、第一晶体管，所述第一晶体管的第一极连接第一初始信号线，第二极连接所述驱动晶体管的栅极；
    多个所述遮挡部中包括所述第一初始信号线。
  3. 根据权利要求2所述的显示面板，其中，所述第一有源层包括第一有源部、第三子有源部，所述第一有源部用于形成所述第一晶体管的沟道区，所述第一有源部包括第一子有源部和第二子有源部，所述第三子有源部连接于所述第一子有源部和所述第二子有源部之间；
    所述第一初始信号线包括第一延伸部，所述第一延伸部在所述衬底基板上的正投影与所述第三子有源部在所述衬底基板上的正投影至少部分交叠。
  4. 根据权利要求2所述的显示面板，其中，所述显示面板还包括：
    第一导电层，位于所述第一有源层背离所述衬底基板的一侧，所述第一导电层包括第一复位信号线，所述第一复位信号线在所述衬底基板上的正投影沿第一方向延伸且覆盖所述第一有源部在所述衬底基板上的正投影，所述第一复位信号线的部分结构用于形成所述第一晶体管的栅极；
    所述第一初始信号线包括第二延伸部，所述第二延伸部在所述衬底基板上的正投影与所述第一复位信号线在所述衬底基板上的正投影至少部分交叠。
  5. 根据权利要求2所述的显示面板，其中，所述显示面板还包括：
    第四导电层，位于所述第一有源层背离所述衬底基板的一侧，所述第 四导电层包括第一初始连接线；
    其中，所述第一初始信号线在所述衬底基板上的正投影沿第一方向延伸，所述第一初始连接线在所述衬底基板上的正投影沿第二方向延伸，所述第一方向和所述第二方向相交，且所述第一初始连接线通过过孔连接与其在所述衬底基板上正投影相交的所述第一初始信号线。
  6. 根据权利要求1所述的显示面板，其中，所述显示面板还包括发光单元，所述像素驱动电路包括第七晶体管，所述第七晶体管的第一极连接第二初始信号线，第二极连接所述发光单元的第一电极；
    多个所述遮挡部中包括所述第二初始信号线。
  7. 根据权利要求6所述的显示面板，其中，所述像素驱动电路还包括驱动晶体管、第六晶体管，所述第六晶体管的第一极连接所述驱动晶体管的第二极，第二极连接所述发光单元的第一电极；
    所述第一有源层包括第六有源部、第七有源部，所述第六有源部用于形成所述第六晶体管的沟道区，所述第七有源部用于形成所述第七晶体管的沟道区；
    所述显示面板还包括：第一导电层，所述第一导电层位于所述第一有源层背离所述衬底基板的一侧，所述第一导电层包括：
    使能信号线，所述使能信号线在所述衬底基板上的正投影沿第一方向延伸且覆盖所述第六有源部在所述衬底基板上的正投影，所述使能信号线的部分结构用于形成所述第六晶体管的栅极；
    第二复位信号线，所述第二复位信号线在所述衬底基板上的正投影沿第一方向延伸且覆盖所述第七有源部在所述衬底基板上的正投影，所述第二复位信号线的部分结构用于形成所述第七晶体管的栅极；
    其中，所述第二初始信号线在所述衬底基板上的正投影位于所述使能信号线在所述衬底基板上的正投影和所述第二复位信号线在所述衬底基板上的正投影之间。
  8. 根据权利要求6所述的显示面板，其中，所述显示面板还包括：
    第四导电层，位于所述第一有源层背离所述衬底基板的一侧，所述第四导电层包括第二初始连接线；
    其中，所述第二初始信号线在所述衬底基板上的正投影沿第一方向延 伸，所述第二初始连接线在所述衬底基板上的正投影沿第二方向延伸，所述第一方向和所述第二方向相交，且所述第二初始连接线通过过孔连接与其在所述衬底基板上正投影相交的所述第二初始信号线。
  9. 根据权利要求1所述的显示面板，其中，所述像素驱动电路包括驱动晶体管，所述第一有源层包括第三有源部，所述第三有源部用于形成所述驱动晶体管的沟道区；
    多个所述遮挡部中包括第一遮挡部，所述第一遮挡部连接一稳定电压源，且所述第一遮挡部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影。
  10. 根据权利要求9所述的显示面板，其中，所述像素驱动电路还包括电容，所述电容的第一电极连接所述驱动晶体管的栅极，所述电容的第二电极连接电源线；
    所述显示面板还包括：
    第一导电层，位于所述第一有源层背离所述衬底基板的一侧，所述第一导电层包括第一导电部，所述第一导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第一导电部用于形成所述驱动晶体管的栅极和所述电容的第一电极；
    所述电源线形成所述稳定电压源，所述第一遮挡部用于形成所述电容的第二电极。
  11. 根据权利要求10所述的显示面板，其中，所述显示面板还包括：
    第四导电层，位于所述第一导电层背离所述衬底基板的一侧，所述第四导电层包括所述电源线，所述电源线在所述衬底基板上的正投影沿第二方向延伸；
    所述显示面板包括在第一方向和所述第二方向上阵列分布的多个所述像素驱动电路，所述第一方向和所述第二方向相交，在所述第一方向上分布的多个所述第一遮挡部相连接，所述电源线通过过孔连接所述第一遮挡部。
  12. 根据权利要求11所述的显示面板，其中，所述电源线包括第三延伸部、第四延伸部，以及连接于所述第三延伸部和所述第四延伸部之间的第五延伸部，所述第五延伸部在所述衬底基板上的正投影在第一方向上 的尺寸大于所述第三延伸部在所述衬底基板上的正投影在第一方向上的尺寸，所述第五延伸部在所述衬底基板上的正投影在第一方向上的尺寸大于所述第四延伸部在所述衬底基板上的正投影在第一方向上的尺寸，所述第一方向和所述第二方向相交；
    所述第五延伸部在所述衬底基板上的正投影与所述第一导电部在所述衬底基板上的正投影至少部分交叠，所述第五延伸部的至少部分结构用于形成所述电容的第二电极。
  13. 根据权利要求9所述的显示面板，其中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，所述第二晶体管的第二极连接所述驱动晶体管的第二极；
    所述第一有源层还包括第二有源部、第六子有源部，所述第二有源部用于形成所述第二晶体管的沟道区，所述第二有源部包括第四子有源部和第五子有源部，所述第六子有源部连接于所述第四子有源部和所述第五子有源部之间；
    所述遮挡层还包括第二遮挡部，所述第二遮挡部连接于所述第一遮挡部，所述第一遮挡部包括第一边沿，所述第二遮挡部包括第二边沿，所述第一边沿和所述第二边沿连接，且所述第一边沿在所述衬底基板上的正投影与所述第二边沿在所述衬底基板上的正投影之间的夹角小于180°，所述第二遮挡部在所述衬底基板上的正投影与所述第六子有源部在所述衬底基板上的正投影至少部分交叠。
  14. 根据权利要求9所述的显示面板，其中，所述像素驱动电路还包括第一晶体管、第二晶体管，所述第一晶体管的第一极连接第一初始信号线，第二极连接所述驱动晶体管的栅极，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极；
    所述第一有源层还包括第一有源部、第二有源部、第八有源部，所述第一有源部用于形成所述第一晶体管的沟道区，所述第二有源部用于形成所述第二晶体管的沟道区，所述第八有源部连接于所述第一有源部和所述第二有源部之间；
    所述遮挡层还包括第三遮挡部，所述第三遮挡部连接于所述第一遮挡部，所述第一遮挡部包括第一边沿，所述第三遮挡部包括第三边沿，所述 第一边沿和所述第三边沿连接，且所述第一边沿在所述衬底基板上的正投影与所述第三边沿在所述衬底基板上的正投影之间的夹角小于180°，所述第三遮挡部在所述衬底基板上的正投影与所述第八有源部在所述衬底基板上的正投影至少部分交叠。
  15. 根据权利要求9所述的显示面板，其中，所述像素驱动电路还包括第一晶体管、第二晶体管，所述第一晶体管的第一极连接第一初始信号线，第二极连接所述驱动晶体管的栅极，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极；
    所述第一有源层还包括第一有源部、第二有源部、第六子有源部、第八有源部，所述第一有源部用于形成所述第一晶体管的沟道区，所述第二有源部用于形成所述第二晶体管的沟道区，所述第二有源部包括第四子有源部和第五子有源部，所述第六子有源部连接于所述第四子有源部和所述第五子有源部之间，所述第八有源部连接于所述第一有源部和所述第二有源部之间；
    所述显示面板还包括第一导电层，所述第一导电层位于所述第一有源层背离所述衬底基板的一侧，所述第一导电层包括第一导电部和第一栅线，所述第一导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第一栅线在所述衬底基板上的正投影沿第一方向延伸且覆盖所述第二有源部在所述衬底基板上的正投影；
    所述遮挡层还包括第二遮挡部、第三遮挡部、第一连接部，所述第二遮挡部连接于所述第一遮挡部，所述第二遮挡部在所述衬底基板上的正投影与所述第六子有源部在所述衬底基板上的正投影至少部分交叠；
    所述第三遮挡部连接于所述第一遮挡部，所述第三遮挡部在所述衬底基板上的正投影与所述第八有源部在所述衬底基板上的正投影至少部分交叠；
    所述第一连接部连接于在所述第一方向上相邻像素驱动电路中所述第二遮挡部和所述第三遮挡部之间，且所述第一连接部在所述衬底基板上的正投影位于所述第一栅线在所述衬底基板上的正投影远离所述第一导电部在所述衬底基板上的正投影的一侧。
  16. 根据权利要求1所述的显示面板，其中，所述显示面板还包括显 示区和位于显示区周围的边框区，部分所述遮挡部位于所述显示区，部分所述遮挡部位于所述边框区。
  17. 根据权利要求1所述的显示面板，其中，所述像素驱动电路包括多个晶体管，多个所述遮挡部中包括与所述晶体管对应的恒压遮挡部，所述恒压遮挡部在所述衬底基板上的正投影和与其对应的所述晶体管的沟道区在所述衬底基板上的正投影至少部分交叠；
    至少部分不同的所述恒压遮挡部用于接收不同的电源电压。
  18. 根据权利要求17所述的显示面板，其中，所述像素驱动电路包括N型晶体管和P型晶体管；
    多个所述恒压遮挡部中包括正压遮挡部和负压遮挡部，所述正压遮挡部用于接收正的电源电压，所述负压遮挡部用于接收负的电源电压；
    所述正压遮挡部在所述衬底基板上的正投影与所述P型晶体管沟道区在所述衬底基板上的正投影至少部分交叠，所述负压遮挡部在所述衬底基板上的正投影与所述N型晶体管沟道区在所述衬底基板上的正投影至少部分交叠。
  19. 根据权利要求17所述的显示面板，其中，所述显示面板还包括发光单元，所述像素驱动电路包括驱动晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管，所述驱动晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管为P型晶体管；
    所述第四晶体管的第一极连接数据线，第二极连接所述驱动晶体管的第一极；
    所述第五晶体管的第一极连接第一电源端，第二极连接所述驱动晶体管的第一极；
    所述第六晶体管的第一极连接所述驱动晶体管的第二极，第二极连接所述发光单元的第一电极；
    所述第七晶体管的第一极连接第二初始信号线，第二极连接所述发光单元的第一电极；
    多个所述恒压遮挡部中包括多个正压遮挡部，多个所述正压遮挡部中包括：
    第一正压遮挡部，所述第一正压遮挡部在所述衬底基板上的正投影覆 盖所述驱动晶体管沟道区在所述衬底基板上的正投影；
    第二正压遮挡部，所述第二正压遮挡部在所述衬底基板上的正投影覆盖所述第五晶体管沟道区在所述衬底基板上的正投影、第六晶体管沟道区在所述衬底基板上的正投影；
    第三正压遮挡部，所述第三正压遮挡部在所述衬底基板上的正投影覆盖所述第四晶体管沟道区在所述衬底基板上的正投影、第七晶体管沟道区在所述衬底基板上的正投影；
    其中，所述第一正压遮挡部用于接收的正电压大于所述第二正压遮挡部用于接收的正电压，所述第三正压遮挡部用于接收的正电压大于所述第一正压遮挡部用于接收的正电压。
  20. 根据权利要求17所述的显示面板，其中，所述显示面板包括高密度集成区和低密度集成区，所述高密度集成区中晶体管的密度大于所述低密度集成区中晶体管的密度；
    所述高密度集成区包括第一高密度集成区和第二高密度集成区，所述第二高密度集成区位于所述第一高密度集成区远离所述低密度集成区的一侧；
    在所述像素驱动电路中同一晶体管对应的恒压遮挡部中，位于所述第一高密度集成区中的恒压遮挡部用于接收的电压的绝对值大于位于所述第二高密度集成区中的恒压遮挡部用于接收的电压的绝对值。
  21. 一种显示装置，其中，包括权利要求1-20任一项所述的显示面板。
PCT/CN2022/096331 2022-05-31 2022-05-31 显示面板及显示装置 WO2023230871A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202280001587.0A CN117501855A (zh) 2022-05-31 2022-05-31 显示面板及显示装置
PCT/CN2022/096331 WO2023230871A1 (zh) 2022-05-31 2022-05-31 显示面板及显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/096331 WO2023230871A1 (zh) 2022-05-31 2022-05-31 显示面板及显示装置

Publications (2)

Publication Number Publication Date
WO2023230871A1 true WO2023230871A1 (zh) 2023-12-07
WO2023230871A9 WO2023230871A9 (zh) 2024-02-15

Family

ID=89026705

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/096331 WO2023230871A1 (zh) 2022-05-31 2022-05-31 显示面板及显示装置

Country Status (2)

Country Link
CN (1) CN117501855A (zh)
WO (1) WO2023230871A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150187959A1 (en) * 2013-12-26 2015-07-02 Lg Display Co., Ltd. Array substrate
US20200050036A1 (en) * 2018-08-10 2020-02-13 Sharp Kabushiki Kaisha Display device
CN211293912U (zh) * 2020-03-31 2020-08-18 京东方科技集团股份有限公司 阵列基板和触控显示装置
CN112466209A (zh) * 2020-09-30 2021-03-09 武汉天马微电子有限公司 显示面板和显示装置
CN114156290A (zh) * 2021-12-31 2022-03-08 京东方科技集团股份有限公司 驱动背板及显示面板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150187959A1 (en) * 2013-12-26 2015-07-02 Lg Display Co., Ltd. Array substrate
US20200050036A1 (en) * 2018-08-10 2020-02-13 Sharp Kabushiki Kaisha Display device
CN211293912U (zh) * 2020-03-31 2020-08-18 京东方科技集团股份有限公司 阵列基板和触控显示装置
CN112466209A (zh) * 2020-09-30 2021-03-09 武汉天马微电子有限公司 显示面板和显示装置
CN114156290A (zh) * 2021-12-31 2022-03-08 京东方科技集团股份有限公司 驱动背板及显示面板

Also Published As

Publication number Publication date
CN117501855A (zh) 2024-02-02
WO2023230871A9 (zh) 2024-02-15

Similar Documents

Publication Publication Date Title
US20240257734A1 (en) Display panel and display apparatus
WO2023230885A1 (zh) 显示面板及显示装置
CN114495835B (zh) 像素驱动电路及其驱动方法、显示面板、显示装置
US20240206268A1 (en) Display substrate, method of manufacturing the same, and display apparatus
WO2023230871A1 (zh) 显示面板及显示装置
WO2022126366A1 (zh) 显示基板和显示装置
WO2023159602A9 (zh) 显示面板、显示装置
WO2024000273A1 (zh) 显示面板及显示装置
WO2024045059A1 (zh) 显示面板及显示装置
WO2023245676A9 (zh) 像素驱动电路及其驱动方法、显示面板、显示装置
WO2024045037A1 (zh) 显示面板及显示装置
WO2023206157A1 (zh) 显示面板及显示装置
WO2023201570A1 (zh) 显示面板及显示装置
US20240161696A1 (en) Display panel and display device
US20240306445A1 (en) Display panel and display device
WO2023193207A9 (zh) 显示面板、显示装置
WO2024092496A1 (zh) 像素驱动电路及其驱动方法、显示面板、显示装置
US20240324352A1 (en) Display panel and display apparatus
WO2023050273A9 (zh) 显示面板和显示装置
WO2024065591A1 (zh) 显示面板及显示装置
US20240213261A1 (en) Display panel and display device
CN117337099A (zh) 显示面板及显示装置
KR20240072087A (ko) 표시 패널 및 표시 장치

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22944208

Country of ref document: EP

Kind code of ref document: A1