WO2024065591A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024065591A1
WO2024065591A1 PCT/CN2022/123046 CN2022123046W WO2024065591A1 WO 2024065591 A1 WO2024065591 A1 WO 2024065591A1 CN 2022123046 W CN2022123046 W CN 2022123046W WO 2024065591 A1 WO2024065591 A1 WO 2024065591A1
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WIPO (PCT)
Prior art keywords
transistor
substrate
orthographic projection
base substrate
gate
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PCT/CN2022/123046
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English (en)
French (fr)
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WO2024065591A9 (zh
Inventor
刘彪
尚庭华
龙祎璇
牛佐吉
陈家兴
周洋
张毅
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/123046 priority Critical patent/WO2024065591A1/zh
Publication of WO2024065591A1 publication Critical patent/WO2024065591A1/zh
Publication of WO2024065591A9 publication Critical patent/WO2024065591A9/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel and a display device.
  • a display panel includes: a plurality of pixel driving circuits, the pixel driving circuits including a driving transistor and a fourth transistor, the first electrode of the fourth transistor being connected to a data line, the second electrode being connected to the first electrode of the driving transistor, and the gate being connected to a first gate line; wherein the plurality of pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit; the capacitance formed by the equipotential structure of the gate of the driving transistor in the first pixel driving circuit and the first gate line is C1, the capacitance formed by the equipotential structure of the gate of the driving transistor in the second pixel driving circuit and the first gate line is C2, and C1 is not equal to C2.
  • the display panel also includes a plurality of light-emitting units, including a first light-emitting unit and a second light-emitting unit; the first pixel driving circuit is used to drive the first light-emitting unit, and the second pixel driving circuit is used to drive the second light-emitting unit; under the same driving current, the brightness of the first light-emitting unit is less than the brightness of the second light-emitting unit, and C1 is less than C2.
  • the display panel further comprises: a substrate, a first active layer, a first conductive layer, and a second conductive portion.
  • the first active layer is located on one side of the substrate, the first active layer comprises a third active portion, and the third active portion is used to form a channel region of the driving transistor;
  • the first conductive layer is located on the side of the first active layer away from the substrate, the first conductive layer comprises a first conductive portion, the orthographic projection of the first conductive portion on the substrate covers the orthographic projection of the third active portion on the substrate, and the first conductive portion is used to form a gate of the driving transistor;
  • the second conductive portion is arranged corresponding to the first conductive portion, the second conductive portion is connected to the first conductive portion corresponding thereto, the overlap area of the orthographic projection of the second conductive portion on the substrate and the orthographic projection of the first gate line on the substrate in the first pixel driving circuit is S1, and the overlap area of the orthographic projection of the second conductive portion on the substrate and
  • the pixel driving circuit also includes: an eighth transistor, a first electrode of the eighth transistor is connected to the gate of the driving transistor, and the display panel also includes: a second active layer, the second active layer is located on the side of the first conductive layer away from the substrate, the second active layer includes an eighth active portion and a ninth active portion connected to each other, and the eighth active portion is used to form a channel region of the eighth transistor; wherein the ninth active portion is connected to the first conductive portion, the second conductive portion includes the ninth active portion, and an overlapping area of an orthographic projection of the ninth active portion on the substrate in the first pixel driving circuit and an orthographic projection of the first gate line on the substrate is smaller than an overlapping area of an orthographic projection of the ninth active portion on the substrate in the second pixel driving circuit and an orthographic projection of the first gate line on the substrate.
  • the first conductive layer includes the first gate line, and the orthographic projection of the first gate line on the substrate extends along the first direction.
  • the first gate line includes: a plurality of first extensions and a plurality of second extensions, the orthographic projections of the plurality of first extensions on the substrate extend along the first direction and are spaced apart along the first direction; the second extensions are connected between the first extensions adjacent to each other in the first direction; wherein the size of the orthographic projection of the first extension on the substrate in the second direction is smaller than the size of the orthographic projection of the second extension on the substrate in the second direction, and the first direction and the second direction intersect; the orthographic projection of the second conductive portion on the substrate and the orthographic projection of the second extension on the substrate at least partially overlap.
  • the pixel driving circuit further includes: an eighth transistor, a first electrode of the eighth transistor is connected to the gate of the driving transistor, and the display panel further includes: a second active layer, the second active layer is located on the side of the first conductive layer away from the substrate, the second active layer includes an eighth active portion and a ninth active portion connected to each other, the eighth active portion is used to form a channel region of the eighth transistor; wherein the ninth active portion is connected to the first conductive portion, the second conductive portion includes the ninth active portion, and the orthographic projection of the ninth active portion on the substrate is located on the orthographic projection of the second extension portion on the substrate; and the size of the orthographic projection of the ninth active portion on the substrate in the first pixel driving circuit on the substrate in the first direction is smaller than the size of the orthographic projection of the ninth active portion on the substrate in the second pixel driving circuit on the substrate in the first direction.
  • the first light emitting unit is a blue light emitting unit
  • the second light emitting unit is a red light emitting unit or a green light emitting unit.
  • the plurality of pixel driving circuits are arrayed along a first direction and a second direction
  • the display panel further includes: a base substrate, a fourth conductive layer, and a fifth conductive layer
  • the fourth conductive layer is located on one side of the base substrate
  • the fourth conductive layer includes a plurality of first power line segments, the first power line segments are arranged corresponding to the pixel driving circuits, the orthographic projections of the plurality of first power line segments on the base substrate are arrayed along the first direction and the second direction and extend along the second direction, the first direction and the second direction intersect, and the first power line segments are connected to a stable voltage source
  • the fifth conductive layer is located on a side of the fourth conductive layer away from the base substrate, the fifth conductive layer includes the data line, and the orthographic projection of the data line on the base substrate extends along the second direction.
  • the pixel driving circuit further includes: an eighth transistor, a first electrode of the eighth transistor is connected to the gate of the driving transistor, and the display panel further includes: a second active layer and a third conductive layer, the second active layer is located between the fourth conductive layer and the substrate, the second active layer includes an eighth active portion, and the eighth active portion is used to form a channel region of the eighth transistor; the third conductive layer is located between the second active layer and the fourth conductive layer, the third conductive layer includes a second gate line, the orthographic projection of the second gate line on the substrate extends along the first direction and covers the orthographic projection of the eighth active portion on the substrate, and a partial structure of the second gate line is used to form a top gate of the eighth transistor; wherein the orthographic projection of the first power line segment on the substrate is located between two adjacent orthographic projections of the second gate line on the substrate.
  • the display panel also includes a source driving circuit, a signal output terminal of the source driving circuit is connected to the plurality of data lines, and a signal output terminal of the source driving circuit provides data signals to the plurality of data lines in a time-sharing manner within a row scanning cycle;
  • the first power line segment includes a third extension portion, wherein an orthographic projection of the third extension portion on the substrate and an orthographic projection of the data line on the substrate at least partially overlap.
  • the area of the orthographic projection of the data line on the base substrate is S3
  • the overlapping area of the orthographic projection of the data line on the base substrate and the orthographic projection of the third extension portion on the base substrate is S4, and S4/S3 is greater than or equal to 20% and less than or equal to 70%.
  • the first electrode of the driving transistor is connected to a power line;
  • the fourth conductive layer also includes a first connecting portion, and the first connecting portion is connected between two adjacent first power line segments in the first direction;
  • the fifth conductive layer also includes the power line, and the orthographic projection of the power line on the substrate extends along the second direction, and the power line is used to provide the stable voltage source.
  • the first power line segment also includes a fourth extension portion;
  • the display panel also includes a second conductive portion, and the second conductive portion is connected to the gate of the driving transistor;
  • the orthographic projection of the fourth extension portion on the base substrate extends along the second direction and is located between the orthographic projection of the data line on the base substrate and the orthographic projection of the second conductive portion on the base substrate.
  • the display panel also includes a second conductive portion, which is connected to the gate of the driving transistor;
  • the first power line segment also includes a third extension portion, which is connected to the fourth extension portion, and the size of the orthographic projection of the third extension portion on the substrate is larger than the size of the orthographic projection of the fourth extension portion on the substrate in the first direction;
  • the orthographic projection of a partial structure of the third extension portion on the substrate is located between the orthographic projection of the second conductive portion on the substrate and the orthographic projection of the data line on the substrate.
  • the first electrode of the driving transistor is connected to the power line
  • the pixel driving circuit further includes: an eighth transistor
  • the first electrode of the eighth transistor is connected to the gate of the driving transistor
  • the display panel further includes: a base substrate, a second active layer, and a fifth conductive layer
  • the second active layer is located on one side of the base substrate, the second active layer includes an active portion, and a partial structure of the active portion is used to form a channel region of the eighth transistor
  • the fifth conductive layer is located on a side of the second active layer away from the base substrate, the fifth conductive layer includes the power line, and the orthographic projection of the power line on the base substrate covers the orthographic projection of the active portion on the base substrate.
  • the first electrode of the driving transistor is connected to a power line
  • the display panel further includes: a base substrate, a second conductive portion, and a fifth conductive layer, wherein the second conductive portion is connected to the gate of the driving transistor; the fifth conductive layer is located on one side of the base substrate, and the fifth conductive layer includes the power line, and the orthographic projection of the power line on the base substrate covers the orthographic projection of the second conductive portion on the base substrate.
  • the first electrode of the driving transistor is connected to a power line
  • the display panel further includes: a base substrate, a fifth conductive layer, an electrode layer, and a pixel definition layer, wherein the fifth conductive layer is located on one side of the base substrate, and the fifth conductive layer includes the power line and the data line, and the orthographic projection of the power line on the base substrate and the orthographic projection of the data line on the base substrate extend along the second direction;
  • the electrode layer includes a plurality of electrode portions, and the orthographic projections of the electrode portions on the base substrate and the orthographic projections of the power line on the base substrate and the data line on the base substrate all overlap;
  • the pixel definition layer is located on a side of the electrode layer away from the base substrate, and a pixel opening for forming a light-emitting unit is formed on the pixel definition layer, and the orthographic projection of the pixel opening on the base substrate coincides with the orthographic projection of the electrode portion on the base substrate.
  • the electrode portion consists of a first part and a second part, the orthographic projection of the first part on the substrate and the orthographic projection of the second part on the substrate are distributed along a first direction, and the maximum size of the orthographic projection of the first part on the substrate in the first direction is equal to the maximum size of the orthographic projection of the second part on the substrate in the first direction, and the first direction and the second direction intersect; the orthographic projection of the first part on the substrate and the orthographic projection of the power line on the substrate at least partially overlap, and the orthographic projection of the second part on the substrate and the orthographic projection of the data line on the substrate at least partially overlap.
  • the minimum size of the overlapping area of the orthographic projection of the electrode portion on the base substrate and the orthographic projection of the power line on the base substrate in the first direction is L1
  • the minimum size of the orthographic projection of the data line on the base substrate in the first direction is L2
  • L1 is greater than L2.
  • the display panel also includes a plurality of light-emitting units, including a first light-emitting unit and a second light-emitting unit; the first pixel driving circuit is used to drive the first light-emitting unit, and the second pixel driving circuit is used to drive the second light-emitting unit; the voltage required for the first light-emitting unit to emit light is greater than the voltage required for the second light-emitting unit to emit light, and the width-to-length ratio of the channel region of the driving transistor in the first pixel driving circuit is greater than the width-to-length ratio of the channel region of the driving transistor in the second pixel driving circuit.
  • the channel region length of the driving transistor in the first pixel driving circuit is smaller than the channel region length of the driving transistor in the second pixel driving circuit.
  • the display panel also includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light.
  • the pixel driving circuit also includes: an eighth transistor, a first transistor, a second transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a capacitor.
  • the first electrode of the eighth transistor is connected to the gate of the driving transistor, and the gate is connected to the second gate line; the first electrode of the first transistor is connected to the first initial signal line, the second electrode is connected to the second electrode of the eighth transistor, and the gate is connected to the first reset signal line; the first electrode of the second transistor is connected to the second electrode of the eighth transistor, the second electrode is connected to the second electrode of the driving transistor, and the gate is connected to the first gate line; the first electrode of the fifth transistor is connected to the power line, the second electrode is connected to the first electrode of the driving transistor, and the gate is connected to the enable signal line; the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode is connected to the first electrode of the light-emitting unit, and the gate is connected to the enable signal line; the first electrode of the seventh transistor is connected to the second initial signal line, the second electrode is connected to the first electrode of the light-emitting unit, and the gate is connected to the second reset signal line; the capacitor is connected between the gate of the
  • the display panel further comprises: a base substrate, a first active layer, a first conductive layer, a second active layer, and a third conductive layer.
  • the first active layer is located on one side of the base substrate, and the first active layer comprises a first active portion, a second active portion, a third active portion, a fourth active portion, a fifth active portion, a sixth active portion, and a seventh active portion.
  • the first active portion is used to form a channel region of the first transistor
  • the second active portion is used to form a channel region of the second transistor
  • the third active portion is used to form a channel region of the driving transistor
  • the fourth active portion is used to form a channel region of the fourth transistor
  • the fifth active portion is used to form a channel region of the driving transistor.
  • the first conductive layer includes the first gate line, the first reset signal line, the second reset signal line, the enable signal line, and the first conductive portion, and the positive projections of the first gate line, the first reset signal line, the second reset signal line, and the enable signal line on the substrate all extend along the first direction; wherein, a portion of the first gate line is used to form the gates of the second transistor and the fourth transistor, respectively, a portion of the enable signal line is used to form the gates of the fifth transistor and the sixth transistor, a portion of the first reset signal line is used to form the gate of the first transistor, a portion of the second reset signal line is used to form the gate of the seventh transistor, and the first conductive portion is used to form the gate of the driving transistor; the second active layer is located at the first conductive layer.
  • the second active layer is located on a side away from the substrate, the second active layer includes an eighth active portion, and the eighth active portion is used to form a channel region of the eighth transistor;
  • the third conductive layer is located on a side of the second active layer away from the substrate, the third conductive layer includes the second gate line, and a partial structure of the second gate line is used to form a top gate of the eighth transistor; wherein the orthographic projection of the first conductive portion on the substrate is located between the orthographic projection of the first gate line on the substrate and the orthographic projection of the enable signal line on the substrate, the orthographic projection of the first reset signal line on the substrate is located on a side of the orthographic projection of the first gate line on the substrate away from the orthographic projection of the first conductive portion on the substrate, and the orthographic projection of the second gate line on the substrate is located between the orthographic projection of the first reset signal line on the substrate and the orthographic projection of the first gate line on the substrate.
  • the first direction is a row direction
  • the display panel includes multiple rows of pixel driving circuits; the orthographic projection of the second initial signal line in the pixel driving circuit of the previous adjacent row on the substrate substrate is located between the orthographic projection of the first reset signal line in the pixel driving circuit of the current row on the substrate substrate and the orthographic projection of the second gate line in the pixel driving circuit of the current row on the substrate substrate; the orthographic projection of the first initial signal line in the pixel driving circuit of the next adjacent row on the substrate substrate is located between the orthographic projection of the second reset signal line in the pixel driving circuit of the current row on the substrate substrate and the orthographic projection of the enable signal line in the pixel driving circuit of the current row on the substrate substrate; the second reset signal line in the pixel driving circuit of the current row is multiplexed as the first reset signal line in the pixel driving circuit of the next adjacent row.
  • the first transistor, the second transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are P-type transistors, and the eighth transistor is an N-type transistor.
  • a display device comprising the above-mentioned display panel.
  • FIG1 is a schematic diagram of a circuit structure of a pixel driving circuit in an exemplary embodiment of a display panel disclosed herein;
  • FIG2 is a timing diagram of signals at each node in the pixel driving circuit shown in FIG1 ;
  • FIG3 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;
  • FIG4 is a structural diagram of the shielding layer in FIG3 ;
  • FIG5 is a structural diagram of the first active layer in FIG3;
  • FIG6 is a structural diagram of the first conductive layer in FIG3 ;
  • FIG7 is a structural diagram of the second conductive layer in FIG3 ;
  • FIG8 is a structural diagram of the second active layer in FIG3;
  • FIG9 is a structural diagram of the third conductive layer in FIG3 ;
  • FIG10 is a structural diagram of the fourth conductive layer in FIG3 ;
  • FIG11 is a structural diagram of the fifth conductive layer in FIG3 ;
  • FIG12 is a structural diagram of the electrode layer in FIG3 ;
  • FIG13 is a structural layout diagram of the shielding layer and the first active layer in FIG3 ;
  • FIG14 is a structural layout diagram of the shielding layer, the first active layer, and the first conductive layer in FIG3 ;
  • FIG15 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, and the second conductive layer in FIG3;
  • FIG16 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG3 ;
  • FIG17 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG3;
  • FIG18 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG3 ;
  • FIG19 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in FIG3 ;
  • FIG20 is a structural layout diagram of a fifth conductive layer and an electrode layer in an exemplary embodiment of a display panel of the present disclosure
  • FIG21 is a structural layout diagram of the fifth conductive layer in FIG20.
  • FIG22 is a structural layout diagram of the electrode layer in FIG20;
  • FIG. 23 is a partial cross-sectional view of the display panel shown in FIG. 3 taken along the dotted line AA.
  • the display panel includes a plurality of sub-pixel units, each of which may include a pixel driving circuit and a light-emitting unit.
  • the pixel driving circuit provides a driving current to the light-emitting unit according to a data signal to drive the light-emitting unit to emit light. Since light-emitting units of different colors have light-emitting material layers of different materials, the data signal voltages required for sub-pixel units of different colors in the black state are different, that is, under the same driving current, light-emitting units of different colors have different brightness. For example, the data signal voltage required for the blue sub-pixel unit in the black state is less than the data signal voltage required for the red and green sub-pixel units in the black state.
  • the greater the data signal voltage the lower the brightness of the light-emitting unit.
  • the brightness of the blue light-emitting unit is less than the brightness of the red light-emitting unit and the green light-emitting unit.
  • the display panel displays abnormally, especially at low grayscale.
  • the data signal voltage required for the blue sub-pixel unit in the black state is 6 V
  • the data signal voltage required for the red sub-pixel unit and the green sub-pixel in the black state is 6.5 V
  • the data signal voltage when the display panel displays a black screen is 6.5 V.
  • the data signal voltage is less than 6.5 V
  • the brightness of the blue light-emitting unit is less than the brightness of the red light-emitting unit and the green light-emitting unit.
  • this exemplary embodiment provides a display panel, as shown in Figure 1, which is a circuit structure diagram of a pixel driving circuit in an exemplary embodiment of the display panel disclosed in the present invention.
  • the pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C.
  • the first electrode of the eighth transistor T8 is connected to the gate of the driving transistor T3, and the gate is connected to the second gate driving signal terminal G2;
  • the first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, the second electrode is connected to the second electrode of the eighth transistor T8, and the gate is connected to the first reset signal terminal Re1;
  • the first electrode of the second transistor T2 is connected to the second electrode of the eighth transistor T8, the second electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the first gate driving signal terminal G1;
  • the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the first gate driving signal terminal G1;
  • the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM,
  • the first electrode of the sixth transistor T6 is connected to the
  • the pixel driving circuit can be used to drive the light emitting unit L to emit light, wherein the first electrode of the light emitting unit L is connected to the second electrode of the sixth transistor T6, and the second electrode of the light emitting unit L is connected to the second power supply terminal VSS.
  • the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can all be P-type transistors
  • the eighth transistor T8 can be an N-type transistor.
  • FIG2 it is a timing diagram of the signals on each node in the pixel driving circuit shown in FIG1.
  • EM represents the timing diagram of the signal on the enable signal terminal
  • G1 represents the timing diagram of the signal on the first gate driving signal terminal
  • G2 represents the timing diagram of the signal on the second gate driving signal terminal
  • Re1 represents the timing diagram of the signal on the first reset signal terminal
  • Re2 represents the timing diagram of the signal on the second reset signal terminal.
  • the driving method of the pixel driving circuit in the present disclosure may include a first reset stage t1, a second reset stage t2, a data writing stage t3, and a light emitting stage t4.
  • the first reset stage t1 the first reset signal terminal Re1 outputs a low level
  • the second gate driving signal terminal G2 outputs a high level
  • the first transistor T1 and the eighth transistor T8 are turned on
  • the first initial signal terminal Vinit1 inputs a first initial signal to the gate of the driving transistor T3
  • the second reset signal terminal Re2 outputs a low level signal
  • the seventh transistor T7 is turned on
  • the second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the light emitting unit
  • the data writing stage t3 the first gate driving signal terminal G1 outputs a low level signal
  • the second gate driving signal terminal G2 outputs a high level signal
  • the eighth transistor T8, the fourth transistor T4, and the second transistor T2 are turned on
  • the data signal terminal Da the data signal
  • the enable signal terminal EM outputs a low-level signal
  • the fifth transistor T5 and the sixth transistor T6 are turned on
  • the driving transistor T3 drives the light-emitting unit L to emit light under the action of the voltage Vdata+Vth at its gate.
  • the driving transistor output current formula I ( ⁇ WCox/2L)(Vgs-Vth) 2 , where ⁇ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor.
  • the pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.
  • the display panel may include a plurality of the above-mentioned pixel driving circuits, wherein the plurality of pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit; the display panel also includes a plurality of light-emitting units, wherein the plurality of light-emitting units include a first light-emitting unit and a second light-emitting unit; the first pixel driving circuit is used to drive the first light-emitting unit, and the second pixel driving circuit is used to drive the second light-emitting unit; the capacitance formed by the equipotential structure of the gate of the driving transistor in the first pixel driving circuit and the first gate line is C1, and the capacitance formed by the equipotential structure of the gate of the driving transistor in the second pixel driving circuit and the first gate line is C2, and the first gate line can be used to provide the first gate driving signal terminal G1 in Figure 1. Under the same driving current, the brightness of the first light-emitting unit is less
  • the first gate line changes from a low level to a high level at the end of the data writing phase t3, and the first gate line can pull up the voltage of the gate of the driving transistor through the coupling effect of the capacitance between the first gate line and the gate of the driving transistor.
  • the capacitance formed by the equipotential structure of the gate of the driving transistor in the first pixel driving circuit and the first gate line is smaller than the capacitance formed by the equipotential structure of the gate of the driving transistor in the second pixel driving circuit and the first gate line, so that the pull-up effect of the first gate line on the gate of the driving transistor in the first pixel driving circuit is smaller than the pull-up effect of the first gate line on the gate of the driving transistor in the second pixel driving circuit.
  • the actual driving voltage of the gate of the driving transistor in the first pixel driving circuit is smaller than the actual driving voltage of the gate of the driving transistor in the second pixel driving circuit, and the difference in the actual driving voltage can just compensate for the difference in the data signal voltage required by the first light-emitting unit and the second light-emitting unit in the black state, so that this exemplary embodiment can make the brightness of the first light-emitting unit and the second light-emitting unit the same under the same data signal.
  • the pixel driving circuit may also be other structures, as long as the pixel driving circuit includes the driving transistor T3 and the fourth transistor T4, the display abnormality caused by the difference in data signal voltage required by different light-emitting units in the black state can be compensated by the differentiated setting of the capacitance between the gate equipotential structure of the driving transistor and the first gate line in different pixel driving circuits.
  • the differentiated setting of the capacitance between the gate equipotential structure of the driving transistor and the first gate line in different pixel driving circuits can also be used to solve the problem of inconsistent brightness of different light-emitting units under the same data signal voltage due to other reasons.
  • this setting can also solve the problem of inconsistent brightness of different light-emitting units under the same data signal voltage due to differences in output characteristics of the driving transistor in the pixel driving circuit.
  • the display panel may include a base substrate, a shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and an electrode layer stacked in sequence, wherein an insulating layer may be disposed between the adjacent layers.
  • Figure 3 is a structural layout diagram of an exemplary embodiment of the display panel of the present disclosure
  • Figure 4 is a structural layout diagram of the shielding layer in Figure 3
  • Figure 5 is a structural layout diagram of the first active layer in Figure 3
  • Figure 6 is a structural layout diagram of the first conductive layer in Figure 3
  • Figure 7 is a structural layout diagram of the second active layer in Figure 3.
  • FIG. 8 is a structural layout of the second active layer in FIG. 3
  • FIG. 9 is a structural layout of the third conductive layer in FIG. 3
  • FIG. 10 is a structural layout of the fourth conductive layer in FIG. 3
  • FIG. 11 is a structural layout of the fifth conductive layer in FIG. 3
  • FIG. 12 is a structural layout of the electrode layer in FIG. 3
  • FIG. 13 is a structural layout of the shielding layer and the first active layer in FIG. 3
  • FIG. 14 is a structural layout of the shielding layer, the first active layer, and the first conductive layer in FIG. 3
  • FIG. 15 is a structural layout of the shielding layer, the first active layer, the first conductive layer, and the second conductive layer in FIG. 3
  • FIG. 15 is a structural layout of the shielding layer, the first active layer, the first conductive layer, and the second conductive layer in FIG. 3
  • FIG. 15 is a structural layout of the shielding layer, the first active layer, the first conductive layer, and the second
  • FIG 16 is a structural layout of the shielding layer in FIG. 3
  • FIG17 is a structural layout of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer in FIG3
  • FIG18 is a structural layout of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG3
  • FIG19 is a structural layout of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in FIG3
  • the display panel may include a plurality of pixel drive circuits as shown in FIG1 . As shown in FIG19 , the plurality of pixel drive circuits may include the first pixel drive circuit P1 and the second pixel drive circuit P2 described above.
  • the shielding layer may include a plurality of shielding portions 71, connecting portions 73, and connecting portions 72, wherein the orthographic projection of the connecting portion 73 on the base substrate extends along the second direction Y and is connected between the shielding portions 71 adjacent to each other in the second direction Y; the orthographic projection of the connecting portion 72 on the base substrate extends along the first direction X and is connected between the shielding portions 71 adjacent to each other in the first direction X.
  • the first direction X and the second direction Y may be connected to each other, for example, the first direction X may be a row direction, and the second direction Y may be a column direction.
  • the first active layer may include a first active portion 61, a second active portion 62, a third active portion 63, a fourth active portion 64, a fifth active portion 65, a sixth active portion 66, and a seventh active portion 67.
  • the first active portion 61 is used to form a channel region of the first transistor T1
  • the second active portion 62 is used to form a channel region of the second transistor T2
  • the third active portion 63 is used to form a channel region of the driving transistor T3
  • the fourth active portion 64 is used to form a channel region of the fourth transistor T4
  • the fifth active portion 65 is used to form a channel region of the fifth transistor T5
  • the sixth active portion 66 is used to form a channel region of the sixth transistor T6, and the seventh active portion 67 is used to form a channel region of the seventh transistor T7.
  • the first active layer may further include an eleventh active portion 611, a twelfth active portion 612, a thirteenth active portion 613, a fourteenth active portion 614, a fifteenth active portion 615, and a sixteenth active portion 616.
  • the fifteenth active portion 615 is connected to one end of the fourth active portion 64 away from the third active portion 63; the sixteenth active portion 616 is connected between the first active portion 61 and the second active portion 62; the eleventh active portion 611 is connected to one end of the first active portion 61 away from the second active portion 62; the twelfth active portion 612 is connected to one end of the fifth active portion 65 away from the third active portion 63; the thirteenth active portion 613 is connected between the sixth active portion 66 and the seventh active portion 67; and the fourteenth active portion 614 is connected to one end of the seventh active portion 67 away from the sixth active portion 66.
  • the orthographic projection of the shielding portion 71 on the substrate can cover the orthographic projection of the third active portion 63 on the substrate, and the shielding portion 71 can shield the third active portion 63 from light, so as to reduce the influence of light on the driving characteristics of the driving transistor T3.
  • the shielding layer may be a conductive material, and the shielding layer may also be connected to a stable voltage source to shield the driving transistor T3 from noise.
  • the shielding layer may be connected to the first power supply terminal VDD, the first initial signal terminal Vinit1, the second initial signal terminal Vinit2, the second power supply terminal VSS, etc.
  • the first active layer may be formed of polysilicon material, and accordingly, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type low-temperature polysilicon thin film transistors.
  • the first conductive layer may include a first reset signal line Re1, a first gate line G1, an enable signal line EM, a second reset signal line Re2, and a first conductive portion 11.
  • the first reset signal line Re1 may be used to provide the first reset signal terminal in FIG. 1.
  • the orthographic projection of the first reset signal line Re1 on the substrate may cover the orthographic projection of the first active portion 61 on the substrate, and a partial structure of the first reset signal line Re1 may be used to form the gate of the first transistor T1.
  • the first gate line G1 may be used to provide the first gate drive signal terminal in FIG. 1.
  • the orthographic projection of the first gate line G1 on the substrate may cover the orthographic projection of the second active portion 62 on the substrate, and the orthographic projection of the fourth active portion 64 on the substrate.
  • a partial structure of the first gate line G1 may be used to form the gate of the second transistor T2, and another partial structure of the first gate line G1 may be used to form the gate of the fourth transistor T4.
  • the enable signal line EM is used to provide the enable signal terminal in FIG. 1 .
  • the orthographic projection of the enable signal line EM on the substrate can extend along the first direction X and cover the orthographic projection of the fifth active portion 65 on the substrate and the orthographic projection of the sixth active portion 66 on the substrate.
  • Part of the structure of the enable signal line EM can be used to form the gate of the fifth transistor T5, and the other part of the structure of the enable signal line EM can be used to form the gate of the sixth transistor T6.
  • the second reset signal line Re2 is used to provide the second reset signal terminal in FIG. 1 .
  • the orthographic projection of the second reset signal line Re2 on the substrate can cover the orthographic projection of the seventh active portion 67 on the substrate.
  • Part of the structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7.
  • the orthographic projection of the first conductive portion 11 on the substrate can cover the orthographic projection of the third active portion 63 on the substrate.
  • the first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C.
  • the orthographic projection of the first reset signal line Re1 on the substrate, the orthographic projection of the first gate line G1 on the substrate, the orthographic projection of the first conductive portion 11 on the substrate, the orthographic projection of the enable signal line EM on the substrate, and the orthographic projection of the second reset signal line Re2 on the substrate can be distributed in sequence along the second direction Y.
  • the first reset signal line Re1 in the pixel driving circuit of this row can be reused as the second reset signal line Re2 in the pixel driving circuit of the adjacent previous row. This setting can improve the integration of the pixel driving circuit in the second direction Y.
  • the display panel can use the first conductive layer as a mask to perform conductor processing on the first active layer, that is, the area covered by the first conductive layer in the first active layer can form a channel region of the transistor, and the area not covered by the first conductive layer in the first active layer forms a conductor structure.
  • the second conductive layer may include a third gate line 2G2, a first initial signal line Vinit1, and a third conductive portion 23.
  • the orthographic projection of the first initial signal line Vinit1 on the substrate substrate and the orthographic projection of the third gate line 2G2 on the substrate substrate may both extend along the first direction X.
  • the first initial signal line Vinit1 is used to provide the first initial signal terminal in Figure 1
  • the third gate line 2G2 is used to provide the second gate drive signal terminal in Figure 1.
  • the orthographic projection of the third conductive portion 23 on the substrate substrate may overlap with the orthographic projection of the first conductive portion 11 on the substrate substrate, and the third conductive portion 23 may be used to form the second electrode of the capacitor C.
  • the orthographic projection of the first initial signal line Vinit1 in the adjacent next row of pixel driving circuits on the substrate substrate may be located between the orthographic projection of the enable signal line EM in the pixel driving circuit of this row on the substrate substrate and the orthographic projection of the second reset signal line Re2 in the pixel driving circuit of this row on the substrate substrate.
  • This arrangement can further improve the integration of the pixel driving circuit in the second direction Y.
  • the first initial signal line Vinit1 may also be located in other conductive layers, for example, the first initial signal line Vinit1 may also be located in the shielding layer, the third conductive layer, the fourth conductive layer, etc.
  • the second active layer may include a plurality of active portions 8, the active portion 8 includes an eighth active portion 88, a ninth active portion 89, and a tenth active portion 810, the eighth active portion 88 is connected between the ninth active portion 89 and the tenth active portion 810, and the eighth active portion 88 is used to form a channel region of the eighth transistor.
  • the orthographic projection of the third gate line 2G2 on the substrate can cover the orthographic projection of the eighth active portion 88 on the substrate, and a partial structure of the third gate line 2G2 can be used to form the bottom gate of the eighth transistor T8.
  • the second active layer can be formed of indium gallium zinc oxide, and accordingly, the eighth transistor T8 can be an N-type metal oxide thin film transistor.
  • the third conductive layer may include: a second gate line 3G2, and the orthographic projection of the second gate line 3G2 on the substrate can extend along the first direction X.
  • the second gate line 3G2 is used to provide the second gate drive signal terminal in Figure 1, and the orthographic projection of the second gate line 3G2 on the substrate can cover the orthographic projection of the eighth active part 88 on the substrate, and the partial structure of the second gate line 3G2 can be used to form the top gate of the eighth transistor T8.
  • the second gate line 3G2 and the third gate line 2G2 in the same row of pixel driving circuits can be connected through vias, and the vias connected between the second gate line 3G2 and the third gate line 2G2 can be located in the edge routing area outside the display area of the display panel.
  • the display panel can use the third conductive layer as a mask to perform conductor processing on the second active layer, that is, the area covered by the third conductive layer in the second active layer can form the channel area of the transistor, and the area not covered by the third conductive layer in the second active layer forms a conductor structure.
  • the orthographic projection of the second active portion 62 on the substrate substrate is located on the side of the orthographic projection of the eighth active portion 88 on the substrate substrate away from the orthographic projection of the connecting portion 73 on the substrate substrate.
  • This arrangement can make the second active portion 62 away from the connecting portion 73, thereby avoiding the change in the crystallization state of the first active layer and the risk of tunneling caused by the edge morphology of the connecting portion 73.
  • the minimum distance between the orthographic projection of the first active portion 61 on the substrate and the orthographic projection of the shielding layer on the substrate is L3, and the size of the orthographic projection of the first active portion 61 on the substrate in the first direction X is L4, and L3 may be greater than or equal to L4.
  • L3 may be 1 times, 2 times, 3 times, 4 times, etc. of L4.
  • the minimum distance between the orthographic projection of the second active portion 62 on the substrate and the orthographic projection of the shielding layer on the substrate is L7, and the size of the orthographic projection of the second active portion 62 on the substrate in the first direction X is L8, and L7 may be greater than or equal to L8.
  • L7 may be 0.5 times, 1 times, 2 times, 3 times, 4 times, etc. of L8.
  • the minimum distance between the orthographic projection of the fourth active portion 64 on the substrate and the orthographic projection of the shielding layer on the substrate is L9, and the size of the orthographic projection of the fourth active portion 64 on the substrate in the first direction X is L10, and L9 may be greater than or equal to L10.
  • L9 may be 1 times, 2 times, 3 times, 4 times, etc. of L10.
  • the minimum distance between the orthographic projection of the fifth active portion 65 on the substrate substrate and the orthographic projection of the shielding layer on the substrate substrate is L11, and the size of the orthographic projection of the fifth active portion 65 on the substrate substrate in the first direction X is L12, and L11 may be greater than or equal to L12.
  • L11 may be 1 times, 2 times, 3 times, 4 times, etc. of L12.
  • the minimum distance between the orthographic projection of the sixth active portion 66 on the substrate substrate and the orthographic projection of the shielding layer on the substrate substrate is L13, and the size of the orthographic projection of the sixth active portion 66 on the substrate substrate in the first direction X is L14, and L13 may be greater than or equal to L14.
  • L13 may be 1 times, 2 times, 3 times, 4 times, etc. of L14.
  • the minimum distance between the orthographic projection of the seventh active portion 67 on the substrate and the orthographic projection of the shielding layer on the substrate is L15, and the size of the orthographic projection of the seventh active portion 67 on the substrate in the first direction X is L16, and L15 may be greater than or equal to L16.
  • L15 may be 1 times, 2 times, 3 times, 4 times, etc. of L16.
  • This setting sets the shielding layer at a position away from the channel region in the first active layer, thereby avoiding the change in the crystallization state of the first active layer and the risk of tunneling caused by the edge morphology of the shielding layer. It should be understood that in other exemplary embodiments, the distance between the orthographic projection of the shielding layer on the substrate and the orthographic projection of the channel region in the first active layer on the substrate may not be limited.
  • the fourth conductive layer may include: a second initial signal line Vinit2, a first power line segment 4VDD, a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, and a fifth bridge portion 45.
  • the second initial signal line Vinit2 may be used to provide the second initial signal terminal in FIG.
  • the second initial signal line Vinit2 may be connected to the fourteenth active portion 614 through a via H to connect the first electrode and the second initial signal terminal of the seventh transistor T7, wherein the black square indicates the position of the via.
  • the first power line segment 4VDD is arranged in a one-to-one correspondence with the pixel driving circuit, and the positive projections of the plurality of first power line segments 4VDD on the substrate are distributed in an array along the first direction X and the second direction Y and extend along the second direction Y.
  • the first power line segment 4VDD may be connected to the twelfth active portion 612 and the third conductive portion 23 through vias, respectively, to connect the first electrode of the fifth transistor T5 and the second electrode of the capacitor C.
  • the first bridge portion 41 can be connected to the first conductive portion 11 and the ninth active portion 89 through vias, respectively, to connect the gate of the driving transistor T3 and the first pole of the eighth transistor T8.
  • an opening 231 is formed on the third conductive portion 23, and the orthographic projection of the via connected between the first conductive portion 11 and the first bridge portion 41 on the substrate substrate is located within the orthographic projection of the opening 231 on the substrate substrate, so that the via connected between the first conductive portion 11 and the first bridge portion 41 is insulated from the third conductive portion 23.
  • the second bridge portion 42 can be connected to the eleventh active portion 611 and the first initial signal line Vinit1 through vias, respectively, to connect the first pole of the first transistor T1 and the first initial signal end.
  • the third bridge portion 43 can be connected to the thirteenth active portion 613 through vias, to connect the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7.
  • the fourth bridge portion 44 can be connected to the tenth active portion 810 and the sixteenth active portion 616 through vias, respectively, to connect the second pole of the eighth transistor T8 and the second pole of the first transistor and the first pole of the second transistor.
  • the fifth bridge portion 45 is connected to the fifteenth active portion 615 through a via hole to connect the first electrode of the fourth transistor.
  • the positive projection of the second initial signal line Vinit2 in the adjacent previous row of pixel driving circuits on the substrate substrate is located between the positive projection of the first reset signal line Re1 in the pixel driving circuit of this row on the substrate substrate and the positive projection of the second gate line 3G2 in the pixel driving circuit of this row on the substrate substrate.
  • This setting can improve the integration of the pixel driving circuit in the second direction Y.
  • the second initial signal line Vinit2 can also be located in other conductive layers, for example, the second initial signal line Vinit2 can be located in the shielding layer, the second conductive layer, the third conductive layer, etc.
  • the first gate line G1 is arranged between the first conductive portion 11 and the second gate line 3G2, so that the coupling effect between the first gate line G1 and the first conductive portion 11 can be increased.
  • the voltage of the first gate line G1 increases, and the first gate line G1 can pull up the voltage of the gate of the driving transistor T3.
  • This setting can reduce the voltage of the data signal under the black screen of the display panel, thereby reducing the power consumption of the display panel.
  • the positive projection of the ninth active portion 89 on the substrate substrate and the positive projection of the first gate line G1 on the substrate substrate overlap at least partially.
  • the first gate line G1 can be able to pull up the voltage of the gate of the driving transistor T3 through the ninth active portion 89. This setting can further reduce the voltage of the data signal under the black screen of the display panel, thereby reducing the power consumption of the display panel.
  • the first gate line G1 may include: a plurality of first extensions G11 and a plurality of second extensions G12, wherein the orthogonal projections of the plurality of first extensions G11 on the substrate extend along the first direction X and are spaced apart along the first direction X; the second extensions G12 are connected between the first extensions adjacent to each other in the first direction X; wherein the size of the orthogonal projection of the first extension G11 on the substrate in the second direction Y is smaller than the size of the orthogonal projection of the second extension G12 on the substrate in the second direction Y.
  • the ninth active portion 89 is an equipotential structure of the gate of the driving transistor, and this exemplary embodiment can achieve differentiated settings of C1 and C2 by adjusting the overlapping area of the ninth active portion 89 and the second extension G12 on the substrate.
  • the overlapping area of the orthogonal projection of the ninth active portion 89 on the substrate in the first pixel driving circuit P1 and the orthogonal projection of the first gate line G1 on the substrate can be smaller than the overlapping area of the orthogonal projection of the ninth active portion 89 on the substrate in the second pixel driving circuit P2 and the orthogonal projection of the first gate line G1 on the substrate.
  • the orthographic projection of the ninth active portion 89 on the substrate substrate is located on the orthographic projection of the second extension portion G12 on the substrate substrate; and the size of the orthographic projection of the ninth active portion 89 on the substrate substrate in the first pixel driving circuit P1 in the first direction X is smaller than the size of the orthographic projection of the ninth active portion 89 on the substrate substrate in the second pixel driving circuit P2 in the first direction X.
  • the equipotential structure of the gate of the driving transistor T3 may also include other structures, for example, the equipotential structure of the gate of the driving transistor T3 may also include a first bridge portion 41.
  • the equipotential structure of the gate of the driving transistor T3 connected to the first conductive portion may form a second conductive portion.
  • This exemplary embodiment may achieve differentiated settings of C1 and C2 by adjusting the overlapping area of the second conductive portion and the second extension portion G12 on the substrate.
  • the overlapping area of the orthographic projection of the second conductive portion on the substrate and the orthographic projection of the first gate line G1 on the substrate in the first pixel driving circuit P1 is S1
  • the overlapping area of the orthographic projection of the second conductive portion on the substrate and the orthographic projection of the first gate line on the substrate in the second pixel driving circuit is S2
  • S1 may be smaller than S2.
  • the differentiated settings of C1 and C2 can be realized by other methods.
  • the capacitance between the second conductive part and the first gate line can be adjusted by adjusting the distance between the second conductive part and the first gate line in the orthographic overlapped portion on the substrate.
  • the fifth conductive layer may include a data line Da, a power line 5VDD, and a sixth bridge portion 56.
  • the data line Da may be used to provide the data signal terminal in Figure 1
  • the power line 5VDD may be used to provide the first power terminal in Figure 1.
  • the orthographic projection of the data line Da on the substrate substrate and the orthographic projection of the power line 5VDD on the substrate substrate may extend along the second direction Y.
  • the data line Da may be connected to the fifth bridge portion 45 through a via hole to connect the first electrode and the data signal terminal of the fourth transistor T4.
  • a power line 5VDD may be correspondingly provided for each column of pixel driving circuits, and the power line 5VDD may be connected to the first power line segment 4VDD through a via hole to connect the first power terminal and the second electrode of the capacitor C and the first electrode of the fifth transistor T5.
  • the sixth bridge portion 56 may be connected to the third bridge portion 43 through a via hole to connect the second electrode of the sixth transistor T6.
  • the orthographic projection of the power line 5VDD on the substrate can cover the orthographic projection of the active part 8 on the substrate, and the power line 5VDD can reduce the influence of light on the characteristics of the eighth transistor T8.
  • the orthographic projection of the power line 5VDD on the substrate can also cover the orthographic projection of the ninth active part 89 and the first bridge part 41 on the substrate, and the power line 5VDD can be used to shield the noise interference of other signals on the ninth active part 89 and the first bridge part 41, thereby improving the stability of the gate voltage of the driving transistor T3.
  • the orthographic projection of the power line 5VDD on the substrate can cover the orthographic projection of the above-mentioned second conductive part on the substrate.
  • the display panel may also include a source driving circuit, and a signal output terminal of the source driving circuit may be connected to a plurality of the data lines, and a signal output terminal of the source driving circuit may provide data signals to the plurality of data lines in a time-sharing manner within a row scanning cycle, and the plurality of data lines need to simultaneously provide data signals to the scanning pixel rows during the data writing phase. Therefore, the data line needs to have a certain data storage capacity.
  • the first power line segment 4VDD may include a third extension portion 4VDD3, wherein the orthographic projection of the third extension portion 4VDD3 on the substrate substrate and the orthographic projection of the data line Da on the substrate substrate at least partially overlap.
  • This arrangement may form a parasitic capacitance between the data line Da and the third extension portion 4VDD3, thereby enabling the data line to have a certain data storage capacity.
  • the area of the orthographic projection of the data line Da on the substrate is S3
  • the overlapping area of the orthographic projection of the data line Da on the substrate and the orthographic projection of the third extension portion 4VDD3 on the substrate is S4,
  • S4/S3 is greater than or equal to 20% and less than or equal to 70%, for example, S4/S3 can be equal to 20%, 30%, 40%, 50%, 60%, 70%.
  • the first power line segment 4VDD may further include a fourth extension portion 4VDD4, the orthographic projection of the fourth extension portion 4VDD4 on the substrate extends along the second direction Y and is located between the orthographic projection of the data line Da on the substrate and the orthographic projection of the second conductive portion on the substrate.
  • the orthographic projection of the fourth extension portion 4VDD4 on the substrate is located between the orthographic projection of the data line Da on the substrate and the orthographic projections of the ninth active portion 89 and the first bridge portion 41 on the substrate.
  • This arrangement can shield the noise influence of the data signal on the data line Da on the gate of the driving transistor through the fourth extension portion 4VDD4.
  • the size of the orthogonal projection of the third extension portion 4VDD3 on the substrate in the first direction X can be larger than the size of the orthogonal projection of the fourth extension portion 4VDD4 on the substrate in the first direction X; the orthogonal projection of a part of the structure of the third extension portion 4VDD3 on the substrate can also be located between the orthogonal projection of the second conductive portion on the substrate and the orthogonal projection of the data line Da on the substrate.
  • the orthogonal projection of a part of the structure of the third extension portion 4VDD3 on the substrate is located between the orthogonal projection of the first bridge portion 41 on the substrate and the orthogonal projection of the data line Da on the substrate.
  • This setting can also shield the noise influence of the data signal on the data line Da on the gate of the driving transistor.
  • the first power line segment 4VDD is connected to the power line 5VDD through a via. It should be understood that in other exemplary embodiments, the first power line segment 4VDD can also be connected to other stable voltage terminals. For example, the first power line segment 4VDD can also be connected to the first initial signal terminal, the second initial signal terminal, etc.
  • the fourth conductive layer may further include a first connecting portion 46 , and the first connecting portion 46 is connected between two adjacent first power line segments 4VDD in the first direction X.
  • the first power line segments 4VDD connected in the first direction X may form a grid structure with the power line 5VDD, and the power line of the grid structure has a relatively small resistance, thereby reducing the voltage difference between the first power terminals at different positions of the display panel, thereby improving the display uniformity of the display panel.
  • the design of the first power line segment 4VDD forming a parasitic capacitor with the data line, and the design of the first power line segment 4VDD shielding the noise of the data line to the gate of the driving transistor can be applied to display panels of any other architecture.
  • the design is not limited to other film layers and other film layer structures.
  • the first power line segment 4VDD located in a different film layer from the power line and the data line can be used to form a parasitic capacitor with the data line, and to shield the noise interference of the data line to the gate of the driving transistor.
  • the voltage required for the first light-emitting unit to emit light is greater than the voltage required for the second light-emitting unit to emit light.
  • the width-to-length ratio of the channel region of the driving transistor in the first pixel driving circuit P1 may be greater than the width-to-length ratio of the channel region of the driving transistor in the second pixel driving circuit P2.
  • the length of the channel region of the driving transistor in the first pixel driving circuit P1 may be less than the length of the channel region of the driving transistor in the second pixel driving circuit P2. This setting can reduce the impedance of the driving transistor, thereby increasing the voltage division between the first power supply terminal VDD and the second power supply terminal VSS of the light-emitting unit L.
  • this setting can make the voltage on both sides of the first light-emitting unit greater than the voltage on both sides of the second light-emitting unit under the same data signal, and this setting can meet the requirement that the voltage required for the first light-emitting unit to emit light is greater than the voltage required for the second light-emitting unit to emit light.
  • Figure 20 is a structural layout of the fifth conductive layer and the electrode layer in an exemplary embodiment of the display panel of the present disclosure
  • Figure 21 is a structural layout of the fifth conductive layer in Figure 20
  • Figure 22 is a structural layout of the electrode layer in Figure 20.
  • the electrode layer may include a plurality of electrode portions: a first electrode portion R, a second electrode portion B, and a third electrode portion G, each of which may be connected to the sixth bridge portion 56 through a via to connect the second electrode of the sixth transistor T6.
  • the first electrode portion R may be used to form a first electrode of a red light-emitting unit
  • the second electrode portion B may be used to form a first electrode of a blue light-emitting unit
  • the third electrode portion G may be used to form a first electrode of a green light-emitting unit.
  • the display panel may also include a pixel definition layer located on the side of the electrode layer away from the base substrate, and a pixel opening for forming a light-emitting unit is formed on the pixel definition layer.
  • the orthographic projection of the first electrode portion R on the substrate coincides with the orthographic projection of the corresponding pixel opening on the pixel definition layer on the substrate substrate
  • the orthographic projection of the second electrode portion B on the substrate coincides with the orthographic projection of the corresponding pixel opening on the pixel definition layer on the substrate substrate
  • the orthographic projection of the third electrode portion G on the substrate coincides with the orthographic projection of the corresponding pixel opening on the pixel definition layer on the substrate substrate.
  • the orthographic projections of each electrode portion on the substrate overlap with the orthographic projections of the power line 5VDD on the substrate and the orthographic projections of the data line Da on the substrate.
  • This arrangement allows as much of the electrode portion as possible to be located on the fifth conductive layer, thereby improving the flatness of the electrode portion to reduce the risk of color shift of the display panel at different viewing angles.
  • the minimum size of the overlapping portion of the orthographic projection of the electrode portion on the substrate substrate and the orthographic projection of the power line 5VDD on the substrate substrate in the first direction X is L1
  • the minimum size of the orthographic projection of the data line Da on the substrate substrate in the first direction X can be L2
  • L1 can be greater than L2, for example, L1/L2 can be equal to 1.5, 2, 3, 4, etc. This arrangement can further improve the flatness of the electrode portion.
  • the electrode portion may be composed of a first portion X1 and a second portion X2, and the orthographic projection of the first portion X1 on the substrate and the orthographic projection of the second portion X2 on the substrate may be distributed along the first direction X, and the maximum size of the orthographic projection of the first portion X1 on the substrate in the first direction X is equal to the maximum size of the orthographic projection of the second portion X2 on the substrate in the first direction X.
  • the orthographic projection of the first portion X1 on the substrate and the orthographic projection of the power line 5VDD on the substrate at least partially overlap, and the orthographic projection of the second portion X2 on the substrate and the orthographic projection of the data line Da on the substrate at least partially overlap.
  • This arrangement can make both sides of the electrode portion in the first direction X located on the fifth conductive layer, thereby further improving the flatness of the electrode portion.
  • the first light emitting unit may be a blue light emitting unit
  • the second light emitting unit may be a red light emitting unit
  • the second light emitting unit may also be a green light emitting unit. That is, the pixel driving circuit corresponding to the green light emitting unit may have all the features of the second pixel driving circuit described above.
  • the black squares drawn on the side of the fourth conductive layer away from the base substrate indicate that the fourth conductive layer is connected to the via holes of other layers facing the base substrate; the black squares drawn on the side of the fifth conductive layer away from the base substrate indicate that the fifth conductive layer is connected to the via holes of other layers facing the base substrate; the black squares drawn on the side of the electrode layer away from the base substrate indicate that the electrode layer is connected to the via holes of other layers facing the base substrate.
  • the black squares indicate the positions of the via holes, and different via holes represented by black squares at different positions may penetrate different insulating layers.
  • the display panel may further include a first insulating layer 91, a second insulating layer 92, a third insulating layer 93, a fourth insulating layer 94, a fifth insulating layer 95, a first dielectric layer 96, a passivation layer 97, a first flat layer 98, and a second flat layer 99, wherein the base substrate 90, the shielding layer, the first insulating layer 91, the first active layer, the second insulating layer 92, the first conductive layer, the third insulating layer 93, the second conductive layer, the fourth insulating layer 94, the second active layer, the fifth insulating layer 95, the third conductive layer, the first dielectric layer 96, the fourth conductive layer, the passivation layer 97, the first flat layer 98, the fifth conductive layer, the second flat layer 99, and the electrode layer are sequentially
  • the first insulating layer 91, the second insulating layer 92, the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 may be a single-layer structure or a multi-layer structure, and the materials of the first insulating layer 91, the second insulating layer 92, the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 may be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the first dielectric layer 96 may be a silicon nitride layer; the materials of the first flat layer 98 and the second flat layer 99 may be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), etc.
  • PI polyimide
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • SOG silicon-glass bonding structure
  • the substrate 90 may include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence, and the barrier layer may be an inorganic material.
  • the passivation layer 97 may be a silicon oxide layer.
  • the materials of the first conductive layer, the second conductive layer, and the third conductive layer may be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy, or a molybdenum/titanium alloy or a stack, etc.
  • the material of the fourth conductive layer and the fifth conductive layer may include a metal material, for example, one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or a laminate, or a titanium/aluminum/titanium laminate.
  • the electrode layer may include an indium tin oxide layer and a silver layer. The square resistance of any conductive layer of the first conductive layer, the second conductive layer, and the third conductive layer may be greater than the square resistance of any conductive layer of the fourth conductive layer and the fifth conductive layer.
  • the proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited to this.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the number shown in the figure.
  • the drawings described in the present disclosure are only structural schematic diagrams.
  • the first, second and other qualifiers are only used to define different structural names, and they do not have a specific order and quantity.
  • the positive projection of a certain structure on the substrate substrate extends in a certain direction, which can be understood as the positive projection of the structure on the substrate substrate extending straight or bending along the direction.
  • a transistor refers to an element including at least three terminals: a gate, a drain and a source.
  • the transistor has a channel region between the drain (drain electrode terminal, a drain region or a drain electrode) and the source (source electrode terminal, a source region or a source electrode), and the current can flow through the drain, the channel region and the source.
  • the channel region refers to the area where the current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the gate electrode may also be referred to as a control electrode.
  • This exemplary embodiment also provides a display device, which includes the above-mentioned display panel.
  • the display device can be a display device such as a mobile phone, a tablet computer, a television, etc.

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Abstract

一种显示面板及显示装置，显示面板包括：多个像素驱动电路，像素驱动电路包括驱动晶体管（T3）、第四晶体管（T4），第四晶体管（T4）的第一极连接数据线（Da），第二极连接驱动晶体管（T3）的第一极，栅极连接第一栅线（G1）；其中，多个像素驱动电路中包括第一像素驱动电路（P1）和第二像素驱动电路（P2）；第一像素驱动电路（P1）中驱动晶体管（T3）栅极的等电位结构与第一栅线（G1）形成的电容容量为C1，第二像素驱动电路（P2）中驱动晶体管（T3）栅极的等电位结构与第一栅线（G1）形成的电容容量为C2，C1不等于C2。该显示面板可以提高显示效果。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
相关技术中，在相同数据信号驱动下，至少部分不同子像素的发光亮度存在差异。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
根据本公开的一个方面，提供一种显示面板，其中，所述显示面板包括：多个像素驱动电路，所述像素驱动电路包括驱动晶体管、第四晶体管，所述第四晶体管的第一极连接数据线，第二极连接所述驱动晶体管的第一极，栅极连接第一栅线；其中，多个所述像素驱动电路中包括第一像素驱动电路和第二像素驱动电路；所述第一像素驱动电路中所述驱动晶体管栅极的等电位结构与所述第一栅线形成的电容容量为C1，所述第二像素驱动电路中所述驱动晶体管栅极的等电位结构与所述第一栅线形成的电容容量为C2，C1不等于C2。
本公开一种示例性实施例中，所述显示面板还包括多个发光单元，多个所述发光单元中包括第一发光单元和第二发光单元；所述第一像素驱动电路用于驱动所述第一发光单元，所述第二像素驱动电路用于驱动所述第二发光单元；在同一驱动电流下，所述第一发光单元的亮度小于所述第二发光单元的亮度，且C1小于C2。
本公开一种示例性实施例中，所述显示面板还包括：衬底基板、第一有源层、第一导电层、第二导电部。第一有源层位于所述衬底基板的一侧，所述第一有源层包括第三有源部，所述第三有源部用于形成所述驱动晶体 管的沟道区；第一导电层位于所述第一有源层背离所述衬底基板的一侧，所述第一导电层包括第一导电部，所述第一导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第一导电部用于形成所述驱动晶体管的栅极；第二导电部与所述第一导电部对应设置，所述第二导电部连接与其对应的所述第一导电部，所述第一像素驱动电路中所述第二导电部在所述衬底基板上的正投影和所述第一栅线在所述衬底基板上的正投影的交叠面积为S1，所述第二像素驱动电路中所述第二导电部在所述衬底基板上的正投影和所述第一栅线在所述衬底基板上的正投影的交叠面积为S2，S1小于S2。
本公开一种示例性实施例中，所述像素驱动电路还包括：第八晶体管，所述第八晶体管的第一极连接所述驱动晶体管的栅极，所述显示面板还包括：第二有源层，第二有源层位于所述第一导电层背离所述衬底基板的一侧，所述第二有源层包括相连接的第八有源部和第九有源部，所述第八有源部用于形成所述第八晶体管的沟道区；其中，所述第九有源部连接所述第一导电部，所述第二导电部包括所述第九有源部，且所述第一像素驱动电路中所述第九有源部在所述衬底基板上的正投影和所述第一栅线在所述衬底基板上的正投影的交叠面积小于所述第二像素驱动电路中所述第九有源部在所述衬底基板上的正投影和所述第一栅线在所述衬底基板上的正投影的交叠面积。
本公开一种示例性实施例中，所述第一导电层包括所述第一栅线，所述第一栅线在所述衬底基板上的正投影沿第一方向延伸。所述第一栅线包括：多个第一延伸部、多个第二延伸部，多个所述第一延伸部在所述衬底基板上的正投影沿所述第一方向延伸且沿所述第一方向间隔分布；第二延伸部连接于在所述第一方向上相邻的所述第一延伸部之间；其中，所述第一延伸部在所述衬底基板上的正投影在第二方向上的尺寸小于所述第二延伸部在所述衬底基板上的正投影在第二方向上的尺寸，所述第一方向和所述第二方向相交；所述第二导电部在所述衬底基板上的正投影和所述第二延伸部在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述像素驱动电路还包括：第八晶体管，所述第八晶体管的第一极连接所述驱动晶体管的栅极，所述显示面板还包 括：第二有源层，第二有源层位于所述第一导电层背离所述衬底基板的一侧，所述第二有源层包括相连接的第八有源部和第九有源部，所述第八有源部用于形成所述第八晶体管的沟道区；其中，所述第九有源部连接所述第一导电部，所述第二导电部包括所述第九有源部，所述第九有源部在所述衬底基板上的正投影位于所述第二延伸部在所述衬底基板上的正投影上；且所述第一像素驱动电路中所述第九有源部在所述衬底基板上的正投影在所述第一方向上的尺寸小于所述第二像素驱动电路中所述第九有源部在所述衬底基板上的正投影在所述第一方向上的尺寸。
本公开一种示例性实施例中，所述第一发光单元为蓝色发光单元，所述第二发光单元为红色发光单元或绿色发光单元。
本公开一种示例性实施例中，多个所述像素驱动电路沿第一方向和第二方向阵列分布，所述显示面板还包括：衬底基板、第四导电层、第五导电层，第四导电层位于所述衬底基板的一侧，所述第四导电层包括多条第一电源线段，所述第一电源线段与所述像素驱动电路对应设置，多条所述第一电源线段在所述衬底基板上的正投影沿第一方向和第二方向阵列分布且沿所述第二方向延伸，所述第一方向和所述第二方向相交，所述第一电源线段连接稳定电压源；第五导电层位于所述第四导电层背离所述衬底基板的一侧，所述第五导电层包括所述数据线，所述数据线在所述衬底基板上的正投影沿所述第二方向延伸。
本公开一种示例性实施例中，所述像素驱动电路还包括：第八晶体管，所述第八晶体管的第一极连接所述驱动晶体管的栅极，所述显示面板还包括：第二有源层、第三导电层，第二有源层位于所述第四导电层和所述衬底基板之间，所述第二有源层包括第八有源部，所述第八有源部用于形成所述第八晶体管的沟道区；第三导电层位于所述第二有源层和所述第四导电层之间，所述第三导电层包括第二栅线，所述第二栅线在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第八有源部在所述衬底基板上的正投影，所述第二栅线的部分结构用于形成所述第八晶体管的顶栅；其中，所述第一电源线段在所述衬底基板上的正投影位于相邻两所述第二栅线在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述显示面板还包括源极驱动电路，所 述源极驱动电路的一个信号输出端连接多条所述数据线，所述源极驱动电路的一个信号输出端在一行扫描周期内分时向多条所述数据线提供数据信号；所述第一电源线段包括第三延伸部，其中，所述第三延伸部在所述衬底基板上的正投影和所述数据线在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述数据线在所述衬底基板上的正投影的面积为S3，所述数据线在所述衬底基板上的正投影和所述第三延伸部在所述衬底基板上的正投影的交叠面积为S4，S4/S3大于等于20％且小于等于70％。
本公开一种示例性实施例中，所述驱动晶体管的第一极连接电源线；所述第四导电层还包括第一连接部，所述第一连接部连接于在所述第一方向上相邻的两所述第一电源线段之间；所述第五导电层还包括所述电源线，所述电源线在所述衬底基板上的正投影沿所述第二方向延伸，所述电源线用于提供所述稳定电压源。
本公开一种示例性实施例中，所述第一电源线段还包括第四延伸部；所述显示面板还包括第二导电部，所述第二导电部连接所述驱动晶体管的栅极；所述第四延伸部在所述衬底基板上的正投影沿所述第二方向延伸且位于所述数据线在所述衬底基板上的正投影和所述第二导电部在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述显示面板还包括第二导电部，所述第二导电部连接所述驱动晶体管的栅极；所述第一电源线段还包括第三延伸部，所述第三延伸部连接所述第四延伸部，所述第三延伸部在所述衬底基板上的正投影在所述第一方向上的尺寸大于所述第四延伸部在所述衬底基板上的正投影在所述第一方向上的尺寸；所述第三延伸部的部分结构在所述衬底基板上的正投影位于所述第二导电部在所述衬底基板上的正投影和所述数据线在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述驱动晶体管的第一极连接电源线，所述像素驱动电路还包括：第八晶体管，所述第八晶体管的第一极连接所述驱动晶体管的栅极，所述显示面板还包括：衬底基板、第二有源层、第五导电层，第二有源层位于所述衬底基板的一侧，所述第二有源层包括有 源部，所述有源部的部分结构用于形成所述第八晶体管的沟道区；第五导电层位于所述第二有源层背离所述衬底基板的一侧，所述第五导电层包括所述电源线，所述电源线在所述衬底基板上的正投影覆盖所述有源部在所述衬底基板上的正投影。
本公开一种示例性实施例中，所述驱动晶体管的第一极连接电源线，所述显示面板还包括：衬底基板、第二导电部、第五导电层，所述第二导电部连接所述驱动晶体管的栅极；第五导电层位于所述衬底基板的一侧，所述第五导电层包括所述电源线，所述电源线在所述衬底基板上的正投影覆盖所述第二导电部在所述衬底基板上的正投影。
本公开一种示例性实施例中，所述驱动晶体管的第一极连接电源线，所述显示面板还包括：衬底基板、第五导电层、电极层、像素定义层，第五导电层位于所述衬底基板的一侧，所述第五导电层包括所述电源线和所述数据线，所述电源线在所述衬底基板上的正投影、所述数据线在所述衬底基板上的正投影沿第二方向延伸；电极层包括多个电极部，所述电极部在所述衬底基板上的正投影和所述电源线在所述衬底基板上的正投影、所述数据线在所述衬底基板上的正投影均交叠；像素定义层位于所述电极层背离所述衬底基板的一侧，所述像素定义层上形成有用于形成发光单元的像素开口，所述像素开口在所述衬底基板上的正投影和所述电极部在所述衬底基板上的正投影重合。
本公开一种示例性实施例中，所述电极部由第一部分和第二部分组成，所述第一部分在所述衬底基板上的正投影和所述第二部分在所述衬底基板上的正投影沿第一方向分布，且所述第一部分在所述衬底基板上的正投影在所述第一方向上的最大尺寸等于所述第二部分在所述衬底基板上的正投影在所述第一方向上的最大尺寸，所述第一方向和所述第二方向相交；所述第一部分在所述衬底基板上的正投影和所述电源线在所述衬底基板上的正投影至少部分交叠，所述第二部分在所述衬底基板上的正投影和所述数据线在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述电极部在所述衬底基板上的正投影和所述电源线在所述衬底基板上的正投影的交叠区域在所述第一方向上的最小尺寸为L1，所述数据线在所述衬底基板上的正投影在所述第一方向 上的最小尺寸为L2，L1大于L2。
本公开一种示例性实施例中，所述显示面板还包括多个发光单元，多个所述发光单元中包括第一发光单元和第二发光单元；所述第一像素驱动电路用于驱动所述第一发光单元，所述第二像素驱动电路用于驱动所述第二发光单元；所述第一发光单元发光所需跨压大于所述第二发光单元发光所需跨压，所述第一像素驱动电路中所述驱动晶体管沟道区的宽长比大于所述第二像素驱动电路中所述驱动晶体管沟道区的宽长比。
本公开一种示例性实施例中，所述第一像素驱动电路中所述驱动晶体管的沟道区长度小于所述第二像素驱动电路中所述驱动晶体管的沟道区长度。
本公开一种示例性实施例中，所述显示面板还包括发光单元，所述像素驱动电路用于驱动所述发光单元发光，所述像素驱动电路还包括：第八晶体管、第一晶体管、第二晶体管、第五晶体管、第六晶体管、第七晶体管、电容，第八晶体管的第一极连接所述驱动晶体管的栅极，栅极连接第二栅线；第一晶体管的第一极连接第一初始信号线，第二极连接所述第八晶体管的第二极，栅极连接第一复位信号线；第二晶体管的第一极连接所述第八晶体管的第二极，第二极连接所述驱动晶体管的第二极，栅极连接所述第一栅线；第五晶体管的第一极连接电源线，第二极连接所述驱动晶体管的第一极，栅极连接使能信号线；第六晶体管的第一极连接所述驱动晶体管的第二极，第二极连接所述发光单元的第一电极，栅极连接所述使能信号线；第七晶体管的第一极连接第二初始信号线，第二极连接所述发光单元的第一电极，栅极连接第二复位信号线；电容连接于所述驱动晶体管的栅极和所述电源线之间。
本公开一种示例性实施例中，所述显示面板还包括：衬底基板、第一有源层、第一导电层、第二有源层、第三导电层。第一有源层位于所述衬底基板的一侧，所述第一有源层包括第一有源部、第二有源部、第三有源部、第四有源部、第五有源部、第六有源部、第七有源部，所述第一有源部用于形成所述第一晶体管的沟道区，所述第二有源部用于形成所述第二晶体管的沟道区，所述第三有源部用于形成所述驱动晶体管的沟道区，所述第四有源部用于形成所述第四晶体管的沟道区，所述第五有源部用于形 成所述第五晶体管的沟道区，所述第六有源部用于形成所述第六晶体管的沟道区，所述第七有源部用于形成所述第七晶体管的沟道区；第一导电层包括所述第一栅线、第一复位信号线、第二复位信号线、使能信号线、第一导电部，所述第一栅线、第一复位信号线、第二复位信号线、使能信号线在所述衬底基板上的正投影均沿第一方向延伸；其中，所述第一栅线的部分结构用于分别形成所述第二晶体管、第四晶体管的栅极，所述使能信号线的部分结构用于分别形成所述第五晶体管、第六晶体管的栅极，所述第一复位信号线的部分结构用于形成所述第一晶体管的栅极，所述第二复位信号线的部分结构用于形成所述第七晶体管的栅极，所述第一导电部用于形成所述驱动晶体管的栅极；第二有源层位于所述第一导电层背离所述衬底基板的一侧，所述第二有源层包括第八有源部，所述第八有源部用于形成所述第八晶体管的沟道区；第三导电层位于所述第二有源层背离所述衬底基板的一侧，所述第三导电层包括所述第二栅线，所述第二栅线的部分结构用于形成所述第八晶体管的顶栅；其中，所述第一导电部在所述衬底基板上的正投影位于所述第一栅线在所述衬底基板上的正投影和所述使能信号线在所述衬底基板上的正投影之间，所述第一复位信号线在所述衬底基板上的正投影位于所述第一栅线在所述衬底基板上的正投影远离所述第一导电部在所述衬底基板上的正投影的一侧，所述第二栅线在所述衬底基板上的正投影位于所述第一复位信号线在所述衬底基板上的正投影和所述第一栅线在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述第一方向为行方向，所述显示面板包括多行像素驱动电路；相邻上一行像素驱动电路中所述第二初始信号线在衬底基板上的正投影位于本行像素驱动电路中所述第一复位信号线在所述衬底基板上的正投影和本行像素驱动电路中所述第二栅线在所述衬底基板上的正投影之间；相邻下一行像素驱动电路中所述第一初始信号线在所述衬底基板上的正投影位于本行像素驱动电路中所述第二复位信号线在所述衬底基板上的正投影和本行像素驱动电路中所述使能信号线在所述衬底基板上的正投影之间；本行像素驱动电路中所述第二复位信号线复用为相邻下一行像素驱动电路中所述第一复位信号线。
本公开一种示例性实施例中，所述第一晶体管、第二晶体管、驱动晶 体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管为P型晶体管，所述第八晶体管为N型晶体管。
根据本公开的一个方面，提供一种显示装置，其中，包括上述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开显示面板一种示例性实施例中像素驱动电路的电路结构示意图；
图2为图1所示像素驱动电路中各节点上信号的时序图；
图3为本公开显示面板一种示例性实施例中的结构版图；
图4为图3中遮挡层的结构版图；
图5为图3中第一有源层的结构版图；
图6为图3中第一导电层的结构版图；
图7为图3中第二导电层的结构版图；
图8为图3中第二有源层的结构版图；
图9为图3中第三导电层的结构版图；
图10为图3中第四导电层的结构版图；
图11为图3中第五导电层的结构版图；
图12为图3中电极层的结构版图；
图13为图3中遮挡层、第一有源层的结构版图；
图14为图3中遮挡层、第一有源层、第一导电层的结构版图；
图15为图3中遮挡层、第一有源层、第一导电层、第二导电层的结构版图；
图16为图3中遮挡层、第一有源层、第一导电层、第二导电层、第二有源层的结构版图；
图17为图3中遮挡层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层的结构版图；
图18为图3中遮挡层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层的结构版图；
图19为图3中遮挡层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层、第五导电层的结构版图；
图20为本公开显示面板一种示例性实施例中第五导电层和电极层的结构版图；
图21为图20中第五导电层的结构版图；
图22为图20中电极层的结构版图；
图23为图3所示显示面板沿虚线AA剖开的部分剖视图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
相关技术中，显示面板包括多个子像素单元，每个子像素单元可以包括像素驱动电路和发光单元，像素驱动电路根据数据信号向发光单元提供驱动电流以驱动发光单元发光。由于不同颜色发光单元具有不同材质的发光材料层，不同颜色子像素单元在黑态下所需的数据信号电压不同，即在同一驱动电流下，不同颜色发光单元具有不同的亮度。例如，蓝色子像素单元在黑态下所需的数据信号电压小于红色和绿色子像素单元在黑态下 所需的数据信号电压。以像素驱动电路中驱动晶体管为P型晶体管为例，数据信号电压越大发光单元亮度越低，在同一驱动电流下，蓝色发光单元的亮度小于红色发光单元和绿色发光单元的亮度。同时，由于显示面板中不同颜色子像素单元在黑态下的数据信号相同，从而导致显示面板显示异常，尤其在低灰阶下显示异常尤为明显。例如，蓝色子像素单元在黑态下所需的数据信号电压为6V，红色子像素单元和绿色子像素在黑态下所需的数据信号电压为6.5V，显示面板显示黑画面时的数据信号电压为6.5V。显然，当数据信号电压小于6.5V时，蓝色发光单元的亮度小于红色发光单元和绿色发光单元的亮度。
基于此，本示例性实施例提供一种显示面板，如图1所示，为本公开显示面板一种示例性实施例中像素驱动电路的电路结构示意图。该像素驱动电路可以包括：第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、电容C。其中，第八晶体管T8的第一极连接驱动晶体管T3的栅极，栅极连接第二栅极驱动信号端G2；第一晶体管T1的第一极连接第一初始信号端Vinit1，第二极连接第八晶体管T8的第二极，栅极连接第一复位信号端Re1；第二晶体管T2的第一极连接第八晶体管T8的第二极，第二极连接驱动晶体管T3的第二极，栅极连接第一栅极驱动信号端G1；第四晶体管T4的第一极连接数据信号端Da，第二极连接驱动晶体管T3的第一极，栅极连接第一栅极驱动信号端G1；第五晶体管T5的第一极连接第一电源端VDD，第二极连接驱动晶体管T3的第一极，栅极连接使能信号端EM，第六晶体管T6的第一极连接驱动晶体管T3的第二极，栅极连接使能信号端EM；第七晶体管T7的第一极连接第二初始信号端Vinit2，第二极连接第六晶体管T6的第二极，栅极连接第二复位信号端Re2；电容的第一电极连接驱动晶体管T3的栅极，第二电极连接第一电源端VDD。该像素驱动电路可以用于驱动发光单元L发光，发光单元L的第一电极连接第六晶体管T6的第二极，发光单元L的第二电极连接第二电源端VSS。其中，第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以均为P型晶体管，第八晶体管T8可以为N型晶体管。
如图2所示，为图1所示像素驱动电路中各节点上信号的时序图。其中，EM表示使能信号端上信号的时序图；G1表示第一栅极驱动信号端上信号的时序图；G2表示第二栅极驱动信号端上信号的时序图；Re1表示第一复位信号端上信号的时序图；Re2表示第二复位信号端上信号的时序图。
本公开中像素驱动电路的驱动方法可以包括第一复位阶段t1、第二复位阶段t2、数据写入阶段t3、发光阶段t4。第一复位阶段t1：第一复位信号端Re1输出低电平，第二栅极驱动信号端G2输出高电平，第一晶体管T1、第八晶体管T8导通，第一初始信号端Vinit1向驱动晶体管T3栅极输入第一初始信号；在第二复位阶段t2，第二复位信号端Re2输出低电平信号，第七晶体管T7导通，第二初始信号端Vinit2向发光单元的第一电极输入第二初始信号；在数据写入阶段t3，第一栅极驱动信号端G1输出低电平信号，第二栅极驱动信号端G2输出高电平信号，第八晶体管T8、第四晶体管T4、第二晶体管T2导通，数据信号端Da输出数据信号以向驱动晶体管的栅极写入补偿电压Vdata+Vth，其中Vdata为数据信号的电压，Vth为驱动晶体管T3的阈值电压。在发光阶段t4：使能信号端EM输出低电平信号，第五晶体管T5、第六晶体管T6导通，驱动晶体管T3在其栅极的电压Vdata+Vth作用下驱动发光单元L发光。根据驱动晶体管输出电流公式I＝(μWCox/2L)(Vgs-Vth) 2，其中，μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电压。本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth) 2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。
本示例性实施例中，显示面板可以包括多个上述的像素驱动电路，其中，多个所述像素驱动电路中包括第一像素驱动电路和第二像素驱动电路；所述显示面板还包括多个发光单元，多个所述发光单元中包括第一发光单元和第二发光单元；所述第一像素驱动电路用于驱动所述第一发光单元，所述第二像素驱动电路用于驱动所述第二发光单元；所述第一像素驱动电路中所述驱动晶体管栅极的等电位结构与所述第一栅线形成的电容容量为C1，所述第二像素驱动电路中所述驱动晶体管栅极的等电位结构与所述 第一栅线形成的电容容量为C2，第一栅线可以用于提供图1中的第一栅极驱动信号端G1。在同一驱动电流下，所述第一发光单元的亮度小于所述第二发光单元的亮度，且C1小于C2。
本示例性实施例中，第一栅线在数据写入阶段t3结束时从低电平变为高电平，通过第一栅线与驱动晶体管栅极之间电容的耦合作用，第一栅线可以拉高驱动晶体管栅极的电压。本示例性实施例，第一像素驱动电路中驱动晶体管栅极的等电位结构与第一栅线所形成电容的容量小于第二像素驱动电路中驱动晶体管栅极的等电位结构与第一栅线所形成电容的容量，从而第一栅线对第一像素驱动电路中驱动晶体管栅极的上拉作用小于第一栅线对第二像素驱动电路中驱动晶体管栅极的上拉作用。即在相同数据信号下，第一像素驱动电路中驱动晶体管栅极的实际驱动电压小于第二像素驱动电路中驱动晶体管栅极的实际驱动电压，该实际驱动电压的差异刚好可以补偿第一发光单元和第二发光单元在黑态下所需数据信号电压的差异，从而本示例性实施例可以使得在同一数据信号下，第一发光单元和第二发光单元的亮度相同。
需要说明的是，在其他示例性实施例中，像素驱动电路还可以为其他结构，只要该像素驱动电路包括驱动晶体管T3和第四晶体管T4，均可以通过不同像素驱动电路中驱动晶体管栅极等电位结构和第一栅线之间电容容量的差异化设置，以补偿由于不同发光单元在黑态下所需数据信号电压差异导致的显示异常。此外，不同像素驱动电路中驱动晶体管栅极等电位结构和第一栅线之间电容容量的差异化设置还可以用于解决由于其他原因导致的同一数据信号电压下不同发光单元亮度不一致的问题，例如，该设置还可以解决由于像素驱动电路中驱动晶体管输出特性差异导致的同一数据信号电压下不同发光单元亮度不一致的问题。
在本示例性实施例中，显示面板可以包括依次层叠设置的衬底基板、遮挡层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层、第五导电层、电极层，其中，上述相邻层级之间可以设置有绝缘层。如图3-19所示，图3为本公开显示面板一种示例性实施例中的结构版图，图4为图3中遮挡层的结构版图，图5为图3中第一有源层的结构版图，图6为图3中第一导电层的结构版图，图7为图3中第二 导电层的结构版图，图8为图3中第二有源层的结构版图，图9为图3中第三导电层的结构版图，图10为图3中第四导电层的结构版图，图11为图3中第五导电层的结构版图，图12为图3中电极层的结构版图，图13为图3中遮挡层、第一有源层的结构版图，图14为图3中遮挡层、第一有源层、第一导电层的结构版图，图15为图3中遮挡层、第一有源层、第一导电层、第二导电层的结构版图，图16为图3中遮挡层、第一有源层、第一导电层、第二导电层、第二有源层的结构版图，图17为图3中遮挡层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层的结构版图，图18为图3中遮挡层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层的结构版图，图19为图3中遮挡层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层、第五导电层的结构版图。该显示面板可以包括多个图1所示的像素驱动电路。如图19所示，多个像素驱动电路中可以包括上述的第一像素驱动电路P1和第二像素驱动电路P2。
如图3、图4、图13所示，遮挡层可以包括多个遮挡部71、连接部73、连接部72，连接部73在衬底基板上的正投影沿第二方向Y延伸，且连接于在第二方向Y上相邻的遮挡部71之间；连接部72在衬底基板上的正投影沿第一方向X延伸，且连接于在第一方向X上相邻的遮挡部71之间。其中，第一方向X和第二方向Y可以相互连接，例如，第一方向X可以为行方向，第二方向Y可以为列方向。
如图3、5、13、14所示，第一有源层可以包括第一有源部61、第二有源部62、第三有源部63、第四有源部64、第五有源部65、第六有源部66、第七有源部67。其中，第一有源部61用于形成第一晶体管T1的沟道区，第二有源部62用于形成第二晶体管T2的沟道区，第三有源部63用于形成驱动晶体管T3的沟道区，第四有源部64用于形成第四晶体管T4的沟道区，第五有源部65用于形成第五晶体管T5的沟道区，第六有源部66用于形成第六晶体管T6的沟道区，第七有源部67用于形成第七晶体管T7的沟道区。此外，第一有源层还可以包括：第十一有源部611、第十二有源部612、第十三有源部613、第十四有源部614、第十五有源部615、第十六有源部616。第十五有源部615连接于第四有源部64远离第三有源 部63的一端；第十六有源部616连接于第一有源部61和第二有源部62之间；第十一有源部611连接于第一有源部61远离第二有源部62的一端；第十二有源部612连接于第五有源部65远离第三有源部63的一端，第十三有源部613连接于第六有源部66和第七有源部67之间；第十四有源部614连接于第七有源部67远离第六有源部66的一端。遮挡部71在衬底基板上的正投影可以覆盖第三有源部63在衬底基板上的正投影，遮挡部71可以对第三有源部63进行遮光，以降低光照对驱动晶体管T3驱动特性的影响。此外，遮挡层可以为导电材料，遮挡层还可以连接一稳定电压源，以对驱动晶体管T3进行噪音屏蔽，例如，遮挡层可以连接第一电源端VDD、第一初始信号端Vinit1、第二初始信号端Vinit2、第二电源端VSS等。第一有源层可以由多晶硅材料形成，相应的，第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型的低温多晶硅薄膜晶体管。
如图3、6、14所示，第一导电层可以包括第一复位信号线Re1、第一栅线G1、使能信号线EM、第二复位信号线Re2、第一导电部11。第一复位信号线Re1可以用于提供图1中的第一复位信号端。第一复位信号线Re1在衬底基板上的正投影可以覆盖第一有源部61在衬底基板上的正投影，第一复位信号线Re1的部分结构可以用于形成第一晶体管T1的栅极。第一栅线G1可以用于提供图1中的第一栅极驱动信号端。第一栅线G1在衬底基板上的正投影可以覆盖第二有源部62在衬底基板上的正投影、第四有源部64在衬底基板上的正投影。第一栅线G1的部分结构可以用于形成第二晶体管T2的栅极，第一栅线G1的另外部分结构可以用于形成第四晶体管T4的栅极。使能信号线EM用于提供图1中的使能信号端，使能信号线EM在衬底基板上的正投影可以沿第一方向X延伸且覆盖第五有源部65在衬底基板上的正投影、第六有源部66在衬底基板上的正投影，使能信号线EM的部分结构可以用于形成第五晶体管T5的栅极，使能信号线EM的另外部分结构可以用于形成第六晶体管T6的栅极。第二复位信号线Re2用于提供图1中的第二复位信号端。第二复位信号线Re2在衬底基板上的正投影可以覆盖第七有源部67在衬底基板上的正投影。第二复位信号线Re2的部分结构可以用于形成第七晶体管T7的栅极。第一导电部11在衬 底基板上的正投影可以覆盖第三有源部63在衬底基板上的正投影，第一导电部11可以用于形成驱动晶体管T3的栅极和电容C的第一电极。
如图3、6、14所示，第一复位信号线Re1在衬底基板上的正投影、第一栅线G1在衬底基板上的正投影、第一导电部11在衬底基板上的正投影、使能信号线EM在衬底基板上的正投影、第二复位信号线Re2在衬底基板上的正投影可以沿第二方向Y依次分布。本行像素驱动电路中的第一复位信号线Re1可以复用为相邻上一行像素驱动电路中的第二复位信号线Re2。该设置可以提高像素驱动电路在第二方向Y上的集成度。此外，该显示面板可以利用第一导电层为掩膜对第一有源层进行导体化处理，即第一有源层中被第一导电层覆盖的区域可以形成晶体管的沟道区，第一有源层中未被第一导电层覆盖的区域形成导体结构。
如图3、7、15所示，第二导电层可以包括第三栅线2G2、第一初始信号线Vinit1、第三导电部23。第一初始信号线Vinit1在衬底基板上的正投影、第三栅线2G2在衬底基板上的正投影均可以沿第一方向X延伸。第一初始信号线Vinit1用于提供图1中的第一初始信号端，第三栅线2G2用于提供图1中的第二栅极驱动信号端。第三导电部23在衬底基板上的正投影可以与第一导电部11在衬底基板上的正投影交叠，第三导电部23可以用于形成电容C的第二电极。如图3、7、15所示，相邻下一行像素驱动电路中第一初始信号线Vinit1在衬底基板上的正投影可以位于本行像素驱动电路中使能信号线EM在衬底基板上的正投影和本行像素驱动电路中第二复位信号线Re2在衬底基板上的正投影之间。该设置可以进一步提高像素驱动电路在第二方向Y上的集成度。应该理解的是，在其他示例性实施例中，第一初始信号线Vinit1还可以位于其他导电层，例如，第一初始信号线Vinit1还可以位于遮挡层、第三导电层、第四导电层等。
如图3、8、16所示，第二有源层可以包括多个有源部8，有源部8包括第八有源部88、第九有源部89、第十有源部810，第八有源部88连接于第九有源部89和第十有源部810之间，第八有源部88用于形成第八晶体管的沟道区。第三栅线2G2在衬底基板上的正投影可以覆盖第八有源部88在衬底基板上的正投影，第三栅线2G2的部分结构可以用于形成第八晶体管T8的底栅。其中，第二有源层可以由氧化铟镓锌形成，相应的， 第八晶体管T8可以为N型的金属氧化物薄膜晶体管。
如图3、9、17所示，第三导电层可以包括：第二栅线3G2，第二栅线3G2在衬底基板上的正投影可以沿第一方向X延伸。第二栅线3G2用于提供图1中的第二栅极驱动信号端，第二栅线3G2在衬底基板上的正投影可以覆盖第八有源部88在衬底基板上的正投影，第二栅线3G2的部分结构可以用于形成第八晶体管T8的顶栅。同一行像素驱动电路中的第二栅线3G2和第三栅线2G2可以通过过孔连接，连接于第二栅线3G2和第三栅线2G2之间的过孔可以位于显示面板显示区以外的边沿走线区。此外，该显示面板可以利用第三导电层为掩膜对第二有源层进行导体化处理，即第二有源层中被第三导电层覆盖的区域可以形成晶体管的沟道区，第二有源层中未被第三导电层覆盖的区域形成导体结构。
如图3、9、17所示，在同一像素驱动电路中，且在第一方向X上，第二有源部62在衬底基板上的正投影位于第八有源部88在衬底基板上的正投影远离连接部73在衬底基板上的正投影的一侧。该设置可以使得第二有源部62远离连接部73，从而可以避免连接部73边缘形貌引起的第一有源层晶化状态变化以及隧穿风险。
如图3、9、17所示，第一有源部61在衬底基板上的正投影与遮挡层在衬底基板上的正投影之间的最小距离为L3，第一有源部61在衬底基板上的正投影在第一方向X上的尺寸为L4，L3可以大于等于L4。例如，L3可以为L4的1倍、2倍、3倍、4倍等。第二有源部62在衬底基板上的正投影与遮挡层在衬底基板上的正投影之间的最小距离为L7，第二有源部62在衬底基板上的正投影在第一方向X上的尺寸为L8，L7可以大于等于L8。例如，L7可以为L8的0.5倍、1倍、2倍、3倍、4倍等。第四有源部64在衬底基板上的正投影与遮挡层在衬底基板上的正投影之间的最小距离为L9，第四有源部64在衬底基板上的正投影在第一方向X上的尺寸为L10，L9可以大于等于L10。例如，L9可以为L10的1倍、2倍、3倍、4倍等。第五有源部65在衬底基板上的正投影与遮挡层在衬底基板上的正投影之间的最小距离为L11，第五有源部65在衬底基板上的正投影在第一方向X上的尺寸为L12，L11可以大于等于L12。例如，L11可以为L12的1倍、2倍、3倍、4倍等。第六有源部66在衬底基板上的正投影与遮挡 层在衬底基板上的正投影之间的最小距离为L13，第六有源部66在衬底基板上的正投影在第一方向X上的尺寸为L14，L13可以大于等于L14。例如，L13可以为L14的1倍、2倍、3倍、4倍等。第七有源部67在衬底基板上的正投影与遮挡层在衬底基板上的正投影之间的最小距离为L15，第七有源部67在衬底基板上的正投影在第一方向X上的尺寸为L16，L15可以大于等于L16。例如，L15可以为L16的1倍、2倍、3倍、4倍等。该设置将遮挡层设置于远离第一有源层中沟道区的位置，从而可以避免遮挡层边缘形貌引起的第一有源层晶化状态变化以及隧穿风险。应该理解的是，在其他示例性实施例中，遮挡层在衬底基板上正投影和第一有源层中沟道区在衬底基板上正投影之间的距离也可以不做限定。
如图3、10、18所示，第四导电层可以包括：第二初始信号线Vinit2、第一电源线段4VDD、第一桥接部41、第二桥接部42、第三桥接部43、第四桥接部44、第五桥接部45。第二初始信号线Vinit2可以用于提供图1中的第二初始信号端。第二初始信号线Vinit2可以通过过孔H连接第十四有源部614，以连接第七晶体管T7的第一极和第二初始信号端，其中，黑色方块表示过孔的位置。第一电源线段4VDD与所述像素驱动电路一一对应设置，多条所述第一电源线段4VDD在所述衬底基板上的正投影沿第一方向X和第二方向Y阵列分布且沿所述第二方向Y延伸。第一电源线段4VDD可以分别通过过孔连接第十二有源部612和第三导电部23，以连接第五晶体管T5的第一极和电容C的第二极。第一桥接部41可以分别通过过孔连接第一导电部11和第九有源部89，以连接驱动晶体管T3的栅极和第八晶体管T8的第一极。如图7所示，第三导电部23上形成有开口231，连接于第一导电部11和第一桥接部41之间的过孔在衬底基板上的正投影位于开口231在衬底基板上的正投影以内，以使连接于第一导电部11和第一桥接部41之间的过孔与第三导电部23绝缘。第二桥接部42可以分别通过过孔连接第十一有源部611和第一初始信号线Vinit1，以连接第一晶体管T1的第一极和第一初始信号端。第三桥接部43可以通过过孔连接第十三有源部613，以连接第六晶体管T6的第二极和第七晶体管T7的第二极。第四桥接部44可以分别通过过孔连接第十有源部810和第十六有源部616以连接第八晶体管T8的第二极和第一晶体管的第二极、第二晶 体管的第一极。第五桥接部45通过过孔连接第十五有源部615，以连接第四晶体管的第一极。本示例性实施例中，相邻上一行像素驱动电路中所述第二初始信号线Vinit2在衬底基板上的正投影位于本行像素驱动电路中第一复位信号线Re1在所述衬底基板上的正投影和本行像素驱动电路中所述第二栅线3G2在所述衬底基板上的正投影之间，该设置可以提高像素驱动电路在第二方向Y上的集成度。应该理解的是，第二初始信号线Vinit2还可以位于其他导电层，例如，第二初始信号线Vinit2可以位于遮挡层、第二导电层、第三导电层等。
如图3、8、17、18所示，本示例性实施例将第一栅线G1设置于第一导电部11和第二栅线3G2之间，从而可以增加第一栅线G1和第一导电部11之间的耦合作用，在数据写入阶段结束时，第一栅线G1的电压升高，第一栅线G1可以拉高驱动晶体管T3栅极的电压。该设置可以降低显示面板黑画面下数据信号的电压，从而降低显示面板的功耗。本示例性实施例中，第九有源部89在衬底基板上的正投影和第一栅线G1在衬底基板上的正投影至少部分交叠。在数据写入阶段结束时，第一栅线G1可以能够通过第九有源部89拉高驱动晶体管T3栅极的电压。该设置可以进一步降低显示面板黑画面下数据信号的电压，从而降低显示面板的功耗。
如图3、6、8、17、18所示，第一栅线G1可以包括：多个第一延伸部G11和多个第二延伸部G12，多个所述第一延伸部G11在所述衬底基板上的正投影沿所述第一方向X延伸且沿所述第一方向X间隔分布；第二延伸部G12连接于在所述第一方向X上相邻的所述第一延伸部之间；其中，所述第一延伸部G11在所述衬底基板上的正投影在第二方向Y上的尺寸小于所述第二延伸部G12在所述衬底基板上的正投影在第二方向Y上的尺寸。第九有源部89为驱动晶体管栅极的等电位结构，本示例性实施例可以通过调节第九有源部89和第二延伸部G12在衬底基板上的交叠面积以实现C1和C2的差异化设置。本示例性实施例中，第一像素驱动电路P1中第九有源部89在所述衬底基板上的正投影和所述第一栅线G1在所述衬底基板上的正投影的交叠面积可以小于第二像素驱动电路P2中第九有源部89在所述衬底基板上的正投影和所述第一栅线G1在所述衬底基板上的正投影的交叠面积。
如图3、6、8、17、18所示，本示例性实施例中，第九有源部89在所述衬底基板上的正投影位于所述第二延伸部G12在所述衬底基板上的正投影上；且所述第一像素驱动电路P1中所述第九有源部89在所述衬底基板上的正投影在所述第一方向X上的尺寸小于所述第二像素驱动电路P2中所述第九有源部89在所述衬底基板上的正投影在所述第一方向X上的尺寸。
应该理解的是，驱动晶体管T3栅极的等电位结构还可以包括其他结构，例如，驱动晶体管T3栅极的等电位结构还可以包括第一桥接部41。与第一导电部连接的驱动晶体管T3栅极的等电位结构可以形成第二导电部。本示例性实施例可以通过调节第二导电部和第二延伸部G12在衬底基板上的交叠面积以实现C1和C2的差异化设置。例如，本示例性实施例中，所述第一像素驱动电路P1中第二导电部在所述衬底基板上的正投影和所述第一栅线G1在所述衬底基板上的正投影的交叠面积为S1，所述第二像素驱动电路中所述第二导电部在所述衬底基板上的正投影和所述第一栅线在所述衬底基板上的正投影的交叠面积为S2，S1可以小于S2。
此外，在其他示例性实施例中，还可以通过其他方式实现C1和C2的差异化设置。例如，可以通过调节在衬底基板上正投影交叠部分的第二导电部和第一栅线之间的距离以调节第二导电部和第一栅线之间的电容容量。
如图3、11、19所示，第五导电层可以包括数据线Da、电源线5VDD、第六桥接部56。其中，数据线Da可以用于提供图1中的数据信号端，电源线5VDD可以用于提供图1中的第一电源端。数据线Da在衬底基板上的正投影、电源线5VDD在衬底基板上的正投影可以沿第二方向Y延伸。数据线Da可以通过过孔连接第五桥接部45，以连接第四晶体管T4的第一极和数据信号端。每列像素驱动电路可以对应设置一条电源线5VDD，电源线5VDD可以通过过孔连接第一电源线段4VDD，以连接第一电源端和电容C的第二电极、第五晶体管T5的第一极。第六桥接部56可以通过过孔连接第三桥接部43以连接第六晶体管T6的第二极。
如图3、11、19所示，电源线5VDD在衬底基板上的正投影可以覆盖有源部8在衬底基板上的正投影，电源线5VDD可以降低光照对第八晶体 管T8的特性影响。此外，电源线5VDD在衬底基板上的正投影还可以覆盖第九有源部89、第一桥接部41在衬底基板上的正投影，电源线5VDD可以用于屏蔽其他信号对第九有源部89、第一桥接部41的噪音干扰，从而提高驱动晶体管T3栅极电压的稳定性。电源线5VDD在衬底基板上的正投影可以覆盖上述的第二导电部在衬底基板上的正投影。
本示例性实施例中，所述显示面板还可以包括源极驱动电路，所述源极驱动电路的一个信号输出端可以连接多条所述数据线，所述源极驱动电路的一个信号输出端在一行扫描周期内可以分时向多条所述数据线提供数据信号，多条数据线在数据写入阶段需要同时向扫描像素行提供数据信号。因此，数据线需要具有一定的数据存储能力。如图3、10、11、19所示，所述第一电源线段4VDD可以包括第三延伸部4VDD3，其中，所述第三延伸部4VDD3在所述衬底基板上的正投影和所述数据线Da在所述衬底基板上的正投影至少部分交叠。该设置可以使得数据线Da与第三延伸部4VDD3之间形成寄生电容，进而使得数据线具有一定的数据存储能力。本示例性实施例中，数据线Da在所述衬底基板上的正投影的面积为S3，所述数据线Da在所述衬底基板上的正投影和所述第三延伸部4VDD3在所述衬底基板上的正投影的交叠面积为S4，S4/S3大于等于20％且小于等于70％，例如，S4/S3可以等于20％、30％、40％、50％、60％、70％。
如图3、10、11、19所示，第一电源线段4VDD还可以包括第四延伸部4VDD4，第四延伸部4VDD4在所述衬底基板上的正投影沿所述第二方向Y延伸且位于所述数据线Da在所述衬底基板上的正投影和所述第二导电部在所述衬底基板上的正投影之间。例如，当第二导电部包括第九有源部89和第一桥接部41时，第四延伸部4VDD4在所述衬底基板上的正投影位于所述数据线Da在所述衬底基板上的正投影和第九有源部89、第一桥接部41在所述衬底基板上的正投影之间。该设置可以通过第四延伸部4VDD4屏蔽数据线Da上数据信号对驱动晶体管栅极的噪音影响。
如图3、11、19所示，所述第三延伸部4VDD3在所述衬底基板上的正投影在所述第一方向X上的尺寸可以大于所述第四延伸部4VDD4在所述衬底基板上的正投影在所述第一方向X上的尺寸；所述第三延伸部4VDD3的部分结构在所述衬底基板上的正投影同样可以位于所述第二导电部在所 述衬底基板上的正投影和所述数据线Da在所述衬底基板上的正投影之间。例如，第三延伸部4VDD3的部分结构在所述衬底基板上的正投影位于第一桥接部41在衬底基板上的正投影和所述数据线Da在所述衬底基板上的正投影之间。该设置同样可以屏蔽数据线Da上数据信号对驱动晶体管栅极的噪音影响。
本示例性实施例中，第一电源线段4VDD通过过孔连接电源线5VDD，应该理解的是，在其他示例性实施例中，第一电源线段4VDD也可以连接其他稳定电压端，例如，第一电源线段4VDD也可以连接第一初始信号端、第二初始信号端等。
如图3、11、19所示，第四导电层还可以包括第一连接部46，第一连接部46连接于在所述第一方向X上相邻的两所述第一电源线段4VDD之间。在第一方向X上相连接的第一电源线段4VDD可以和电源线5VDD形成网格结构，该网格结构的电源线具有较小的电阻，从而可以降低显示面板不同位置上第一电源端之间的电压差，进而提高显示面板显示的均一性。
需要说明的是，本示例性实施例中，第一电源线段4VDD与数据线形成寄生电容的设计，以及第一电源线段4VDD屏蔽数据线对驱动晶体管栅极噪音的设计可以应用于其他任何架构的显示面板中。该设计并不限于其他膜层以及其他膜层的结构。只要显示面板包括电源线和数据线，均可以利用与电源线、数据线位于不同膜层的第一电源线段4VDD实现与数据线形成寄生电容，以及实现屏蔽数据线对驱动晶体管栅极的噪音干扰。
本示例性实施例中，第一发光单元发光所需跨压大于所述第二发光单元发光所需跨压。相应的，所述第一像素驱动电路P1中所述驱动晶体管沟道区的宽长比可以大于所述第二像素驱动电路P2中所述驱动晶体管沟道区的宽长比。例如，所述第一像素驱动电路P1中所述驱动晶体管的沟道区长度可以小于所述第二像素驱动电路P2中所述驱动晶体管的沟道区长度。该设置可以降低驱动晶体管的阻抗，从而提高发光单元L在第一电源端VDD和第二电源端VSS之间的分压。即该设置可以在相同数据信号下，使得第一发光单元两侧电压大于第二发光单元两侧的电压，该设置可以满足第一发光单元发光所需跨压大于所述第二发光单元发光所需跨压的需求。
如图3、12、20、21、22所示，图20为本公开显示面板一种示例性实施例中第五导电层和电极层的结构版图，图21为图20中第五导电层的结构版图，图22为图20中电极层的结构版图。本示例性实施例中，电极层可以包括多个电极部：第一电极部R、第二电极部B、第三电极部G，各个电极部可以通过过孔连接第六桥接部56，以连接第六晶体管T6的第二极。第一电极部R可以用于形成红色发光单元的第一电极，第二电极部B可以用于形成蓝色发光单元的第一电极，第三电极部G可以用于形成绿色发光单元的第一电极。显示面板还可以包括位于电极层背离衬底基板一侧的像素定义层，所述像素定义层上形成有用于形成发光单元的像素开口。其中，第一电极部R在衬底基板上的正投影和像素定义层上与其对应的像素开口在衬底基板上的正投影重合，第二电极部B在衬底基板上的正投影和像素定义层上与其对应的像素开口在衬底基板上的正投影重合，第三电极部G在衬底基板上的正投影和像素定义层上与其对应的像素开口在衬底基板上的正投影重合。
本示例性实施例中，各个电极部在所述衬底基板上的正投影和所述电源线5VDD在所述衬底基板上的正投影、所述数据线Da在所述衬底基板上的正投影均交叠。该设置可以使得电极部尽量多的部分位于第五导电层上，从而提高电极部的平坦度，以降低显示面板在不同视角下出现色偏的风险。本示例性实施例中，电极部在衬底基板上正投影与电源线5VDD在衬底基板上正投影交叠部分在第一方向X上的最小尺寸为L1，数据线Da在衬底基板上正投影在第一方向X上的最小尺寸可以为L2，L1可以大于L2，例如，L1/L2可以等于1.5、2、3、4等。该设置可以进一步提高电极部的平坦度。
本示例性实施例中，所述电极部可以由第一部分X1和第二部分X2组成，所述第一部分X1在所述衬底基板上的正投影和所述第二部分X2在所述衬底基板上的正投影可以沿第一方向X分布，且所述第一部分X1在所述衬底基板上的正投影在所述第一方向X上的最大尺寸等于所述第二部分X2在所述衬底基板上的正投影在所述第一方向X上的最大尺寸。第一部分X1在所述衬底基板上的正投影和所述电源线5VDD在所述衬底基板上的正投影至少部分交叠，所述第二部分X2在所述衬底基板上的正投影和所述 数据线Da在所述衬底基板上的正投影至少部分交叠。该设置可以使得电极部在第一方向X上的两侧均位于第五导电层上，从而进一步提高电极部的平坦度。
本示例性实施例中，第一发光单元可以为蓝色发光单元，第二发光单元可以为红色发光单元。此外，第二发光单元也可以为绿色发光单元。即绿色发光单元对应的像素驱动电路可以具有上述第二像素驱动电路的所有特征。
需要说明的是，如图3、18、19、20所示，画于第四导电层背离衬底基板一侧的黑色方块表示第四导电层连接面向衬底基板一侧的其他层级的过孔；画于第五导电层背离衬底基板一侧的黑色方块表示第五导电层连接面向衬底基板一侧的其他层级的过孔；画于电极层背离衬底基板一侧的黑色方块表示电极层连接面向衬底基板一侧的其他层级的过孔。该黑色方块表示过孔的位置，不同位置黑色方块所表示的不同过孔可以贯穿于不同绝缘层。
如图23所示，为图3所示显示面板沿虚线AA剖开的部分剖视图。该显示面板还可以包括第一绝缘层91、第二绝缘层92、第三绝缘层93、第四绝缘层94、第五绝缘层95、第一介电层96、钝化层97、第一平坦层98、第二平坦层99，其中，衬底基板90、遮挡层、第一绝缘层91、第一有源层、第二绝缘层92、第一导电层、第三绝缘层93、第二导电层、第四绝缘层94、第二有源层、第五绝缘层95、第三导电层、第一介电层96、第四导电层、钝化层97、第一平坦层98、第五导电层、第二平坦层99、电极层依次层叠设置。第一绝缘层91、第二绝缘层92、第三绝缘层93、第四绝缘层94、第五绝缘层95可以为单层结构或多层结构，且第一绝缘层91、第二绝缘层92、第三绝缘层93、第四绝缘层94、第五绝缘层95的材料可以为氮化硅，氧化硅，氮氧化硅中的至少一种；第一介电层96可以为氮化硅层；第一平坦层98、第二平坦层99的材料可以为有机材料，例如聚酰亚胺(PI)、聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)、硅-玻璃键合结构(SOG)等材料。衬底基板90可以包括依次层叠设置的玻璃基板、阻挡层、聚酰亚胺层，阻挡层可以为无机材料。钝化层97可以为氧化硅层。第一导电层、第二导电层、第三导电层的材料可以是钼、 铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等。第四导电层、第五导电层的材料可以包括金属材料，例如可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层。电极层可以包括氧化铟锡层、银层。第一导电层、第二导电层、第三导电层中任一导电层的方块电阻可以大于第四导电层、第五导电层中任一导电层的方块电阻。
需要说明的是，本公开中的附图比例可以作为实际工艺中的参考，但不限于此，例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图。此外，第一、第二等限定词仅用于限定不同的结构名称，其并没有特定顺序和数量的含义。在本示例性实施例中，某一结构在衬底基板上的正投影沿某一方向延伸，可以理解为该结构在衬底基板上的正投影沿该方向直线延伸或弯折延伸。晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区，并且电流能够流过漏极、沟道区以及源极。在本示例性实施例中，沟道区是指电流主要流过的区域。在本示例性实施例中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况下，“源极”及“漏极”的功能有时互相调换。因此，在本示例性实施例中，“源极”和“漏极”可以互相调换。另外，栅极还可以称为控制极。
本示例性实施例还提供一种显示装置，其中，包括上述的显示面板。该显示装置可以为手机、平板电脑、电视等显示装置。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设 计。在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (26)

  1. 一种显示面板，其中，所述显示面板包括：多个像素驱动电路，所述像素驱动电路包括驱动晶体管、第四晶体管，所述第四晶体管的第一极连接数据线，第二极连接所述驱动晶体管的第一极，栅极连接第一栅线；
    其中，多个所述像素驱动电路中包括第一像素驱动电路和第二像素驱动电路；
    所述第一像素驱动电路中所述驱动晶体管栅极的等电位结构与所述第一栅线形成的电容容量为C1，所述第二像素驱动电路中所述驱动晶体管栅极的等电位结构与所述第一栅线形成的电容容量为C2，C1不等于C2。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板还包括多个发光单元，多个所述发光单元中包括第一发光单元和第二发光单元；
    所述第一像素驱动电路用于驱动所述第一发光单元，所述第二像素驱动电路用于驱动所述第二发光单元；
    在同一驱动电流下，所述第一发光单元的亮度小于所述第二发光单元的亮度，且C1小于C2。
  3. 根据权利要求2所述的显示面板，其中，所述显示面板还包括：
    衬底基板；
    第一有源层，位于所述衬底基板的一侧，所述第一有源层包括第三有源部，所述第三有源部用于形成所述驱动晶体管的沟道区；
    第一导电层，位于所述第一有源层背离所述衬底基板的一侧，所述第一导电层包括第一导电部，所述第一导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第一导电部用于形成所述驱动晶体管的栅极；
    第二导电部，与所述第一导电部对应设置，所述第二导电部连接与其对应的所述第一导电部，所述第一像素驱动电路中所述第二导电部在所述衬底基板上的正投影和所述第一栅线在所述衬底基板上的正投影的交叠面积为S1，所述第二像素驱动电路中所述第二导电部在所述衬底基板上的正投影和所述第一栅线在所述衬底基板上的正投影的交叠面积为S2，S1小于S2。
  4. 根据权利要求3所述的显示面板，其中，所述像素驱动电路还包 括：第八晶体管，所述第八晶体管的第一极连接所述驱动晶体管的栅极，所述显示面板还包括：
    第二有源层，位于所述第一导电层背离所述衬底基板的一侧，所述第二有源层包括相连接的第八有源部和第九有源部，所述第八有源部用于形成所述第八晶体管的沟道区；
    其中，所述第九有源部连接所述第一导电部，所述第二导电部包括所述第九有源部，且所述第一像素驱动电路中所述第九有源部在所述衬底基板上的正投影和所述第一栅线在所述衬底基板上的正投影的交叠面积小于所述第二像素驱动电路中所述第九有源部在所述衬底基板上的正投影和所述第一栅线在所述衬底基板上的正投影的交叠面积。
  5. 根据权利要求3所述的显示面板，其中，所述第一导电层包括所述第一栅线，所述第一栅线在所述衬底基板上的正投影沿第一方向延伸；
    所述第一栅线包括：
    多个第一延伸部，多个所述第一延伸部在所述衬底基板上的正投影沿所述第一方向延伸且沿所述第一方向间隔分布；
    多个第二延伸部，所述第二延伸部连接于在所述第一方向上相邻的所述第一延伸部之间；
    其中，所述第一延伸部在所述衬底基板上的正投影在第二方向上的尺寸小于所述第二延伸部在所述衬底基板上的正投影在第二方向上的尺寸，所述第一方向和所述第二方向相交；
    所述第二导电部在所述衬底基板上的正投影和所述第二延伸部在所述衬底基板上的正投影至少部分交叠。
  6. 根据权利要求5所述的显示面板，其中，所述像素驱动电路还包括：第八晶体管，所述第八晶体管的第一极连接所述驱动晶体管的栅极，所述显示面板还包括：
    第二有源层，位于所述第一导电层背离所述衬底基板的一侧，所述第二有源层包括相连接的第八有源部和第九有源部，所述第八有源部用于形成所述第八晶体管的沟道区；
    其中，所述第九有源部连接所述第一导电部，所述第二导电部包括所述第九有源部，所述第九有源部在所述衬底基板上的正投影位于所述第二 延伸部在所述衬底基板上的正投影上；
    且所述第一像素驱动电路中所述第九有源部在所述衬底基板上的正投影在所述第一方向上的尺寸小于所述第二像素驱动电路中所述第九有源部在所述衬底基板上的正投影在所述第一方向上的尺寸。
  7. 根据权利要求2-6任一项所述的显示面板，其中，所述第一发光单元为蓝色发光单元，所述第二发光单元为红色发光单元或绿色发光单元。
  8. 根据权利要求1所述的显示面板，其中，多个所述像素驱动电路沿第一方向和第二方向阵列分布，所述显示面板还包括：
    衬底基板；
    第四导电层，位于所述衬底基板的一侧，所述第四导电层包括多条第一电源线段，所述第一电源线段与所述像素驱动电路对应设置，多条所述第一电源线段在所述衬底基板上的正投影沿第一方向和第二方向阵列分布且沿所述第二方向延伸，所述第一方向和所述第二方向相交，所述第一电源线段连接稳定电压源；
    第五导电层，位于所述第四导电层背离所述衬底基板的一侧，所述第五导电层包括所述数据线，所述数据线在所述衬底基板上的正投影沿所述第二方向延伸。
  9. 根据权利要求8所述的显示面板，其中，所述像素驱动电路还包括：第八晶体管，所述第八晶体管的第一极连接所述驱动晶体管的栅极，所述显示面板还包括：
    第二有源层，位于所述第四导电层和所述衬底基板之间，所述第二有源层包括第八有源部，所述第八有源部用于形成所述第八晶体管的沟道区；
    第三导电层，位于所述第二有源层和所述第四导电层之间，所述第三导电层包括第二栅线，所述第二栅线在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第八有源部在所述衬底基板上的正投影，所述第二栅线的部分结构用于形成所述第八晶体管的顶栅；
    其中，所述第一电源线段在所述衬底基板上的正投影位于相邻两所述第二栅线在所述衬底基板上的正投影之间。
  10. 根据权利要求8所述的显示面板，其中，所述显示面板还包括源极驱动电路，所述源极驱动电路的一个信号输出端连接多条所述数据线， 所述源极驱动电路的一个信号输出端在一行扫描周期内分时向多条所述数据线提供数据信号；
    所述第一电源线段包括第三延伸部，其中，所述第三延伸部在所述衬底基板上的正投影和所述数据线在所述衬底基板上的正投影至少部分交叠。
  11. 根据权利要求10所述的显示面板，其中，所述数据线在所述衬底基板上的正投影的面积为S3，所述数据线在所述衬底基板上的正投影和所述第三延伸部在所述衬底基板上的正投影的交叠面积为S4，S4/S3大于等于20％且小于等于70％。
  12. 根据权利要求8所述的显示面板，其中，所述驱动晶体管的第一极连接电源线；
    所述第四导电层还包括第一连接部，所述第一连接部连接于在所述第一方向上相邻的两所述第一电源线段之间；
    所述第五导电层还包括所述电源线，所述电源线在所述衬底基板上的正投影沿所述第二方向延伸，所述电源线用于提供所述稳定电压源。
  13. 根据权利要求8所述的显示面板，其中，所述第一电源线段还包括第四延伸部；
    所述显示面板还包括第二导电部，所述第二导电部连接所述驱动晶体管的栅极；
    所述第四延伸部在所述衬底基板上的正投影沿所述第二方向延伸且位于所述数据线在所述衬底基板上的正投影和所述第二导电部在所述衬底基板上的正投影之间。
  14. 根据权利要求13所述的显示面板，其中，所述显示面板还包括第二导电部，所述第二导电部连接所述驱动晶体管的栅极；
    所述第一电源线段还包括第三延伸部，所述第三延伸部连接所述第四延伸部，所述第三延伸部在所述衬底基板上的正投影在所述第一方向上的尺寸大于所述第四延伸部在所述衬底基板上的正投影在所述第一方向上的尺寸；
    所述第三延伸部的部分结构在所述衬底基板上的正投影位于所述第二导电部在所述衬底基板上的正投影和所述数据线在所述衬底基板上的 正投影之间。
  15. 根据权利要求1所述的显示面板，其中，所述驱动晶体管的第一极连接电源线，所述像素驱动电路还包括：第八晶体管，所述第八晶体管的第一极连接所述驱动晶体管的栅极，所述显示面板还包括：
    衬底基板；
    第二有源层，位于所述衬底基板的一侧，所述第二有源层包括有源部，所述有源部的部分结构用于形成所述第八晶体管的沟道区；
    第五导电层，位于所述第二有源层背离所述衬底基板的一侧，所述第五导电层包括所述电源线，所述电源线在所述衬底基板上的正投影覆盖所述有源部在所述衬底基板上的正投影。
  16. 根据权利要求1所述的显示面板，其中，所述驱动晶体管的第一极连接电源线，所述显示面板还包括：
    衬底基板；
    第二导电部，所述第二导电部连接所述驱动晶体管的栅极；
    第五导电层，位于所述衬底基板的一侧，所述第五导电层包括所述电源线，所述电源线在所述衬底基板上的正投影覆盖所述第二导电部在所述衬底基板上的正投影。
  17. 根据权利要求1所述的显示面板，其中，所述驱动晶体管的第一极连接电源线，所述显示面板还包括：
    衬底基板；
    第五导电层，位于所述衬底基板的一侧，所述第五导电层包括所述电源线和所述数据线，所述电源线在所述衬底基板上的正投影、所述数据线在所述衬底基板上的正投影沿第二方向延伸；
    电极层，包括多个电极部，所述电极部在所述衬底基板上的正投影和所述电源线在所述衬底基板上的正投影、所述数据线在所述衬底基板上的正投影均交叠；
    像素定义层，位于所述电极层背离所述衬底基板的一侧，所述像素定义层上形成有用于形成发光单元的像素开口，所述像素开口在所述衬底基板上的正投影和所述电极部在所述衬底基板上的正投影重合。
  18. 根据权利要求17所述的显示面板，其中，所述电极部由第一部 分和第二部分组成，所述第一部分在所述衬底基板上的正投影和所述第二部分在所述衬底基板上的正投影沿第一方向分布，且所述第一部分在所述衬底基板上的正投影在所述第一方向上的最大尺寸等于所述第二部分在所述衬底基板上的正投影在所述第一方向上的最大尺寸，所述第一方向和所述第二方向相交；
    所述第一部分在所述衬底基板上的正投影和所述电源线在所述衬底基板上的正投影至少部分交叠，所述第二部分在所述衬底基板上的正投影和所述数据线在所述衬底基板上的正投影至少部分交叠。
  19. 根据权利要求17所述的显示面板，其中，所述电极部在所述衬底基板上的正投影和所述电源线在所述衬底基板上的正投影的交叠区域在第一方向上的最小尺寸为L1，所述数据线在所述衬底基板上的正投影在所述第一方向上的最小尺寸为L2，L1大于L2。
  20. 根据权利要求1所述的显示面板，其中，所述显示面板还包括多个发光单元，多个所述发光单元中包括第一发光单元和第二发光单元；
    所述第一像素驱动电路用于驱动所述第一发光单元，所述第二像素驱动电路用于驱动所述第二发光单元；
    所述第一发光单元发光所需跨压大于所述第二发光单元发光所需跨压，所述第一像素驱动电路中所述驱动晶体管沟道区的宽长比大于所述第二像素驱动电路中所述驱动晶体管沟道区的宽长比。
  21. 根据权利要求20所述的显示面板，其中，所述第一像素驱动电路中所述驱动晶体管的沟道区长度小于所述第二像素驱动电路中所述驱动晶体管的沟道区长度。
  22. 根据权利要求1所述的显示面板，其中，所述显示面板还包括发光单元，所述像素驱动电路用于驱动所述发光单元发光，所述像素驱动电路还包括：
    第八晶体管，第一极连接所述驱动晶体管的栅极，栅极连接第二栅线；
    第一晶体管，第一极连接第一初始信号线，第二极连接所述第八晶体管的第二极，栅极连接第一复位信号线；
    第二晶体管，第一极连接所述第八晶体管的第二极，第二极连接所述驱动晶体管的第二极，栅极连接所述第一栅线；
    第五晶体管，第一极连接电源线，第二极连接所述驱动晶体管的第一极，栅极连接使能信号线；
    第六晶体管，第一极连接所述驱动晶体管的第二极，第二极连接所述发光单元的第一电极，栅极连接所述使能信号线；
    第七晶体管，第一极连接第二初始信号线，第二极连接所述发光单元的第一电极，栅极连接第二复位信号线；
    电容，连接于所述驱动晶体管的栅极和所述电源线之间。
  23. 根据权利要求22所述的显示面板，其中，所述显示面板还包括：
    衬底基板；
    第一有源层，位于所述衬底基板的一侧，所述第一有源层包括第一有源部、第二有源部、第三有源部、第四有源部、第五有源部、第六有源部、第七有源部，所述第一有源部用于形成所述第一晶体管的沟道区，所述第二有源部用于形成所述第二晶体管的沟道区，所述第三有源部用于形成所述驱动晶体管的沟道区，所述第四有源部用于形成所述第四晶体管的沟道区，所述第五有源部用于形成所述第五晶体管的沟道区，所述第六有源部用于形成所述第六晶体管的沟道区，所述第七有源部用于形成所述第七晶体管的沟道区；
    第一导电层，包括所述第一栅线、第一复位信号线、第二复位信号线、使能信号线、第一导电部，所述第一栅线、第一复位信号线、第二复位信号线、使能信号线在所述衬底基板上的正投影均沿第一方向延伸；
    其中，所述第一栅线的部分结构用于分别形成所述第二晶体管、第四晶体管的栅极，所述使能信号线的部分结构用于分别形成所述第五晶体管、第六晶体管的栅极，所述第一复位信号线的部分结构用于形成所述第一晶体管的栅极，所述第二复位信号线的部分结构用于形成所述第七晶体管的栅极，所述第一导电部用于形成所述驱动晶体管的栅极；
    第二有源层，位于所述第一导电层背离所述衬底基板的一侧，所述第二有源层包括第八有源部，所述第八有源部用于形成所述第八晶体管的沟道区；
    第三导电层，位于所述第二有源层背离所述衬底基板的一侧，所述第三导电层包括所述第二栅线，所述第二栅线的部分结构用于形成所述第八 晶体管的顶栅；
    其中，所述第一导电部在所述衬底基板上的正投影位于所述第一栅线在所述衬底基板上的正投影和所述使能信号线在所述衬底基板上的正投影之间，所述第一复位信号线在所述衬底基板上的正投影位于所述第一栅线在所述衬底基板上的正投影远离所述第一导电部在所述衬底基板上的正投影的一侧，所述第二栅线在所述衬底基板上的正投影位于所述第一复位信号线在所述衬底基板上的正投影和所述第一栅线在所述衬底基板上的正投影之间。
  24. 根据权利要求23所述的显示面板，其中，所述第一方向为行方向，所述显示面板包括多行像素驱动电路；
    相邻上一行像素驱动电路中所述第二初始信号线在衬底基板上的正投影位于本行像素驱动电路中所述第一复位信号线在所述衬底基板上的正投影和本行像素驱动电路中所述第二栅线在所述衬底基板上的正投影之间；
    相邻下一行像素驱动电路中所述第一初始信号线在所述衬底基板上的正投影位于本行像素驱动电路中所述第二复位信号线在所述衬底基板上的正投影和本行像素驱动电路中所述使能信号线在所述衬底基板上的正投影之间；
    本行像素驱动电路中所述第二复位信号线复用为相邻下一行像素驱动电路中所述第一复位信号线。
  25. 根据权利要求22所述的显示面板，其中，所述第一晶体管、第二晶体管、驱动晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管为P型晶体管，所述第八晶体管为N型晶体管。
  26. 一种显示装置，其中，所述显示装置包括权利要求1-25任一项所述的显示面板。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010161084A (ja) * 2010-04-02 2010-07-22 Casio Computer Co Ltd 表示装置及び表示装置の製造方法
CN110634884A (zh) * 2018-06-21 2019-12-31 三星显示有限公司 显示装置
KR20210083679A (ko) * 2019-12-27 2021-07-07 엘지디스플레이 주식회사 전계발광 표시장치
CN113707704A (zh) * 2021-09-02 2021-11-26 京东方科技集团股份有限公司 显示基板和显示装置
CN114122101A (zh) * 2021-11-29 2022-03-01 京东方科技集团股份有限公司 显示面板、显示装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010161084A (ja) * 2010-04-02 2010-07-22 Casio Computer Co Ltd 表示装置及び表示装置の製造方法
CN110634884A (zh) * 2018-06-21 2019-12-31 三星显示有限公司 显示装置
KR20210083679A (ko) * 2019-12-27 2021-07-07 엘지디스플레이 주식회사 전계발광 표시장치
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CN114122101A (zh) * 2021-11-29 2022-03-01 京东方科技集团股份有限公司 显示面板、显示装置

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