WO2024045037A9 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024045037A9
WO2024045037A9 PCT/CN2022/116185 CN2022116185W WO2024045037A9 WO 2024045037 A9 WO2024045037 A9 WO 2024045037A9 CN 2022116185 W CN2022116185 W CN 2022116185W WO 2024045037 A9 WO2024045037 A9 WO 2024045037A9
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WIPO (PCT)
Prior art keywords
transistor
orthographic projection
active portion
base substrate
electrode
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Application number
PCT/CN2022/116185
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English (en)
French (fr)
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WO2024045037A1 (zh
Inventor
李孟
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280002938.XA priority Critical patent/CN117957942A/zh
Priority to PCT/CN2022/116185 priority patent/WO2024045037A1/zh
Publication of WO2024045037A1 publication Critical patent/WO2024045037A1/zh
Publication of WO2024045037A9 publication Critical patent/WO2024045037A9/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel and a display device.
  • a display panel generally includes a pixel driving circuit and a light-emitting unit.
  • the pixel driving circuit is used to drive the light-emitting unit to emit light.
  • the pixel driving circuit includes a driving transistor, which provides a driving current to the light-emitting unit according to its gate voltage.
  • the gate of the driving transistor has a leakage problem, which leads to display abnormality.
  • a display panel comprising: a pixel driving circuit, the pixel driving circuit comprising a driving transistor, a first transistor, and a second transistor, the first electrode of the second transistor being connected to the gate of the driving transistor, the second electrode of the second transistor being connected to the second electrode of the driving transistor, the first electrode of the first transistor being connected to a first initial signal line, and the second electrode of the first transistor being connected to the second electrode of the second transistor; the display panel further comprising: a base substrate, a first reset signal line, a second gate line, and a first conductive portion, the orthographic projection of the first reset signal line on the base substrate extending along a first direction, and a partial structure of the first reset signal line being used to form the gate of the first transistor; the orthographic projection of the second gate line on the base substrate extending along the first direction, and a partial structure of the second gate line being used to form the gate of the second transistor; the first conductive portion being used to form the gate of the driving
  • the display panel further includes: a first active portion, a second active portion, a seventeenth active portion, a twentieth active portion, and a fifth bridging portion, wherein the orthographic projection of the first reset signal line on the substrate covers the orthographic projection of the first active portion on the substrate, and the first active portion is used to form a channel region of the first transistor; the orthographic projection of the second gate line on the substrate covers the orthographic projection of the second active portion on the substrate, and the second active portion is used to form a channel region of the second transistor; the seventeenth active portion is connected to the first active portion; the twentieth active portion is connected to the second active portion; the orthographic projection of the fifth bridging portion on the substrate extends along a second direction, the second direction intersects with the first direction, the fifth bridging portion connects the seventeenth active portion and the twentieth active portion through vias, respectively, and the orthographic projection of the fifth bridging portion on the substrate intersects with the orthographic projection of the second gate line on the substrate.
  • the display panel further includes: a first active portion, a seventeenth active portion, a third active portion, an eighteenth active portion, and a fifth bridging portion, wherein the orthographic projection of the first reset signal line on the substrate covers the orthographic projection of the first active portion on the substrate, and the first active portion is used to form a channel region of the first transistor; the seventeenth active portion is connected to the first active portion; the orthographic projection of the first conductive portion on the substrate covers the orthographic projection of the third active portion on the substrate, and the third active portion is used to form a channel region of the driving transistor; the eighteenth active portion is connected to the third active portion; the orthographic projection of the fifth bridging portion on the substrate extends along a second direction, the second direction intersects with the first direction, the fifth bridging portion connects the seventeenth active portion and the eighteenth active portion through vias, respectively, and the orthographic projection of the fifth bridging portion on the substrate intersects with the orthographic projection of the
  • the display panel also includes: a nineteenth active portion and a fourth bridging portion, the nineteenth active portion being connected to a side of the second active portion away from the twentieth active portion; a fourth bridging portion connecting the nineteenth active portion and the first conductive portion through vias respectively; wherein the orthographic projection of the fourth bridging portion on the substrate extends along the second direction and intersects with the orthographic projection of the second gate line on the substrate.
  • the display panel further comprises: a first active layer, a first conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer, wherein the first active layer is located on one side of the base substrate, the first active layer comprises a first active portion, a third active portion, a seventeenth active portion, and an eighteenth active portion, the first active portion is used to form a channel region of the first transistor, the third active portion is used to form a channel region of the driving transistor, the seventeenth active portion is connected to the first active portion, and the eighteenth active portion is connected to the third active portion; the first conductive layer is located on a side of the first active layer away from the base substrate, the first conductive layer comprises the first reset signal line and the first conductive portion; the second active layer is located on a side of the first conductive layer away from the base substrate, the second active layer comprises a second active portion, a nineteenth active portion, and a twentieth active portion, the second active portion is used to
  • the pixel driving circuit further includes a fourth transistor, a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to a first electrode of the driving transistor;
  • the display panel further includes: a first active layer and a second active layer, the first active layer is located on one side of the substrate, the first active layer includes a third active portion and a fourth active portion, the third active portion is used to form a channel region of the driving transistor, and the fourth active portion is used to form a channel region of the fourth transistor;
  • the second active layer is located on a side of the first active layer away from the substrate, the second active layer includes a second active portion, the orthographic projection of the second gate line on the substrate covers the orthographic projection of the second active portion on the substrate, and the second active portion is used to form a channel region of the second transistor; wherein, in the first direction, the orthographic projection of the third active portion on the substrate is located between the orthographic projection of the second active portion on the substrate and the ortho
  • the pixel driving circuit also includes a fourth transistor, a first electrode of the fourth transistor is connected to the data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor;
  • the display panel also includes: a first conductive layer, the first conductive layer is located on one side of the base substrate, the first conductive layer includes a first gate line, the orthographic projection of the first gate line on the base substrate extends along the first direction and is located between the orthographic projection of the first reset signal line on the base substrate and the orthographic projection of the second gate line on the base substrate, and a partial structure of the first gate line is used to form a gate of the fourth transistor; wherein the orthographic projection of the nineteenth active portion on the base substrate at least partially overlaps with the orthographic projection of the first gate line on the base substrate.
  • a maximum dimension of an orthographic projection of the nineteenth active portion on the base substrate in the first direction is greater than a maximum dimension of an orthographic projection of the nineteenth active portion on the base substrate in the second direction.
  • the maximum dimension of the orthographic projection of the nineteenth active portion on the base substrate in the first direction is L1
  • the maximum dimension of the orthographic projection of the nineteenth active portion on the base substrate in the second direction is L2
  • L1/L2 is greater than or equal to 1.5 and less than or equal to 5.
  • the pixel driving circuit also includes a fourth transistor, a first electrode of the fourth transistor is connected to the data line, a second electrode of the fourth transistor is connected to the first electrode of the driving transistor, and a gate of the fourth transistor is connected to the first gate line; wherein the capacitance formed by the equipotential structure of the first conductive portion and the equipotential structure of the first gate line is C1, and the capacitance formed by the equipotential structure of the first conductive portion and the equipotential structure of the second gate line is C2, and C1 is greater than C2.
  • the display panel further includes: a second active portion, a nineteenth active portion, and a fourth bridging portion, wherein the second active portion is used to form a channel region of the second transistor; the nineteenth active portion is connected to the second active portion, and the orthographic projection of the nineteenth active portion on the substrate substrate and the orthographic projection of the first gate line on the substrate substrate at least partially overlap; a fourth bridging portion, wherein the fourth bridging portion connects the nineteenth active portion and the first conductive portion through vias, respectively, and the orthographic projection of the fourth bridging portion on the substrate substrate extends along the second direction and at least partially overlaps with the orthographic projection of the second gate line on the substrate substrate; wherein the overlapping area of the orthographic projection of the nineteenth active portion on the substrate substrate and the orthographic projection of the first gate line on the substrate substrate is S1, and the overlapping area of the orthographic projection of the fourth bridging portion on the substrate substrate and the orthographic projection of the second gate line on the substrate substrate is S2; S
  • the display panel also includes a light-emitting unit, the pixel driving circuit is used to drive the light-emitting unit to emit light, and the pixel driving circuit also includes a seventh transistor, the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode is connected to the first electrode of the light-emitting unit;
  • the display panel also includes: a fourth conductive layer, the fourth conductive layer is located on one side of the base substrate, and the fourth conductive layer includes the second initial signal line; wherein the second initial signal line includes a first sub-initial signal line and a second sub-initial signal line, the orthographic projection of the first sub-initial signal line on the base substrate extends along the first direction, and the orthographic projection of the second sub-initial signal line on the base substrate extends along the second direction, and the second direction intersects with the first direction; the first sub-initial signal line is connected to the second sub-initial signal line intersecting with its orthographic projection on the
  • the pixel driving circuit also includes a fifth transistor, a first electrode of the fifth transistor is connected to a power line, and a second electrode is connected to the first electrode of the driving transistor;
  • the display panel also includes: a fourth conductive layer and a fifth conductive layer, the fifth conductive layer is located on a side of the fourth conductive layer away from the base substrate, and the fifth conductive layer includes the power line; a first notch is formed on the power line, and the first notch is at least partially located in a light-transmitting area of the display panel.
  • the orthographic projection of the power line on the substrate extends along a second direction, and the second direction intersects the first direction;
  • the power line includes a first power line segment, a second power line segment, and a third power line segment, and the second power line segment is connected between the first power line segment and the third power line segment;
  • the size of the orthographic projection of the second power line segment on the substrate in the first direction is larger than the size of the orthographic projection of the first power line segment on the substrate in the first direction, and the size of the orthographic projection of the second power line segment on the substrate in the first direction is larger than the size of the orthographic projection of the third power line segment on the substrate in the first direction;
  • the first notch includes a first side edge and a second side edge, and the angle formed by the orthographic projection of the first side edge on the substrate and the orthographic projection of the second side edge on the substrate is less than 90°; and the first side edge is formed by a partial edge of the second power line segment, and the second side edge is formed by
  • the pixel driving circuit also includes a capacitor, a first electrode of the capacitor is connected to the gate of the driving transistor, a second electrode of the capacitor is connected to a power line, and the first conductive portion is multiplexed as the first electrode of the capacitor;
  • the display panel also includes: a first conductive layer, a second active layer, and a second conductive layer, the first conductive layer is located on one side of the base substrate; the second active layer is located on a side of the first conductive layer away from the base substrate; the second conductive layer is located between the first conductive layer and the second active layer, the second conductive layer includes a second conductive portion, an orthographic projection of the second conductive portion on the base substrate at least partially overlaps with an orthographic projection of the first conductive portion on the base substrate, and the second conductive portion is used to form the second electrode of the capacitor; wherein at least part of the second conductive portions adjacent in the first direction are connected.
  • the display panel includes repeating units distributed in an array along the first direction and the second direction, the first direction and the second direction intersect, the repeating unit includes two pixel driving circuits distributed in the first direction, and the two pixel driving circuits in the same repeating unit are at least partially mirror-symmetrically arranged;
  • the second conductive layer also includes: a first connecting portion, the first connecting portion is connected between two second conductive portions in the same repeating unit, the size of the orthographic projection of the first connecting portion on the substrate in the second direction is smaller than the size of the orthographic projection of the second conductive portion on the substrate in the second direction, the first connecting portion and the second conductive portion connected thereto form a third notch; the orthographic projection of the third notch on the substrate at least partially overlaps with the orthographic projection of the equipotential structure of the second pole of the driving transistor on the substrate.
  • the display panel includes repeating units distributed in an array along the first direction and the second direction, the first direction and the second direction intersect, the repeating unit includes two pixel driving circuits distributed in the first direction, and the two pixel driving circuits in the same repeating unit are at least partially mirror-symmetrically arranged; a plurality of second gate lines are connected to the same signal terminal; the second conductive layer also includes: a second connecting portion, the second connecting portion is connected between two adjacent second conductive portions in the repeating units adjacent to each other in the first direction, the size of the orthogonal projection of the second connecting portion on the substrate in the second direction is smaller than the size of the orthogonal projection of the second conductive portion on the substrate in the second direction, the second connecting portion and the second conductive portion connected thereto form a second notch; the orthogonal projection of the second notch on the substrate at least partially overlaps with the orthogonal projection of the equipotential structure of the first pole of the driving transistor on the substrate.
  • the display panel further includes a light-emitting unit, the pixel driving circuit is used to drive the light-emitting unit to emit light, the pixel driving circuit further includes a seventh transistor and an eighth transistor, the first electrode of the seventh transistor is connected to the second initial signal line, the second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit, the first electrode of the eighth transistor is connected to the third initial signal line, and the second electrode of the eighth transistor is connected to the first electrode of the driving transistor; the display panel further includes: a first conductive layer and a third conductive layer, the first conductive layer is located on one side of the base substrate, the first conductive layer includes a second reset signal line, the orthographic projection of the second reset signal line on the base substrate extends along the first direction, and a part of the structure of the second reset signal line is used to form a gate of the seventh transistor; the third conductive layer is located on a side of the first conductive layer away from the base substrate, the third conductive layer
  • the display panel also includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light.
  • the pixel driving circuit also includes: a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a capacitor.
  • the first electrode of the fourth transistor is connected to the data line, and the second electrode is connected to the first electrode of the driving transistor; the first electrode of the fifth transistor is connected to the power line, and the second electrode is connected to the first electrode of the driving transistor; the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light-emitting unit; the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode is connected to the first electrode of the light-emitting unit; the first electrode of the eighth transistor is connected to the third initial signal line, and the second electrode is connected to the first electrode of the driving transistor; the capacitor is connected between the gate of the driving transistor and the power line; the display panel also includes: a first active layer, a first conductive layer, a second active layer, and a third conductive layer.
  • the first active layer includes a first active portion, a third active portion, a fourth active portion, a fifth active portion, a sixth active portion, a seventh active portion, and an eighth active portion, wherein the first active portion is used to form a channel region of the first transistor, the third active portion is used to form a channel region of the driving transistor, the fourth active portion is used to form a channel region of the fourth transistor, the fifth active portion is used to form a channel region of the fifth transistor, the sixth active portion is used to form a channel region of the sixth transistor, the seventh active portion is used to form a channel region of the seventh transistor, and the eighth active portion is used to form a channel region of the eighth transistor; the first conductive layer is located on a side of the first active layer away from the substrate, the first conductive layer includes the first reset signal line, a first gate line, a second reset signal line, an enable signal line, and a first conductive portion, a partial structure of the first gate line is used to form a gate of the fourth transistor, a partial structure of
  • the second active layer is located on the side of the first conductive layer away from the substrate, the second active layer includes a second active portion, and the second active portion is used to form the channel region of the second transistor;
  • the third conductive layer is located on the side of the second active layer away from the substrate, and the third conductive layer includes the second gate line; wherein the orthographic projection of the enable signal line on the substrate extends along the first direction and is located on the side where the orthographic projection of the first conductive portion on the substrate is away from the orthographic projection of the first reset signal line on the substrate;
  • the orthographic projection of the first gate line on the substrate extends along the first direction and is located between the orthographic projection of the second gate line on the substrate and the orthographic projection of the first reset signal line on the substrate;
  • the orthographic projection of the second reset signal line on the substrate extends along the first direction and is located on the side where the orthographic projection of the enable signal line on the substrate is away from the orthographic projection
  • the first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type transistors
  • the second transistor is an N-type transistor.
  • a display device comprising the above-mentioned display panel.
  • FIG1 is a schematic diagram of a circuit structure of a pixel driving circuit in an exemplary embodiment of a display panel disclosed herein;
  • FIG2 is a timing diagram of signals at each node in the pixel driving circuit shown in FIG1 ;
  • FIG3 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;
  • FIG4 is a structural diagram of the shielding layer in FIG3 ;
  • FIG5 is a structural diagram of the first active layer in FIG3;
  • FIG6 is a structural diagram of the first conductive layer in FIG3 ;
  • FIG7 is a structural diagram of the second conductive layer in FIG3 ;
  • FIG8 is a structural diagram of the second active layer in FIG3;
  • FIG9 is a structural diagram of the third conductive layer in FIG3 ;
  • FIG10 is a structural diagram of the fourth conductive layer in FIG3 ;
  • FIG11 is a structural diagram of the fifth conductive layer in FIG3 ;
  • FIG12 is a structural diagram of the electrode layer in FIG3 ;
  • FIG13 is a structural layout diagram of the shielding layer and the first active layer in FIG3 ;
  • FIG14 is a structural layout diagram of the shielding layer, the first active layer, and the first conductive layer in FIG3 ;
  • FIG15 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, and the second conductive layer in FIG3;
  • FIG16 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG3 ;
  • FIG17 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG3;
  • FIG18 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG3 ;
  • FIG19 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in FIG3 ;
  • FIG20 is a partial cross-sectional view of the display panel shown in FIG3 taken along the dotted line AA;
  • FIG21 is a schematic structural diagram of a fifth conductive layer in another exemplary embodiment of the display panel of the present disclosure.
  • FIG. 22 is a schematic diagram of the structure of the fourth conductive layer in another exemplary embodiment of the display panel disclosed herein.
  • FIG. 1 is a circuit structure diagram of a pixel driving circuit in an exemplary embodiment of the display panel disclosed in the present invention.
  • the pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C.
  • the first electrode of the second transistor T2 is connected to the gate of the driving transistor T3, the second electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the second gate driving signal terminal G2;
  • the first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, the second electrode is connected to the second electrode of the second transistor T2, and the gate is connected to the first reset signal terminal Re1;
  • the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the first gate driving signal terminal G1;
  • the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM,
  • the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM;
  • the first electrode of the seventh transistor T7 is connected to the second initial
  • the pixel driving circuit can be used to drive the light emitting unit L to emit light, wherein the first electrode of the light emitting unit L is connected to the second electrode of the sixth transistor T6, and the second electrode of the light emitting unit L is connected to the second power supply terminal VSS.
  • the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can all be P-type transistors
  • the second transistor T2 can be an N-type transistor.
  • FIG2 it is a timing diagram of signals on each node in the pixel driving circuit shown in FIG1.
  • EM represents the timing diagram of the signal on the enable signal terminal
  • G1 represents the timing diagram of the signal on the first gate driving signal terminal
  • G2 represents the timing diagram of the signal on the second gate driving signal terminal
  • Re1 represents the timing diagram of the signal on the first reset signal terminal
  • Re2 represents the timing diagram of the signal on the second reset signal terminal.
  • the driving method of the pixel driving circuit in the present disclosure may include a scanning frame Ft and a holding frame St.
  • the scanning frame Ft may include: a first reset stage t1, a second reset stage t2, a third reset stage t3, a data writing stage t4, and a light emitting stage t5.
  • the first reset stage t1 the second gate driving signal terminal G2 outputs a high level signal
  • the second reset signal terminal Re2 outputs a low level signal
  • the second transistor T2 the seventh transistor T7, and the eighth transistor T8 are turned on
  • the second initial signal terminal Vinit2 inputs the second initial signal to the first electrode of the light emitting unit L
  • the third initial signal terminal Vinit3 inputs the third initial signal to the first electrode of the driving transistor.
  • the driving transistor T3 can be turned on, and the third initial signal terminal Vinit3 writes a reset signal Vinit3+Vth to the gate of the driving transistor, wherein Vinit3 is the voltage of the third initial signal, and Vth is the threshold voltage of the driving transistor T3; in the second reset stage t2: the second gate driving signal terminal G2 outputs a high level signal, the first reset signal terminal Re1 outputs a low level signal, the first transistor T1 and the second transistor T2 are turned on, and the first initial signal terminal Vinit1 inputs the gate of the driving transistor T3.
  • the second gate drive signal terminal G2 outputs a high level signal, the first reset signal terminal Re1 outputs a low level signal, the first transistor T1 and the second transistor T2 are turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to the gate of the driving transistor T3;
  • the data writing stage t4 the first gate drive signal terminal G1 outputs a low level signal, the second gate drive signal terminal G2 outputs a high level signal, the second transistor T2 and the fourth transistor T4 are turned on, and the data signal terminal Da outputs a data signal to write a compensation voltage Vdata+Vth to the gate of the driving transistor, wherein Vdata is the voltage of the data signal, and Vth is the threshold voltage of the driving transistor T3;
  • the enable signal terminal EM outputs a low level signal, the fifth transistor T5 and the sixth transistor T6 are turned on, and the driving transistor T3 drives the light-emitting unit L to emit light
  • the driving transistor output current formula I ( ⁇ WCox/2L)(Vgs-Vth) 2 , ⁇ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor.
  • the pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.
  • the gate of the driving transistor T3 is connected to the first initial signal terminal through the second transistor T2 and the first transistor T1, so that the leakage current of the driving transistor T3 to the first initial signal terminal during the light-emitting stage can be reduced.
  • the third initial signal terminal inputs a reset signal to the gate of the driving transistor and inputs a third initial signal to the first electrode of the driving transistor. This setting can restore the hysteresis of the driving transistor T3 caused by the bias of the previous frame, and solve the problem of dim brightness in the first frame.
  • the timing of the first reset signal terminal, the second reset signal terminal, and the enable signal terminal in the hold frame St can be the same as their timing in the scan frame.
  • This setting can make the driving transistor have the same hysteresis state in the scan frame and the hold frame to improve the display panel flickering problem caused by the different brightness of adjacent frames.
  • the pixel driving circuit may also have other driving methods, and the present application does not limit the driving method of the pixel driving circuit.
  • the display panel may include a base substrate, a shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and an electrode layer, which are sequentially stacked, wherein an insulating layer may be provided between the above adjacent layers.
  • Figure 3 is a structural layout diagram of an exemplary embodiment of the display panel disclosed in the present disclosure
  • Figure 4 is a structural layout diagram of the shielding layer in Figure 3
  • Figure 5 is a structural layout diagram of the first active layer in Figure 3
  • Figure 6 is a structural layout diagram of the first conductive layer in Figure 3
  • Figure 7 is a structural layout diagram of the second conductive layer in Figure 3
  • Figure 8 is a structural layout diagram of the second active layer in Figure 3
  • Figure 9 is a structural layout diagram of the third conductive layer in Figure 3
  • Figure 10 is a structural layout diagram of the fourth conductive layer in Figure 3
  • Figure 11 is a structural layout diagram of the fifth conductive layer in Figure 3
  • Figure 12 is a structural layout diagram of the electrode layer in Figure 3
  • Figure 13 is a structural layout diagram of the shielding layer and the first active layer in Figure 3
  • Figure 14 is a structural layout diagram of the shielding layer, the first active layer, and the first conductive layer in Figure 3.
  • FIG 15 is a structural layout of the shielding layer, the first active layer, the first conductive layer, and the second conductive layer in FIG3
  • FIG16 is a structural layout of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG3
  • FIG17 is a structural layout of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG3
  • FIG18 is a structural layout of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG3,
  • FIG19 is a structural layout of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in FIG3.
  • the display panel may include a plurality of pixel drive circuits shown in FIG1.
  • the plurality of pixel driving circuits may include a first pixel driving circuit P1 and a second pixel driving circuit P2 adjacently distributed in a first direction X, and at least a portion of the structure of the first pixel driving circuit P1 and the second pixel driving circuit P2 may be arranged in mirror symmetry with respect to a mirror symmetry plane BB.
  • the mirror symmetry plane BB may be perpendicular to the substrate.
  • the first pixel driving circuit P1 and the second pixel driving circuit P2 may form a repeating unit, and the display panel may include a plurality of repeating units arranged in an array in the first direction X and the second direction Y.
  • the second direction Y and the first direction X may intersect, for example, the first direction X may be a row direction, and the second direction Y may be a column direction.
  • the blocking layer may include a plurality of blocking parts 71, connecting parts 73 and connecting parts 72, wherein the orthographic projection of the connecting part 73 on the base substrate extends along the second direction Y and is connected between adjacent blocking parts 71 in the second direction Y; the orthographic projection of the connecting part 72 on the base substrate extends along the first direction X and is connected between adjacent blocking parts 71 in the first direction X.
  • the first active layer may include a first active portion 61, a third active portion 63, a fourth active portion 64, a fifth active portion 65, a sixth active portion 66, a seventh active portion 67, and an eighth active portion 68.
  • the first active portion 61 is used to form a channel region of the first transistor T1
  • the third active portion 63 is used to form a channel region of the driving transistor T3
  • the fourth active portion 64 is used to form a channel region of the fourth transistor T4
  • the fifth active portion 65 is used to form a channel region of the fifth transistor T5
  • the sixth active portion 66 is used to form a channel region of the sixth transistor T6
  • the seventh active portion 67 is used to form a channel region of the seventh transistor T7
  • the eighth active portion 68 is used to form a channel region of the eighth transistor T8.
  • the first active layer may further include a ninth active portion 69 , a tenth active portion 610 , an eleventh active portion 611 , a twelfth active portion 612 , a thirteenth active portion 613 , a fourteenth active portion 614 , a fifteenth active portion 615 , a sixteenth active portion 616 , a seventeenth active portion 617 , and an eighteenth active portion 618 .
  • the ninth active portion 69 is connected to one end of the fourth active portion 64 away from the third active portion 63; the tenth active portion 610 is connected to one end of the fifth active portion 65 away from the third active portion 63, wherein, in the adjacent repeating units in the first direction X, the adjacent fifth active portions 65 are connected through the tenth active portion 610; the eleventh active portion 611 is connected between the fifth active portion 65 and the third active portion 63; the twelfth active portion 612 is connected to one end of the seventh active portion 67 away from the sixth active portion 66; the thirteenth active portion 613 and the fourteenth active portion 614 are respectively connected to the eighth active portion 68
  • the fifteenth active portion 615 is connected between the sixth active portion 66 and the seventh active portion 67; the sixteenth active portion 616 and the seventeenth active portion 617 are connected to the two ends of the first active portion 61, wherein, in the same repeating unit, two adjacent first active portions 61 are connected through the sixteenth active portion 616; the eighteen
  • the orthographic projection of the shielding portion 71 on the substrate can cover the orthographic projection of the third active portion 63 on the substrate, and the shielding portion 71 can shield the third active portion 63 from light to reduce the influence of light on the driving characteristics of the driving transistor T3.
  • the shielding layer can be a conductive material, and the shielding layer can also be connected to a stable voltage source to shield the driving transistor T3 from noise.
  • the shielding layer can be connected to the first power supply terminal VDD, the first initial signal terminal Vinit1, the second initial signal terminal Vinit2, the third initial signal terminal Vinit3, the second power supply terminal VSS, etc.
  • the first active layer can be formed of polysilicon material, and accordingly, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type low-temperature polysilicon thin film transistors.
  • the first conductive layer may include a first reset signal line Re1, a first gate line G1, an enable signal line EM, a second reset signal line Re2, and a first conductive portion 11.
  • the orthographic projections of the first reset signal line Re1, the first gate line G1, the enable signal line EM, and the second reset signal line Re2 on the substrate may extend along the first direction X.
  • the first reset signal line Re1 may be used to provide the first reset signal terminal in FIG. 1.
  • the orthographic projection of the first reset signal line Re1 on the substrate may cover the orthographic projection of the first active portion 61 on the substrate, and a partial structure of the first reset signal line Re1 may be used to form the gate of the first transistor T1.
  • the first gate line G1 may be used to provide the first gate drive signal terminal in FIG. 1.
  • the orthographic projection of the first gate line G1 on the substrate may cover the orthographic projection of the fourth active portion 64 on the substrate.
  • a partial structure of the first gate line G1 may be used to form the gate of the fourth transistor T4.
  • the enable signal line EM is used to provide the enable signal terminal in FIG. 1 .
  • the orthographic projection of the enable signal line EM on the substrate can cover the orthographic projection of the fifth active portion 65 on the substrate and the orthographic projection of the sixth active portion 66 on the substrate. Part of the structure of the enable signal line EM can be used to form the gate of the fifth transistor T5, and another part of the structure of the enable signal line EM can be used to form the gate of the sixth transistor T6.
  • the second reset signal line Re2 is used to provide the second reset signal terminal in FIG. 1 .
  • the orthographic projection of the second reset signal line Re2 on the substrate can cover the orthographic projection of the seventh active portion 67 on the substrate. Part of the structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7.
  • the orthographic projection of the first conductive portion 11 on the substrate can cover the orthographic projection of the third active portion 63 on the substrate.
  • the first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C.
  • the orthographic projection of the first reset signal line Re1 on the substrate, the orthographic projection of the first gate line G1 on the substrate, the orthographic projection of the first conductive portion 11 on the substrate, the orthographic projection of the enable signal line EM on the substrate, and the orthographic projection of the second reset signal line Re2 on the substrate can be sequentially distributed along the second direction Y.
  • the display panel can use the first conductive layer as a mask to perform conductor processing on the first active layer, that is, the area of the first active layer covered by the first conductive layer can form a channel region of the transistor, and the area of the first active layer not covered by the first conductive layer forms a conductor structure.
  • the second conductive layer may include a third gate line 2G2, a first initial signal line Vinit1, and a second conductive portion 22.
  • the orthographic projection of the first initial signal line Vinit1 on the substrate substrate and the orthographic projection of the third gate line 2G2 on the substrate substrate may both extend along the first direction X.
  • the first initial signal line Vinit1 is used to provide the first initial signal terminal in Figure 1
  • the third gate line 2G2 is used to provide the second gate drive signal terminal in Figure 1.
  • the orthographic projection of the second conductive portion 22 on the substrate substrate may overlap with the orthographic projection of the first conductive portion 11 on the substrate substrate, and the second conductive portion 22 may be used to form the second electrode of the capacitor C.
  • the first initial signal line Vinit1 may also be located in other conductive layers, for example, the first initial signal line Vinit1 may also be located in a shielding layer, a third conductive layer, a fourth conductive layer, etc.
  • the second conductive layer also includes a first connecting portion 23 and a second connecting portion 24, the first connecting portion 23 is connected between two second conductive portions 22 in the same repeating unit, and the second connecting portion 24 is connected between two adjacent second conductive portions 22 in adjacent repeating units in the first direction X.
  • An opening 221 is further formed on the second conductive portion 22 .
  • the second active layer may include a plurality of active portions 8, the active portion 8 includes a second active portion 82, a nineteenth active portion 819, and a twentieth active portion 820, the second active portion 82 is connected between the nineteenth active portion 819 and the twentieth active portion 820, and the second active portion 82 is used to form the channel region of the second transistor.
  • the orthographic projection of the third gate line 2G2 on the substrate can cover the orthographic projection of the second active portion 82 on the substrate, and a partial structure of the third gate line 2G2 can be used to form the bottom gate of the second transistor T2.
  • the orthographic projection of the third active portion 63 on the substrate is located between the orthographic projection of the second active portion 82 on the substrate and the orthographic projection of the fourth active portion 64 on the substrate.
  • the second active layer can be formed of indium gallium zinc oxide, and accordingly, the second transistor T2 can be an N-type metal oxide thin film transistor.
  • the third conductive layer may include: a second gate line 3G2, a third initial signal line Vinit3, and the orthographic projection of the second gate line 3G2 on the substrate substrate and the orthographic projection of the third initial signal line Vinit3 on the substrate substrate may extend along the first direction X.
  • the second gate line 3G2 is used to provide the second gate drive signal terminal in Figure 1, and the orthographic projection of the second gate line 3G2 on the substrate substrate may cover the orthographic projection of the second active portion 82 on the substrate substrate, and a partial structure of the second gate line 3G2 may be used to form the top gate of the second transistor T2.
  • the second gate line 3G2 and the third gate line 2G2 in the same row of pixel driving circuits may be connected through vias, and the vias connected between the second gate line 3G2 and the third gate line 2G2 may be located in an edge routing area outside the display area of the display panel.
  • the third initial signal line Vinit3 may be used to provide the third initial signal terminal in Figure 1, and the orthographic projection of the third initial signal line Vinit3 on the substrate substrate may overlap with the orthographic projection of the second reset signal line Re2 on the substrate substrate, and this arrangement may improve the transmittance of the display panel.
  • the display panel can use the third conductive layer as a mask to conduct the second active layer, that is, the area of the second active layer covered by the third conductive layer can form the channel region of the transistor, and the area of the second active layer not covered by the third conductive layer forms a conductor structure.
  • the fourth conductive layer may include: a second initial signal line Vinit2, a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, a seventh bridge portion 47, and an eighth bridge portion 48.
  • the second initial signal line Vinit2 may be used to provide the second initial signal terminal in FIG. 1.
  • the second initial signal line Vinit2 may include a first sub-initial signal line Vinit21 and a second sub-initial signal line Vinit22.
  • the orthographic projection of the first sub-initial signal line Vinit21 on the substrate extends along the first direction X
  • the orthographic projection of the second sub-initial signal line Vinit22 on the substrate extends along the second direction Y
  • the orthographic projection of the first sub-initial signal line Vinit21 on the substrate intersects with the orthographic projection of the second sub-initial signal line Vinit22 on the substrate.
  • a first sub-initial signal line Vinit21 may be correspondingly provided for each row of pixel driving circuits
  • a second sub-initial signal line Vinit22 may be correspondingly provided for each column of repeating units.
  • the first sub-initial signal line Vinit21 and the second sub-initial signal line Vinit22 can form a grid structure, which can reduce the self-resistance of the second initial signal line, thereby reducing the voltage difference of the second initial signal terminal at different positions of the display panel.
  • the second initial signal line Vinit2 can be connected to the twelfth active part 612 through the via H to connect the second initial signal terminal and the first pole of the seventh transistor T7.
  • the black square represents the position of the via.
  • the adjacent insulating layer on the side of the fourth conductive layer facing the substrate substrate will have a convex structure at the position where the third gate line 2G2 and the second gate line 3G2 are located, which can easily cause the second sub-initial signal line Vinit22 to break.
  • the third gate line 2G2 and the second gate line 3G2 both include two side edges extending along the first direction X, and the orthographic projection of the second sub-initial signal line Vinit2 on the substrate substrate substrate and the orthographic projection of the two side edges of the third gate line 2G2 on the substrate substrate are perpendicular or nearly perpendicular.
  • the orthographic projection of the second sub-initial signal line Vinit2 on the substrate substrate and the orthographic projection of the two side edges of the third gate line 2G2 on the substrate substrate are both greater than or equal to 80° and less than or equal to 100°.
  • the orthographic projection of the second sub-initial signal line Vinit2 on the substrate substrate and the orthographic projection of the two side edges of the third gate line 2G2 on the substrate substrate can be equal to 80°, 90°, 100°, etc.
  • the orthographic projection of the second sub-initial signal line Vinit2 on the substrate substrate is perpendicular or nearly perpendicular to the orthographic projection of the two side edges of the second gate line 3G2 on the substrate substrate.
  • the angle between the orthographic projection of the second sub-initial signal line Vinit2 on the substrate substrate and the orthographic projection of the two side edges of the second gate line 3G2 on the substrate substrate is greater than or equal to 80° and less than or equal to 100°.
  • the angle between the orthographic projection of the second sub-initial signal line Vinit2 on the substrate substrate and the orthographic projection of the two side edges of the second gate line 3G2 on the substrate substrate can be equal to 80°, 90°, 100°, etc. This setting can reduce the risk of the second sub-initial signal line Vinit2 breaking.
  • the orthographic projection on the substrate substrate intersects the partial side of the third gate line 2G2 of the second sub-initial signal line Vinit22 and the orthographic projection on the substrate substrate intersects the partial side of the third gate line 2G2 of the second sub-initial signal line Vinit22 on the substrate substrate do not overlap, and the setting can make the adjacent insulating layer of the fourth conductive layer facing the substrate substrate side form a slope at the location of the third gate line 2G2 and the second gate line 3G2, so that the setting can also reduce the risk of the second sub-initial signal line Vinit2 breaking.
  • the first bridge portion 41 can be connected to the sixteenth active portion 616 and the first initial signal line Vinit1 through a via hole, respectively, to connect the first pole and the first initial signal end of the first transistor T1.
  • the second bridge portion 42 can be connected to the ninth active portion 69 through a via hole to connect the first pole of the fourth transistor T4.
  • the third bridge portion 43 can be connected to the second connecting portion 24 and the tenth active portion 610 through a via hole, respectively, to connect the first pole of the fifth transistor T5 and the second electrode of the capacitor.
  • the fourth bridge portion 44 can be connected to the nineteenth active portion 819 and the first conductive portion 11 through vias, respectively, to connect the first electrode of the second transistor T2 and the gate of the driving transistor T3.
  • the orthographic projection of the via connected between the first conductive portion 11 and the fourth bridge portion 44 on the substrate substrate is located within the orthographic projection of the opening 221 on the substrate substrate, so that the via connected between the first conductive portion 11 and the fourth bridge portion 44 is insulated from the second conductive portion 22.
  • the orthographic projection of the fourth bridge portion 44 on the substrate substrate can extend along the second direction Y and intersect with the orthographic projection of the second gate line 3G2 on the substrate substrate.
  • the fifth bridge portion 45 can be connected to the seventeenth active portion 617, the eighteenth active portion 618, and the twentieth active portion 820 through vias, respectively, to connect the second electrode of the first transistor T1, the second electrode of the driving transistor T3, and the second electrode of the second transistor T2.
  • the orthographic projection of the fifth bridge portion 45 on the substrate substrate can overlap at least partially with the orthographic projection of the active portion 8 on the substrate substrate, and this arrangement can provide the transmittance of the display panel.
  • the orthographic projection of the fifth bridge portion 45 on the substrate substrate may extend along the second direction Y and intersect with the orthographic projection of the second gate line 3G2 on the substrate substrate.
  • the sixth bridge portion 46 may be connected to the eleventh active portion 611 and the fourteenth active portion 614 through vias, respectively, to connect the second pole of the eighth transistor and the first pole of the driving transistor T3.
  • the seventh bridge portion 47 may be connected to the fifteenth active portion 615 through vias to connect the second pole of the sixth transistor.
  • the eighth bridge portion 48 may be connected to the thirteenth active portion 613 and the third initial signal line Vinit3 through vias, respectively, to connect the first pole and the third initial signal end of the eighth transistor T8.
  • the second initial signal line Vinit2 may also be located in other conductive layers, for example, the second initial signal line Vinit2 may be located in a shielding layer, a second conductive layer, a third conductive layer, etc.; the second initial signal line Vinit2 may also include only the first sub-initial signal line Vinit21 or the second sub-initial signal line Vinit22.
  • multiple second gate lines 3G2 in multiple rows of pixel driving circuits can be provided with second gate drive signals by the same signal terminal.
  • two second gate lines 3G2 in adjacent odd-even pixel driving circuit rows can be provided with second gate drive signals by the same-level shift register unit in the gate driving circuit.
  • the equipotential structure of the first pole of the driving transistor T3 forms a parasitic capacitance with other conductive structures, and after the fourth transistor T4 is turned off, the equipotential structure of the first pole of the driving transistor T3 can continue to write a compensation voltage to the gate of the driving transistor.
  • the two rows of pixel driving circuits need to turn on the second transistor T2 during the data writing stage. Therefore, the duration of the upper row of pixel driving circuits writing the compensation voltage to the gate of the driving transistor through the equipotential structure of the first pole of the driving transistor T3 is longer than the duration of the adjacent next row of pixel driving circuits writing the compensation voltage to the gate of the driving transistor through the equipotential structure of the first pole of the driving transistor T3. Thereby causing display differences between adjacent sub-pixel rows of the display panel.
  • the size of the orthographic projection of the second connection portion 24 on the substrate in the second direction Y is smaller than the size of the orthographic projection of the second conductive portion 22 on the substrate in the second direction Y.
  • a second notch 25 is formed between the second connection portion 24 and the second conductive portion 22.
  • the orthographic projection of the second notch 25 on the substrate overlaps with the orthographic projection of the first pole equipotential structure of the driving transistor T3 on the substrate.
  • the orthographic projection of the second notch 25 on the substrate overlaps with the orthographic projection of the sixth bridge portion 46 on the substrate and the orthographic projection of the eleventh active portion 611 on the substrate.
  • the size of the orthographic projection of the first connection portion 23 on the substrate substrate in the second direction Y is smaller than the size of the orthographic projection of the second conductive portion 22 on the substrate substrate in the second direction Y.
  • a third notch 26 is formed between the first connection portion 23 and the second conductive portion 22, and the orthographic projection of the third notch 26 on the substrate substrate overlaps with the orthographic projection of the second pole equipotential structure of the driving transistor T3 on the substrate substrate.
  • the orthographic projection of the third notch 26 on the substrate substrate overlaps with the orthographic projection of the fifth bridge portion 45 on the substrate substrate.
  • the positive projection of the nineteenth active portion 819 on the substrate substrate and the positive projection of the first gate line G1 on the substrate substrate at least partially overlap.
  • the first gate line G1 can be able to pull up the voltage of the gate of the driving transistor T3 through the nineteenth active portion 819.
  • This setting can reduce the voltage of the data signal under the black screen of the display panel, thereby reducing the power consumption of the display panel.
  • the maximum size of the positive projection of the nineteenth active portion 819 on the substrate substrate in the first direction X can be greater than the maximum size of the positive projection of the nineteenth active portion 819 on the substrate substrate in the second direction Y.
  • the maximum size of the positive projection of the nineteenth active portion 819 on the substrate substrate in the first direction X is L1
  • the maximum size of the positive projection of the nineteenth active portion on the substrate substrate in the second direction Y is L2
  • L1/L2 can be greater than or equal to 1.5 and less than or equal to 5, for example, L1/L2 can be equal to 1.5, 2, 2.5, 3, 4, 5, etc.
  • the capacitance between the nineteenth active portion 819 and the first gate line G1 is not easy to be too large, that is, in this exemplary embodiment, the maximum size of the orthographic projection of the nineteenth active portion 819 on the base substrate in the first direction X is not easy to be too large.
  • the capacitance between the nineteenth active portion 819 and the first gate line G1 is too large, the capacitance between the nineteenth active portion 819 and the first gate line G1 is easily affected by a process error and causes a large change, thereby causing problems such as uneven display of the display panel.
  • the equipotential structure of the gate of the driving transistor T3 and the equipotential structure of the second gate line 3G2 can also form a parasitic capacitor.
  • the fourth bridge portion 44 and the second gate line 3G2 can form a parasitic capacitor.
  • the second gate line 3G2 will pull down the voltage of the gate of the driving transistor T3 through the fourth bridge portion 44.
  • the parasitic capacitor formed by the equipotential structure of the gate of the driving transistor T3 and the equipotential structure of the second gate line 3G2 can be smaller than the parasitic capacitor formed by the equipotential structure of the gate of the driving transistor T3 and the equipotential structure of the first gate line G1.
  • the capacitance formed by the equipotential structure of the first conductive portion 11 and the equipotential structure of the first gate line G1 is C1
  • the capacitance formed by the equipotential structure of the first conductive portion 11 and the equipotential structure of the second gate line 3G2 is C2
  • C1 is greater than C2.
  • the overlapping area of the orthographic projection of the nineteenth active portion 819 on the substrate and the orthographic projection of the first gate line G1 on the substrate is S1
  • the overlapping area of the orthographic projection of the fourth bridging portion 44 on the substrate and the orthographic projection of the second gate line 3G2 on the substrate is S2;
  • S1/S2 can be greater than or equal to 1.2 and less than or equal to 2, for example, S1/S2 can be equal to 1.2, 1.5, 2, etc.
  • the fifth conductive layer may include a data line Da, a power line VDD, and a ninth bridge portion 59.
  • the data line Da can be used to provide the data signal terminal in Figure 1
  • the power line VDD can be used to provide the first power terminal in Figure 1.
  • the orthographic projection of the data line Da on the substrate substrate and the orthographic projection of the power line VDD on the substrate substrate can extend along the second direction Y.
  • the data line Da can be connected to the second bridge portion 42 through a via hole to connect the first electrode and the data signal terminal of the fourth transistor T4.
  • a power line VDD can be correspondingly set for each column of pixel driving circuits, and the power line VDD can be connected to the third bridge portion 43 through a via hole through the connecting portion 52 to connect the first power terminal and the second electrode of the capacitor C and the first electrode of the fifth transistor T5.
  • the power line VDD may include a first power line segment VDD1, a second power line segment VDD2, and a third power line segment VDD3, the second power line segment VDD2 is connected between the first power line segment VDD1 and the third power line segment VDD3, the size of the orthogonal projection of the second power line segment VDD2 on the substrate in the first direction X may be greater than the size of the orthogonal projection of the first power line segment VDD1 on the substrate in the first direction X, and the size of the orthogonal projection of the second power line segment VDD2 on the substrate in the first direction X may be greater than the size of the orthogonal projection of the third power line segment VDD3 on the substrate in the first direction X.
  • the orthogonal projection of the second power line segment VDD2 on the substrate may also cover the orthogonal projection of the active portion 8 on the substrate, and the second power line segment VDD2 may reduce the influence of light on the characteristics of the second transistor T2.
  • the orthogonal projection of the power line VDD on the substrate may also cover the orthogonal projection of the fourth bridge portion 44 on the substrate, and the power line VDD may be used to shield the noise interference of other signals on the fourth bridge portion 44, thereby improving the stability of the gate voltage of the driving transistor T3.
  • the ninth bridge portion 59 may be connected to the seventh bridge portion 47 through a via hole to connect to the second electrode of the sixth transistor T6 .
  • the first power line segment VDD1 may be widened along the first direction X so that the orthographic projection of the first power line segment VDD1 on the substrate overlaps the orthographic projection of the sixth bridge portion 46 on the substrate.
  • this arrangement can reduce the resistance of the power line, on the other hand, this arrangement can stabilize the sixth bridge portion 46 through the first power line segment VDD1 to improve the stability of the voltage of the first electrode of the driving transistor, and on the other hand, this arrangement can increase the parasitic capacitance of the first electrode of the driving transistor, so that after the fourth transistor T4 is turned off, the data signal stored in the parasitic capacitance can still write the compensation voltage to the gate of the driving transistor.
  • two adjacent second power line segments VDD2 can be connected to each other.
  • the power line VDD and the second conductive portion 22 connected in the first direction X can form a grid structure, and the power line of the grid structure has a small resistance, so that the voltage difference between the first power terminals at different positions of the display panel can be reduced, thereby improving the uniformity of the display of the display panel.
  • the second conductive layer can also be provided with only one of the first connecting portion 23 and the second connecting portion 24, or the second conductive layer can also be provided with neither the first connecting portion 23 nor the second connecting portion 24. This setting can improve the transmittance of the display panel.
  • a first notch 51 is formed on the power line VDD, and at least a portion of the first notch may be located in the light-transmitting area of the display panel.
  • the light-transmitting area of the display panel may refer to an area where no light-shielding structures such as a barrier layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer are provided except for the electrode layer.
  • the first notch 51 may include a first side edge VDD21 and a second side edge VDD11, the first side edge VDD21 may be formed by a portion of the edge of the second power line segment VDD2, the second side edge VDD11 may be formed by a portion of the edge of the first power line segment VDD1, and the angle formed by the orthographic projection of the first side edge VDD21 on the substrate and the orthographic projection of the second side edge VDD11 on the substrate may be less than 90°.
  • the orthographic projection of the first notch 51 on the substrate can also overlap with the orthographic projections of the first initial signal line Vinit1, the first reset signal line Re1 and other signal lines on the substrate.
  • the first notch 51 can reduce the parasitic capacitance of the first initial signal line Vinit1, the first reset signal line Re1 and other signal lines, thereby improving the charging efficiency of the signal lines.
  • first notch, the second notch, and the third notch may also be located at other positions
  • the orthographic projections of the first notch, the second notch, and the third notch on the substrate may also be other shapes
  • the first notch, the second notch, and the third notch may be either closed shapes or non-closed shapes.
  • first pixel driving circuit P1 and the second pixel driving circuit P2 may be arranged in mirror symmetry along the mirror symmetry plane BB.
  • the electrode layer may include a plurality of electrode portions: a first electrode portion R, a second electrode portion B, and a third electrode portion G, each of which may be connected to the ninth bridge portion 59 through a via to connect the second electrode of the sixth transistor T6.
  • the first electrode portion R may be used to form a first electrode of a red light-emitting unit
  • the second electrode portion B may be used to form a first electrode of a blue light-emitting unit
  • the third electrode portion G may be used to form a first electrode of a green light-emitting unit.
  • the plurality of electrode portions are distributed in an array along a first direction X and a second direction Y, the plurality of electrode portions distributed along the first direction X form an electrode row, and the plurality of electrode portions distributed along the second direction Y form an electrode column.
  • the first electrode portion R, the third electrode portion G, the second electrode portion B, and the third electrode portion G are alternately distributed in the first direction X.
  • the plurality of electrode columns include a first electrode column ROW1, a second electrode column ROW2, a third electrode column ROW3, and a fourth electrode column ROW4 that are adjacent to each other in sequence, wherein the first electrode column ROW1 includes a first electrode portion R and a second electrode portion B that are alternately distributed in sequence in the second direction Y; the second electrode column ROW2 includes a plurality of third electrode portions G that are distributed in the second direction Y; the third electrode column ROW3 includes a second electrode portion B and a first electrode portion R that are alternately distributed in sequence in the second direction Y; and the fourth electrode column ROW4 includes a plurality of third electrode portions G that are distributed in the second direction Y.
  • the minimum distance K1 between the orthogonal projections of two third electrode portions G located in adjacent electrode rows of the same electrode column on the substrate in the second direction Y may be greater than a dimension K2 of the orthogonal projection of the first electrode portion R on the substrate in the second direction Y, or greater than a dimension K3 of the orthogonal projection of the second electrode portion B on the substrate in the second direction Y.
  • the display panel may further include a pixel definition layer located on a side of the electrode layer away from the substrate, wherein a pixel opening for forming a light-emitting unit is formed on the pixel definition layer.
  • the orthographic projection of the first electrode portion R on the substrate coincides with the orthographic projection of the corresponding pixel opening on the pixel definition layer on the substrate substrate
  • the orthographic projection of the second electrode portion B on the substrate coincides with the orthographic projection of the corresponding pixel opening on the pixel definition layer on the substrate substrate
  • the orthographic projection of the third electrode portion G on the substrate coincides with the orthographic projection of the corresponding pixel opening on the pixel definition layer on the substrate substrate.
  • the black squares drawn on the side of the fourth conductive layer away from the base substrate indicate that the fourth conductive layer is connected to the via holes of other layers facing the base substrate; the black squares drawn on the side of the fifth conductive layer away from the base substrate indicate that the fifth conductive layer is connected to the via holes of other layers facing the base substrate; the black squares drawn on the side of the electrode layer away from the base substrate indicate that the electrode layer is connected to the via holes of other layers facing the base substrate.
  • the black squares indicate the positions of the via holes, and different via holes indicated by black squares at different positions may penetrate different insulating layers.
  • the display panel may further include a first insulating layer 91, a second insulating layer 92, a third insulating layer 93, a fourth insulating layer 94, a fifth insulating layer 95, a first dielectric layer 96, a passivation layer 97, a first flat layer 98, and a second flat layer 99, wherein the base substrate 90, the shielding layer, the first insulating layer 91, the first active layer, the second insulating layer 92, the first conductive layer, the third insulating layer 93, the second conductive layer, the fourth insulating layer 94, the second active layer, the fifth insulating layer 95, the third conductive layer, the first dielectric layer 96, the fourth conductive layer, the passivation layer 97, the first flat layer 98, the fifth conductive layer, the second flat layer 99, and the electrode layer are sequentially
  • the first insulating layer 91, the second insulating layer 92, the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 may be a single-layer structure or a multi-layer structure, and the materials of the first insulating layer 91, the second insulating layer 92, the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 may be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the first dielectric layer 96 may be a silicon nitride layer; the materials of the first flat layer 98 and the second flat layer 99 may be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), etc.
  • PI polyimide
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • SOG silicon-glass bonding structure
  • the substrate 90 may include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence, and the barrier layer may be an inorganic material.
  • the passivation layer 97 may be a silicon oxide layer.
  • the materials of the first conductive layer, the second conductive layer, and the third conductive layer may be one of molybdenum, aluminum, copper, titanium, and niobium, or an alloy, or a molybdenum/titanium alloy or a stack, etc.
  • the material of the fourth conductive layer and the fifth conductive layer may include a metal material, for example, one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or a laminate, or a titanium/aluminum/titanium laminate.
  • the electrode layer may include an indium tin oxide layer and a silver layer. The square resistance of any conductive layer of the first conductive layer, the second conductive layer, and the third conductive layer may be greater than the square resistance of any conductive layer of the fourth conductive layer and the fifth conductive layer.
  • FIG. 21 it is a schematic diagram of the structure of the fifth conductive layer in another exemplary embodiment of the display panel of the present disclosure.
  • the first notch may not be set on the power line VDD, and this setting can reduce the resistance of the power line.
  • FIG. 22 it is a schematic diagram of the structure of the fourth conductive layer in another exemplary embodiment of the display panel of the present disclosure.
  • the second initial signal line may also include only the first sub-initial signal line Vinit21.
  • the proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited to this.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the number shown in the figure.
  • the drawings described in the present disclosure are only structural schematic diagrams.
  • the first, second and other qualifiers are only used to define different structural names, and they do not have a specific order and quantity.
  • the positive projection of a certain structure on the substrate substrate extends in a certain direction, which can be understood as the positive projection of the structure on the substrate substrate extending straight or bending along the direction.
  • a transistor refers to an element including at least three terminals: a gate, a drain and a source.
  • the transistor has a channel region between the drain (drain electrode terminal, a drain region or a drain electrode) and the source (source electrode terminal, a source region or a source electrode), and the current can flow through the drain, the channel region and the source.
  • the channel region refers to the area where the current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the gate electrode may also be referred to as a control electrode.
  • This exemplary embodiment also provides a display device, which includes the above-mentioned display panel.
  • the display device can be a display device such as a mobile phone, a tablet computer, a television, etc.

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Abstract

一种显示面板及显示装置，显示面板包括：像素驱动电路，像素驱动电路包括驱动晶体管(T3)、第一晶体管(T1)、第二晶体管(T2)，第二晶体管(T2)的第一极连接驱动晶体管(T3)的栅极，第二晶体管(T2)的第二极连接驱动晶体管(T3)的第二极，第一晶体管(T1)的第一极连接第一初始信号线(Vinit1)，第一晶体管(T1)的第二极连接第二晶体管(T2)的第二极；显示面板还包括：衬底基板(90)、第一复位信号线 (Re1)、第二栅线(3G2)、第一导电部(11)，第一复位信号线(Re1)在衬底基板(90)上的正投影沿第一方向(X)延伸，第一复位信号线(Rel)的部分结构用于形成第一晶体管(T1)的栅极；第二栅线(3G2)在衬底基板(90)上的正投影沿第一方向(X)延伸，第二栅线(3G2)的部分结构用于形成第二晶体管(T2)的栅极；第一导电部(11)用于形成驱动晶体管(T3)的栅极；其中，第二栅线(3G2)在衬底基板(90)上的正投影位于第一复位信号线(Rel)在衬底基板(90)上的正投影和第一导电部(11)在衬底基板(90)上的正投影之间。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
相关技术中，显示面板通常包括有像素驱动电路和发光单元，像素驱动电路用于驱动发光单元发光。像素驱动电路包括驱动晶体管，驱动晶体管根据其栅极电压向发光单元提供驱动电流。然而，驱动晶体管的栅极存在漏电问题，从而导致显示异常。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
根据本公开的一个方面，提供一种显示面板，所述显示面板包括：像素驱动电路，所述像素驱动电路包括驱动晶体管、第一晶体管、第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，所述第二晶体管的第二极连接所述驱动晶体管的第二极，所述第一晶体管的第一极连接第一初始信号线，所述第一晶体管的第二极连接所述第二晶体管的第二极；所述显示面板还包括：衬底基板、第一复位信号线、第二栅线、第一导电部，所述第一复位信号线在所述衬底基板上的正投影沿第一方向延伸，所述第一复位信号线的部分结构用于形成所述第一晶体管的栅极；所述第二栅线在所述衬底基板上的正投影沿所述第一方向延伸，所述第二栅线的部分结构用于形成所述第二晶体管的栅极；所述第一导电部用于形成所述驱动晶体管的栅极；其中，所述第二栅线在所述衬底基板上的正投影位于所述第一复位信号线在所述衬底基板上的正投影和所述第一导电部在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述显示面板还包括：第一有源部、第 二有源部、第十七有源部、第二十有源部、第五桥接部，所述第一复位信号线在所述衬底基板上的正投影覆盖所述第一有源部在所述衬底基板上的正投影，所述第一有源部用于形成所述第一晶体管的沟道区；所述第二栅线在所述衬底基板上的正投影覆盖所述第二有源部在所述衬底基板上的正投影，所述第二有源部用于形成所述第二晶体管的沟道区；第十七有源部连接于第一有源部；第二十有源部连接于所述第二有源部；所述第五桥接部在所述衬底基板上的正投影沿第二方向延伸，所述第二方向和所述第一方向相交，所述第五桥接部分别通过过孔连接所述第十七有源部和所述第二十有源部，且所述第五桥接部在所述衬底基板上的正投影与所述第二栅线在所述衬底基板上的正投影相交。
本公开一种示例性实施例中，所述显示面板还包括：第一有源部、第十七有源部、第三有源部、第十八有源部、第五桥接部，所述第一复位信号线在所述衬底基板上的正投影覆盖所述第一有源部在所述衬底基板上的正投影，所述第一有源部用于形成所述第一晶体管的沟道区；第十七有源部连接于第一有源部；所述第一导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第三有源部用于形成所述驱动晶体管的沟道区；第十八有源部连接于所述第三有源部；所述第五桥接部在所述衬底基板上的正投影沿第二方向延伸，所述第二方向和所述第一方向相交，所述第五桥接部分别通过过孔连接所述第十七有源部和第十八有源部，且所述第五桥接部在所述衬底基板上的正投影与所述第二栅线在所述衬底基板上的正投影相交。
本公开一种示例性实施例中，所述显示面板还包括：第十九有源部、第四桥接部，第十九有源部连接于所述第二有源部远离所述第二十有源部的一侧；第四桥接部所述第四桥接部分别通过过孔连接所述第十九有源部和所述第一导电部；其中，所述第四桥接部在所述衬底基板上的正投影沿所述第二方向延伸且与所述第二栅线在所述衬底基板上的正投影相交。
本公开一种示例性实施例中，所述显示面板还包括：第一有源层、第一导电层、第二有源层、第三导电层、第四导电层，第一有源层位于所述衬底基板的一侧，所述第一有源层包括第一有源部、第三有源部、第十七有源部、第十八有源部，所述第一有源部用于用于形成所述第一晶体管的 沟道区，所述第三有源部用于形成所述驱动晶体管的沟道区，所述第十七有源部连接于第一有源部，所述第十八有源部连接于所述第三有源部；第一导电层位于所述第一有源层背离所述衬底基板的一侧，所述第一导电层包括所述第一复位信号线、第一导电部；第二有源层位于所述第一导电层背离所述衬底基板的一侧，所述第二有源层包括第二有源部、第十九有源部、第二十有源部，所述第二有源部用于形成所述第二晶体管的沟道区，所述第十九有源部和第二十有源部分别连接于所述第二有源部的两端；第三导电层位于所述第二有源层背离所述衬底基板的一侧，所述第三导电层包括所述第二栅线；第四导电层位于所述第三导电层背离所述衬底基板的一侧，所述第四导电层包括第四桥接部、第五桥接部，所述第四桥接部分别通过过孔连接所述第十九有源部和所述第一导电部，所述第五桥接部分别通过过孔连接所述第十八有源部、第十七有源部、所述第二十有源部。
本公开一种示例性实施例中，所述像素驱动电路还包括第四晶体管，所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极；所述显示面板还包括；第一有源层、第二有源层，第一有源层位于所述衬底基板的一侧，所述第一有源层包括第三有源部和第四有源部，所述第三有源部用于形成所述驱动晶体管的沟道区，所述第四有源部用于形成所述第四晶体管的沟道区；第二有源层位于所述第一有源层背离所述衬底基板的一侧，所述第二有源层包括第二有源部，所述第二栅线在所述衬底基板上的正投影覆盖所述第二有源部在所述衬底基板上的正投影，所述第二有源部用于形成所述第二晶体管的沟道区；其中，在所述第一方向上，所述第三有源部在所述衬底基板上的正投影位于所述第二有源部在所述衬底基板上的正投影和所述第四有源部在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述像素驱动电路还包括第四晶体管，所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极；所述显示面板还包括：第一导电层，第一导电层位于所述衬底基板的一侧，所述第一导电层包括第一栅线，所述第一栅线在所述衬底基板上的正投影沿所述第一方向延伸且位于所述第一复位信号线在所述衬底基板上的正投影和所述第二栅线在所述衬底基板上的正投 影之间，所述第一栅线的部分结构用于形成所述第四晶体管的栅极；其中，所述第十九有源部在所述衬底基板上的正投影与所述第一栅线在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述第十九有源部在所述衬底基板上的正投影在所述第一方向上的最大尺寸大于所述第十九有源部在所述衬底基板上的正投影在第二方向上的最大尺寸。
本公开一种示例性实施例中，所述第十九有源部在所述衬底基板上的正投影在所述第一方向上的最大尺寸为L1，所述第十九有源部在所述衬底基板上的正投影在第二方向上的最大尺寸为L2，L1/L2大于等于1.5且小于等于5。
本公开一种示例性实施例中，所述像素驱动电路还包括第四晶体管，所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极，所述第四晶体管的栅极连接第一栅线；其中，所述第一导电部的等电位结构和所述第一栅线的等电位结构形成的电容容量为C1，所述第一导电部的等电位结构和所述第二栅线的等电位结构形成的电容容量为C2，C1大于C2。
本公开一种示例性实施例中，所述显示面板还包括：第二有源部、第十九有源部、第四桥接部，第二有源部用于形成所述第二晶体管的沟道区；第十九有源部连接于所述第二有源部，所述第十九有源部在所述衬底基板上的正投影和所述第一栅线在所述衬底基板上的正投影至少部分交叠；第四桥接部所述第四桥接部分别通过过孔连接所述第十九有源部和所述第一导电部，所述第四桥接部在所述衬底基板上的正投影沿所述第二方向延伸且与所述第二栅线在所述衬底基板上的正投影至少部分交叠；其中，所述第十九有源部在所述衬底基板上的正投影和所述第一栅线在所述衬底基板上的正投影的交叠面积为S1，所述第四桥接部在所述衬底基板上的正投影和所述第二栅线在所述衬底基板上的正投影的交叠面积为S2；S1/S2大于等于1.2且小于等于2。
本公开一种示例性实施例中，所述显示面板还包括发光单元，所述像素驱动电路用于驱动所述发光单元发光，所述像素驱动电路还包括第七晶体管，所述第七晶体管的第一极连接第二初始信号线，第二极连接所述发 光单元的第一电极；所述显示面板还包括：第四导电层，第四导电层位于所述衬底基板的一侧，所述第四导电层包括所述第二初始信号线；其中，所述第二初始信号线包括第一子初始信号线和第二子初始信号线，所述第一子初始信号线在所述衬底基板上的正投影沿所述第一方向延伸，所述第二子初始信号线在所述衬底基板上的正投影沿第二方向延伸，所述第二方向和所述第一方向相交；所述第一子初始信号线连接与其在所述衬底基板上正投影相交的所述第二子初始信号线。
本公开一种示例性实施例中，所述像素驱动电路还包括第五晶体管，所述第五晶体管的第一极连接电源线，第二极连接所述驱动晶体管的第一极；所述显示面板还包括：第四导电层、第五导电层，第五导电层位于所述第四导电层背离所述衬底基板的一侧，所述第五导电层包括所述电源线；所述电源线上形成有第一缺口，所述第一缺口至少部分位于所述显示面板的透光区。
本公开一种示例性实施例中，所述电源线在所述衬底基板上的正投影沿第二方向延伸，所述第二方向和所述第一方向相交；所述电源线包括第一电源线段、第二电源线段、第三电源线段，所述第二电源线段连接于所述第一电源线段和所述第三电源线段之间；所述第二电源线段在所述衬底基板上的正投影在所述第一方向上的尺寸大于所述第一电源线段在所述衬底基板上的正投影在所述第一方向上的尺寸，所述第二电源线段在所述衬底基板上的正投影在所述第一方向上的尺寸大于所述第三电源线段在所述衬底基板上的正投影在所述第一方向上的尺寸；所述第一缺口包括第一侧边和第二侧边，所述第一侧边在所述衬底基板上的正投影和所述第二侧边在所述衬底基板上的正投影形成的夹角小于90°；且所述第一侧边由所述第二电源线段的部分边沿形成，所述第二侧边由所述第一电源线段的部分边沿形成。
本公开一种示例性实施例中，所述像素驱动电路还包括电容，所述电容的第一电极连接所述驱动晶体管的栅极，所述电容的第二电极连接电源线，所述第一导电部复用为所述电容的第一电极；所述显示面板还包括：第一导电层、第二有源层、第二导电层，第一导电层位于所述衬底基板的一侧；第二有源层位于所述第一导电层背离所述衬底基板的一侧；第二导 电层位于所述第一导电层和所述第二有源层之间，所述第二导电层包括第二导电部，所述第二导电部在所述衬底基板上的正投影与所述第一导电部在所述衬底基板上的正投影至少部分交叠，所述第二导电部用于形成所述电容的第二电极；其中，在所述第一方向上相邻的至少部分所述第二导电部相连接。
本公开一种示例性实施例中，所述显示面板包括沿所述第一方向和第二方向阵列分布的重复单元，所述第一方向和所述第二方向相交，所述重复单元包括在所述第一方向上分布的两个所述像素驱动电路，同一重复单元中两所述像素驱动电路至少部分镜像对称设置；所述第二导电层还包括：第一连接部，第一连接部连接于同一所述重复单元中两所述第二导电部之间，所述第一连接部在所述衬底基板上的正投影在所述第二方向上的尺寸小于所述第二导电部在所述衬底基板上的正投影在所述第二方向上的尺寸，所述第一连接部和与其连接的所述第二导电部形成第三缺口；所述第三缺口在衬底基板上的正投影和所述驱动晶体管第二极的等电位结构在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述显示面板包括沿所述第一方向和第二方向阵列分布的重复单元，所述第一方向和所述第二方向相交，所述重复单元包括在所述第一方向上分布的两个所述像素驱动电路，同一重复单元中两所述像素驱动电路至少部分镜像对称设置；多条所述第二栅线连接同一信号端；所述第二导电层还包括：第二连接部，所述第二连接部连接于在所述第一方向上相邻的所述重复单元中两相邻所述第二导电部之间，所述第二连接部在所述衬底基板上的正投影在所述第二方向上的尺寸小于所述第二导电部在所述衬底基板上的正投影在所述第二方向上的尺寸，所述第二连接部和与其连接的所述第二导电部形成第二缺口；所述第二缺口在衬底基板上的正投影和所述驱动晶体管第一极的等电位结构在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述显示面板还包括发光单元，所述像素驱动电路用于驱动所述发光单元发光，所述像素驱动电路还包括第七晶体管、第八晶体管，所述第七晶体管的第一极连接第二初始信号线，所述第七晶体管的第二极连接所述发光单元的第一电极，所述第八晶体管的第 一极连接第三初始信号线，所述第八晶体管的第二极连接所述驱动晶体管的第一极；所述显示面板还包括：第一导电层、第三导电层，第一导电层位于所述衬底基板的一侧，所述第一导电层包括第二复位信号线，所述第二复位信号线在所述衬底基板上的正投影沿所述第一方向延伸，且所述第二复位信号线的部分结构用于形成所述第七晶体管的栅极；第三导电层位于所述第一导电层背离所述衬底基板的一侧，所述第三导电层包括所述第三初始信号线，所述第三初始信号线在所述衬底基板上的正投影沿所述第一方向延伸；其中，所述第二复位信号线在所述衬底基板上的正投影和所述第三初始信号线在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述显示面板还包括发光单元，所述像素驱动电路用于驱动所述发光单元发光，所述像素驱动电路还包括：第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、电容，第四晶体管的第一极连接数据线，第二极连接所述驱动晶体管的第一极；第五晶体管的第一极连接电源线，第二极连接所述驱动晶体管的第一极；第六晶体管的第一极连接所述驱动晶体管的第二极，第二极连接所述发光单元的第一电极；第七晶体管的第一极连接第二初始信号线，第二极连接所述发光单元的第一电极；第八晶体管的第一极连接第三初始信号线，第二极连接所述驱动晶体管的第一极；电容连接于所述驱动晶体管栅极和所述电源线之间；所述显示面板还包括：第一有源层、第一导电层、第二有源层、第三导电层。所述第一有源层包括第一有源部、第三有源部、第四有源部、第五有源部、第六有源部、第七有源部、第八有源部，所述第一有源部用于形成所述第一晶体管的沟道区，所述第三有源部用于形成驱动晶体管的沟道区，所述第四有源部用于形成所述第四晶体管的沟道区，所述第五有源部用于形成第五晶体管的沟道区，所述第六有源部用于形成所述第六晶体管的沟道区，所述第七有源部用于形成所述第七晶体管的沟道区，所述第八有源部用于形成所述第八晶体管的沟道区；第一导电层位于所述第一有源层背离所述衬底基板的一侧，所述第一导电层包括所述第一复位信号线、第一栅线、第二复位信号线、使能信号线、第一导电部，所述第一栅线的部分结构用于形成所述第四晶体管的栅极，所述使能信号线的部分结构分别用于形成所述第五晶体管、第六晶体管的栅极，所述第二复位 信号线的部分结构分别用于形成所述第七晶体管和第八晶体管的栅极；第二有源层位于所述第一导电层背离所述衬底基板的一侧，所述第二有源层包括第二有源部，所述第二有源部用于形成所述第二晶体管的沟道区；第三导电层位于所述第二有源层背离所述衬底基板的一侧，所述第三导电层包括所述第二栅线；其中，所述使能信号线在所述衬底基板上的正投影沿所述第一方向延伸且位于所述第一导电部在所述衬底基板上的正投影远离所述第一复位信号线在所述衬底基板上的正投影的一侧；所述第一栅线在所述衬底基板上的正投影沿所述第一方向延伸且位于所述第二栅线在所述衬底基板上的正投影和所述第一复位信号线在所述衬底基板上的正投影之间；所述第二复位信号线在所述衬底基板上的正投影沿所述第一方向延伸且位于所述使能信号线在所述衬底基板上的正投影远离所述第一导电部在所述衬底基板上的正投影的一侧。
本公开一种示例性实施例中，所述第一晶体管、驱动晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管为P型晶体管，所述第二晶体管为N型晶体管。
根据本公开的一个方面，提供一种显示装置，其中，包括上述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开显示面板一种示例性实施例中像素驱动电路的电路结构示意图；
图2为图1所示像素驱动电路中各节点上信号的时序图；
图3为本公开显示面板一种示例性实施例中的结构版图；
图4为图3中遮挡层的结构版图；
图5为图3中第一有源层的结构版图；
图6为图3中第一导电层的结构版图；
图7为图3中第二导电层的结构版图；
图8为图3中第二有源层的结构版图；
图9为图3中第三导电层的结构版图；
图10为图3中第四导电层的结构版图；
图11为图3中第五导电层的结构版图；
图12为图3中电极层的结构版图；
图13为图3中遮挡层、第一有源层的结构版图；
图14为图3中遮挡层、第一有源层、第一导电层的结构版图；
图15为图3中遮挡层、第一有源层、第一导电层、第二导电层的结构版图；
图16为图3中遮挡层、第一有源层、第一导电层、第二导电层、第二有源层的结构版图；
图17为图3中遮挡层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层的结构版图；
图18为图3中遮挡层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层的结构版图；
图19为图3中遮挡层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层、第五导电层的结构版图；
图20为图3所示显示面板沿虚线AA剖开的部分剖视图；
图21为本公开显示面板另一种示例性实施例中第五导电层的结构示意图；
图22为本公开显示面板另一种示例性实施例中第四导电层的结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实 施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
本示例性实施例提供一种显示面板，如图1所示，为本公开显示面板一种示例性实施例中像素驱动电路的电路结构示意图。该像素驱动电路可以包括：第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、电容C。其中，第二晶体管T2的第一极连接驱动晶体管T3的栅极，第二极连接驱动晶体管T3的第二极，栅极连接第二栅极驱动信号端G2；第一晶体管T1的第一极连接第一初始信号端Vinit1，第二极连接第二晶体管T2的第二极，栅极连接第一复位信号端Re1；第四晶体管T4的第一极连接数据信号端Da，第二极连接驱动晶体管T3的第一极，栅极连接第一栅极驱动信号端G1；第五晶体管T5的第一极连接第一电源端VDD，第二极连接驱动晶体管T3的第一极，栅极连接使能信号端EM，第六晶体管T6的第一极连接驱动晶体管T3的第二极，栅极连接使能信号端EM；第七晶体管T7的第一极连接第二初始信号端Vinit2，第二极连接第六晶体管T6的第二极，栅极连接第二复位信号端Re2；第八晶体管T8的第一极连接第三初始信号端Vinit3，第二极连接驱动晶体管T3的第一极，栅极连接第二复位信号端Re2；电容的第一电极连接驱动晶体管T3的栅极，第二电极连接第一电源端VDD。该像素驱动电路可以用于驱动发光单元L发光，发光单元L的第一电极连接第六晶体管T6的第二极，发光单元L的第二电极连接第二电源端VSS。其中，第一晶体管T1、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8可以均为P型晶体管，第二晶体管T2可以为N型晶体管。
如图2所示，为图1所示像素驱动电路中各节点上信号的时序图。其中，EM表示使能信号端上信号的时序图；G1表示第一栅极驱动信号端上 信号的时序图；G2表示第二栅极驱动信号端上信号的时序图；Re1表示第一复位信号端上信号的时序图；Re2表示第二复位信号端上信号的时序图。
本公开中像素驱动电路的驱动方法可以包括扫描帧Ft和保持帧St。扫描帧Ft可以包括：第一复位阶段t1、第二复位阶段t2、第三复位阶段t3、数据写入阶段t4、发光阶段t5。在第一复位阶段t1：第二栅极驱动信号端G2输出高电平信号，第二复位信号端Re2输出低电平信号，第二晶体管T2、第七晶体管T7、第八晶体管T8导通，第二初始信号端Vinit2向发光单元L的第一电极输入第二初始信号，第三初始信号端Vinit3向驱动晶体管的第一极输入第三初始信号，同时，驱动晶体管T3可以导通，第三初始信号端Vinit3向驱动晶体管栅极写入复位信号Vinit3+Vth，其中，Vinit3为第三初始信号的电压，Vth为驱动晶体管T3的阈值电压；在第二复位阶段t2：第二栅极驱动信号端G2输出高电平信号，第一复位信号端Re1输出低电平信号，第一晶体管T1、第二晶体管T2导通，第一初始信号端Vinit1向驱动晶体管T3的栅极输入第一初始信号；在第三复位阶段t3：第二栅极驱动信号端G2输出高电平信号，第一复位信号端Re1输出低电平信号，第一晶体管T1、第二晶体管T2导通，第一初始信号端Vinit1向驱动晶体管T3的栅极输入第一初始信号；在数据写入阶段t4，第一栅极驱动信号端G1输出低电平信号，第二栅极驱动信号端G2输出高电平信号，第二晶体管T2、第四晶体管T4导通，数据信号端Da输出数据信号以向驱动晶体管的栅极写入补偿电压Vdata+Vth，其中Vdata为数据信号的电压，Vth为驱动晶体管T3的阈值电压；在发光阶段t5：使能信号端EM输出低电平信号，第五晶体管T5、第六晶体管T6导通，驱动晶体管T3在其栅极的电压Vdata+Vth作用下驱动发光单元L发光。根据驱动晶体管输出电流公式I＝(μWCox/2L)(Vgs-Vth) 2，其中，μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电压。本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth) 2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。
本示例性实施例中，驱动晶体管T3的栅极通过第二晶体管T2和第一 晶体管T1连接第一初始信号端，从而可以降低驱动晶体管T3在发光阶段向第一初始信号端的漏电流。此外，在第一复位阶段t1，第三初始信号端向驱动晶体管的栅极输入复位信号，向驱动晶体管的第一极输入第三初始信号，该设置可以恢复驱动晶体管T3由于前一帧偏压造成的磁滞，以及解决首帧亮度偏暗等问题。
本示例性实施例中，第一复位信号端、第二复位信号端、使能信号端在保持帧St中的时序可以和其在扫描帧中的时序相同，该设置可以使得驱动晶体管在扫描帧和保持帧中具有相同的磁滞状态，以改善由于相邻帧亮度不一导致的显示面板闪烁问题。
需要说明的是，在其他示例性实施例中，该像素驱动电路还可以有其他驱动方法，本申请不对像素驱动电路的驱动方法进行限定。
本示例性实施例中，显示面板可以包括依次层叠设置的衬底基板、遮挡层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层、第五导电层、电极层，其中，上述相邻层级之间可以设置有绝缘层。如图3-19所示，图3为本公开显示面板一种示例性实施例中的结构版图，图4为图3中遮挡层的结构版图，图5为图3中第一有源层的结构版图，图6为图3中第一导电层的结构版图，图7为图3中第二导电层的结构版图，图8为图3中第二有源层的结构版图，图9为图3中第三导电层的结构版图，图10为图3中第四导电层的结构版图，图11为图3中第五导电层的结构版图，图12为图3中电极层的结构版图，图13为图3中遮挡层、第一有源层的结构版图，图14为图3中遮挡层、第一有源层、第一导电层的结构版图，图15为图3中遮挡层、第一有源层、第一导电层、第二导电层的结构版图，图16为图3中遮挡层、第一有源层、第一导电层、第二导电层、第二有源层的结构版图，图17为图3中遮挡层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层的结构版图，图18为图3中遮挡层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层的结构版图，图19为图3中遮挡层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层、第五导电层的结构版图。该显示面板可以包括多个图1所示的像素驱动电路。如图19所示，多个像素驱动电路中可以包括在第一方 向X上相邻分布第一像素驱动电路P1和第二像素驱动电路P2，第一像素驱动电路P1和第二像素驱动电路P2的至少部分结构可以以镜像对称面BB镜像对称设置。其中，镜像对称面BB可以垂直于衬底基板。且第一像素驱动电路P1在衬底基板上的正投影和第二像素驱动电路P2在衬底基板上的正投影的至少部分结构可以以镜像对称面BB与衬底基板的交线为对称轴对称设置。其中，第一像素驱动电路P1和第二像素驱动电路P2可以形成一重复单元，该显示面板可以包括在第一方向X和第二方向Y上阵列分布的多个重复单元。其中，第二方向Y和第一方向X可以相交，例如，第一方向X可以为行方向，第二方向Y可以为列方向。
如图3、图4、图13所示，遮挡层可以包括多个遮挡部71、连接部73、连接部72，连接部73在衬底基板上的正投影沿第二方向Y延伸，且连接于在第二方向Y上相邻的遮挡部71之间；连接部72在衬底基板上的正投影沿第一方向X延伸，且连接于在第一方向X上相邻的遮挡部71之间。
如图3、5、13、14所示，第一有源层可以包括第一有源部61、第三有源部63、第四有源部64、第五有源部65、第六有源部66、第七有源部67、第八有源部68。其中，第一有源部61用于形成第一晶体管T1的沟道区，第三有源部63用于形成驱动晶体管T3的沟道区，第四有源部64用于形成第四晶体管T4的沟道区，第五有源部65用于形成第五晶体管T5的沟道区，第六有源部66用于形成第六晶体管T6的沟道区，第七有源部67用于形成第七晶体管T7的沟道区，第八有源部68用于形成第八晶体管T8的沟道区。此外，第一有源层还可以包括：第九有源部69、第十有源部610、第十一有源部611、第十二有源部612、第十三有源部613、第十四有源部614、第十五有源部615、第十六有源部616、第十七有源部617、第十八有源部618。第九有源部69连接于第四有源部64远离第三有源部63的一端；第十有源部610连接于第五有源部65远离第三有源部63的一端，其中，在第一方向X上相邻的重复单元中，相邻第五有源部65通过第十有源部610连接；第十一有源部611连接于第五有源部65和第三有源部63之间；第十二有源部612连接于第七有源部67远离第六有源部66的一端；第十三有源部613和第十四有源部614分别连接于第八有源部68 的两端；第十五有源部615连接于第六有源部66和第七有源部67之间；第十六有源部616和第十七有源部617连接于第一有源部61的两端，其中，在同一重复单元中，相邻两第一有源部61通过第十六有源部616连接；第十八有源部618连接于第三有源部63和第六有源部66之间。其中，在第一方向上，第八有源部68在衬底基板上的正投影位于第七有源部67在衬底基板上的正投影和第五有源部65在衬底基板上的正投影之间。
如图3、5、13、14所示，遮挡部71在衬底基板上的正投影可以覆盖第三有源部63在衬底基板上的正投影，遮挡部71可以对第三有源部63进行遮光，以降低光照对驱动晶体管T3驱动特性的影响。此外，遮挡层可以为导电材料，遮挡层还可以连接一稳定电压源，以对驱动晶体管T3进行噪音屏蔽，例如，遮挡层可以连接第一电源端VDD、第一初始信号端Vinit1、第二初始信号端Vinit2、第三初始信号端Vinit3、第二电源端VSS等。第一有源层可以由多晶硅材料形成，相应的，第一晶体管T1、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8可以为P型的低温多晶硅薄膜晶体管。
如图3、6、14所示，第一导电层可以包括第一复位信号线Re1、第一栅线G1、使能信号线EM、第二复位信号线Re2、第一导电部11。第一复位信号线Re1、第一栅线G1、使能信号线EM、第二复位信号线Re2在衬底基板上的正投影可以沿第一方向X延伸。第一复位信号线Re1可以用于提供图1中的第一复位信号端。第一复位信号线Re1在衬底基板上的正投影可以覆盖第一有源部61在衬底基板上的正投影，第一复位信号线Re1的部分结构可以用于形成第一晶体管T1的栅极。第一栅线G1可以用于提供图1中的第一栅极驱动信号端。第一栅线G1在衬底基板上的正投影可以覆盖第四有源部64在衬底基板上的正投影。第一栅线G1的部分结构可以用于形成第四晶体管T4的栅极。使能信号线EM用于提供图1中的使能信号端，使能信号线EM在衬底基板上的正投影可以覆盖第五有源部65在衬底基板上的正投影、第六有源部66在衬底基板上的正投影，使能信号线EM的部分结构可以用于形成第五晶体管T5的栅极，使能信号线EM的另外部分结构可以用于形成第六晶体管T6的栅极。第二复位信号线Re2用于提供图1中的第二复位信号端。第二复位信号线Re2在衬底基板上的正投 影可以覆盖第七有源部67在衬底基板上的正投影。第二复位信号线Re2的部分结构可以用于形成第七晶体管T7的栅极。第一导电部11在衬底基板上的正投影可以覆盖第三有源部63在衬底基板上的正投影，第一导电部11可以用于形成驱动晶体管T3的栅极和电容C的第一电极。
如图3、6、14所示，第一复位信号线Re1在衬底基板上的正投影、第一栅线G1在衬底基板上的正投影、第一导电部11在衬底基板上的正投影、使能信号线EM在衬底基板上的正投影、第二复位信号线Re2在衬底基板上的正投影可以沿第二方向Y依次分布。此外，该显示面板可以利用第一导电层为掩膜对第一有源层进行导体化处理，即第一有源层中被第一导电层覆盖的区域可以形成晶体管的沟道区，第一有源层中未被第一导电层覆盖的区域形成导体结构。
如图3、7、15所示，第二导电层可以包括第三栅线2G2、第一初始信号线Vinit1、第二导电部22。第一初始信号线Vinit1在衬底基板上的正投影、第三栅线2G2在衬底基板上的正投影均可以沿第一方向X延伸。第一初始信号线Vinit1用于提供图1中的第一初始信号端，第三栅线2G2用于提供图1中的第二栅极驱动信号端。第二导电部22在衬底基板上的正投影可以与第一导电部11在衬底基板上的正投影交叠，第二导电部22可以用于形成电容C的第二电极。应该理解的是，在其他示例性实施例中，第一初始信号线Vinit1还可以位于其他导电层，例如，第一初始信号线Vinit1还可以位于遮挡层、第三导电层、第四导电层等。如图7所示，第二导电层还包括第一连接部23、第二连接部24，第一连接部23连接于同一重复单元中两第二导电部22之间，第二连接部24连接于在第一方向X上相邻重复单元中相邻两第二导电部22之间。第二导电部22上还形成有开口221。
如图3、8、16所示，第二有源层可以包括多个有源部8，有源部8包括第二有源部82、第十九有源部819、第二十有源部820，第二有源部82连接于第十九有源部819和第二十有源部820之间，第二有源部82用于形成第二晶体管的沟道区。第三栅线2G2在衬底基板上的正投影可以覆盖第二有源部82在衬底基板上的正投影，第三栅线2G2的部分结构可以用于形成第二晶体管T2的底栅。在所述第一方向X上，所述第三有源部 63在所述衬底基板上的正投影位于所述第二有源部82在所述衬底基板上的正投影和所述第四有源部64在所述衬底基板上的正投影之间。其中，第二有源层可以由氧化铟镓锌形成，相应的，第二晶体管T2可以为N型的金属氧化物薄膜晶体管。
如图3、9、17所示，第三导电层可以包括：第二栅线3G2、第三初始信号线Vinit3，第二栅线3G2在衬底基板上的正投影、第三初始信号线Vinit3在衬底基板上的正投影均可以沿第一方向X延伸。第二栅线3G2用于提供图1中的第二栅极驱动信号端，第二栅线3G2在衬底基板上的正投影可以覆盖第二有源部82在衬底基板上的正投影，第二栅线3G2的部分结构可以用于形成第二晶体管T2的顶栅。同一行像素驱动电路中的第二栅线3G2和第三栅线2G2可以通过过孔连接，连接于第二栅线3G2和第三栅线2G2之间的过孔可以位于显示面板显示区以外的边沿走线区。第三初始信号线Vinit3可以用于提供图1中的第三初始信号端，第三初始信号线Vinit3在衬底基板上的正投影可以和第二复位信号线Re2在衬底基板上的正投影交叠，该设置可以提高显示面板的透过率。此外，该显示面板可以利用第三导电层为掩膜对第二有源层进行导体化处理，即第二有源层中被第三导电层覆盖的区域可以形成晶体管的沟道区，第二有源层中未被第三导电层覆盖的区域形成导体结构。
如图3、10、18所示，第四导电层可以包括：第二初始信号线Vinit2、第一桥接部41、第二桥接部42、第三桥接部43、第四桥接部44、第五桥接部45、第六桥接部46、第七桥接部47、第八桥接部48。第二初始信号线Vinit2可以用于提供图1中的第二初始信号端。第二初始信号线Vinit2可以包括第一子初始信号线Vinit21和第二子初始信号线Vinit22。第一子初始信号线Vinit21在衬底基板上的正投影沿第一方向X延伸，第二子初始信号线Vinit22在衬底基板上的正投影沿第二方向Y延伸，且第一子初始信号线Vinit21在衬底基板上的正投影和第二子初始信号线Vinit22在衬底基板上的正投影相交。每行像素驱动电路可以对应设置一条第一子初始信号线Vinit21，每列重复单元可以对应设置一条第二子初始信号线Vinit22。第一子初始信号线Vinit21和第二子初始信号线Vinit22可以形成网格结构，该设置可以降低第二初始信号线的自身电阻，进而降低显 示面板不同位置上第二初始信号端的电压差异。第二初始信号线Vinit2可以通过过孔H连接第十二有源部612，以连接第二初始信号端和第七晶体管T7的第一极。本示例性实施例中，黑色方块表示过孔的位置。第四导电层面向衬底基板一侧的相邻绝缘层在第三栅线2G2、第二栅线3G2所在位置会出现凸起结构，从而容易导致第二子初始信号线Vinit22断裂。本示例性实施例中，第三栅线2G2、第二栅线3G2均包括沿第一方向X延伸的两侧边，第二子初始信号线Vinit2在衬底基板上的正投影和第三栅线2G2中两侧边在衬底基板上的正投影垂直或接近垂直，例如，第二子初始信号线Vinit2在衬底基板上的正投影和第三栅线2G2中两侧边在衬底基板上的正投影的夹角均大于等于80°且小于等于100°，第二子初始信号线Vinit2在衬底基板上的正投影和第三栅线2G2中两侧边在衬底基板上的正投影的夹角可以等于80°、90°、100°等。第二子初始信号线Vinit2在衬底基板上的正投影和第二栅线3G2中两侧边在衬底基板上的正投影垂直或接近垂直，例如，第二子初始信号线Vinit2在衬底基板上的正投影和第二栅线3G2中两侧边在衬底基板上的正投影的夹角均大于等于80°且小于等于100°，第二子初始信号线Vinit2在衬底基板上的正投影和第二栅线3G2中两侧边在衬底基板上的正投影的夹角可以等于80°、90°、100°等。该设置可以降低第二子初始信号线Vinit2断裂的风险。此外，本示例性实施例中，在衬底基板上的正投影与第二子初始信号线Vinit22相交的第三栅线2G2的部分侧边和在衬底基板上的正投影与第二子初始信号线Vinit22相交的第三栅线2G2的部分侧边在衬底基板上的正投影不交叠，该设置可以使得第四导电层面向衬底基板一侧的相邻绝缘层在第三栅线2G2、第二栅线3G2所在位置形成坡度，从而该设置同样可以降低第二子初始信号线Vinit2断裂的风险。第一桥接部41可以分别通过过孔连接第十六有源部616、第一初始信号线Vinit1，以连接第一晶体管T1的第一极和第一初始信号端。第二桥接部42可以通过过孔连接第九有源部69，以连接第四晶体管T4的第一极。第三桥接部43可以分别通过过孔连接第二连接部24和第十有源部610，以连接第五晶体管T5的第一极和电容的第二电极。第四桥接部44可以分别通过过孔连接第十九有源部819和第一导电部11，以连接第二晶体管T2的第一极和驱动晶体管 T3的栅极，连接于第一导电部11和第四桥接部44之间的过孔在衬底基板上的正投影位于开口221在衬底基板上的正投影以内，以使连接于第一导电部11和第四桥接部44之间的过孔与第二导电部22绝缘。第四桥接部44在所述衬底基板上的正投影可以沿所述第二方向Y延伸且与所述第二栅线3G2在所述衬底基板上的正投影相交。第五桥接部45可以分别通过过孔连接第十七有源部617、第十八有源部618、第二十有源部820，以连接第一晶体管T1的第二极、驱动晶体管T3的第二极、第二晶体管T2的第二极。第五桥接部45在衬底基板上的正投影可以和有源部8在衬底基板上的正投影至少部分交叠，该设置可以提供显示面板的透过率。此外，第五桥接部45在所述衬底基板上的正投影可以沿第二方向Y延伸且与第二栅线3G2在所述衬底基板上的正投影相交。第六桥接部46可以分别通过过孔连接第十一有源部611和第十四有源部614，以连接第八晶体管的第二极和驱动晶体管T3的第一极。第七桥接部47可以通过过孔连接第十五有源部615，以连接第六晶体管的第二极。第八桥接部48可以分别通过过孔连接第十三有源部613和第三初始信号线Vinit3，以连接第八晶体管T8的第一极和第三初始信号端。应该理解的是，在其他示例性实施例中，第二初始信号线Vinit2还可以位于其他导电层，例如，第二初始信号线Vinit2可以位于遮挡层、第二导电层、第三导电层等；第二初始信号线Vinit2也可以仅包括第一子初始信号线Vinit21或第二子初始信号线Vinit22。
本示例性实施例中，多行像素驱动电路中的多条第二栅线3G2可以由同一信号端提供第二栅极驱动信号。例如，相邻奇偶像素驱动电路行中的两条第二栅线3G2可以由栅极驱动电路中同一级移位寄存器单元提供第二栅极驱动信号。本示例性实施例中，驱动晶体管T3第一极的等电位结构与其他导电结构形成寄生电容，在第四晶体管T4关断后，驱动晶体管T3第一极等电位结构可以持续向驱动晶体管栅极写入补偿电压。由于接收同一第二栅极驱动信号的两行像素驱动电路中，两行像素驱动电路在数据写入阶段均需要将第二晶体管T2导通。因而，上一行像素驱动电路通过驱动晶体管T3第一极等电位结构向驱动晶体管栅极写入补偿电压的时长大于相邻下一行像素驱动电路通过驱动晶体管T3第一极等电位结构向驱动 晶体管栅极写入补偿电压的时长。从而导致显示面板相邻子像素行存在显示差异。
如图7所示，第二连接部24在所述衬底基板上的正投影在所述第二方向Y上的尺寸小于所述第二导电部22在所述衬底基板上的正投影在所述第二方向Y上的尺寸，第二连接部24和第二导电部22之间形成有第二缺口25，第二缺口25在衬底基板上的正投影和驱动晶体管T3第一极等电位结构在衬底基板上的正投影交叠，例如，第二缺口25在衬底基板上的正投影和第六桥接部46在衬底基板上的正投影、第十一有源部611在衬底基板上的正投影交叠。该设置可以降低驱动晶体管T3第一极等电位结构与其他结构之间的寄生电容，从而改善显示面板相邻子像素行存在显示差异的问题。
如图7所示，第一连接部23在所述衬底基板上的正投影在所述第二方向Y上的尺寸小于所述第二导电部22在所述衬底基板上的正投影在所述第二方向Y上的尺寸。第一连接部23和第二导电部22之间形成有第三缺口26，第三缺口26在衬底基板上的正投影和驱动晶体管T3第二极等电位结构在衬底基板上的正投影交叠，例如，第三缺口26在衬底基板上的正投影和第五桥接部45在衬底基板上的正投影交叠。该设置可以降低驱动晶体管T3第二极等电位结构与其他结构的寄生电容，从而提高数据信号端向驱动晶体管T3栅极写入补偿电压的效率。
如图3、8、17、18所示，本示例性实施例中，第十九有源部819在衬底基板上的正投影和第一栅线G1在衬底基板上的正投影至少部分交叠。在数据写入阶段结束时，第一栅线G1可以能够通过第十九有源部819拉高驱动晶体管T3栅极的电压。该设置可以降低显示面板黑画面下数据信号的电压，从而降低显示面板的功耗。第十九有源部819在衬底基板上的正投影在第一方向X上的最大尺寸可以大于第十九有源部819在衬底基板上的正投影在第二方向Y上的最大尺寸。所述第十九有源部819在所述衬底基板上的正投影在所述第一方向X上的最大尺寸为L1，所述第十九有源部在所述衬底基板上的正投影在第二方向Y上的最大尺寸为L2，L1/L2可以大于等于1.5且小于等于5，例如，L1/L2可以等于1.5、2、2.5、3、4、5等。第十九有源部819和第一栅线G1之间的电容容量不易过大，即本示 例性实施例中第十九有源部819在所述衬底基板上的正投影在所述第一方向X上的最大尺寸不易过大。如果第十九有源部819和第一栅线G1之间的电容容量过大，第十九有源部819和第一栅线G1之间的电容容量容易受到工艺误差造成较大的变化，从而导致显示面板显示不均等问题。
本示例性实施例中，驱动晶体管T3栅极的等电位结构和第二栅线3G2的等电位结构同样可以形成寄生电容，例如，第四桥接部44和第二栅线3G2可以形成寄生电容，数据写入阶段结束时，第二栅线3G2会通过第四桥接部44拉低驱动晶体管T3栅极的电压。本示例性实施例中，驱动晶体管T3栅极的等电位结构和第二栅线3G2的等电位结构形成的寄生电容可以小于驱动晶体管T3栅极的等电位结构和第一栅线G1的等电位结构形成的寄生电容。所述第一导电部11的等电位结构和所述第一栅线G1的等电位结构形成的电容容量为C1，所述第一导电部11的等电位结构和所述第二栅线3G2的等电位结构形成的电容容量为C2，C1大于C2。
第十九有源部819在衬底基板上的正投影和第一栅线G1在衬底基板上的正投影的交叠面积为S1，第四桥接部44在衬底基板上的正投影和第二栅线3G2在衬底基板上的正投影的交叠面积为S2；S1/S2可以大于等于1.2且小于等于2，例如，S1/S2可以等于1.2、1.5、2等。
如图3、11、19所示，第五导电层可以包括数据线Da、电源线VDD、第九桥接部59。其中，数据线Da可以用于提供图1中的数据信号端，电源线VDD可以用于提供图1中的第一电源端。数据线Da在衬底基板上的正投影、电源线VDD在衬底基板上的正投影可以沿第二方向Y延伸。数据线Da可以通过过孔连接第二桥接部42，以连接第四晶体管T4的第一极和数据信号端。每列像素驱动电路可以对应设置一条电源线VDD，电源线VDD可以通过连接部52与第三桥接部43过孔连接，以连接第一电源端和电容C的第二电极、第五晶体管T5的第一极。本示例性实施例中，电源线VDD可以包括第一电源线段VDD1、第二电源线段VDD2、第三电源线段VDD3，第二电源线段VDD2连接于第一电源线段VDD1和第三电源线段VDD3之间，第二电源线段VDD2在所述衬底基板上的正投影在第一方向X上的尺寸可以大于第一电源线段VDD1在所述衬底基板上的正投影在第一方向X上的尺寸，且所述第二电源线段VDD2在所述衬底基板上的正投影在第一方向X 上的尺寸可以大于所述第三电源线段VDD3在所述衬底基板上的正投影在第一方向X上的尺寸。此外，第二电源线段VDD2在衬底基板上的正投影还可以覆盖有源部8在衬底基板上的正投影，第二电源线段VDD2可以降低光照对第二晶体管T2的特性影响。此外，电源线VDD在衬底基板上的正投影还可以覆盖第四桥接部44在衬底基板上的正投影，电源线VDD可以用于屏蔽其他信号对第四桥接部44的噪音干扰，从而提高驱动晶体管T3栅极电压的稳定性。第九桥接部59可以通过过孔连接第七桥接部47以连接第六晶体管T6的第二极。
在其他示例性实施例中，第一电源线段VDD1可以沿第一方向X加宽设置，以使第一电源线段VDD1在衬底基板上的正投影和第六桥接部46在衬底基板上的正投影交叠。一方面，该设置可以降低电源线的电阻，另一方面，该设置可以通过第一电源线段VDD1对第六桥接部46进行稳压，以提高驱动晶体管第一极电压的稳定性，再一方面，该设置可以提高驱动晶体管第一极的寄生电容，从而使得第四晶体管T4关断后，该寄生电容存储的数据信号依然可以向驱动晶体管栅极写入补偿电压。
如图3、11、19所示，本示例性实施例中，在同一重复单元中，相邻两第二电源线段VDD2可以相互连接。电源线VDD和在第一方向X上相连接的第二导电部22可以形成网格结构，该网格结构的电源线具有较小的电阻，从而可以降低显示面板不同位置上第一电源端之间的电压差，进而提高显示面板显示的均一性。应该理解的是，在其他示例性实施例中，第二导电层也可以仅设置第一连接部23、第二连接部24中的一个，或第二导电层也可以不设置第一连接部23和第二连接部24。该设置可以提高显示面板的透过率。
如图3、11、19所示，电源线VDD上形成有第一缺口51，第一缺口至少部分可以位于显示面板的透光区。显示面板的透光区可以指除电极层以外没有设置阻挡层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层、第五导电层等遮光结构的区域。其中，第一缺口51可以包括第一侧边VDD21和第二侧边VDD11，第一侧边VDD21可以由第二电源线段VDD2的部分边沿形成，第二侧边VDD11可以由第一电源线段VDD1的部分边沿形成，第一侧边VDD21在衬底基板上的正投影和第二 侧边VDD11在衬底基板上的正投影形成的夹角可以小于90°。第一缺口51在衬底基板上的正投影还可以与第一初始信号线Vinit1、第一复位信号线Re1等信号线在衬底基板上的正投影交叠，第一缺口51可以降低第一初始信号线Vinit1、第一复位信号线Re1等信号线的寄生电容，从而提高信号线的充电效率。
应该理解的是，在其他示例性实施例中，第一缺口、第二缺口、第三缺口还可以位于其他位置，第一缺口、第二缺口、第三缺口在衬底基板上的正投影还可以为其他形状，第一缺口、第二缺口、第三缺口即可以为闭合形状也可以非闭合形状。
如图3、11、19所示，除第三桥接部43、连接部52、第九桥接部59以外，第一像素驱动电路P1和第二像素驱动电路P2的其他结构可以沿镜像对称面BB镜像对称设置。
如图3、12所示，本示例性实施例中，电极层可以包括多个电极部：第一电极部R、第二电极部B、第三电极部G，各个电极部可以通过过孔连接第九桥接部59，以连接第六晶体管T6的第二极。第一电极部R可以用于形成红色发光单元的第一电极，第二电极部B可以用于形成蓝色发光单元的第一电极，第三电极部G可以用于形成绿色发光单元的第一电极。其中，多个电极部沿第一方向X和第二方向Y阵列分布，沿第一方向X分布的多个电极部形成电极行，沿第二方向Y分布的多个电极部形成电极列。在同一电极行中，第一电极部R、第三电极部G、第二电极部B、第三电极部G在第一方向X上依次交替分布。多个电极列包括依次相邻的第一电极列ROW1、第二电极列ROW2、第三电极列ROW3、第四电极列ROW4，第一电极列ROW1包括在第二方向Y上依次交替分布的第一电极部R、第二电极部B；第二电极列ROW2包括多个在第二方向Y上分布的第三电极部G；第三电极列ROW3包括在第二方向Y上依次交替分布的第二电极部B、第一电极部R；第四电极列ROW4包括多个在第二方向Y上分布的第三电极部G。位于同一电极列相邻电极行的两个第三电极部G在所述衬底基板上的正投影在第二方向Y上的最小距离K1可以大于所述第一电极部R在所述衬底基板上的正投影在第二方向Y上的尺寸K2，或者大于所述第二电极部B所述衬底基板上的正投影在第二方向Y上的尺寸K3。显示面板还可以包括位于 电极层背离衬底基板一侧的像素定义层，所述像素定义层上形成有用于形成发光单元的像素开口。其中，第一电极部R在衬底基板上的正投影和像素定义层上与其对应的像素开口在衬底基板上的正投影重合，第二电极部B在衬底基板上的正投影和像素定义层上与其对应的像素开口在衬底基板上的正投影重合，第三电极部G在衬底基板上的正投影和像素定义层上与其对应的像素开口在衬底基板上的正投影重合。
需要说明的是，如图3、18、19所示，画于第四导电层背离衬底基板一侧的黑色方块表示第四导电层连接面向衬底基板一侧的其他层级的过孔；画于第五导电层背离衬底基板一侧的黑色方块表示第五导电层连接面向衬底基板一侧的其他层级的过孔；画于电极层背离衬底基板一侧的黑色方块表示电极层连接面向衬底基板一侧的其他层级的过孔。该黑色方块表示过孔的位置，不同位置黑色方块所表示的不同过孔可以贯穿于不同绝缘层。
如图20所示，为图3所示显示面板沿虚线AA剖开的部分剖视图。该显示面板还可以包括第一绝缘层91、第二绝缘层92、第三绝缘层93、第四绝缘层94、第五绝缘层95、第一介电层96、钝化层97、第一平坦层98、第二平坦层99，其中，衬底基板90、遮挡层、第一绝缘层91、第一有源层、第二绝缘层92、第一导电层、第三绝缘层93、第二导电层、第四绝缘层94、第二有源层、第五绝缘层95、第三导电层、第一介电层96、第四导电层、钝化层97、第一平坦层98、第五导电层、第二平坦层99、电极层依次层叠设置。第一绝缘层91、第二绝缘层92、第三绝缘层93、第四绝缘层94、第五绝缘层95可以为单层结构或多层结构，且第一绝缘层91、第二绝缘层92、第三绝缘层93、第四绝缘层94、第五绝缘层95的材料可以为氮化硅，氧化硅，氮氧化硅中的至少一种；第一介电层96可以为氮化硅层；第一平坦层98、第二平坦层99的材料可以为有机材料，例如聚酰亚胺(PI)、聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)、硅-玻璃键合结构(SOG)等材料。衬底基板90可以包括依次层叠设置的玻璃基板、阻挡层、聚酰亚胺层，阻挡层可以为无机材料。钝化层97可以为氧化硅层。第一导电层、第二导电层、第三导电层的材料可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等。第四导 电层、第五导电层的材料可以包括金属材料，例如可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层。电极层可以包括氧化铟锡层、银层。第一导电层、第二导电层、第三导电层中任一导电层的方块电阻可以大于第四导电层、第五导电层中任一导电层的方块电阻。
应该理解的是，在其他示例性实施例中，如图21所示，为本公开显示面板另一种示例性实施例中第五导电层的结构示意图。其中，电源线VDD上也可以不设置第一缺口，该设置可以降低电源线的电阻。如图22所示，为本公开显示面板另一种示例性实施例中第四导电层的结构示意图。第二初始信号线也可以仅包括第一子初始信号线Vinit21。
需要说明的是，本公开中的附图比例可以作为实际工艺中的参考，但不限于此，例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图。此外，第一、第二等限定词仅用于限定不同的结构名称，其并没有特定顺序和数量的含义。在本示例性实施例中，某一结构在衬底基板上的正投影沿某一方向延伸，可以理解为该结构在衬底基板上的正投影沿该方向直线延伸或弯折延伸。晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区，并且电流能够流过漏极、沟道区以及源极。在本示例性实施例中，沟道区是指电流主要流过的区域。在本示例性实施例中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况下，“源极”及“漏极”的功能有时互相调换。因此，在本示例性实施例中，“源极”和“漏极”可以互相调换。另外，栅极还可以称为控制极。
本示例性实施例还提供一种显示装置，其中，包括上述的显示面板。该显示装置可以为手机、平板电脑、电视等显示装置。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应 性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (21)

  1. 一种显示面板，其中，所述显示面板包括：像素驱动电路，所述像素驱动电路包括驱动晶体管、第一晶体管、第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，所述第二晶体管的第二极连接所述驱动晶体管的第二极，所述第一晶体管的第一极连接第一初始信号线，所述第一晶体管的第二极连接所述第二晶体管的第二极；
    所述显示面板还包括：
    衬底基板；
    第一复位信号线，所述第一复位信号线在所述衬底基板上的正投影沿第一方向延伸，所述第一复位信号线的部分结构用于形成所述第一晶体管的栅极；
    第二栅线，所述第二栅线在所述衬底基板上的正投影沿所述第一方向延伸，所述第二栅线的部分结构用于形成所述第二晶体管的栅极；
    第一导电部，所述第一导电部用于形成所述驱动晶体管的栅极；
    其中，所述第二栅线在所述衬底基板上的正投影位于所述第一复位信号线在所述衬底基板上的正投影和所述第一导电部在所述衬底基板上的正投影之间。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    第一有源部，所述第一复位信号线在所述衬底基板上的正投影覆盖所述第一有源部在所述衬底基板上的正投影，所述第一有源部用于形成所述第一晶体管的沟道区；
    第二有源部，所述第二栅线在所述衬底基板上的正投影覆盖所述第二有源部在所述衬底基板上的正投影，所述第二有源部用于形成所述第二晶体管的沟道区；
    第十七有源部，连接于第一有源部；
    第二十有源部，连接于所述第二有源部；
    第五桥接部，所述第五桥接部在所述衬底基板上的正投影沿第二方向延伸，所述第二方向和所述第一方向相交，所述第五桥接部分别通过过孔连接所述第十七有源部和所述第二十有源部，且所述第五桥接部在所述衬底基板上的正投影与所述第二栅线在所述衬底基板上的正投影相交。
  3. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    第一有源部，所述第一复位信号线在所述衬底基板上的正投影覆盖所述第一有源部在所述衬底基板上的正投影，所述第一有源部用于形成所述第一晶体管的沟道区；
    第十七有源部，连接于第一有源部；
    第三有源部，所述第一导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第三有源部用于形成所述驱动晶体管的沟道区；
    第十八有源部，连接于所述第三有源部；
    第五桥接部，所述第五桥接部在所述衬底基板上的正投影沿第二方向延伸，所述第二方向和所述第一方向相交，所述第五桥接部分别通过过孔连接所述第十七有源部和第十八有源部，且所述第五桥接部在所述衬底基板上的正投影与所述第二栅线在所述衬底基板上的正投影相交。
  4. 根据权利要求2所述的显示面板，其中，所述显示面板还包括：
    第十九有源部，连接于所述第二有源部远离所述第二十有源部的一侧；
    第四桥接部，所述第四桥接部分别通过过孔连接所述第十九有源部和所述第一导电部；
    其中，所述第四桥接部在所述衬底基板上的正投影沿所述第二方向延伸且与所述第二栅线在所述衬底基板上的正投影相交。
  5. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    第一有源层，位于所述衬底基板的一侧，所述第一有源层包括第一有源部、第三有源部、第十七有源部、第十八有源部，所述第一有源部用于用于形成所述第一晶体管的沟道区，所述第三有源部用于形成所述驱动晶体管的沟道区，所述第十七有源部连接于第一有源部，所述第十八有源部连接于所述第三有源部；
    第一导电层，位于所述第一有源层背离所述衬底基板的一侧，所述第一导电层包括所述第一复位信号线、第一导电部；
    第二有源层，位于所述第一导电层背离所述衬底基板的一侧，所述第二有源层包括第二有源部、第十九有源部、第二十有源部，所述第二有源部用于形成所述第二晶体管的沟道区，所述第十九有源部和第二十有源部 分别连接于所述第二有源部的两端；
    第三导电层，位于所述第二有源层背离所述衬底基板的一侧，所述第三导电层包括所述第二栅线；
    第四导电层，位于所述第三导电层背离所述衬底基板的一侧，所述第四导电层包括第四桥接部、第五桥接部，所述第四桥接部分别通过过孔连接所述第十九有源部和所述第一导电部，所述第五桥接部分别通过过孔连接所述第十八有源部、第十七有源部、所述第二十有源部。
  6. 根据权利要求1所述的显示面板，其中，所述像素驱动电路还包括第四晶体管，所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极；
    所述显示面板还包括；
    第一有源层，位于所述衬底基板的一侧，所述第一有源层包括第三有源部和第四有源部，所述第三有源部用于形成所述驱动晶体管的沟道区，所述第四有源部用于形成所述第四晶体管的沟道区；
    第二有源层，位于所述第一有源层背离所述衬底基板的一侧，所述第二有源层包括第二有源部，所述第二栅线在所述衬底基板上的正投影覆盖所述第二有源部在所述衬底基板上的正投影，所述第二有源部用于形成所述第二晶体管的沟道区；
    其中，在所述第一方向上，所述第三有源部在所述衬底基板上的正投影位于所述第二有源部在所述衬底基板上的正投影和所述第四有源部在所述衬底基板上的正投影之间。
  7. 根据权利要求4所述的显示面板，其中，所述像素驱动电路还包括第四晶体管，所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极；
    所述显示面板还包括：
    第一导电层，位于所述衬底基板的一侧，所述第一导电层包括第一栅线，所述第一栅线在所述衬底基板上的正投影沿所述第一方向延伸且位于所述第一复位信号线在所述衬底基板上的正投影和所述第二栅线在所述衬底基板上的正投影之间，所述第一栅线的部分结构用于形成所述第四晶体管的栅极；
    其中，所述第十九有源部在所述衬底基板上的正投影与所述第一栅线在所述衬底基板上的正投影至少部分交叠。
  8. 根据权利要求7所述的显示面板，其中，所述第十九有源部在所述衬底基板上的正投影在所述第一方向上的最大尺寸大于所述第十九有源部在所述衬底基板上的正投影在第二方向上的最大尺寸。
  9. 根据权利要求8所述的显示面板，其中，所述第十九有源部在所述衬底基板上的正投影在所述第一方向上的最大尺寸为L1，所述第十九有源部在所述衬底基板上的正投影在第二方向上的最大尺寸为L2，L1/L2大于等于1.5且小于等于5。
  10. 根据权利要求1所述的显示面板，其中，所述像素驱动电路还包括第四晶体管，所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极，所述第四晶体管的栅极连接第一栅线；
    其中，所述第一导电部的等电位结构和所述第一栅线的等电位结构形成的电容容量为C1，所述第一导电部的等电位结构和所述第二栅线的等电位结构形成的电容容量为C2，C1大于C2。
  11. 根据权利要求10所述的显示面板，其中，所述显示面板还包括：
    第二有源部，用于形成所述第二晶体管的沟道区；
    第十九有源部，连接于所述第二有源部，所述第十九有源部在所述衬底基板上的正投影和所述第一栅线在所述衬底基板上的正投影至少部分交叠；
    第四桥接部，所述第四桥接部分别通过过孔连接所述第十九有源部和所述第一导电部，所述第四桥接部在所述衬底基板上的正投影沿所述第二方向延伸且与所述第二栅线在所述衬底基板上的正投影至少部分交叠；
    其中，所述第十九有源部在所述衬底基板上的正投影和所述第一栅线在所述衬底基板上的正投影的交叠面积为S1，所述第四桥接部在所述衬底基板上的正投影和所述第二栅线在所述衬底基板上的正投影的交叠面积为S2；
    S1/S2大于等于1.2且小于等于2。
  12. 根据权利要求1所述的显示面板，其中，所述显示面板还包括发 光单元，所述像素驱动电路用于驱动所述发光单元发光，所述像素驱动电路还包括第七晶体管，所述第七晶体管的第一极连接第二初始信号线，第二极连接所述发光单元的第一电极；
    所述显示面板还包括：
    第四导电层，位于所述衬底基板的一侧，所述第四导电层包括所述第二初始信号线；
    其中，所述第二初始信号线包括第一子初始信号线和第二子初始信号线，所述第一子初始信号线在所述衬底基板上的正投影沿所述第一方向延伸，所述第二子初始信号线在所述衬底基板上的正投影沿第二方向延伸，所述第二方向和所述第一方向相交；
    所述第一子初始信号线连接与其在所述衬底基板上正投影相交的所述第二子初始信号线。
  13. 根据权利要求1所述的显示面板，其中，所述像素驱动电路还包括第五晶体管，所述第五晶体管的第一极连接电源线，第二极连接所述驱动晶体管的第一极；
    所述显示面板还包括：
    第四导电层；
    第五导电层，位于所述第四导电层背离所述衬底基板的一侧，所述第五导电层包括所述电源线；
    所述电源线上形成有第一缺口，所述第一缺口至少部分位于所述显示面板的透光区。
  14. 根据权利要求13所述的显示面板，其中，所述电源线在所述衬底基板上的正投影沿第二方向延伸，所述第二方向和所述第一方向相交；
    所述电源线包括第一电源线段、第二电源线段、第三电源线段，所述第二电源线段连接于所述第一电源线段和所述第三电源线段之间；
    所述第二电源线段在所述衬底基板上的正投影在所述第一方向上的尺寸大于所述第一电源线段在所述衬底基板上的正投影在所述第一方向上的尺寸，所述第二电源线段在所述衬底基板上的正投影在所述第一方向上的尺寸大于所述第三电源线段在所述衬底基板上的正投影在所述第一方向上的尺寸；
    所述第一缺口包括第一侧边和第二侧边，所述第一侧边在所述衬底基板上的正投影和所述第二侧边在所述衬底基板上的正投影形成的夹角小于90°；
    且所述第一侧边由所述第二电源线段的部分边沿形成，所述第二侧边由所述第一电源线段的部分边沿形成。
  15. 根据权利要求1所述的显示面板，其中，所述像素驱动电路还包括电容，所述电容的第一电极连接所述驱动晶体管的栅极，所述电容的第二电极连接电源线，所述第一导电部复用为所述电容的第一电极；
    所述显示面板还包括：
    第一导电层，位于所述衬底基板的一侧；
    第二有源层，位于所述第一导电层背离所述衬底基板的一侧；
    第二导电层，位于所述第一导电层和所述第二有源层之间，所述第二导电层包括第二导电部，所述第二导电部在所述衬底基板上的正投影与所述第一导电部在所述衬底基板上的正投影至少部分交叠，所述第二导电部用于形成所述电容的第二电极；
    其中，在所述第一方向上相邻的至少部分所述第二导电部相连接。
  16. 根据权利要求15所述的显示面板，其中，所述显示面板包括沿所述第一方向和第二方向阵列分布的重复单元，所述第一方向和所述第二方向相交，所述重复单元包括在所述第一方向上分布的两个所述像素驱动电路，同一重复单元中两所述像素驱动电路至少部分镜像对称设置；
    所述第二导电层还包括：
    第一连接部，连接于同一所述重复单元中两所述第二导电部之间，所述第一连接部在所述衬底基板上的正投影在所述第二方向上的尺寸小于所述第二导电部在所述衬底基板上的正投影在所述第二方向上的尺寸，所述第一连接部和与其连接的所述第二导电部形成第三缺口；
    所述第三缺口在衬底基板上的正投影和所述驱动晶体管第二极的等电位结构在所述衬底基板上的正投影至少部分交叠。
  17. 根据权利要求15所述的显示面板，其中，所述显示面板包括沿所述第一方向和第二方向阵列分布的重复单元，所述第一方向和所述第二方向相交，所述重复单元包括在所述第一方向上分布的两个所述像素驱动 电路，同一重复单元中两所述像素驱动电路至少部分镜像对称设置；
    多条所述第二栅线连接同一信号端；
    所述第二导电层还包括：
    第二连接部，所述第二连接部连接于在所述第一方向上相邻的所述重复单元中两相邻所述第二导电部之间，所述第二连接部在所述衬底基板上的正投影在所述第二方向上的尺寸小于所述第二导电部在所述衬底基板上的正投影在所述第二方向上的尺寸，所述第二连接部和与其连接的所述第二导电部形成第二缺口；
    所述第二缺口在衬底基板上的正投影和所述驱动晶体管第一极的等电位结构在所述衬底基板上的正投影至少部分交叠。
  18. 根据权利要求1所述的显示面板，其中，所述显示面板还包括发光单元，所述像素驱动电路用于驱动所述发光单元发光，所述像素驱动电路还包括第七晶体管、第八晶体管，所述第七晶体管的第一极连接第二初始信号线，所述第七晶体管的第二极连接所述发光单元的第一电极，所述第八晶体管的第一极连接第三初始信号线，所述第八晶体管的第二极连接所述驱动晶体管的第一极；
    所述显示面板还包括：
    第一导电层，位于所述衬底基板的一侧，所述第一导电层包括第二复位信号线，所述第二复位信号线在所述衬底基板上的正投影沿所述第一方向延伸，且所述第二复位信号线的部分结构用于形成所述第七晶体管的栅极；
    第三导电层，位于所述第一导电层背离所述衬底基板的一侧，所述第三导电层包括所述第三初始信号线，所述第三初始信号线在所述衬底基板上的正投影沿所述第一方向延伸；
    其中，所述第二复位信号线在所述衬底基板上的正投影和所述第三初始信号线在所述衬底基板上的正投影至少部分交叠。
  19. 根据权利要求1所述的显示面板，其中，所述显示面板还包括发光单元，所述像素驱动电路用于驱动所述发光单元发光，所述像素驱动电路还包括：
    第四晶体管，第一极连接数据线，第二极连接所述驱动晶体管的第一 极；
    第五晶体管，第一极连接电源线，第二极连接所述驱动晶体管的第一极；
    第六晶体管，第一极连接所述驱动晶体管的第二极，第二极连接所述发光单元的第一电极；
    第七晶体管，第一极连接第二初始信号线，第二极连接所述发光单元的第一电极；
    第八晶体管，第一极连接第三初始信号线，第二极连接所述驱动晶体管的第一极；
    电容，连接于所述驱动晶体管栅极和所述电源线之间；
    所述显示面板还包括：
    第一有源层，所述第一有源层包括第一有源部、第三有源部、第四有源部、第五有源部、第六有源部、第七有源部、第八有源部，所述第一有源部用于形成所述第一晶体管的沟道区，所述第三有源部用于形成驱动晶体管的沟道区，所述第四有源部用于形成所述第四晶体管的沟道区，所述第五有源部用于形成第五晶体管的沟道区，所述第六有源部用于形成所述第六晶体管的沟道区，所述第七有源部用于形成所述第七晶体管的沟道区，所述第八有源部用于形成所述第八晶体管的沟道区；
    第一导电层，位于所述第一有源层背离所述衬底基板的一侧，所述第一导电层包括所述第一复位信号线、第一栅线、第二复位信号线、使能信号线、第一导电部，所述第一栅线的部分结构用于形成所述第四晶体管的栅极，所述使能信号线的部分结构分别用于形成所述第五晶体管、第六晶体管的栅极，所述第二复位信号线的部分结构分别用于形成所述第七晶体管和第八晶体管的栅极；
    第二有源层，位于所述第一导电层背离所述衬底基板的一侧，所述第二有源层包括第二有源部，所述第二有源部用于形成所述第二晶体管的沟道区；
    第三导电层，位于所述第二有源层背离所述衬底基板的一侧，所述第三导电层包括所述第二栅线；
    其中，所述使能信号线在所述衬底基板上的正投影沿所述第一方向延 伸且位于所述第一导电部在所述衬底基板上的正投影远离所述第一复位信号线在所述衬底基板上的正投影的一侧；
    所述第一栅线在所述衬底基板上的正投影沿所述第一方向延伸且位于所述第二栅线在所述衬底基板上的正投影和所述第一复位信号线在所述衬底基板上的正投影之间；
    所述第二复位信号线在所述衬底基板上的正投影沿所述第一方向延伸且位于所述使能信号线在所述衬底基板上的正投影远离所述第一导电部在所述衬底基板上的正投影的一侧。
  20. 根据权利要求19所述的显示面板，其中，所述第一晶体管、驱动晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管为P型晶体管，所述第二晶体管为N型晶体管。
  21. 一种显示装置，其中，所述显示装置包括权利要求1-20任一项所述的显示面板。
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