WO2022267001A1 - 像素驱动电路及其驱动方法、显示面板 - Google Patents

像素驱动电路及其驱动方法、显示面板 Download PDF

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Publication number
WO2022267001A1
WO2022267001A1 PCT/CN2021/102363 CN2021102363W WO2022267001A1 WO 2022267001 A1 WO2022267001 A1 WO 2022267001A1 CN 2021102363 W CN2021102363 W CN 2021102363W WO 2022267001 A1 WO2022267001 A1 WO 2022267001A1
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Prior art keywords
transistor
signal terminal
node
gate
active
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PCT/CN2021/102363
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English (en)
French (fr)
Inventor
青海刚
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180001638.5A priority Critical patent/CN115769297A/zh
Priority to US17/796,308 priority patent/US20240185780A1/en
Priority to EP21946495.5A priority patent/EP4207162A4/en
Priority to PCT/CN2021/102363 priority patent/WO2022267001A1/zh
Priority to KR1020237018810A priority patent/KR20240024766A/ko
Publication of WO2022267001A1 publication Critical patent/WO2022267001A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel driving circuit, a driving method thereof, and a display panel.
  • the display panel usually provides driving current to the light emitting unit through the pixel driving circuit to drive the light emitting unit to emit light.
  • the driving current output by the pixel driving circuit is related to the voltage of the power line.
  • the power lines at different positions on the display panel have different voltage drops, resulting in uneven display on the display panel.
  • a pixel driving circuit which includes: a driving circuit, a control circuit, a voltage stabilizing circuit, and a first storage circuit, and the driving circuit is connected to the first node, the second node, and the third node for According to the signal of the first node, the driving current is provided to the third node through the second node;
  • the control circuit is connected to the first enable signal terminal, the second node, the first power supply terminal, and the fourth node, and Connecting the second node and the fourth node in response to the signal of the first enabling signal terminal, and connecting the first power supply terminal and the fourth node in response to the signal of the first enabling signal terminal; stable
  • the voltage circuit is connected to the fourth node, the second enabling signal terminal, and the reference voltage terminal, and is used to transmit the signal of the reference voltage terminal to the fourth node in response to the signal of the second enabling signal terminal;
  • the first storage is connected between the first node and the fourth node, and is used for storing charges of the
  • the signal on the first enabling signal terminal is opposite in polarity to the signal on the second enabling signal terminal.
  • control circuit is further connected to the third node, the fifth node, and the first enabling signal terminal, and the control circuit is also configured to respond to the signal of the first enabling signal terminal to communicate with the third node and the fifth node.
  • the pixel driving circuit further includes: a first reset circuit connected to the initial signal terminal and the fifth node, and used to transmit the signal of the initial signal terminal to the fifth node in response to at least one control signal.
  • the first reset circuit is also connected to the second enable signal terminal, and the first reset circuit is used to respond to the signal of the second enable signal terminal to reset the initial The signal at the signal end is transmitted to the fifth node.
  • the driving circuit includes: a driving transistor, the first pole of which is connected to the second node, the second pole is connected to the third node, and the gate is connected to the first node .
  • the control circuit includes: a fifth transistor, an eighth transistor, and a sixth transistor. The first pole of the fifth transistor is connected to the second node, the second pole is connected to the fourth node, and the gate is connected to the first node.
  • the enable signal end; the first pole of the eighth transistor is connected to the fourth node, the second pole is connected to the first power supply end, and the gate is connected to the first enable signal end; the first pole of the sixth transistor is connected to the The fifth node, the second pole is connected to the third node, and the gate is connected to the first enable signal terminal.
  • the voltage stabilizing circuit includes: a third transistor, the first pole of the third transistor is connected to the reference voltage terminal, the second pole is connected to the fourth node, and the gate is connected to the second enabling signal terminal.
  • the first storage circuit includes: a first capacitor connected between the first node and the fourth node; the first reset circuit includes: a seventh transistor, a first pole of the seventh transistor connected to the initial signal terminal, the second pole is connected to the fifth node, and the gate is connected to the second enabling signal terminal.
  • the pixel driving circuit further includes: a data writing circuit and a compensation circuit, the data writing circuit is connected to the second node and the data signal terminal, and is used to respond to at least one control signal The signal of the data signal terminal is transmitted to the second node; the compensation circuit is connected to the third node and the first node, and is used to connect the first node and the third node in response to at least one control signal.
  • the data writing circuit is further connected to the first gate driving signal terminal, and the data writing circuit is used to respond to the signal of the first gate driving signal terminal to write the data signal to The signal at the terminal is transmitted to the second node;
  • the compensation circuit is also connected to the first gate drive signal terminal, and the compensation circuit is used to respond to the signal at the first gate drive signal terminal to communicate with the first node and the third node.
  • the data writing circuit is further connected to the second enabling signal terminal, and the data writing circuit is used to write the data signal to The signal at the end is transmitted to the second node; the compensation circuit is also connected to the second enable signal end, and the compensation circuit is used to respond to the signal at the second enable signal end to communicate with the first node and the Describe the third node.
  • the pixel driving circuit further includes: a second reset circuit, the second reset circuit is connected to the first node, the initial signal terminal, and the reset signal terminal, and is used to respond to the reset signal terminal A signal transmits a signal from the initial signal terminal to the first node.
  • the data writing circuit includes: a fourth transistor, the first pole of the fourth transistor is connected to the data signal terminal, the second pole is connected to the second node, and the gate is connected to the The first gate drive signal terminal.
  • the compensation circuit includes: a second transistor, the first pole of the second transistor is connected to the first node, the second pole is connected to the third node, and the gate is connected to the first gate drive signal terminal.
  • the second reset circuit includes: a first transistor, the first pole of the first transistor is connected to the initial signal terminal, the second pole is connected to the first node, and the gate is connected to the reset signal terminal.
  • the pixel driving circuit further includes: a second storage circuit connected between the second node and the fourth node for storing the second node and charge of the fourth node.
  • the data writing circuit is also connected to the first gate driving signal terminal, and the data writing circuit is used to transmit the signal of the data signal terminal to the second node in response to the signal of the first gate driving signal terminal;
  • the compensation circuit is also connected to the second gate driving signal terminal, and the compensation circuit is used for connecting the first node and the third node in response to the signal of the second gate driving signal terminal.
  • the pixel driving circuit further includes: a second reset circuit connected to the first node and an initial signal terminal, and configured to respond to at least one control signal to set the initial The signal at the signal end is transmitted to the first node.
  • the second reset circuit is further connected to a reset signal terminal, a first gate drive signal terminal, and a sixth node, and is used to connect to the initial signal terminal in response to a signal of the reset signal terminal and the sixth node, and for connecting the sixth node and the first node in response to the signal of the first gate driving signal terminal.
  • the data writing circuit includes: a fourth transistor, the first pole of the fourth transistor is connected to the data signal terminal, the second pole is connected to the second node, and the gate is connected to the The first gate drive signal terminal.
  • the compensation circuit includes: a second transistor, the first pole of the second transistor is connected to the first node, the second pole is connected to the third node, and the gate is connected to the second gate driving signal terminal.
  • the second reset circuit includes: a first transistor and a ninth transistor, the first pole of the first transistor is connected to the initial signal terminal, the second pole is connected to the sixth node, and the gate is connected to the reset signal terminal; The first pole of the nine transistors is connected to the sixth node, the second pole is connected to the first node, and the gate is connected to the first gate driving signal terminal.
  • the second storage circuit includes a second capacitor connected between the second node and the fourth node.
  • a driving method of a pixel driving circuit for driving the above-mentioned pixel driving circuit, wherein the driving method includes:
  • At least in the threshold compensation phase input an inactive level to the first enabling signal terminal, and input an active level to the second enabling signal terminal;
  • an active level is input to the first enabling signal terminal, and an inactive level is input to the second enabling signal terminal.
  • a driving method of a pixel driving circuit for driving the above-mentioned pixel driving circuit, wherein the driving method includes:
  • an active level is input to the reset signal terminal and the second enable signal terminal, and an inactive level is input to the first gate drive signal terminal and the first enable signal terminal;
  • an active level is input to the first gate drive signal terminal and the second enable signal terminal, and an inactive level is input to the reset signal terminal and the first enable signal terminal;
  • an active level is input to the first enable signal terminal, and an inactive level is input to the first gate drive signal terminal, the reset signal terminal, and the second enable signal terminal.
  • a driving method of a pixel driving circuit for driving the above-mentioned pixel driving circuit, wherein the driving method includes:
  • an active level is input to the reset signal terminal and the second enable signal terminal, and an inactive level is input to the first gate drive signal terminal, the first enable signal terminal, and the second gate drive signal terminal;
  • an active level is input to the reset signal terminal, the second enable signal terminal, and the first gate drive signal terminal, and an inactive level is input to the first enable signal terminal and the second gate drive signal terminal;
  • the first threshold compensation stage In the first threshold compensation stage, input an active level to the first gate drive signal terminal, the second enable signal terminal, and the second gate drive signal terminal, and input an invalid level to the reset signal terminal and the first enable signal terminal ;
  • an active level is input to the second enable signal terminal and the second gate drive signal terminal, and an invalid level is input to the first gate drive signal terminal, the reset signal terminal, and the first enable signal terminal ;
  • an active level is input to the first enable signal terminal, and an inactive level is input to the first gate drive signal terminal, the second gate drive signal terminal, the reset signal terminal, and the second enable signal terminal.
  • a display panel is provided, wherein the display panel includes the above-mentioned pixel driving circuit.
  • a display panel includes a pixel driving circuit
  • the pixel driving circuit includes: a driving transistor, a fifth transistor, an eighth transistor, a third transistor, and a first capacitor
  • the first pole of the fifth transistor is connected to the first pole of the driving transistor, and the gate is connected to the first enabling signal line;
  • the first pole of the eighth transistor is connected to the second pole of the fifth transistor, and the gate of the eighth transistor is connected to the second pole of the fifth transistor.
  • the two poles are connected to the power line, the gate is connected to the first enabling signal line; the first pole of the third transistor is connected to the reference voltage line, the second pole is connected to the second pole of the fifth transistor, and the gate is connected to the first Two enabling signal lines; the first capacitor is connected between the gate and the first electrode of the driving transistor.
  • the display panel further includes: a base substrate, an active layer, a first conductive layer, a second conductive layer, and a third conductive layer, and the active layer is located on the base substrate
  • the active layer includes: a tenth active portion, a third active portion, a fifth active portion, an eighth active portion, and an eleventh active portion, and the eleventh active portion is respectively connected to the third active part, the fifth active part, and the eighth active part, and the tenth active part is connected to an end of the fifth active part away from the eleventh active part;
  • the tenth active part is used to form the channel region of the driving transistor
  • the third active part is used to form the channel region of the third transistor
  • the fifth active part is used to form the channel region of the driving transistor.
  • a channel region of the fifth transistor is formed, and the eighth active portion is used to form a channel region of the eighth transistor.
  • the first conductive layer is located on the side of the active layer away from the base substrate, and the first conductive layer includes: a tenth conductive part, a first enable signal line, an eighth conductive part, a second enable signal line; wherein, the orthographic projection of the tenth conductive part on the base substrate covers the orthographic projection of the tenth active part on the base substrate, and the tenth conductive part is used to form the The gate of the drive transistor and the first electrode of the first capacitor; the orthographic projection of the first enable signal line on the base substrate extends along the first direction, and the first enable signal line The orthographic projection on the substrate covers the orthographic projection of the fifth active portion on the substrate, and the partial structure of the first enabling signal line is used to form the gate of the fifth transistor; The orthographic projection of the second enabling signal line on the substrate extends along the first direction, and the orthographic projection of the second enabling signal line
  • Orthographic projection on the base substrate the partial structure of the second enabling signal line is used to form the gate of the third transistor; the eighth conductive part is connected to the first enabling signal line, so The orthographic projection of the eighth conductive portion on the substrate covers the orthographic projection of the eighth active portion on the substrate, and the eighth conductive portion is used to form the gate of the eighth transistor. pole.
  • the second conductive layer is located on the side of the first conductive layer away from the base substrate, the second conductive layer includes an eleventh conductive part, and the positive side of the eleventh conductive part on the base substrate is The projection at least partially coincides with the orthographic projection of the tenth conductive portion on the base substrate, and the eleventh conductive portion is used to form the second electrode of the first capacitor.
  • the third conductive layer is located on the side of the second conductive layer away from the base substrate, and the third conductive layer includes: a first connecting portion, and the first connecting portion is respectively connected to the eleventh conductive layer through a via hole. active part and the eleventh conductive part.
  • the active layer further includes: a twelfth active part, a thirteenth active part, and the twelfth active part is connected to the eighth active part and is away from the One end of the eleventh active part; the thirteenth active part is connected to an end of the third active part away from the eleventh active part.
  • the third conductive layer further includes a reference voltage line, the orthographic projection of the reference voltage line on the base substrate extends along the first direction, and the reference voltage line is connected to the thirteenth active part through a via hole. .
  • the display panel further includes a fourth conductive layer, the fourth conductive layer is located on the side of the third conductive layer away from the base substrate, the fourth conductive layer includes the power line, and the power line is on the side of the base substrate.
  • the orthographic projection on the base substrate extends along a second direction, the first direction intersects with the second direction, and the power line is connected to the twelfth active part through a via hole.
  • the pixel driving circuit further includes a second transistor and a fourth transistor, the first pole of the second transistor is connected to the gate of the driving transistor, and the second pole is connected to the gate of the driving transistor.
  • the second pole of the transistor, the gate is connected to the first gate line
  • the first pole of the fourth transistor is connected to the data line
  • the second pole is connected to the first pole of the driving transistor
  • the gate is connected to the first gate line
  • There are a plurality of pixel driving circuits and the plurality of pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit distributed at intervals in the first direction
  • the first conductive layer further includes: a fourth A conductive part, a part of the structure of the fourth conductive part is used to form the gate of the second transistor in the first pixel driving circuit, and another part of the structure of the fourth conductive part is used to form the second pixel driving circuit
  • the gate of the fourth transistor there are multiple fourth conductive parts, and the orthographic projections of multiple fourth pixel .
  • the pixel driving circuit further includes a second transistor and a fourth transistor, the first pole of the second transistor is connected to the gate of the driving transistor, and the second pole is connected to the gate of the driving transistor.
  • the second pole of the transistor, the first pole of the fourth transistor is connected to the data line, and the second pole is connected to the first pole of the driving transistor.
  • the active layer further includes: a second active part and a fourteenth active part, the second active part is used to form the channel region of the second transistor; the fourteenth active part is connected to the second an active part, and the fourteenth active part is used to connect to the tenth conductive part.
  • the second conductive layer further includes: a twelfth conductive part, the twelfth conductive part is connected to the eleventh conductive part, and the orthographic projection of the twelfth conductive part on the base substrate is along the The second direction extends, and the orthographic projection of the twelfth conductive part on the base substrate is at least partly located between the orthographic projection of the fourteenth active part on the base substrate and the data line. between the orthographic projections on the substrate substrate.
  • the multiple pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit distributed in the first direction at intervals;
  • the first conductive layer further includes: a fourth conductive part, a part of the structure of the fourth conductive part is used to form the gate of the second transistor in the first pixel driving circuit, and another part of the structure of the fourth conductive part It is used to form the gate of the fourth transistor in the second pixel driving circuit;
  • there are multiple fourth conductive parts and the orthographic projection of the multiple fourth conductive parts on the base substrate is on the first Distributed at intervals in one direction; the orthographic projection of the twelfth conductive portion on the base substrate is located between two adjacent fourth conductive portions in the first direction on the base substrate between orthographic projections.
  • the pixel driving circuit further includes a second transistor, the first pole of the second transistor is connected to the gate of the driving transistor, and the second pole is connected to the second gate of the driving transistor. pole;
  • the active layer further includes: a second active portion, a fourteenth active portion, the second active portion is used to form the channel region of the second transistor; the fourteenth active portion is connected to the The second active part, and the fourteenth active part is used to connect the tenth conductive part;
  • the orthographic projections on the base substrate are at least partially coincident.
  • the pixel driving circuit further includes a second transistor, the first pole of the second transistor is connected to the gate of the driving transistor, and the second pole is connected to the second gate of the driving transistor. pole.
  • the active layer further includes: a second active part and a fourteenth active part, the second active part is used to form the channel region of the second transistor; the fourteenth active part is connected to the second an active part, and the fourteenth active part is used to connect to the tenth conductive part.
  • the third conductive layer further includes: a second connection part, the second connection part is respectively connected to the tenth conductive part and the fourteenth active part through via holes, and the power line is connected to the substrate
  • the orthographic projection on the substrate at least partially coincides with the orthographic projection of the second connecting portion on the base substrate.
  • the display panel further includes a light-emitting unit
  • the pixel driving circuit is connected to the first electrode of the light-emitting unit
  • the pixel driving circuit further includes a first transistor and a seventh transistor.
  • the first pole of the first transistor is connected to the first initial signal line
  • the second pole is connected to the gate of the driving transistor
  • the first pole of the seventh transistor is connected to the second initial signal line
  • the second pole is connected to the light emitting the first electrode of the unit.
  • the active layer further includes: a first active portion, a seventh active portion, a first initial signal line, and a second initial signal line, the first active portion is used to form a channel region of the first transistor;
  • the seventh active part is used to form the channel region of the seventh transistor;
  • the first initial signal line is connected to an end of the first active part away from the tenth active part;
  • the second initial signal line is connected to The seventh active part is far away from an end of the tenth active part.
  • the pixel driving circuit further includes a first transistor, the first electrode of the first transistor is connected to the first initial signal line, the second electrode is connected to the gate of the driving transistor, and the gate The pole is connected to the reset line;
  • the first conductive layer further includes: a plurality of first conductive parts, and the orthographic projections of the plurality of first conductive parts on the base substrate are distributed at intervals in the first direction, so Part of the structure of the first conductive part is used to form the gate of the first transistor, and another part of the structure of the first conductive part is used to form the gate of the first transistor in the same pixel driving circuit;
  • the third conductive layer further includes the reset lines, the orthographic projection of the reset lines on the base substrate extends along the first direction, and the reset lines are respectively connected in the first direction through via holes. A plurality of the first conductive parts are distributed, and the sheet resistance of the third conductive layer is smaller than the sheet resistance of the first conductive layer.
  • the pixel driving circuit further includes a fourth transistor and a ninth transistor, the first pole of the fourth transistor is connected to the data line, and the second pole is connected to the first pole of the driving transistor. , the gate is connected to the first gate line, the first pole of the ninth transistor is connected to the initial signal line, the second pole is connected to the gate of the driving transistor, and the gate is connected to the first gate line.
  • the first conductive layer further includes: a plurality of ninth conductive parts, the orthographic projections of the plurality of ninth conductive parts on the base substrate are distributed at intervals in the first direction, and the ninth conductive parts A part of the structure of the ninth conductive part is used to form the gate of the fourth transistor, and another part of the structure of the ninth conductive part is used to form the gate of the ninth transistor in the same pixel driving circuit.
  • the third conductive layer further includes: the first gate lines, the orthographic projection of the first gate lines on the base substrate extends along the first direction, and the first gate lines are respectively connected to the For the plurality of ninth conductive portions distributed in the first direction, the sheet resistance of the third conductive layer is smaller than the sheet resistance of the first conductive layer.
  • the pixel driving circuit further includes a second transistor, the first pole of the second transistor is connected to the gate of the driving crystal, and the second pole is connected to the second gate of the driving transistor. electrode, and the gate is connected to the second gate line.
  • the first conductive layer further includes: a plurality of second conductive parts, the orthographic projections of the plurality of second conductive parts on the base substrate are distributed at intervals along the first direction, and the second conductive parts use for forming the gate of the second transistor.
  • the third conductive layer further includes: the second gate lines, the orthographic projection of the second gate lines on the base substrate extends along the first direction, and the second gate lines are respectively connected to the A plurality of the second conductive parts distributed in the first direction.
  • the active layer further includes: a twelfth active part, a thirteenth active part, and the twelfth active part is connected to the eighth active part and is away from the One end of the eleventh active part; the thirteenth active part is connected to an end of the third active part away from the eleventh active part.
  • the third conductive layer further includes: a power line, the orthographic projection of the power line on the base substrate extends along a second direction, the second direction intersects the first direction, and the power line passes through the via hole Connect the twelfth active part.
  • the display panel further includes: a fourth conductive layer, the fourth conductive layer is located on the side of the third conductive layer away from the base substrate, the fourth conductive layer includes the reference voltage line, and the reference voltage An orthographic projection of the line on the base substrate extends along the second direction, and the reference voltage line is connected to the thirteenth active part through a via hole.
  • the pixel driving circuit further includes a first transistor, a first pole of the first transistor is connected to the initial signal line, and a second pole is connected to the gate of the driving transistor.
  • the active layer further includes: a first sub-active portion, a second sub-active portion, and a third sub-active portion, the first sub-active portion is used to form the first channel region of the first transistor;
  • the second sub-active part is used to form the second channel region of the first transistor;
  • the third sub-active part is connected between the first sub-active part and the second sub-active part.
  • An orthographic projection of the power line on the base substrate is at least partially coincident with an orthographic projection of the third sub-active portion on the base substrate.
  • the pixel driving circuit further includes a second transistor, the first pole of the second transistor is connected to the gate of the driving transistor, and the second pole is connected to the second gate of the driving transistor.
  • the active layer further includes: a fourth sub-active portion, a fifth sub-active portion, and a sixth sub-active portion, and the fourth sub-active portion is used to form a channel region of the second transistor;
  • the fifth sub-active part is used to form the channel region of the second transistor;
  • the sixth sub-active part is connected between the fourth sub-active part and the fifth sub-active part.
  • the fourth conductive layer further includes: a seventeenth conductive part, the seventeenth conductive part is connected to the reference voltage line; the display panel includes first pixel drive circuits and The second pixel driving circuit; wherein, the orthographic projection of the seventeenth conductive part in the first pixel driving circuit on the substrate is the same as that of the sixth sub-active part in the second pixel driving circuit on the substrate The orthographic projections on the base substrate are at least partially coincident.
  • the display panel further includes a light-emitting unit
  • the pixel driving circuit is connected to the first electrode of the light-emitting unit
  • the pixel driving circuit further includes a first transistor and a seventh transistor.
  • the first pole of the first transistor is connected to the initial signal line
  • the second pole is connected to the gate of the driving transistor
  • the first pole of the seventh transistor is connected to the initial signal line
  • the second pole is connected to the light emitting unit.
  • first electrode There are a plurality of pixel driving circuits, the plurality of pixel driving circuits include a third pixel driving circuit and a fourth pixel driving circuit adjacent in a second direction, and the first direction intersects with the second direction.
  • the active layer may further include: a first active portion, a seventh active portion, and a fifteenth active portion, the first active portion is used to form a channel region of the first transistor; the seventh active portion The part is used to form the channel region of the seventh transistor; the fifteenth active part is connected to the first active part in the third pixel driving circuit and the seventh active part in the fourth pixel driving circuit between departments.
  • the display panel further includes: a fourth conductive layer, the fourth conductive layer includes the initial signal line, the orthographic projection of the initial signal line on the base substrate extends along the second direction, and the initial signal line The line is connected to the fifteenth active part through the via hole.
  • the pixel driving circuit further includes a second transistor, the first pole of the second transistor is connected to the gate of the driving transistor, and the second pole is connected to the second gate of the driving transistor. pole.
  • the active layer further includes: a second active part and a fourteenth active part, the second active part is used to form the channel region of the second transistor; the fourteenth active part is connected to the second an active part, and the fourteenth active part is used to connect to the tenth conductive part.
  • the initial signal line includes a first sub-initial signal line, an orthographic projection of the first sub-initial signal line on the base substrate and an orthographic projection of the fourteenth active portion on the base substrate at least partially coincident.
  • the pixel driving circuit further includes a second transistor, the first pole of the second transistor is connected to the gate of the driving transistor, and the second pole is connected to the second gate of the driving transistor. pole.
  • the active layer further includes: a second active part and a fourteenth active part, the second active part is used to form the channel region of the second transistor; the fourteenth active part is connected to the second an active part, and the fourteenth active part is used to connect to the tenth conductive part.
  • the third conductive layer further includes: a second connection part, the second connection part is respectively connected to the tenth conductive part and the fourteenth active part through via holes; the initial signal line includes a first sub For the initial signal line, the orthographic projection of the first sub-initial signal line on the base substrate at least partially coincides with the orthographic projection of the second connecting portion on the base substrate.
  • the initial signal line further includes a second sub-initial signal line, the second sub-initial signal line is connected to the first sub-initial signal line, and the second sub-initial signal line
  • An orthographic projection of the line on the base substrate at least partially coincides with an orthographic projection of the power line on the base substrate.
  • the pixel driving circuit further includes a first transistor, a second transistor, and a fourth transistor, the first pole of the first transistor is connected to the initial signal line, and the second pole is connected to the driving The gate of the transistor, the gate is connected to the reset signal line, the first pole of the second transistor is connected to the gate of the driving transistor, the second pole is connected to the second pole of the driving transistor, and the first pole of the fourth transistor One pole is connected to the data line, and the second pole is connected to the first pole of the driving transistor.
  • the active layer further includes: a second active part and a fourteenth active part, the second active part is used to form the channel region of the second transistor; the fourteenth active part is connected to the second an active part, and the fourteenth active part is used to connect to the tenth conductive part.
  • the second conductive layer further includes: the reset signal line, a thirteenth conductive part, the orthographic projection of the reset signal line on the base substrate extends along the first direction; the thirteenth conductive part is connected to For the reset signal line, the orthographic projection of the thirteenth conductive part on the base substrate is located at the same position as the orthographic projection of the fourteenth active part on the base substrate between the orthographic projections on the substrate substrate.
  • the active layer further includes: an active line, and the orthographic projection of the active line on the base substrate is along the The first direction extends, and the active line connects a plurality of the fifteenth active parts distributed in the first direction.
  • the pixel driving circuit further includes a second capacitor, the first electrode of the second capacitor is connected to the second electrode of the fifth transistor, and the second electrode of the second capacitor connected to the first pole of the driving transistor.
  • the active layer further includes: a sixteenth active part, the sixteenth active part is connected to an end of the fifth active part away from the eleventh active part, and the sixteenth active part A second electrode for forming the second capacitor.
  • the second conductive layer further includes: a fourteenth conductive part, the fourteenth conductive part is connected to the eleventh conductive part, and the orthographic projection of the fourteenth conductive part on the base substrate is the same as the Orthographic projections of the sixteenth active portion on the base substrate are at least partially overlapped, and the fourteenth conductive portion is used to form the first electrode of the second capacitor.
  • FIG. 1 is a schematic diagram of a circuit structure of a pixel driving circuit in the related art
  • FIG. 2 is a timing diagram of each node in a driving method of the pixel driving circuit in FIG. 1;
  • FIG. 3 is a schematic structural diagram of an exemplary embodiment of a pixel driving circuit of the present disclosure
  • FIG. 4 is a timing diagram of each node of the pixel driving circuit in FIG. 3;
  • FIG. 5 is a schematic structural diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure.
  • FIG. 6 is a sequence diagram of each node in FIG. 5;
  • FIG. 7 is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit of the present disclosure.
  • FIG. 8 is a timing diagram of each node of the pixel driving circuit in FIG. 7;
  • FIG. 9 is a structural layout of an exemplary embodiment of a display panel of the present disclosure.
  • FIG. 10 is a structural layout of the active layer in FIG. 9;
  • FIG. 11 is a structural layout of the first conductive layer in FIG. 9;
  • FIG. 12 is a structural layout of the second conductive layer in FIG. 9;
  • FIG. 13 is a structural layout of the third conductive layer in FIG. 9;
  • FIG. 14 is a structural layout of the fourth conductive layer in FIG. 9;
  • FIG. 15 is a structural layout of the active layer and the first conductive layer in FIG. 9;
  • FIG. 16 is a structural layout of the active layer, the first conductive layer, and the second conductive layer in FIG. 9;
  • FIG. 17 is a structural layout of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in FIG. 9;
  • Fig. 18 is a partial cross-sectional view at the position of dotted line A in Fig. 9;
  • FIG. 19 is a structural layout of an exemplary embodiment of a display panel of the present disclosure.
  • FIG. 20 is a structural layout of the active layer in FIG. 19;
  • FIG. 21 is a structural layout of the first conductive layer in FIG. 19;
  • FIG. 22 is a structural layout of the second conductive layer in FIG. 19;
  • FIG. 23 is a structural layout of the third conductive layer in FIG. 19;
  • FIG. 24 is a structural layout of the fourth conductive layer in FIG. 19;
  • FIG. 25 is a structural layout of the active layer and the first conductive layer in FIG. 19;
  • FIG. 26 is a structural layout of the active layer, the first conductive layer, and the second conductive layer in FIG. 19;
  • FIG. 27 is a structural layout of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in FIG. 19;
  • Fig. 28 is a partial cross-sectional view at the position of dotted line B in Fig. 19;
  • FIG. 29 is a structural layout of an exemplary embodiment of a display panel of the present disclosure.
  • FIG. 30 is a structural layout of the active layer in FIG. 29;
  • FIG. 31 is a structural layout of the first conductive layer in FIG. 29;
  • FIG. 32 is a structural layout of the second conductive layer in FIG. 29;
  • FIG. 33 is a structural layout of the third conductive layer in FIG. 29;
  • FIG. 34 is a structural layout of the fourth conductive layer in FIG. 29;
  • FIG. 35 is a structural layout of the active layer and the first conductive layer in FIG. 29;
  • FIG. 36 is a structural layout of the active layer, the first conductive layer, and the second conductive layer in FIG. 29;
  • FIG. 37 is a structural layout of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in FIG. 29;
  • FIG. 38 is a partial cross-sectional view at the position of the dotted line C in FIG. 29 .
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C.
  • the first pole of the first transistor T1 is connected to the first node N1, the second pole is connected to the initial signal terminal Vinit, and the gate is connected to the reset signal terminal Re;
  • the first pole of the second transistor T2 is connected to the first pole of the driving transistor T3, and The two poles are connected to the first node N1;
  • the gate is connected to the gate drive signal terminal Gate;
  • the gate of the driving transistor T3 is connected to the first node N1;
  • the first pole of the fourth transistor T4 is connected to the data signal terminal Data, and the second pole is connected to the driving transistor.
  • the second pole of T3, the gate is connected to the gate drive signal terminal Gate;
  • the first pole of the fifth transistor T5 is connected to the first power supply terminal VDD, the second pole is connected to the second pole of the driving transistor T3, and the gate is connected to the enable signal terminal EM;
  • the first pole of the sixth transistor T6 is connected to the first pole of the driving transistor T3, and the gate is connected to the enable signal terminal EM;
  • the first pole of the seventh transistor T7 is connected to the initial signal terminal Vinit, and the second pole is connected to the sixth transistor T6. second pole.
  • the pixel driving circuit may be connected to a light emitting unit OLED for driving the light emitting unit OLED to emit light, and the light emitting unit OLED may be connected between the second pole of the sixth transistor T6 and the second power supply terminal VSS.
  • the transistors T1-T7 may all be P-type transistors.
  • FIG. 2 it is a timing diagram of each node in a driving method of the pixel driving circuit in FIG. 1 .
  • Gate represents the timing of the gate drive signal terminal Gate
  • Re represents the timing of the reset signal terminal Re
  • EM represents the timing of the enable signal terminal EM
  • Data represents the timing of the data signal terminal Data.
  • the driving method of the pixel driving circuit may include a reset phase t1, a compensation phase t2, and a light emitting phase t3.
  • the reset phase t1 the reset signal terminal Re outputs a low-level signal
  • the first transistor T1 and the seventh transistor T7 are turned on, and the initial signal terminal Vinit inputs an initialization signal to the first node N1 and the second pole of the sixth transistor T6.
  • the gate drive signal terminal Gate outputs a low-level signal
  • the fourth transistor T4 and the second transistor T2 are turned on, and at the same time, the data signal terminal Data outputs a drive signal to write the voltage Vdata+Vth to the first node N1, Wherein Vdata is the voltage of the driving signal, and Vth is the threshold voltage of the driving transistor T3.
  • Light-emitting stage t3 the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata+Vth stored in the capacitor C.
  • the driving transistor output current formula I ( ⁇ WCox/2L)(Vgs-Vth) 2 , where ⁇ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, and L drives The length of the transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor.
  • the pixel driving circuit can avoid the influence of the threshold value of the driving transistor on its output current.
  • the first power terminal is provided by the power line on the display panel, however, due to the voltage drop (IR-drop) of the power line itself, the power lines at different positions on the display panel have different voltages, thus causing the display panel to operate at the same Display is uneven in grayscale. The problem of uneven display is especially obvious in large-size display panels or vertical screens.
  • this exemplary embodiment provides a pixel driving circuit, wherein, as shown in FIG. 3 , it is a schematic structural diagram of an exemplary embodiment of the pixel driving circuit of the present disclosure.
  • the pixel driving circuit may include: a driving circuit 01, The control circuit 02, the voltage stabilizing circuit 03, the first storage circuit 04, and the driving circuit 01 can be connected to the first node N1, the second node N2, and the third node N3, and are used to pass the first node N1 according to the signal of the first node N1.
  • the second node N2 provides driving current to the third node N3; the control circuit 02 can be connected to the first enable signal terminal EM1, the second node N2, the first power supply terminal VDD, and the fourth node N4 for responding to the
  • the signal of the first enable signal terminal EM1 is connected to the second node N2 and the fourth node N4, and is used to connect the first power supply terminal VDD and the fourth node in response to the signal of the first enable signal terminal EM1.
  • the voltage stabilizing circuit 03 can be connected to the fourth node N4, the second enabling signal terminal EM2, and the reference voltage terminal Vref, for responding to the signal of the second enabling signal terminal EM2, the reference voltage terminal Vref
  • the signal is transmitted to the fourth node N4;
  • the first storage circuit 04 is connected between the first node N1 and the fourth node N4 for storing the first node N1 and the fourth node N4 charge.
  • the driving circuit 01 may include: a driving transistor DTFT, the first pole of the driving transistor DTFT is connected to the second node N2, the second pole is connected to the third node N3, and the gate is connected to the The first node N1.
  • the control circuit 02 may include: a fifth transistor T5 and an eighth transistor T8, the first pole of the fifth transistor T5 is connected to the second node N2, the second pole is connected to the fourth node N4, and the gate is connected to the The first enabling signal terminal EM1; the first pole of the eighth transistor T8 is connected to the fourth node N4, the second pole is connected to the first power supply terminal VDD, and the gate is connected to the first enabling signal terminal EM1.
  • the voltage stabilizing circuit 03 may include: a third transistor T3, the first pole of the third transistor T3 is connected to the reference voltage terminal Vref, the second pole is connected to the fourth node N4, and the gate is connected to the second enable Signal terminal EM2.
  • the first storage circuit 04 may include: a first capacitor C1 connected between the first node N1 and the fourth node N4.
  • the pixel driving circuit provided by this exemplary embodiment can input an active level to the second enable signal terminal and an inactive level to the first enable signal terminal at least in the threshold compensation stage, so that the signal on the reference voltage terminal Vref
  • the first node N1 will be written with a voltage of Vdata+Vth, where Vdata is the data signal, and Vth is the threshold voltage of the driving transistor.
  • Vdata+Vth-Vref the voltage difference between the two ends of the first capacitor C1 It is Vdata+Vth-Vref
  • Vref is the voltage of the reference voltage terminal.
  • an active level can be input to the first enable signal terminal EM1
  • an inactive level can be input to the second enable signal terminal EM2.
  • the current output by the pixel driving circuit has nothing to do with the voltage of the first power supply terminal VDD, that is, the display panel using the pixel driving circuit will not cause uneven display due to the voltage drop of the source line itself.
  • the reference voltage line used to provide the reference voltage terminal itself has resistance, there is no current on the reference voltage line after the reference voltage terminal Vref writes a voltage to the first capacitor C1, so no voltage will be generated on the reference voltage line. drop, that is, the voltage of the reference voltage terminal at different positions of the display panel will not vary due to the resistance of the reference voltage line itself.
  • the driving circuit, the first storage circuit, and the control circuit may also have other structures.
  • the driving circuit may include multiple driving transistors connected in parallel
  • the first storage circuit may include multiple capacitors in parallel.
  • this embodiment in order to ensure that the voltage across the first capacitor C1 is Vdata+Vth-Vref at the end of the threshold compensation phase, this embodiment needs to input an active level to the second enable signal terminal EM2 at least during the threshold compensation phase .
  • an active level can also be input to the second enable signal terminal EM2 in other stages than the light-emitting stage, for example, it can be input to the second enable signal terminal EM2 in the reset stage before the threshold compensation stage.
  • the enable signal terminal EM2 inputs an active level so that the reference voltage terminal Vref precharges the fourth node N4, so as to ensure that the same voltage can be written into the fourth node N4 at different positions of the display panel before the end of the threshold compensation phase.
  • the signal on the first enable signal terminal EM1 may be opposite in polarity to the signal on the second enable signal terminal EM2 .
  • control circuit 02 can also be connected to the third node N3, the fifth node N5, and the first enable signal terminal EM1, and the control circuit 02 is also used to respond to The signal of the first enable signal terminal EM1 is connected to the third node N3 and the fifth node N5.
  • the control circuit 02 may further include a sixth transistor.
  • the first pole of the sixth transistor T6 is connected to the fifth node N5
  • the second pole is connected to the third node N3
  • the gate is connected to the first enable signal terminal EM1 .
  • the pixel driving circuit may further include: a first reset circuit 05, which is connected to the initial signal terminal Vinit and the fifth node N5, and is used to transmit the signal of the initial signal terminal Vinit to the initial signal terminal Vinit in response to at least one control signal Describe the fifth node N5.
  • the first reset circuit 05 can be connected to the second enable signal terminal EM2, and the first reset circuit 05 can be used to respond to the signal of the second enable signal terminal EM2 to switch the initial signal terminal Vinit The signal of is transmitted to the fifth node N5.
  • the first reset circuit 05 may include: a seventh transistor T7, the first pole of the seventh transistor T7 is connected to the initial signal terminal Vinit, the second pole is connected to the fifth node N5, and the gate is connected to the second enabling terminal. Can signal terminal EM2.
  • the pixel driving circuit may further include: a data writing circuit 06, a compensation circuit 07, and the data writing circuit 06 may be connected to the second node N2, the data signal terminal Vdata , used to transmit the signal of the data signal terminal Vdata to the second node N2 in response to at least one control signal; the compensation circuit 07 can be connected to the third node N3 and the first node N1, and used to respond to at least one control signal to communicate with the first node N1 and the third node N3.
  • the data writing circuit 06 can be connected to the first gate driving signal terminal Gate1, and the data writing circuit 06 can be used to respond to the signal of the first gate driving signal terminal Gate1
  • the signal of the data signal terminal Vdata is transmitted to the second node N2;
  • the compensation circuit 07 can be connected to the first gate drive signal terminal Gate1, and the compensation circuit 07 can be used to respond to the first gate drive
  • the signal at the signal terminal Gate1 is connected to the first node N1 and the third node N3.
  • the pixel drive circuit may further include: a second reset circuit 09 connected to the first node N1, the initial signal terminal Vinit, and the reset signal terminal Reset The second reset circuit 09 is configured to transmit the signal of the initial signal terminal Vinit to the first node N1 in response to the signal of the reset signal terminal Reset.
  • the data writing circuit 06 may include: a fourth transistor T4, the first pole of the fourth transistor T4 is connected to the data signal terminal Vdata, and the second pole is connected to the The gate of the second node N2 is connected to the first gate driving signal terminal Gate1.
  • the compensation circuit 07 may include: a second transistor T2, the first pole of the second transistor T2 is connected to the first node N1, the second pole is connected to the third node N3, and the gate is connected to the first gate driver Signal terminal Gate1.
  • the second reset circuit 09 may include: a first transistor T1, the first pole of the first transistor T1 is connected to the initial signal terminal Vinit, the second pole is connected to the first node N1, and the gate is connected to the reset signal terminal Reset.
  • the fifth node N5 can be used to connect the first electrode of a light emitting unit OLED, the second electrode of the light emitting unit OLED can be connected to the second power supply terminal VSS, and the light emitting unit OLED can be a light emitting diode.
  • the first transistor T1 to the eighth transistor T8 and the driving transistor DTFT can all be P-type transistors, the first power supply terminal VDD can be a high-level signal terminal, and the second power supply terminal VSS can be a low-level signal terminal.
  • FIG. 4 it is a timing diagram of each node of the pixel driving circuit in FIG. 3 .
  • Reset is the timing diagram of the reset signal terminal Reset
  • Vinit is the timing diagram of the initial signal terminal Vinit
  • EM1 is the timing diagram of the first enabling signal terminal EM1
  • EM2 is the timing diagram of the second enabling signal terminal EM2
  • Vdata is The timing diagram of the data signal terminal Vdata
  • Gate1 is the timing diagram of the first gate driving signal terminal Gate1.
  • the driving method of the pixel driving circuit may include four stages: a reset stage t1, a threshold compensation stage t2, a buffer stage t3, and a light emitting stage t4.
  • an active level (low level) can be input to the reset signal terminal Reset and the second enable signal terminal EM2, and an inactive level can be input to the first gate drive signal terminal Gate1 and the first enable signal terminal EM1 (high level).
  • the first transistor T1, the seventh transistor T7, and the third transistor T3 are turned on, the initial signal terminal Vinit inputs initial signals to the first node N1 and the fifth node N5, and the reference voltage terminal Vref precharges the reference voltage to the fourth node N4, wherein , writing the initial signal to the fifth node N5 can eliminate the carriers that are not recombined on the light-emitting interface inside the light-emitting diode, and alleviate the aging of the light-emitting diode.
  • an active level is input to the first gate drive signal terminal Gate1 and the second enable signal terminal EM2, an inactive level is input to the reset signal terminal Reset and the first enable signal terminal EM1, and the second transistor T2 , the fourth transistor T4, the seventh transistor T7, and the third transistor T3 are turned on, the reference voltage terminal Vref continues to write the reference voltage to the fourth node N4, and the data signal terminal Vdata writes the voltage Vdata+Vth to the first node N1, and this , the voltage across the first capacitor C1 is Vdata+Vth-Vref, where Vdata is the voltage at the data signal terminal, Vth is the threshold voltage of the driving transistor, and Vref is the voltage at the reference voltage terminal.
  • an active level is input to the second enable signal terminal EM2, and an inactive level is input to the first gate drive signal terminal Gate1, the reset signal terminal Reset, and the first enable signal terminal EM1.
  • the voltage across the first capacitor C1 maintains Vdata+Vth-Vref.
  • an active level is input to the first enable signal terminal EM1
  • an inactive level is input to the first gate drive signal terminal Gate1, the reset signal terminal Reset, and the second enable signal terminal EM2.
  • the current output by the pixel driving circuit has nothing to do with the voltage of the first power supply terminal VDD, that is, the display panel using the pixel driving circuit will not cause uneven display due to the voltage drop of the source line itself.
  • the data writing circuit 06, the compensation circuit 07, and the first reset circuit 05 may also have other connection modes.
  • the pixel driving circuit of the present disclosure Schematic diagram of the structure in another exemplary embodiment.
  • the data write-in circuit 06 can be connected to the second enable signal terminal EM2, and the data write-in circuit 06 is used to respond to the signal of the second enable signal terminal EM2 to write the data signal terminal Vdata
  • the signal is transmitted to the second node N2;
  • the compensation circuit 07 can be connected to the second enable signal terminal EM2, and the compensation circuit is used to respond to the signal of the second enable signal terminal EM2 to communicate with the first A node N1 and the third node N3;
  • the first reset circuit 05 can be connected to the reset signal terminal Reset, and the first reset circuit is used to transmit the signal of the initial signal terminal Vinit to the fifth node N5 in response to the signal of the reset signal terminal Reset . As shown in FIG.
  • the driving method of the pixel driving circuit may also include four stages: a reset stage t1 , a threshold compensation stage t2 , a buffer stage t3 , and a light emitting stage t4 .
  • the difference between the pixel driving circuit shown in FIG. 5 and the pixel driving circuit shown in FIG. 3 is that the pixel driving circuit shown in FIG. 5 can only control the data writing circuit 06, the compensation circuit 07, and the voltage stabilizing circuit through the second enable signal terminal EM2. 03, so that the voltage Vdata+Vth-Vref is written to both ends of the first capacitor C1 in the threshold compensation stage.
  • the driving method of the pixel driving circuit shown in FIG. 3 and FIG. 5 may not set a buffer stage.
  • the control terminal of the first reset circuit 05 in FIG. 5 can also share the second enable signal terminal EM2, that is, the gate of the seventh transistor T7 can be connected to the second enable signal terminal.
  • the control terminal of the first reset circuit 05 in FIG. 3 may share the reset signal terminal Reset, that is, the gate of the seventh transistor T7 may be connected to the reset signal terminal Reset.
  • the first reset circuit and the second reset circuit may also be connected to initial signal terminals with different potentials.
  • the pixel driving circuit may further include: a second storage circuit 08, which may be connected between the second node N2 and the fourth node N4, and is used for storing the second node N2 and the fourth node N2. The charge of the four-node N4.
  • the data writing circuit 06 can also be connected to the first gate driving signal terminal Gate1, and the data writing circuit 06 can be used to respond to the signal of the first gate driving signal terminal Gate1 to write the data signal terminal Vdata
  • the signal is transmitted to the second node N2;
  • the compensation circuit 07 can also be connected to the second gate drive signal terminal Gate2, and the compensation circuit 07 can be used to respond to the signal of the second gate drive signal terminal Gate2 to connect The first node N1 and the third node N3.
  • the second reset circuit 09 may be connected to the first node N1 and the initial signal terminal Vinit, and is used to transmit the signal of the initial signal terminal Vinit to the first node in response to at least one control signal N1.
  • the second reset circuit 09 can be connected to the reset signal terminal Reset, the first gate drive signal terminal Gate1, and the sixth node N6, and is used to connect the initial signal terminal Vinit and the initial signal terminal Vinit in response to the signal of the reset signal terminal Reset.
  • the sixth node N6 is used to connect the sixth node N6 with the first node N1 in response to the signal of the first gate driving signal terminal Gate1.
  • the data writing circuit 06 may include: a fourth transistor T4, the first pole of the fourth transistor T4 is connected to the data signal terminal Vdata, and the second pole is connected to the The gate of the second node N2 is connected to the first gate driving signal terminal Gate1.
  • the compensation circuit 07 may include: a second transistor T2, the first pole of the second transistor T2 is connected to the first node N1, the second pole is connected to the third node N3, and the gate is connected to the second gate driver Signal terminal Gate2.
  • the second reset circuit 09 may include: a first transistor T1 and a ninth transistor T9, the first pole of the first transistor T1 is connected to the initial signal terminal Vinit, the second pole is connected to the sixth node N6, and the gate is connected to The reset signal terminal Reset; the first pole of the ninth transistor T9 is connected to the sixth node N6, the second pole is connected to the first node N1, and the gate is connected to the first gate driving signal terminal Gate1.
  • the second storage circuit 08 may include a second capacitor C2 connected between the second node N2 and the fourth node N4. In other exemplary embodiments, the second storage circuit 08 may also be connected between the second node N2 and other stable voltage terminals.
  • the first transistor T1 to the ninth transistor T9, and the driving transistor DTFT can all be P-type transistors
  • the first power supply terminal VDD can be a high-level signal terminal
  • the second power supply terminal VSS can be a low-level power supply terminal.
  • FIG. 8 it is a timing diagram of each node of the pixel driving circuit in FIG. 7 .
  • Reset is the timing diagram of the reset signal terminal Reset
  • Vinit is the timing diagram of the initial signal terminal Vinit
  • EM1 is the timing diagram of the first enabling signal terminal EM1
  • EM2 is the timing diagram of the second enabling signal terminal EM2
  • Vdata is The timing diagram of the data signal terminal Vdata
  • Gate1 is the timing diagram of the first gate driving signal terminal Gate1
  • Gate2 is the timing diagram of the second gate driving signal terminal Gate2.
  • the driving method of the pixel driving circuit may include five stages: a first reset stage t1, a second reset stage t2, a first threshold compensation stage t3, a second threshold compensation stage t4, and a light emitting stage t5.
  • a first reset phase t1 an active level (low level) is input to the reset signal terminal Reset and the second enable signal terminal EM2, and the active level (low level) is input to the first gate drive signal terminal Gate1, the first enable signal terminal EM1, the second The gate driving signal terminal Gate2 inputs an inactive level (high level).
  • the seventh transistor T7 and the third transistor T3 are turned on, the reference voltage terminal Vref pre-writes a reference voltage into the fourth node N4, and the initial signal terminal Vinit writes an initial signal into the fifth node.
  • an active level is input to the reset signal terminal Reset, the second enable signal terminal EM2, and the first gate drive signal terminal Gate1, and the active level is input to the first enable signal terminal EM1, the second gate drive signal terminal Gate2 input invalid level.
  • the first transistor T1, the ninth transistor T9, the seventh transistor T7, the third transistor T3, and the fourth transistor T4 are turned on, the initial signal terminal Vinit writes the initial signal to the first node N1, and the reference voltage terminal Vref continues to the fourth node N4 writes the reference voltage.
  • the active level is input to the first gate drive signal terminal Gate1, the second enable signal terminal EM2, and the second gate drive signal terminal Gate2, and the reset signal terminal Reset, the first enable signal terminal End EM1 input invalid level.
  • the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the third transistor T3 are turned on, and the voltage of the first node N1 continues to rise until the end of the first threshold compensation stage t3. The voltage of the first node N1 can still be in the rising stage .
  • the active level is input to the second enable signal terminal EM2 and the second gate drive signal terminal Gate2, and the active level is input to the first gate drive signal terminal Gate1, the reset signal terminal Reset, the first enable signal terminal End EM1 input invalid level.
  • the second transistor T2 is turned on, and the charge stored in the second node N2 of the second capacitor C2 continues to charge the first node until the voltage of the first node N1 is Vdata+Vth, at this time, the voltage across the first capacitor C1 is Vdata+Vth-Vref, wherein, Vdata is the voltage of the data signal terminal, Vth is the threshold voltage of the driving transistor, and Vref is the voltage of the reference voltage terminal.
  • an active level is input to the first enable signal terminal EM1, and input to the first gate drive signal terminal Gate1, the second gate drive signal terminal Gate2, the reset signal terminal Reset, and the second enable signal terminal EM2. invalid level.
  • the current output by the pixel driving circuit has nothing to do with the voltage of the first power supply terminal VDD, that is, the display panel using the pixel driving circuit will not cause uneven display due to the voltage drop of the source line itself.
  • the duration of the threshold compensation phase (t3 and t4) in the pixel driving circuit shown in FIG. may have a longer threshold compensation duration.
  • the gate of the ninth transistor T9 may also be connected to the reset signal Reset.
  • the gate of the ninth transistor T9 may be connected to the first gate driving signal terminal Gate1.
  • the ninth transistor T9 may not be provided in the second reset circuit in FIG. 7 .
  • This exemplary embodiment also provides a driving method of a pixel driving circuit, for driving the above-mentioned pixel driving circuit, wherein the driving method includes:
  • an inactive level is input to the first enable signal terminal EM1, and an active level is input to the second enable signal terminal EM2;
  • an active level is input to the first enable signal terminal EM1, and an inactive level is input to the second enable signal terminal EM2.
  • This exemplary embodiment also provides a driving method of a pixel driving circuit, for driving the above-mentioned pixel driving circuit, wherein the driving method includes:
  • an active level is input to the reset signal terminal and the second enable signal terminal EM2, and an invalid level is input to the first gate drive signal terminal Gate1 and the first enable signal terminal EM1;
  • an active level is input to the first gate drive signal terminal Gate1 and the second enable signal terminal EM2, and an invalid level is input to the reset signal terminal and the first enable signal terminal EM1;
  • an active level is input to the second enable signal terminal EM2, and an inactive level is input to the first gate drive signal terminal Gate1, the reset signal terminal, and the first enable signal terminal EM1;
  • an active level is input to the first enable signal terminal EM1 , and an inactive level is input to the first gate drive signal terminal Gate1 , the reset signal terminal, and the second enable signal terminal EM2 .
  • This exemplary embodiment also provides a driving method of a pixel driving circuit, for driving the above-mentioned pixel driving circuit, wherein the driving method includes:
  • the active level is input to the reset signal terminal and the second enable signal terminal EM2, and input to the first gate drive signal terminal Gate1, the first enable signal terminal EM1, and the second gate drive signal terminal Gate2. invalid level;
  • the active level is input to the reset signal terminal, the second enable signal terminal EM2, and the first gate drive signal terminal Gate1, and the input level is input to the first enable signal terminal EM1 and the second gate drive signal terminal Gate2. invalid level;
  • the active level is input to the first gate drive signal terminal Gate1, the second enable signal terminal EM2, and the second gate drive signal terminal Gate2, and the active level is input to the reset signal terminal and the first enable signal terminal EM1. Input invalid level;
  • the active level is input to the second enable signal terminal EM2 and the second gate drive signal terminal Gate2, and the active level is input to the first gate drive signal terminal Gate1, the reset signal terminal, and the first enable signal terminal EM1 Input invalid level;
  • an active level is input to the first enable signal terminal EM1, and an invalid level is input to the first gate drive signal terminal Gate1, the second gate drive signal terminal Gate2, the reset signal terminal, and the second enable signal terminal EM2. flat.
  • This exemplary embodiment also provides a display panel, wherein the display panel includes the above-mentioned pixel driving circuit.
  • the display panel can be applied to display devices such as mobile phones, tablet computers, and televisions.
  • This exemplary embodiment also provides a display panel, wherein the display panel may include a pixel driving circuit as shown in FIG. 3 .
  • the display panel may include a base substrate, an active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer that are sequentially stacked, as shown in FIGS. 9-17 .
  • the structural layout in an exemplary embodiment of the display panel FIG. 10 is the structural layout of the active layer in FIG. 9
  • FIG. 11 is the structural layout of the first conductive layer in FIG. 9
  • FIG. 12 is the second conductive layer in FIG.
  • Figure 13 is the structural layout of the third conductive layer in Figure 9, Figure 13 is the structural layout of the fourth conductive layer in Figure 9, Figure 15 is the structural layout of the active layer and the first conductive layer in Figure 9, Figure 16 is the structural layout of the active layer, the first conductive layer, and the second conductive layer in Figure 9, and Figure 17 is the structural layout of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in Figure 9 .
  • the active layer may include a first active portion 51, a second active portion 52, a third active portion 53, a fourth active portion 54, a fifth active portion 55, Sixth active part 56, seventh active part 57, eighth active part 58, tenth active part 510, eleventh active part 511, twelfth active part 512, thirteenth active part 513 , a fourteenth active portion 514 , a first initial signal line Vinit1 , and a second initial signal line Vinit2 .
  • the first active part 51 includes a sub-active part 5110 and a sub-active part 5120, and the sub-active part 5110 and the sub-active part 5120 can be used to form two channel regions of the first transistor; the second active part 52 A sub-active portion 521 and a sub-active portion 522 may be included, and the sub-active portion 521 and the sub-active portion 522 may be used to form two channel regions of the second transistor; the third active portion 53 is used to form the third transistor T3 The channel region; the fourth active portion 54 is used to form the channel region of the fourth transistor T4; the fifth active portion 55 is used to form the channel region of the fifth transistor T5; the sixth active portion 56 is used to form The channel region of the sixth transistor T6; the seventh active portion 57 is used to form the channel region of the seventh transistor T7; the eighth active portion 58 is used to form the channel region of the eighth transistor T8, and the tenth active portion 510 is used to form the channel region of the driving transistor DTFT.
  • the eleventh active part 511 may be connected to the third active part 53 , the fifth active part 55 , and the eighth active part 58 respectively, and the tenth active part 510 may be connected to the eighth active part 510 .
  • the fifth active part 55 is away from the end of the eleventh active part 511, and the twelfth active part 512 can be connected to the end of the eighth active part 58 away from the eleventh active part 511;
  • the thirteenth active part 513 may be connected to an end of the third active part 53 away from the eleventh active part 511 .
  • the first initial signal line Vinit1 is connected to an end of the first active portion 51 away from the fourteenth active portion 514, and is used to provide an initial signal terminal to the first transistor T1
  • the second initial signal line Vinit2 can be connected to the seventh One end of the active portion 57 away from the sixth active portion 56 is used for providing an initial signal end to the seventh transistor T7.
  • the orthographic projection of the first initial signal line Vinit1 on the base substrate and the orthographic projection of the second initial signal line Vinit2 on the base substrate can both extend along the first direction X, and the first direction X can be the row of the display panel. direction.
  • the first initial signal line Vinit1 may also be used to provide an initial signal terminal to the seventh transistor T7 in the pixel driving circuit in the upper row.
  • the second initial signal line Vinit2 can also be used to provide an initial signal terminal to the first transistor T1 in the next row of pixel driving circuits.
  • the active layer may be formed of polysilicon semiconductor, and the first transistor to the eighth transistor and the driving transistor may all be low temperature polysilicon transistors.
  • the first conductive layer may include: a first enable signal line EM1, a second enable signal line EM2, a tenth conductive portion 110, an eighth conductive portion 18, and a first conductive portion 11. , a plurality of fourth conductive portions 14 .
  • the orthographic projection of the tenth conductive portion 110 on the substrate may cover the orthographic projection of the tenth active portion 510 on the substrate, and the tenth conductive portion 110 may be used for Form the gate of the drive transistor and the first electrode of the first capacitor;
  • the orthographic projection of the first enable signal line EM1 on the substrate may extend along the first direction X, and the first enable
  • the orthographic projection of the enable signal line EM1 on the base substrate can cover the orthographic projection of the fifth active portion 55 on the base substrate, and the partial structure of the first enable signal line EM1 can be used for
  • the gate of the fifth transistor T5 is formed;
  • the orthographic projection of the second enabling signal line EM2 on the substrate can extend along the first direction X, and the second enabling signal line EM2 is formed on the substrate
  • the orthographic projection on the base substrate can cover the orthographic projection of the third active portion 53 on the base substrate, and the partial structure of the second enable signal line EM2 can be used to form the third transistor T3.
  • the eighth conductive portion 18 may be connected to the first enable signal line EM1, and the orthographic projection of the eighth conductive portion 18 on the base substrate may cover the eighth active portion 58 In the orthographic projection on the base substrate, the eighth conductive portion 18 may be used to form the gate of the eighth transistor T8; the first conductive portion 11 may be used to form the gate of the first transistor.
  • the orthographic projections of the plurality of fourth conductive portions 14 on the substrate can be distributed in intervals in the first direction X, and part of the structure of the fourth conductive portions 14 can be used for the gate of the second transistor in a pixel driving circuit, and the fourth conductive portion Another part of the structure of the conductive part 14 can be used to form the gate of the fourth transistor in another pixel driving circuit, and the two pixel driving circuits can be adjacently arranged in the first direction X. As shown in FIG.
  • part of the structure of the fourth conductive portion 14 on the left is used to form the gate of the second transistor in the pixel driving circuit, and another part of the structure of the fourth conductive portion 14 on the left (not shown in the figure) can be It is used to form the gate of the fourth transistor in the pixel driving circuit on the left side of the pixel driving circuit.
  • the display panel can use the first conductive layer as a mask to conduct conductive treatment on the active layer, the area covered by the first conductive layer can form the channel region of the transistor, and the area not covered by the first conductive layer can be form a conductor structure.
  • the second conductive layer may include an eleventh conductive part 211 and a twelfth conductive part 212, an opening 2111 is opened on the eleventh conductive part 211, and the eleventh conductive part 211 is formed on the lining.
  • the orthographic projection on the base substrate may at least partially coincide with the orthographic projection of the tenth conductive portion on the base substrate, and the eleventh conductive portion 211 may be used to form the second electrode of the first capacitor C.
  • the twelfth conductive part 212 may be connected to the eleventh conductive part 211, and the orthographic projection of the twelfth conductive part 212 on the base substrate may extend along the second direction Y, which may be the column direction of the display panel. .
  • the third conductive layer may include a reference voltage line Vref, a first gate line Gate1, a reset signal line Reset, a first connecting portion 31, a second connecting portion 32, a transfer portion 33, a transfer Connecting part 34, transfer part 35.
  • the orthographic projection of the reference voltage line Vref on the substrate, the orthographic projection of the first gate line Gate1 on the substrate, and the orthographic projection of the reset signal line Reset on the substrate can all extend along the first direction X.
  • the reference voltage line Vref is used to provide a reference voltage terminal
  • the first gate line Gate1 is used to provide a first gate driving signal terminal
  • the reset signal line Reset is used to provide a reset signal terminal. As shown in FIG.
  • the reference voltage line Vref can be connected to the thirteenth active portion 513 through the via hole H2 to connect the first pole of the third transistor T3 and the reference voltage terminal.
  • the first connection part 31 can be connected to the eleventh active part 511 through the via hole H3 and connected to the eleventh conductive part 211 through the via hole H4, so as to connect the second electrode of the third transistor and the second electrode of the first capacitor C1.
  • the transition part 34 can be connected to the twelfth active part 512 through the via hole H5 to connect to the second pole of the eighth transistor.
  • the transfer part 33 may connect the active layer between the sixth active part 56 and the seventh active part 57 through the via hole H1 to connect to the fifth node.
  • the second connection part 32 can connect the tenth conductive part 110 through the via hole H6, and connect the fourteenth active part 514 through the via hole H7, so as to connect the gate of the driving transistor and the first pole of the second transistor, wherein the via hole H6
  • the orthographic projection on the base substrate may be located within the orthographic projection of the opening 2111 on the base substrate, so as to insulate the via hole H6 from the eleventh conductive portion 211 .
  • the transition part 35 can be connected to the active layer at the end of the fourth active part 54 away from the tenth active part 510 through the via hole H9, so as to be connected to the first electrode of the fourth transistor.
  • the reset signal line Reset can be connected to a plurality of first conductive portions 11 in the same row through via holes, so as to connect the gate of the first transistor to the reset signal terminal.
  • the first gate line Gate1 can be connected to the second conductive portion 14 through the via hole H8 to connect the first gate driving signal terminal to the gate of the second transistor, and the first gate driving signal terminal to the gate of the fourth transistor.
  • the sheet resistance of the third conductive layer may be smaller than that of the second conductive layer.
  • the reference voltage line Vref, the first gate line Gate1, and the reset signal line Reset are all set on the third conductive layer.
  • the conductive layer can improve the response speed of the first transistor, the fourth transistor and the second transistor.
  • the fourth conductive layer may include a power line VDD, a data line Vdata, and a transfer portion 41 .
  • the power line VDD is used to provide the first power terminal
  • the data line Vdata is used to provide the data signal terminal.
  • the orthographic projection of the power line VDD on the substrate and the orthographic projection of the data line Vdata on the substrate can be along the second direction. Y extension.
  • the power line VDD can be connected to the transfer portion 34 through the via hole H12 to connect the second pole of the eighth transistor to the first power terminal.
  • the data line Vdata can be connected to the transition part 35 through the via hole H11, so as to connect the first electrode of the fourth transistor and the data signal terminal.
  • the transition part 41 can be connected to the transition part 33 through the via hole H13, and the transition part 41 can be used to connect the first electrode of the light emitting unit.
  • the orthographic projection of the power line VDD on the base substrate and the orthographic projection of the fourteenth active portion 514 on the base substrate can at least partially overlap, and the power line VDD can stabilize the gate of the driving transistor. voltage to reduce the voltage fluctuation of the drive transistor gate during the light-emitting phase.
  • the orthographic projection of the power line VDD on the base substrate may at least partially coincide with the orthographic projection of the second connecting portion 32 on the base substrate.
  • the power line VDD can stabilize the gate voltage of the drive transistor to reduce The voltage at the gate of the drive transistor fluctuates during the light-emitting phase.
  • the orthographic projection of the twelfth conductive portion 212 on the base substrate may be at least partly located between the orthographic projection of the fourteenth active portion 414 on the base substrate and the data line Vdata on the base substrate. between orthographic projections on the substrate substrate.
  • the twelfth conductive part 212 is connected to the power line VDD, and the twelfth conductive part 212 can shield the interference of the data line Vdata to the fourteenth active part 414, thereby further stabilizing the voltage of the gate of the driving transistor.
  • the orthographic projection of the twelfth conductive portion 212 on the base substrate may be located between two adjacent fourth conductive portions 14 in the first direction X.
  • this setting can The parasitic capacitance on the fourth conductive part 14 is reduced, thereby improving the response speed of the second transistor and the fourth transistor.
  • the display panel may also include a buffer layer 62, a first insulating layer 63, a second insulating layer 64, a dielectric layer 65, a passivation layer 66, and a flat layer 67, wherein the base substrate 61, the buffer layer 62, and the active layer , the first insulating layer 63, the first conductive layer, the second insulating layer 64, the second conductive layer, the dielectric layer 65, the third conductive layer, the passivation layer 66, the planar layer 67, and the fourth conductive layer can be stacked in sequence .
  • the buffer 62 may include at least one of a silicon oxide layer and a silicon nitride layer.
  • the first insulating layer 63 and the second insulating layer 64 may be silicon oxide layers.
  • the dielectric layer may be a silicon nitride layer.
  • the material of the passivation layer 66 may include an organic insulating material or an inorganic insulating material, for example, a silicon nitride material.
  • the material of the flat layer 67 can be organic materials such as organic resin.
  • the material of the first conductive layer and the second conductive layer may be molybdenum, aluminum, copper, titanium, niobium, one of them or an alloy, or a molybdenum/titanium alloy or laminated layers.
  • the material of the third conductive layer and the fourth conductive layer may include metal materials, such as molybdenum, aluminum, copper, titanium, niobium, one of them or an alloy, or a molybdenum/titanium alloy or laminate, etc., or may be titanium/titanium Aluminum/titanium stack.
  • the base substrate 61 may include a glass substrate, a barrier layer, and a polyimide layer that are sequentially stacked, and the barrier layer may be an inorganic material.
  • This exemplary embodiment also provides another display panel, wherein the display panel may include a pixel driving circuit as shown in FIG. 3 .
  • the display panel may include a base substrate, an active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer that are sequentially stacked, as shown in FIGS. 19-27 .
  • the structural layout in an exemplary embodiment of the display panel FIG. 20 is the structural layout of the active layer in FIG. 19
  • FIG. 21 is the structural layout of the first conductive layer in FIG. 19
  • FIG. 22 is the second conductive layer in FIG.
  • Figure 23 is the structural layout of the third conductive layer in Figure 19
  • Figure 24 is the structural layout of the fourth conductive layer in Figure 19
  • Figure 25 is the structural layout of the active layer and the first conductive layer in Figure 19
  • Figure 26 is the structural layout of the active layer, the first conductive layer, and the second conductive layer in Figure 19
  • Figure 27 is the structural layout of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in Figure 19 .
  • the active layer may include a first active portion 51, a second active portion 52, a third active portion 53, a fourth active portion 54, a fifth active portion 55, Sixth active part 56, seventh active part 57, eighth active part 58, tenth active part 510, eleventh active part 511, twelfth active part 512, thirteenth active part 513 , the fourteenth active part 514 , the fifteenth active part 515 , and the active line 50 .
  • the first active part 51 may include a first sub-active part 5110 and a second sub-active part 5120, and the first sub-active part 5110 and the second sub-active part 5120 may be used to form two parts of the first transistor.
  • the active layer may further include a third sub-active portion 5130 connected between the first sub-active portion 5110 and the second sub-active portion 5120 .
  • the second active part 52 may include a fourth sub-active part 521 and a fifth sub-active part 522, and the fourth sub-active part 521 and the fifth sub-active part 522 may be used to form two trenches of the second transistor.
  • the active layer may further include a sixth sub-active part 523 connected between the fourth sub-active part 521 and the fifth sub-active part 522 .
  • the third active portion 53 is used to form the channel region of the third transistor T3; the fourth active portion 54 is used to form the channel region of the fourth transistor T4; the fifth active portion 55 is used to form the channel region of the fifth transistor T5 channel region; the sixth active portion 56 is used to form the channel region of the sixth transistor T6; the seventh active portion 57 is used to form the channel region of the seventh transistor T7; the eighth active portion 58 is used to form the channel region of the sixth transistor T6
  • the channel region of the eight transistor T8, the tenth active portion 510 is used to form the channel region of the driving transistor DTFT.
  • the eleventh active part 511 may be connected to the third active part 53 , the fifth active part 55 , and the eighth active part 58 respectively, and the tenth active part 510 may be connected to the eighth active part 510 .
  • the fifth active part 55 is away from the end of the eleventh active part 511
  • the twelfth active part 512 is connected to the end of the eighth active part 58 away from the eleventh active part 511;
  • the third active part 513 is connected to an end of the third active part 53 away from the eleventh active part 511;
  • the fifteenth active part 515 is connected to the seventh active part 57 and away from the sixth active part 56 one end.
  • the orthographic projection of the active line 50 on the base substrate extends along the first direction X, the first direction X may be the row direction of the display panel, and the active line 50 may connect multiple fifteenth active active lines located in the same pixel circuit row. Section 515.
  • the active layer may be formed of polysilicon semiconductor, and the first transistor to the eighth transistor and the driving transistor may all be low temperature polysilicon transistors.
  • the first conductive layer may include: a first enable signal line EM1, a second enable signal line EM2, a tenth conductive portion 110, an eighth conductive portion 18, and a fifteenth conductive portion 115 , the thirteenth conductive part 113 , the sixteenth conductive part 116 , the reset signal line Reset, and the first gate line Gate1 .
  • the first enable signal line EM1 is used to provide a first enable signal terminal
  • the second enable signal line EM2 is used to form a second enable signal terminal
  • the reset signal line Reset is used to provide a reset signal terminal
  • the first gate line Gate1 Used to provide the first gate drive signal terminal.
  • the orthographic projection of the first enable signal line EM1 on the base substrate, the orthographic projection of the second enable signal line EM2 on the base substrate, the orthographic projection of the reset signal line Reset on the base substrate, the first gate line Gate1 Both orthographic projections on the base substrate may extend along the first direction X.
  • the tenth conductive part 110 is used to form the gate of the drive transistor and the first electrode of the first capacitor; the orthographic projection of the first enable signal line EM1 on the base substrate covers the fifth active
  • the orthographic projection of part 55 on the substrate substrate, the partial structure of the first enable signal line EM1 is used to form the gate of the fifth transistor T5; the second enable signal line EM2 is on the substrate
  • the orthographic projection on the substrate can cover the orthographic projection of the third active portion 53 on the base substrate and the orthographic projection of the seventh active portion 57 on the base substrate.
  • the second enable signal line EM2 Part of the structure of the second enable signal line EM2 can be used to form the gate of the third transistor T3, and another part of the structure of the second enable signal line EM2 can be used to form the gate of the seventh transistor T7; the eighth conductive part 18 can be connected to the first enable signal line EM1, the orthographic projection of the eighth conductive portion 18 on the base substrate can cover the orthographic projection of the eighth active portion 58 on the base substrate, The eighth conductive portion 18 may be used to form the gate of the eighth transistor T8.
  • the thirteenth conductive part 113 can be connected to the side of the reset signal line Reset facing the first gate line Gate1, the fifteenth conductive part 115 can be connected to the side of the first gate line Gate1 facing the reset signal line, and the sixteenth conductive part 116 may be connected to a side of the reset signal line away from the first gate line Gate1.
  • a part of the structure of the first gate line Gate1 can be used to form the gate of the second transistor and the fourth transistor, the fifteenth conductive part 115 can be used to form another gate of the second transistor, and a part of the structure of the reset signal line Reset can be Used to form the gate of the first transistor, the sixteenth conductive portion 116 may be used to form another gate of the first transistor.
  • the display panel can use the first conductive layer as a mask to conduct conductive treatment on the active layer, the area covered by the first conductive layer can form the channel region of the transistor, and the area not covered by the first conductive layer can be form a conductor structure.
  • the second conductive layer may include an eleventh conductive portion 211 , and an opening 2111 may be opened on the eleventh conductive portion 211 .
  • the orthographic projection of the eleventh conductive portion 211 on the substrate may at least partially coincide with the orthographic projection of the tenth conductive portion 110 on the substrate, and the eleventh conductive portion 211 may be used to form the second capacitor of the first capacitor C1. electrode.
  • the third conductive layer may include: a power line VDD, a first connecting portion 31, a second connecting portion 32, an adapter portion 33, an adapter portion 34, an adapter portion 35, an adapter Section 36.
  • the power line VDD is used to provide the first power terminal, and the orthographic projection of the power line VDD on the base substrate may extend along the second direction Y, and the second direction may be the column direction of the display panel.
  • the power line VDD can be connected to the twelfth active portion 512 through the via hole H6 to connect the second pole of the eighth transistor to the first power terminal.
  • the first connection part 31 can be connected to the eleventh active part 511 through the via hole H4, and connected to the eleventh conductive part 211 through the via hole H5, so as to connect the second pole of the third transistor and the second pole of the first capacitor C1.
  • the second connection part 32 can be connected to the tenth conductive part 110 through the via hole H7, and connected to the fourteenth active part 514 through the via hole H8, so as to connect the gate of the driving transistor and the first pole of the second transistor, wherein the via hole H7
  • the orthographic projection on the base substrate may be located within the orthographic projection of the opening 2111 on the base substrate, so as to insulate the via hole H7 from the eleventh conductive portion 211 .
  • the transition part 33 can be connected to the thirteenth active part 513 through the via hole H2, so as to be connected to the first pole of the third transistor.
  • the transition part 34 can be connected to the fifteenth active part 515 through the via hole H1, so as to be connected to the first electrode of the seventh transistor.
  • the transfer part 35 can be connected to the active layer between the sixth active part 56 and the seventh active part 57 through the via hole H3, so as to be connected to the first electrode of the sixth transistor.
  • the transition part 36 can be connected to the active layer at the end of the fourth active part 54 away from the fifth active part 55 through the via hole H9, so as to connect to the first electrode of the fourth transistor.
  • the orthographic projection of the power line VDD on the base substrate and the orthographic projection of the third sub-active portion 5130 on the base substrate may at least partially overlap, and the power line VDD may stabilize the voltage of the third sub-active portion 5130, Therefore, the abnormal leakage to the source and drain of the first transistor due to the voltage fluctuation of the third sub-active part 5130 is reduced.
  • the fourth conductive layer may include an initial signal line Vinit, a data line Vdata, a reference voltage line Vref, a transfer portion 41 , and a seventeenth conductive portion 42 .
  • the initial signal line Vinit can be used to provide an initial signal terminal
  • the data line Vdata can be used to provide a data signal terminal
  • the reference voltage line Vref can be used to provide a reference voltage terminal.
  • the orthographic projection of the initial signal line Vinit on the base substrate, the orthographic projection of the data line Vdata on the base substrate, and the orthographic projection of the reference voltage line Vref on the base substrate can all extend along the second direction Y. As shown in FIG.
  • the initial signal line Vinit can be connected to the transition part 34 through the via hole H11 to connect the first electrode of the seventh transistor, and the fifteenth active part 515 can be connected to the first electrode of the next row of pixel driving circuits.
  • the sub-active part 5110 is connected, so the initial signal line Vinit can also provide an initial signal terminal to the first pole of the first transistor in the pixel driving circuit of the next row.
  • the first pole of the first transistor in the pixel driving circuit of this row can be
  • the initial signal line Vinit is connected through the transition part 34 in the pixel driving circuit in the upper row.
  • the initial signal line Vinit can form a grid structure with the active line 50 , so that the resistance of the initial signal line Vinit itself can be reduced.
  • the initial signal line Vinit may include connected first sub-initial signal line Vinit1 and second sub-initial signal line Vinit2, the orthographic projection of the first sub-initial signal line Vinit1 on the substrate substrate and the second sub-initial signal line Vinit2 on the substrate
  • the orthographic projections on the base substrate may be staggered in the first direction.
  • the orthographic projection of the first sub-initial signal line Vinit1 on the base substrate can also at least partially overlap with the orthographic projection of the second connecting portion 32 on the base substrate, and the first sub-initial signal line Vinit1 can overlap the second connecting portion 32.
  • the orthographic projection of the first sub-initial signal line Vinit1 on the base substrate may also at least partially coincide with the orthographic projection of the fourteenth active portion 514 on the base substrate, and the first sub-initial signal line Vinit1 may have an impact on the fourteenth active portion 514.
  • the source part 514 plays a role of voltage stabilization, thereby reducing the voltage fluctuation of the gate of the driving transistor during the light-emitting phase.
  • the orthographic projection of the second sub-initial signal line Vinit2 on the base substrate may at least partially coincide with the orthographic projection of the power line VDD on the base substrate. This setting can reduce the light-shielding influence of the second sub-initial signal line Vinit2 on the display panel.
  • the data line Vdata can be connected to the transition part 36 through the via hole H13, so as to connect the first pole of the fourth transistor and the data signal terminal.
  • the reference voltage line Vref can be connected to the transfer portion 33 through the via hole H10 to connect the reference voltage terminal and the first electrode of the third transistor.
  • the transition part 41 can be connected to the transition part 35 through the via hole H12 to connect the first pole of the sixth transistor, and the transition part 41 can be used to connect the first pole of the light emitting unit.
  • the seventeenth conductive part 42 can be connected to the side of the reference voltage line Vref away from the data line Vdata, and the orthographic projection of the seventeenth conductive part 42 on the base substrate can be the same as the sixth sub-active part 523 in the right pixel driving circuit.
  • the orthographic projections on the base substrate are at least partially overlapped, and the seventeenth conductive part 42 can stabilize the voltage of the sixth sub-active part 523, thereby reducing the voltage fluctuation of the sixth sub-active part 523 to the second transistor. Abnormal leakage of source and drain.
  • the display panel may also include a buffer layer 62, a first insulating layer 63, a second insulating layer 64, a dielectric layer 65, a passivation layer 66, and a flat layer 67, wherein the base substrate 61, the buffer layer 62, and the active layer , the first insulating layer 63 , the first conductive layer, the second insulating layer 64 , the second conductive layer, the dielectric layer 65 , the third conductive layer, the passivation layer 66 , the flat layer 67 , and the fourth conductive layer are sequentially stacked.
  • the buffer 62 may include at least one of a silicon oxide layer and a silicon nitride layer.
  • the first insulating layer 63 and the second insulating layer 64 may be silicon oxide layers.
  • the dielectric layer may be a silicon nitride layer.
  • the material of the passivation layer 66 may include an organic insulating material or an inorganic insulating material, for example, a silicon nitride material.
  • the material of the flat layer 67 can be organic materials such as organic resin.
  • the material of the first conductive layer and the second conductive layer can be molybdenum, aluminum, copper, titanium, niobium, one of them or an alloy, or a molybdenum/titanium alloy or laminated layers.
  • the material of the third conductive layer and the fourth conductive layer may include metal materials, such as molybdenum, aluminum, copper, titanium, niobium, one of them or an alloy, or a molybdenum/titanium alloy or laminate, etc., or may be titanium/titanium Aluminum/titanium stack.
  • the base substrate 61 may include a glass substrate, a barrier layer, and a polyimide layer that are sequentially stacked, and the barrier layer may be an inorganic material.
  • This exemplary embodiment also provides another display panel, wherein the display panel may include a pixel driving circuit as shown in FIG. 7 .
  • the display panel may include a base substrate, an active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer that are sequentially stacked, as shown in FIGS. 29-37 .
  • the structural layout in an exemplary embodiment of the display panel, FIG. 30 is the structural layout of the active layer in FIG. 29
  • FIG. 31 is the structural layout of the first conductive layer in FIG. 29
  • FIG. 32 is the second conductive layer in FIG.
  • Figure 33 is the structural layout of the third conductive layer in Figure 29
  • Figure 34 is the structural layout of the fourth conductive layer in Figure 29
  • Figure 35 is the structural layout of the active layer and the first conductive layer in Figure 29
  • Figure 36 is the structural layout of the active layer, the first conductive layer, and the second conductive layer in Figure 29
  • Figure 37 is the structural layout of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in Figure 29 .
  • the active layer may include a first active portion 51, a second active portion 52, a third active portion 53, a fourth active portion 54, a fifth active portion 55, Sixth active part 56, seventh active part 57, eighth active part 58, ninth active part 59, tenth active part 510, eleventh active part 511, twelfth active part 512 , the thirteenth active part 513 , the fourteenth active part 514 , the sixteenth active part, the first initial signal line Vinit1 , and the second initial signal line Vinit2 .
  • the first active portion 51 can be used to form the channel region of the first transistor;
  • the second active portion 52 can include a sub-active portion 521 and a sub-active portion 522, and the sub-active portion 521 and the sub-active portion 522 can be Used to form two channel regions of the second transistor;
  • the third active portion 53 is used to form the channel region of the third transistor T3;
  • the fourth active portion 54 is used to form the channel region of the fourth transistor T4;
  • the fifth active portion 55 is used to form the channel region of the fifth transistor T5;
  • the sixth active portion 56 is used to form the channel region of the sixth transistor T6;
  • the seventh active portion 57 is used to form the channel of the seventh transistor T7 channel region;
  • the eighth active portion 58 is used to form the channel region of the eighth transistor T8,
  • the ninth active portion 59 is used to form the channel region of the ninth transistor T9;
  • the tenth active portion 510 is used to form the drive transistor The channel region of a DTFT.
  • the eleventh active part 511 may be connected to the third active part 53 , the fifth active part 55 , and the eighth active part 58 respectively, and the tenth active part 510 may be connected to the eighth active part 510 .
  • the fifth active part 55 is away from the end of the eleventh active part 511, the twelfth active part 512 is connected to the end of the eighth active part 58 away from the eleventh active part 511;
  • the third active part 513 is connected to an end of the third active part 53 away from the eleventh active part 511; the fourteenth active part 514 is connected to the second active part 52 and the ninth active part 59
  • the sixteenth active part 516 is connected between the fourth active part 54 and the tenth active part 510, the sixteenth active part 516 can be used to form the first electrode of the second capacitor, the sixteenth active part
  • the size of the orthographic projection of the portion 516 on the base substrate in the first direction X may be larger than the size of the orthographic projection of the fourth active portion 54 on the
  • Both the orthographic projection of the first initial signal line Vinit1 on the base substrate and the orthographic projection of the second initial signal line Vinit2 on the base substrate may extend along a first direction X, which may be a row direction of the display panel.
  • Two adjacent pixel driving circuits in the column direction can share one initial signal line, for example, the first initial signal line Vinit1 can also be used to provide an initial signal terminal to the seventh transistor T7 in the pixel driving circuit in the upper row.
  • the second initial signal line Vinit2 can also be used to provide an initial signal terminal to the first transistor T1 in the next row of pixel driving circuits.
  • the active layer may be formed of polysilicon semiconductor, and the first transistor to the eighth transistor and the driving transistor may all be low temperature polysilicon transistors.
  • the first conductive layer may include: a first enable signal line EM1, a second enable signal line EM2, a tenth conductive part 110, an eighth conductive part 18, a plurality of first conductive portion 11, a plurality of ninth conductive portions 19, and a plurality of second conductive portions 12.
  • the orthographic projection of the tenth conductive portion 110 on the base substrate covers the orthographic projection of the tenth active portion 510 on the base substrate, and the tenth conductive portion 110 is used to form the The gate of the drive transistor and the first electrode of the first capacitor; the orthographic projection of the first enable signal line EM1 on the substrate can extend along the first direction X, and the first enable signal The orthographic projection of the line EM1 on the base substrate covers the orthographic projection of the fifth active portion 55 on the base substrate, and the partial structure of the first enable signal line EM1 is used to form the first The gate of five transistors T5; the orthographic projection of the second enable signal line EM2 on the base substrate can extend along the first direction X, and the second enable signal line EM2 on the base substrate The orthographic projection covers the orthographic projection of the third active portion 53 on the substrate and the orthographic projection of the seventh active portion 57 on the substrate, and the partial structure of the second enable signal line EM2 may be For forming the gate of the third transistor T3,
  • the orthographic projection of the ninth conductive portion 19 on the base substrate can cover the orthographic projection of the fourth active portion 54 on the base substrate and the orthographic projection of the ninth active portion 59 on the base substrate.
  • the ninth conductive portion 19 It can be used to form the gate of the fourth transistor and the gate of the ninth transistor.
  • the orthographic projection of the second conductive part 12 on the base substrate may cover the second active part, and the second conductive part 12 may be used to form a gate of the second transistor.
  • the display panel can use the first conductive layer as a mask to conduct conductive treatment on the active layer, the area covered by the first conductive layer can form the channel region of the transistor, and the area not covered by the first conductive layer can form a conductor structure.
  • the second conductive layer may include an eleventh conductive part 211 and a fourteenth conductive part 214, and the orthographic projection of the eleventh conductive part on the base substrate may be the same as that of the tenth conductive part 110.
  • the orthographic projections on the substrate substrate are at least partially coincident.
  • the eleventh conductive portion 211 may form a second electrode of the first capacitor C1.
  • the fourteenth conductive portion 214 may be connected to the eleventh conductive portion 211, and the orthographic projection of the fourteenth conductive portion 214 on the substrate may at least partially overlap with the orthographic projection of the sixteenth active portion 516 on the substrate.
  • the fourteenth conductive portion 214 may be used to form the second electrode of the second capacitor C2.
  • an opening 2111 is opened on the eleventh conductive portion 211 .
  • the third conductive layer may include a reference voltage line Vref, a first gate line Gate1, a reset signal line Reset, a second gate line Gate2, a first connection part 31, a second connection part 32, An adapter portion 33 , an adapter portion 34 , and an adapter portion 35 .
  • the orthographic projection of the reference voltage line Vref on the substrate, the orthographic projection of the first gate line Gate1 on the substrate, the orthographic projection of the reset signal line Reset on the substrate, and the orthographic projection of the second gate line Gate2 on the substrate All the orthographic projections on the substrate may extend along the first direction X.
  • the reset signal line Reset can be connected to the first conductive part 11 through the via hole H2, so as to connect the reset signal terminal and the gate of the first transistor, wherein the same reset signal line Reset can be connected to the first conductive part 11 located on the same pixel circuit row.
  • the first gate line Gate1 can be connected to the ninth conductive part 19 through the via hole H3, so as to connect the first gate driving signal terminal and the gate of the fourth transistor and the gate of the ninth transistor, wherein the same first gate line Gate1 can be A plurality of ninth conductive portions 19 located in the same pixel circuit row are connected.
  • the second gate line Gate2 can be connected to the second conductive part 12 through the via hole H4 to connect the second gate driving signal terminal and the gate of the second transistor, wherein the same second gate line Gate2 can be connected to the second gate line located in the same pixel circuit row.
  • the reference voltage line Vref can be connected to the thirteenth active part 513 through the via hole H9, so as to connect the reference voltage terminal and the first electrode of the third transistor.
  • the first connection part 31 can be connected to the eleventh active part 511 through the via hole H8, and connected to the eleventh conductive part 211 through the via hole H7, so as to connect the second electrode of the third transistor and the second electrode of the first capacitor C1.
  • the second connection part 32 can connect the tenth conductive part 110 through the via hole H6, and connect the fourteenth active part 514 through the via hole H5, so as to connect the first electrode of the second transistor and the gate of the driving transistor, wherein the via hole
  • the orthographic projection of H6 on the base substrate is located within the orthographic projection of the opening 2111 on the base substrate, so as to insulate the via hole H6 from the eleventh conductive portion 211 .
  • the transition part 33 can be connected to the active layer between the sixth active part 56 and the seventh active part 57 through the via hole H11, so as to connect to the first electrode of the sixth transistor.
  • the transition part 34 can be connected to the twelfth active part 512 through the via hole H10 to connect to the second pole of the eighth transistor.
  • the transition part 35 can be connected to the active layer of the fourth active part 54 on the side away from the tenth active part 510 through the via hole H1, so as to be connected to the first electrode of the fourth transistor.
  • the sheet resistance of the third conductive layer may be smaller than the sheet resistance of the first conductive layer.
  • the reset signal line Reset, the first gate line Gate1 , the second gate line Gate2 , and the reference voltage line Vref are disposed on the third conductive layer, which can reduce the self-resistance of the above signal lines.
  • the fourth conductive layer may include: a data line Vdata, a power line VDD, and a transfer portion 41 .
  • the data line Vdata can be used to provide a data signal terminal
  • the power line VDD can be used to provide a first power terminal.
  • Both the orthographic projection of the data line Vdata on the base substrate and the orthographic projection of the power line VDD on the base substrate may extend along the second direction Y, and the second direction Y may be the column direction of the display panel.
  • the power line VDD can be connected to the transfer portion 34 through H12 to connect the second pole of the eighth transistor and the first power terminal.
  • the data line Vdata can be connected to the transition part 35 through the via hole H13, so as to connect the first pole of the fourth transistor and the data signal terminal.
  • the transfer portion 41 can be connected to the transfer portion 33 through the via hole H14 to connect to the first electrode of the sixth transistor, and the transfer portion 41 can be used to connect to the first electrode of the light emitting unit.
  • the orthographic projection of the power supply line VDD on the base substrate may at least partially coincide with the orthographic projection of the fourteenth active portion 514 on the base substrate, and the power supply line VDD may stabilize the gate of the driving transistor. voltage to reduce the voltage fluctuation of the drive transistor gate during the light-emitting phase.
  • the orthographic projection of the power line VDD on the base substrate may at least partially coincide with the orthographic projection of the second connecting portion 32 on the base substrate.
  • the power line VDD can stabilize the gate voltage of the drive transistor to reduce The voltage at the gate of the drive transistor fluctuates during the light-emitting phase.
  • the display panel may also include a buffer layer 62, a first insulating layer 63, a second insulating layer 64, a dielectric layer 65, a passivation layer 66, and a flat layer 67, wherein the base substrate 61, the buffer layer 62, and the active layer , the first insulating layer 63 , the first conductive layer, the second insulating layer 64 , the second conductive layer, the dielectric layer 65 , the third conductive layer, the passivation layer 66 , the flat layer 67 , and the fourth conductive layer are sequentially stacked.
  • the buffer 62 may include at least one of a silicon oxide layer and a silicon nitride layer.
  • the first insulating layer 63 and the second insulating layer 64 may be silicon oxide layers.
  • the dielectric layer may be a silicon nitride layer.
  • the material of the passivation layer 66 may include an organic insulating material or an inorganic insulating material, for example, a silicon nitride material.
  • the material of the flat layer 67 can be organic materials such as organic resin.
  • the material of the first conductive layer and the second conductive layer may be molybdenum, aluminum, copper, titanium, niobium, one of them or an alloy, or a molybdenum/titanium alloy or laminated layers.
  • the material of the third conductive layer and the fourth conductive layer may include metal materials, such as molybdenum, aluminum, copper, titanium, niobium, one of them or an alloy, or a molybdenum/titanium alloy or laminate, etc., or may be titanium/titanium Aluminum/titanium stack.
  • the base substrate 61 may include a glass substrate, a barrier layer, and a polyimide layer that are sequentially stacked, and the barrier layer may be an inorganic material.

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Abstract

一种像素驱动电路及其驱动方法、显示面板，其中，像素驱动电路包括：驱动电路(01)、控制电路(02)、稳压电路(03)、第一存储电路(04)，驱动电路(01)连接第一节点(N1)、第二节点(N2)、第三节点(N3)，用于根据第一节点(N1)的信号通过第二节点(N2)向第三节点(N3)提供驱动电流；控制电路(02)连接第一使能信号端(EM1)、第二节点(N2)、第一电源端(VDD)、第四节点(N4)，用于响应第一使能信号端(EM1)的信号连通第二节点(N2)和第四节点(N4)，以及用于响应第一使能信号端(EM1)的信号连通第一电源端(VDD)和第四节点(N4)；稳压电路(03)连接第四节点(N4)、第二使能信号端(EM2)、参考电压端(Vref)，用于响应第二使能信号端(EM2)的信号将参考电压端(Vref)的信号传输到第四节点(N4)；第一存储电路(04)连接于第一节点(N1)和第四节点(N4)之间，用于存储第一节点(N1)和第四节点(N4)的电荷。

Description

像素驱动电路及其驱动方法、显示面板 技术领域
本公开涉及显示技术领域，尤其涉及一种像素驱动电路及其驱动方法、显示面板。
背景技术
显示面板通常通过像素驱动电路向发光单元提供驱动电流，以驱动发光单元发光，在相关技术中，像素驱动电路输出的驱动电流和电源线的电压相关。然而，显示面板上不同位置的电源线具有不同的压降，从而导致显示面板显示不均匀。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
根据本公开的一个方面，提供一种像素驱动电路，其中，包括：驱动电路、控制电路、稳压电路、第一存储电路，驱动电路连接第一节点、第二节点、第三节点，用于根据所述第一节点的信号通过所述第二节点向所述第三节点提供驱动电流；控制电路连接第一使能信号端、所述第二节点、第一电源端、第四节点，用于响应所述第一使能信号端的信号连通所述第二节点和第四节点，以及用于响应所述第一使能信号端的信号连通所述第一电源端和所述第四节点；稳压电路连接所述第四节点、第二使能信号端、参考电压端，用于响应所述第二使能信号端的信号将所述参考电压端的信号传输到所述第四节点；第一存储电路连接于所述第一节点和所述第四节点之间，用于存储所述第一节点和所述第四节点的电荷。
本公开一种示例性实施例中，所述第一使能信号端上的信号和所述第二使能信号端上的信号极性相反。
本公开一种示例性实施例中，所述控制电路还连接所述第三节点、第五节点、第一使能信号端，所述控制电路还用于响应所述第一使能信号端的信号以连通所述第三节点和所述第五节点。所述像素驱动电路还包括：第一复位电路，第一复位电路连接初始信号端、第五节点，用于响应至少一个控制信号将所述初始信号端的信号传输到所述第五节点。
本公开一种示例性实施例中，所述第一复位电路还来连接所述第二使能信号端，所述第一复位电路用于响应所述第二使能信号端的信号将所述初始信号端的信号传输到所述第五节点。
本公开一种示例性实施例中，所述驱动电路包括：驱动晶体管，驱动晶体管的第一极连接所述第二节点，第二极连接所述第三节点，栅极连接所述第一节点。所述控制电路包括：第五晶体管、第八晶体管、第六晶体管，第五晶体管的第一极连接所述 第二节点，第二极连接所述第四节点，栅极连接所述第一使能信号端；第八晶体管的第一极连接所述第四节点，第二极连接所述第一电源端，栅极连接所述第一使能信号端；第六晶体管的第一极连接所述第五节点，第二极连接所述第三节点，栅极连接所述第一使能信号端。所述稳压电路包括：第三晶体管，第三晶体管的第一极连接所述参考电压端，第二极连接所述第四节点，栅极连接所述第二使能信号端。所述第一存储电路包括：第一电容，第一电容连接于所述第一节点和所述第四节点之间；所述第一复位电路包括：第七晶体管，第七晶体管的第一极连接所述初始信号端，第二极连接所述第五节点，栅极连接所述第二使能信号端。
本公开一种示例性实施例中，所述像素驱动电路还包括：数据写入电路、补偿电路，数据写入电路连接所述第二节点、数据信号端，用于响应至少一个控制信号将所述数据信号端的信号传输到所述第二节点；补偿电路连接所述第三节点、第一节点，用于响应至少一个控制信号以连通所述第一节点和所述第三节点。
本公开一种示例性实施例中，所述数据写入电路还连接第一栅极驱动信号端，所述数据写入电路用于响应所述第一栅极驱动信号端的信号将所述数据信号端的信号传输到所述第二节点；所述补偿电路还连接所述第一栅极驱动信号端，所述补偿电路用于响应所述第一栅极驱动信号端的信号以连通所述第一节点和所述第三节点。
本公开一种示例性实施例中，所述数据写入电路还连接所述第二使能信号端，所述数据写入电路用于响应所述第二使能信号端的信号将所述数据信号端的信号传输到所述第二节点；所述补偿电路还连接所述第二使能信号端，所述补偿电路用于响应所述第二使能信号端的信号以连通所述第一节点和所述第三节点。
本公开一种示例性实施例中，所述像素驱动电路还包括：第二复位电路，第二复位电路连接所述第一节点、初始信号端、复位信号端，用于响应所述复位信号端的信号将所述初始信号端的信号传输到所述第一节点。
本公开一种示例性实施例中，所述数据写入电路包括：第四晶体管，第四晶体管的第一极连接所述数据信号端，第二极连接所述第二节点，栅极连接所述第一栅极驱动信号端。所述补偿电路包括：第二晶体管，第二晶体管的第一极连接所述第一节点，第二极连接所述第三节点，栅极连接所述第一栅极驱动信号端。所述第二复位电路包括：第一晶体管，第一晶体管的第一极连接所述初始信号端，第二极连接所述第一节点，栅极连接所述复位信号端。
本公开一种示例性实施例中，所述像素驱动电路还包括：第二存储电路，第二存储电路连接于所述第二节点和所述第四节点之间，用于存储第二节点和所述第四节点的电荷。所述数据写入电路还连接第一栅极驱动信号端，所述数据写入电路用于响应所述第一栅极驱动信号端的信号将所述数据信号端的信号传输到所述第二节点；所述补偿电路还连接第二栅极驱动信号端，所述补偿电路用于响应所述第二栅极驱动信号端的信号以连通所述第一节点和所述第三节点。
本公开一种示例性实施例中，所述像素驱动电路还包括：第二复位电路，第二复位电路连接所述第一节点、初始信号端，用于响应至少一个控制信号以将所述初始信号端的信号传输到所述第一节点。
本公开一种示例性实施例中，所述第二复位电路还连接复位信号端、第一栅极驱动信号端、第六节点，用于响应所述复位信号端的信号以连通所述初始信号端和所述第六节点，以及用于响应所述第一栅极驱动信号端的信号以连通所述第六节点和所述第一节点。
本公开一种示例性实施例中，所述数据写入电路包括：第四晶体管，第四晶体管的第一极连接所述数据信号端，第二极连接所述第二节点，栅极连接所述第一栅极驱动信号端。所述补偿电路包括：第二晶体管，第二晶体管的第一极连接所述第一节点，第二极连接所述第三节点，栅极连接所述第二栅极驱动信号端。所述第二复位电路包括：第一晶体管、第九晶体管，第一晶体管的第一极连接所述初始信号端，第二极连接所述第六节点，栅极连接所述复位信号端；第九晶体管的第一极连接所述第六节点，第二极连接所述第一节点，栅极连接所述第一栅极驱动信号端。所述第二存储电路包括第二电容，第二电容连接于所述第二节点和所述第四节点之间。
根据本公开的一个方面，提供一种像素驱动电路的驱动方法，用于驱动上述的像素驱动电路，其中，所述驱动方法包括：
至少在阈值补偿阶段，向第一使能信号端输入无效电平，向第二使能信号端输入有效电平；
在发光阶段，向第一使能信号端输入有效电平，向第二使能信号端输入无效电平。
根据本公开的一个方面，提供一种像素驱动电路的驱动方法，用于驱动上述的像素驱动电路，其中，所述驱动方法包括：
在复位阶段，向复位信号端、第二使能信号端输入有效电平，向第一栅极驱动信号端、第一使能信号端输入无效电平；
在阈值补偿阶段，向第一栅极驱动信号端、第二使能信号端输入有效电平，向复位信号端、第一使能信号端输入无效电平；
在发光阶段，向第一使能信号端输入有效电平，向第一栅极驱动信号端、复位信号端、第二使能信号端输入无效电平。
根据本公开的一个方面，提供一种像素驱动电路的驱动方法，用于驱动上述的像素驱动电路，其中，所述驱动方法包括：
在第一复位阶段，向复位信号端、第二使能信号端输入有效电平，向第一栅极驱动信号端、第一使能信号端、第二栅极驱动信号端输入无效电平；
在第二复位阶段，向复位信号端、第二使能信号端、第一栅极驱动信号端输入有效电平，向第一使能信号端、第二栅极驱动信号端输入无效电平；
在第一阈值补偿阶段，向第一栅极驱动信号端、第二使能信号端、第二栅极驱动 信号端输入有效电平，向复位信号端、第一使能信号端输入无效电平；
在第二阈值补偿阶段，向第二使能信号端、第二栅极驱动信号端输入有效电平，向第一栅极驱动信号端、复位信号端、第一使能信号端输入无效电平；
在发光阶段，向第一使能信号端输入有效电平，向第一栅极驱动信号端、第二栅极驱动信号端、复位信号端、第二使能信号端输入无效电平。
根据本公开的一个方面，提供一种显示面板，其中，所述显示面板包括上述的像素驱动电路。
根据本公开的一个方面，提供一种显示面板，其中，所述显示面板包括像素驱动电路，所述像素驱动电路包括：驱动晶体管、第五晶体管、第八晶体管、第三晶体管、第一电容，所述第五晶体管的第一极连接所述驱动晶体管的第一极，栅极连接第一使能信号线；所述第八晶体管的第一极连接所述第五晶体管的第二极，第二极连接电源线，栅极连接所述第一使能信号线；所述第三晶体管的第一极连接参考电压线，第二极连接所述第五晶体管的第二极，栅极连接第二使能信号线；所述第一电容连接于所述驱动晶体管的栅极和第一极之间。
本公开一种示例性实施例中，所述显示面板还包括：衬底基板、有源层、第一导电层、第二导电层、第三导电层，有源层位于所述衬底基板的一侧，所述有源层包括：第十有源部、第三有源部、第五有源部、第八有源部、第十一有源部，所述第十一有源部分别与所述第三有源部、第五有源部、第八有源部连接，所述第十有源部连接于所述第五有源部远离所述第十一有源部的一端；其中，所述第十有源部用于形成所述驱动晶体管的沟道区，所述第三有源部用于形成所述第三晶体管的沟道区，所述第五有源部用于形成所述第五晶体管的沟道区，所述第八有源部用于形成所述第八晶体管的沟道区。第一导电层位于所述有源层背离所述衬底基板的一侧，所述第一导电层包括：第十导电部、第一使能信号线、第八导电部、第二使能信号线；其中，所述第十导电部在所述衬底基板上的正投影覆盖所述第十有源部在所述衬底基板上的正投影，所述第十导电部用于形成所述驱动晶体管的栅极和所述第一电容的第一电极；所述第一使能信号线在所述衬底基板上的正投影沿第一方向延伸，且第一使能信号线在所述衬底基板上的正投影覆盖所述第五有源部在所述衬底基板上的正投影，所述第一使能信号线的部分结构用于形成所述第五晶体管的栅极；所述第二使能信号线在所述衬底基板上的正投影沿第一方向延伸，且第二使能信号线在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第二使能信号线的部分结构用于形成所述第三晶体管的栅极；所述第八导电部连接于所述第一使能信号线，所述第八导电部在所述衬底基板上的正投影覆盖所述第八有源部在所述衬底基板上的正投影，所述第八导电部用于形成所述第八晶体管的栅极。第二导电层位于所述第一导电层背离所述衬底基板的一侧，所述第二导电层包括第十一导电部，所述第十一导电部在所述衬底基板上的正投影与所述第十导电部在所述衬底基板上的正投影至少部分重合，所 述第十一导电部用于形成所述第一电容的第二电极。第三导电层位于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括：第一连接部，所述第一连接部分别通过过孔连接所述第十一有源部和所述第十一导电部。
本公开一种示例性实施例中，所述有源层还包括：第十二有源部、第十三有源部，第十二有源部连接于所述第八有源部远离所述第十一有源部的一端；第十三有源部连接于所述第三有源部远离所述第十一有源部的一端。所述第三导电层还包括参考电压线，参考电压线在所述衬底基板上的正投影沿所述第一方向延伸，所述参考电压线通过过孔连接所述第十三有源部。所述显示面板还包括第四导电层，第四导电层位于所述第三导电层背离所述衬底基板的一侧，所述第四导电层包括所述电源线，所述电源线在所述衬底基板上的正投影沿第二方向延伸，所述第一方向和第二方向相交，所述电源线通过过孔连接所述第十二有源部。
本公开一种示例性实施例中，所述像素驱动电路还包括第二晶体管、第四晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极，栅极连接第一栅线，所述第四晶体管的第一极连接数据线，第二极连接所述驱动晶体管的第一极，栅极连接所述第一栅线；所述像素驱动电路为多个，多个所述像素驱动电路包括在所述第一方向上间隔分布的第一像素驱动电路和第二像素驱动电路；所述第一导电层还包括：第四导电部，所述第四导电部的部分结构用于形成所述第一像素驱动电路中第二晶体管的栅极，所述第四导电部的另外部分结构用于形成所述第二像素驱动电路中第四晶体管的栅极；所述第四导电部为多个，多个所述第四导电部在所述衬底基板上的正投影在所述第一方向上间隔分布；所述第三导电层还包括：所述第一栅线，所述第一栅线在所述衬底基板上的正投影沿所述第一方向延伸，所述第一栅线分别通过过孔连接在所述第一方向上间隔分布的多个所述第四导电部；其中，所述第三导电层的方块电阻小于所述第一导电层的方块电阻。
本公开一种示例性实施例中，所述像素驱动电路还包括第二晶体管、第四晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极，所述第四晶体管的第一极连接数据线，第二极连接所述驱动晶体管的第一极。所述有源层还包括：第二有源部、第十四有源部，第二有源部用于形成所述第二晶体管的沟道区；第十四有源部连接所述第二有源部，且所述第十四有源部用于连接所述第十导电部。所述第二导电层还包括：第十二导电部，第十二导电部连接于所述第十一导电部，所述第十二导电部在所述衬底基板上的正投影沿所述第二方向延伸，且所述第十二导电部在所述衬底基板上的正投影至少部分位于所述第十四有源部在所述衬底基板上的正投影和所述数据线在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述像素驱动电路为多个，多个所述像素驱动电路包括在所述第一方向上间隔分布的第一像素驱动电路和第二像素驱动电路；所述第一导电层还包括：第四导电部，所述第四导电部的部分结构用于形成所述第一像素驱动 电路中第二晶体管的栅极，所述第四导电部的另外部分结构用于形成所述第二像素驱动电路中第四晶体管的栅极；所述第四导电部为多个，多个所述第四导电部在所述衬底基板上的正投影在所述第一方向上间隔分布；所述第十二导电部在所述衬底基板上的正投影位于在所述第一方向上相邻的两个所述第四导电部在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极；所述有源层还包括：第二有源部、第十四有源部，第二有源部用于形成所述第二晶体管的沟道区；第十四有源部连接所述第二有源部，且所述第十四有源部用于连接所述第十导电部；所述电源线在所述衬底基板上的正投影与所述第十四有源部在所述衬底基板上的正投影至少部分重合。
本公开一种示例性实施例中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极。所述有源层还包括：第二有源部、第十四有源部，第二有源部用于形成所述第二晶体管的沟道区；第十四有源部连接所述第二有源部，且所述第十四有源部用于连接所述第十导电部。所述第三导电层还包括：第二连接部，所述第二连接部分别通过过孔连接所述第十导电部和所述第十四有源部，所述电源线在所述衬底基板上的正投影与所述第二连接部在所述衬底基板上的正投影至少部分重合。
本公开一种示例性实施例中，所述显示面板还包括发光单元，所述像素驱动电路连接所述发光单元的第一电极，所述像素驱动电路还包括第一晶体管、第七晶体管，所述第一晶体管的第一极连接第一初始信号线，第二极连接所述驱动晶体管的栅极，所述第七晶体管的第一极连接第二初始信号线，第二极连接所述发光单元的第一电极。所述有源层还包括：第一有源部、第七有源部、第一初始信号线、第二初始信号线，第一有源部用于形成所述第一晶体管的沟道区；第七有源部用于形成所述第七晶体管的沟道区；第一初始信号线连接于所述第一有源部远离所述第十有源部的一端；第二初始信号线连接于所述第七有源部远离所述第十有源部的一端。
本公开一种示例性实施例中，所述像素驱动电路还包括第一晶体管，所述第一晶体管的第一极连接第一初始信号线，第二极连接所述驱动晶体管的栅极，栅极连接复位线；所述第一导电层还包括：多个第一导电部，多个所述第一导电部在所述衬底基板上的正投影在所述第一方向上间隔分布，所述第一导电部的部分结构用于形成所述第一晶体管的栅极，所述第一导电部的另外部分结构用于形成同一所述像素驱动电路中所述第一晶体管的栅极；所述第三导电层还包括所述复位线，所述复位线在所述衬底基板上的正投影沿所述第一方向延伸，所述复位线分别通过过孔连接在所述第一方向上分布的多个所述第一导电部，所述第三导电层的方块电阻小于所述第一导电层的方块电阻。
本公开一种示例性实施例中，所述像素驱动电路还包括第四晶体管、第九晶体管，所述第四晶体管的第一极连接数据线，第二极连接所述驱动晶体管的第一极，栅极连接第一栅线，所述第九晶体管的第一极连接初始信号线，第二极连接所述驱动晶体管的栅极，栅极连接所述第一栅线。所述第一导电层还包括：多个第九导电部，多个所述第九导电部在所述衬底基板上的正投影在所述第一方向上间隔分布，所述第九导电部的部分结构用于形成所述第四晶体管的栅极，所述第九导电部的另外部分结构用于形成同一像素驱动电路中所述第九晶体管的栅极。所述第三导电层还包括：所述第一栅线，第一栅线在所述衬底基板上的正投影沿所述第一方向延伸，所述第一栅线分别通过过孔连接在所述第一方向上分布的多个所述第九导电部，所述第三导电层的方块电阻小于所述第一导电层的方块电阻。
本公开一种示例性实施例中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极连接所述驱动晶体的栅极，第二极连接所述驱动晶体管的第二极，栅极连接第二栅线。所述第一导电层还包括：多个第二导电部，多个所述第二导电部在所述衬底基板上的正投影沿所述第一方向间隔分布，所述第二导电部用于形成所述第二晶体管的栅极。所述第三导电层还包括：所述第二栅线，第二栅线在所述衬底基板上的正投影沿所述第一方向延伸，所述第二栅线分别通过过孔连接在所述第一方向上分布的多个所述第二导电部。
本公开一种示例性实施例中，所述有源层还包括：第十二有源部、第十三有源部，第十二有源部连接于所述第八有源部远离所述第十一有源部的一端；第十三有源部连接于所述第三有源部远离所述第十一有源部的一端。所述第三导电层还包括：电源线，电源线在所述衬底基板上的正投影沿第二方向延伸，所述第二方向与所述第一方向相交，所述电源线通过过孔连接所述第十二有源部。所述显示面板还包括：第四导电层，第四导电层位于所述第三导电层背离所述衬底基板的一侧，所述第四导电层包括所述参考电压线，所述参考电压线在所述衬底基板上的正投影沿第二方向延伸，所述参考电压线通过过孔连接所述第十三有源部。
本公开一种示例性实施例中，所述像素驱动电路还包括第一晶体管，所述第一晶体管的第一极连接初始信号线，第二极连接所述驱动晶体管的栅极。所述有源层还包括：第一子有源部、第二子有源部、第三子有源部，第一子有源部用于形成所述第一晶体管的第一沟道区；第二子有源部用于形成所述第一晶体管的第二沟道区；第三子有源部连接于所述第一子有源部和第二子有源部之间。所述电源线在所述衬底基板上的正投影与所述第三子有源部在所述衬底基板上的正投影至少部分重合。
本公开一种示例性实施例中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极；所述有源层还包括：第四子有源部、第五子有源部、第六子有源部，第四子有源部用于形成所述第二晶体管的沟道区；第五子有源部用于形成所述第二晶体管的沟道区；第 六子有源部连接于所述第四子有源部和所述第五子有源部之间。所述第四导电层还包括：第十七导电部，第十七导电部连接于所述参考电压线；所述显示面板包括在所述第一方向上相邻设置的第一像素驱动电路和第二像素驱动电路；其中，所述第一像素驱动电路中第十七导电部在所述衬底基板上的正投影与所述第二像素驱动电路中第六子有源部在所述衬底基板上的正投影至少部分重合。
本公开一种示例性实施例中，所述显示面板还包括发光单元，所述像素驱动电路连接所述发光单元的第一电极，所述像素驱动电路还包括第一晶体管、第七晶体管，所述第一晶体管的第一极连接初始信号线，第二极连接所述驱动晶体管的栅极，所述第七晶体管的第一极连接所述初始信号线，第二极连接所述发光单元的第一电极。所述像素驱动电路为多个，多个所述像素驱动电路包括在第二方向上相邻的第三像素驱动电路和第四像素驱动电路，所述第一方向和所述第二方向相交。所述有源层还可以包括：第一有源部、第七有源部、第十五有源部，第一有源部用于形成所述第一晶体管的沟道区；第七有源部用于形成所述第七晶体管的沟道区；所述第十五有源部连接于所述第三像素驱动电路中第一有源部和所述第四像素驱动电路中第七有源部之间。所述显示面板还包括：第四导电层，所述第四导电层包括所述初始信号线，初始信号线在所述衬底基板上的正投影沿所述第二方向延伸，所述初始信号线通过过孔连接所述第十五有源部。
本公开一种示例性实施例中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极。所述有源层还包括：第二有源部、第十四有源部，第二有源部用于形成所述第二晶体管的沟道区；第十四有源部连接所述第二有源部，且所述第十四有源部用于连接所述第十导电部。所述初始信号线包括第一子初始信号线，所述第一子初始信号线在所述衬底基板上的正投影与所述第十四有源部在所述衬底基板上的正投影至少部分重合。
本公开一种示例性实施例中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极。所述有源层还包括：第二有源部、第十四有源部，第二有源部用于形成所述第二晶体管的沟道区；第十四有源部连接所述第二有源部，且所述第十四有源部用于连接所述第十导电部。所述第三导电层还包括：第二连接部，所述第二连接部分别通过过孔连接所述第十导电部和所述第十四有源部；所述初始信号线包括第一子初始信号线，所述第一子初始信号线在所述衬底基板上的正投影与所述第二连接部在所述衬底基板上的正投影至少部分重合。
本公开一种示例性实施例中，所述初始信号线还包括第二子初始信号线，所述第二子初始信号线与所述第一子初始信号线连接，所述第二子初始信号线在所述衬底基板上的正投影与所述电源线在所述衬底基板上的正投影至少部分重合。
本公开一种示例性实施例中，所述像素驱动电路还包括第一晶体管、第二晶体管、 第四晶体管，所述第一晶体管的第一极连接初始信号线，第二极连接所述驱动晶体管的栅极，栅极连接复位信号线，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极，所述第四晶体管的第一极连接数据线，第二极连接所述驱动晶体管的第一极。所述有源层还包括：第二有源部、第十四有源部，第二有源部用于形成所述第二晶体管的沟道区；第十四有源部连接所述第二有源部，且所述第十四有源部用于连接所述第十导电部。所述第二导电层还包括：所述复位信号线、第十三导电部，所述复位信号线在所述衬底基板上的正投影沿所述第一方向延伸；第十三导电部连接于所述复位信号线，所述第十三导电部在所述衬底基板上的正投影位于所述第十四有源部在所述衬底基板上的正投影与所述数据线在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述第十五有源部为多个，所述有源层还包括：有源线，所述有源线在所述衬底基板上的正投影沿所述第一方向延伸，所述有源线连接在所述第一方向上分布的多个所述第十五有源部。
本公开一种示例性实施例中，所述像素驱动电路还包括第二电容，所述第二电容的第一电极连接所述第五晶体管的第二极，所述第二电容的第二电极连接所述驱动晶体管的第一极。所述有源层还包括：第十六有源部，第十六有源部连接于所述第五有源部远离所述第十一有源部的一端，所述第十六有源部用于形成所述第二电容的第二电极。所述第二导电层还包括：第十四导电部，第十四导电部连接于所述第十一导电部，所述第十四导电部在所述衬底基板上的正投影与所述第十六有源部在所述衬底基板上的正投影至少部分重合，所述第十四导电部用于形成所述第二电容的第一电极。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中一种像素驱动电路的电路结构示意图；
图2为图1像素驱动电路一种驱动方法中各节点的时序图；
图3为本公开像素驱动电路一种示例性实施例的结构示意图；
图4为图3中像素驱动电路各节点的时序图；
图5为本公开像素驱动电路另一种示例性实施例中的结构示意图；
图6为图5中各个节点的时序图；
图7为本公开像素驱动电路另一种示例性实施例中的结构示意图；
图8为图7中像素驱动电路各节点的时序图；
图9为本公开显示面板一种示例性实施例中的结构版图；
图10为图9中有源层的结构版图；
图11为图9中第一导电层的结构版图；
图12为图9中第二导电层的结构版图；
图13为图9中第三导电层的结构版图；
图14为图9中第四导电层的结构版图；
图15为图9中有源层、第一导电层的结构版图；
图16为图9中有源层、第一导电层、第二导电层的结构版图；
图17为图9中有源层、第一导电层、第二导电层、第三导电层的结构版图；
图18为图9中虚线A位置的部分剖视图；
图19为本公开显示面板一种示例性实施例中的结构版图；
图20为图19中有源层的结构版图；
图21为图19中第一导电层的结构版图；
图22为图19中第二导电层的结构版图；
图23为图19中第三导电层的结构版图；
图24为图19中第四导电层的结构版图；
图25为图19中有源层、第一导电层的结构版图；
图26为图19中有源层、第一导电层、第二导电层的结构版图；
图27为图19中有源层、第一导电层、第二导电层、第三导电层的结构版图；
图28为图19中虚线B位置的部分剖视图；
图29为本公开显示面板一种示例性实施例中的结构版图；
图30为图29中有源层的结构版图；
图31为图29中第一导电层的结构版图；
图32为图29中第二导电层的结构版图；
图33为图29中第三导电层的结构版图；
图34为图29中第四导电层的结构版图；
图35为图29中有源层、第一导电层的结构版图；
图36为图29中有源层、第一导电层、第二导电层的结构版图；
图37为图29中有源层、第一导电层、第二导电层、第三导电层的结构版图；
图38为图29中虚线C位置的部分剖视图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相 同或类似的结构，因而将省略它们的详细描述。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
如图1所示，为相关技术中一种像素驱动电路的电路结构示意图。该像素驱动电路可以包括：第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、电容C。其中，第一晶体管T1的第一极连接第一节点N1，第二极连接初始信号端Vinit，栅极连接复位信号端Re；第二晶体管T2第一极连接驱动晶体管T3的第一极，第二极连接第一节点N1；栅极连接栅极驱动信号端Gate；驱动晶体管T3的栅极连接第一节点N1；第四晶体管T4的第一极连接数据信号端Data，第二极连接驱动晶体管T3的第二极，栅极连接栅极驱动信号端Gate；第五晶体管T5的第一极连接第一电源端VDD，第二极连接驱动晶体管T3的第二极，栅极连接使能信号端EM；第六晶体管T6第一极连接驱动晶体管T3的第一极，栅极连接使能信号端EM；第七晶体管T7的第一极连接初始信号端Vinit，第二极连接第六晶体管T6的第二极。该像素驱动电路可以连接一发光单元OLED，用于驱动该发光单元OLED发光，发光单元OLED可以连接于第六晶体管T6的第二极和第二电源端VSS之间。其中，晶体管T1-T7可以均为P型晶体管。
如图2所示，为图1像素驱动电路一种驱动方法中各节点的时序图。其中，Gate表示栅极驱动信号端Gate的时序，Re表示复位信号端Re的时序，EM表示使能信号端EM的时序，Data表示数据信号端Data的时序。该像素驱动电路的驱动方法可以包括复位阶段t1、补偿阶段t2，发光阶段t3。在复位阶段t1：复位信号端Re输出低电平信号，第一晶体管T1、第七晶体管T7导通，初始信号端Vinit向第一节点N1，第六晶体管T6的第二极输入初始化信号。在补偿阶段t2：栅极驱动信号端Gate输出低电平信号，第四晶体管T4、第二晶体管T2导通，同时数据信号端Data输出驱动信号以向第一节点N1写入电压Vdata+Vth，其中Vdata为驱动信号的电压，Vth为驱动晶体管T3的阈值电压。发光阶段t3：使能信号端EM输出低电平信号，第六晶体管T6、第五晶体管T5导通，驱动晶体管T3在电容C存储的电压Vdata+Vth作用下发光。根据驱动晶体管输出电流公式I＝(μWCox/2L)(Vgs-Vth) 2，其中，μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电压。本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth) 2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。其中，第一电源端由位于显示面板上的电源线提供，然而，由于电源线自身存在压降(IR-drop)，显示面板上不同位置的电源线具有不同的电压，从而导致显示面板在相同灰阶下显示不均匀。该显示不均匀的问题尤其在大尺寸显示面板或竖屏中尤其明显。
基于此，本示例性实施例提供一种像素驱动电路，其中，如图3所示，为本公开像素 驱动电路一种示例性实施例的结构示意图，该像素驱动电路可以包括：驱动电路01、控制电路02、稳压电路03、第一存储电路04，驱动电路01可以连接第一节点N1、第二节点N2、第三节点N3，用于根据所述第一节点N1的信号通过所述第二节点N2向所述第三节点N3提供驱动电流；控制电路02可以连接第一使能信号端EM1、所述第二节点N2、第一电源端VDD、第四节点N4，用于响应所述第一使能信号端EM1的信号连通所述第二节点N2和第四节点N4，以及用于响应所述第一使能信号端EM1的信号连通所述第一电源端VDD和所述第四节点N4；稳压电路03可以连接所述第四节点N4、第二使能信号端EM2、参考电压端Vref，用于响应所述第二使能信号端EM2的信号将所述参考电压端Vref的信号传输到所述第四节点N4；第一存储电路04连接于所述第一节点N1和所述第四节点N4之间，用于存储所述第一节点N1和所述第四节点N4的电荷。
本示例性实施例中，所述驱动电路01可以包括：驱动晶体管DTFT，驱动晶体管DTFT的第一极连接所述第二节点N2，第二极连接所述第三节点N3，栅极连接所述第一节点N1。所述控制电路02可以包括：第五晶体管T5、第八晶体管T8，第五晶体管T5的第一极连接所述第二节点N2，第二极连接所述第四节点N4，栅极连接所述第一使能信号端EM1；第八晶体管T8的第一极连接所述第四节点N4，第二极连接所述第一电源端VDD，栅极连接所述第一使能信号端EM1。所述稳压电路03可以包括：第三晶体管T3，第三晶体管T3的第一极连接所述参考电压端Vref，第二极连接所述第四节点N4，栅极连接所述第二使能信号端EM2。所述第一存储电路04可以包括：第一电容C1，第一电容C1连接于所述第一节点N1和所述第四节点N4之间。
本示例性实施例提供的像素驱动电路可以至少在阈值补偿阶段，向第二使能信号端输入有效电平，向第一使能信号端输入无效电平，从而将参考电压端Vref上的信号传输到第四节点；同时在阈值补偿阶段，第一节点N1会被写入电压Vdata+Vth，其中，Vdata为数据信号，Vth为驱动晶体管的阈值电压，此时第一电容C1两端的电压差为Vdata+Vth-Vref，Vref为参考电压端的电压。在发光阶段，可以向第一使能信号端EM1输入有效电平，向第二使能信号端EM2输入无效电平，在第一电容C1自举作用下，第一电容C1两端的电压维持阈值补偿阶段的电压，从而驱动晶体管输出的电流I＝(μWCox/2L)(Vgs-Vth) 2＝(μWCox/2L)(Vdata+Vth-Vref-Vth) 2，其中，μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差。从而该像素驱动电路输出的电流与第一电源端VDD的电压无关，即应用该像素驱动电路的显示面板不会因为源线自身压降造成显示不均匀。同时，虽然用于提供参考电压端的参考电压线自身也存在电阻，但是参考电压端Vref向第一电容C1写入电压后参考电压线上已经没有电流，从而参考电压线上也就不会产生压降，即显示面板不同位置上参考电压端的电压不会因为参考电压线自身电阻发生差异。
应该理解的是，在其他示例性实施例中，驱动电路、第一存储电路、控制电路还可以为其他结构，例如，驱动电路可以包括多个并联的驱动晶体管，第一存储电路可 以包括多个并联的电容。
本示例性实施例中，为保证阈值补偿阶段结束时，第一电容C1两端的电压为Vdata+Vth-Vref，本实施例至少需要在阈值补偿阶段向第二使能信号端EM2输入有效电平。应该理解的是，在其他示例性实施例中，还可以在发光阶段以外的其他阶段向第二使能信号端EM2输入有效电平，例如，可以在阈值补偿阶段之前的复位阶段向第二使能信号端EM2输入有效电平，以使参考电压端Vref向第四节点N4进行预充电，从而保证在阈值补偿阶段结束前，显示面板不同位置上的第四节点N4可以写入相同的电压。本示例性实施例中，所述第一使能信号端EM1上的信号可以和所述第二使能信号端EM2上的信号极性相反。
本示例性实施例中，如图3所示，所述控制电路02还可以连接所述第三节点N3、第五节点N5、第一使能信号端EM1，所述控制电路02还用于响应所述第一使能信号端EM1的信号以连通所述第三节点N3和所述第五节点N5。控制电路02还可以包括第六晶体管，第六晶体管T6的第一极连接所述第五节点N5，第二极连接所述第三节点N3，栅极连接所述第一使能信号端EM1。所述像素驱动电路还可以包括：第一复位电路05，第一复位电路05连接初始信号端Vinit、第五节点N5，用于响应至少一个控制信号将所述初始信号端Vinit的信号传输到所述第五节点N5。例如，所述第一复位电路05可以连接所述第二使能信号端EM2，所述第一复位电路05可以用于响应所述第二使能信号端EM2的信号将所述初始信号端Vinit的信号传输到所述第五节点N5。所述第一复位电路05可以包括：第七晶体管T7，第七晶体管T7的第一极连接所述初始信号端Vinit，第二极连接所述第五节点N5，栅极连接所述第二使能信号端EM2。
本示例性实施例中，如图3所示，所述像素驱动电路还可以包括：数据写入电路06、补偿电路07，数据写入电路06可以连接所述第二节点N2、数据信号端Vdata，用于响应至少一个控制信号将所述数据信号端Vdata的信号传输到所述第二节点N2；补偿电路07可以连接所述第三节点N3、第一节点N1，用于响应至少一个控制信号以连通所述第一节点N1和所述第三节点N3。本示例性实施例中，所述数据写入电路06可以连接第一栅极驱动信号端Gate1，所述数据写入电路06可以用于响应所述第一栅极驱动信号端Gate1的信号将所述数据信号端Vdata的信号传输到所述第二节点N2；所述补偿电路07可以连接所述第一栅极驱动信号端Gate1，所述补偿电路07可以用于响应所述第一栅极驱动信号端Gate1的信号以连通所述第一节点N1和所述第三节点N3。
本示例性实施例中，如图3所示，所述像素驱动电路还可以包括：第二复位电路09，第二复位电路09连接所述第一节点N1、初始信号端Vinit、复位信号端Reset，第二复位电路09用于响应所述复位信号端Reset的信号将所述初始信号端Vinit的信号传输到所述第一节点N1。
本示例性实施例中，如图3所示，所述数据写入电路06可以包括：第四晶体管 T4，第四晶体管T4的第一极连接所述数据信号端Vdata，第二极连接所述第二节点N2，栅极连接所述第一栅极驱动信号端Gate1。所述补偿电路07可以包括：第二晶体管T2，第二晶体管T2的第一极连接所述第一节点N1，第二极连接所述第三节点N3，栅极连接所述第一栅极驱动信号端Gate1。所述第二复位电路09可以包括：第一晶体管T1，第一晶体管T1的第一极连接所述初始信号端Vinit，第二极连接所述第一节点N1，栅极连接所述复位信号端Reset。
本示例性实施例中，第五节点N5可以用于连接一发光单元OLED的第一电极，发光单元OLED的第二电极可以连接第二电源端VSS，发光单元OLED可以为发光二极管。第一晶体管T1到第八晶体管T8，以及驱动晶体管DTFT均可以为P型晶体管，第一电源端VDD可以为高电平信号端，第二电源端VSS可以为低电平信号端。
如图4所示，为图3中像素驱动电路各节点的时序图。其中，Reset为复位信号端Reset的时序图，Vinit为初始信号端Vinit的时序图，EM1为第一使能信号端EM1的时序图，EM2为第二使能信号端EM2的时序图，Vdata为数据信号端Vdata的时序图，Gate1为第一栅极驱动信号端Gate1的时序图。该像素驱动电路的驱动方法可以包括四个阶段：复位阶段t1、阈值补偿阶段t2、缓冲阶段t3、发光阶段t4。在复位阶段t1，可以向复位信号端Reset、第二使能信号端EM2输入有效电平(低电平)，向第一栅极驱动信号端Gate1、第一使能信号端EM1输入无效电平(高电平)。第一晶体管T1、第七晶体管T7、第三晶体管T3导通，初始信号端Vinit向第一节点N1、第五节点N5输入初始信号，参考电压端Vref向第四节点N4预充参考电压，其中，向第五节点N5写入初始信号可以消除发光二极管内部发光界面上没有复合的载流子，缓解发光二极管的老化。在阈值补偿阶段t2，向第一栅极驱动信号端Gate1、第二使能信号端EM2输入有效电平，向复位信号端Reset、第一使能信号端EM1输入无效电平，第二晶体管T2、第四晶体管T4、第七晶体管T7、第三晶体管T3导通，参考电压端Vref持续向第四节点N4写入参考电压，数据信号端Vdata向第一节点N1写入电压Vdata+Vth，此时，第一电容C1两端的电压为Vdata+Vth-Vref，其中，Vdata为数据信号端的电压，Vth为驱动晶体管的阈值电压，Vref为参考电压端的电压。在缓冲阶段t3，向第二使能信号端EM2输入有效电平，向第一栅极驱动信号端Gate1、复位信号端Reset、第一使能信号端EM1输入无效电平。第一电容C1两端的电压维持Vdata+Vth-Vref。在发光阶段t4，向第一使能信号端EM1输入有效电平，向第一栅极驱动信号端Gate1、复位信号端Reset、第二使能信号端EM2输入无效电平。第六晶体管T6、第五晶体管T5、第八晶体管T8导通，第一电容C1在自举作用下两端电压维持Vdata+Vth-Vref，从而驱动晶体管输出的电流I＝(μWCox/2L)(Vgs-Vth) 2＝(μWCox/2L)(Vdata+Vth-Vref-Vth) 2，其中，μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差。该像素驱动电路输出的电流与第一电源端VDD的电压无关，即应用该像 素驱动电路的显示面板不会因为源线自身存在压降造成显示不均匀。
应该理解的是，在其他示例性实施例中，数据写入电路06、补偿电路07、第一复位电路05还可以有其他的连接方式，例如，如图5所示，为本公开像素驱动电路另一种示例性实施例中的结构示意图。其中，所述数据写入电路06可以连接所述第二使能信号端EM2，所述数据写入电路06用于响应所述第二使能信号端EM2的信号将所述数据信号端Vdata的信号传输到所述第二节点N2；所述补偿电路07可以连接所述第二使能信号端EM2，所述补偿电路用于响应所述第二使能信号端EM2的信号以连通所述第一节点N1和所述第三节点N3；第一复位电路05可以连接复位信号端Reset，第一复位电路用于响应复位信号端Reset的信号以将初始信号端Vinit的信号传输到第五节点N5。如图6所示，为图5中各个节点的时序图，该像素驱动电路驱动方法同样可以包括四个阶段：复位阶段t1、阈值补偿阶段t2、缓冲阶段t3、发光阶段t4。图5所示像素驱动电路与图3所示像素驱动电路不同的是，图5所示像素驱动电路可以仅通过第二使能信号端EM2控制数据写入电路06、补偿电路07、稳压电路03，从而在阈值补偿阶段向第一电容C1两端写入电压Vdata+Vth-Vref。
应该理解的是，在其他示例性实施例中，图3、图5所示像素驱动电路驱动方法还可以不设置缓冲阶段。图5中第一复位电路05的控制端还可以共用第二使能信号端EM2，即第七晶体管T7的栅极可以连接第二使能信号端。图3中第一复位电路05的控制端可以共用复位信号端Reset，即第七晶体管T7的栅极可以连接复位信号端Reset。第一复位电路和第二复位电路还可以连接具有不同电位的初始信号端。
如图7所示，为本公开像素驱动电路另一种示例性实施例中的结构示意图。所述像素驱动电路还可以包括：第二存储电路08，第二存储电路08可以连接于所述第二节点N2和所述第四节点N4之间，用于存储第二节点N2和所述第四节点N4的电荷。所述数据写入电路06还可以连接第一栅极驱动信号端Gate1，所述数据写入电路06可以用于响应所述第一栅极驱动信号端Gate1的信号将所述数据信号端Vdata的信号传输到所述第二节点N2；所述补偿电路07还可以连接第二栅极驱动信号端Gate2，所述补偿电路07可以用于响应所述第二栅极驱动信号端Gate2的信号以连通所述第一节点N1和所述第三节点N3。本示例性实施例中，第二复位电路09可以连接所述第一节点N1、初始信号端Vinit，用于响应至少一个控制信号以将所述初始信号端Vinit的信号传输到所述第一节点N1。例如，所述第二复位电路09可以连接复位信号端Reset、第一栅极驱动信号端Gate1、第六节点N6，用于响应所述复位信号端Reset的信号以连通所述初始信号端Vinit和所述第六节点N6，以及用于响应所述第一栅极驱动信号端Gate1的信号以连通所述第六节点N6和所述第一节点N1。
本示例性实施例中，如图7所示，所述数据写入电路06可以包括：第四晶体管T4，第四晶体管T4的第一极连接所述数据信号端Vdata，第二极连接所述第二节点N2，栅极连接所述第一栅极驱动信号端Gate1。所述补偿电路07可以包括：第二晶体 管T2，第二晶体管T2的第一极连接所述第一节点N1，第二极连接所述第三节点N3，栅极连接所述第二栅极驱动信号端Gate2。所述第二复位电路09可以包括：第一晶体管T1、第九晶体管T9，第一晶体管T1的第一极连接所述初始信号端Vinit，第二极连接所述第六节点N6，栅极连接所述复位信号端Reset；第九晶体管T9的第一极连接所述第六节点N6，第二极连接所述第一节点N1，栅极连接所述第一栅极驱动信号端Gate1。所述第二存储电路08可以包括第二电容C2，第二电容C2连接于所述第二节点N2和所述第四节点N4之间。在其他示例性实施例中，第二存储电路08还可以连接于第二节点N2和其他稳定电压端之间。
本示例性实施例中，第一晶体管T1到第九晶体管T9，以及驱动晶体管DTFT均可以为P型晶体管，第一电源端VDD可以为高电平信号端，第二电源端VSS可以为低电平信号端。
如图8所示，为图7中像素驱动电路各节点的时序图。其中，Reset为复位信号端Reset的时序图，Vinit为初始信号端Vinit的时序图，EM1为第一使能信号端EM1的时序图，EM2为第二使能信号端EM2的时序图，Vdata为数据信号端Vdata的时序图，Gate1为第一栅极驱动信号端Gate1的时序图，Gate2为第二栅极驱动信号端Gate2的时序图。该像素驱动电路的驱动方法可以包括五个阶段：第一复位阶段t1、第二复位阶段t2、第一阈值补偿阶段t3、第二阈值补偿阶段t4、发光阶段t5。在第一复位阶段t1，向复位信号端Reset、第二使能信号端EM2输入有效电平(低电平)，向第一栅极驱动信号端Gate1、第一使能信号端EM1、第二栅极驱动信号端Gate2输入无效电平(高电平)。第七晶体管T7、第三晶体管T3导通，参考电压端Vref向第四节点N4预写入参考电压，初始信号端Vinit向第五节点写入初始信号。在第二复位阶段t2，向复位信号端Reset、第二使能信号端EM2、第一栅极驱动信号端Gate1输入有效电平，向第一使能信号端EM1、第二栅极驱动信号端Gate2输入无效电平。第一晶体管T1、第九晶体管T9、第七晶体管T7、第三晶体管T3、第四晶体管T4导通，初始信号端Vinit向第一节点N1写入初始信号，参考电压端Vref持续向第四节点N4写入参考电压。在第一阈值补偿阶段t3，向第一栅极驱动信号端Gate1、第二使能信号端EM2、第二栅极驱动信号端Gate2输入有效电平，向复位信号端Reset、第一使能信号端EM1输入无效电平。第二晶体管T2、第四晶体管T4、第七晶体管T7、第三晶体管T3导通，第一节点N1的电压持续上升，直到第一阈值补偿阶段t3结束第一节点N1的电压还可以处于上升阶段。在第二阈值补偿阶段t4，向第二使能信号端EM2、第二栅极驱动信号端Gate2输入有效电平，向第一栅极驱动信号端Gate1、复位信号端Reset、第一使能信号端EM1输入无效电平。第二晶体管T2导通，存储于第二电容C2的第二节点N2的电荷继续向第一节点充电，直到第一节点N1的电压为Vdata+Vth，此时，第一电容C1两端的电压为Vdata+Vth-Vref，其中，Vdata为数据信号端的电压，Vth为驱动晶体管的阈值电压，Vref为参考电压端的电压。在发光阶段t5，向第一使能信 号端EM1输入有效电平，向第一栅极驱动信号端Gate1、第二栅极驱动信号端Gate2、复位信号端Reset、第二使能信号端EM2输入无效电平。第六晶体管T6、第五晶体管T5、第八晶体管T8导通，第一电容C1在自举作用下两端电压维持Vdata+Vth-Vref，从而驱动晶体管输出的电流I＝(μWCox/2L)(Vgs-Vth) 2＝(μWCox/2L)(Vdata+Vth-Vref-Vth) 2，其中，μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差。该像素驱动电路输出的电流与第一电源端VDD的电压无关，即应用该像素驱动电路的显示面板不会因为源线自身存在压降造成显示不均匀。相比于图3所示的像素驱动电路，图7所示像素驱动电路中阈值补偿阶段(t3和t4)的时长大于数据信号端有效数据信号的脉宽(t3)，因此，在相同的有效数据信号脉宽情况下，图7所示像素驱动电路可以具有更长的阈值补偿时长。
应该理解的是，在其他示例性实施例中，第九晶体管T9的栅极还可以连接复位信号Reset，本示例性实施例将第九晶体管T9的栅极连接第一栅极驱动信号端Gate1可以便于显示面板的版图设计，关于显示面板的版图结构会在下述内容详细说明。此外，图7中第二复位电路还可以不设置第九晶体管T9。
本示例性实施例还提供一种像素驱动电路的驱动方法，用于驱动上述的像素驱动电路，其中，所述驱动方法包括：
至少在阈值补偿阶段，向第一使能信号端EM1输入无效电平，向第二使能信号端EM2输入有效电平；
在发光阶段，向第一使能信号端EM1输入有效电平，向第二使能信号端EM2输入无效电平。
该像素驱动电路驱动方法在上述内容中已经做出详细说明，此处不再赘述。
本示例性实施例还提供一种像素驱动电路的驱动方法，用于驱动上述的像素驱动电路，其中，所述驱动方法包括：
在复位阶段，向复位信号端、第二使能信号端EM2输入有效电平，向第一栅极驱动信号端Gate1、第一使能信号端EM1输入无效电平；
在阈值补偿阶段，向第一栅极驱动信号端Gate1、第二使能信号端EM2输入有效电平，向复位信号端、第一使能信号端EM1输入无效电平；
在缓冲阶段，向第二使能信号端EM2输入有效电平，向第一栅极驱动信号端Gate1、复位信号端、第一使能信号端EM1输入无效电平；
在发光阶段，向第一使能信号端EM1输入有效电平，向第一栅极驱动信号端Gate1、复位信号端、第二使能信号端EM2输入无效电平。
该像素驱动电路驱动方法在上述内容中已经做出详细说明，此处不再赘述。
本示例性实施例还提供一种像素驱动电路的驱动方法，用于驱动上述的像素驱动电路，其中，所述驱动方法包括：
在第一复位阶段，向复位信号端、第二使能信号端EM2输入有效电平，向第一栅极驱动信号端Gate1、第一使能信号端EM1、第二栅极驱动信号端Gate2输入无效电平；
在第二复位阶段，向复位信号端、第二使能信号端EM2、第一栅极驱动信号端Gate1输入有效电平，向第一使能信号端EM1、第二栅极驱动信号端Gate2输入无效电平；
在第一阈值补偿阶段，向第一栅极驱动信号端Gate1、第二使能信号端EM2、第二栅极驱动信号端Gate2输入有效电平，向复位信号端、第一使能信号端EM1输入无效电平；
在第二阈值补偿阶段，向第二使能信号端EM2、第二栅极驱动信号端Gate2输入有效电平，向第一栅极驱动信号端Gate1、复位信号端、第一使能信号端EM1输入无效电平；
在发光阶段，向第一使能信号端EM1输入有效电平，向第一栅极驱动信号端Gate1、第二栅极驱动信号端Gate2、复位信号端、第二使能信号端EM2输入无效电平。
该像素驱动电路驱动方法在上述内容中已经做出详细说明，此处不再赘述。
本示例性实施例还提供一种显示面板，其中，所述显示面板包括上述的像素驱动电路。该显示面板可以应用于手机、平板电脑、电视等显示装置。
本示例性实施例还提供一种显示面板，其中，所述显示面板可以包括如图3所示的像素驱动电路。该显示面板可以包括依次层叠设置的衬底基板、有源层、第一导电层、第二导电层、第三导电层、第四导电层，如图9-17所示，图9为本公开显示面板一种示例性实施例中的结构版图，图10为图9中有源层的结构版图，图11为图9中第一导电层的结构版图，图12为图9中第二导电层的结构版图，图13为图9中第三导电层的结构版图，图13为图9中第四导电层的结构版图，图15为图9中有源层、第一导电层的结构版图，图16为图9中有源层、第一导电层、第二导电层的结构版图，图17为图9中有源层、第一导电层、第二导电层、第三导电层的结构版图。
如图9、10、15所示，有源层可以包括第一有源部51、第二有源部52、第三有源部53、第四有源部54、第五有源部55、第六有源部56、第七有源部57、第八有源部58、第十有源部510、第十一有源部511、第十二有源部512、第十三有源部513、第十四有源部514、第一初始信号线Vinit1，第二初始信号线Vinit2。其中，第一有源部51包括子有源部5110和子有源部5120，子有源部5110和子有源部5120可以用于形成第一晶体管的两个沟道区；第二有源部52可以包括子有源部521和子有源部522，子有源部521和子有源部522可以用于形成第二晶体管的两个沟道区；第三有源部53用于形成第三晶体管T3的沟道区；第四有源部54用于形成第四晶体管T4的沟道区；第五有源部55用于形成第五晶体管T5的沟道区；第六有源部56用于形成第六晶体管T6的沟道区；第七有源部57用于形成第七晶体管T7的沟道区；第八有源部58用于 形成第八晶体管T8的沟道区，第十有源部510用于形成驱动晶体管DTFT的沟道区。所述第十一有源部511可以分别与所述第三有源部53、第五有源部55、第八有源部58连接，所述第十有源部510可以连接于所述第五有源部55远离所述第十一有源部511的一端，第十二有源部512可以连接于所述第八有源部58远离所述第十一有源部511的一端；第十三有源部513可以连接于所述第三有源部53远离所述第十一有源部511的一端。第一初始信号线Vinit1连接于第一有源部51远离所述第十四有源部514的一端，用于向第一晶体管T1提供初始信号端，第二初始信号线Vinit2可以连接于第七有源部57远离所述第六有源部56的一端，用于向第七晶体管T7提供初始信号端。其中，第一初始信号线Vinit1在衬底基板上的正投影和第二初始信号线Vinit2在衬底基板上的正投影均可以沿第一方向X延伸，第一方向X可以为显示面板的行方向。在列方向上相邻的两个像素驱动电路可以共用一条初始信号线，例如，第一初始信号线Vinit1还可以用于向上一行像素驱动电路中的第七晶体管T7提供初始信号端。第二初始信号线Vinit2还可以用于向下一行像素驱动电路中的第一晶体管T1提供初始信号端。有源层可以由多晶硅半导体形成，第一晶体管到第八晶体管、驱动晶体管均可以为低温多晶硅晶体管。
如图9、11、15所示，第一导电层可以包括：第一使能信号线EM1、第二使能信号线EM2、第十导电部110、第八导电部18、第一导电部11，多个第四导电部14。其中，所述第十导电部110在所述衬底基板上的正投影可以覆盖所述第十有源部510在所述衬底基板上的正投影，所述第十导电部110可以用于形成所述驱动晶体管的栅极和所述第一电容的第一电极；所述第一使能信号线EM1在所述衬底基板上的正投影可以沿第一方向X延伸，且第一使能信号线EM1在所述衬底基板上的正投影可以覆盖所述第五有源部55在所述衬底基板上的正投影，所述第一使能信号线EM1的部分结构可以用于形成所述第五晶体管T5的栅极；所述第二使能信号线EM2在所述衬底基板上的正投影可以沿第一方向X延伸，且第二使能信号线EM2在所述衬底基板上的正投影可以覆盖所述第三有源部53在所述衬底基板上的正投影，所述第二使能信号线EM2的部分结构可以用于形成所述第三晶体管T3的栅极；所述第八导电部18可以连接于所述第一使能信号线EM1，所述第八导电部18在所述衬底基板上的正投影可以覆盖所述第八有源部58在所述衬底基板上的正投影，所述第八导电部18可以用于形成所述第八晶体管T8的栅极；第一导电部11可以用于形成第一晶体管的栅极。多个第四导电部14在衬底基板上的正投影可以在第一方向X上间隔分布，第四导电部14的部分结构可以用于一个像素驱动电路中第二晶体管的栅极，第四导电部14的另外部分结构可以用于形成另一像素驱动电路中第四晶体管的栅极，该两个像素驱动电路可以在第一方向X上相邻设置。如图11所示，左侧第四导电部14的部分结构用于形成该像素驱动电路中第二晶体管的栅极，左侧第四导电部14的另外部分结构(图中未画出)可以用于形成该像素驱动电路左侧像素驱动电路中第四晶体管的栅极。此外， 该显示面板可以利用第一导电层为掩膜版对有源层进行导体化处理，被第一导电层覆盖的区域可以形成晶体管的沟道区，未被第一导电层覆盖的区域可以形成导体结构。
如图9、12、16所示，第二导电层可以包括第十一导电部211、第十二导电部212，第十一导电部211上开设有开口2111，第十一导电部211在衬底基板上的正投影可以与第十导电部在衬底基板上的正投影至少部分重合，第十一导电部211可以用于形成第一电容C的第二电极。第十二导电部212可以连接于第十一导电部211，且第十二导电部212在衬底基板上的正投影可以沿第二方向Y延伸，第二方向Y可以为显示面板的列方向。
如图9、13、17所示，第三导电层可以包括参考电压线Vref、第一栅线Gate1、复位信号线Reset、第一连接部31、第二连接部32、转接部33、转接部34、转接部35。参考电压线Vref在衬底基板上的正投影、第一栅线Gate1在衬底基板上的正投影、复位信号线Reset在衬底基板上的正投影均可以沿第一方向X延伸。参考电压线Vref用于提供参考电压端，第一栅线Gate1用于提供第一栅极驱动信号端，复位信号线Reset用于提供复位信号端。如图17所示，参考电压线Vref可以通过过孔H2连接第十三有源部513，以连接第三晶体管T3的第一极和参考电压端。第一连接部31可以通过过孔H3连接第十一有源部511，通过过孔H4连接第十一导电部211，以连接第三晶体管的第二极和第一电容C1的第二电极。转接部34可以通过过孔H5连接第十二有源部512，以连接第八晶体管的第二极。转接部33可以通过过孔H1连接第六有源部56和第七有源部57之间的有源层，以连接第五节点。第二连接部32可以通过过孔H6连接第十导电部110，通过过孔H7连接第十四有源部514，以连接驱动晶体管栅极和第二晶体管的第一极，其中，过孔H6在衬底基板上的正投影可以位于开口2111在衬底基板上的正投影以内，以使过孔H6与第十一导电部211绝缘。转接部35可以通过过孔H9连接第四有源部54远离第十有源部510一端的有源层，以连接第四晶体管的第一极。复位信号线Reset可以通过过孔连接位于同一行的多个第一导电部11，以连接第一晶体管的栅极和复位信号端。第一栅线Gate1可以通过过孔H8连接第二导电部14，以连接第一栅极驱动信号端和第二晶体管的栅极，以及第一栅极驱动信号端和第四晶体管的栅极。本示例性实施例中，第三导电层的方块电阻可以小于第二导电层的方块电阻，本示例性实施例将参考电压线Vref、第一栅线Gate1、复位信号线Reset均设置于第三导电层，从而可以提高第一晶体管、第四晶体管、第二晶体管的响应速度。
如图9、14所示，第四导电层可以包括电源线VDD、数据线Vdata、转接部41。电源线VDD用于提供第一电源端，数据线Vdata用于提供数据信号端，电源线VDD在衬底基板上的正投影和数据线Vdata在衬底基板上的正投影均可以沿第二方向Y延伸。电源线VDD可以通过过孔H12连接转接部34，以连接第八晶体管第二极和第一电源端。数据线Vdata可以通过过孔H11连接转接部35，以连接第四晶体管的第一极 和数据信号端。转接部41可以通过过孔H13连接转接部33，转接部41可以用于连接发光单元的第一电极。如图9所示，电源线VDD在衬底基板上的正投影与第十四有源部514在衬底基板上的正投影可以至少部分重合，电源线VDD可以对驱动晶体管栅极起到稳压作用，以降低驱动晶体管栅极在发光阶段的电压波动。电源线VDD在衬底基板上的正投影可以与第二连接部32在衬底基板上的正投影至少部分重合，同样的，电源线VDD可以对驱动晶体管栅极起到稳压作用，以降低驱动晶体管栅极在发光阶段的电压波动。所述第十二导电部212在所述衬底基板上的正投影至少部分可以位于所述第十四有源部414在所述衬底基板上的正投影和所述数据线Vdata在所述衬底基板上的正投影之间。在发光阶段，第十二导电部212连接电源线VDD，第十二导电部212可以屏蔽数据线Vdata对第十四有源部414的干扰，从而进一步稳定驱动晶体管栅极的电压。如图9、16所示，所述第十二导电部212在所述衬底基板上的正投影可以位于在所述第一方向X上相邻的两个所述第四导电部14在所述衬底基板上的正投影之间，即第十二导电部212在所述衬底基板上的正投影与第四导电部14在所述衬底基板上的正投影不相交，该设置可以降低第四导电部14上的寄生电容，从而提高第二晶体管、第四晶体管的响应速度。
如图18所示，为图9中虚线A位置的部分剖视图。该显示面板还可以包括缓冲层62、第一绝缘层63、第二绝缘层64、介电层65、钝化层66、平坦层67，其中，衬底基板61、缓冲层62、有源层、第一绝缘层63、第一导电层、第二绝缘层64、第二导电层、介电层65、第三导电层、钝化层66、平坦层67、第四导电层可以依次层叠设置。其中，缓冲62可以包括氧化硅层、氮化硅层中的至少一层。第一绝缘层63、第二绝缘层64可以为氧化硅层。介电层可以为氮化硅层。钝化层66的材料可以包括有机绝缘材料或无机绝缘材料，例如，氮化硅材料。平坦层67的材料可采用有机树脂等有机材料。第一导电层、第二导电层的材料可以是钼，铝，铜，钛，铌，其中之一或者合金，或者钼/钛合金或者叠层等。第三导电层、第四导电层的材料可以包括金属材料，例如可以是钼，铝，铜，钛，铌，其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层。衬底基板61可以包括依次层叠设置的玻璃基板、阻挡层、聚酰亚胺层，阻挡层可以为无机材料。
本示例性实施例还提供另一种显示面板，其中，所述显示面板可以包括如图3所示的像素驱动电路。该显示面板可以包括依次层叠设置的衬底基板、有源层、第一导电层、第二导电层、第三导电层、第四导电层，如图19-27所示，图19为本公开显示面板一种示例性实施例中的结构版图，图20为图19中有源层的结构版图，图21为图19中第一导电层的结构版图，图22为图19中第二导电层的结构版图，图23为图19中第三导电层的结构版图，图24为图19中第四导电层的结构版图，图25为图19中有源层、第一导电层的结构版图，图26为图19中有源层、第一导电层、第二导电层的结构版图，图27为图19中有源层、第一导电层、第二导电层、第三导电层的结构 版图。
如图19、20、25所示，有源层可以包括第一有源部51、第二有源部52、第三有源部53、第四有源部54、第五有源部55、第六有源部56、第七有源部57、第八有源部58、第十有源部510、第十一有源部511、第十二有源部512、第十三有源部513、第十四有源部514、第十五有源部515、有源线50。其中，第一有源部51可以包括第一子有源部5110和第二子有源部5120，第一子有源部5110和第二子有源部5120可以用于形成第一晶体管的两个沟道区，有源层还可以包括连接于第一子有源部5110和第二子有源部5120之间的第三子有源部5130。第二有源部52可以包括第四子有源部521和第五子有源部522，第四子有源部521和第五子有源部522可以用于形成第二晶体管的两个沟道区，有源层还可以包括连接于第四子有源部521和第五子有源部522之间的第六子有源部523。第三有源部53用于形成第三晶体管T3的沟道区；第四有源部54用于形成第四晶体管T4的沟道区；第五有源部55用于形成第五晶体管T5的沟道区；第六有源部56用于形成第六晶体管T6的沟道区；第七有源部57用于形成第七晶体管T7的沟道区；第八有源部58用于形成第八晶体管T8的沟道区，第十有源部510用于形成驱动晶体管DTFT的沟道区。所述第十一有源部511可以分别与所述第三有源部53、第五有源部55、第八有源部连接58，所述第十有源部510可以连接于所述第五有源部55远离所述第十一有源部511的一端，第十二有源部512连接于所述第八有源部58远离所述第十一有源部511的一端；第十三有源部513连接于所述第三有源部53远离所述第十一有源部511的一端；第十五有源部515连接于第七有源部57远离第六有源部56的一端。有源线50在衬底基板上的正投影沿第一方向X延伸，第一方向X可以为显示面板的行方向，有源线50可以连接位于同一像素电路行的多个第十五有源部515。有源层可以由多晶硅半导体形成，第一晶体管到第八晶体管、驱动晶体管均可以为低温多晶硅晶体管。
如图19、21、25所示，第一导电层可以包括：第一使能信号线EM1、第二使能信号线EM2、第十导电部110、第八导电部18、第十五导电部115、第十三导电部113、第十六导电部116、复位信号线Reset、第一栅线Gate1。第一使能信号线EM1用于提供第一使能信号端，第二使能信号线EM2用于形成第二使能信号端，复位信号线Reset用于提供复位信号端，第一栅线Gate1用于提供第一栅极驱动信号端。第一使能信号线EM1在衬底基板上的正投影、第二使能信号线EM2在衬底基板上的正投影、复位信号线Reset在衬底基板上的正投影、第一栅线Gate1在衬底基板上的正投影均可以沿第一方向X延伸。第十导电部110用于形成所述驱动晶体管的栅极和所述第一电容的第一电极；第一使能信号线EM1在所述衬底基板上的正投影覆盖所述第五有源部55在所述衬底基板上的正投影，所述第一使能信号线EM1的部分结构用于形成所述第五晶体管T5的栅极；第二使能信号线EM2在所述衬底基板上的正投影可以覆盖所述第三有源部53在所述衬底基板上的正投影、第七有源部57在衬底基板上的正投影， 所述第二使能信号线EM2的部分结构可以用于形成所述第三晶体管T3的栅极，第二使能信号线EM2的另外部分结构可以用于形成所述第七晶体管T7的栅极；所述第八导电部18可以连接于所述第一使能信号线EM1，所述第八导电部18在所述衬底基板上的正投影可以覆盖所述第八有源部58在所述衬底基板上的正投影，所述第八导电部18可以用于形成所述第八晶体管T8的栅极。第十三导电部113可以连接于复位信号线Reset面向第一栅线Gate1的一侧，第十五导电部115可以连接于第一栅线Gate1面向复位信号线的一侧，第十六导电部116可以连接于复位信号线背离第一栅线Gate1的一侧。第一栅线Gate1的部分结构可以用于形成第二晶体管、第四晶体管的栅极，第十五导电部115可以用于形成第二晶体管的另一栅极，复位信号线Reset的部分结构可以用于形成第一晶体管的栅极，第十六导电部116可以用于形成第一晶体管的另一栅极。其中，该显示面板可以利用第一导电层为掩膜版对有源层进行导体化处理，被第一导电层覆盖的区域可以形成晶体管的沟道区，未被第一导电层覆盖的区域可以形成导体结构。
如图19、22、26所示，第二导电层可以包括第十一导电部211，第十一导电部211上可以开设有开口2111。第十一导电部211在衬底基板上的正投影可以与第十导电部110在衬底基板上的正投影至少部分重合，第十一导电部211可以用于形成第一电容C1的第二电极。
如图19、23、27所示，第三导电层可以包括：电源线VDD、第一连接部31、第二连接部32、转接部33、转接部34、转接部35、转接部36。电源线VDD用于提供第一电源端，电源线VDD在衬底基板上的正投影可以沿第二方向Y延伸，第二方向可以为显示面板的列方向。如图27所示，电源线VDD可以通过过孔H6连接第十二有源部512，以连接第八晶体管的第二极和第一电源端。第一连接部31可以通过过孔H4连接第十一有源部511，通过过孔H5连接第十一导电部211，以连接第三晶体管的第二极和第一电容C1的第二极。第二连接部32可以通过过孔H7连接第十导电部110，通过过孔H8连接第十四有源部514，以连接驱动晶体管栅极和第二晶体管的第一极，其中，过孔H7在衬底基板上的正投影可以位于开口2111在衬底基板上的正投影以内，以使过孔H7与第十一导电部211绝缘。转接部33可以通过过孔H2连接第十三有源部513，以连接第三晶体管的第一极。转接部34可以通过过孔H1连接第十五有源部515，以连接第七晶体管的第一极。转接部35可以通过过孔H3连接第六有源部56和第七有源部57之间的有源层，以连接第六晶体管的第一极。转接部36可以通过过孔H9连接第四有源部54远离第五有源部55的一端的有源层，以连接第四晶体管的第一极。电源线VDD在衬底基板上的正投影与第三子有源部5130在衬底基板上的正投影可以至少部分重合，电源线VDD可以对第三子有源部5130起到稳压作用，从而降低了由于第三子有源部5130电压波动而向第一晶体管源漏极的异常漏电。
如图19、24所示，第四导电层可以包括初始信号线Vinit，数据线Vdata、参考电 压线Vref、转接部41、第十七导电部42。初始信号线Vinit可以用于提供初始信号端，数据线Vdata可以用于提供数据信号端，参考电压线Vref可以用于提供参考电压端。初始信号线Vinit在衬底基板上的正投影，数据线Vdata在衬底基板上的正投影、参考电压线Vref在衬底基板上的正投影均可以沿第二方向Y延伸。如图19所示，初始信号线Vinit可以通过过孔H11连接转接部34，以连接第七晶体管的第一极，同时第十五有源部515可以与下一行像素驱动电路中的第一子有源部5110连接，因此初始信号线Vinit还可以向下一行像素驱动电路中第一晶体管的第一极提供初始信号端，同理，本行像素驱动电路中第一晶体管的第一极可以通过上一行像素驱动电路中的转接部34连接初始信号线Vinit。初始信号线Vinit可以与有源线50形成网格结构，从而可以降低初始信号线Vinit自身的电阻。初始信号线Vinit可以包括相连接的第一子初始信号线Vinit1和第二子初始信号线Vinit2，第一子初始信号线Vinit1在衬底基板上的正投影和第二子初始信号线Vinit2在衬底基板上的正投影可以在第一方向上相错设置。第一子初始信号线Vinit1在衬底基板上的正投影还可以与第二连接部32在衬底基板上的正投影至少部分重合，第一子初始信号线Vinit1可以对第二连接部32起到稳压作用，从而降低驱动晶体管栅极在发光阶段的电压波动。第一子初始信号线Vinit1在衬底基板上的正投影还可以与第十四有源部514在衬底基板上的正投影至少部分重合，第一子初始信号线Vinit1可以对第十四有源部514起到稳压作用，从而降低驱动晶体管栅极在发光阶段的电压波动。第二子初始信号线Vinit2在衬底基板上的正投影可以与电源线VDD在衬底基板上的正投影至少部分重合，该设置可以降低第二子初始信号线Vinit2对显示面板的遮光影响。数据线Vdata可以通过过孔H13连接转接部36，以连接第四晶体管的第一极和数据信号端。参考电压线Vref可以通过过孔H10连接转接部33，以连接参考电压端和第三晶体管的第一极。转接部41可以通过过孔H12连接转接部35，以连接第六晶体管的第一极，转接部41可以用于连接发光单元的第一极。第十七导电部42可以连接于参考电压线Vref远离数据线Vdata的一侧，第十七导电部42在衬底基板上的正投影可以与右侧像素驱动电路中第六子有源部523在衬底基板上的正投影至少部分重合，第十七导电部42可以对第六子有源部523起到稳压作用，从而降低由于第六子有源部523电压波动而向第二晶体管源漏极的异常漏电。
如图28所示，为图19中虚线B位置的部分剖视图。该显示面板还可以包括缓冲层62、第一绝缘层63、第二绝缘层64、介电层65、钝化层66、平坦层67，其中，衬底基板61、缓冲层62、有源层、第一绝缘层63、第一导电层、第二绝缘层64、第二导电层、介电层65、第三导电层、钝化层66、平坦层67、第四导电层依次层叠设置。其中，缓冲62可以包括氧化硅层、氮化硅层中的至少一层。第一绝缘层63、第二绝缘层64可以为氧化硅层。介电层可以为氮化硅层。钝化层66的材料可以包括有机绝缘材料或无机绝缘材料，例如，氮化硅材料。平坦层67的材料可采用有机树脂等有机材料。第一导电层、第二导电层的材料可以是钼，铝，铜，钛，铌，其中之一或者合 金，或者钼/钛合金或者叠层等。第三导电层、第四导电层的材料可以包括金属材料，例如可以是钼，铝，铜，钛，铌，其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层。衬底基板61可以包括依次层叠设置的玻璃基板、阻挡层、聚酰亚胺层，阻挡层可以为无机材料。
本示例性实施例还提供另一种显示面板，其中，所述显示面板可以包括如图7所示的像素驱动电路。该显示面板可以包括依次层叠设置的衬底基板、有源层、第一导电层、第二导电层、第三导电层、第四导电层，如图29-37所示，图29为本公开显示面板一种示例性实施例中的结构版图，图30为图29中有源层的结构版图，图31为图29中第一导电层的结构版图，图32为图29中第二导电层的结构版图，图33为图29中第三导电层的结构版图，图34为图29中第四导电层的结构版图，图35为图29中有源层、第一导电层的结构版图，图36为图29中有源层、第一导电层、第二导电层的结构版图，图37为图29中有源层、第一导电层、第二导电层、第三导电层的结构版图。
如图29、30、35所示，有源层可以包括第一有源部51、第二有源部52、第三有源部53、第四有源部54、第五有源部55、第六有源部56、第七有源部57、第八有源部58、第九有源部59、第十有源部510、第十一有源部511、第十二有源部512、第十三有源部513、第十四有源部514、第十六有源部、第一初始信号线Vinit1、第二初始信号线Vinit2。其中，第一有源部51可以用于形成第一晶体管的沟道区；第二有源部52可以包括子有源部521和子有源部522，子有源部521和子有源部522可以用于形成第二晶体管的两个沟道区；第三有源部53用于形成第三晶体管T3的沟道区；第四有源部54用于形成第四晶体管T4的沟道区；第五有源部55用于形成第五晶体管T5的沟道区；第六有源部56用于形成第六晶体管T6的沟道区；第七有源部57用于形成第七晶体管T7的沟道区；第八有源部58用于形成第八晶体管T8的沟道区，第九有源部59用于形成第九晶体管T9的沟道区；第十有源部510用于形成驱动晶体管DTFT的沟道区。所述第十一有源部511可以分别与所述第三有源部53、第五有源部55、第八有源部连接58，所述第十有源部510可以连接于所述第五有源部55远离所述第十一有源部511的一端，第十二有源部512连接于所述第八有源部58远离所述第十一有源部511的一端；第十三有源部513连接于所述第三有源部53远离所述第十一有源部511的一端；第十四有源部514连接于第二有源部52和第九有源部59；第十六有源部516连接于第四有源部54和第十有源部510之间，第十六有源部516可以用于形成第二电容的第一电极，第十六有源部516在衬底基板上的正投影在第一方向X上的尺寸可以大于第四有源部54在衬底基板上的正投影在第一方向X上的尺寸。第一初始信号线Vinit1在衬底基板上的正投影和第二初始信号线Vinit2在衬底基板上的正投影均可以沿第一方向X延伸，第一方向X可以为显示面板的行方向。在列方向上相邻的两个像素驱动电路可以共用一条初始信号线，例如，第一初始信号线Vinit1还 可以用于向上一行像素驱动电路中的第七晶体管T7提供初始信号端。第二初始信号线Vinit2还可以用于向下一行像素驱动电路中的第一晶体管T1提供初始信号端。有源层可以由多晶硅半导体形成，第一晶体管到第八晶体管、驱动晶体管均可以为低温多晶硅晶体管。
如图29、31、35所示，第一导电层可以包括：第一使能信号线EM1、第二使能信号线EM2、第十导电部110、第八导电部18、多个第一导电部11，多个第九导电部19，多个第二导电部12。其中，所述第十导电部110在所述衬底基板上的正投影覆盖所述第十有源部510在所述衬底基板上的正投影，所述第十导电部110用于形成所述驱动晶体管的栅极和所述第一电容的第一电极；所述第一使能信号线EM1在所述衬底基板上的正投影可以沿第一方向X延伸，且第一使能信号线EM1在所述衬底基板上的正投影覆盖所述第五有源部55在所述衬底基板上的正投影，所述第一使能信号线EM1的部分结构用于形成所述第五晶体管T5的栅极；所述第二使能信号线EM2在所述衬底基板上的正投影可以沿第一方向X延伸，且第二使能信号线EM2在所述衬底基板上的正投影覆盖所述第三有源部53在所述衬底基板上的正投影、第七有源部57在衬底基板上的正投影，所述第二使能信号线EM2的部分结构可以用于形成所述第三晶体管T3的栅极，第二使能信号线EM2的另外部分结构可以用于形成所述第七晶体管T7的栅极；所述第八导电部18可以连接于所述第一使能信号线EM1，所述第八导电部18在所述衬底基板上的正投影可以覆盖所述第八有源部58在所述衬底基板上的正投影，所述第八导电部18用于形成所述第八晶体管T8的栅极；第一导电部11可以用于形成第一晶体管的栅极。第九导电部19在衬底基板上的正投影可以覆盖第四有源部54在衬底基板上的正投影和第九有源部59在衬底基板上的正投影，第九导电部19可以用于形成第四晶体管的栅极和第九晶体管的栅极。第二导电部12在衬底基板上的正投影可以覆盖第二有源部，第二导电部12可以用于形成第二晶体管的栅极。该显示面板可以利用第一导电层为掩膜版对有源层进行导体化处理，被第一导电层覆盖的区域可以形成晶体管的沟道区，未被第一导电层覆盖的区域可以形成导体结构。
如图29、32、36所示，第二导电层可以包括第十一导电部211、第十四导电部214，第十一导电部在衬底基板上的正投影可以与第十导电部110在衬底基板上的正投影至少部分重合。第十一导电部211可以形成第一电容C1的第二电极。第十四导电部214可以连接于第十一导电部211，第十四导电部214在衬底基板上的正投影可以与第十六有源部516在衬底基板上的正投影至少部分重合，第十四导电部214可以用于形成第二电容C2的第二电极。此外，第十一导电部211上还开设有开口2111。
如图29、33、37所示，第三导电层可以包括参考电压线Vref、第一栅线Gate1、复位信号线Reset、第二栅线Gate2、第一连接部31、第二连接部32、转接部33、转接部34、转接部35。其中，参考电压线Vref在衬底基板上的正投影、第一栅线Gate1在衬底基板上的正投影、复位信号线Reset在衬底基板上的正投影、第二栅线Gate2 在衬底基板上的正投影均可以沿第一方向X延伸。如图37所示，复位信号线Reset可以通过过孔H2连接第一导电部11，以连接复位信号端和第一晶体管的栅极，其中，同一复位信号线Reset可以连接位于同一像素电路行上的多个第一导电部11。第一栅线Gate1可以通过过孔H3连接第九导电部19，以连接第一栅极驱动信号端和第四晶体管的栅极、第九晶体管的栅极，其中，同一第一栅线Gate1可以连接位于同一像素电路行中的多个第九导电部19。第二栅线Gate2可以通过过孔H4连接第二导电部12，以连接第二栅极驱动信号端和第二晶体管的栅极，其中，同一第二栅线Gate2可以连接位于同一像素电路行中的多个第二导电部12。参考电压线Vref可以通过过孔H9连接第十三有源部513，以连接参考电压端和第三晶体管的第一极。第一连接部31可以通过过孔H8连接第十一有源部511，通过过孔H7连接第十一导电部211，以连接第三晶体管的第二极和第一电容C1的第二电极。第二连接部32可以通过过孔H6连接第十导电部110，通过过孔H5连接第十四有源部514，以连接第二晶体管的第一极和驱动晶体管的栅极，其中，过孔H6在衬底基板上的正投影位于开口2111在衬底基板的正投影以内，以使过孔H6与第十一导电部211绝缘。转接部33可以通过过孔H11连接位于第六有源部56和第七有源部57之间的有源层，以连接第六晶体管的第一极。转接部34可以通过过孔H10连接连接第十二有源部512，以连接第八晶体管的第二极。转接部35可以通过过孔H1连接第四有源部54远离第十有源部510一侧的有源层，以连接第四晶体管的第一极。其中，第三导电层的方块电阻可以小于第一导电层的方块电阻。本示例性实施例将复位信号线Reset、第一栅线Gate1、第二栅线Gate2、参考电压线Vref设置于第三导电层，可以降低上述信号线的自身电阻。
如图29、34所示，第四导电层可以包括：数据线Vdata、电源线VDD、转接部41。数据线Vdata可以用于提供数据信号端，电源线VDD可以用于提供第一电源端。数据线Vdata在衬底基板上的正投影、电源线VDD在衬底基板上的正投影均可以沿第二方向Y延伸，第二方向Y可以为显示面板的列方向。如图29所示，电源线VDD可以通过H12连接转接部34，以连接第八晶体管的第二极和第一电源端。数据线Vdata可以通过过孔H13连接转接部35，以连接第四晶体管的第一极和数据信号端。转接部41可以通过过孔H14连接转接部33，以连接第六晶体管的第一极，转接部41可以用于连接发光单元的第一电极。如图29所示，电源线VDD在衬底基板上的正投影可以与第十四有源部514在衬底基板上的正投影至少部分重合，电源线VDD可以对驱动晶体管栅极起到稳压作用，以降低驱动晶体管栅极在发光阶段的电压波动。电源线VDD在衬底基板上的正投影可以与第二连接部32在衬底基板上的正投影至少部分重合，同样的，电源线VDD可以对驱动晶体管栅极起到稳压作用，以降低驱动晶体管栅极在发光阶段的电压波动。
如图38所示，为图29中虚线C位置的部分剖视图。该显示面板还可以包括缓冲层62、第一绝缘层63、第二绝缘层64、介电层65、钝化层66、平坦层67，其中，衬 底基板61、缓冲层62、有源层、第一绝缘层63、第一导电层、第二绝缘层64、第二导电层、介电层65、第三导电层、钝化层66、平坦层67、第四导电层依次层叠设置。其中，缓冲62可以包括氧化硅层、氮化硅层中的至少一层。第一绝缘层63、第二绝缘层64可以为氧化硅层。介电层可以为氮化硅层。钝化层66的材料可以包括有机绝缘材料或无机绝缘材料，例如，氮化硅材料。平坦层67的材料可采用有机树脂等有机材料。第一导电层、第二导电层的材料可以是钼，铝，铜，钛，铌，其中之一或者合金，或者钼/钛合金或者叠层等。第三导电层、第四导电层的材料可以包括金属材料，例如可以是钼，铝，铜，钛，铌，其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层。衬底基板61可以包括依次层叠设置的玻璃基板、阻挡层、聚酰亚胺层，阻挡层可以为无机材料。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (40)

  1. 一种像素驱动电路，其中，包括：
    驱动电路，连接第一节点、第二节点、第三节点，用于根据所述第一节点的信号通过所述第二节点向所述第三节点提供驱动电流；
    控制电路，连接第一使能信号端、所述第二节点、第一电源端、第四节点，用于响应所述第一使能信号端的信号连通所述第二节点和第四节点，以及用于响应所述第一使能信号端的信号连通所述第一电源端和所述第四节点；
    稳压电路，连接所述第四节点、第二使能信号端、参考电压端，用于响应所述第二使能信号端的信号将所述参考电压端的信号传输到所述第四节点；
    第一存储电路，连接于所述第一节点和所述第四节点之间，用于存储所述第一节点和所述第四节点的电荷。
  2. 根据权利要求1所述的像素驱动电路，其中，所述第一使能信号端上的信号和所述第二使能信号端上的信号极性相反。
  3. 根据权利要求1所述的像素驱动电路，其中，所述控制电路还连接所述第三节点、第五节点、第一使能信号端，所述控制电路还用于响应所述第一使能信号端的信号以连通所述第三节点和所述第五节点；
    所述像素驱动电路还包括：
    第一复位电路，连接初始信号端、第五节点，用于响应至少一个控制信号将所述初始信号端的信号传输到所述第五节点。
  4. 根据权利要求3所述的像素驱动电路，其中，所述第一复位电路还来连接所述第二使能信号端，所述第一复位电路用于响应所述第二使能信号端的信号将所述初始信号端的信号传输到所述第五节点。
  5. 根据权利要求4所述的像素驱动电路，其中，
    所述驱动电路包括：
    驱动晶体管，第一极连接所述第二节点，第二极连接所述第三节点，栅极连接所述第一节点；
    所述控制电路包括：
    第五晶体管，第一极连接所述第二节点，第二极连接所述第四节点，栅极连接所述第一使能信号端；
    第八晶体管，第一极连接所述第四节点，第二极连接所述第一电源端，栅极连接所述第一使能信号端；
    第六晶体管，第一极连接所述第五节点，第二极连接所述第三节点，栅极连接所述第一使能信号端；
    所述稳压电路包括：
    第三晶体管，第一极连接所述参考电压端，第二极连接所述第四节点，栅极连接 所述第二使能信号端；
    所述第一存储电路包括：
    第一电容，连接于所述第一节点和所述第四节点之间；
    所述第一复位电路包括：
    第七晶体管，第一极连接所述初始信号端，第二极连接所述第五节点，栅极连接所述第二使能信号端。
  6. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路还包括：
    数据写入电路，连接所述第二节点、数据信号端，用于响应至少一个控制信号将所述数据信号端的信号传输到所述第二节点；
    补偿电路，连接所述第三节点、第一节点，用于响应至少一个控制信号以连通所述第一节点和所述第三节点。
  7. 根据权利要求6所述的像素驱动电路，其中，所述数据写入电路还连接第一栅极驱动信号端，所述数据写入电路用于响应所述第一栅极驱动信号端的信号将所述数据信号端的信号传输到所述第二节点；
    所述补偿电路还连接所述第一栅极驱动信号端，所述补偿电路用于响应所述第一栅极驱动信号端的信号以连通所述第一节点和所述第三节点。
  8. 根据权利要求6所述的像素驱动电路，其中，所述数据写入电路还连接所述第二使能信号端，所述数据写入电路用于响应所述第二使能信号端的信号将所述数据信号端的信号传输到所述第二节点；
    所述补偿电路还连接所述第二使能信号端，所述补偿电路用于响应所述第二使能信号端的信号以连通所述第一节点和所述第三节点。
  9. 根据权利要求7所述的像素驱动电路，其中，所述像素驱动电路还包括：
    第二复位电路，连接所述第一节点、初始信号端、复位信号端，用于响应所述复位信号端的信号将所述初始信号端的信号传输到所述第一节点。
  10. 根据权利要求9所述的像素驱动电路，其中，
    所述数据写入电路包括：
    第四晶体管，第一极连接所述数据信号端，第二极连接所述第二节点，栅极连接所述第一栅极驱动信号端；
    所述补偿电路包括：
    第二晶体管，第一极连接所述第一节点，第二极连接所述第三节点，栅极连接所述第一栅极驱动信号端；
    所述第二复位电路包括：
    第一晶体管，第一极连接所述初始信号端，第二极连接所述第一节点，栅极连接所述复位信号端。
  11. 根据权利要求6所述的像素驱动电路，其中，所述像素驱动电路还包括：
    第二存储电路，连接于所述第二节点，用于存储第二节点的电荷；
    所述数据写入电路还连接第一栅极驱动信号端，所述数据写入电路用于响应所述第一栅极驱动信号端的信号将所述数据信号端的信号传输到所述第二节点；
    所述补偿电路还连接第二栅极驱动信号端，所述补偿电路用于响应所述第二栅极驱动信号端的信号以连通所述第一节点和所述第三节点。
  12. 根据权利要求11所述的像素驱动电路，其中，所述像素驱动电路还包括：
    第二复位电路，连接所述第一节点、初始信号端，用于响应至少一个控制信号以将所述初始信号端的信号传输到所述第一节点。
  13. 根据权利要求12所述的像素驱动电路，其中，所述第二复位电路还连接复位信号端、第一栅极驱动信号端、第六节点，用于响应所述复位信号端的信号以连通所述初始信号端和所述第六节点，以及用于响应所述第一栅极驱动信号端的信号以连通所述第六节点和所述第一节点。
  14. 根据权利要求13所述的像素驱动电路，其中，
    所述数据写入电路包括：
    第四晶体管，第一极连接所述数据信号端，第二极连接所述第二节点，栅极连接所述第一栅极驱动信号端；
    所述补偿电路包括：
    第二晶体管，第一极连接所述第一节点，第二极连接所述第三节点，栅极连接所述第二栅极驱动信号端；
    所述第二复位电路包括：
    第一晶体管，第一极连接所述初始信号端，第二极连接所述第六节点，栅极连接所述复位信号端；
    第九晶体管，第一极连接所述第六节点，第二极连接所述第一节点，栅极连接所述第一栅极驱动信号端；
    所述第二存储电路包括：
    第二电容，连接于所述第二节点和所述第四节点之间。
  15. 一种像素驱动电路的驱动方法，用于驱动权利要求1-14任一项所述的像素驱动电路，其中，所述驱动方法包括：
    至少在阈值补偿阶段，向第一使能信号端输入无效电平，向第二使能信号端输入有效电平；
    在发光阶段，向第一使能信号端输入有效电平，向第二使能信号端输入无效电平。
  16. 一种像素驱动电路的驱动方法，用于驱动权利要求9或10所述的像素驱动电路，其中，所述驱动方法包括：
    在复位阶段，向复位信号端、第二使能信号端输入有效电平，向第一栅极驱动信号端、第一使能信号端输入无效电平；
    在阈值补偿阶段，向第一栅极驱动信号端、第二使能信号端输入有效电平，向复位信号端、第一使能信号端输入无效电平；
    在发光阶段，向第一使能信号端输入有效电平，向第一栅极驱动信号端、复位信号端、第二使能信号端输入无效电平。
  17. 一种像素驱动电路的驱动方法，用于驱动权利要求13或14所述的像素驱动电路，其中，所述驱动方法包括：
    在第一复位阶段，向复位信号端、第二使能信号端输入有效电平，向第一栅极驱动信号端、第一使能信号端、第二栅极驱动信号端输入无效电平；
    在第二复位阶段，向复位信号端、第二使能信号端、第一栅极驱动信号端输入有效电平，向第一使能信号端、第二栅极驱动信号端输入无效电平；
    在第一阈值补偿阶段，向第一栅极驱动信号端、第二使能信号端、第二栅极驱动信号端输入有效电平，向复位信号端、第一使能信号端输入无效电平；
    在第二阈值补偿阶段，向第二使能信号端、第二栅极驱动信号端输入有效电平，向第一栅极驱动信号端、复位信号端、第一使能信号端输入无效电平；
    在发光阶段，向第一使能信号端输入有效电平，向第一栅极驱动信号端、第二栅极驱动信号端、复位信号端、第二使能信号端输入无效电平。
  18. 一种显示面板，其中，所述显示面板包括权利要求1-14任一项所述的像素驱动电路。
  19. 一种显示面板，其中，所述显示面板包括像素驱动电路，所述像素驱动电路包括：
    驱动晶体管；
    第五晶体管，所述第五晶体管的第一极连接所述驱动晶体管的第一极，栅极连接第一使能信号线；
    第八晶体管，所述第八晶体管的第一极连接所述第五晶体管的第二极，第二极连接电源线，栅极连接所述第一使能信号线；
    第三晶体管，所述第三晶体管的第一极连接参考电压线，第二极连接所述第五晶体管的第二极，栅极连接第二使能信号线；
    第一电容，所述第一电容连接于所述驱动晶体管的栅极和第一极之间。
  20. 根据权利要求19所述的显示面板，其中，所述显示面板还包括：
    衬底基板；
    有源层，位于所述衬底基板的一侧，所述有源层包括：第十有源部、第三有源部、第五有源部、第八有源部、第十一有源部，所述第十一有源部分别与所述第三有源部、第五有源部、第八有源部连接，所述第十有源部连接于所述第五有源部远离所述第十一有源部的一端；
    其中，所述第十有源部用于形成所述驱动晶体管的沟道区，所述第三有源部用于 形成所述第三晶体管的沟道区，所述第五有源部用于形成所述第五晶体管的沟道区，所述第八有源部用于形成所述第八晶体管的沟道区；
    第一导电层，位于所述有源层背离所述衬底基板的一侧，所述第一导电层包括：所述第一使能信号线、第二使能信号线、第十导电部、第八导电部；
    其中，所述第十导电部在所述衬底基板上的正投影覆盖所述第十有源部在所述衬底基板上的正投影，所述第十导电部用于形成所述驱动晶体管的栅极和所述第一电容的第一电极；
    所述第一使能信号线在所述衬底基板上的正投影沿第一方向延伸，且第一使能信号线在所述衬底基板上的正投影覆盖所述第五有源部在所述衬底基板上的正投影，所述第一使能信号线的部分结构用于形成所述第五晶体管的栅极；
    所述第二使能信号线在所述衬底基板上的正投影沿所述第一方向延伸，且第二使能信号线在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第二使能信号线的部分结构用于形成所述第三晶体管的栅极；
    所述第八导电部连接于所述第一使能信号线，所述第八导电部在所述衬底基板上的正投影覆盖所述第八有源部在所述衬底基板上的正投影，所述第八导电部用于形成所述第八晶体管的栅极；
    第二导电层，位于所述第一导电层背离所述衬底基板的一侧，所述第二导电层包括第十一导电部，所述第十一导电部在所述衬底基板上的正投影与所述第十导电部在所述衬底基板上的正投影至少部分重合，所述第十一导电部用于形成所述第一电容的第二电极；
    第三导电层，位于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括：第一连接部，所述第一连接部分别通过过孔连接所述第十一有源部和所述第十一导电部。
  21. 根据权利要求20所述的显示面板，其中，
    所述有源层还包括：
    第十二有源部，连接于所述第八有源部远离所述第十一有源部的一端；
    第十三有源部，连接于所述第三有源部远离所述第十一有源部的一端；
    所述第三导电层还包括：
    参考电压线，在所述衬底基板上的正投影沿所述第一方向延伸，所述参考电压线通过过孔连接所述第十三有源部；
    所述显示面板还包括：
    第四导电层，位于所述第三导电层背离所述衬底基板的一侧，所述第四导电层包括所述电源线，所述电源线在所述衬底基板上的正投影沿第二方向延伸，所述第一方向和第二方向相交，所述电源线通过过孔连接所述第十二有源部。
  22. 根据权利要求21所述的显示面板，其中，所述像素驱动电路还包括第二晶 体管、第四晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极，栅极连接第一栅线，所述第四晶体管的第一极连接数据线，第二极连接所述驱动晶体管的第一极，栅极连接所述第一栅线；
    所述像素驱动电路为多个，多个所述像素驱动电路包括在所述第一方向上间隔分布的第一像素驱动电路和第二像素驱动电路；
    所述第一导电层还包括：
    第四导电部，所述第四导电部的部分结构用于形成所述第一像素驱动电路中第二晶体管的栅极，所述第四导电部的另外部分结构用于形成所述第二像素驱动电路中第四晶体管的栅极；
    所述第四导电部为多个，多个所述第四导电部在所述衬底基板上的正投影在所述第一方向上间隔分布；
    所述第三导电层还包括：
    所述第一栅线，所述第一栅线在所述衬底基板上的正投影沿所述第一方向延伸，所述第一栅线分别通过过孔连接在所述第一方向上间隔分布的多个所述第四导电部；
    其中，所述第三导电层的方块电阻小于所述第一导电层的方块电阻。
  23. 根据权利要求21所述的显示面板，其中，所述像素驱动电路还包括第四晶体管，所述第四晶体管的第一极连接数据线，第二极连接所述驱动晶体管的第一极；
    所述有源层还包括：
    第十四有源部，所述第十四有源部连接所述第十导电部；
    所述第二导电层还包括：
    第十二导电部，连接于所述第十一导电部，所述第十二导电部在所述衬底基板上的正投影沿所述第二方向延伸，且所述第十二导电部在所述衬底基板上的正投影至少部分位于所述第十四有源部在所述衬底基板上的正投影和所述数据线在所述衬底基板上的正投影之间。
  24. 根据权利要求23所述的显示面板，其中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极，所述像素驱动电路为多个，多个所述像素驱动电路包括在所述第一方向上间隔分布的第一像素驱动电路和第二像素驱动电路；
    所述第一导电层还包括：
    第四导电部，所述第四导电部的部分结构用于形成所述第一像素驱动电路中第二晶体管的栅极，所述第四导电部的另外部分结构用于形成所述第二像素驱动电路中第四晶体管的栅极；
    所述第四导电部为多个，多个所述第四导电部在所述衬底基板上的正投影在所述第一方向上间隔分布；
    所述第十二导电部在所述衬底基板上的正投影位于在所述第一方向上相邻的两 个所述第四导电部在所述衬底基板上的正投影之间。
  25. 根据权利要求21所述的显示面板，其中，
    所述有源层还包括：
    第十四有源部，所述第十四有源部连接所述第十导电部；
    所述电源线在所述衬底基板上的正投影与所述第十四有源部在所述衬底基板上的正投影至少部分重合。
  26. 根据权利要求21所述的显示面板，其中，
    所述有源层还包括：
    第十四有源部；
    所述第三导电层还包括：
    第二连接部，所述第二连接部分别通过过孔连接所述第十导电部和所述第十四有源部，所述电源线在所述衬底基板上的正投影与所述第二连接部在所述衬底基板上的正投影至少部分重合。
  27. 根据权利要求21所述的显示面板，其中，所述显示面板还包括发光单元，所述像素驱动电路连接所述发光单元的第一电极，所述像素驱动电路还包括第一晶体管、第七晶体管，所述第一晶体管的第一极连接第一初始信号线，第二极连接所述驱动晶体管的栅极，所述第七晶体管的第一极连接第二初始信号线，第二极连接所述发光单元的第一电极；
    所述有源层还包括：
    第一有源部，用于形成所述第一晶体管的沟道区；
    第七有源部，用于形成所述第七晶体管的沟道区；
    第一初始信号线，连接于所述第一有源部远离所述第十有源部的一端；
    第二初始信号线，连接于所述第七有源部远离所述第十有源部的一端。
  28. 根据权利要求21所述的显示面板，其中，所述像素驱动电路还包括第一晶体管，所述第一晶体管的第一极连接第一初始信号线，第二极连接所述驱动晶体管的栅极，栅极连接复位线；
    所述第一导电层还包括：
    多个第一导电部，多个所述第一导电部在所述衬底基板上的正投影在所述第一方向上间隔分布，所述第一导电部的部分结构用于形成所述第一晶体管的栅极；
    所述第三导电层还包括：
    所述复位线，在所述衬底基板上的正投影沿所述第一方向延伸，所述复位线分别通过过孔连接在所述第一方向上分布的多个所述第一导电部；
    所述第三导电层的方块电阻小于所述第一导电层的方块电阻。
  29. 根据权利要求21所述的显示面板，其中，所述像素驱动电路还包括第四晶体管、第九晶体管，所述第四晶体管的第一极连接数据线，第二极连接所述驱动晶体 管的第一极，栅极连接第一栅线，所述第九晶体管的第一极连接初始信号线，第二极连接所述驱动晶体管的栅极，栅极连接所述第一栅线；
    所述第一导电层还包括：
    多个第九导电部，多个所述第九导电部在所述衬底基板上的正投影在所述第一方向上间隔分布，所述第九导电部的部分结构用于形成所述第四晶体管的栅极，所述第九导电部的另外部分结构用于形成同一像素驱动电路中所述第九晶体管的栅极；
    所述第三导电层还包括：
    所述第一栅线，在所述衬底基板上的正投影沿所述第一方向延伸，所述第一栅线分别通过过孔连接在所述第一方向上分布的多个所述第九导电部；
    所述第三导电层的方块电阻小于所述第一导电层的方块电阻。
  30. 根据权利要求29所述的显示面板，其中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极连接所述驱动晶体的栅极，第二极连接所述驱动晶体管的第二极，栅极连接第二栅线；
    所述第一导电层还包括：
    多个第二导电部，多个所述第二导电部在所述衬底基板上的正投影沿所述第一方向间隔分布，所述第二导电部用于形成所述第二晶体管的栅极；
    所述第三导电层还包括：
    所述第二栅线，在所述衬底基板上的正投影沿所述第一方向延伸，所述第二栅线分别通过过孔连接在所述第一方向上分布的多个所述第二导电部。
  31. 根据权利要求29所述的显示面板，其中，所述像素驱动电路还包括第二电容，所述第二电容的第一电极连接所述第五晶体管的第二极，所述第二电容的第二电极连接所述驱动晶体管的第一极；
    所述有源层还包括：
    第十六有源部，连接于所述第五有源部远离所述第十一有源部的一端，所述第十六有源部用于形成所述第二电容的第二电极；
    所述第二导电层还包括：
    第十四导电部，连接于所述第十一导电部，所述第十四导电部在所述衬底基板上的正投影与所述第十六有源部在所述衬底基板上的正投影至少部分重合，所述第十四导电部用于形成所述第二电容的第一电极。
  32. 根据权利要求20所述的显示面板，其中，所述有源层还包括：
    第十二有源部，连接于所述第八有源部远离所述第十一有源部的一端；
    第十三有源部，连接于所述第三有源部远离所述第十一有源部的一端；
    所述第三导电层还包括：
    电源线，在所述衬底基板上的正投影沿第二方向延伸，所述第二方向与所述第一方向相交，所述电源线通过过孔连接所述第十二有源部；
    所述显示面板还包括：
    第四导电层，位于所述第三导电层背离所述衬底基板的一侧，所述第四导电层包括所述参考电压线，所述参考电压线通过过孔连接所述第十三有源部。
  33. 根据权利要求32所述的显示面板，其中，所述像素驱动电路还包括第一晶体管，所述第一晶体管的第一极连接初始信号线，第二极连接所述驱动晶体管的栅极；
    所述有源层还包括：
    第一子有源部，用于形成所述第一晶体管的第一沟道区；
    第二子有源部，用于形成所述第一晶体管的第二沟道区；
    第三子有源部，连接于所述第一子有源部和第二子有源部之间；
    所述电源线在所述衬底基板上的正投影与所述第三子有源部在所述衬底基板上的正投影至少部分重合。
  34. 根据权利要求32所述的显示面板，其中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极；
    所述有源层还包括：
    第四子有源部，用于形成所述第二晶体管的沟道区；
    第五子有源部，用于形成所述第二晶体管的沟道区；
    第六子有源部，连接于所述第四子有源部和所述第五子有源部之间；
    所述第四导电层还包括：
    第十七导电部，连接于所述参考电压线；
    所述显示面板包括在所述第一方向上相邻设置的第一像素驱动电路和第二像素驱动电路；
    其中，所述第一像素驱动电路中第十七导电部在所述衬底基板上的正投影与所述第二像素驱动电路中第六子有源部在所述衬底基板上的正投影至少部分重合。
  35. 根据权利要求20所述的显示面板，其中，所述显示面板还包括发光单元，所述像素驱动电路连接所述发光单元的第一电极，所述像素驱动电路还包括第一晶体管、第七晶体管，所述第一晶体管的第一极连接初始信号线，第二极连接所述驱动晶体管的栅极，所述第七晶体管的第一极连接所述初始信号线，第二极连接所述发光单元的第一电极；
    所述像素驱动电路为多个，多个所述像素驱动电路包括在第二方向上相邻的第三像素驱动电路和第四像素驱动电路，所述第一方向和所述第二方向相交；
    所述有源层还可以包括：
    第一有源部，用于形成所述第一晶体管的沟道区；
    第七有源部，用于形成所述第七晶体管的沟道区；
    第十五有源部，所述第十五有源部连接于所述第三像素驱动电路中第一有源部和 所述第四像素驱动电路中第七有源部之间；
    所述显示面板还包括：第四导电层，所述第四导电层包括所述初始信号线，所述初始信号线在所述衬底基板上的正投影沿所述第二方向延伸，所述初始信号线通过过孔连接所述第十五有源部。
  36. 根据权利要求35所述的显示面板，其中，所述有源层还包括：
    第十四有源部，所述第十四有源部连接所述第十导电部；
    所述初始信号线包括第一子初始信号线，所述第一子初始信号线在所述衬底基板上的正投影与所述第十四有源部在所述衬底基板上的正投影至少部分重合。
  37. 根据权利要求35所述的显示面板，其中，所述有源层还包括：
    第十四有源部；
    所述第三导电层还包括：
    第二连接部，所述第二连接部分别通过过孔连接所述第十导电部和所述第十四有源部；
    所述初始信号线包括第一子初始信号线，所述第一子初始信号线在所述衬底基板上的正投影与所述第二连接部在所述衬底基板上的正投影至少部分重合。
  38. 根据权利要求36或37所述的显示面板，其中，所述初始信号线还包括第二子初始信号线，所述第二子初始信号线与所述第一子初始信号线连接，所述第二子初始信号线在所述衬底基板上的正投影与所述电源线在所述衬底基板上的正投影至少部分重合。
  39. 根据权利要求35所述的显示面板，其中，所述像素驱动电路还包括第一晶体管、第四晶体管，所述第一晶体管的第一极连接初始信号线，第二极连接所述驱动晶体管的栅极，栅极连接复位信号线，所述第四晶体管的第一极连接数据线，第二极连接所述驱动晶体管的第一极；
    所述有源层还包括：
    第十四有源部，所述第十四有源部连接所述第十导电部；
    所述第二导电层还包括：
    所述复位信号线，所述复位信号线在所述衬底基板上的正投影沿所述第一方向延伸；
    第十三导电部，连接于所述复位信号线，所述第十三导电部在所述衬底基板上的正投影位于所述第十四有源部在所述衬底基板上的正投影与所述数据线在所述衬底基板上的正投影之间。
  40. 根据权利要求35所述的显示面板，其中，所述第十五有源部为多个，所述有源层还包括：
    有源线，所述有源线在所述衬底基板上的正投影沿所述第一方向延伸，所述有源线连接在所述第一方向上分布的多个所述第十五有源部。
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