WO2024011635A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024011635A1
WO2024011635A1 PCT/CN2022/106113 CN2022106113W WO2024011635A1 WO 2024011635 A1 WO2024011635 A1 WO 2024011635A1 CN 2022106113 W CN2022106113 W CN 2022106113W WO 2024011635 A1 WO2024011635 A1 WO 2024011635A1
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WO
WIPO (PCT)
Prior art keywords
electrode
base substrate
layer
transistor
orthographic projection
Prior art date
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PCT/CN2022/106113
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English (en)
French (fr)
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WO2024011635A9 (zh
Inventor
周宏军
刘练彬
梁恒镇
王吉
宋星亮
牛文骁
邓英俊
王新鹏
严志辉
闵航
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/106113 priority Critical patent/WO2024011635A1/zh
Publication of WO2024011635A1 publication Critical patent/WO2024011635A1/zh
Publication of WO2024011635A9 publication Critical patent/WO2024011635A9/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • the same data line in the display panel needs to provide data signals to sub-pixel units of different colors, so the source driving circuit in the display panel has high power consumption.
  • high-frequency display panels are also prone to color cast problems.
  • a display panel including: a base substrate, an electrode layer, a plurality of pixel driving circuits, and a plurality of data lines.
  • the electrode layer is located on one side of the base substrate.
  • the electrode layer includes a plurality of electrode parts. The electrode parts are used to form the first electrode of the light-emitting unit.
  • the plurality of electrode parts are on the base substrate.
  • the orthographic projection is distributed in an array along a first direction and a second direction, the first direction and the second direction intersect, and a plurality of the electrode portions distributed in the second direction form an electrode column, at least part of the electrodes
  • the columns include electrode portions for forming first electrodes of light-emitting units of different colors; pixel driving circuits are arranged corresponding to the electrode portions, the pixel driving circuits are connected to the corresponding electrode portions, and the pixel driving circuits are used to drive all The light-emitting unit emits light; the orthographic projection of the data line on the base substrate extends along the second direction, the data line is connected to a plurality of the pixel driving circuits, and the data line is used to send light to the pixel drive circuit connected thereto.
  • the pixel driving circuit provides a data signal, and multiple pixel driving circuits connected to the same data line are used to drive the light-emitting units of the same color.
  • the plurality of electrode parts include a first electrode part and a second electrode part, and the first electrode part and the second electrode part are respectively used to form first electrodes of light-emitting units of different colors.
  • Electrode; the plurality of electrode rows include: a first electrode row and a second electrode row; the first electrode row includes a plurality of first electrode parts and a plurality of second electrode parts; in the same first electrode row In the electrode row, the orthographic projections of the first electrode part and the second electrode part on the base substrate are alternately distributed along the second direction; the second electrode row includes a plurality of the first electrode parts.
  • the plurality of data lines include: first data line and a second data line, the pixel driving circuit connected to the first data line connects the first electrode portion in the first electrode column and the second electrode column; the second data line connects The pixel driving circuit connects the first electrode column and the second electrode part in the second electrode column.
  • the plurality of electrode parts further includes a third electrode part, and the first electrode part, the second electrode part, and the third electrode part are respectively used to form the third electrode part of the light-emitting unit of different colors.
  • One electrode; the plurality of electrode columns also include: a third electrode column and a fourth electrode column, the first electrode column, the third electrode column, the second electrode column, and the fourth electrode column are on the first side.
  • the third electrode row includes a plurality of third electrode parts, and the orthographic projection of the third electrode part in the same third electrode row on the base substrate is in the second direction distributed at intervals;
  • the fourth electrode row includes a plurality of third electrode parts, and the orthographic projection of the third electrode part in the same fourth electrode row on the base substrate is in the second direction interval distribution.
  • orthographic projections of a plurality of pixel driving circuits on the substrate are distributed in an array along the first direction and a second direction, and the plurality of pixel driving circuits distributed in the second direction are
  • Each of the pixel driving circuits forms a pixel circuit column, and the plurality of pixel circuit columns include a first pixel circuit column and a second pixel circuit column; the pixel driving circuit in the first pixel circuit column is connected to the first electrode.
  • the electrode portion in the column; the pixel driving circuit in the second pixel circuit column is connected to the electrode portion in the second electrode column; the first data line is connected to the first electrode column and the second electrode column.
  • the second data line connects the pixel driving circuit connected to the first electrode part in the first electrode column and the pixel driving circuit connected to the second electrode part in the second electrode column.
  • orthographic projections of a plurality of pixel driving circuits on the substrate are distributed in an array along the first direction and the second direction, and the orthogonal projections of the plurality of pixel driving circuits distributed in the second direction are
  • a plurality of the pixel driving circuits form a pixel circuit column, and the pixel circuit column includes a first pixel circuit column and a second pixel circuit column; the first data line connects the pixel driving circuits in the first pixel circuit column, The second data line is connected to the pixel driving circuit in the second pixel circuit column; the pixel driving circuit in the first pixel circuit column is connected to the first electrode part in the first electrode column and the second electrode column. ; The pixel driving circuit in the second pixel circuit column is connected to the second electrode portion in the first electrode column and the second electrode column.
  • the display panel further includes: a first bridge part and a second bridge part.
  • the first bridge part is connected to the pixel driving circuit in the first pixel circuit column and the third bridge part. between the first electrode parts in the two electrode columns; the second bridge part is connected between the pixel driving circuit in the second pixel circuit column and the second electrode part in the first electrode column.
  • the display panel further includes: a first signal line and a second signal line, and the orthographic projection of the first signal line on the substrate extends along the first direction; Orthographic projections of two signal lines on the base substrate extend along the first direction; wherein the first signal line and the second signal line are used to provide stable voltage signals; the first bridge portion includes a first extending portion, the second bridging portion including a second extending portion, an orthographic projection of the first extending portion on the substrate, and an orthographic projection of the second extending portion on the substrate.
  • both extend along the first direction; the orthographic projection of the first extension portion on the substrate substrate at least partially overlaps the orthographic projection of the first signal line on the substrate substrate, and/or An orthographic projection of the second extension portion on the base substrate and an orthographic projection of the second signal line on the base substrate at least partially overlap.
  • the pixel driving circuit includes a driving transistor, a first transistor, and a seventh transistor.
  • the first electrode of the first transistor is connected to the first initial signal line, and the third terminal of the first transistor is connected to the first initial signal line.
  • the second electrode is connected to the gate electrode of the driving transistor, the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode of the seventh transistor is connected to the second electrode of the driving transistor; the first electrode The initial signal line forms the first signal line, and the second initial signal line forms the second signal line; or the first initial signal line forms the second signal line, and the second initial signal line The first signal line is formed.
  • the pixel driving circuit includes a driving transistor and a first transistor, the first electrode of the first transistor is connected to the first initial signal line, and the second electrode of the first transistor is connected to the The gate electrode of the driving transistor; the two adjacent first initial signal lines form the first signal line and the second signal line respectively.
  • the display panel further includes: a third signal line, an orthographic projection of the third signal line on the base substrate extends along the second direction, and the third signal line extends along the second direction.
  • the second bridge part also includes a third extension part, the orthographic projection of the third extension part on the substrate extends along the second direction, and the An orthographic projection of the third extension portion on the base substrate and an orthographic projection of the third signal line on the base substrate at least partially overlap.
  • the display panel further includes: a fourth signal line, an orthographic projection of the fourth signal line on the base substrate extends along the second direction, and the third signal line extends along the second direction.
  • Four signal lines are used to provide stable voltage signals;
  • the first bridge part also includes a sixth extension part, the orthographic projection of the sixth extension part on the substrate extends along the second direction, and the An orthographic projection of the sixth extension portion on the base substrate and an orthographic projection of the fourth signal line on the base substrate at least partially overlap.
  • the pixel driving circuit includes a driving transistor and a second transistor.
  • the first electrode of the second transistor is connected to the gate of the driving transistor, and the second electrode of the second transistor is connected to the gate of the driving transistor.
  • the display panel also includes: a first active layer, the first active layer is located between the substrate substrate and the electrode layer, the first active layer includes a second active part, the second active part is used to form a channel region of the second transistor; the second bridge part includes a second extension part, a third extension part, and is connected to the second extension part.
  • a seventh extension portion between the second extension portion and a third extension portion, an orthographic projection of the second extension portion on the base substrate extends along the first direction, and the third extension portion is on the base substrate
  • the orthographic projection on the base substrate extends along the second direction, and the orthographic projection of the seventh extension portion on the base substrate and the orthographic projection of the second active portion on the base substrate at least partially overlap.
  • the display panel further includes: a third bridge part and a fourth bridge part, the third bridge part is connected to the pixel driving circuit in the first pixel circuit column and the third bridge part. between the first electrode parts in an electrode column; the fourth bridge part is connected between the pixel driving circuit in the second pixel circuit column and the second electrode part in the second electrode column.
  • the first bridge portion is connected between pixel driving circuits and electrode portions located in the same row
  • the second bridge portion is connected between pixel driving circuits and electrode portions located in the same row
  • the third bridge portion is connected between the pixel driving circuits and the electrode portions located in the same number of rows and columns
  • the fourth bridge portion is connected between the pixel driving circuits and the electrode portions located in the same number of rows and columns.
  • the parasitic capacitance formed by the first bridge part and other structures is C1
  • the parasitic capacitance formed by the second bridge part and other structures is C2
  • the display panel further includes: a plurality of third signal lines, orthogonal projections of the third signal lines on the base substrate extending along the second direction and along the second direction. Distributed at intervals in one direction, and the third signal line is used to provide a stable voltage signal; the third bridge portion includes a fourth extension portion, the fourth bridge portion includes a fifth extension portion, and the fourth extension portion is at The orthographic projection on the base substrate and the orthographic projection of the fifth extension part on the base substrate both extend along the second direction; the orthographic projection of the fourth extension part on the base substrate The projection and the orthographic projection of the third signal line on the base substrate at least partially overlap, and the orthographic projection of the fifth extension portion on the base substrate and the other third signal line are on the base substrate. The orthographic projections on the substrate at least partially overlap.
  • the pixel driving circuit includes a driving transistor, and the display panel further includes: a first power line connected to a first pole of the driving transistor, and the first power line lines form the third signal line.
  • the display panel further includes: a first source and drain layer and a second source and drain layer, the first source and drain layer being located between the base substrate and the electrode layer; a second source and drain layer;
  • the source-drain layer is located between the first source-drain layer and the electrode layer; the first bridge portion, the second bridge portion, the third bridge portion, and the fourth bridge portion are located in the electrode layer; or, the The conductive layer where the first bridge part, the second bridge part, the third bridge part and the fourth bridge part are located is between the second source and drain layer and the electrode layer; or, the first bridge part, the conductive layer
  • the conductive layer where the second bridge portion, the third bridge portion and the fourth bridge portion are located is located between the second source and drain layer and the first source and drain layer.
  • the display panel further includes: a source driving circuit, the source driving circuit includes: a data latch and a data reset circuit, and the data latch is used to receive a plurality of original data signal, the original data signal includes a plurality of original data in series, and at least part of the original data in the original data signal is used to drive light-emitting units of different colors; the data reset circuit is used to generate a reset according to the original data signal.
  • the reset data signal includes multiple reset data in series, and the reset data in the same reset data signal is used to drive the light-emitting unit of the same color.
  • the pixel driving circuit includes a driving transistor and a second transistor.
  • the first electrode of the second transistor is connected to the gate of the driving transistor, and the second electrode of the second transistor is connected to the gate of the driving transistor.
  • the display panel also includes: a first active layer, the first active layer is located between the substrate substrate and the electrode layer, the first active layer includes a second active part, the second active part is used to form a channel region of the second transistor;
  • the electrode layer also includes: an additional part, the additional part is connected to the electrode part, the additional part is The orthographic projection on the base substrate and the orthographic projection of the second active portion on the base substrate at least partially overlap.
  • the pixel driving circuit includes a driving transistor and a first transistor.
  • the first electrode of the first transistor is connected to the first initial signal line, and the second electrode is connected to the gate of the driving transistor.
  • the display panel further includes: a second gate layer, a first source and drain layer, the second gate layer is located between the base substrate and the electrode layer, the second gate layer includes the third An initial signal line, the orthographic projection of the first initial signal line on the base substrate extends along the first direction; the first source and drain layer is located between the second gate layer and the electrode layer , the first source and drain layer includes a first initial connection line, the orthographic projection of the first initial connection line on the base substrate extends along the second direction, and the first initial connection line passes through a via hole The first initial signal line intersecting its orthographic projection on the base substrate is connected, and the first initial connection line is connected to the first pole of the first transistor.
  • the display panel includes a plurality of repeating units distributed in an array along the first direction and the second direction; each of the repeating units includes two repeating units distributed along the first direction.
  • the pixel driving circuit two pixel driving circuits in the same repeating unit are arranged in mirror symmetry; the pixel driving circuit includes a driving transistor and a capacitor, the first electrode of the capacitor is connected to the gate of the driving transistor, The second electrode of the capacitor is connected to the first power line; the display panel also includes: a second gate layer and a second source and drain layer, the second gate layer is located between the base substrate and the electrode layer , the second gate layer includes a third conductive part, the third conductive part is used to form the second electrode of the capacitor; the second source and drain layer is located between the second gate layer and the electrode layer.
  • the second source and drain layer includes the first power line, two adjacent first power lines in the same repeating unit are connected; and two adjacent repeating units in the first direction Two adjacent third conductive parts are connected.
  • the display panel further includes: a first source and drain layer, the first source and drain layer is located between the second gate electrode layer and the second source and drain layer, and the first source and drain layer is located between the second gate electrode layer and the second source and drain layer.
  • a source and drain layer includes a power connection line, the orthographic projection of the power connection line on the base substrate extends along the first direction, and the power connection line is connected to the third conductive part and the third conductive part through via holes respectively.
  • a power cord is a power cord.
  • the first power line includes: a first power line segment, a second power line segment, and a third power line segment, and the second power line segment is connected to the first power line segment and the between the third power line segments; the orthographic projection of the second power line segment on the base substrate in the first direction is larger than the orthographic projection of the first power line segment on the base substrate in the first direction.
  • the size of the orthographic projection of the second power line segment on the base substrate in the first direction is larger than the orthographic projection of the third power line segment on the base substrate in the first direction. Size; In the same repeating unit, two adjacent second power line segments are connected, and the orthographic projection of the connected second power line segment on the substrate covers its orthographic projection on the substrate. Orthographic projections of the intersecting electrode portions on the base substrate.
  • the first power line includes: a first power line segment, a second power line segment, and a third power line segment, and the second power line segment is connected to the first power line segment and the between the third power line segments; the orthographic projection of the second power line segment on the base substrate in the first direction is larger than the orthographic projection of the first power line segment on the base substrate in the first direction.
  • the size of the orthographic projection of the second power line segment on the base substrate in the first direction is larger than the orthographic projection of the third power line segment on the base substrate in the first direction.
  • a display device which includes the above-mentioned display panel.
  • Figure 1 is a schematic structural diagram of a display panel in the related art
  • Figure 2 shows the timing diagram of different data lines when the display panel displays a pure red picture
  • Figure 3 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • Figure 4 is a timing diagram of signals on data lines at different locations in the fan-out area of the display panel
  • Figure 5 is a schematic structural diagram of an exemplary embodiment of a display panel of the present disclosure.
  • Figure 6 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • Figure 7 is a distribution diagram of the pixel driving circuit in Figure 6;
  • Figure 8 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • Figure 9 is a distribution diagram of the pixel driving circuit in Figure 8.
  • Figure 10 is a schematic circuit structure diagram of a pixel driving circuit in an exemplary embodiment of the display panel of the present disclosure
  • Figure 11 is a timing diagram of each node signal in a driving method of the pixel driving circuit shown in Figure 10;
  • Figure 12 is a structural layout of an exemplary embodiment of a display panel of the present disclosure.
  • Figure 13 shows the structural layout of the first active layer in Figure 12
  • Figure 14 is a structural layout of the first gate layer in Figure 12;
  • Figure 15 is a structural layout of the second gate layer in Figure 12;
  • Figure 16 is a structural layout of the first source and drain layer in Figure 12;
  • Figure 17 is a structural layout of the second source and drain layer in Figure 12;
  • Figure 18 is the structural layout of the bridge layer in Figure 12;
  • Figure 19 is the structural layout of the electrode layer in Figure 12;
  • Figure 20 is a structural layout of the first active layer and the first gate layer in Figure 12;
  • Figure 21 is a structural layout of the first active layer, the first gate layer, and the second gate layer in Figure 12;
  • Figure 22 is a structural layout of the first active layer, the first gate layer, the second gate layer, and the first source and drain layer in Figure 12;
  • Figure 23 is a structural layout of the first active layer, the first gate layer, the second gate layer, the first source and drain layer, and the second source and drain layer in Figure 12;
  • Figure 24 is a structural layout of the first active layer, the first gate layer, the second gate layer, the first source and drain layer, the second source and drain layer, and the bridge layer in Figure 12;
  • Figure 25 is a partial cross-sectional view of the display panel shown in Figure 12 taken along the dotted line AA;
  • Figure 26 is a structural layout of another exemplary embodiment of a display panel of the present disclosure.
  • Figure 27 is a structural layout of the first active layer, the first gate layer, the second gate layer, the first source and drain layer, the second source and drain layer, and the bridge layer in Figure 26;
  • Figure 28 is the structural layout of the bridge layer in Figure 26;
  • Figure 29 is a structural layout of another exemplary embodiment of a display panel of the present disclosure.
  • Figure 30 is a structural layout of the first active layer, the first gate layer, the second gate layer, the first source and drain layer, the second source and drain layer, and the bridge layer in Figure 29;
  • Figure 31 is the structural layout of the bridge layer in Figure 29;
  • Figure 32 is a structural layout of an exemplary embodiment of a display panel of the present disclosure.
  • Figure 33 shows the structural layout of the first active layer in Figure 32
  • Figure 34 is a structural layout of the first gate layer in Figure 32;
  • Figure 35 is a structural layout of the second gate layer in Figure 32;
  • Figure 36 is a structural layout of the first source and drain layer in Figure 32;
  • Figure 37 is a structural layout of the second source and drain layer in Figure 32;
  • Figure 38 is the structural layout of the bridge layer in Figure 32;
  • Figure 39 is a structural layout of the electrode layer in Figure 32;
  • Figure 40 is a structural layout of the first active layer and the first gate layer in Figure 32;
  • Figure 41 is a structural layout of the first active layer, the first gate layer, and the second gate layer in Figure 32;
  • Figure 42 is a structural layout of the first active layer, the first gate layer, the second gate layer, and the first source and drain layer in Figure 32;
  • Figure 43 is a structural layout of the first active layer, the first gate layer, the second gate layer, the first source and drain layer, and the second source and drain layer in Figure 32;
  • Figure 44 is a structural layout of the first active layer, the first gate layer, the second gate layer, the first source and drain layer, the second source and drain layer, and the bridge layer in Figure 32;
  • Figure 45 is a partial cross-sectional view of the display panel shown in Figure 32 taken along the dotted line BB;
  • Figure 46 is a structural layout of another exemplary embodiment of a display panel of the present disclosure.
  • Figure 47 is the structural layout of the electrode layer in Figure 46;
  • Figure 48 is a schematic circuit structure diagram of the pixel driving circuit in the display panel of the present disclosure.
  • Figure 49 is a timing diagram of each node in a driving method of the pixel driving circuit in Figure 48;
  • Figure 50 is a structural layout of a display panel in an exemplary embodiment of the present disclosure.
  • Figure 51 is the structural layout of the occlusion layer in Figure 50;
  • Figure 52 is a structural layout of the first active layer in Figure 50;
  • Figure 53 is a structural layout of the first gate layer in Figure 50;
  • Figure 54 is a structural layout of the second gate layer in Figure 50;
  • Figure 55 is a structural layout of the second active layer in Figure 50;
  • Figure 56 is a structural layout of the third gate layer in Figure 50;
  • Figure 57 is a structural layout of the first source and drain layer in Figure 50;
  • Figure 58 is a structural layout of the second source and drain layer in Figure 50;
  • Figure 59 is a structural layout of the electrode layer in Figure 50;
  • Figure 60 is a structural layout of the occlusion layer and the first active layer in Figure 50;
  • Figure 61 is a structural layout of the shielding layer, the first active layer, and the first gate layer in Figure 50;
  • Figure 62 is a structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in Figure 50;
  • Figure 63 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in Figure 50;
  • Figure 64 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer and the third gate layer in Figure 50;
  • Figure 65 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source and drain layer in Figure 50;
  • Figure 66 shows the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source and drain layer, and the second source and drain layer in Figure 50 structural layout;
  • Figure 67 is a partial cross-sectional view of the display panel shown in Figure 50 taken along the dotted line CC;
  • Figure 68 is a structural layout of another exemplary embodiment of a display panel of the present disclosure.
  • Figure 69 is a structural layout of the first active layer, the first gate layer, the second gate layer, the first source and drain layer, the second source and drain layer, and the bridge layer in Figure 68;
  • Figure 70 is the structural layout of the bridge layer in Figure 68;
  • FIG. 71 is a schematic structural diagram of a source driving circuit in a display panel of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments. To those skilled in the art.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the display panel may include a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B, a data line Da, a source driving circuit D IC, Main flexible circuit board MFPC, connector Cnet.
  • Each sub-pixel may include a light-emitting unit and a pixel driving circuit for driving the light-emitting unit, and the light-emitting unit may be an OLED light-emitting unit.
  • the data line Da connects multiple sub-pixels located in the same column, and the data line Da is used to provide data signals to the sub-pixels connected thereto.
  • the source driver circuit D IC is used to provide data signals to each data line.
  • the source driver circuit D IC can be connected to other driver chips through the main flexible circuit board MFPC and connector Cnet. As shown in FIG. 1 , in the display panel provided by this exemplary embodiment, the same data line needs to provide data signals to the red sub-pixel R and the blue sub-pixel B respectively.
  • the luminous efficiency of the luminescent material corresponding to the red light-emitting unit is much higher than that of the luminescent material corresponding to the blue light-emitting unit.
  • the data signal required by the blue sub-pixel and the data signal required by the red sub-pixel are different in size, that is, the data signal voltage range corresponding to the blue sub-pixel is greater than the data signal voltage range corresponding to the red sub-pixel.
  • the driving transistor in the pixel driving circuit is a P-type tube
  • the voltage of the data signal required by the blue sub-pixel is smaller than the voltage of the data signal required by the red sub-pixel. Therefore, when the display panel scans row by row in the column direction, the voltage on the data line Da needs to jump between the data signal voltage required by the red sub-pixel and the data signal voltage required by the blue sub-pixel.
  • the voltage fluctuation on the data line Da is greater.
  • FIG 2 it is the timing diagram of different data lines when the display panel displays a pure red picture.
  • JI represents the timing diagram of the odd-numbered column data lines in Figure 1
  • OU represents the timing diagram of the even-numbered column data lines in Figure 1.
  • a certain odd-numbered column data line provides data signals to blue sub-pixels
  • an even-numbered column data line provides data signals to green sub-pixels
  • this data line provides data signals to red sub-pixels
  • the even column data lines provide data signals to the green subpixels.
  • the gray level corresponding to the blue sub-pixel and the green sub-pixel is 0; in the second stage t2, the red sub-pixel corresponds to the maximum gray level, and the gray level corresponding to the green sub-pixel is 0. Therefore, when the display panel displays pure red, the voltage on the data line Da fluctuates greatly. In the same way, when the display panel displays pure blue, the voltage fluctuation on the data line Da is also large.
  • FIG. 3 it is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • the display panel may include a fan-out area Fanout, and the data line Da is fan-out in the fan-out area Fanout and is connected to the source driving circuit D IC.
  • the length of the data lines on both sides of the fan-out area is longer, and the length of the data line in the middle of the fan-out area is shorter. This results in a longer delay of the data signals on the data lines on both sides of the fan-out area.
  • the data signal delay of the data line in the middle of the outgoing area is small.
  • Figure 4 it is a timing diagram of the signals on the data lines at different locations in the fan-out area of the display panel.
  • Gout represents the timing diagram of data writing to the transistor gate in the pixel drive circuit
  • Da1 represents the timing diagram of the signal on the data line on both sides of the fan-out area
  • Da2 represents the timing diagram of the signal on the data line in the middle of the fan-out area.
  • this exemplary embodiment provides a display panel, as shown in FIG. 5 , which is a schematic structural diagram of a display panel according to an exemplary embodiment of the present disclosure.
  • the display panel can also include red sub-pixels R, green sub-pixels G, blue sub-pixels B, data lines, source driving circuit D IC, main flexible circuit board MFPC, and connector Cnet.
  • red sub-pixels R, green sub-pixels G, blue sub-pixels B, and green sub-pixels G are distributed in sequence.
  • the display panel includes a plurality of sub-pixel column groups, and each sub-pixel column group includes sequentially adjacent first sub-pixel column ROW1, second sub-pixel column ROW2, third sub-pixel column ROW3, and fourth sub-pixel column ROW4.
  • the first sub-pixel column ROW1 includes red sub-pixels R and blue sub-pixels B distributed alternately in the second direction Y
  • the second sub-pixel column ROW2 includes a plurality of green sub-pixels distributed in the second direction Y.
  • G the third sub-pixel column ROW3 includes blue sub-pixels B and red sub-pixels R distributed alternately in the second direction Y
  • the fourth sub-pixel column ROW4 includes a plurality of green sub-pixels distributed in the second direction Y G.
  • the first direction X may intersect the second direction Y.
  • the first direction X may be a row direction and the second direction may be a column direction.
  • the data lines in the display panel shown in Figure 5 include a first data line Da1, a second data line Da2, a third data line Da3, and a fourth data line Da4, in the same sub-pixel column.
  • the first data lines Da1 alternately connect the red sub-pixels R in the first sub-pixel column ROW1 and the third sub-pixel column ROW3 row by row along the second direction Y
  • the second data lines Da2 alternate row by row along the second direction Y. Connect the blue sub-pixel B in the first sub-pixel column ROW1 and the third sub-pixel column ROW3.
  • the green sub-pixel G in the second sub-pixel column ROW2 is connected to the third data line Da3, and the green sub-pixel G in the fourth sub-pixel column ROW4 is connected to the fourth data line Da4.
  • the first data line Da1 and the second data line Da2 only need to provide a stable voltage signal, and the first data line Da1 and the second data line Da2 no longer need to provide changing signals. Therefore, this display panel can solve the above-mentioned technical problems of high power consumption and color shift of the source driver circuit D IC.
  • the pixel driving circuit and the light-emitting unit in the same sub-pixel are connected.
  • the first data line Da1 and the second data line Da2 may be connected to pixel driving circuits in different sub-pixel columns by winding.
  • the position where the first data line Da1 and the second data line Da2 intersect in orthographic projection on the substrate in the display panel can be transferred through other conductive layers to avoid short circuiting of the first data line Da1 and the second data line Da2. .
  • the first data line Da1 connecting the red sub-pixel R in the first sub-pixel column ROW1 and the third sub-pixel column ROW3 may also have other winding methods; the second data line Da2 connects the blue sub-pixel B in the first sub-pixel column ROW1 and the third sub-pixel column ROW3.
  • Other winding methods are also possible.
  • the first data line Da1 can connect the red sub-pixels R in the first sub-pixel column ROW1 and the third sub-pixel column ROW3
  • the second data line Da2 can connect the red sub-pixels R in the first sub-pixel column ROW1 and the third sub-pixel column ROW3.
  • Blue sub-pixel B can achieve the above technical effects.
  • the pixel arrangement structure in the display panel can also be in other ways. As long as the same column of sub-pixels includes sub-pixels of different colors, the same data line can be connected through the same color sub-pixel column. This method reduces the power consumption of the source driver circuit and improves color shift.
  • the above technical problem can be solved as long as the pixel driving circuits connected to the same data line drive the same color light-emitting unit. Therefore, in other exemplary embodiments, the data line can still connect the pixel driving circuits located in the same column, and at the same time, by changing the light-emitting unit connected to the pixel driving circuit, the pixel driving circuit connected to the same data line can drive the same color light-emitting unit. .
  • Figure 6 is a schematic structural diagram of another exemplary embodiment of the display panel of the present disclosure
  • Figure 7 is a distribution diagram of the pixel driving circuit in Figure 6.
  • the display panel may include a base substrate, a plurality of pixel driving circuits P11, P12, P13...P24, etc. located on the base substrate, and a plurality of electrode portions connected to the pixel driving circuits.
  • the plurality of electrode parts include a first electrode part R, a second electrode part B, and a third electrode part G.
  • the first electrode part R can be used to form the first electrode of the red light-emitting unit;
  • the two electrode parts B can be used to form the first electrode of the blue light-emitting unit;
  • the third electrode part G can be used to form the first electrode of the green light-emitting unit.
  • a plurality of pixel driving circuits are arranged in an array along the first direction X and the second direction Y, and the same column of pixel driving circuits can be connected to the same data line. In the first direction X, the first electrode part R, the third electrode part G, the second electrode part B, and the third electrode part G are distributed in sequence.
  • the plurality of electrode parts may form a plurality of electrode columns, each electrode column includes a plurality of electrode parts, and the orthographic projections of the plurality of electrode parts in the same electrode column on the substrate are spaced apart along the second direction Y.
  • the plurality of electrode rows may include a first electrode row ROW1, a second electrode row ROW2, a third electrode row ROW3, and a fourth electrode row ROW4. Orthographic projections of the first electrode row ROW1, the third electrode row ROW3, the second electrode row ROW2, and the fourth electrode row ROW4 on the substrate may be alternately distributed in the first direction X.
  • the first electrode row ROW1 includes first electrode parts R and second electrode parts B distributed alternately in the second direction Y;
  • the third electrode row ROW3 includes a plurality of third electrode parts distributed in the second direction Y.
  • G the second electrode row ROW2 includes second electrode parts B and first electrode parts R distributed alternately in the second direction Y;
  • the fourth electrode row ROW4 includes a plurality of third electrode parts distributed in the second direction Y G.
  • the orthographic projections of a plurality of the pixel driving circuits on the substrate are distributed in an array along the first direction X and the second direction Y, and the plurality of pixel driving circuits are distributed in the second direction Y.
  • a pixel circuit column is formed, including a first pixel circuit column PX1 and a second pixel circuit column Px2.
  • the display panel may further include a plurality of bridge portions Bg, and the plurality of bridge portions Bg include a first bridge portion Bg1 and a second bridge portion Bg2.
  • the first bridge portion Bg1 is connected between the pixel driving circuit in the first pixel circuit column PX1 and the first electrode portion R in the second electrode column ROW2; the second bridge portion Bg2 is connected to the second pixel circuit column between the pixel driving circuit in PX2 and the second electrode part in the first electrode column ROW1.
  • the pixel driving circuit P21 can be connected to the first electrode part R in the second electrode row ROW2 through the first bridge part Bg1, and the pixel driving circuit P23 can be connected to the first electrode row ROW1 through the second bridge part Bg2.
  • the second electrode part B in . Therefore, the display panel can realize that the same data line is used to drive the light-emitting units of the same color.
  • Figure 8 is a schematic structural diagram of another exemplary embodiment of the display panel of the present disclosure
  • Figure 9 is a distribution diagram of the pixel driving circuit in Figure 8.
  • the pixel driving circuit P13 may be connected to the first electrode part R in the first electrode row ROW1 through the bridge part Bg, and the pixel driving circuit P11 may also be connected to the second electrode part B of the second electrode row ROW2 through the bridge part Bg.
  • This setting can also enable pixel driving circuits connected to the same data line to connect to light-emitting units of the same color.
  • the electrode part may be located on the electrode layer, and the bridge part Bg may be located on any conductive layer between the electrode layer and the base substrate.
  • the bridge part Bg may also be located on the electrode layer.
  • the bridge portion Bg can be used to connect pixel driving circuits and electrode portions located in the same row.
  • the pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C.
  • the first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1
  • the second electrode is connected to the node N
  • the gate is connected to the first reset signal terminal Re1
  • the first electrode of the second transistor T2 is connected to the gate of the driving transistor T3.
  • the second electrode is connected to the second electrode of the driving transistor T3; the gate is connected to the first gate driving signal terminal G1; the gate of the driving transistor T3 is connected to the node N; the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, and the second electrode of the fourth transistor T4 is connected to the data signal terminal Da.
  • the first electrode of the fifth transistor T5 is connected to the first power terminal VDD, the second electrode is connected to the first electrode of the drive transistor T3, and the gate electrode is connected to the first gate drive signal terminal G1.
  • the first pole of the sixth transistor T6 is connected to the second pole of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the first pole of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the first pole of the seventh transistor T7 is connected to the second initial signal terminal Vinit2.
  • the diode is connected to the second electrode of the sixth transistor T6, and the gate is connected to the second reset signal terminal Re2.
  • the first electrode of the capacitor C is connected to the gate of the driving transistor T3, and the second electrode of the capacitor C is connected to the first power terminal VDD.
  • the pixel driving circuit can be connected to a light-emitting unit OLED. The pixel driving circuit is used to drive the light-emitting unit OLED to emit light.
  • the first electrode of the light-emitting unit OLED can be connected to the second electrode of the sixth transistor T6.
  • the second electrode of the light-emitting unit OLED can be Connect the second power terminal VSS.
  • the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may all be P-type transistors.
  • FIG. 11 it is a timing diagram of each node signal in a driving method of the pixel driving circuit shown in Figure 10.
  • G1 represents the timing of the G1 signal at the first gate drive signal terminal
  • Re1 represents the timing of the Re1 signal at the first reset signal terminal
  • Re2 represents the timing of the Re2 signal at the second reset signal terminal
  • EM represents the timing of the EM signal at the enable signal terminal
  • Da represents the timing of the Da signal at the data signal end.
  • the driving method of the pixel driving circuit may include a reset phase t1, a data writing phase t2, and a light emitting phase t3.
  • the first reset signal terminal Re1 outputs a low-level signal
  • the first transistor T1 is turned on
  • the first initial signal terminal Vinit1 inputs the first initial signal to the node N.
  • the second reset signal terminal Re2 and the first gate drive signal terminal G1 output low-level signals
  • the fourth transistor T4, the second transistor T2, and the seventh transistor T7 are turned on, and at the same time the data signal terminal Da
  • the data signal is output to write the voltage Vdata+Vth to the node N, where Vdata is the voltage of the data signal, Vth is the threshold voltage of the driving transistor T3, and the second initial signal terminal Vinit2 inputs the second initial signal to the second pole of the sixth transistor T6. Signal.
  • the enable signal terminal EM outputs a low-level signal
  • the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the voltage Vdata+Vth of the node N.
  • ⁇ is the carrier mobility
  • Cox is the gate capacitance per unit area
  • W is the width of the driving transistor channel
  • L is the length of the driving transistor channel
  • Vgs is the gate-source voltage difference of the driving transistor
  • Vth is the driving transistor threshold. Voltage.
  • the pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.
  • This exemplary embodiment also provides another display panel, which may include a base substrate, a first active layer, a first gate layer, a second gate layer, and a first source and drain layer that are stacked in sequence.
  • the second source and drain layer, bridge layer, electrode layer, and an insulating layer are provided between the above structural layers.
  • Figure 12 is a structural layout of an exemplary embodiment of the display panel of the present disclosure.
  • Figure 13 is a structural layout of the first active layer in Figure 12.
  • Figure 14 is a structural layout of the first gate layer in Figure 12.
  • Figure 15 is the structural layout of the second gate layer in Figure 12
  • Figure 16 is the structural layout of the first source and drain layer in Figure 12
  • Figure 17 is the structural layout of the second source and drain layer in Figure 12
  • Figure 18 is the structural layout of the bridge layer in Figure 12
  • Figure 19 is the structural layout of the electrode layer in Figure 12
  • Figure 20 is the structural layout of the first active layer and the first gate layer in Figure 12
  • Figure 21 is the structural layout of the first active layer and the first gate layer in Figure 12
  • Figure 22 shows the first active layer, the first gate layer, the second gate layer, and the first source and drain layer in Figure 12
  • the structural layout of Figure 23 is the structural layout of the first active layer, the first gate layer, the second gate layer, the first source and drain layer, and the second source and drain layer in Figure 12.
  • Figure 24 is the structural layout of the first source and drain layer in Figure 12.
  • the first active layer may include a first active portion 71, a second active portion 72, a third active portion 73, a fourth active portion 74, and a fifth active portion. 75.
  • the sixth active part 76 and the seventh active part 77 are used to form the first active part 71 and the second active part 72 .
  • the first active part 71 is used to form the channel region of the first transistor T1
  • the second active part 72 is used to form the channel region of the second transistor T2
  • the third active part 73 is used to form the driving transistor T3.
  • the fourth active part 74 is used to form the channel region of the fourth transistor T4
  • the fifth active part 75 is used to form the channel region of the fifth transistor T5
  • the sixth active part 76 is used to form the channel region of the fourth transistor T4.
  • the channel region of the sixth transistor T6 and the seventh active portion 77 are used to form the channel region of the seventh transistor T7.
  • the first active part 71 includes a fourth sub-active part 714 and a fifth sub-active part 715
  • the second active part 72 includes a first sub-active part 721 and a second sub-active part 722 .
  • the first active layer may further include a sixth sub-active part 716 connected between the fourth sub-active part 714 and the fifth sub-active part 715, a sixth sub-active part 716 connected between the first sub-active part 721 and the second sub-active part 715.
  • the first active layer may be formed of polysilicon material.
  • the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P. low temperature polysilicon thin film transistor.
  • the first gate layer may include: a first reset signal line Re1 , a second reset signal line Re2 , a first gate line G1 , an enable signal line EM, and a first conductive portion 11 .
  • the first reset signal line Re1 is used to provide the first reset signal terminal in Figure 10
  • the second reset signal line Re2 is used to provide the second reset signal terminal in Figure 10
  • the first gate line G1 is used to provide the second reset signal terminal in Figure 10
  • the enable signal line EM is used to provide the enable signal terminal in FIG. 10 .
  • the orthographic projection of the first reset signal line Re1 on the base substrate may extend along the first direction X and cover the orthographic projection of the first active part 71 on the base substrate, and a partial structure of the first reset signal line Re1 is used to form The gate of the first transistor T1.
  • the orthographic projection of the second reset signal line Re2 on the base substrate may extend along the first direction The gate of the seventh transistor T7.
  • the orthographic projection of the enable signal line EM on the base substrate may extend along the first direction X and cover the orthographic projection of the fifth active part 75 on the base substrate and the orthographic projection of the sixth active part 76 on the base substrate.
  • Projection shows that a part of the structure of the enable signal line EM is used to form the gate electrode of the fifth transistor T5, and another part of the structure of the enable signal line EM is used to form the gate electrode of the sixth transistor T6.
  • the orthographic projection of the first gate line G1 on the base substrate extends along the first direction X and covers the orthographic projection of the second active portion 72 on the base substrate and the orthographic projection of the fourth active portion 74 on the base substrate.
  • part of the structure of the first gate line G1 is used to form the gate electrode of the second transistor T2
  • another part of the structure of the first gate line G1 is used to form the gate electrode of the fourth transistor T4.
  • the orthographic projection of the first conductive part 11 on the base substrate covers the orthographic projection of the third active part 73 on the base substrate, and the first conductive part 11 is used to form the gate of the driving transistor T3.
  • the first conductive part 11 can also be reused as the first electrode of the capacitor C.
  • the orthographic projection of the first conductive part 11 on the base substrate may be located between the orthographic projection of the first gate line G1 on the base substrate and the orthographic projection of the enable signal line EM on the base substrate.
  • the orthographic projection of the first reset signal line Re1 on the base substrate may be located on a side of the orthographic projection of the first gate line G1 on the base substrate away from the orthographic projection of the first conductive part 11 on the base substrate.
  • the orthographic projection of the second reset signal line Re2 on the base substrate may be located on a side away from the orthographic projection of the enable signal line EM on the base substrate and the orthographic projection of the first conductive part 11 on the base substrate.
  • the second reset signal line Re2 in the pixel driving circuit of the previous row can be shared as the first reset signal line Re1 in the pixel driving circuit of this row. This arrangement can reduce the pixel driving time.
  • the display panel can use the first gate layer as a mask to conduct conduction processing on the first active layer, that is, the area of the first active layer covered by the first gate layer can form the channel region of the transistor. A region of the first active layer not covered by the first gate layer forms a conductor structure.
  • the second gate layer may include a first initial signal line Vinit1 , a second initial signal line Vinit2 , a second conductive part 22 , and a third conductive part 23 .
  • the first initial signal line Vinit1 may be used to provide the first initial signal terminal in FIG. 10
  • the second initial signal line Vinit2 may be used to provide the second initial signal terminal in FIG. 10 .
  • Both the orthographic projection of the first initial signal line Vinit1 on the base substrate and the orthographic projection of the second initial signal line Vinit2 on the base substrate can extend along the first direction X.
  • the orthographic projection of the third conductive part 23 on the base substrate may at least partially overlap with the orthographic projection of the first conductive part 11 on the base substrate, and the third conductive part 23 may be used to form the second electrode of the capacitor C, where , a plurality of third conductive parts 23 distributed in the first direction X may be connected in sequence.
  • the orthographic projection of the first initial signal line Vinit1 in the next row of pixel driving circuits on the substrate may be located at the second initial signal line Vinit2 in the current row of pixel driving circuits.
  • this setting can further reduce the amount of interference in the second reset signal line Re2 in the pixel driving circuit of this row. Dimensions in direction.
  • the second conductive part 22 may include a third sub-conductive part 223, and the orthographic projection of the third sub-conductive part 223 on the base substrate at least partially overlaps with the orthographic projection of the third sub-active part 723 on the base substrate,
  • the second conductive part 22 can be connected to a stable voltage source, and the third sub-conductive part 223 can stabilize the voltage of the third sub-active part 723 , thereby improving the voltage variation of the third sub-active part 723 to the second sub-active part 723 .
  • the orthographic projection of the first initial signal line Vinit1 on the base substrate may at least partially overlap with the orthographic projection of the sixth sub-active part 716 in the pixel driving circuit of this row on the base substrate, and the first initial signal line Vinit1 may overlap
  • the sixth sub-active part 716 plays a voltage stabilizing role, thereby improving the problem of leakage to the source and drain of the first transistor T1 due to voltage changes of the sixth sub-active part 716 .
  • the first source and drain layer may include a first power line VDD, a fifth bridge portion 35, a sixth bridge portion 36, a seventh bridge portion 37, an eighth bridge portion 38, and a ninth bridge portion.
  • the first power line VDD may be used to provide the first power terminal in the pixel driving circuit shown in FIG. 10 .
  • the orthographic projection of the first power line VDD on the base substrate may extend along the second direction Y, and the first power line VDD may be connected to the second conductive part 22 through the via hole H to provide a stable voltage source to the second conductive part 22,
  • black squares represent the locations of via holes.
  • a stable voltage source may also be provided to the second conductive part 22 through other signal lines.
  • a stable voltage source may be provided to the second conductive part 22 through the first initial signal line Vinit1 and the second initial signal line Vinit2.
  • the conductive portion 22 provides a stable voltage source.
  • the first power line VDD can also be connected to the third conductive portion 23 through a via hole to connect the second electrode of the capacitor and the first power terminal.
  • the first power line VDD may form a grid structure with the third conductive part 23 connected in the first direction X. This arrangement can reduce the voltage drop caused by the resistance drop of the first power line VDD itself.
  • the first power line VDD may also be connected to the twelfth active part 712 through a via hole to connect the first pole of the fifth transistor T5 and the first power terminal.
  • the fifth bridge portion 35 can be connected to the first conductive portion 11 and the eighth active portion 78 respectively through via holes to connect the gate of the driving transistor T3 and the second electrode of the first transistor T1 and the first electrode of the second transistor T2 .
  • the third conductive part 23 may be provided with an opening 231 , and the orthographic projection of the via hole connected to the fifth bridge part 35 and the first conductive part 11 on the base substrate may be located at the opening 231 on the base substrate. within the orthographic projection on to prevent the via hole from being connected to the third conductive portion 23 .
  • the sixth bridge part 36 may be connected to the ninth active part 79 through a via hole to connect the first pole of the fourth transistor T4.
  • the seventh bridge portion 37 can connect the thirteenth active portion 713 and the second initial signal line Vinit2 through via holes respectively, so as to connect the first pole and the second initial signal terminal of the seventh transistor.
  • the eighth bridge portion 38 can connect the tenth active portion 710 and the first initial signal line Vinit1 through via holes respectively, so as to connect the first pole and the first initial signal terminal of the first transistor T1.
  • the ninth bridge part 39 may be connected to the eleventh active part 711 through a via hole to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.
  • the second conductive part 22 may also include a first sub-conductive part 221.
  • the first sub-conductive part 221 is connected to the third sub-conductive part 223.
  • the first sub-conductive part 221 is on the lining.
  • the orthographic projection on the base substrate may extend along the first direction X and be located between the orthographic projection of the fifth bridge portion 35 on the base substrate and the orthographic projection of the first reset signal line Re1 on the base substrate, that is, The area covered by the orthographic projection of the first sub-conductive portion 221 on the base substrate moves infinitely in the second direction Y, and the area covered by the orthographic projection of the fifth bridge portion 35 on the base substrate moves infinitely in the second direction Y.
  • the first sub-conductive part 221 can shield the noise influence of the first reset signal line Re1 on the fifth bridge part 35, thereby improving the stability of the node N voltage in the pixel driving circuit shown in FIG. 10.
  • the area covered by the orthographic projection of the first sub-conductive portion 221 on the base substrate moving infinitely in the second direction Y can cover the orthographic projection of the fifth bridge portion 35 on the base substrate in the second direction Y. Move the covered area infinitely in direction Y.
  • the second source and drain layer may include: a data line Da, a power connection line 4VDD, and a tenth bridge portion 410.
  • the data line Da is used to provide a data signal terminal in the pixel driving circuit shown in Figure 10.
  • Each column of pixel driving circuits is provided with a data line, and the data line is connected to the first electrode of the fourth transistor in the same column of pixel driving circuits.
  • the orthographic projection of the power connection line 4VDD on the base substrate and the orthographic projection of the data line Da on the base substrate can both extend along the second direction Y.
  • the power connection line 4VDD can be connected to the first power line VDD through the via hole. This dual power line arrangement can further reduce the resistance of the power line itself.
  • the data line Da may be connected to the sixth bridge portion 36 through a via hole to connect the first pole of the fourth transistor T4 and the data signal terminal.
  • the orthographic projection of the first power line VDD on the base substrate may be located between the orthographic projection of the data line Da on the base substrate and the orthographic projection of the fifth bridge portion 35 on the base substrate.
  • the first power line VDD can shield the noise influence of the data line Da in the pixel driving circuit of this column on the fifth bridge portion 35 in the pixel driving circuit of this column.
  • the tenth bridge part 410 may be connected to the ninth bridge part 39 through a via hole to connect the second electrode of the sixth transistor.
  • the second conductive part 22 may also include a second sub-conductive part 222.
  • the second sub-conductive part 222 is connected to a side of the first sub-conductive part 221 away from the third sub-conductive part 223.
  • the orthographic projection of the second sub-conductive part 222 on the base substrate may extend along the second direction Y
  • the orthographic projection of the fifth bridge part 35 on the base substrate and the data line Da may be on the base substrate between the orthographic projection of the second sub-conductive portion 222 on the base substrate and the covered area infinitely moving in the first direction X and the orthographic projection of the fifth bridge portion 35 on the base substrate in the first direction
  • the bridging layer may include a plurality of bridging portions Bg, wherein the plurality of bridging portions include a first bridging portion Bg1 and a second bridging portion Bg2 .
  • the first bridge part Bg1 may be connected to the tenth bridge part 410 in the pixel driving circuit of the first column and second row through a via hole.
  • the second bridge part Bg2 may be connected to the tenth bridge part 410 in the pixel driving circuit of the third column and second row through a via hole.
  • the pixel electrode layer may include a plurality of electrode parts: a first electrode part R, a third electrode part G, and a second electrode part B.
  • Each electrode part may be connected to the bridge part Bg through a via hole to connect to the third electrode part.
  • the first electrode portion R, the third electrode portion G, the second electrode portion B, and the third electrode portion G are sequentially distributed alternately in the first direction X.
  • the plurality of electrode parts form a plurality of electrode rows.
  • the plurality of electrode rows include sequentially adjacent first electrode rows ROW1, third electrode rows ROW3, second electrode rows ROW2, and fourth electrode rows ROW4.
  • the first electrode row ROW1 includes The first electrode portion R and the second electrode portion B are distributed alternately in the second direction Y;
  • the third electrode row ROW3 includes a plurality of third electrode portions G distributed in the second direction Y;
  • the second electrode row ROW2 includes The second electrode parts B and the first electrode parts R are distributed alternately in the second direction Y;
  • the fourth electrode row ROW4 includes a plurality of third electrode parts G distributed in the second direction Y.
  • the minimum distance S1 in the second direction of the orthographic projection of the two third electrode portions G located in adjacent electrode rows of the same electrode column on the base substrate is greater than the first electrode portion R on the base substrate.
  • the dimension S2 of the orthographic projection in the second direction is greater than the dimension S3 of the orthographic projection in the second direction of the second electrode part B on the base substrate.
  • the display panel further includes a pixel definition layer located on a side of the electrode layer facing away from the base substrate, and a pixel opening for forming a light-emitting unit is formed on the pixel definition layer.
  • the orthographic projection of the first electrode part R on the base substrate and the pixel definition layer coincides with the orthographic projection of its corresponding opening on the base substrate, and the third electrode part G is on the orthographic projection of the base substrate and the pixel definition layer.
  • the orthographic projection of the corresponding opening on the base substrate coincides with the orthographic projection of the second electrode portion B on the base substrate and the orthographic projection of the corresponding opening on the base substrate on the pixel definition layer coincides with the orthographic projection of the corresponding opening on the base substrate.
  • the second electrode part B in the first electrode column may be connected to the second bridge part Bg2 through a via hole to connect to the pixel driving circuit in the second row of the third column.
  • the first electrode part R in the second electrode column may be connected to the first bridge part Bg1 through a via hole to connect the pixel driving circuit in the second row of the first column. This setting allows the pixel driving circuit connected to the same data line to drive the light-emitting units of the same color.
  • the first bridge portion Bg1 includes a first extension portion Bg11.
  • the orthographic projection of the first extension portion Bg11 on the base substrate extends along the first direction
  • the orthographic projection of the first initial signal line Vinit1 on the base substrate in the circuit at least partially overlaps.
  • the orthographic projection of the first extension Bg11 on the base substrate can be located in the first initial signal in the adjacent next row of pixel driving circuits.
  • the orthographic projection of line Vinit1 on the base substrate; the second bridge portion Bg2 includes a second extension portion Bg22, and the orthographic projection of the second extension portion Bg22 on the base substrate extends along the first direction
  • the orthographic projection of the second initial signal line Vinit2 on the base substrate in the circuit at least partially overlaps.
  • the orthographic projection of the second extension Bg22 on the base substrate can be located on the second initial signal line Vinit2 in the pixel driving circuit of this row. On the orthographic projection on the base substrate. Since the first initial signal line and the second initial signal line output stable voltage signals, this arrangement can reduce the coupling effect of other AC signals on the bridge part and improve the stability of the voltage on the bridge part. It should be understood that the orthographic projection of the first extension part Bg11 on the base substrate may at least partially overlap with the orthographic projection of any first signal line that outputs a stable voltage signal on the base substrate; the third The orthographic projection of the two extension parts Bg22 on the base substrate may at least partially overlap with the orthographic projection of any second signal line that outputs a stable voltage signal on the base substrate.
  • the first signal line may include the above-mentioned first initial signal line; the second signal line may include the above-mentioned second initial signal line.
  • the electrode layer may further include a plurality of extension parts, and the plurality of extension parts include: a first extension part E1 , a second extension part E2 , and a third extension part E3 .
  • the first extension part E1 and the second extension part E2 are connected to the first electrode part R
  • the third extension part E3 is connected to the second electrode part B.
  • the orthographic projection of the first extension part E1 on the base substrate at least partially overlaps the orthographic projection of the second active part 72 located at the same row and column number on the base substrate.
  • the first addition part E1 can be used to The transistor is shielded from light to reduce the impact of light on the output characteristics of the second transistor; the orthographic projection of the second extension part E2 on the base substrate and the second active part located in the same row number and adjacent columns are on the base substrate The orthographic projections at least partially overlap, and the second extension part E2 is also used to shield the second transistor.
  • the orthographic projection of the third extension part E3 on the substrate at least partially overlaps with the orthographic projection of the second active part located in the same row and adjacent columns on the substrate.
  • the third extension part E3 is also used for The second transistor is shielded from light.
  • the number of rows and columns of each extension part is the same as the number of rows and columns of the electrode part connected thereto, and the number of rows and columns of the second active part is the same as the number of rows and columns of the pixel driving circuit in which it is located.
  • the black squares drawn on the side of the first source and drain layer facing away from the substrate indicate that the first source and drain layer is connected to other levels on the side facing the substrate.
  • Via holes; the black squares drawn on the side of the second source and drain layer facing away from the base substrate indicate the via holes through which the second source and drain layer connects to other levels on the side facing the base substrate; the black squares drawn on the side of the bridge layer facing away from the base substrate.
  • the black square represents the via hole through which the bridge layer connects to other levels on the side facing the base substrate;
  • the black square drawn on the side of the electrode layer facing away from the base substrate represents the via hole through which the electrode layer connects to other levels on the side facing the base substrate.
  • the black square only represents the location of the via hole. Different via holes represented by black squares at different positions can penetrate different insulation layers.
  • FIG. 25 it is a partial cross-sectional view of the display panel shown in FIG. 12 taken along the dotted line AA.
  • the display panel may further include a first insulating layer 91 , a second insulating layer 92 , a dielectric layer 93 , a passivation layer 94 , a first flattening layer 95 , a third insulating layer 96 , and a second flattening layer 97 .
  • Base substrate 90 active layer, first insulating layer 91, first gate layer, second insulating layer 92, second gate layer, dielectric layer 93, first source and drain layer, passivation layer 94, A flat layer 95, a second source and drain layer, a third insulating layer 96, a bridge layer, a second flat layer 97, and an electrode layer can be stacked in sequence.
  • the first insulating layer 91, the second insulating layer 92, and the third insulating layer 96 can be silicon oxide layers
  • the dielectric layer 93 can be a silicon nitride layer
  • the material of the passivation layer 94 can be silicon oxide, silicon nitride, etc.
  • the third The materials of the first flat layer 95 and the second flat layer 97 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), and polyethylene naphthalate (PEN). , silicon-glass bonding structure (SOG) and other materials.
  • the base substrate 90 may include a glass substrate, a barrier layer, and a polyimide layer that are stacked in sequence.
  • the barrier layer may be an inorganic material.
  • the material of the first gate layer and the second gate layer may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or a laminate or other conductive layer.
  • the material of the first source and drain layer and the second source and drain layer may include a metal material, for example, it may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or laminate, etc., or it may be titanium /Aluminum/Titanium laminate and other conductive layers.
  • the bridge layer may be a conductive layer such as an indium tin oxide layer.
  • Figure 26 is a structural layout of another exemplary embodiment of the display panel of the present disclosure.
  • Figure 27 shows the first active layer, the first gate layer, the second gate layer, The structural layout of the first source and drain layer, the second source and drain layer, and the bridge layer.
  • Figure 28 is the structural layout of the bridge layer in Figure 26.
  • the display panel shown in FIG. 26 is different from the display panel shown in FIG. 12 in that: in the display panel shown in FIG. 26 , the second bridge part Bg2 may include a second extension part Bg22 and a third extension part Bg23.
  • the orthographic projection of the portion Bg22 on the substrate extends along the first direction
  • the orthographic projection on the base substrate extends along the second direction Y and at least partially overlaps the orthographic projection of the first power line VDD on the base substrate in the pixel driving circuit of this column.
  • the second extension Bg22 is on the base substrate.
  • the orthographic projection of the first initial signal line Vinit1 on the base substrate may be located on the orthographic projection of the third extension part Bg23 on the base substrate.
  • the orthographic projection of the third extension part Bg23 on the base substrate may be located on the orthographic projection of the first power line VDD on the base substrate. . This setting can also reduce the noise impact of other AC signals on the bridge. It should be understood that the orthographic projection of the third extension part Bg23 on the base substrate may overlap with the orthographic projection of any third signal line outputting a stable voltage signal on the base substrate.
  • the third signal line may include the above-mentioned first power supply line VDD.
  • the third signal line may further include: the equipotential signal line of the second power supply terminal in FIG. An equipotential signal line at the first initial signal end, an equipotential signal line at the second initial signal end, etc.
  • the orthographic projections of the first bridge portion Bg1 and the second bridge portion Bg2 on the base substrate respectively overlap with the orthographic projections of the different first initial signal lines Vinit1 on the base substrate, so that the Settings can be applied to a single initial signal line or to a highly integrated display panel.
  • the display panel with a single initial signal line refers to a display panel in which one row of pixel driving circuits is provided with one initial signal line, that is, the first transistor T1 and the seventh transistor T7 are connected to the same initial signal line.
  • Figure 29 is a structural layout of another exemplary embodiment of the display panel of the present disclosure.
  • Figure 30 shows the first active layer, the first gate layer, the second gate layer, The structural layout of the first source and drain layer, the second source and drain layer, and the bridge layer.
  • Figure 31 is the structural layout of the bridge layer in Figure 29.
  • the display panel shown in FIG. 29 is different from the display panel shown in FIG. 12 in that in the display panel shown in FIG. 29 , the plurality of bridge portions Bg further include a third bridge portion Bg3 and a fourth bridge portion Bg4.
  • the third bridge portion Bg3 can be used to connect the first electrode portion R and the pixel driving circuit located in the same number of rows and columns
  • the fourth bridge portion Bg4 can be used to connect the second electrode portion B and the pixel driving circuit located in the same number of rows and columns.
  • the third bridge part includes a fourth extension part Bg34, and the orthographic projection of the fourth extension part Bg34 on the base substrate may overlap with the orthographic projection of the power connection line 4VDD on the base substrate.
  • the fourth bridge part Bg4 includes a fifth extension part Bg45, and the orthographic projection of the fifth extension part Bg45 on the base substrate may overlap with the orthographic projection of the power connection line 4VDD on the base substrate.
  • This arrangement can compensate the parasitic capacitance of the third bridge part Bg3 through the fourth extension part Bg34, and compensate the parasitic capacitance of the fourth bridge part Bg4 through the fifth extension part Bg45, so that the first bridge part Bg1 and the third bridge part are connected
  • the parasitic capacitance of the part Bg3 is close to or consistent
  • the parasitic capacitance of the second bridge part Bg2 and the fourth bridge part Bg4 is close to or consistent, so as to solve the problem of uneven parasitic capacitance at the equipotential points of different electrode parts, thereby improving the uniformity of the display panel.
  • the parasitic capacitance between the first bridge part Bg1 and other structures is C1
  • the parasitic capacitance between the second bridge part Bg2 and other structures is C2
  • the parasitic capacitance between the third bridge part Bg3 and other structures is C3.
  • the parasitic capacitance between the fourth bridge Bg4 and other structures is C4.
  • N1 can be equal to 70%, 80%, 90%, 95%, 100%, 105%, 110% , 120%, 130%, etc.
  • N2 can be greater than or equal to 70% and less than or equal to 130%, for example, N2 can be equal to 70%, 80%, 90%, 95%, 100%, 105%, 110%, 120%, 130 %wait.
  • This exemplary embodiment also provides another display panel, which may include a base substrate, a first active layer, a first gate layer, a second gate layer, and a first source and drain layer that are stacked in sequence.
  • the second source and drain layer, bridge layer, electrode layer, and an insulating layer are provided between the above structural layers.
  • Figure 32 is a structural layout of an exemplary embodiment of the display panel of the present disclosure.
  • Figure 33 is a structural layout of the first active layer in Figure 32.
  • Figure 34 is a structural layout of the first gate layer in Figure 32.
  • the structural layout of Figure 35 is the structural layout of the second gate layer in Figure 32.
  • Figure 36 is the structural layout of the first source and drain layer in Figure 32.
  • Figure 37 is the structural layout of the second source and drain layer in Figure 32.
  • Figure 38 is the structural layout of the bridge layer in Figure 32
  • Figure 39 is the structural layout of the electrode layer in Figure 32
  • Figure 40 is the structural layout of the first active layer and the first gate layer in Figure 32
  • Figure 41 is the structural layout of the first active layer and the first gate layer in Figure 32
  • Figure 42 shows the first active layer, the first gate layer, the second gate layer, and the first source and drain layer in Figure 32
  • the structural layout of Figure 43 is the structural layout of the first active layer, the first gate layer, the second gate layer, the first source and drain layer, and the second source and drain layer in Figure 32.
  • Figure 44 is the structural layout of the first active layer, the first gate layer, the second gate layer, the first source and drain layer in Figure 32.
  • the first active layer may include a first active portion 71, a second active portion 72, a third active portion 73, a fourth active portion 74, and a fifth active portion. 75.
  • the sixth active part 76 and the seventh active part 77 are used to form the first active part 71 and the second active part 72 .
  • the first active part 71 is used to form the channel region of the first transistor T1
  • the second active part 72 is used to form the channel region of the second transistor T2
  • the third active part 73 is used to form the driving transistor T3.
  • the fourth active part 74 is used to form the channel region of the fourth transistor T4
  • the fifth active part 75 is used to form the channel region of the fifth transistor T5
  • the sixth active part 76 is used to form the channel region of the fourth transistor T4.
  • the channel region of the sixth transistor T6 and the seventh active portion 77 are used to form the channel region of the seventh transistor T7.
  • the first active part 71 includes a fourth sub-active part 714 and a fifth sub-active part 715
  • the second active part 72 includes a first sub-active part 721 and a second sub-active part 722 .
  • the first active layer may further include a sixth sub-active part 716 connected between the fourth sub-active part 714 and the fifth sub-active part 715, a sixth sub-active part 716 connected between the first sub-active part 721 and the second sub-active part 715.
  • the first active layer may be formed of polysilicon material.
  • the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P. low temperature polysilicon thin film transistor.
  • the first gate layer may include: a first reset signal line Re1 , a second reset signal line Re2 , a first gate line G1 , an enable signal line EM, and a first conductive portion 11 .
  • the first reset signal line Re1 is used to provide the first reset signal terminal in Figure 10
  • the second reset signal line Re2 is used to provide the second reset signal terminal in Figure 10
  • the first gate line G1 is used to provide the second reset signal terminal in Figure 10
  • the enable signal line EM is used to provide the enable signal terminal in FIG. 10 .
  • the orthographic projection of the first reset signal line Re1 on the base substrate may extend along the first direction X and cover the orthographic projection of the first active part 71 on the base substrate, and a partial structure of the first reset signal line Re1 is used to form The gate of the first transistor T1.
  • the orthographic projection of the second reset signal line Re2 on the base substrate may extend along the first direction The gate of the seventh transistor T7.
  • the orthographic projection of the enable signal line EM on the base substrate may extend along the first direction X and cover the orthographic projection of the fifth active part 75 on the base substrate and the orthographic projection of the sixth active part 76 on the base substrate.
  • Projection shows that a part of the structure of the enable signal line EM is used to form the gate electrode of the fifth transistor T5, and another part of the structure of the enable signal line EM is used to form the gate electrode of the sixth transistor T6.
  • the orthographic projection of the first gate line G1 on the base substrate extends along the first direction X and covers the orthographic projection of the second active portion 72 on the base substrate and the orthographic projection of the fourth active portion 74 on the base substrate.
  • part of the structure of the first gate line G1 is used to form the gate electrode of the second transistor T2
  • another part of the structure of the first gate line G1 is used to form the gate electrode of the fourth transistor T4.
  • the orthographic projection of the first conductive part 11 on the base substrate covers the orthographic projection of the third active part 73 on the base substrate, and the first conductive part 11 is used to form the gate of the driving transistor T3.
  • the first conductive part 11 can also be reused as the first electrode of the capacitor C.
  • the orthographic projection of the first conductive part 11 on the base substrate may be located between the orthographic projection of the first gate line G1 on the base substrate and the orthographic projection of the enable signal line EM on the base substrate.
  • the orthographic projection of the first reset signal line Re1 on the base substrate may be located on a side of the orthographic projection of the first gate line G1 on the base substrate away from the orthographic projection of the first conductive part 11 on the base substrate.
  • the orthographic projection of the second reset signal line Re2 on the base substrate may be located on a side away from the orthographic projection of the enable signal line EM on the base substrate and the orthographic projection of the first conductive part 11 on the base substrate.
  • the second reset signal line Re2 in the pixel driving circuit of the previous row can be shared as the first reset signal line Re1 in the pixel driving circuit of this row. This arrangement can reduce the pixel driving time.
  • the display panel can use the first gate layer as a mask to conduct conduction processing on the first active layer, that is, the area of the first active layer covered by the first gate layer can form the channel region of the transistor. A region of the first active layer not covered by the first gate layer forms a conductor structure.
  • the second gate layer may include a first initial signal line Vinit1 , a second initial signal line Vinit2 , a second conductive part 22 , and a third conductive part 23 .
  • the first initial signal line Vinit1 may be used to provide the first initial signal terminal in FIG. 10
  • the second initial signal line Vinit2 may be used to provide the second initial signal terminal in FIG. 10 .
  • Both the orthographic projection of the first initial signal line Vinit1 on the base substrate and the orthographic projection of the second initial signal line Vinit2 on the base substrate can extend along the first direction X.
  • the orthographic projection of the third conductive part 23 on the base substrate may at least partially overlap with the orthographic projection of the first conductive part 11 on the base substrate, and the third conductive part 23 may be used to form the second electrode of the capacitor C, wherein , a plurality of third conductive parts 23 distributed in the first direction X may be connected in sequence.
  • the orthographic projection of the first initial signal line Vinit1 in the next row of pixel driving circuits on the substrate may be located at the position of the enable signal line EM in the current row of pixel driving circuits.
  • the second conductive part 22 may include a third sub-conductive part 223, and the orthographic projection of the third sub-conductive part 223 on the base substrate at least partially overlaps with the orthographic projection of the third sub-active part 723 on the base substrate,
  • the second conductive part 22 can be connected to a stable voltage source, and the third sub-conductive part 223 can stabilize the voltage of the third sub-active part 723 , thereby improving the voltage variation of the third sub-active part 723 to the second sub-active part 723 .
  • the orthographic projection of the first initial signal line Vinit1 on the base substrate may at least partially overlap with the orthographic projection of the sixth sub-active part 716 on the base substrate, and the first initial signal line Vinit1 may overlap the sixth sub-active part 716 716 plays a voltage stabilizing role, which can improve the problem of leakage to the source and drain of the first transistor T1 due to the voltage change of the sixth sub-active part 716.
  • the first source and drain layer may include a first power line VDD, a data line Da, a first initial connection line 4Vinit1, a fifth bridge portion 35, a seventh bridge portion 37, and a ninth bridge portion 39.
  • the first power line VDD may be used to provide the first power terminal in the pixel driving circuit shown in FIG. 10 .
  • the orthographic projection of the first power line VDD on the base substrate may extend along the second direction Y, and the first power line VDD may be connected to the second conductive part 22 through a via hole to provide a stable voltage source to the second conductive part 22 . It should be understood that in other exemplary embodiments, a stable voltage source may also be provided to the second conductive part 22 through other signal lines.
  • a stable voltage source may be provided to the second conductive part 22 through the first initial signal line Vinit1 and the second initial signal line Vinit2.
  • the conductive portion 22 provides a stable voltage source.
  • the first power line VDD can also be connected to the third conductive portion 23 through a via hole to connect the second electrode of the capacitor and the first power terminal.
  • the first power line VDD may form a grid structure with the third conductive part 23 connected in the first direction X, thereby reducing the voltage drop caused by the resistance drop of the first power line VDD itself.
  • the first power line VDD may also be connected to the twelfth active part 712 through a via hole to connect the first pole and the second power terminal of the fifth transistor T5.
  • the data line Da is used to provide a data signal terminal in the pixel driving circuit shown in FIG. 10 .
  • Each column of pixel driving circuits is provided with a data line, and the data line is connected to the first electrode of the fourth transistor in the same column of pixel driving circuits.
  • the orthographic projection of the data line Da on the base substrate can extend along the second direction Y.
  • the data line Da can be connected to the ninth active part 79 through a via hole to connect the first electrode of the fourth transistor T4 and the data signal terminal.
  • the orthographic projection of the first initial connection line 4Vinit1 on the base substrate extends along the second direction Y.
  • the first initial connection line 4Vinit1 is connected to the first initial signal line Vinit1 that intersects its orthographic projection on the base substrate through a via hole.
  • the initial connection line 4 Vinit1 and the first initial signal line Vinit1 may form a grid structure, thereby reducing the own resistance of the first initial signal line Vinit1.
  • the first initial connection line 4Vinit1 is also connected to the tenth active part 710 through a via hole to connect the first initial signal terminal and the first pole of the first transistor.
  • the fifth bridge portion 35 can be connected to the first conductive portion 11 and the eighth active portion 78 respectively through via holes to connect the gate of the driving transistor T3 and the second electrode of the first transistor T1 and the first electrode of the second transistor T2 . As shown in FIG.
  • the third conductive part 23 may be provided with an opening 231 , and the orthographic projection of the via hole connected to the fifth bridge part 35 and the first conductive part 11 on the base substrate may be located at the opening 231 on the base substrate. within the orthographic projection on to prevent the via hole from being connected to the third conductive portion 23 .
  • the seventh bridge portion 37 can connect the thirteenth active portion 713 and the second initial signal line Vinit2 through via holes respectively, so as to connect the first pole and the second initial signal terminal of the seventh transistor.
  • the ninth bridge portion 39 may be connected to the eleventh active portion 711 through a via hole to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.
  • the second conductive part 22 may also include a first sub-conductive part 221.
  • the first sub-conductive part 221 is connected to the third sub-conductive part 223.
  • the first sub-conductive part 221 is on the lining.
  • the orthographic projection on the base substrate may extend along the first direction X and be located between the orthographic projection of the fifth bridge portion 35 on the base substrate and the orthographic projection of the first reset signal line Re1 on the base substrate, that is, The area covered by the orthographic projection of the first sub-conductive portion 221 on the base substrate moves infinitely in the second direction Y, and the area covered by the orthographic projection of the fifth bridge portion 35 on the base substrate moves infinitely in the second direction Y.
  • the first sub-conductive part 221 can shield the noise influence of the first reset signal line Re1 on the fifth bridge part 35, thereby improving the stability of the node N voltage in the pixel driving circuit shown in FIG. 10.
  • the area covered by the orthographic projection of the first sub-conductive portion 221 on the base substrate moving infinitely in the second direction Y can cover the orthographic projection of the fifth bridge portion 35 on the base substrate in the second direction Y. Move the covered area infinitely in direction Y.
  • the second conductive part 22 may also include a second sub-conductive part 222.
  • the second sub-conductive part 222 is connected to the side of the first sub-conductive part 221 away from the third sub-conductive part 223.
  • the second sub-conductive part 222 is on the substrate.
  • the orthographic projection on can extend along the second direction Y and be located between the orthographic projection of the fifth bridge portion 35 on the base substrate and the orthographic projection of the data line Da on the base substrate, that is, the second sub-conductive portion
  • the area covered by the orthographic projection of 222 on the substrate and infinitely moving in the first direction X at least partially intersects with the area covered by the orthographic projection of the fifth bridge portion 35 on the substrate and infinitely moved in the first direction X.
  • the second conductive part 222 can shield the noise influence of the data line Da on the fifth bridge part 35 .
  • the orthographic projection of the second initial signal line Vinit2 in the pixel driving circuit of the previous row on the substrate can be located between the orthographic projection of the first reset signal line Re1 on the substrate in the pixel driving circuit of this row and the fifth bridge portion 35 Between the orthographic projections on the base substrate, the second initial signal line Vinit2 can also shield the noise influence of the first reset signal line Re1 on the fifth bridge portion 35 .
  • the second source and drain layer may include: a virtual data line Dmy and a tenth bridge portion 410.
  • the fan-out area of the display panel may be located in the display area, and data bridge lines located at the second source-drain layer may be provided in the fan-out area so that the data lines are fan-out in a local area.
  • the virtual data line Dmy is used to simulate the occlusion state and parasitic capacitance of the data bridge line in the fan-out area so that the entire display area displays uniformly.
  • the tenth bridge part 410 may be connected to the ninth bridge part 39 through a via hole to connect the second electrode of the sixth transistor.
  • the bridging layer may include a plurality of bridging portions Bg, wherein the plurality of bridging portions include a first bridging portion Bg1 and a second bridging portion Bg2.
  • the first bridge part Bg1 may be connected to the tenth bridge part 410 in the pixel driving circuit of the first column and second row through a via hole.
  • the second bridge part Bg2 may be connected to the tenth bridge part 410 in the pixel driving circuit of the third column and second row through a via hole.
  • the first bridge portion Bg1 includes a first extension portion Bg11.
  • the orthographic projection of the first extension portion Bg11 on the base substrate extends along the first direction The orthographic projections on the base substrate at least partially overlap.
  • the orthographic projection of the first extension Bg11 on the base substrate is located on the orthographic projection of the first initial signal line Vinit1 in the adjacent next row of pixel driving circuits on the base substrate.
  • the second bridge portion Bg2 may include a second extension portion Bg22 and a third extension portion Bg23.
  • the orthographic projection of the second extension portion Bg22 on the base substrate extends along the first direction
  • the orthographic projections of the two initial signal lines Vinit2 on the base substrate at least partially overlap.
  • the orthographic projection of the second extension part Bg22 on the base substrate can be located on the second initial signal line Vinit2 in the adjacent upper row of pixel driving circuits.
  • the orthographic projection of the third extension part Bg23 on the base substrate extends along the second direction Y and is at least the same as the orthographic projection of the first power supply line VDD on the base substrate in the pixel driving circuit of this column.
  • the orthographic projection of the third extension part Bg23 on the substrate may be located on the orthographic projection of the first power line VDD on the substrate in the pixel driving circuit of this column. Since the first initial signal line Vinit1, the second initial signal line Vinit2, and the first power line VDD are used to provide a stable voltage source, this arrangement can reduce the coupling effect of the AC signal on the bridge part and improve the stability of the voltage of the bridge part. In addition, this setting can also improve the transmittance of the display panel.
  • the pixel electrode layer may include a plurality of electrode parts: a first electrode part R, a third electrode part G, and a second electrode part B.
  • Each electrode part may be connected to the bridge part Bg through a via hole to connect to the third electrode part.
  • the first electrode portion R, the third electrode portion G, the second electrode portion B, and the third electrode portion G are sequentially distributed alternately in the first direction X.
  • the plurality of electrode parts form a plurality of electrode rows.
  • the plurality of electrode rows include sequentially adjacent first electrode rows ROW1, third electrode rows ROW3, second electrode rows ROW2, and fourth electrode rows ROW4.
  • the first electrode row ROW1 includes The first electrode portion R and the second electrode portion B are distributed alternately in the second direction Y;
  • the third electrode row ROW3 includes a plurality of third electrode portions G distributed in the second direction Y;
  • the second electrode row ROW2 includes The second electrode parts B and the first electrode parts R are distributed alternately in the second direction Y;
  • the fourth electrode row ROW4 includes a plurality of third electrode parts G distributed in the second direction Y.
  • the minimum distance S1 in the second direction of the orthographic projection of the two third electrode portions G located in adjacent electrode rows of the same electrode column on the base substrate is greater than the first electrode portion R on the base substrate.
  • the dimension S2 of the orthographic projection in the second direction is greater than the dimension S3 of the orthographic projection in the second direction of the second electrode part B on the base substrate.
  • the orthographic projection of the first electrode part R on the base substrate coincides with the orthographic projection of its corresponding opening on the base substrate on the pixel definition layer
  • the orthographic projection of the third electrode part G on the base substrate coincides with the pixel definition layer.
  • the orthographic projection of the corresponding opening on the layer on the base substrate coincides with the orthographic projection of the second electrode portion B on the base substrate and the orthographic projection of the corresponding opening on the pixel definition layer on the base substrate.
  • the second electrode part B in the first electrode column may be connected to the second bridge part Bg2 through a via hole to connect to the pixel driving circuit in the second row of the third column.
  • the first electrode part R in the second electrode row of the second electrode column may be connected to the first bridge part Bg1 through a via hole to connect the pixel driving circuit in the first column and second row. That is, this application uses at least part of the bridge portion Bg to connect pixel driving circuits and electrode portions located at different column positions, so that the pixel driving circuits connected to the same data line can drive the same color light-emitting units.
  • the pixel driving circuits and electrode portions connected to the first bridge portion Bg1 may be located in the same row and in different columns, and the pixel driving circuits and electrode portions connected to the second bridge portion Bg2 may be located in the same row and different columns. It should be understood that in other exemplary embodiments, the pixel driving circuit and the electrode portion connected by the bridge portion may be located in different rows and different columns.
  • the electrode layer may further include a fourth extension part E4, which is connected to the third electrode part G.
  • the orthographic projection of the fourth extension part E4 on the base substrate and the second active The orthographic projection of the portion 72 on the base substrate at least partially overlaps, and the fourth additional portion E4 can shield the second transistor to reduce the impact of light on the output characteristics of the second transistor.
  • the black squares drawn on the side of the first source and drain layer facing away from the base substrate indicate that the first source and drain layer is connected to other levels on the side facing the base substrate.
  • Via holes; the black squares drawn on the side of the second source and drain layer facing away from the base substrate indicate the via holes through which the second source and drain layer connects to other levels on the side facing the base substrate; the black squares drawn on the side of the bridge layer facing away from the base substrate
  • the black square represents the via hole through which the bridge layer connects to other levels on the side facing the base substrate;
  • the black square drawn on the side of the electrode layer facing away from the base substrate represents the via hole through which the electrode layer connects to other levels on the side facing the base substrate.
  • the black square only represents the location of the via hole. Different via holes represented by black squares at different positions can penetrate different insulation layers.
  • FIG. 45 it is a partial cross-sectional view of the display panel shown in FIG. 32 taken along the dotted line BB.
  • the display panel may further include a first insulating layer 91 , a second insulating layer 92 , a dielectric layer 93 , a passivation layer 94 , a first flattening layer 95 , a third insulating layer 96 , and a second flattening layer 97 .
  • Base substrate 90 active layer, first insulating layer 91, first gate layer, second insulating layer 92, second gate layer, dielectric layer 93, first source and drain layer, passivation layer 94, A flat layer 95, a second source and drain layer, a third insulating layer 96, a bridge layer, a second flat layer 97, and an electrode layer can be stacked in sequence.
  • the first insulating layer 91, the second insulating layer 92, and the third insulating layer 96 can be silicon oxide layers
  • the dielectric layer 93 can be a silicon nitride layer
  • the material of the passivation layer 94 can be silicon oxide, silicon nitride, etc.
  • the third The materials of the first flat layer 95 and the second flat layer 97 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), and polyethylene naphthalate (PEN). , silicon-glass bonding structure (SOG) and other materials.
  • the base substrate 90 may include a glass substrate, a barrier layer, and a polyimide layer that are stacked in sequence.
  • the barrier layer may be an inorganic material.
  • the material of the first gate layer and the second gate layer may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or a laminate or other conductive layer.
  • the material of the first source and drain layer and the second source and drain layer may include a metal material, for example, it may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or laminate, etc., or it may be titanium /Aluminum/Titanium laminate and other conductive layers.
  • the bridge layer may be a conductive layer such as an indium tin oxide layer.
  • Figure 46 is a structural layout of another exemplary embodiment of the display panel of the present disclosure
  • Figure 47 is a structural layout of the electrode layer in Figure 46.
  • the display panel shown in Figure 46 is different from the display panel shown in Figure 32 in that the display panel shown in Figure 46 is not provided with a bridge layer.
  • the electrode layer in the display panel shown in Figure 46 includes a first bridge portion Bg1 and a second bridge portion Bg2. .
  • the first bridge portion Bg1 is connected to the first electrode portion R of the second electrode row ROW2, and the first bridge portion Bg1 is connected to the tenth bridge portion 410 in the pixel driving circuit of the second row and first column through a via hole.
  • the second bridge part Bg2 is connected to the second electrode part B of the first electrode row ROW1, and the second bridge part Bg2 is connected to the tenth bridge part 410 in the pixel driving circuit of the second row and third column through a via hole.
  • the first bridge portion Bg1 may include a first extension portion Bg11 and a sixth extension portion Bg16.
  • the orthographic projection of the first extension portion Bg11 on the base substrate extends along the first direction
  • the orthographic projection of an initial signal line Vinit1 on the base substrate at least partially overlaps
  • the orthographic projection of the sixth extension portion Bg16 on the base substrate extends along the second direction Y and is connected to the first power line in the pixel driving circuit of this column. Orthographic projections of VDD on the base substrate at least partially overlap.
  • the orthographic projection of the sixth extension part Bg16 on the base substrate may overlap with the orthographic projection of any fourth signal line that outputs a stable voltage signal on the base substrate.
  • the fourth signal line may include the above-mentioned first power supply line VDD.
  • the fourth signal line may further include: the equipotential signal line of the second power supply end in Figure 10, the third An equipotential signal line at the first initial signal end, an equipotential signal line at the second initial signal end, etc.
  • the second bridge portion Bg2 includes a second extension portion Bg22, a third extension portion Bg23, and a seventh extension portion Bg27.
  • the seventh extension portion Bg27 is connected between the second extension portion Bg22 and the third extension portion Bg23.
  • the orthographic projection of the second extension part Bg22 on the base substrate extends along the first direction
  • the orthographic projection of the three extending portions Bg23 on the base substrate extends along the second direction Y, and at least partially overlaps with the orthographic projection of the third conductive portion 23 on the base substrate. This arrangement can reduce the coupling effect of other AC signals on the bridge portion, and can also reduce the impact of the first bridge portion Bg1 and the second bridge portion Bg2 on the transmittance of the display panel.
  • the orthographic projection of the seventh extension portion Bg27 on the base substrate can overlap with the orthographic projection of the second active portion 72 on the base substrate, and the seventh extension portion Bg27 can reduce the impact of light on the output characteristics of the second transistor T2. Influence.
  • the pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C.
  • the first electrode of the fourth transistor T4 is connected to the data signal terminal Da
  • the second electrode of the fourth transistor T4 is connected to the first electrode of the driving transistor T3, and the gate electrode of the fourth transistor T4 is connected to the first gate driving signal terminal G1
  • the first pole of the fifth transistor T5 is connected to the first power terminal VDD
  • the second pole of the fifth transistor T5 is connected to the first pole of the driving transistor T3, and the gate of the fifth transistor T5 is connected to the enable signal terminal EM
  • the gate is connected to the node N
  • the first electrode of the second transistor T2 is connected to the node N
  • the second electrode of the second transistor T2 is connected to the second electrode of the driving transistor T3, and the gate of the second transistor T2 is connected to the second gate driving signal terminal.
  • the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3
  • the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7
  • the gate electrode of the sixth transistor T6 is connected to the enable signal terminal EM.
  • the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate electrode of the seventh transistor T7 is connected to the second reset signal terminal Re2; the second electrode of the first transistor T1 is connected to the node N, and the first electrode of the first transistor T1
  • the first initial signal terminal Vinit1 is connected, the gate of the first transistor T1 is connected to the first reset signal terminal Re1; the first electrode of the capacitor C is connected to the node N, and the second electrode of the capacitor C is connected to the first power terminal VDD.
  • the pixel driving circuit can be connected to a light-emitting unit OLED for driving the light-emitting unit OLED to emit light.
  • the light-emitting unit OLED can be connected between the second pole of the sixth transistor T6 and the second power terminal VSS, and the first electrode of the light-emitting unit can be
  • the second electrode of the light-emitting unit may be the anode of the light-emitting unit, and the second electrode of the light-emitting unit may be the cathode of the light-emitting unit.
  • the first transistor T1 and the second transistor T2 may be N-type transistors.
  • the first transistor T1 and the second transistor T2 may be N-type metal oxide transistors. N-type transistors have smaller leakage current, thereby avoiding In the light-emitting phase, node N leaks electricity through the first transistor T1 and the second transistor T2.
  • the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors.
  • the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 can be P-type low-temperature polycrystalline silicon transistors.
  • P-type transistors have high carrier mobility, which is conducive to achieving high resolution, high response speed, high pixel density, and high aperture ratio display. panel.
  • the first initial signal terminal and the second initial signal terminal may output the same or different voltage signals according to actual conditions.
  • FIG. 49 it is a timing diagram of each node in a driving method of the pixel driving circuit in Figure 48.
  • G1 represents the timing of the first gate drive signal terminal G1
  • G2 represents the timing of the second gate drive signal terminal G2
  • Re1 represents the timing of the first reset signal terminal Re1
  • Re2 represents the timing of the second reset signal terminal Re2.
  • EM represents the timing of the enable signal terminal EM
  • Da represents the timing of the data signal terminal Da.
  • the driving method of the pixel driving circuit may include a reset phase t1, a data writing phase t2, and a light emitting phase t3.
  • the first reset signal terminal Re1 outputs a high-level signal
  • the second reset signal terminal Re2 outputs a low-level signal
  • the first transistor T1 and the seventh transistor T7 are turned on
  • the first initial signal terminal Vinit1 is connected to the node N
  • the first initial signal is input
  • the second initial signal terminal Vinit2 inputs the second initial signal to the first electrode of the light-emitting unit OLED.
  • the second gate drive signal terminal G2 outputs a high-level signal
  • the first gate drive signal terminal G1 outputs a low-level signal
  • the fourth transistor T4 and the second transistor T2 are turned on, and at the same time the data signal
  • the terminal Da outputs the data signal to write the compensation voltage Vdata+Vth to the node N, where Vdata is the voltage of the data signal, and Vth is the threshold voltage of the driving transistor T3.
  • the enable signal terminal EM outputs a low-level signal
  • the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in the capacitor C.
  • the driving transistor output current formula is as follows:
  • the pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.
  • the display panel may include a base substrate, a shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, and a base plate. layer, a third gate layer, a first source-drain layer, a second source-drain layer, and an electrode layer, wherein an insulating layer may be provided between the adjacent layers.
  • Figure 50 is a structural layout of a display panel in an exemplary embodiment of the present disclosure.
  • Figure 51 is a structural layout of the occlusion layer in Figure 50.
  • Figure 52 is a structural layout of the first active layer in Figure 50.
  • Figure 53 is the structural layout of the first gate layer in Figure 50
  • Figure 54 is the structural layout of the second gate layer in Figure 50
  • Figure 55 is the structural layout of the second active layer in Figure 50
  • Figure 56 is the structural layout of the third gate layer in Figure 50
  • Figure 57 is the structural layout of the first source and drain layer in Figure 50
  • Figure 58 is the structural layout of the second source and drain layer in Figure 50
  • Figure 59 is the electrode in Figure 50
  • Figure 60 is the structural layout of the shielding layer and the first active layer in Figure 50.
  • Figure 61 is the structural layout of the shielding layer, the first active layer and the first gate layer in Figure 50.
  • Figure 62 is The structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in Figure 50.
  • Figure 63 shows the shielding layer, the first active layer, the first gate layer, and the second gate layer in Figure 50. The structural layout of the gate layer and the second active layer.
  • Figure 64 shows the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate in Figure 50 Layer structural layout
  • Figure 65 shows the shielding layer, first active layer, first gate layer, second gate layer, second active layer, third gate layer, and first source and drain layer in Figure 50 Structural layout
  • Figure 66 shows the shielding layer, first active layer, first gate layer, second gate layer, second active layer, third gate layer, first source and drain layer, second Structural layout of source and drain layers.
  • the display panel may include a plurality of pixel driving circuits shown in FIG. 48 . As shown in FIG.
  • the plurality of pixel driving circuits may include a first pixel driving circuit P1 and a second pixel driving circuit P2 adjacently distributed in the first direction X, and the first pixel driving circuit P1 and the second pixel driving circuit P2 It can be set up with mirror symmetry on the mirror symmetry plane BB.
  • the mirror symmetry plane BB may be perpendicular to the base substrate.
  • the orthographic projection of the first pixel driving circuit P1 on the base substrate and the orthographic projection of the second pixel driving circuit P2 on the base substrate can be arranged symmetrically with the intersection line of the mirror symmetry plane BB and the base substrate as the symmetry axis.
  • the first pixel driving circuit P1 and the second pixel driving circuit P2 may form a repeating unit, and the display panel may include a plurality of repeating units distributed in an array in the first direction X and the second direction Y.
  • the shielding layer may include multiple shielding parts 61, and adjacent shielding parts 61 may be connected to each other. It should be understood that in other exemplary embodiments, the display panel may not include the blocking layer.
  • the first active layer may include a third active part 73 , a fourth active part 74 , a fifth active part 75 , a sixth active part 76 , a seventh active part 76 , and a third active part 73 .
  • the third active part 73 may be used to form a channel region of the driving transistor T3; the fourth active part 74 may be used to form a channel region of the fourth transistor T4; and the fifth active part 75 may be used to form a channel region of the fourth transistor T4.
  • the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; and the seventh active portion 77 can be used to form the channel region of the seventh transistor T7.
  • the first active layer also includes a ninth active part 79 , a tenth active part 710 , an eleventh active part 711 , a twelfth active part 712 , and a thirteenth active part 713 .
  • the ninth active part 79 is connected to the side of the fifth active part 75 away from the third active part 73
  • the ninth active part 79 is connected to two adjacent repeating units in the first direction X. between the fifth active part 75 .
  • the tenth active part 710 is connected between the sixth active part 76 and the seventh active part 77 .
  • the eleventh active part 711 is connected between the sixth active part 76 and the third active part 73 .
  • the twelve active parts 712 are connected to an end of the fourth active part 74 away from the third active part 73
  • the thirteenth active part 713 is connected to an end of the seventh active part 77 away from the sixth active part 76 .
  • the orthographic projection of the shielding portion 61 on the base substrate can cover the orthographic projection of the third active portion 73 on the base substrate, and the shielding portion 61 can reduce the impact of light on the driving characteristics of the driving transistor T3.
  • the first active layer may be formed of polysilicon material.
  • the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type low-temperature polysilicon thin film transistors.
  • the first gate layer may include: a first conductive portion 11, a first gate line G1, an enable signal line EM, and a second reset signal line Re2.
  • the first gate line G1 can be used to provide the first gate drive signal terminal in Figure 48;
  • the enable signal line EM can be used to provide the enable signal terminal in Figure 48;
  • the second reset signal line Re2 can be used to provide the enable signal terminal in Figure 48 The second reset signal terminal in .
  • the orthographic projection of the first gate line G1 on the base substrate, the orthographic projection of the enable signal line EM on the base substrate, and the orthographic projection of the second reset signal line Re2 on the base substrate can all extend along the first direction X .
  • the orthographic projection of the first gate line G1 on the base substrate covers the orthographic projection of the fourth active part 74 on the base substrate, and part of the structure of the first gate line G1 is used to form the gate electrode of the fourth transistor.
  • the orthographic projection of the enable signal line EM on the base substrate covers the orthographic projection of the fifth active part 75 on the base substrate and the orthographic projection of the sixth active part 76 on the base substrate.
  • the enable signal line EM Part of the structure may be used to form gates of the fifth transistor T5 and the sixth transistor T6 respectively.
  • the orthographic projection of the second reset signal line Re2 on the base substrate can cover the orthographic projection of the seventh active part 77 on the base substrate, and part of the structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7 pole.
  • the orthographic projection of the first conductive portion 11 on the base substrate covers the orthographic projection of the third active portion 73 on the base substrate.
  • the first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first capacitor C. electrode.
  • the first gate line G1 in the pixel driving circuit of this row can be multiplexed as the second reset signal line Re2 in the pixel driving circuit of the next row, and the display panel can be driven row by row from top to bottom.
  • the shielding layer can also be connected to a stable power supply terminal.
  • the shielding layer can be connected to the first power supply terminal, the first initial signal terminal, the second initial signal terminal, etc. in Figure 48.
  • the shielding portion 61 can shield the impact of other signals on the driving transistor T3. Noise impact.
  • the display panel can use the first gate layer as a mask to conduct conduction processing on the first active layer, that is, the area of the first active layer covered by the first gate layer can form the channel region of the transistor. A region of the first active layer not covered by the first gate layer forms a conductor structure.
  • the second gate layer may include: a first initial signal line Vinit1 , a third reset signal line 2Re1 , a third gate line 2G2 , and a plurality of third conductive portions 23 .
  • the first initial signal line Vinit1 is used to provide the first initial signal terminal in Figure 48
  • the third reset signal line 2Re1 can be used to provide the first reset signal terminal in Figure 48
  • the third gate line 2G2 can be used to provide The second gate drive signal terminal in Figure 48.
  • the orthographic projection of the first initial signal line Vinit1 on the base substrate, the orthographic projection of the third reset signal line 2Re1 on the base substrate, and the orthographic projection of the third gate line 2G2 on the base substrate can all be along the first direction X. extend.
  • the second gate layer may further include a plurality of connecting portions 24 .
  • the connecting portions 24 are connected to two third third units adjacent in the first direction X. between conductive parts 23.
  • adjacent third conductive portions 23 in the same repeating unit may also be connected.
  • the second active layer may include a first active part 81, a second active part 82, a fourteenth active part 814, a fifteenth active part 815, a sixteenth active part Active part 816.
  • the first active portion 81 is used to form a channel region of the first transistor T1
  • the second active portion 82 is used to form a channel region of the second transistor T2.
  • the fifteenth active part 815 is connected between the first active part 81 and the second active part 82 .
  • the fourteenth active part 814 is connected to an end of the first active part 81 away from the second active part 82
  • the sixteenth active part 816 is connected to an end of the second active part 82 away from the first active part 81 .
  • the second active layer may be formed of indium gallium zinc oxide, and accordingly, the first transistor T1 and the second transistor T2 may be N-type metal oxide thin film transistors.
  • the orthographic projection of the third gate line 2G2 on the base substrate can cover the orthographic projection of the second active part 82 on the base substrate, and part of the structure of the third gate line 2G2 can be used to form the bottom gate of the second transistor T2.
  • the orthographic projection of the third reset signal line 2Re1 on the base substrate can cover the orthographic projection of the first active part 81 on the base substrate, and part of the structure of the third reset signal line 2Re1 can be used to form the bottom of the first transistor T1 gate.
  • the third gate layer may include a first reset signal line 3Re1 and a second gate line 3G2. Both the orthographic projection of the first reset signal line 3Re1 on the base substrate and the orthographic projection of the second gate line 3G2 on the base substrate can extend along the first direction X.
  • the first reset signal line 3Re1 can be used to provide the first reset signal terminal in FIG. 48
  • the orthographic projection of the first reset signal line 3Re1 on the base substrate can cover the orthographic projection of the first active part 81 on the base substrate.
  • part of the structure of the first reset signal line 3Re1 can be used to form the top gate of the first transistor T1, and at the same time, the first reset signal line 3Re1 can be connected to the third reset signal line 2Re1 through a via hole located in the frame area of the display panel.
  • the second gate line 3G2 can be used to provide the second gate driving signal terminal in FIG. 48 , and the orthographic projection of the second gate line 3G2 on the base substrate can cover the orthographic projection of the second active portion 82 on the base substrate.
  • part of the structure of the second gate line 3G2 can be used to form the top gate of the second transistor T2, and at the same time, the second gate line 3G2 can be connected to the third gate line 2G2 through a via hole located in the frame area of the display panel.
  • the display panel can use the third gate layer as a mask to conduct conduction processing on the second active layer, that is, the area of the second active layer covered by the third gate layer can form the channel region of the transistor. A region of the second active layer not covered by the third gate layer forms a conductor structure.
  • the first source and drain layer may include a power connection line 4VDD, a second initial signal line Vinit2, a fifth bridge portion 45, a sixth bridge portion 46, a seventh bridge portion 47, and an eighth bridge portion. part 48 and the ninth bridge part 49.
  • the orthographic projection of the power connection line 4VDD on the base substrate extends along the first direction the second electrode.
  • the fifth bridge portion 45 may be connected to the tenth active portion 710 through a via hole to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.
  • the sixth bridge portion 46 can be connected to the eleventh active portion 711 and the sixteenth active portion 816 respectively through via holes to connect the second electrode of the second transistor T2, the first electrode of the sixth transistor T6, and the driving transistor T3. the second pole.
  • the seventh bridge portion 47 can be connected to the fifteenth active portion 815 and the first conductive portion 11 through via holes respectively, so as to connect the first electrode of the second transistor T2 and the gate electrode of the driving transistor.
  • An opening 231 is formed on the third conductive part 23, and the orthographic projection of the via hole connected between the first conductive part 11 and the seventh bridge part 47 on the base substrate is located within the orthographic projection of the opening 231 on the base substrate. So that the via hole and the third conductive part 23 are insulated from each other.
  • the eighth bridge portion 48 can be connected to the fourteenth active portion 814 and the first initial signal line Vinit1 through via holes respectively, so as to connect the first pole of the first transistor and the first initial signal terminal. Wherein, in the same repeating unit, two adjacent pixel driving circuits may share the same eighth bridge portion 48 .
  • the ninth bridge part 49 may be connected to the twelfth active part 712 through a via hole to connect the first electrode of the fourth transistor.
  • the second initial signal line Vinit2 can be used to provide the second initial signal terminal in Figure 48.
  • the orthographic projection of the second initial signal line Vinit2 on the substrate can extend along the first direction X, and the second initial signal line Vinit2 can pass through
  • the via hole is connected to the thirteenth active part 713 to connect the first electrode and the second initial signal terminal of the seventh transistor.
  • the second source-drain layer may include a plurality of first power lines VDD, a plurality of data lines Da, and a tenth bridge portion 510 .
  • the orthographic projection of the first power line VDD on the base substrate and the orthographic projection of the data line Da on the base substrate can both extend along the second direction Y.
  • the first power line VDD may be used to provide the first power terminal in FIG. 48
  • the data line Da may be used to provide the data signal terminal in FIG. 48 .
  • each column of pixel driving circuits can be provided with a first power line VDD.
  • the first power line VDD can be connected to the power connection line 4VDD through a via hole to connect the first pole of the fifth transistor and the first power terminal.
  • the data line Da may be connected to the ninth bridge portion 49 through a via hole to connect the first pole of the fourth transistor and the data signal terminal.
  • the tenth bridge part 510 may be connected to the fifth bridge part 45 through a via hole to connect the second pole of the seventh transistor.
  • adjacent first power lines VDD are connected to each other, so that the first power line VDD, the power connection line 4VDD, and the third conductive portion 23 can form a grid structure. Power cords reduce the voltage drop on the power signal across them.
  • multiple openings VDDx may be formed on the connected first power line VDD, and the openings VDDx may be located in the light-transmitting area of the display panel, that is, the orthographic projection of the openings VDDx on the substrate may be different from other non-transparent
  • the orthographic projection of the structural layer on the base substrate does not overlap, and this arrangement can improve the transmittance of the display panel.
  • the other non-transparent structural layers may include a first gate layer, a second gate layer, a first source-drain layer, a first active layer, and a second active layer.
  • the first power line VDD may include a first power line segment VDD1, a second power line segment VDD2, and a third power line segment VDD3.
  • the second power line segment VDD2 is connected to the first power line segment VDD1 and the third power line segment.
  • the size of the orthographic projection of the second power line segment VDD2 on the substrate in the first direction X may be larger than the orthogonal projection of the first power line segment VDD1 on the substrate in the first direction.
  • the size in the first direction The size in the first direction X.
  • the orthographic projection of the second power line segment VDD2 on the base substrate can also cover the orthographic projection of the first active part 81 on the base substrate and the orthographic projection of the second active part 82 on the base substrate.
  • the power line segment VDD2 can reduce the impact of light on the characteristics of the first transistor T1 and the second transistor T2.
  • the orthographic projection of the first power line VDD on the base substrate can also at least partially overlap with the orthographic projection of the seventh bridge portion 47 on the base substrate, and the first power line VDD can be used to shield other signals from the seventh bridge. The noise of the bridge portion 47 interferes, thereby improving the stability of the gate voltage of the driving transistor T3.
  • the pixel electrode layer may include a plurality of electrode parts: a first electrode part R, a third electrode part G, and a second electrode part B. Each electrode part may be connected to the third electrode of the sixth transistor through a bridge part Bg. Two poles.
  • the first electrode portion R, the third electrode portion G, the second electrode portion B, and the third electrode portion G are sequentially distributed alternately in the first direction X.
  • the plurality of electrode parts form a plurality of electrode rows.
  • the plurality of electrode rows include sequentially adjacent first electrode rows ROW1, third electrode rows ROW3, second electrode rows ROW2, and fourth electrode rows ROW4.
  • the first electrode row ROW1 is included in The first electrode portion R and the second electrode portion B are distributed alternately in the second direction Y;
  • the third electrode row ROW3 includes a plurality of third electrode portions G distributed in the second direction Y;
  • the second electrode row ROW2 includes The second electrode parts B and the first electrode parts R are distributed alternately in the second direction Y;
  • the fourth electrode row ROW4 includes a plurality of third electrode parts G distributed in the second direction Y.
  • the minimum distance S1 in the second direction Y of the orthographic projection of the two third electrode portions G located in adjacent electrode rows of the same electrode column on the base substrate is greater than the distance S1 of the first electrode portion R on the base substrate.
  • the dimension S2 of the orthogonal projection on the second electrode part B in the second direction Y is larger than the dimension S3 of the orthogonal projection on the base substrate of the second electrode part B in the second direction Y.
  • the orthographic projection of the first electrode part R on the base substrate coincides with the orthographic projection of its corresponding opening on the base substrate on the pixel definition layer
  • the orthographic projection of the third electrode part G on the base substrate coincides with the pixel definition layer.
  • the orthographic projection of the corresponding opening on the layer on the base substrate coincides with the orthographic projection of the second electrode portion B on the base substrate and the orthographic projection of the corresponding opening on the pixel definition layer on the base substrate.
  • two second power line segments VDD2 in adjacent first power lines VDD are connected.
  • the orthographic projection of the two connected second power supply line segments VDD2 on the base substrate covers the orthographic projection of the electrode portion on the base substrate that intersects with its orthographic projection on the base substrate. This arrangement can make the height of each position of the electrode portion more precise. Uniform.
  • the electrode layer may further include a first bridge portion Bg1 and a second bridge portion Bg2.
  • the first bridge portion Bg1 is connected to the first electrode portion R in the third electrode column ROW3, and the first bridge portion Bg1 is connected to the tenth bridge portion 510 in the pixel driving circuit of the second row and first column through a via hole.
  • the second bridge part Bg2 is connected to the second electrode part B in the first electrode row ROW1, and the second bridge part Bg2 is connected to the tenth bridge part 510 in the pixel driving circuit of the second row and third column through a via hole.
  • the black squares drawn on the side of the first source and drain layer facing away from the base substrate represent the via holes of the first source and drain layer connected to other levels on the side facing the base substrate.
  • the black square drawn on the side of the second source and drain layer facing away from the base substrate indicates the via holes of the second source and drain layer connecting to other levels on the side facing the base substrate;
  • the black square drawn on the side of the electrode layer facing away from the base substrate Indicates the vias through which the electrode layer connects to other levels on the side facing the base substrate.
  • the black square only represents the location of the via hole. Different via holes represented by black squares at different positions can penetrate different insulation layers.
  • the display panel may further include a first insulating layer 91, a second insulating layer 92, a third insulating layer 93, a fourth insulating layer 94, a fifth insulating layer 95, a first dielectric layer 96, a passivation layer 97, a first Flat layer 98, second flat layer 99, wherein the base substrate 90, the shielding layer, the first insulating layer 91, the first active layer, the second insulating layer 92, the first gate layer, the third insulating layer 93, The second gate layer, the fourth insulating layer 94, the second active layer, the fifth insulating layer 95, the third gate layer, the first dielectric layer 96, the first source and drain layer, the passivation layer 97, the first The flat layer 98, the second source and drain layer, and the second flat layer 99 are stacked in sequence.
  • the first insulating layer 91 , the second insulating layer 92 , the third insulating layer 93 , the fourth insulating layer 94 and the fifth insulating layer 95 can be a single-layer structure or a multi-layer structure, and the first insulating layer 91 and the second insulating layer 92.
  • the material of the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the first dielectric layer 96 can be silicon nitride.
  • the material of the first flat layer 98 and the second flat layer 99 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG) and other materials.
  • Passivation layer 97 may be a silicon oxide layer.
  • the base substrate 90 may include a glass substrate, a barrier layer, and a polyimide layer that are stacked in sequence.
  • the barrier layer may be an inorganic material.
  • the material of the first gate layer, the second gate layer, and the third gate layer may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or a laminate or other conductive layer.
  • the material of the first source and drain layer and the second source and drain layer may include a metal material, for example, it may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or laminate, etc., or it may be titanium /Aluminum/Titanium laminate and other conductive layers.
  • first bridge portion and the second bridge portion may also be located on other conductive layers.
  • first bridge portion and the second bridge portion may be located on the second source-drain layer and Bridging layer between electrode layers.
  • Figure 68 is a structural layout of another exemplary embodiment of the display panel of the present disclosure.
  • Figure 69 shows the first active layer, the first gate layer, the second gate layer, The structural layout of the first source and drain layer, the second source and drain layer, and the bridge layer.
  • Figure 70 is the structural layout of the bridge layer in Figure 68.
  • the display panel shown in FIG. 68 is different from the display panel shown in FIG. 50 in that: in the display panel shown in FIG. 68 , the bridge layer may include a plurality of bridge parts Bg, and the bridge parts Bg are respectively connected to the tenth bridge part through via holes. 510 and electrode section.
  • the plurality of bridge portions include a first bridge portion Bg1 and a second bridge portion Bg2.
  • the first bridge part Bg1 may connect the tenth bridge part 510 in the pixel driving circuit of the first column and the second row and the first electrode part R in the third electrode column through a via hole.
  • the second bridge part Bg2 may connect the tenth bridge part 510 in the pixel driving circuit of the third column and the second row and the second electrode part B in the first electrode column through a via hole.
  • the source driving circuit may include a data latch 03 and a data reset circuit 04 .
  • the data latch 03 may be used to receive multiple original data signals, the original data signals including multiple original data in series, at least part of the original data in the original data signals is used to drive light-emitting units of different colors; data
  • the reset circuit 04 is used to generate a reset data signal according to the original data signal.
  • the reset data signal includes multiple reset data in series. The reset data in the same reset data signal is used to drive the same reset data signal. Colored lighting units.
  • the source driver circuit may also include a random access memory 01 , a data control circuit 02 , a boost circuit 05 , a digital-to-analog converter 06 , a data output terminal 07 , a timing controller TCON, and a gamma module 08 .
  • the random access memory 01 is used to receive picture data; the data control circuit 02 is used to optimize the picture data to generate the original data signal; the boost circuit 05 boosts the reset data signal; the digital-to-analog converter 06 boosts the voltage.
  • the reset data signal after digital-to-analog conversion is converted to digital-to-analog;
  • the data output terminal 07 transmits the reset data signal after digital-to-analog conversion to the corresponding data line;
  • the timing controller TCON can control the data control circuit 02, data latch 03, data Reset the working sequence of the circuit 04;
  • the gamma module 08 is used to provide gamma data, and the gamma data may include gamma voltages corresponding to each gray scale under each brightness value.
  • the original data signal corresponding to the first data line connected to the first pixel circuit column PX1 includes multiple series of original data, and the multiple series of original data are used for alternate driving.
  • the original data signal corresponding to the second data line connected to the second pixel circuit column PX2 includes multiple series of original data, and the multiple series of original data are used to alternately drive the red light-emitting unit. and blue light-emitting units.
  • the data reset circuit 04 can replace the original data corresponding to the first data line for driving the blue light-emitting unit with the original data corresponding to the second data line for driving the red light-emitting unit; at the same time, the original data corresponding to the second data line is used to drive the red light-emitting unit.
  • the original data for driving the red light-emitting unit is replaced with the original data for driving the blue light-emitting unit corresponding to the first data line, thereby generating a reset data signal.
  • the scale of the drawings in this disclosure can be used as a reference in the actual process, but is not limited thereto, for example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line, It can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the figures described in this disclosure are only structural schematic diagrams.
  • the qualifiers such as first and second are only used to define different structure names and have no specific order meaning.
  • the same structural layer can be formed through the same patterning process.
  • the orthographic projection of a certain structure on the base substrate extends along a certain direction. It can be understood that the orthographic projection of the structure on the base substrate extends straightly or in a bend along the direction.
  • This exemplary embodiment also provides a display device, which includes the above-mentioned display panel.
  • the display device can be a display device such as a mobile phone, a tablet computer, or a television.

Abstract

一种显示面板及显示装置，可以降低源极驱动电路(D IC)的功耗，以及可以改善显示面板色偏的问题。其中，显示面板包括：衬底基板(90)、电极层、多个像素驱动电路(P11, P12, P13,..., P24)、多条数据线(Da)，电极层位于衬底基板(90)的一侧，电极层包括多个电极部，电极部用于形成发光单元(OLED)的第一电极，多个电极部在衬底基板(90)上的正投影沿第一方向(X)和第二方向(Y)阵列分布，第一方向(X)和第二方向(Y)相交，在第二方向(Y)上分布的多个电极部形成电极列，至少部分电极列包括用于形成不同颜色发光单元(OLED)第一电极的电极部；多个像素驱动电路(P11, P12, P13,..., P24)与电极部对应设置，像素驱动电路(P11, P12, P13,..., P24)连接与其对应的电极部，像素驱动电路(P11, P12, P13,..., P24)用于驱动发光单元(OLED)发光；数据线(Da)在衬底基板(90)上的正投影沿第一方向(X)间隔分布且沿第二方向(Y)延伸，数据线(Da)连接多个像素驱动电路(P11, P12, P13,..., P24)，数据线(Da)用于向与其连接的像素驱动电路(P11, P12, P13,..., P24)提供数据信号，且同一数据线(Da)所连接的多个像素驱动电路(P11, P12, P13,..., P24)用于驱动同一颜色的发光单元(OLED)。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
相关技术中，显示面板中同一数据线需要向不同颜色的子像素单元提供数据信号，从而显示面板中的源极驱动电路具有较高的功耗。此外，高频显示面板也容易出现色偏的问题。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
根据本公开的一个方面，提供一种显示面板，其中，所述显示面板包括：衬底基板、电极层、多个像素驱动电路、多条数据线。电极层位于所述衬底基板的一侧，所述电极层包括多个电极部，所述电极部用于形成发光单元的第一电极，多个所述电极部在所述衬底基板上的正投影沿第一方向和第二方向阵列分布，所述第一方向和所述第二方向相交，在所述第二方向上分布的多个所述电极部形成电极列，至少部分所述电极列包括用于形成不同颜色发光单元第一电极的电极部；像素驱动电路与所述电极部对应设置，所述像素驱动电路连接与其对应的所述电极部，所述像素驱动电路用于驱动所述发光单元发光；数据线在所述衬底基板上的正投影沿所述第二方向延伸，所述数据线连接多个所述像素驱动电路，所述数据线用于向与其连接的所述像素驱动电路提供数据信号，且同一所述数据线所连接的多个所述像素驱动电路用于驱动同一颜色的所述发光单元。
本公开一种示例性实施例中，多个所述电极部中包括第一电极部和第二电极部，所述第一电极部和第二电极部分别用于形成不同颜色发光单元的第一电极；多个所述电极列中包括：第一电极列、第二电极列，第一电 极列包括多个所述第一电极部和多个所述第二电极部，在同一所述第一电极列中，所述第一电极部和所述第二电极部在所述衬底基板上的正投影沿所述第二方向依次交替分布；第二电极列包括多个所述第一电极部和多个所述第二电极部，在同一所述第二电极列中，所述第一电极部和所述第二电极部在所述衬底基板上的正投影沿所述第二方向依次交替分布；其中，在所述第一电极列和所述第二电极列中，所述第一电极部和所述第二电极部位于同一行；多条所述数据线中包括：第一数据线、第二数据线，所述第一数据线所连接的像素驱动电路连接所述第一电极列和所述第二电极列中的所述第一电极部；所述第二数据线所连接的像素驱动电路连接所述第一电极列和所述第二电极列中的所述第二电极部。
本公开一种示例性实施例中，多个所述电极部中还包括第三电极部，所述第一电极部、第二电极部、第三电极部分别用于形成不同颜色发光单元的第一电极；多个所述电极列中还包括：第三电极列、第四电极列，所述第一电极列、第三电极列、第二电极列、第四电极列在所述第一方向上依次交替分布；所述第三电极列包括多个所述第三电极部，同一所述第三电极列中的第三电极部在所述衬底基板上的正投影在所述第二方向上间隔分布；所述第四电极列包括多个所述第三电极部，同一所述第四电极列中的第三电极部在所述衬底基板上的正投影在所述第二方向上间隔分布。
本公开一种示例性实施例中，多个所述像素驱动电路在所述衬底基板上的正投影沿所述第一方向和第二方向阵列分布，在所述第二方向上分布的多个所述像素驱动电路形成像素电路列，多个所述像素电路列中包括第一像素电路列和第二像素电路列；所述第一像素电路列中的像素驱动电路连接所述第一电极列中的电极部；所述第二像素电路列中的像素驱动电路连接所述第二电极列中的电极部；所述第一数据线连接所述第一电极列和所述第二电极列中所述第一电极部所连接的像素驱动电路；所述第二数据线连接所述第一电极列和所述第二电极列中第二电极部所连接的像素驱动电路。
本公开一种示例性实施例中，多个所述像素驱动电路在所述衬底基板上的正投影沿所述第一方向和所述第二方向阵列分布，在所述第二方向分布的多个所述像素驱动电路形成像素电路列，所述像素电路列包括第一像 素电路列和第二像素电路列；所述第一数据线连接所述第一像素电路列中的像素驱动电路，所述第二数据线连接所述第二像素电路列中的像素驱动电路；所述第一像素电路列中的像素驱动电路连接所述第一电极列和第二电极列中的第一电极部；所述第二像素电路列中的像素驱动电路连接所述第一电极列和第二电极列中的第二电极部。
本公开一种示例性实施例中，所述显示面板还包括：第一桥接部、第二桥接部，所述第一桥接部连接于所述第一像素电路列中像素驱动电路和所述第二电极列中第一电极部之间；所述第二桥接部连接于所述第二像素电路列中像素驱动电路和所述第一电极列中第二电极部之间。
本公开一种示例性实施例中，所述显示面板还包括：第一信号线、第二信号线，第一信号线在所述衬底基板上的正投影沿所述第一方向延伸；第二信号线在所述衬底基板上的正投影沿所述第一方向延伸；其中，所述第一信号线和所述第二信号线用于提供稳定电压信号；所述第一桥接部包括第一延伸部，所述第二桥接部包括第二延伸部，所述第一延伸部在所述衬底基板上的正投影、所述第二延伸部在所述衬底基板上的正投影均沿所述第一方向延伸；所述第一延伸部在所述衬底基板上的正投影与所述第一信号线在所述衬底基板上的正投影至少部分交叠，和/或所述第二延伸部在所述衬底基板上的正投影和所述第二信号线在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述像素驱动电路包括驱动晶体管、第一晶体管、第七晶体管，所述第一晶体管的第一极连接第一初始信号线，所述第一晶体管的第二极连接所述驱动晶体管的栅极，所述第七晶体管的第一极连接第二初始信号线，所述第七晶体管的第二极连接所述驱动晶体管的第二极；所述第一初始信号线形成所述第一信号线，所述第二初始信号线形成所述第二信号线；或，所述第一初始信号线形成所述第二信号线，所述第二初始信号线形成所述第一信号线。
本公开一种示例性实施例中，所述像素驱动电路包括驱动晶体管、第一晶体管，所述第一晶体管的第一极连接第一初始信号线，所述第一晶体管的第二极连接所述驱动晶体管的栅极；相邻的两条所述第一初始信号线分别形成所述第一信号线和所述第二信号线。
本公开一种示例性实施例中，所述显示面板还包括：第三信号线，所述第三信号线在所述衬底基板上的正投影沿所述第二方向延伸，且所述第三信号线用于提供稳定电压信号；所述第二桥接部还包括第三延伸部，所述第三延伸部在所述衬底基板上的正投影沿所述第二方向延伸，且所述第三延伸部在所述衬底基板上的正投影和所述第三信号线在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述显示面板还包括：第四信号线，所述第四信号线在所述衬底基板上的正投影沿所述第二方向延伸，且所述第四信号线用于提供稳定电压信号；所述第一桥接部还包括第六延伸部，所述第六延伸部在所述衬底基板上的正投影沿所述第二方向延伸，且所述第六延伸部在所述衬底基板上的正投影和所述第四信号线在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述像素驱动电路包括驱动晶体管、第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，所述第二晶体管的第二极连接所述驱动晶体管的第二极；所述显示面板还包括：第一有源层，第一有源层位于所述衬底基板和所述电极层之间，所述第一有源层包括第二有源部，所述第二有源部用于形成所述第二晶体管的沟道区；所述第二桥接部包括第二延伸部、第三延伸部、连接于所述第二延伸部和第三延伸部之间的第七延伸部，所述第二延伸部在所述衬底基板上的正投影沿所述第一方向延伸，所述第三延伸部在所述衬底基板上的正投影沿所述第二方向延伸，所述第七延伸部在所述衬底基板上的正投影和所述第二有源部在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述显示面板还包括：第三桥接部、第四桥接部，所述第三桥接部连接于所述第一像素电路列中像素驱动电路和所述第一电极列中的第一电极部之间；所述第四桥接部连接于所述第二像素电路列中的像素驱动电路和所述第二电极列中的第二电极部之间。
本公开一种示例性实施例中，所述第一桥接部连接位于同一行数的像素驱动电路和电极部之间，所述第二桥接部连接位于同一行数的像素驱动电路和电极部之间，所述第三桥接部连接位于同一行列数的像素驱动电路和电极部之间，所述第四桥接部连接位于同一行列数的像素驱动电路和电 极部之间。
本公开一种示例性实施例中，所述第一桥接部和其他结构形成的寄生电容容量为C1，所述第二桥接部和其他结构形成的寄生电容容量为C2，所述第三桥接部和其他结构形成的寄生电容容量为C3，所述第四桥接部和其他结构形成的寄生电容容量为C4；其中，C1＝N1*C3，C2＝N2*C4，N1大于等于70％且小于等于130％，N2大于等于70％且小于等于130％。
本公开一种示例性实施例中，显示面板还包括：多条第三信号线，所述第三信号线在所述衬底基板上的正投影沿所述第二方向延伸且沿所述第一方向间隔分布，且所述第三信号线用于提供稳定电压信号；所述第三桥接部包括第四延伸部，所述第四桥接部包括第五延伸部，所述第四延伸部在所述衬底基板上的正投影、所述第五延伸部在所述衬底基板上的正投影均沿所述第二方向延伸；所述第四延伸部在所述衬底基板上的正投影和所述第三信号线在所述衬底基板上的正投影至少部分交叠，所述第五延伸部在所述衬底基板上的正投影和另一所述第三信号线在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述像素驱动电路包括驱动晶体管，所述显示面板还包括：第一电源线，第一电源线连接所述驱动晶体管的第一极，所述第一电源线形成所述第三信号线。
本公开一种示例性实施例中，所述显示面板还包括：第一源漏层、第二源漏层，第一源漏层位于所述衬底基板和所述电极层之间；第二源漏层位于所述第一源漏层和所述电极层之间；所述第一桥接部、第二桥接部、第三桥接部、第四桥接部位于所述电极层；或，所述第一桥接部、所述第二桥接部、第三桥接部、第四桥接部所在导电层位于所述第二源漏层和所述电极层之间；或，所述第一桥接部、所述第二桥接部、第三桥接部、第四桥接部所在导电层位于所述第二源漏层和所述第一源漏层之间。
本公开一种示例性实施例中，所述显示面板还包括：源极驱动电路，所述源极驱动电路包括：数据锁存器、数据重置电路，数据锁存器用于接收多个原始数据信号，所述原始数据信号包括串行的多个原始数据，至少部分所述原始数据信号中的原始数据用于驱动不同颜色的发光单元；数据重置电路用于根据所述原始数据信号生成重置数据信号，所述重置数据信 号包括串行的多个重置数据，同一所述重置数据信号中的重置数据用于驱动同一颜色的发光单元。
本公开一种示例性实施例中，所述像素驱动电路包括驱动晶体管、第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，所述第二晶体管的第二极连接所述驱动晶体管的第二极；所述显示面板还包括：第一有源层，第一有源层位于所述衬底基板和所述电极层之间，所述第一有源层包括第二有源部，所述第二有源部用于形成所述第二晶体管的沟道区；所述电极层还包括：增设部，增设部连接于所述电极部，所述增设部在所述衬底基板上的正投影和所述第二有源部在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述像素驱动电路包括驱动晶体管、第一晶体管，所述第一晶体管的第一极连接第一初始信号线，第二极连接所述驱动晶体管的栅极；所述显示面板还包括：第二栅极层、第一源漏层，第二栅极层位于所述衬底基板和所述电极层之间，所述第二栅极层包括所述第一初始信号线，所述第一初始信号线在所述衬底基板上的正投影沿所述第一方向延伸；第一源漏层位于所述第二栅极层和所述电极层之间，所述第一源漏层包括第一初始连接线，所述第一初始连接线在所述衬底基板上的正投影沿所述第二方向延伸，所述第一初始连接线通过过孔连接与其在衬底基板上正投影相交的所述第一初始信号线，且所述第一初始连接线连接所述第一晶体管的第一极。
本公开一种示例性实施例中，所述显示面板包括沿所述第一方向和所述第二方向阵列分布的多个重复单元；每个所述重复单元包括沿第一方向分布的两个所述像素驱动电路，同一所述重复单元中两个所述像素驱动电路镜像对称设置；所述像素驱动电路包括驱动晶体管、电容，所述电容的第一电极连接所述驱动晶体管的栅极，所述电容的第二电极连接第一电源线；所述显示面板还包括：第二栅极层、第二源漏层，第二栅极层位于所述衬底基板和所述电极层之间，所述第二栅极层包括第三导电部，所述第三导电部用于形成所述电容的第二电极；第二源漏层位于所述第二栅极层和所述电极层之间，所述第二源漏层包括所述第一电源线，在同一重复单元中相邻两所述第一电源线相连接；且在所述第一方向上相邻的两所述重 复单元中相邻两所述第三导电部相连接。
本公开一种示例性实施例中，所述显示面板还包括：第一源漏层，第一源漏层位于所述第二栅极层和所述第二源漏层之间，所述第一源漏层包括电源连接线，所述电源连接线在所述衬底基板上的正投影沿所述第一方向延伸，所述电源连接线分别通过过孔连接所述第三导电部、第一电源线。
本公开一种示例性实施例中，所述第一电源线包括：第一电源线段、第二电源线段、第三电源线段，所述第二电源线段连接于所述第一电源线段和所述第三电源线段之间；所述第二电源线段在所述衬底基板上的正投影在第一方向上的尺寸大于第一电源线段在所述衬底基板上的正投影在第一方向上的尺寸，且所述第二电源线段在所述衬底基板上的正投影在第一方向上的尺寸大于所述第三电源线段在所述衬底基板上的正投影在第一方向上的尺寸；在同一重复单元中，相邻两所述第二电源线段相连接，相连接的所述第二电源线段在所述衬底基板上的正投影覆盖与其在所述衬底基板上正投影相交的电极部在所述衬底基板上的正投影。
本公开一种示例性实施例中，所述第一电源线包括：第一电源线段、第二电源线段、第三电源线段，所述第二电源线段连接于所述第一电源线段和所述第三电源线段之间；所述第二电源线段在所述衬底基板上的正投影在第一方向上的尺寸大于第一电源线段在所述衬底基板上的正投影在第一方向上的尺寸，且所述第二电源线段在所述衬底基板上的正投影在第一方向上的尺寸大于所述第三电源线段在所述衬底基板上的正投影在第一方向上的尺寸；在同一重复单元中，相邻两所述第一电源线段相连接，相邻两所述第三电源线段相连接，相连接的所述第一电源线段上形成有开口，和/或相连接的所述第三电源线段上形成有开口，所述开口位于所述显示面板的透光区。
根据本公开的一个方面，提供一种显示装置，其中，包括上述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中一种显示面板的结构示意图；
图2为显示面板显示纯红色画面时不同数据线上的时序图；
图3为本公开显示面板另一种示例性实施例的结构示意图；
图4为显示面板扇出区不同位置数据线上信号的时序图；
图5为本公开显示面板一种示例性实施例的结构示意图；
图6为本公开显示面板另一种示例性实施例的结构示意图；
图7为图6中像素驱动电路的分布图；
图8为本公开显示面板另一种示例性实施例的结构示意图；
图9为图8中像素驱动电路的分布图；
图10为本公开显示面板一种示例性实施例中像素驱动电路的电路结构示意图；
图11为图10所示像素驱动电路一种驱动方法中各节点信号的时序图；
图12为本公开显示面板一种示例性实施例的结构版图；
图13图12中第一有源层的结构版图；
图14为图12中第一栅极层的结构版图；
图15为图12中第二栅极层的结构版图；
图16为图12中第一源漏层的结构版图；
图17为图12中第二源漏层的结构版图；
图18为图12中桥接层的结构版图；
图19为图12中电极层的结构版图；
图20为图12中第一有源层、第一栅极层的结构版图；
图21为图12中第一有源层、第一栅极层、第二栅极层的结构版图；
图22为图12中第一有源层、第一栅极层、第二栅极层、第一源漏层的结构版图；
图23为图12中第一有源层、第一栅极层、第二栅极层、第一源漏层、 第二源漏层的结构版图；
图24为图12中第一有源层、第一栅极层、第二栅极层、第一源漏层、第二源漏层、桥接层的结构版图；
图25为图12所示显示面板沿虚线AA剖开的部分剖视图；
图26为本公开显示面板另一种示例性实施例的结构版图；
图27为图26中第一有源层、第一栅极层、第二栅极层、第一源漏层、第二源漏层、桥接层的结构版图；
图28为图26中桥接层的结构版图；
图29为本公开显示面板另一种示例性实施例的结构版图；
图30为图29中第一有源层、第一栅极层、第二栅极层、第一源漏层、第二源漏层、桥接层的结构版图；
图31为图29中桥接层的结构版图；
图32为本公开显示面板一种示例性实施例的结构版图；
图33图32中第一有源层的结构版图；
图34为图32中第一栅极层的结构版图；
图35为图32中第二栅极层的结构版图；
图36为图32中第一源漏层的结构版图；
图37为图32中第二源漏层的结构版图；
图38为图32中桥接层的结构版图；
图39为图32中电极层的结构版图；
图40为图32中第一有源层、第一栅极层的结构版图；
图41为图32中第一有源层、第一栅极层、第二栅极层的结构版图；
图42为图32中第一有源层、第一栅极层、第二栅极层、第一源漏层的结构版图；
图43为图32中第一有源层、第一栅极层、第二栅极层、第一源漏层、第二源漏层的结构版图；
图44为图32中第一有源层、第一栅极层、第二栅极层、第一源漏层、第二源漏层、桥接层的结构版图；
图45为图32所示显示面板沿虚线BB剖开的部分剖视图；
图46为本公开显示面板另一种示例性实施例的结构版图；
图47为图46中电极层的结构版图；
图48为本公开显示面板中像素驱动电路的电路结构示意图；
图49为图48中像素驱动电路一种驱动方法中各节点的时序图；
图50为本公开显示面板一种示例性实施例中的结构版图；
图51为图50中遮挡层的结构版图；
图52为图50中第一有源层的结构版图；
图53为图50中第一栅极层的结构版图；
图54为图50中第二栅极层的结构版图；
图55为图50中第二有源层的结构版图；
图56为图50中第三栅极层的结构版图；
图57为图50中第一源漏层的结构版图；
图58为图50中第二源漏层的结构版图；
图59为图50中电极层的结构版图；
图60为图50中遮挡层、第一有源层的结构版图；
图61为图50中遮挡层、第一有源层、第一栅极层的结构版图；
图62为图50中遮挡层、第一有源层、第一栅极层、第二栅极层的结构版图；
图63为图50中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层的结构版图；
图64为图50中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层的结构版图；
图65为图50中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层、第一源漏层的结构版图；
图66为图50中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层、第一源漏层、第二源漏层的结构版图；
图67为图50所示显示面板沿虚线CC剖开的部分剖视图；
图68为本公开显示面板另一种示例性实施例的结构版图；
图69为图68中第一有源层、第一栅极层、第二栅极层、第一源漏层、第二源漏层、桥接层的结构版图；
图70为图68中桥接层的结构版图；
图71为本公开一种显示面板中源极驱动电路的结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
如图1所示，为相关技术中一种显示面板的结构示意图，该显示面板可以包括红色子像素R、绿色子像素G、蓝色子像素B、数据线Da、源极驱动电路D IC、主柔性电路板MFPC、连接器Cnet。各个子像素可以包括发光单元和用于驱动发光单元的像素驱动电路，发光单元可以为OLED发光单元。数据线Da连接位于同一列的多个子像素，数据线Da用于向与其连接的子像素提供数据信号。源极驱动电路D IC用于向各数据线提供数据信号，此外，源极驱动电路D IC可以通过主柔性电路板MFPC、连接器Cnet连接其他驱动芯片。如图1所示，本示例性实施例提供的显示面板中，同一条数据线需要向红色子像素R和蓝色子像素B分别提供数据信号。
然而，由于红色发光单元对应发光材料的发光效率远高于蓝色发光单元对应发光材料的发光效率。在相同灰阶下，蓝色子像素所需数据信号与红色子像素所需数据信号大小不同，即蓝色子像素对应的数据信号电压区间大于红色子像素对应的数据信号电压区间。例如，当像素驱动电路中驱动晶体管为P型管时，在白画面情况下，蓝色子像素所需数据信号的电压要小于红色子像素所需的数据信号电压。从而，当显示面板沿列方向逐行扫描时，数据线Da上的电压需要在红色子像素所需的数据信号电压和蓝色子像素所需的数据信号电压之间跳变。
当显示面板显示纯红色或纯蓝色画面时，数据线Da上的电压波动更大。例如，如图2所示，为显示面板显示纯红色画面时不同数据线上的时 序图。其中，JI表示图1中奇数列数据线的时序图，OU表示图1中偶数列数据线的时序图。在第一阶段t1，某一奇数列数据线向蓝色子像素提供数据信号，偶数列数据线向绿色子像素提供数据信号；在第二阶段t2，该数据线向红色子像素提供数据信号，偶数列数据线向绿色子像素提供数据信号。其中，在第一阶段t1，蓝色子像素、绿色子像素对应的灰阶为0；在第二阶段t2，红色子像素对应最大灰阶，绿色子像素对应的灰阶为0。因此，当显示面板显示纯红色时，数据线Da上的电压波动较大。同理，当显示面板显示纯蓝色时，数据线Da上的电压波动也较大。
数据线Da上较大的电压波动会导致源极驱动电路D IC的功耗增加。此外，在一些高频或者数据信号延时较大的显示面板中，数据线交替提供红色数据信号和蓝色数据信号时，容易导致数据信号误冲，从而产生色偏。例如，如图3所示，为本公开显示面板另一种示例性实施例的结构示意图。该显示面板可以包括扇出区Fanout，数据线Da在扇出区Fanout扇出并与源极驱动电路D IC连接。在显示面板扇出区中，扇出区两边位置的数据线长度较长，扇出区中间位置的数据线长度较短，从而导致扇出区两边位置数据线上数据信号延时较长，扇出区中间位置数据线的数据信号延时较小。如图4所示，为显示面板扇出区不同位置数据线上信号的时序图。其中，Gout表示像素驱动电路中数据写入晶体管栅极的时序图，Da1表示扇出区两边位置数据线上信号的时序图，Da2表示扇出区中间位置数据线上信号的时序图。数据写入晶体管导通后，数据线可以向像素驱动电路写入数据信号。如图4所示，在数据写入阶段t，数据线向像素驱动电路写入数据信号。根据图4可以看出，扇出区两边位置数据线上信号的下降沿较长，扇出区中间位置数据线上信号的下降沿较短。扇出区两边位置数据线容易向像素驱动电路误冲数据信号。
基于此，本示例性实施例提供一种显示面板，如图5所示，为本公开显示面板一种示例性实施例的结构示意图。该显示面板同样可以包括红色子像素R、绿色子像素G、蓝色子像素B、数据线、源极驱动电路D IC、主柔性电路板MFPC、连接器Cnet。其中，在第一方向X上，红色子像素R、绿色子像素G、蓝色子像素B、绿色子像素G依次分布。该显示面板包括多个子像素列组，每个子像素列组包括依次相邻的第一子像素列ROW1、第 二子像素列ROW2、第三子像素列ROW3、第四子像素列ROW4。其中，第一子像素列ROW1包括在第二方向Y上依次交替分布的红色子像素R、蓝色子像素B；第二子像素列ROW2包括多个在第二方向Y上分布的绿色子像素G；第三子像素列ROW3包括在第二方向Y上依次交替分布的蓝色子像素B、红色子像素R；第四子像素列ROW4包括多个在第二方向Y上分布的绿色子像素G。第一方向X可以和第二方向Y相交，例如，第一方向X可以为行方向，第二方向可以为列方向。相比较于图1所示显示面板，图5所示显示面板中的数据线包括第一数据线Da1、第二数据线Da2、第三数据线Da3、第四数据线Da4，在同一子像素列组中，第一数据线Da1沿第二方向Y逐行交替连接第一子像素列ROW1和第三子像素列ROW3中的红色子像素R，第二数据线Da2沿第二方向Y逐行交替连接第一子像素列ROW1和第三子像素列ROW3中蓝色子像素B。第二子像素列ROW2中的绿色子像素G连接第三数据线Da3，第四子像素列ROW4中的绿色子像素G连接第四数据线Da4。当显示白色时，第一数据线Da1和第二数据线Da2仅需要提供一稳定的电压信号，第一数据线Da1和第二数据线Da2不再需要提供变化的信号。从而该显示面板可以解决上述的源极驱动电路D IC功耗大以及色偏的技术问题。
如图5所示，本示例性实施例中，同一子像素中的像素驱动电路和发光单元相连接。第一数据线Da1和第二数据线Da2可以通过绕线的方式连接不同子像素列中的像素驱动电路。其中，第一数据线Da1和第二数据线Da2在显示面板中衬底基板上正投影相交的位置可以通过其他导电层进行转接，以避免第一数据线Da1和第二数据线Da2短接。
应该理解的是，在其他示例性实施例中，第一数据线Da1连接第一子像素列ROW1和第三子像素列ROW3中的红色子像素R还可以有其他绕线方式；第二数据线Da2连接第一子像素列ROW1和第三子像素列ROW3中的蓝色子像素B还可以有其他绕线方式。只要第一数据线Da1能够连接第一子像素列ROW1和第三子像素列ROW3中的红色子像素R，第二数据线Da2能够连接第一子像素列ROW1和第三子像素列ROW3中的蓝色子像素B，就可以实现上述的技术效果。
此外，在其他示例性实施例中，显示面板中的像素排布结构也可以为 其他方式，只要同一列子像素中包括有不同颜色的子像素，均可以通过同一颜色子像素列连接同一数据线的方式降低源极驱动电路的功耗，以及改善色偏。
需要说明的是，本示例性实施例中，只要同一数据线连接的像素驱动电路驱动同一颜色发光单元即可解决上述的技术问题。因而，在其他示例性实施例中，数据线可以依然连接位于同一列的像素驱动电路，同时通过改变像素驱动电路所连接的发光单元，以实现同一数据线连接的像素驱动电路驱动同一颜色发光单元。
如图6-7所示，图6为本公开显示面板另一种示例性实施例的结构示意图，图7为图6中像素驱动电路的分布图。该显示面板可以包括衬底基板、位于衬底基板上的多个像素驱动电路P11、P12、P13……P24等，以及连接像素驱动电路的多个电极部。如图6-7所示，多个电极部中包括第一电极部R、第二电极部B、第三电极部G，第一电极部R可以用于形成红色发光单元的第一电极；第二电极部B可以用于形成蓝色发光单元的第一电极；第三电极部G可以用于形成绿色发光单元的第一电极。多个像素驱动电路沿第一方向X和第二方向Y阵列分布，同一列像素驱动电路可以连接同一条数据线。在第一方向X上，第一电极部R、第三电极部G、第二电极部B、第三电极部G依次分布。多个电极部可以形成多个电极列，每个电极列包括多个电极部，同一电极列中的多个电极部在衬底基板上的正投影沿第二方向Y间隔分布。多个电极列中可以包括第一电极列ROW1、第二电极列ROW2、第三电极列ROW3、第四电极列ROW4。第一电极列ROW1、第三电极列ROW3、第二电极列ROW2、第四电极列ROW4在衬底基板上的正投影可以在第一方向X上依次交替分布。其中，第一电极列ROW1包括在第二方向Y上依次交替分布的第一电极部R、第二电极部B；第三电极列ROW3包括多个在第二方向Y上分布的第三电极部G；第二电极列ROW2包括在第二方向Y上依次交替分布的第二电极部B、第一电极部R；第四电极列ROW4包括多个在第二方向Y上分布的第三电极部G。
多个所述像素驱动电路在所述衬底基板上的正投影沿所述第一方向X和所述第二方向Y阵列分布，在所述第二方向Y分布的多个所述像素驱动电路形成像素电路列，所述像素电路列包括第一像素电路列PX1和第二像 素电路列Px2。该显示面板还可以包括多个桥接部Bg，多个桥接部Bg中包括第一桥接部Bg1、第二桥接部Bg2。第一桥接部Bg1连接于所述第一像素电路列PX1中像素驱动电路和所述第二电极列ROW2中第一电极部R之间；第二桥接部Bg2连接于所述第二像素电路列PX2中像素驱动电路和所述第一电极列ROW1中第二电极部之间。
如图6-7所示，像素驱动电路P21可以通过第一桥接部Bg1连接第二电极列ROW2中的第一电极部R，像素驱动电路P23可以通过第二桥接部Bg2连接第一电极列ROW1中的第二电极部B。从而该显示面板可以实现同一数据线用于驱动同一颜色的发光单元。
如图8-9所示，图8为本公开显示面板另一种示例性实施例的结构示意图，图9为图8中像素驱动电路的分布图。像素驱动电路P13可以通过桥接部Bg连接第一电极列ROW1中的第一电极部R，像素驱动电路P11也可以通过桥接部Bg连接第二电极列ROW2的第二电极部B。该设置同样可以实现同一数据线连接的像素驱动电路连接同一颜色的发光单元。
本示例性实施例中，电极部可以位于电极层，桥接部Bg可以位于电极层和衬底基板之间的任意一导电层，此外，桥接部Bg也可以位于电极层。桥接部Bg可以用于连接位于同一行数的像素驱动电路和电极部。
如图10所示，为本公开显示面板一种示例性实施例中像素驱动电路的电路结构示意图。该像素驱动电路可以包括：第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、电容C。其中，第一晶体管T1的第一极连接第一初始信号端Vinit1，第二极连接节点N，栅极连接第一复位信号端Re1；第二晶体管T2第一极连接驱动晶体管T3的栅极，第二极连接驱动晶体管T3的第二极；栅极连接第一栅极驱动信号端G1；驱动晶体管T3的栅极连接节点N；第四晶体管T4的第一极连接数据信号端Da，第二极连接驱动晶体管T3的第一极，栅极连接第一栅极驱动信号端G1；第五晶体管T5的第一极连接第一电源端VDD，第二极连接驱动晶体管T3的第一极，栅极连接使能信号端EM；第六晶体管T6第一极连接驱动晶体管T3的第二极，栅极连接使能信号端EM；第七晶体管T7的第一极连接第二初始信号端Vinit2，第二极连接第六晶体管T6的第二极，栅极连接第二复位信号端Re2。电容 C的第一电极连接驱动晶体管T3的栅极，电容C的第二电极连接第一电源端VDD。该像素驱动电路可以连接一发光单元OLED，该像素驱动电路用于驱动该发光单元OLED发光，发光单元OLED的第一电极可以连接第六晶体管T6的第二极，发光单元OLED的第二电极可以连接第二电源端VSS。其中，第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以均为P型晶体管。
如图11所示，为图10所示像素驱动电路一种驱动方法中各节点信号的时序图。其中，G1表示第一栅极驱动信号端G1信号的时序，Re1表示第一复位信号端Re1信号的时序，Re2表示第二复位信号端Re2信号的时序，EM表示使能信号端EM信号的时序，Da表示数据信号端Da信号的时序。该像素驱动电路的驱动方法可以包括复位阶段t1、数据写入阶段t2，发光阶段t3。在复位阶段t1：第一复位信号端Re1输出低电平信号，第一晶体管T1导通，第一初始信号端Vinit1向节点N输入第一初始信号。在数据写入阶段t2：第二复位信号端Re2、第一栅极驱动信号端G1输出低电平信号，第四晶体管T4、第二晶体管T2、第七晶体管T7导通，同时数据信号端Da输出数据信号以向节点N写入电压Vdata+Vth，其中Vdata为数据信号的电压，Vth为驱动晶体管T3的阈值电压，第二初始信号端Vinit2向第六晶体管T6的第二极输入第二初始信号。在发光阶段t3：使能信号端EM输出低电平信号，第六晶体管T6、第五晶体管T5导通，驱动晶体管T3在节点N的电压Vdata+Vth作用下驱动发光单元发光。本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth) 2。其中，μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电压。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。
本示例性实施例还提供另一种显示面板，该显示面板可以包括依次层叠设置的衬底基板、第一有源层、第一栅极层、第二栅极层、第一源漏层、第二源漏层、桥接层、电极层，上述结构层之间设置有绝缘层。如图12-24所示，图12为本公开显示面板一种示例性实施例的结构版图，图13图12中第一有源层的结构版图，图14为图12中第一栅极层的结构版图，图15 为图12中第二栅极层的结构版图，图16为图12中第一源漏层的结构版图，图17为图12中第二源漏层的结构版图，图18为图12中桥接层的结构版图，图19为图12中电极层的结构版图，图20为图12中第一有源层、第一栅极层的结构版图，图21为图12中第一有源层、第一栅极层、第二栅极层的结构版图，图22为图12中第一有源层、第一栅极层、第二栅极层、第一源漏层的结构版图，图23为图12中第一有源层、第一栅极层、第二栅极层、第一源漏层、第二源漏层的结构版图，图24为图12中第一有源层、第一栅极层、第二栅极层、第一源漏层、第二源漏层、桥接层的结构版图。
如图12、13、20所示，第一有源层可以包括第一有源部71、第二有源部72、第三有源部73、第四有源部74、第五有源部75、第六有源部76、第七有源部77。其中，第一有源部71用于形成第一晶体管T1的沟道区，第二有源部72用于形成第二晶体管T2的沟道区，第三有源部73用于形成驱动晶体管T3的沟道区，第四有源部74用于形成第四晶体管T4的沟道区，第五有源部75用于形成第五晶体管T5的沟道区，第六有源部76用于形成第六晶体管T6的沟道区，第七有源部77用于形成第七晶体管T7的沟道区。其中，第一有源部71包括第四子有源部714和第五子有源部715，第二有源部72包括第一子有源部721和第二子有源部722。第一有源层还可以包括连接于第四子有源部714和第五子有源部715之间的第六子有源部716、连接于第一子有源部721和第二子有源部722之间的第三子有源部723、连接于第二有源部72和第一有源部71之间的第八有源部78、连接于第四有源部74远离第三有源部73一侧的第九有源部79、连接于第一有源部71远离第二有源部72一侧的第十有源部710、连接于第六有源部76和第七有源部77之间的第十一有源部711、连接于第五有源部75远离第三有源部73一侧的第十二有源部712、连接于第七有源部77远离第六有源部76一侧的第十三有源部713。第一有源层可以由多晶硅材料形成，相应的，第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型的低温多晶硅薄膜晶体管。
如图12、14、20所示，第一栅极层可以包括：第一复位信号线Re1、 第二复位信号线Re2、第一栅线G1、使能信号线EM、第一导电部11。其中，第一复位信号线Re1用于提供图10中的第一复位信号端，第二复位信号线Re2用于提供图10中的第二复位信号端，第一栅线G1用于提供图10中的第一栅极驱动信号端，使能信号线EM用于提供图10中的使能信号端。第一复位信号线Re1在衬底基板上的正投影可以沿第一方向X延伸且覆盖第一有源部71在衬底基板上的正投影，第一复位信号线Re1的部分结构用于形成第一晶体管T1的栅极。第二复位信号线Re2在衬底基板上的正投影可以沿第一方向X延伸且覆盖第七有源部77在衬底基板上的正投影，第二复位信号线Re2的部分结构用于形成第七晶体管T7的栅极。使能信号线EM在衬底基板上的正投影可以沿第一方向X延伸且覆盖第五有源部75在衬底基板上的正投影、第六有源部76在衬底基板上的正投影，使能信号线EM的部分结构用于形成第五晶体管T5的栅极，使能信号线EM的另外部分结构用于形成第六晶体管T6的栅极。第一栅线G1在衬底基板上的正投影沿第一方向X延伸且覆盖第二有源部72在衬底基板上的正投影、第四有源部74在衬底基板上的正投影，第一栅线G1的部分结构用于形成第二晶体管T2的栅极，第一栅线G1的另外部分结构用于形成第四晶体管T4的栅极。第一导电部11在衬底基板上的正投影覆盖第三有源部73在衬底基板上的正投影，第一导电部11用于形成驱动晶体管T3的栅极。第一导电部11还可以复用为电容C的第一电极。其中，第一导电部11在衬底基板上的正投影可以位于第一栅线G1在衬底基板上的正投影和使能信号线EM在衬底基板上的正投影之间。第一复位信号线Re1在衬底基板上的正投影可以位于第一栅线G1在衬底基板上的正投影远离第一导电部11在衬底基板上的正投影的一侧。第二复位信号线Re2在衬底基板上的正投影可以位于使能信号线EM在衬底基板上的正投影远离第一导电部11在衬底基板上的正投影的一侧。在相邻行像素驱动电路中，上一行像素驱动电路中的所述第二复位信号线Re2可以共用为本行像素驱动电路中的所述第一复位信号线Re1，该设置可以减小像素驱动电路在第二方向Y上的尺寸。此外，该显示面板可以利用第一栅极层为掩膜对第一有源层进行导体化处理，即第一有源层中被第一栅极层覆盖的区域可以形成晶体管的沟道区，第一有源层中未被第一栅极层覆盖的区域形成导体结构。
如图12、15、21所示，第二栅极层可以包括第一初始信号线Vinit1、第二初始信号线Vinit2、第二导电部22、第三导电部23。第一初始信号线Vinit1可以用于提供图10中的第一初始信号端，第二初始信号线Vinit2可以用于提供图10中的第二初始信号端。第一初始信号线Vinit1在衬底基板上的正投影、第二初始信号线Vinit2在衬底基板上的正投影均可以沿第一方向X延伸。第三导电部23在衬底基板上的正投影可以与第一导电部11在衬底基板上的正投影至少部分交叠，第三导电部23可以用于形成电容C的第二电极，其中，在第一方向X上分布的多个第三导电部23可以依次连接。在相邻像素驱动电路行中，下一行像素驱动电路中的所述第一初始信号线Vinit1在所述衬底基板上的正投影可以位于本行像素驱动电路中所述第二初始信号线Vinit2在所述衬底基板上的正投影和本行像素驱动电路中所述第二复位信号线Re2在所述衬底基板上的正投影之间，该设置可以进一步减小像素驱动电路在第二方向上的尺寸。第二导电部22可以包括的第三子导电部223，第三子导电部223在衬底基板上的正投影与第三子有源部723在衬底基板上的正投影至少部分交叠，第二导电部22可以连接一稳定电压源，第三子导电部223可以对第三子有源部723起到稳压作用，从而可以改善由于第三子有源部723电压变化产生向第二晶体管T2源漏极漏电的问题。第一初始信号线Vinit1在衬底基板上的正投影可以与本行像素驱动电路中第六子有源部716在衬底基板上的正投影至少部分交叠，第一初始信号线Vinit1可以对第六子有源部716起到稳压作用，从而可以改善由于第六子有源部716电压变化产生向第一晶体管T1源漏极漏电的问题。
如图12、16、22所示，第一源漏层可以包括第一电源线VDD、第五桥接部35、第六桥接部36、第七桥接部37、第八桥接部38、第九桥接部39。其中，第一电源线VDD可以用于提供图10所示像素驱动电路中的第一电源端。第一电源线VDD在衬底基板上的正投影可以沿第二方向Y延伸，第一电源线VDD可以通过过孔H连接第二导电部22，以向第二导电部22提供稳定电压源，本示例性实施例中，黑色方块表示过孔的位置。应该理解的是，在其他示例性实施例中，还可以通过其他信号线向第二导电部22提供稳定电压源，例如，可以通过第一初始信号线Vinit1、第二初始信号 线Vinit2向第二导电部22提供稳定电压源。第一电源线VDD还可以通过过孔连接第三导电部23以连接电容的第二电极和第一电源端。第一电源线VDD可以和在第一方向X上连接的第三导电部23形成网格结构，该设置可以降低由于第一电源线VDD自身电阻降造成的压降。第一电源线VDD还可以通过过孔连接第十二有源部712，以连接第五晶体管T5的第一极和第一电源端。第五桥接部35可以分别通过过孔连接第一导电部11和第八有源部78，以连接驱动晶体管T3的栅极和第一晶体管T1的第二极、第二晶体管T2的第一极。如图15所示，第三导电部23上可以设置有开口231，连接于第五桥接部35和第一导电部11的过孔在衬底基板上的正投影可以位于开口231在衬底基板上的正投影以内，以避免该过孔与第三导电部23连接。第六桥接部36可以通过过孔连接第九有源部79，以连接第四晶体管T4的第一极。第七桥接部37可以分别通过过孔连接第十三有源部713和第二初始信号线Vinit2，以连接第七晶体管的第一极和第二初始信号端。第八桥接部38可以分别通过过孔连接第十有源部710和第一初始信号线Vinit1，以连接第一晶体管T1的第一极和第一初始信号端。第九桥接部39可以通过过孔连接第十一有源部711，以连接第六晶体管T6的第二极和第七晶体管T7的第二极。如图12、15、16、22所示，第二导电部22还可以包括第一子导电部221，第一子导电部221连接于第三子导电部223，第一子导电部221在衬底基板上的正投影可以沿第一方向X延伸，且位于第五桥接部35在衬底基板上的正投影和所述第一复位信号线Re1在衬底基板上的正投影之间，即第一子导电部221在衬底基板上的正投影在第二方向Y上无限移动所覆盖区域和第五桥接部35在衬底基板上的正投影在第二方向Y上无限移动所覆盖区域至少部分相交，第一子导电部221可以屏蔽第一复位信号线Re1对第五桥接部35的噪音影响，从而提高图10所示像素驱动电路中节点N电压的稳定性。本示例性实施例中，第一子导电部221在衬底基板上的正投影在第二方向Y上无限移动所覆盖区域可以覆盖第五桥接部35在衬底基板上的正投影在第二方向Y上无限移动所覆盖区域。
如图12、17、23所示，第二源漏层可以包括：数据线Da、电源连接线4VDD、第十桥接部410。数据线Da用于提供图10所示像素驱动电路中 的数据信号端。每列像素驱动电路对应设置一条数据线，数据线连接同一列像素驱动电路中的第四晶体管的第一极。电源连接线4VDD在衬底基板上的正投影、数据线Da在衬底基板上的正投影均可以沿第二方向Y延伸。电源连接线4VDD可以通过过孔连接第一电源线VDD，该双电源线设置可以进一步降低电源线的自身电阻。数据线Da可以通过过孔连接第六桥接部36，以连接第四晶体管T4的第一极和数据信号端。如图23所示，第一电源线VDD在衬底基板上的正投影可以位于数据线Da在衬底基板上的正投影和第五桥接部35在衬底基板上的正投影之间。第一电源线VDD可以屏蔽本列像素驱动电路中数据线Da对本列像素驱动电路中第五桥接部35的噪音影响。第十桥接部410可以通过过孔连接第九桥接部39，以连接第六晶体管的第二极。
如图12、15、16、23所示，第二导电部22还可以包括第二子导电部222，第二子导电部222连接于第一子导电部221远离第三子导电部223的一侧，第二子导电部222在衬底基板上的正投影可以沿第二方向Y延伸，且位于第五桥接部35在衬底基板上的正投影和所述数据线Da在衬底基板上的正投影之间，即第二子导电部222在衬底基板上的正投影在第一方向X上无限移动所覆盖区域和第五桥接部35在衬底基板上的正投影在第一方向X上无限移动所覆盖区域至少部分相交，第二子导电部222可以屏蔽数据线Da对第五桥接部35的噪音影响。
如图12、18、24所示，桥接层可以包括多个桥接部Bg，其中，多个桥接部中包括第一桥接部Bg1和第二桥接部Bg2。第一桥接部Bg1可以通过过孔连接第一列第二行像素驱动电路中的第十桥接部410。第二桥接部Bg2可以通过过孔连接第三列第二行像素驱动电路中的第十桥接部410。
如图12、19所示，像素电极层可以包括多个电极部：第一电极部R、第三电极部G、第二电极部B，各个电极部可以通过过孔连接桥接部Bg以连接第六晶体管的第二极。同一电极行中，第一电极部R、第三电极部G、第二电极部B、第三电极部G在第一方向X上依次交替分布。多个电极部形成多个电极列，多个电极列包括依次相邻的第一电极列ROW1、第三电极列ROW3、第二电极列ROW2、第四电极列ROW4中，第一电极列ROW1包括在第二方向Y上依次交替分布的第一电极部R、第二电极部B；第三电极 列ROW3包括多个在第二方向Y上分布的第三电极部G；第二电极列ROW2包括在第二方向Y上依次交替分布的第二电极部B、第一电极部R；第四电极列ROW4包括多个在第二方向Y上分布的第三电极部G。位于同一电极列相邻电极行的两个第三电极部G在所述衬底基板上的正投影在第二方向上的最小距离S1大于所述第一电极部R在所述衬底基板上的正投影在第二方向的尺寸S2，或者大于所述第二电极部B所述衬底基板上的正投影在第二方向的尺寸S3。其中，该显示面板还包括包括位于电极层背离衬底基板一侧的像素定义层，像素定义层上形成有用于形成发光单元的像素开口。第一电极部R在衬底基板上的正投影和像素定义层上与其对应的开口在衬底基板上的正投影重合，第三电极部G在衬底基板上的正投影和像素定义层上与其对应的开口在衬底基板上的正投影重合，第二电极部B在衬底基板上的正投影和像素定义层上与其对应的开口在衬底基板上的正投影重合。
如图12、19所示，第一电极列中的第二电极部B可以通过过孔连接第二桥接部Bg2，以连接第三列第二行中的像素驱动电路。第二电极列中的第一电极部R可以通过过孔连接第一桥接部Bg1，以连接第一列第二行中的像素驱动电路。该设置可以使得同一数据线所连接像素驱动电路驱动同一种颜色的发光单元。
如图12、18、24所示，第一桥接部Bg1包括第一延伸部Bg11，第一延伸部Bg11在衬底基板上的正投影沿第一方向X延伸，且和相邻下一行像素驱动电路中第一初始信号线Vinit1在衬底基板上的正投影至少部分交叠，例如，第一延伸部Bg11在衬底基板上的正投影可以位于相邻下一行像素驱动电路中第一初始信号线Vinit1在衬底基板上的正投影上；第二桥接部Bg2包括第二延伸部Bg22，第二延伸部Bg22在衬底基板上的正投影沿第一方向X延伸，且和本行像素驱动电路中第二初始信号线Vinit2在衬底基板上的正投影至少部分交叠，例如，第二延伸部Bg22在衬底基板上的正投影可以位于本行像素驱动电路中第二初始信号线Vinit2在衬底基板上的正投影上。由于第一初始信号线和第二初始信号线输出稳定电压信号，从而该设置可以降低其他交流信号对桥接部的耦合作用，提高桥接部上电压的稳定性。应该理解的是，第一延伸部Bg11在所述衬底基板 上的正投影可以与任意输出稳定电压信号的第一信号线在所述衬底基板上的正投影至少部分交叠；所述第二延伸部Bg22在所述衬底基板上的正投影可以与任意输出稳定电压信号的第二信号线在所述衬底基板上的正投影至少部分交叠。本示例性实施例中，第一信号线可以包括上述的第一初始信号线；第二信号线可以包括上述的第二初始信号线。在其他示例性实施例中，第一信号线还可以包括：图10中第一电源端VDD的等电位信号线、第二电源端VSS的等电位信号线等信号线、第二初始信号端的等电位线；第二信号线还可以包括：图10中第一电源端VDD的等电位信号线、第二电源端VSS的等电位信号线、第一初始信号端的等电位信号线。
如图12、19所示，电极层还可以包括多个增设部，多个增设部包括：第一增设部E1、第二增设部E2、第三增设部E3。其中，第一增设部E1和第二增设部E2连接于第一电极部R，第三增设部E3连接于第二电极部B。第一增设部E1在衬底基板上的正投影和与其位于同一行列数的第二有源部72在衬底基板上的正投影至少部分交叠，第一增设部E1可以用于对第二晶体管进行遮光，以降低光照对第二晶体管输出特性的影响；第二增设部E2在衬底基板上的正投影和与其位于同一行数相邻列数的第二有源部在衬底基板上的正投影至少部分交叠，第二增设部E2同样用于对第二晶体管进行遮光。第三增设部E3在衬底基板上的正投影和与其位于同一行数相邻列数的第二有源部在衬底基板上的正投影至少部分交叠，第三增设部E3同样用于对第二晶体管进行遮光。其中，各个增设部的行列数和与其连接的电极部的行列数相同，第二有源部的行列数和其所在的像素驱动电路的行列数相同。
需要说明的是，如图12、22、23、24所示，画于第一源漏层背离衬底基板一侧的黑色方块表示第一源漏层连接面向衬底基板一侧的其他层级的过孔；画于第二源漏层背离衬底基板一侧的黑色方块表示第二源漏层连接面向衬底基板一侧的其他层级的过孔；画于桥接层背离衬底基板一侧的黑色方块表示桥接层连接面向衬底基板一侧的其他层级的过孔；画于电极层背离衬底基板一侧的黑色方块表示电极层连接面向衬底基板一侧的其他层级的过孔。该黑色方块仅表示过孔的位置，不同位置黑色方块所表示的不同过孔可以贯穿于不同绝缘层。
如图25所示，为图12所示显示面板沿虚线AA剖开的部分剖视图。该显示面板还可以包括第一绝缘层91、第二绝缘层92、介电层93、钝化层94、第一平坦层95、第三绝缘层96、第二平坦层97。衬底基板90、有源层、第一绝缘层91、第一栅极层、第二绝缘层92、第二栅极层、介电层93、第一源漏层、钝化层94、第一平坦层95、第二源漏层、第三绝缘层96、桥接层、第二平坦层97、电极层可以依次层叠设置。第一绝缘层91、第二绝缘层92、第三绝缘层96可以氧化硅层，介电层93可以为氮化硅层，钝化层94的材料可以为氧化硅、氮化硅等，第一平坦层95、第二平坦层97的材料可以为有机材料，例如聚酰亚胺(PI)、聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)、硅-玻璃键合结构(SOG)等材料。衬底基板90可以包括依次层叠设置的玻璃基板、阻挡层、聚酰亚胺层，阻挡层可以为无机材料。第一栅极层、第二栅极层的材料可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等导电层。第一源漏层、第二源漏层的材料可以包括金属材料，例如可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层等导电层。桥接层可以为氧化铟锡层等导电层。
如图26-28所示，图26为本公开显示面板另一种示例性实施例的结构版图，图27为图26中第一有源层、第一栅极层、第二栅极层、第一源漏层、第二源漏层、桥接层的结构版图，图28为图26中桥接层的结构版图。
图26所示的显示面板与图12所示的显示面板不同在于：在图26所示的显示面板中，第二桥接部Bg2可以包括第二延伸部Bg22和第三延伸部Bg23，第二延伸部Bg22在衬底基板上的正投影沿第一方向X延伸且和本行像素驱动电路中第一初始信号线Vinit1在衬底基板上的正投影至少部分交叠，第三延伸部Bg23在衬底基板上的正投影沿第二方向Y延伸且和本列像素驱动电路中第一电源线VDD在衬底基板上的正投影至少部分交叠，例如，第二延伸部Bg22在衬底基板上的正投影可以位于第一初始信号线Vinit1在衬底基板上的正投影上，第三延伸部Bg23在衬底基板上的正投影可以位于第一电源线VDD在衬底基板上的正投影上。该设置同样可以降低其他交流信号对桥接部的噪音影响。应该理解的是，第三延伸部 Bg23在衬底基板上的正投影可以和任意输出稳定电压信号的第三信号线在衬底基板上的正投影交叠。本示例性实施例中，第三信号线可以包括上述的第一电源线VDD，在其他示例性实施例中，第三信号线还可以包括：图10中第二电源端的等电位信号线、第一初始信号端的等电位信号线、第二初始信号端的等电位信号线等。此外，本示例性实施例中，第一桥接部Bg1和第二桥接部Bg2在衬底基板上的正投影分别和不同第一初始信号线Vinit1在衬底基板上的正投影交叠，从而该设置可以应用于单初始信号线或集成度较高的显示面板中。其中，单初始信号线的显示面板是指，该显示面板中一行像素驱动电路对应设置一条初始信号线，即第一晶体管T1和第七晶体管T7连接同一初始信号线。
如图29-31所示，图29为本公开显示面板另一种示例性实施例的结构版图，图30为图29中第一有源层、第一栅极层、第二栅极层、第一源漏层、第二源漏层、桥接层的结构版图，图31为图29中桥接层的结构版图。
图29所示的显示面板与图12所示的显示面板不同在于：在图29所示显示面板中，多个桥接部Bg还包括第三桥接部Bg3和第四桥接部Bg4。第三桥接部Bg3可以用于连接位于相同行列数的第一电极部R和像素驱动电路，第四桥接部Bg4可以用于连接位于相同行列数的第二电极部B和像素驱动电路。第三桥接部包括第四延伸部Bg34，第四延伸部Bg34在衬底基板上的正投影可以和电源连接线4VDD在衬底基板上的正投影交叠。第四桥接部Bg4包括第五延伸部Bg45，第五延伸部Bg45在衬底基板上的正投影可以和电源连接线4VDD在衬底基板上的正投影交叠。该设置可以通过第四延伸部Bg34对第三桥接部Bg3的寄生电容进行补偿，通过第五延伸部Bg45对第四桥接部Bg4的寄生电容进行补偿，从而使得第一桥接部Bg1和第三桥接部Bg3的寄生电容接近或一致，第二桥接部Bg2和第四桥接部Bg4的寄生电容接近或一致，以解决不同电极部等电位点寄生电容不均一的问题，进而提高显示面板显示的均一性。其中，第一桥接部Bg1和其他结构之间的寄生电容为C1，第二桥接部Bg2和其他结构之间的寄生电容为C2，第三桥接部Bg3和其他结构之间的寄生电容为C3，第四桥接部Bg4和其他结构之间的寄生电容为C4。其中，C1＝N1*C3，C2＝N2*C4，N1 大于等于70％且小于等于130％，例如，N1可以等于70％、80％、90％、95％、100％、105％、110％、120％、130％等，N2可以大于等于70％且小于等于130％，例如，N2可以等于70％、80％、90％、95％、100％、105％、110％、120％、130％等。
本示例性实施例还提供另一种显示面板，该显示面板可以包括依次层叠设置的衬底基板、第一有源层、第一栅极层、第二栅极层、第一源漏层、第二源漏层、桥接层、电极层，上述结构层之间设置有绝缘层。如图32-44所示，图32为本公开显示面板一种示例性实施例的结构版图，图33图32中第一有源层的结构版图，图34为图32中第一栅极层的结构版图，图35为图32中第二栅极层的结构版图，图36为图32中第一源漏层的结构版图，图37为图32中第二源漏层的结构版图，图38为图32中桥接层的结构版图，图39为图32中电极层的结构版图，图40为图32中第一有源层、第一栅极层的结构版图，图41为图32中第一有源层、第一栅极层、第二栅极层的结构版图，图42为图32中第一有源层、第一栅极层、第二栅极层、第一源漏层的结构版图，图43为图32中第一有源层、第一栅极层、第二栅极层、第一源漏层、第二源漏层的结构版图，图44为图32中第一有源层、第一栅极层、第二栅极层、第一源漏层、第二源漏层、桥接层的结构版图。
如图32、33、40所示，第一有源层可以包括第一有源部71、第二有源部72、第三有源部73、第四有源部74、第五有源部75、第六有源部76、第七有源部77。其中，第一有源部71用于形成第一晶体管T1的沟道区，第二有源部72用于形成第二晶体管T2的沟道区，第三有源部73用于形成驱动晶体管T3的沟道区，第四有源部74用于形成第四晶体管T4的沟道区，第五有源部75用于形成第五晶体管T5的沟道区，第六有源部76用于形成第六晶体管T6的沟道区，第七有源部77用于形成第七晶体管T7的沟道区。其中，第一有源部71包括第四子有源部714和第五子有源部715，第二有源部72包括第一子有源部721和第二子有源部722。第一有源层还可以包括连接于第四子有源部714和第五子有源部715之间的第六子有源部716、连接于第一子有源部721和第二子有源部722之间的第三子有源部723、连接于第二有源部72和第一有源部71之间的第八有源部 78、连接于第四有源部74远离第三有源部73一侧的第九有源部79、连接于第一有源部71远离第二有源部72一侧的第十有源部710、连接于第六有源部76和第七有源部77之间的第十一有源部711、连接于第五有源部75远离第三有源部73一侧的第十二有源部712、连接于第七有源部77远离第六有源部76一侧的第十三有源部713。第一有源层可以由多晶硅材料形成，相应的，第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型的低温多晶硅薄膜晶体管。
如图32、34、40所示，第一栅极层可以包括：第一复位信号线Re1、第二复位信号线Re2、第一栅线G1、使能信号线EM、第一导电部11。其中，第一复位信号线Re1用于提供图10中的第一复位信号端，第二复位信号线Re2用于提供图10中的第二复位信号端，第一栅线G1用于提供图10中的第一栅极驱动信号端，使能信号线EM用于提供图10中的使能信号端。第一复位信号线Re1在衬底基板上的正投影可以沿第一方向X延伸且覆盖第一有源部71在衬底基板上的正投影，第一复位信号线Re1的部分结构用于形成第一晶体管T1的栅极。第二复位信号线Re2在衬底基板上的正投影可以沿第一方向X延伸且覆盖第七有源部77在衬底基板上的正投影，第二复位信号线Re2的部分结构用于形成第七晶体管T7的栅极。使能信号线EM在衬底基板上的正投影可以沿第一方向X延伸且覆盖第五有源部75在衬底基板上的正投影、第六有源部76在衬底基板上的正投影，使能信号线EM的部分结构用于形成第五晶体管T5的栅极，使能信号线EM的另外部分结构用于形成第六晶体管T6的栅极。第一栅线G1在衬底基板上的正投影沿第一方向X延伸且覆盖第二有源部72在衬底基板上的正投影、第四有源部74在衬底基板上的正投影，第一栅线G1的部分结构用于形成第二晶体管T2的栅极，第一栅线G1的另外部分结构用于形成第四晶体管T4的栅极。第一导电部11在衬底基板上的正投影覆盖第三有源部73在衬底基板上的正投影，第一导电部11用于形成驱动晶体管T3的栅极。第一导电部11还可以复用为电容C的第一电极。其中，第一导电部11在衬底基板上的正投影可以位于第一栅线G1在衬底基板上的正投影和使能信号线EM在衬底基板上的正投影之间。第一复位信号线Re1在衬底基板 上的正投影可以位于第一栅线G1在衬底基板上的正投影远离第一导电部11在衬底基板上的正投影的一侧。第二复位信号线Re2在衬底基板上的正投影可以位于使能信号线EM在衬底基板上的正投影远离第一导电部11在衬底基板上的正投影的一侧。在相邻行像素驱动电路中，上一行像素驱动电路中的所述第二复位信号线Re2可以共用为本行像素驱动电路中的所述第一复位信号线Re1，该设置可以减小像素驱动电路在第二方向Y上的尺寸。此外，该显示面板可以利用第一栅极层为掩膜对第一有源层进行导体化处理，即第一有源层中被第一栅极层覆盖的区域可以形成晶体管的沟道区，第一有源层中未被第一栅极层覆盖的区域形成导体结构。
如图32、35、41所示，第二栅极层可以包括第一初始信号线Vinit1、第二初始信号线Vinit2、第二导电部22、第三导电部23。第一初始信号线Vinit1可以用于提供图10中的第一初始信号端，第二初始信号线Vinit2可以用于提供图10中的第二初始信号端。第一初始信号线Vinit1在衬底基板上的正投影、第二初始信号线Vinit2在衬底基板上的正投影均可以沿第一方向X延伸。第三导电部23在衬底基板上的正投影可以与第一导电部11在衬底基板上的正投影至少部分交叠，第三导电部23可以用于形成电容C的第二电极，其中，在第一方向X上分布的多个第三导电部23可以依次连接。在相邻行像素驱动电路中，下一行像素驱动电路中的所述第一初始信号线Vinit1在所述衬底基板上的正投影可以位于本行像素驱动电路中所述使能信号线EM在所述衬底基板上的正投影和本行像素驱动电路中所述第二复位信号线Re2在所述衬底基板上的正投影之间，该设置可以进一步减小像素驱动电路在第二方向上的尺寸。第二导电部22可以包括的第三子导电部223，第三子导电部223在衬底基板上的正投影与第三子有源部723在衬底基板上的正投影至少部分交叠，第二导电部22可以连接一稳定电压源，第三子导电部223可以对第三子有源部723起到稳压作用，从而可以改善由于第三子有源部723电压变化产生向第二晶体管T2源漏极漏电的问题。第一初始信号线Vinit1在衬底基板上的正投影可以与第六子有源部716在衬底基板上的正投影至少部分交叠，第一初始信号线Vinit1可以对第六子有源部716起到稳压作用，从而可以改善由于第六子有源部716电压变化产生向第一晶体管T1源漏极漏电的问题。
如图32、36、42所示，第一源漏层可以包括第一电源线VDD、数据线Da、第一初始连接线4Vinit1、第五桥接部35、第七桥接部37、第九桥接部39。其中，第一电源线VDD可以用于提供图10所示像素驱动电路中的第一电源端。第一电源线VDD在衬底基板上的正投影可以沿第二方向Y延伸，第一电源线VDD可以通过过孔连接第二导电部22，以向第二导电部22提供稳定电压源。应该理解的是，在其他示例性实施例中，还可以通过其他信号线向第二导电部22提供稳定电压源，例如，可以通过第一初始信号线Vinit1、第二初始信号线Vinit2向第二导电部22提供稳定电压源。第一电源线VDD还可以通过过孔连接第三导电部23以连接电容的第二电极和第一电源端。第一电源线VDD可以和在第一方向X上连接的第三导电部23形成网格结构，从而可以降低由于第一电源线VDD自身电阻降造成的压降。第一电源线VDD还可以通过过孔连接第十二有源部712，以连接第五晶体管T5的第一极和第二电源端。数据线Da用于提供图10所示像素驱动电路中的数据信号端。每列像素驱动电路对应设置一条数据线，数据线连接同一列像素驱动电路中的第四晶体管的第一极。数据线Da在衬底基板上的正投影均可以沿第二方向Y延伸，数据线Da可以通过过孔连接第九有源部79，以连接第四晶体管T4的第一极和数据信号端。第一初始连接线4Vinit1在衬底基板上的正投影沿第二方向Y延伸，第一初始连接线4Vinit1通过过孔连接与其在衬底基板上正投影相交的第一初始信号线Vinit1，第一初始连接线4Vinit1和第一初始信号线Vinit1可以形成网格结构，从而可以降低第一初始信号线Vinit1的自身电阻。第一初始连接线4Vinit1还通过过孔连接第十有源部710以连接第一初始信号端和第一晶体管的第一极。第五桥接部35可以分别通过过孔连接第一导电部11和第八有源部78，以连接驱动晶体管T3的栅极和第一晶体管T1的第二极、第二晶体管T2的第一极。如图35所示，第三导电部23上可以设置有开口231，连接于第五桥接部35和第一导电部11的过孔在衬底基板上的正投影可以位于开口231在衬底基板上的正投影以内，以避免该过孔与第三导电部23连接。第七桥接部37可以分别通过过孔连接第十三有源部713和第二初始信号线Vinit2，以连接第七晶体管的第一极和第二初始信号端。第九桥接部39可以通过过孔连接第十一有源部711，以连接第六 晶体管T6的第二极和第七晶体管T7的第二极。
如图32、35、36、42所示，第二导电部22还可以包括第一子导电部221，第一子导电部221连接于第三子导电部223，第一子导电部221在衬底基板上的正投影可以沿第一方向X延伸，且位于第五桥接部35在衬底基板上的正投影和所述第一复位信号线Re1在衬底基板上的正投影之间，即第一子导电部221在衬底基板上的正投影在第二方向Y上无限移动所覆盖区域和第五桥接部35在衬底基板上的正投影在第二方向Y上无限移动所覆盖区域至少部分相交，第一子导电部221可以屏蔽第一复位信号线Re1对第五桥接部35的噪音影响，从而提高图10所示像素驱动电路中节点N电压的稳定性。本示例性实施例中，第一子导电部221在衬底基板上的正投影在第二方向Y上无限移动所覆盖区域可以覆盖第五桥接部35在衬底基板上的正投影在第二方向Y上无限移动所覆盖区域。第二导电部22还可以包括第二子导电部222，第二子导电部222连接于第一子导电部221远离第三子导电部223的一侧，第二子导电部222在衬底基板上的正投影可以沿第二方向Y延伸，且位于第五桥接部35在衬底基板上的正投影和所述数据线Da在衬底基板上的正投影之间，即第二子导电部222在衬底基板上的正投影在第一方向X上无限移动所覆盖区域和第五桥接部35在衬底基板上的正投影在第一方向X上无限移动所覆盖区域至少部分相交，第二子导电部222可以屏蔽数据线Da对第五桥接部35的噪音影响。相邻上一行像素驱动电路中第二初始信号线Vinit2在衬底基板上的正投影可以位于本行像素驱动电路中第一复位信号线Re1在衬底基板上的正投影和第五桥接部35在衬底基板上的正投影之间，第二初始信号线Vinit2同样可以屏蔽第一复位信号线Re1对第五桥接部35的噪音影响。
如图32、37、43所示，第二源漏层可以包括：虚拟数据线Dmy、第十桥接部410。该显示面板的扇出区可以位于显示区，扇出区中可以设置有位于第二源漏层的数据桥接线，以便数据线在局部区域扇出。虚拟数据线Dmy用于模拟扇出区中数据桥接线的遮挡状态以及寄生电容，以便整个显示区显示均一。第十桥接部410可以通过过孔连接第九桥接部39，以连接第六晶体管的第二极。
如图32、38、44所示，桥接层可以包括多个桥接部Bg，其中，多个 桥接部中包括第一桥接部Bg1和第二桥接部Bg2。第一桥接部Bg1可以通过过孔连接第一列第二行像素驱动电路中的第十桥接部410。第二桥接部Bg2可以通过过孔连接第三列第二行像素驱动电路中的第十桥接部410。第一桥接部Bg1包括第一延伸部Bg11，第一延伸部Bg11在衬底基板上的正投影沿第一方向X延伸，且和相邻下一行像素驱动电路中第一初始信号线Vinit1在衬底基板上的正投影至少部分交叠，例如，第一延伸部Bg11在衬底基板上的正投影位于相邻下一行像素驱动电路中第一初始信号线Vinit1在衬底基板上的正投影上；第二桥接部Bg2可以包括第二延伸部Bg22和第三延伸部Bg23，第二延伸部Bg22在衬底基板上的正投影沿第一方向X延伸且和相邻上一行像素驱动电路中第二初始信号线Vinit2在衬底基板上的正投影至少部分交叠，例如，第二延伸部Bg22在衬底基板上的正投影可以位于相邻上一行像素驱动电路中第二初始信号线Vinit2在衬底基板上的正投影上；第三延伸部Bg23在衬底基板上的正投影沿第二方向Y延伸且和本列像素驱动电路中第一电源线VDD在衬底基板上的正投影至少部分交叠，例如，第三延伸部Bg23在衬底基板上的正投影可以位于本列像素驱动电路中第一电源线VDD在衬底基板上的正投影上。由于第一初始信号线Vinit1、第二初始信号线Vinit2、第一电源线VDD用于提供稳定电压源，从而该设置可以降低交流信号对桥接部的耦合作用，提高桥接部电压的稳定性。此外，该设置还可以提高显示面板的透过率。
如图32、39所示，像素电极层可以包括多个电极部：第一电极部R、第三电极部G、第二电极部B，各个电极部可以通过过孔连接桥接部Bg以连接第六晶体管的第二极。同一电极行中，第一电极部R、第三电极部G、第二电极部B、第三电极部G在第一方向X上依次交替分布。多个电极部形成多个电极列，多个电极列包括依次相邻的第一电极列ROW1、第三电极列ROW3、第二电极列ROW2、第四电极列ROW4中，第一电极列ROW1包括在第二方向Y上依次交替分布的第一电极部R、第二电极部B；第三电极列ROW3包括多个在第二方向Y上分布的第三电极部G；第二电极列ROW2包括在第二方向Y上依次交替分布的第二电极部B、第一电极部R；第四电极列ROW4包括多个在第二方向Y上分布的第三电极部G。位于同一电极列相邻电极行的两个第三电极部G在所述衬底基板上的正投影在第二方向 上的最小距离S1大于所述第一电极部R在所述衬底基板上的正投影在第二方向的尺寸S2，或者大于所述第二电极部B所述衬底基板上的正投影在第二方向的尺寸S3。其中，第一电极部R在衬底基板上的正投影和像素定义层上与其对应的开口在衬底基板上的正投影重合，第三电极部G在衬底基板上的正投影和像素定义层上与其对应的开口在衬底基板上的正投影重合，第二电极部B在衬底基板上的正投影和像素定义层上与其对应的开口在衬底基板上的正投影重合。
如图32、39所示，第一电极列中的第二电极部B可以通过过孔连接第二桥接部Bg2，以连接第三列第二行中的像素驱动电路。第二电极列第二电极行中的第一电极部R可以通过过孔连接第一桥接部Bg1，以连接第一列第二行中的像素驱动电路。即本申请通过至少部分桥接部Bg连接位于不同列数位置的像素驱动电路和电极部，以实现同一数据线所连接的像素驱动电路驱动同一种颜色的发光单元。本示例性实施例中，第一桥接部Bg1所连接的像素驱动电路和电极部可以位于同行不同列，第二桥接部Bg2所连接的像素驱动电路和电极部可以位于同行不同列。应该理解的是，在其他示例性实施例中，桥接部所连接的像素驱动电路和电极部可以位于不同行不同列。
如图32、39所示，电极层还可以包括第四增设部E4，第四增设部E4连接于第三电极部G，第四增设部E4在衬底基板上的正投影和第二有源部72在衬底基板上的正投影至少部分交叠，第四增设部E4可以对第二晶体管进行遮光，以降低光照对第二晶体管输出特性的影响。
需要说明的是，如图32、42、43、44所示，画于第一源漏层背离衬底基板一侧的黑色方块表示第一源漏层连接面向衬底基板一侧的其他层级的过孔；画于第二源漏层背离衬底基板一侧的黑色方块表示第二源漏层连接面向衬底基板一侧的其他层级的过孔；画于桥接层背离衬底基板一侧的黑色方块表示桥接层连接面向衬底基板一侧的其他层级的过孔；画于电极层背离衬底基板一侧的黑色方块表示电极层连接面向衬底基板一侧的其他层级的过孔。该黑色方块仅表示过孔的位置，不同位置黑色方块所表示的不同过孔可以贯穿于不同绝缘层。
如图45所示，为图32所示显示面板沿虚线BB剖开的部分剖视图。 该显示面板还可以包括第一绝缘层91、第二绝缘层92、介电层93、钝化层94、第一平坦层95、第三绝缘层96、第二平坦层97。衬底基板90、有源层、第一绝缘层91、第一栅极层、第二绝缘层92、第二栅极层、介电层93、第一源漏层、钝化层94、第一平坦层95、第二源漏层、第三绝缘层96、桥接层、第二平坦层97、电极层可以依次层叠设置。第一绝缘层91、第二绝缘层92、第三绝缘层96可以氧化硅层，介电层93可以为氮化硅层，钝化层94的材料可以为氧化硅、氮化硅等，第一平坦层95、第二平坦层97的材料可以为有机材料，例如聚酰亚胺(PI)、聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)、硅-玻璃键合结构(SOG)等材料。衬底基板90可以包括依次层叠设置的玻璃基板、阻挡层、聚酰亚胺层，阻挡层可以为无机材料。第一栅极层、第二栅极层的材料可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等导电层。第一源漏层、第二源漏层的材料可以包括金属材料，例如可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层等导电层。桥接层可以为氧化铟锡层等导电层。
如图46-47所示，图46为本公开显示面板另一种示例性实施例的结构版图，图47为图46中电极层的结构版图。图46所示显示面板与图32所示显示面板不同在于：图46所示显示面板不设置桥接层，此外，图46所示显示面板中电极层包括第一桥接部Bg1和第二桥接部Bg2。第一桥接部Bg1连接第二电极列ROW2的第一电极部R，且第一桥接部Bg1通过过孔连接第二行第一列像素驱动电路中的第十桥接部410。第二桥接部Bg2连接第一电极列ROW1的第二电极部B，且第二桥接部Bg2通过过孔连接第二行第三列像素驱动电路中的第十桥接部410。第一桥接部Bg1可以包括第一延伸部Bg11、第六延伸部Bg16，第一延伸部Bg11在衬底基板上的正投影沿第一方向X延伸，且与相邻下一行像素驱动电路中第一初始信号线Vinit1在衬底基板上的正投影至少部分交叠，第六延伸部Bg16在衬底基板上的正投影沿第二方向Y延伸，且与本列像素驱动电路中第一电源线VDD在衬底基板上的正投影至少部分交叠。应该理解的是，第六延伸部Bg16在衬底基板上的正投影可以和任意输出稳定电压信号的第四信号线在衬底基板上的正投影交叠。本示例性实施例中，第四信号线可以包括上述的 第一电源线VDD，在其他示例性实施例中，第四信号线还可以包括：图10中第二电源端的等电位信号线、第一初始信号端的等电位信号线、第二初始信号端的等电位信号线等。第二桥接部Bg2包括第二延伸部Bg22、第三延伸部Bg23、第七延伸部Bg27，第七延伸部Bg27连接于第二延伸部Bg22和第三延伸部Bg23之间。第二延伸部Bg22在衬底基板上的正投影沿第一方向X延伸，且与相邻上一行像素驱动电路中第二初始信号线Vinit2在衬底基板上的正投影至少部分交叠，第三延伸部Bg23在衬底基板上的正投影沿第二方向Y延伸，且与第三导电部23在衬底基板上的正投影至少部分交叠。该设置可以降低其他交流信号对桥接部的耦合作用，同时还可以降低第一桥接部Bg1和第二桥接部Bg2对显示面板透过率的影响。此外，第七延伸部Bg27在衬底基板上的正投影可以和第二有源部72在衬底基板上的正投影交叠，第七延伸部Bg27可以降低光照对第二晶体管T2输出特性的影响。
如图48所示，为本公开显示面板中像素驱动电路的电路结构示意图。该像素驱动电路可以包括：驱动晶体管T3、第一晶体管T1、第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、电容C。其中，第四晶体管T4的第一极连接数据信号端Da，第四晶体管T4的第二极连接驱动晶体管T3的第一极，第四晶体管T4的栅极连接第一栅极驱动信号端G1；第五晶体管T5的第一极连接第一电源端VDD，第五晶体管T5的第二极连接驱动晶体管T3的第一极，第五晶体管T5的栅极连接使能信号端EM；驱动晶体管T3的栅极连接节点N；第二晶体管T2的第一极连接节点N，第二晶体管T2的第二极连接驱动晶体管T3的第二极，第二晶体管T2的栅极连接第二栅极驱动信号端G2；第六晶体管T6的第一极连接驱动晶体管T3的第二极，第六晶体管T6第二极连接第七晶体管T7的第二极，第六晶体管T6栅极连接使能信号端EM，第七晶体管T7的第一极连接第二初始信号端Vinit2，第七晶体管T7的栅极连接第二复位信号端Re2；第一晶体管T1的第二极连接节点N，第一晶体管T1的第一极连接第一初始信号端Vinit1，第一晶体管T1的栅极连接第一复位信号端Re1；电容C的第一电极连接节点N，电容C的第二电极连接第一电源端VDD。该像素驱动电路可以连接一发光单元OLED，用于驱动该发光单元OLED发 光，发光单元OLED可以连接于第六晶体管T6的第二极和第二电源端VSS之间，发光单元的第一电极可以为发光单元的阳极，发光单元的第二电极可以为发光单元的阴极。其中，第一晶体管T1和第二晶体管T2可以为N型晶体管，例如，第一晶体管T1和第二晶体管T2可以为N型金属氧化物晶体管，N型晶体管具有较小的漏电流，从而可以避免发光阶段，节点N通过第一晶体管T1和第二晶体管T2漏电。同时，驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型晶体管，例如，驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型低温多晶体硅晶体管，P型晶体管具有较高的载流子迁移率，从而有利于实现高分辨率、高反应速度、高像素密度、高开口率的显示面板。第一初始信号端和第二初始信号端可以根据实际情况输出相同或不同电压信号。
如图49所示，为图48中像素驱动电路一种驱动方法中各节点的时序图。其中，G1表示第一栅极驱动信号端G1的时序，G2表示第二栅极驱动信号端G2的时序，Re1表示第一复位信号端Re1的时序，Re2表示第二复位信号端Re2的时序，EM表示使能信号端EM的时序，Da表示数据信号端Da的时序。该像素驱动电路的驱动方法可以包括复位阶段t1、数据写入阶段t2，发光阶段t3。在复位阶段t1：第一复位信号端Re1输出高电平信号，第二复位信号端Re2输出低电平信号，第一晶体管T1、第七晶体管T7导通，第一初始信号端Vinit1向节点N输入第一初始信号，第二初始信号端Vinit2向发光单元OLED的第一电极输入第二初始信号。在数据写入阶段t2：第二栅极驱动信号端G2输出高电平信号，第一栅极驱动信号端G1输出低电平信号，第四晶体管T4、第二晶体管T2导通，同时数据信号端Da输出数据信号以向节点N写入补偿电压Vdata+Vth，其中Vdata为数据信号的电压，Vth为驱动晶体管T3的阈值电压。在发光阶段t3：使能信号端EM输出低电平信号，第六晶体管T6、第五晶体管T5导通，驱动晶体管T3在电容C存储的补偿电压Vdata+Vth作用下驱动发光单元发光。
驱动晶体管输出电流公式如下：
I＝(μWCox/2L)(Vgs-Vth) 2
其中，I为驱动晶体管输出电流；μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电压。本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth) 2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。
本示例性实施例还提供另一种显示面板，显示面板可以包括依次层叠设置的衬底基板、遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层、第一源漏层、第二源漏层、电极层，其中，上述相邻层级之间可以设置有绝缘层。如图50-66所示，图50为本公开显示面板一种示例性实施例中的结构版图，图51为图50中遮挡层的结构版图，图52为图50中第一有源层的结构版图，图53为图50中第一栅极层的结构版图，图54为图50中第二栅极层的结构版图，图55为图50中第二有源层的结构版图，图56为图50中第三栅极层的结构版图，图57为图50中第一源漏层的结构版图，图58为图50中第二源漏层的结构版图，图59为图50中电极层的结构版图，图60为图50中遮挡层、第一有源层的结构版图，图61为图50中遮挡层、第一有源层、第一栅极层的结构版图，图62为图50中遮挡层、第一有源层、第一栅极层、第二栅极层的结构版图，图63为图50中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层的结构版图，图64为图50中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层的结构版图，图65为图50中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层、第一源漏层的结构版图，图66为图50中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层、第一源漏层、第二源漏层的结构版图。该显示面板可以包括多个图48所示的像素驱动电路。如图66所示，多个像素驱动电路中可以包括在第一方向X上相邻分布第一像素驱动电路P1和第二像素驱动电路P2，第一像素驱动电路P1和第二像素驱动电路P2可以以镜像对称面BB镜像对称设置。其中，镜像对称面BB可以垂直于衬底基板。且第一像素驱动电路P1在衬底基板上的正投影和第二像素驱动电路P2在衬底基板上的正投影可以以镜像对称面BB与衬底基板 的交线为对称轴对称设置。其中，第一像素驱动电路P1和第二像素驱动电路P2可以形成一重复单元，该显示面板可以包括在第一方向X和第二方向Y上阵列分布的多个重复单元。
如图50、51、60所示，遮挡层可以包括多个遮挡部61、相邻遮挡部61之间可以相互连接。应该理解的是，在其他示例性实施例中，该显示面板也可以不包括遮挡层。
如图50、52、60、61所示，第一有源层可以包括第三有源部73、第四有源部74、第五有源部75、第六有源部76、第七有源部77。其中，第三有源部73可以用于形成驱动晶体管T3的沟道区；第四有源部74可以用于形成第四晶体管T4的沟道区；第五有源部75可以用于形成第五晶体管T5的沟道区；第六有源部76可以用于形成第六晶体管T6的沟道区；第七有源部77可以用于形成第七晶体管T7的沟道区。第一有源层还包括第九有源部79、第十有源部710、第十一有源部711、第十二有源部712、第十三有源部713。其中，第九有源部79连接于第五有源部75远离第三有源部73的一侧，且第九有源部79连接于在第一方向X上相邻重复单元中相邻两第五有源部75之间。第十有源部710连接于第六有源部76和第七有源部77之间，第十一有源部711连接于第六有源部76和第三有源部73之间，第十二有源部712连接于第四有源部74远离第三有源部73的一端，第十三有源部713连接于第七有源部77远离第六有源部76的一端。其中，遮挡部61在衬底基板上的正投影可以覆盖第三有源部73在衬底基板上的正投影，遮挡部61可以降低光照对驱动晶体管T3驱动特性的影响。第一有源层可以由多晶硅材料形成，相应的，驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型的低温多晶硅薄膜晶体管。
如图50、53、61所示，第一栅极层可以包括：第一导电部11、第一栅线G1、使能信号线EM、第二复位信号线Re2。第一栅线G1可以用于提供图48中第一栅极驱动信号端；使能信号线EM可以用于提供图48中的使能信号端；第二复位信号线Re2可以用于提供图48中的第二复位信号端。第一栅线G1在衬底基板上的正投影、使能信号线EM在衬底基板上的正投影、第二复位信号线Re2在衬底基板上的正投影均可以沿第一方向X 延伸。第一栅线G1在衬底基板上的正投影覆盖第四有源部74在衬底基板上的正投影，第一栅线G1的部分结构用于形成第四晶体管的栅极。使能信号线EM在衬底基板上的正投影覆盖第五有源部75在衬底基板上的正投影、第六有源部76在衬底基板上的正投影，使能信号线EM的部分结构可以分别用于形成第五晶体管T5、第六晶体管T6的栅极。第二复位信号线Re2在衬底基板上的正投影可以覆盖第七有源部77在衬底基板上的正投影，第二复位信号线Re2的部分结构可以用于形成第七晶体管T7的栅极。第一导电部11在衬底基板上的正投影覆盖第三有源部73在衬底基板上的正投影，第一导电部11可以用于形成驱动晶体管T3的栅极和电容C的第一电极。如图61所示，本行像素驱动电路中的第一栅线G1可以复用为下一行像素驱动电路中的第二复位信号线Re2，该显示面板可以自上向下逐行驱动。该设置可以提高像素驱动电路的集成度，降低像素驱动电路的布图面积。遮挡层还可以连接一稳定电源端，例如，遮挡层可以连接图48中的第一电源端、第一初始信号端、第二初始信号端等，遮挡部61可以屏蔽其他信号对驱动晶体管T3的噪音影响。此外，该显示面板可以利用第一栅极层为掩膜对第一有源层进行导体化处理，即第一有源层中被第一栅极层覆盖的区域可以形成晶体管的沟道区，第一有源层中未被第一栅极层覆盖的区域形成导体结构。
如图50、54、62所示，第二栅极层可以包括：第一初始信号线Vinit1、第三复位信号线2Re1、第三栅线2G2、多个第三导电部23。其中，第一初始信号线Vinit1用于提供图48中的第一初始信号端，第三复位信号线2Re1可以用于提供图48中的第一复位信号端，第三栅线2G2可以用于提供图48中的第二栅极驱动信号端。第一初始信号线Vinit1在衬底基板上的正投影、第三复位信号线2Re1在衬底基板上的正投影、第三栅线2G2在衬底基板上的正投影均可以沿第一方向X延伸。如图54所示，第二栅极层还可以包括多个连接部24，在第一方向X上相邻的重复单元中，连接部24连接于在第一方向X上相邻的两第三导电部23之间。此外，在其他示例性实施例中，在同一重复单元中，相邻第三导电部23也可以相连接。
如图50、55、63所示，第二有源层可以包括第一有源部81、第二有源部82、第十四有源部814、第十五有源部815、第十六有源部816。第 一有源部81用于形成第一晶体管T1的沟道区，第二有源部82用于形成第二晶体管T2的沟道区。第十五有源部815连接于第一有源部81和第二有源部82之间。第十四有源部814连接于第一有源部81远离第二有源部82的一端，第十六有源部816连接于第二有源部82远离第一有源部81的一端。其中，第二有源层可以由氧化铟镓锌形成，相应的，第一晶体管T1、第二晶体管T2可以为N型的金属氧化物薄膜晶体管。第三栅线2G2在衬底基板上的正投影可以覆盖第二有源部82在衬底基板上的正投影，第三栅线2G2的部分结构可以用于形成第二晶体管T2的底栅。第三复位信号线2Re1在衬底基板上的正投影可以覆盖第一有源部81在衬底基板上的正投影，第三复位信号线2Re1的部分结构可以用于形成第一晶体管T1的底栅。
如图50、56、64所示，第三栅极层可以包括第一复位信号线3Re1、第二栅线3G2。第一复位信号线3Re1在衬底基板上的正投影、第二栅线3G2在衬底基板上的正投影均可以沿第一方向X延伸。第一复位信号线3Re1可以用于提供图48中的第一复位信号端，第一复位信号线3Re1在衬底基板上的正投影可以覆盖第一有源部81在衬底基板上的正投影，第一复位信号线3Re1的部分结构可以用于形成第一晶体管T1的顶栅，同时，第一复位信号线3Re1可以通过位于显示面板边框区的过孔连接第三复位信号线2Re1。第二栅线3G2可以用于提供图48中的第二栅极驱动信号端，第二栅线3G2在衬底基板上的正投影可以覆盖第二有源部82在衬底基板上的正投影，第二栅线3G2的部分结构可以用于形成第二晶体管T2的顶栅，同时，第二栅线3G2可以通过位于显示面板边框区的过孔连接第三栅线2G2。此外，该显示面板可以利用第三栅极层为掩膜对第二有源层进行导体化处理，即第二有源层中被第三栅极层覆盖的区域可以形成晶体管的沟道区，第二有源层中未被第三栅极层覆盖的区域形成导体结构。
如图50、57、65所示，第一源漏层可以包括电源连接线4VDD、第二初始信号线Vinit2、第五桥接部45、第六桥接部46、第七桥接部47、第八桥接部48、第九桥接部49。其中，电源连接线4VDD在衬底基板上的正投影沿第一方向X延伸，且分别通过过孔连接连接部24、第九有源部79，以连接第五晶体管的第一极和电容C的第二电极。第五桥接部45可以通 过过孔连接第十有源部710，以连接第六晶体管T6的第二极和第七晶体管T7的第二极。第六桥接部46可以分别通过过孔连接第十一有源部711、第十六有源部816，以连接第二晶体管T2的第二极、第六晶体管T6的第一极、驱动晶体管T3的第二极。第七桥接部47可以分别通过过孔连接第十五有源部815、第一导电部11，以连接第二晶体管T2的第一极和驱动晶体管的栅极。第三导电部23上形成有开口231，连接于第一导电部11和第七桥接部47之间的过孔在衬底基板上的正投影位于开口231在衬底基板上的正投影以内，以使该过孔与第三导电部23相互绝缘。第八桥接部48可以分别通过过孔连接第十四有源部814、第一初始信号线Vinit1，以连接第一晶体管的第一极和第一初始信号端。其中，同一重复单元中，相邻两像素驱动电路可以共用同一第八桥接部48。第九桥接部49可以通过过孔连接第十二有源部712，以连接第四晶体管的第一极。第二初始信号线Vinit2可以用于提供图48中的第二初始信号端，第二初始信号线Vinit2在衬底基板上的正投影可以沿第一方向X延伸，第二初始信号线Vinit2可以通过过孔连接第十三有源部713，以连接第七晶体管的第一极和第二初始信号端。
如图50、58、66所示，第二源漏层可以包括多条第一电源线VDD、多条数据线Da、第十桥接部510。其中，第一电源线VDD在衬底基板上的正投影、数据线Da在衬底基板上的正投影均可以沿第二方向Y延伸。第一电源线VDD可以用于提供图48中的第一电源端，数据线Da可以用于提供图48中的数据信号端。如图50、66所示，每列像素驱动电路可以对应设置一条第一电源线VDD，第一电源线VDD可以通过过孔连接电源连接线4VDD，以连接第五晶体管的第一极和第一电源端。数据线Da可以通过过孔连接第九桥接部49，以连接第四晶体管的第一极和数据信号端。第十桥接部510可以通过过孔连接第五桥接部45，以连接第七晶体管的第二极。如图58所示，在同一重复单元中，相邻第一电源线VDD相互连接，从而第一电源线VDD、电源连接线4VDD、第三导电部23可以形成网格结构，该网格结构的电源线可以降低其上电源信号的压降。在同一重复单元中，相连接的第一电源线VDD上可以形成有多个开口VDDx，开口VDDx可以位于显示面板的透光区，即开口VDDx在衬底基板上的正投影可以与其他非 透明结构层在衬底基板上的正投影不交叠，该设置可以提高显示面板的透过率。其中，其他非透明结构层可以包括第一栅极层、第二栅极层、第一源漏层、第一有源层、第二有源层。
如图50、58、66所示，第一电源线VDD可以包括第一电源线段VDD1、第二电源线段VDD2、第三电源线段VDD3，第二电源线段VDD2连接于第一电源线段VDD1和第三电源线段VDD3之间，第二电源线段VDD2在所述衬底基板上的正投影在第一方向X上的尺寸可以大于第一电源线段VDD1在所述衬底基板上的正投影在第一方向X上的尺寸，且所述第二电源线段VDD2在所述衬底基板上的正投影在第一方向X上的尺寸可以大于所述第三电源线段VDD3在所述衬底基板上的正投影在第一方向X上的尺寸。此外，第二电源线段VDD2在衬底基板上的正投影还可以覆盖第一有源部81在衬底基板上的正投影、第二有源部82在衬底基板上的正投影，第二电源线段VDD2可以降低光照对第一晶体管T1、第二晶体管T2的特性影响。此外，第一电源线VDD在衬底基板上的正投影还可以与第七桥接部47在衬底基板上的正投影至少部分交叠，第一电源线VDD可以用于屏蔽其他信号对第七桥接部47的噪音干扰，从而提高驱动晶体管T3栅极电压的稳定性。
如图50、59所示，像素电极层可以包括多个电极部：第一电极部R、第三电极部G、第二电极部B，各个电极部可以通过桥接部Bg连接第六晶体管的第二极。同一电极行中，第一电极部R、第三电极部G、第二电极部B、第三电极部G在第一方向X上依次交替分布。多个电极部形成多个电极列，多个电极列包括依次相邻的第一电极列ROW1、第三电极列ROW3、第二电极列ROW2、第四电极列ROW4，第一电极列ROW1包括在第二方向Y上依次交替分布的第一电极部R、第二电极部B；第三电极列ROW3包括多个在第二方向Y上分布的第三电极部G；第二电极列ROW2包括在第二方向Y上依次交替分布的第二电极部B、第一电极部R；第四电极列ROW4包括多个在第二方向Y上分布的第三电极部G。位于同一电极列相邻电极行的两个第三电极部G在所述衬底基板上的正投影在第二方向Y上的最小距离S1大于所述第一电极部R在所述衬底基板上的正投影在第二方向Y上的尺寸S2，或者大于所述第二电极部B所述衬底基板上的正投影在第二方向Y 上的尺寸S3。其中，第一电极部R在衬底基板上的正投影和像素定义层上与其对应的开口在衬底基板上的正投影重合，第三电极部G在衬底基板上的正投影和像素定义层上与其对应的开口在衬底基板上的正投影重合，第二电极部B在衬底基板上的正投影和像素定义层上与其对应的开口在衬底基板上的正投影重合。在同一重复单元中，相邻第一电源线VDD中两第二电源线段VDD2相连接。相连接的两第二电源线段VDD2在衬底基板上的正投影覆盖与其在衬底基板上正投影相交的电极部在衬底基板上的正投影，该设置可以使得电极部各个位置的高度更加均一。
如图50、59所示，电极层还可以包括第一桥接部Bg1和第二桥接部Bg2。第一桥接部Bg1连接第三电极列ROW3中的第一电极部R，且第一桥接部Bg1通过过孔连接第二行第一列像素驱动电路中的第十桥接部510。第二桥接部Bg2连接第一电极列ROW1中的第二电极部B，且第二桥接部Bg2通过过孔连接第二行第三列像素驱动电路中的第十桥接部510。
需要说明的是，如图50、65、66所示，画于第一源漏层背离衬底基板一侧的黑色方块表示第一源漏层连接面向衬底基板一侧的其他层级的过孔；画于第二源漏层背离衬底基板一侧的黑色方块表示第二源漏层连接面向衬底基板一侧的其他层级的过孔；画于电极层背离衬底基板一侧的黑色方块表示电极层连接面向衬底基板一侧的其他层级的过孔。该黑色方块仅表示过孔的位置，不同位置黑色方块所表示的不同过孔可以贯穿于不同绝缘层。
如图67所示，为图50所示显示面板沿虚线CC剖开的部分剖视图。该显示面板还可以包括第一绝缘层91、第二绝缘层92、第三绝缘层93、第四绝缘层94、第五绝缘层95、第一介电层96、钝化层97、第一平坦层98、第二平坦层99，其中，衬底基板90、遮挡层、第一绝缘层91、第一有源层、第二绝缘层92、第一栅极层、第三绝缘层93、第二栅极层、第四绝缘层94、第二有源层、第五绝缘层95、第三栅极层、第一介电层96、第一源漏层、钝化层97、第一平坦层98、第二源漏层、第二平坦层99依次层叠设置。第一绝缘层91、第二绝缘层92、第三绝缘层93、第四绝缘层94、第五绝缘层95可以为单层结构或多层结构，且第一绝缘层91、第二绝缘层92、第三绝缘层93、第四绝缘层94、第五绝缘层95的材料可以 为氮化硅，氧化硅，氮氧化硅中的至少一种；第一介电层96可以为氮化硅层；第一平坦层98、第二平坦层99的材料可以为有机材料，例如聚酰亚胺(PI)、聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)、硅-玻璃键合结构(SOG)等材料。钝化层97可以为氧化硅层。衬底基板90可以包括依次层叠设置的玻璃基板、阻挡层、聚酰亚胺层，阻挡层可以为无机材料。第一栅极层、第二栅极层、第三栅极层的材料可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等导电层。第一源漏层、第二源漏层的材料可以包括金属材料，例如可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层等导电层。
应该理解的是，在其他示例性实施例中，第一桥接部和第二桥接部还可以位于其他导电层，例如，第一桥接部和第二桥接部可以位于增设于第二源漏层和电极层之间的桥接层。
如图68-70所示，图68为本公开显示面板另一种示例性实施例的结构版图，图69为图68中第一有源层、第一栅极层、第二栅极层、第一源漏层、第二源漏层、桥接层的结构版图，图70为图68中桥接层的结构版图。
图68所示的显示面板与图50所示的显示面板不同在于：在图68所示的显示面板中，桥接层可以包括多个桥接部Bg，桥接部Bg分别通过过孔连接第十桥接部510和电极部。其中，多个桥接部中包括第一桥接部Bg1和第二桥接部Bg2。第一桥接部Bg1可以通过过孔连接第一列第二行像素驱动电路中的第十桥接部510和第三电极列中的第一电极部R。第二桥接部Bg2可以通过过孔连接第三列第二行像素驱动电路中的第十桥接部510和第一电极列中的第二电极部B。
如图71所示，为本公开一种显示面板中源极驱动电路的结构示意图。该源极驱动电路可以包括数据锁存器03、数据重置电路04。数据锁存器03可以用于接收多个原始数据信号，所述原始数据信号包括串行的多个原始数据，至少部分所述原始数据信号中的原始数据用于驱动不同颜色的发光单元；数据重置电路04用于根据所述原始数据信号生成重置数据信号，所述重置数据信号包括串行的多个重置数据，同一所述重置数据信号中的 重置数据用于驱动同一颜色的发光单元。该源极驱动电路还可以包括随机存取存储器01、数据控制电路02、升压电路05、数模转换器06、数据输出端07、时序控制器TCON、伽马模块08。随机存取存储器01用于接收画面数据；数据控制电路02用于对画面数据进行优化以生成原始数据信号；升压电路05对重置数据信号进行升压处理；数模转换器06对升压后的重置数据信号进行数模转换；数据输出端07将数模转换后的重置数据信号传输到对于的数据线；时序控制器TCON可以控制数据控制电路02、数据锁存器03、数据重置电路04的工作时序；伽马模块08用于提供伽马数据，伽马数据可以包括各个亮度值下各个灰阶对应的伽马电压。例如，在如图6所示的显示面板，第一像素电路列PX1所连接的第一数据线对应的原始数据信号包括多个串行的原始数据，多个串行的原始数据用于交替驱动红色发光单元和蓝色发光单元；第二像素电路列PX2所连接的第二数据线对应的原始数据信号包括多个串行的原始数据，多个串行的原始数据用于交替驱动红色发光单元和蓝色发光单元。数据重置电路04可以将第一数据线对应的用于驱动蓝色发光单元的原始数据替换为第二数据线对应的用于驱动红色发光单元的原始数据；同时将第二数据线对应的用于驱动红色发光单元的原始数据替换为第一数据线对应的用于驱动蓝色发光单元的原始数据，从而生成重置数据信号。
需要说明的是，本公开中的附图比例可以作为实际工艺中的参考，但不限于此，例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图。此外，第一、第二等限定词仅用于限定不同的结构名称，其并没有特定顺序的含义，同一结构层可以通过同一构图工艺形成。在本示例性实施例中，某一结构在衬底基板上的正投影沿某一方向延伸，可以理解为，该结构在衬底基板上的正投影沿该方向直线延伸或弯折延伸。
本示例性实施例还提供一种显示装置，其中，包括上述的显示面板。该显示装置可以为手机、平板电脑、电视等显示装置。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应 性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (25)

  1. 一种显示面板，其中，所述显示面板包括：
    衬底基板；
    电极层，位于所述衬底基板的一侧，所述电极层包括多个电极部，所述电极部用于形成发光单元的第一电极，多个所述电极部在所述衬底基板上的正投影沿第一方向和第二方向阵列分布，所述第一方向和所述第二方向相交，在所述第二方向上分布的多个所述电极部形成电极列，至少部分所述电极列包括用于形成不同颜色发光单元第一电极的电极部；
    多个像素驱动电路，与所述电极部对应设置，所述像素驱动电路连接与其对应的所述电极部，所述像素驱动电路用于驱动所述发光单元发光；
    多条数据线，在所述衬底基板上的正投影沿所述第一方向间隔分布且沿所述第二方向延伸，所述数据线连接多个所述像素驱动电路，所述数据线用于向与其连接的所述像素驱动电路提供数据信号，且同一所述数据线所连接的多个所述像素驱动电路用于驱动同一颜色的所述发光单元。
  2. 根据权利要求1所述的显示面板，其中，多个所述电极部中包括第一电极部和第二电极部，所述第一电极部和第二电极部分别用于形成不同颜色发光单元的第一电极；
    多个所述电极列中包括：
    第一电极列，包括至少一个所述第一电极部和至少一个所述第二电极部，在同一所述第一电极列中，所述第一电极部和所述第二电极部在所述衬底基板上的正投影沿所述第二方向依次交替分布；
    第二电极列，包括至少一个所述第一电极部和至少一个所述第二电极部，在同一所述第二电极列中，所述第一电极部和所述第二电极部在所述衬底基板上的正投影沿所述第二方向依次交替分布；
    其中，在所述第一电极列和所述第二电极列中，所述第一电极部和所述第二电极部位于同一行；
    多条所述数据线中包括：
    第一数据线，所述第一数据线所连接的像素驱动电路连接所述第一电极列和所述第二电极列中的所述第一电极部；
    第二数据线，所述第二数据线所连接的像素驱动电路连接所述第一电 极列和所述第二电极列中的所述第二电极部。
  3. 根据权利要求2所述的显示面板，其中，多个所述电极部中还包括第三电极部，所述第一电极部、第二电极部、第三电极部分别用于形成不同颜色发光单元的第一电极；
    多个所述电极列中还包括：第三电极列、第四电极列，所述第一电极列、第三电极列、第二电极列、第四电极列在所述第一方向上依次交替分布；
    所述第三电极列包括多个所述第三电极部，同一所述第三电极列中的第三电极部在所述衬底基板上的正投影在所述第二方向上间隔分布；
    所述第四电极列包括多个所述第三电极部，同一所述第四电极列中的第三电极部在所述衬底基板上的正投影在所述第二方向上间隔分布。
  4. 根据权利要求2所述的显示面板，其中，多个所述像素驱动电路在所述衬底基板上的正投影沿所述第一方向和第二方向阵列分布，在所述第二方向上分布的多个所述像素驱动电路形成像素电路列，多个所述像素电路列中包括第一像素电路列和第二像素电路列；
    所述第一像素电路列中的像素驱动电路连接所述第一电极列中的电极部；
    所述第二像素电路列中的像素驱动电路连接所述第二电极列中的电极部；
    所述第一数据线连接所述第一电极列和所述第二电极列中所述第一电极部所连接的像素驱动电路；
    所述第二数据线连接所述第一电极列和所述第二电极列中第二电极部所连接的像素驱动电路。
  5. 根据权利要求2所述的显示面板，其中，多个所述像素驱动电路在所述衬底基板上的正投影沿所述第一方向和所述第二方向阵列分布，在所述第二方向分布的多个所述像素驱动电路形成像素电路列，所述像素电路列包括第一像素电路列和第二像素电路列；
    所述第一数据线连接所述第一像素电路列中的像素驱动电路，所述第二数据线连接所述第二像素电路列中的像素驱动电路；
    所述显示面板还包括：
    第一桥接部，所述第一桥接部连接于所述第一像素电路列中像素驱动电路和所述第二电极列中第一电极部之间；
    第二桥接部，所述第二桥接部连接于所述第二像素电路列中像素驱动电路和所述第一电极列中第二电极部之间。
  6. 根据权利要求5所述的显示面板，其中，所述显示面板还包括：
    第一信号线，在所述衬底基板上的正投影沿所述第一方向延伸；
    第二信号线，在所述衬底基板上的正投影沿所述第一方向延伸；
    其中，所述第一信号线和所述第二信号线用于提供稳定电压信号；
    所述第一桥接部包括第一延伸部，所述第二桥接部包括第二延伸部，所述第一延伸部在所述衬底基板上的正投影、所述第二延伸部在所述衬底基板上的正投影均沿所述第一方向延伸；
    所述第一延伸部在所述衬底基板上的正投影与所述第一信号线在所述衬底基板上的正投影至少部分交叠，和/或所述第二延伸部在所述衬底基板上的正投影和所述第二信号线在所述衬底基板上的正投影至少部分交叠。
  7. 根据权利要求6所述的显示面板，其中，所述像素驱动电路包括驱动晶体管、第一晶体管、第七晶体管，所述第一晶体管的第一极连接第一初始信号线，所述第一晶体管的第二极连接所述驱动晶体管的栅极，所述第七晶体管的第一极连接第二初始信号线，所述第七晶体管的第二极连接所述驱动晶体管的第二极；
    所述第一初始信号线形成所述第一信号线，所述第二初始信号线形成所述第二信号线；
    或，所述第一初始信号线形成所述第二信号线，所述第二初始信号线形成所述第一信号线。
  8. 根据权利要求6所述的显示面板，其中，所述像素驱动电路包括驱动晶体管、第一晶体管，所述第一晶体管的第一极连接第一初始信号线，所述第一晶体管的第二极连接所述驱动晶体管的栅极；
    相邻的两条所述第一初始信号线分别形成所述第一信号线和所述第二信号线。
  9. 根据权利要求5所述的显示面板，其中，所述显示面板还包括：
    第三信号线，所述第三信号线在所述衬底基板上的正投影沿所述第二方向延伸，且所述第三信号线用于提供稳定电压信号；
    所述第二桥接部还包括第三延伸部，所述第三延伸部在所述衬底基板上的正投影沿所述第二方向延伸，且所述第三延伸部在所述衬底基板上的正投影和所述第三信号线在所述衬底基板上的正投影至少部分交叠。
  10. 根据权利要求5所述的显示面板，其中，所述显示面板还包括：
    第四信号线，所述第四信号线在所述衬底基板上的正投影沿所述第二方向延伸，且所述第四信号线用于提供稳定电压信号；
    所述第一桥接部还包括第六延伸部，所述第六延伸部在所述衬底基板上的正投影沿所述第二方向延伸，且所述第六延伸部在所述衬底基板上的正投影和所述第四信号线在所述衬底基板上的正投影至少部分交叠。
  11. 根据权利要求5所述的显示面板，其中，所述像素驱动电路包括驱动晶体管、第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，所述第二晶体管的第二极连接所述驱动晶体管的第二极；
    所述显示面板还包括：
    第一有源层，位于所述衬底基板和所述电极层之间，所述第一有源层包括第二有源部，所述第二有源部用于形成所述第二晶体管的沟道区；
    所述第二桥接部包括第二延伸部、第三延伸部、连接于所述第二延伸部和第三延伸部之间的第七延伸部，所述第二延伸部在所述衬底基板上的正投影沿所述第一方向延伸，所述第三延伸部在所述衬底基板上的正投影沿所述第二方向延伸，所述第七延伸部在所述衬底基板上的正投影和所述第二有源部在所述衬底基板上的正投影至少部分交叠。
  12. 根据权利要求2所述的显示面板，其中，所述显示面板还包括：
    第三桥接部，所述第三桥接部连接于所述第一像素电路列中像素驱动电路和所述第一电极列中的第一电极部之间；
    第四桥接部，所述第四桥接部连接于所述第二像素电路列中的像素驱动电路和所述第二电极列中的第二电极部之间。
  13. 根据权利要求12所述的显示面板，其中，所述第一桥接部连接位于同一行数的像素驱动电路和电极部之间，所述第二桥接部连接位于同一行数的像素驱动电路和电极部之间，所述第三桥接部连接位于同一行列 数的像素驱动电路和电极部之间，所述第四桥接部连接位于同一行列数的像素驱动电路和电极部之间。
  14. 根据权利要求12所述的显示面板，其中，所述第一桥接部和其他结构形成的寄生电容容量为C1，所述第二桥接部和其他结构形成的寄生电容容量为C2，所述第三桥接部和其他结构形成的寄生电容容量为C3，所述第四桥接部和其他结构形成的寄生电容容量为C4；
    其中，C1＝N1*C3，C2＝N2*C4，N1大于等于70％且小于等于130％，N2大于等于70％且小于等于130％。
  15. 根据权利要求12所述的显示面板，其中，显示面板还包括：
    多条第三信号线，所述第三信号线在所述衬底基板上的正投影沿所述第一方向间隔分布且沿所述第二方向延伸，且所述第三信号线用于提供稳定电压信号；
    所述第三桥接部包括第四延伸部，所述第四桥接部包括第五延伸部，所述第四延伸部在所述衬底基板上的正投影、所述第五延伸部在所述衬底基板上的正投影均沿所述第二方向延伸；
    所述第四延伸部在所述衬底基板上的正投影和所述第三信号线在所述衬底基板上的正投影至少部分交叠，所述第五延伸部在所述衬底基板上的正投影和另一所述第三信号线在所述衬底基板上的正投影至少部分交叠。
  16. 根据权利要求9或15所述的显示面板，其中，所述像素驱动电路包括驱动晶体管，所述显示面板还包括：
    第一电源线，连接所述驱动晶体管的第一极，所述第一电源线形成所述第三信号线。
  17. 根据权利要求12所述的显示面板，其中，所述显示面板还包括：
    第一源漏层，位于所述衬底基板和所述电极层之间；
    第二源漏层，位于所述第一源漏层和所述电极层之间；
    所述第一桥接部、第二桥接部、第三桥接部、第四桥接部位于所述电极层；
    或，所述第一桥接部、所述第二桥接部、第三桥接部、第四桥接部所在导电层位于所述第二源漏层和所述电极层之间；
    或，所述第一桥接部、所述第二桥接部、第三桥接部、第四桥接部所在导电层位于所述第二源漏层和所述第一源漏层之间。
  18. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：源极驱动电路，所述源极驱动电路包括：
    数据锁存器，用于接收多个原始数据信号，所述原始数据信号包括串行的多个原始数据，至少部分所述原始数据信号中的原始数据用于驱动不同颜色的发光单元；
    数据重置电路，用于根据所述原始数据信号生成重置数据信号，所述重置数据信号包括串行的多个重置数据，同一所述重置数据信号中的重置数据用于驱动同一颜色的发光单元。
  19. 根据权利要求1所述的显示面板，其中，所述像素驱动电路包括驱动晶体管、第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，所述第二晶体管的第二极连接所述驱动晶体管的第二极；
    所述显示面板还包括：
    第一有源层，位于所述衬底基板和所述电极层之间，所述第一有源层包括第二有源部，所述第二有源部用于形成所述第二晶体管的沟道区；
    所述电极层还包括：
    增设部，连接于所述电极部，所述增设部在所述衬底基板上的正投影和所述第二有源部在所述衬底基板上的正投影至少部分交叠。
  20. 根据权利要求1所述的显示面板，其中，所述像素驱动电路包括驱动晶体管、第一晶体管，所述第一晶体管的第一极连接第一初始信号线，第二极连接所述驱动晶体管的栅极；
    所述显示面板还包括：
    第二栅极层，位于所述衬底基板和所述电极层之间，所述第二栅极层包括所述第一初始信号线，所述第一初始信号线在所述衬底基板上的正投影沿所述第一方向延伸；
    第一源漏层，位于所述第二栅极层和所述电极层之间，所述第一源漏层包括第一初始连接线，所述第一初始连接线在所述衬底基板上的正投影沿所述第二方向延伸，所述第一初始连接线通过过孔连接与其在衬底基板上正投影相交的所述第一初始信号线，且所述第一初始连接线连接所述第 一晶体管的第一极。
  21. 根据权利要求1所述的显示面板，其中，所述显示面板包括沿所述第一方向和所述第二方向阵列分布的多个重复单元；
    每个所述重复单元包括沿第一方向分布的两个所述像素驱动电路，同一所述重复单元中两个所述像素驱动电路镜像对称设置；
    所述像素驱动电路包括驱动晶体管、电容，所述电容的第一电极连接所述驱动晶体管的栅极，所述电容的第二电极连接第一电源线；
    所述显示面板还包括：
    第二栅极层，位于所述衬底基板和所述电极层之间，所述第二栅极层包括第三导电部，所述第三导电部用于形成所述电容的第二电极；
    第二源漏层，位于所述第二栅极层和所述电极层之间，所述第二源漏层包括所述第一电源线，在同一重复单元中相邻两所述第一电源线相连接；
    且在所述第一方向上相邻的两所述重复单元中相邻两所述第三导电部相连接。
  22. 根据权利要求21所述的显示面板，其中，所述显示面板还包括：
    第一源漏层，位于所述第二栅极层和所述第二源漏层之间，所述第一源漏层包括电源连接线，所述电源连接线在所述衬底基板上的正投影沿所述第一方向延伸，所述电源连接线分别通过过孔连接所述第三导电部、第一电源线。
  23. 根据权利要求21所述的显示面板，其中，所述第一电源线包括：第一电源线段、第二电源线段、第三电源线段，所述第二电源线段连接于所述第一电源线段和所述第三电源线段之间；
    所述第二电源线段在所述衬底基板上的正投影在第一方向上的尺寸大于第一电源线段在所述衬底基板上的正投影在第一方向上的尺寸，且所述第二电源线段在所述衬底基板上的正投影在第一方向上的尺寸大于所述第三电源线段在所述衬底基板上的正投影在第一方向上的尺寸；
    在同一重复单元中，相邻两所述第二电源线段相连接，相连接的所述第二电源线段在所述衬底基板上的正投影覆盖与其在所述衬底基板上正投影相交的电极部在所述衬底基板上的正投影。
  24. 根据权利要求21所述的显示面板，其中，所述第一电源线包括： 第一电源线段、第二电源线段、第三电源线段，所述第二电源线段连接于所述第一电源线段和所述第三电源线段之间；
    所述第二电源线段在所述衬底基板上的正投影在第一方向上的尺寸大于第一电源线段在所述衬底基板上的正投影在第一方向上的尺寸，且所述第二电源线段在所述衬底基板上的正投影在第一方向上的尺寸大于所述第三电源线段在所述衬底基板上的正投影在第一方向上的尺寸；
    在同一重复单元中，相邻两所述第一电源线段相连接，相邻两所述第三电源线段相连接，相连接的所述第一电源线段上形成有开口，和/或相连接的所述第三电源线段上形成有开口，所述开口位于所述显示面板的透光区。
  25. 一种显示装置，其中，包括权利要求1-24任一项所述的显示面板。
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