WO2023230817A1 - 驱动背板、显示面板及显示装置 - Google Patents

驱动背板、显示面板及显示装置 Download PDF

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Publication number
WO2023230817A1
WO2023230817A1 PCT/CN2022/096167 CN2022096167W WO2023230817A1 WO 2023230817 A1 WO2023230817 A1 WO 2023230817A1 CN 2022096167 W CN2022096167 W CN 2022096167W WO 2023230817 A1 WO2023230817 A1 WO 2023230817A1
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WIPO (PCT)
Prior art keywords
gate
line
bus
layer
transistor
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PCT/CN2022/096167
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English (en)
French (fr)
Inventor
周桢力
嵇凤丽
石佺
卢彦伟
闫卓然
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/096167 priority Critical patent/WO2023230817A1/zh
Priority to CN202280001555.0A priority patent/CN117501347A/zh
Publication of WO2023230817A1 publication Critical patent/WO2023230817A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present disclosure relates to the field of display technology, and specifically to a driving backplane, a display panel and a display device.
  • OLED (organic electroluminescent diode) display panels have the advantages of self-illumination, wide color gamut, high contrast, flexibility, high response and flexibility, etc., and have broad application prospects.
  • existing display panels may experience abnormal display images such as black screen and flickering.
  • the present disclosure provides a driving backplane, a display panel and a display device.
  • a driving backplane has a pixel area and a control area outside the pixel area.
  • the control area includes a circuit area and is separated from the circuit area and the pixel. bus area between areas; the circuit layer includes:
  • a plurality of gate lines extend along the row direction and are distributed along the column direction, and the pixel circuits in one row are connected to at least one of the gate lines;
  • a gate drive circuit is provided in the control area and includes a plurality of gate shift register units cascaded along the column direction;
  • a bus line is provided in the bus area and is at least partially located between the gate driving circuit and the pixel area, the bus line is located on the side of the gate line away from the substrate;
  • a plurality of gate connection lines, a gate shift register unit is connected to one of the gate connection lines, at least a part of the gate connection line is in a different layer from the gate line, and is connected to at least one of the gate connection lines through a contact hole.
  • Gate line connection; the gate connection line is insulated from the bus line.
  • the gate connection line includes a first connection portion and a second connection portion connected to each other, the first connection portion is connected to the gate shift register unit and passes through In the bus area, the second connection part is spaced apart from the bus line and the pixel circuit, and is connected to at least one gate line; at least one of the first connection part and the second connection part is connected to
  • the gate lines are in different layers.
  • the first connection part and the gate line are arranged in the same layer, and the second connection part and the gate line are in different layers.
  • the first connection part and the second connection part are provided on the same layer and are on different layers from the gate line and the bus line.
  • the circuit layer further includes a power supply line, a data line and a reset signal line, both of the power supply line and the data line extend along the column direction and are distributed along the row direction.
  • the power line and the data line are arranged on the same layer as the bus line;
  • the reset signal line extends along the row direction and is distributed along the column direction, and the reset signal line, the gate line and the bus line Located on different floors;
  • the gate line includes a first gate line and a second gate line
  • the pixel circuit includes a storage capacitor and a plurality of transistors, the transistors including a driving transistor, a writing transistor, a compensation transistor and a first reset transistor; the gates of the compensation transistor and the writing transistor are in contact with the first gate Line connection; the first electrode of the driving transistor is connected to the power line, and the second electrode is connected to the light-emitting device; the compensation transistor is connected to the second electrode and the gate electrode of the driving transistor; the first electrode of the writing transistor Connected to the data line, the second electrode is connected to the first electrode of the driving transistor; the gate electrode of the first reset transistor is connected to the second gate line, and the first electrode is connected to the reset signal line, The second electrode is connected to the gate of the driving transistor; the first plate of the storage capacitor is connected to the gate of the driving transistor, and the second plate is connected to the power line;
  • the first gate line connecting the pixel circuits in the nth row and the second gate line connecting the pixel circuits in the n+1th row are connected to the same gate shift register unit through the same gate connection line.
  • the circuit layer includes:
  • a semiconductor layer is provided on one side of the substrate and includes a channel of each of the transistors;
  • a first gate layer is provided on the surface of the first gate insulating layer away from the substrate, and includes the gate line, the first plate and the gate electrode of each of the transistors;
  • a second gate layer is provided on the surface of the second gate insulating layer away from the substrate, and includes the second electrode plate and the reset signal line;
  • a source and drain layer is provided on a side of the dielectric layer away from the substrate, and includes the bus line, the power line and the data line.
  • connection part if the first connection part is arranged in the same layer as the gate line and is in a different layer from the second connection part:
  • the first connection part is connected to the second gate line; the second connection part is located on the source and drain layer and extends along the column direction, and the second connection part is connected to the first gate line through a contact hole. Grid connection.
  • first connection part and the second connection part are arranged on the same layer:
  • the gate connection line is located on the second gate layer.
  • the first connection portion is connected to the gate shift register unit and the second gate line through a contact hole; the second connection portion extends along the column direction, and Connected to the first connection part, the second connection part is connected to the first gate line through a contact hole.
  • the gate line further includes a third gate line;
  • the pixel circuit further includes a second reset transistor, a first emission control transistor, and a second emission control transistor;
  • the gate electrode of the first light-emitting control transistor is connected to the third gate line, the first electrode is connected to the power line, and the second electrode is connected to the first electrode of the driving transistor;
  • the gate electrode of the second light emitting control transistor is connected to the third gate line, the first electrode is connected to the second electrode of the driving transistor, and the second electrode is connected to the light emitting device;
  • the gate electrode of the second reset transistor is connected to the first gate line, the first electrode is connected to the reset signal line, and the second electrode is connected to the second electrode of the second light emitting control transistor.
  • the circuit layer further includes:
  • a light-emitting control circuit located in the control area, the light-emitting control circuit includes a plurality of light-emitting shift register units cascaded along the column direction;
  • a plurality of light-emitting connection lines, a light-emitting shift register unit is connected to one of the light-emitting connection lines, at least a part of the light-emitting connection line is located on a different layer from the third gate line, and is connected to a light-emitting connection line through a contact hole.
  • the third gate line is connected.
  • the light-emitting connection line is located on the second gate layer and is connected to the light-emitting shift register unit and the third gate line through a contact hole.
  • the light-emitting connection line includes a third connection part and a fourth connection part.
  • the third connection part is provided in the same layer as the gate line and is shifted from the light-emitting connection part.
  • the register unit is connected, and the third connection part passes through the bus area along the direction; the fourth connection part is located on the source-drain layer or the second gate layer, and is connected to the third connection part through a contact hole. is connected to the third gate line.
  • the second reset transistor of the pixel circuit in the nth row is connected to the second gate line of the pixel circuit in the n+1th row.
  • the bus includes a test bus, a reset bus and a power bus located at the source and drain layer, the power line is connected to the power bus, and the reset signal line is connected to the reset bus connection.
  • the reset bus is located between the test bus and the pixel area
  • the second connection portion is located on a side of the reset bus away from the test bus, and It is arranged adjacent to the reset bus; the distance between the second connection part and the reset bus along the row direction is 3 ⁇ m-10 ⁇ m.
  • the width of the second connection portion is 20%-40% of the width of the reset bus.
  • the driving backplane control area includes a lead-out area, which extends along the row direction and is spaced apart from the pixel area along the column direction; the bus line, The data line and the power line are both connected to the lead-out area;
  • the bus area includes a side bus area distributed on both sides of the pixel area along the row direction and a connection bus area connected between the two side bus areas.
  • the connection bus area is located between the lead-out area and the pixel. between districts;
  • the power bus is located in the connection bus area.
  • a display panel including the driving backplane described in any one of the above.
  • a display device including the display panel according to any one of the above.
  • FIG. 1 is a partial cross-sectional schematic diagram of an embodiment of a display panel of the present disclosure.
  • FIG. 2 is a schematic diagram showing the distribution of various regions in an embodiment of the driving backplane of the present disclosure.
  • FIG. 3 is a schematic diagram of circuit distribution in an embodiment of the driving backplane of the present disclosure.
  • FIG. 4 is a schematic diagram of a pixel circuit in an embodiment of the driving backplane of the present disclosure.
  • FIG. 5 is a partial top view of the semiconductor layer in an embodiment of the driving backplane of the present disclosure.
  • FIG. 6 is a partial top view of the first gate layer in an embodiment of the driving backplane of the present disclosure.
  • FIG. 7 is a partial top view of the second gate layer in an embodiment of the driving backplane of the present disclosure.
  • FIG. 8 is a partial top view of the source and drain layers in an embodiment of the driving backplane of the present disclosure.
  • FIG. 9 is a partial top view of a pixel circuit in an embodiment of the driving backplane of the present disclosure.
  • FIG. 10 is a schematic diagram of a gate shift register unit in an embodiment of the driving backplane of the present disclosure.
  • FIG. 11 is a partial schematic diagram of a first embodiment of the first type of driving backplane according to the present disclosure.
  • FIG. 12 is a partial schematic diagram of a second embodiment of the first type of driving backplane according to the present disclosure.
  • FIG. 13 is a partial schematic diagram of a third embodiment of the first type of driving backplane according to the present disclosure.
  • FIG. 14 is a partial schematic diagram of a fourth embodiment of the first type of driving backplane according to the present disclosure.
  • FIG. 15 is a partial schematic diagram of a first embodiment of the second type of driving backplane according to the present disclosure.
  • FIG. 16 is a schematic diagram of circuit distribution in another embodiment of the driving backplane of the present disclosure.
  • FIG. 17 is a partial schematic diagram of a power bus of a driving backplane according to an embodiment of the present disclosure.
  • FIG. 18 is a partial schematic diagram of another embodiment of the power bus of the driving backplane according to the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • row direction X and the column direction Y in this article are only two mutually perpendicular directions.
  • overlap of feature A and feature B in this article means that the orthographic projection of feature A on the substrate and the orthographic projection of feature B on the substrate at least partially overlap.
  • non-overlapping of feature A and feature B in this article means that the area of the overlapping area of the orthographic projection of feature A on the substrate and the orthographic projection of feature B on the substrate is zero.
  • the “same layer” of feature A and feature B in this article means that feature A and feature B can be formed at the same time.
  • the “different layers” of feature A and feature B mean that feature A and feature B are spaced apart in a direction perpendicular to the substrate, and they are separated by other film layers.
  • the display panel of the present disclosure may include a driving backplane BP and a light-emitting device LD disposed on one side of the driving backplane BP.
  • the driving circuit in the driving backplane BP can drive the light-emitting device LD to emit light to display an image. .
  • the light-emitting device LD may be an OLED (organic light-emitting diode), a QLED (quantum dot light-emitting diode), a Micro LED or a Mini LED, etc., and may include a first electrode ANO, a second electrode CAT and a second electrode located between the first electrode ANO and the second electrode CAT. between the luminescent layers EL.
  • the display panel can be divided into at least a luminous display area and a non-luminous peripheral area outside the display area.
  • the driving circuit can include a pixel circuit located in the display area and a peripheral circuit located in the peripheral area.
  • the peripheral circuit can be connected to the pixel circuit through the pixel circuit.
  • the light-emitting device LD is connected, and the first power supply signal VDD is applied to the first electrode ANO of the light-emitting device LD.
  • the peripheral circuit can also be connected to the second electrode CAT of the light-emitting device LD, and the second power supply is applied to the second electrode CAT.
  • the signal VSS can control the current through the light-emitting device LD by controlling the pixel circuit, thereby controlling the brightness of the light-emitting device LD.
  • the driving backplane BP of the present disclosure can at least be divided into a pixel area AA and a control area WA outside the pixel area AA.
  • the pixel area AA is the driving backplane.
  • the area in the board BP corresponds to the display area
  • the control area WA is the area in the driving back panel BP that corresponds to the peripheral area.
  • the control area WA may include a circuit area CA and a bus area LA separated between the circuit area CA and the pixel area AA.
  • the driving backplane BP of the present disclosure may include a substrate SU and a circuit layer CL provided on one side of the substrate SU.
  • the substrate SU may be flexible such as polyimide.
  • the transparent material can also be a hard transparent material such as glass, and the substrate SU can have a multi-layer or single-layer structure.
  • the circuit layer CL may include the pixel circuit PC, gate lines, gate drive circuits, bus lines and gate connection lines, where:
  • One pixel circuit PC can be connected to at least one light-emitting device to drive the light-emitting device to emit light.
  • the gate lines GAL are at least partially located in the pixel area AA, and there are multiple gate lines GAL. Each gate line GAL extends along the row direction X and is distributed along the column direction Y. One row of pixel circuits PC is connected to at least one gate line GAL.
  • the gate driving circuit GGOAs may be disposed in the control area WA, and includes a plurality of gate shift register units GGOAs cascaded along the column direction Y. There are multiple gate connection lines GCL, and one gate shift register unit GGOAs can be connected to one gate connection line GCL, so that signals can be input to the pixel circuit PC through the gate connection line GCL and the gate line GAL. At the same time, at least part of a gate connection line GCL is in a different layer from the gate line GAL, and is connected to at least one gate line GAL through a contact hole.
  • the bus line L is provided in the bus area LA and is at least partially located between the gate driving circuit GGOA and the pixel area AA.
  • the bus line L is insulated from the gate connection line GCL.
  • the driving backplane BP in the embodiment of the present disclosure can make at least part of the gate connection line GCL connecting the gate line GAL and the gate shift register unit GGOAs and the gate line GAL be located on a different layer, so the connection needs to be realized through the contact hole, and the contact
  • the existence of the hole can increase the overall impedance of the gate connection line GCL, improve the ability to block static electricity, play a certain protective role for other circuits, and help ensure the stable transmission of electrical signals and avoid abnormal display phenomena such as black screens and flickers.
  • the gate line GAL that transmits high-frequency pulse signals it can reduce the interference of static electricity on the signal.
  • the pixel circuit PC can include multiple transistors, and can also include capacitors, which can be 3T1C, 7T1C and other pixel circuit PCs.
  • nTmC means that a pixel circuit PC includes n transistors (indicated by the letter “T") and m capacitors (indicated by the letter “C” means).
  • a 7T1C structure pixel circuit PC may include a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a writing transistor T4, a first luminescence control transistor T5, a second luminescence control transistor Transistor T6, second reset transistor T7 and storage capacitor Cst, where:
  • the gate of the first reset transistor T1 is used to receive the first reset control signal RE1.
  • the first electrode is used to receive the reset signal VI.
  • the second electrode is connected to the first plate of the gate storage capacitor Cst of the driving transistor T3 at the N1 node. , the second plate of the storage capacitor Cst is used to receive the first power signal VDD.
  • the gate of the compensation transistor T2 is used to receive the scan signal GA.
  • the first electrode and the second electrode of the driving transistor T3 are connected to the N2 node.
  • the second electrode and the gate of the driving transistor T3 are connected to the N1 node.
  • the gate electrode of the writing transistor T4 is used to receive the scan signal GA, the first electrode is used to receive the data signal DA, and the second electrode is connected to the first electrode of the driving transistor T3 at the N3 node.
  • the gate electrode of the first light emitting control transistor T5 is used to receive the light emitting control signal EM, the first electrode is used to receive the first power supply signal VDD, and the second electrode is connected to the first electrode of the driving transistor T3.
  • the gate electrode of the second light emitting control transistor T6 is used to receive the light emitting control signal EM.
  • the first electrode is connected to the second electrode of the driving transistor T3 at the N2 node, and the second electrode is connected to the first electrode of the light emitting device at the N4 node.
  • the gate electrode of the second reset transistor T7 is used to receive the reset control signal REL, the first electrode is used to receive the reset signal VI, and the second electrode is connected to the second electrode of the second light emitting control transistor T6 at the N4 node.
  • Each transistor of the pixel circuit PC can be a P-type low-temperature polysilicon transistor. Because P-type low-temperature polysilicon transistors have high carrier mobility, they are conducive to achieving high resolution, high response speed, high pixel density, and high aperture ratio. display panel. A P-type low-temperature polysilicon transistor can be turned off when a high level is input to its gate and turned on when a low level signal is input. Of course, the transistor can also be an N-type low-temperature polysilicon transistor, which is turned on at a high level. This article only takes a P-type low-temperature polysilicon transistor as an example.
  • the first reset control signal RE1 is a low-level signal
  • the first reset transistor T1 is turned on
  • the reset signal VI is written to the gate of the driving transistor T3 and the first plate of the storage capacitor Cst.
  • the scanning signal GA can turn on the writing transistor T4 and the compensation transistor T2, and write the data signal DA to the gate of the driving transistor T3 and the first plate Cst1 of the storage capacitor Cst, that is, through the N3 node and The N2 node writes the data signal DA to the N1 node until the potential reaches Vdata+vth.
  • Vdata is the voltage of the data signal Da
  • Vth is the threshold voltage of the driving transistor T3.
  • the scanning signal GA of the writing transistor T4 and the compensation transistor T2 may be the same signal.
  • the second reset control signal RE2 is a low-level signal, causing the second reset transistor T7 to be turned on, and the second reset signal VIN2 is written into the first electrode of the light-emitting device LD and the second pole of the second light-emitting control transistor T6, Reset the N4 node to implement initialization and further eliminate the influence of the data of the previous frame of image.
  • the light-emitting control signal EM is a low-level signal
  • the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on
  • the driving transistor T3 is the voltage Vdata+Vth stored in the storage capacitor Cst and the first power signal VDD.
  • the light-emitting device LD emits light.
  • the circuit layer in addition to the gate line GAL, the circuit layer also includes a power line VDL, a data line DAL, a first reset signal line VIL1 and a second reset signal line VIL1.
  • Reset signal line VIL2 where:
  • the power line VDL may extend along the column direction Y and be distributed along the row direction X, and be connected to the first light-emitting control transistor T5 and the second plate Cst2 of the storage capacitor Cst for transmitting the first power signal VDD.
  • the data line DAL may also extend along the column direction Y and be distributed along the row direction X, and be connected to the first pole of the writing transistor T4 for transmitting the data signal DA.
  • the first reset signal line VIL1 and the second reset signal line VIL2 both extend along the row direction X and are distributed along the column direction Y.
  • the first reset signal line VIL1 may be connected to the first pole of the first reset transistor T1 for transmitting the reset signal VI.
  • the second reset signal line VIL2 may be connected to the first pole of the second reset transistor T7 for transmitting the reset signal VI.
  • the two reset signals VI may be the same or different.
  • the same reset signal line can be used to simultaneously input the reset signal to the second reset transistor T7 of the n-th row pixel circuit PC and the first reset transistor T1 of the n+1-th row pixel circuit PC, also That is to say, the second reset signal line VIL2 connected to the n-th row pixel circuit PC can be multiplexed into the first reset signal line VIL1 connected to the n+1-th row pixel circuit PC.
  • the n-th row pixel circuit PC can be multiplexed
  • the first pole of the second reset transistor T7 is connected to the first pole of the first reset transistor T1 of the n+1th row pixel circuit PC, and is connected to the same reset signal line (the first reset signal line VIL1 and the second reset signal line VIL2) connection, in this way, the number of reset signal lines can be reduced.
  • the gate line GAL can be used to transmit the scan signal GA, the first reset control signal RE1, the second reset control signal RE2 and the emission control signal EM, thereby controlling the on and off of other transistors except the driving transistor T3.
  • the gate line GAL may include a first gate line GAL1, a second gate line GAL2, a third gate line GAL3, and a fourth gate line GAL4, where:
  • the first gate line GAL1 may be connected to the gates of the writing transistor T4 and the compensation transistor T2 at the same time, and simultaneously transmit the scanning signal GA to the writing transistor T4 and the compensation transistor T2.
  • the second gate line GAL2 may be connected to the gate of the first reset transistor T1 for transmitting the first reset control signal RE1.
  • the third gate line GAL3 may be connected to the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 at the same time for the light-emitting control signal EM.
  • the fourth gate line GAL4 may be connected to the gate of the second reset transistor T7 for transmitting the second reset control signal RE2.
  • the first gate line GAL1 and the fourth gate line GAL4 connected to the same pixel circuit PC can receive signals at the same time, and the signals can At the same time, it serves as the scanning signal GA and the second reset control signal RE2.
  • the first gate line GAL1 connected to the n-row pixel circuit PC can be connected to the second gate line GAL2 connected to the first reset transistor T1 of the n+1-row pixel circuit PC, so that the n-th row pixel circuit PC is in the writing stage.
  • the pixel circuit PC of the n+1th row may be in the reset stage.
  • the fourth gate line GAL4 connected to the second reset transistor T7 of the n-th row pixel circuit PC and the second gate line GAL2 connected to the first reset transistor T7 of the n+1-th row pixel circuit PC can be the same gate line GAL, that is to say, the fourth gate line GAL4 connected to the n-th row pixel circuit PC is multiplexed as the second gate line GAL2 of the n+1-th row pixel circuit PC, which is beneficial to simplifying the structure and shortening the refresh time.
  • the circuit layer CL includes a semiconductor layer SEL, a first gate insulating layer GI1, a first gate layer GAT1, a second gate insulating layer GI2, a second Gate layer GAT2, dielectric layer ILD, source and drain layer SD and flat layer PLN, among which:
  • the semiconductor layer SEL may be disposed on one side of the substrate SU and includes channels of each transistor.
  • the material of the semiconductor layer SEL may be low-temperature polysilicon or the like.
  • the channel of the second reset transistor T7 of the n-th row pixel circuit PC may be connected to the channel of the first reset transistor T1 of the n+1-th row pixel circuit PC.
  • the first gate insulating layer GI1 can cover the semiconductor layer SEL, and its material can be insulating materials such as silicon nitride and silicon oxide.
  • the first gate layer GAT1 can be disposed on the surface of the first gate insulating layer GI1 away from the substrate SU.
  • the material of the first gate layer GAT1 can be metal, some metal oxides or other conductive materials. material, and the first gate layer GAT1 may include each gate line GAL and the first plate Cst1 of the storage capacitor Cst
  • the second gate insulating layer GI2 can cover the first gate layer GAT1, and its material can be silicon nitride, silicon oxide or other insulating materials, and the material of the second gate insulating layer GI2 can be the same as the first gate insulating layer GI1.
  • the second gate layer GAT2 can be disposed on the surface of the second gate insulating layer GI2 away from the substrate SU.
  • the material of the second gate layer GAT2 can be metal, some metal oxides or other conductive materials. material, and the second gate layer GAT2 may include a first reset signal line VIL1, a second reset signal line VIL2 and a second plate Cst2.
  • the second reset signal line VIL2 connected to the n-th row pixel circuit PC is multiplexed into the first reset signal line VIL1 connected to the n+1-th row pixel circuit PC, then the channel of the second reset transistor T7 of the n-th row pixel circuit PC
  • the semiconductor layer SEL between the channel and the channel of the first reset transistor T1 of the n+1th row pixel circuit PC may be connected to the first reset signal line VIL1.
  • compensation transistor T2 may be a dual-gate transistor with two channels.
  • the second gate layer GAT2 may also include a shielding portion SL, which may be provided between the first reset signal line VIL1 and the second plate Cst2, and overlap with the area between the two channels of the compensation transistor T2, reducing the Compensates the leakage of transistor T2.
  • the dielectric layer ILD can cover the second gate layer GAT2, and the dielectric layer ILD can also be made of insulating materials such as silicon nitride and silicon oxide.
  • the source and drain layer SD is provided on the surface of the dielectric layer ILD away from the substrate SU.
  • the source and drain layer SD can be made of metal, some metal oxides or other conductive materials, and the first source and drain layer SD It may include a data line DAL and a power line VDL. At the same time, it may also include a transmission part SDc.
  • the transmission part SDc is connected to the channel of the second reset transistor T7 of the n-th row pixel circuit PC and the n+1-th row pixel circuit PC.
  • the gate drive circuit GGOA can include multiple cascaded gate shift register units GGOAs, which can provide signals for multiple rows of gate lines GAL, thereby controlling the multiple rows of gate lines GAL.
  • the connected transistors are turned on in sequence.
  • the data line provides data signals to the pixel circuit PC connected to it to form the grayscale voltage required to display each grayscale of the image, thereby controlling the brightness of the light-emitting device and displaying a frame of image.
  • the number of gate driving circuits GGOA may be one, located on one side of the pixel area AA, and the gate shift register units GGOAs may drive at least one row of pixel circuits PC; or, the number of gate driving circuits GGOA may be two, and located on one side of the pixel area AA.
  • the gate shift register units GGOAs of the two gate drive circuits GOA can be set in one-to-one correspondence, and the pixel circuit PC in the same row can simultaneously receive signals provided by the corresponding gate shift register units GGOAs on both sides.
  • the gate shift register unit GGOAs includes 8 transistors and 2 capacitors, including an input transistor T1, a first control transistor T2, a second control transistor T3, an output control transistor T4, and a gate output transistor T5. , the first noise reduction transistor T6, the second noise reduction transistor T7, the voltage stabilizing transistor T8, the first capacitor C1 and the second capacitor C2.
  • the gate shift register units GGOAs are cascaded.
  • the first pole of the input transistor T21 in the first-stage gate shift register unit GGOAs is connected to the input terminal IN.
  • the input terminal IN is used to connect to the trigger signal line GSTV to receive the trigger signal STV.
  • the first pole of the input transistor T1 in the gate shift register unit GGOAs of other levels is electrically connected to the output end of the upper-level gate shift register unit GGOAs to receive the upper-level gate shift register unit GGOAs.
  • the output signal output by the output terminal GOUT is used as an input signal, thereby realizing shift output for progressive scanning of the pixel circuit PC in the display area.
  • the gate of the input transistor T1 is connected to the first clock signal terminal CK (the first clock signal terminal CK is connected to the first sub-clock signal line GCK) to receive the first clock signal.
  • the two poles are connected to the input terminal IN, and the first pole of the input transistor T1 is connected to the first node N1.
  • the input terminal IN is connected to the trigger signal line GSTV to receive the trigger signal.
  • the gate shift register unit GGOAs of each level other than the gate shift register unit GGOAs is used, the input terminal IN is connected to the output terminal GOUT of the upper-stage gate shift register unit GGOAs.
  • the gate of the first control transistor T2 is connected to the first node N1, the second pole of the first control transistor T2 is connected to the first clock signal terminal CK to receive the first clock signal, and the first pole of the first control transistor T2 is connected to the first clock signal terminal CK.
  • the second node N2 is connected to the gate of the second control transistor T3 and the first clock signal terminal CK to receive the first clock signal, and the second pole of the second control transistor is connected to the second driving power line VGL to receive the second voltage, the first pole of the second control transistor T3 is connected to the second node N2.
  • the gate of the output control transistor T4 is connected to the second node N2, the first electrode of the output control transistor T4 is connected to the first driving power line VGH to receive the first voltage, and the second electrode of the output control transistor T4 is connected to the output terminal GOUT. .
  • the first pole of the first capacitor is connected to the second node N2, and the second pole of the first capacitor C1 is connected to the first driving power line VGH.
  • the gate of the output transistor T5 is connected to the third node N3, the first electrode of the output transistor T5 is connected to the second clock signal terminal CB, and the second electrode of the output transistor T5 is connected to the output terminal GOUT.
  • the first pole of the second capacitor C2 is connected to the third node N3, and the second pole of the second capacitor C2 is connected to the output terminal GOUT.
  • the gate electrode of the first noise reduction transistor T6 is connected to the second node N2, the first electrode of the first noise reduction transistor T6 is connected to the first driving power line VGH to receive the first voltage, and the second electrode of the first noise reduction transistor T6 is connected to the first driving power line VGH. pole is connected to the second pole of the second noise reduction transistor T7.
  • the gate of the second noise reduction transistor T7 is connected to the second clock signal terminal CB (the second clock signal terminal CB is connected to the second sub-clock signal line GCB) to receive the second clock signal.
  • One pole is connected to the first node N1.
  • the gate of the voltage stabilizing transistor T8 is connected to the second driving power line VGL to receive the second voltage, the second pole of the voltage stabilizing transistor T8 is connected to the first node N1, and the first pole of the voltage stabilizing transistor T8 is connected to the third node N3. connect.
  • the transistors in the gate shift register unit GGOAs in Figure 10 are all explained using P-type transistors as an example, that is, each transistor is turned on when the gate is connected to a low level, and is turned off when the gate is connected to a high level.
  • the first electrode of the transistor may be the source electrode
  • the second electrode of the transistor may be the drain electrode.
  • transistor and capacitor markings (T1-T8) of the circuit of the gate shift register unit GGOAs are the same as the transistor markings (T1-T4) of the pixel circuit PC above, but the same markings are used for different circuits. The same mark on a transistor does not mean the same transistor.
  • the channel of each transistor can be located on the semiconductor layer SEL, the gate of each transistor and one plate of the capacitor can be located on the first gate layer GAT1, and the other plate of the capacitor can be located on the second gate layer GAT1.
  • the first driving power line VGH, the second driving power line VGL, the trigger signal line GSTV, the first sub-clock signal line GCK and the second sub-clock signal line GCB are located on the source-drain layer SD.
  • the first driving power line VGH, the second driving power line VGL, the trigger signal line GSTV, the first sub-clock signal line GCK and the second sub-clock signal line GCB are all located on the side of the gate driving circuit GGOA away from the display area.
  • the bus L is located in the bus area LA, and is connected to the lead-out area BA.
  • the bus L can at least include the power bus LVD and the reset bus LVI.
  • Each power line VDL is connected to the power bus LVD. connected to simultaneously transmit the first power supply signal VDD.
  • the reset bus LVI can be connected to the first reset signal line VIL1 and the second reset signal line VIL2 for transmitting the reset signal VI.
  • the bus L can also include a test bus LT, which can transmit test signals for testing the display effect of the display panel.
  • the peripheral area can also have a test unit connected to the test bus LT for sending out test signals. .
  • the test bus LT may be located on the side of the reset bus LVI away from the display area.
  • the number of test buses LT may be multiple, for example, two, and they may be distributed at intervals on the side of the reset bus LVI away from the display area.
  • the power bus LVD can be located on the side of the reset bus LVI close to the display area.
  • the space occupied by the power bus LVD can be reduced by shortening it, so that the range of the peripheral area can be narrowed, for example:
  • the control area WA of the driving backplane may include a lead-out area BA.
  • the lead-out area BA may extend along the row direction X and be spaced apart from the pixel area AA along the column direction Y.
  • the lead-out area BA may be provided with a binding area, each bus L, data line DAL, power line VDL, and the above-mentioned first driving power line VGH, second driving power line VGL, trigger signal line GSTV, and first sub-clock signal line GCK and the second sub-clock signal line GCB can be connected to the binding area of the lead-out area BA so as to be bound to the flexible circuit board through the binding area, and the flexible circuit board can be equipped with a control chip and can be bound to a control motherboard.
  • the display panel can be controlled through the control chip and the control motherboard to realize functions such as image display and testing.
  • the bus area LA may include a side bus area LA1 distributed along the row direction X and on both sides of the pixel area AA and connected to the two side bus areas.
  • the connection bus area LA2 between LA1 can be located between the lead-out area BA and the pixel area AA.
  • Both the reset bus LVI and the test bus LT can have a connection bus area LA2 extending to the two side bus areas LA1.
  • the width of the reset bus LVI can be greater than the width of other buses L, and its power bus LVD can be the bus L closest to the pixel area AA among the buses L, that is, there is no other bus L between the power bus LVD and the pixel area AA.
  • the power bus LVD can only be located in the connection bus area LA2 and not extend into the side bus area LA1, which is beneficial to narrowing the width of the peripheral area in the row direction X and increasing the screen-to-body ratio.
  • the power bus LVD may extend into the side bus area LA1 and surround the outside of the pixel area AA.
  • gate connection lines GCL there are multiple gate connection lines GCL, and one gate shift register unit GGOAs can be connected to one gate connection line GCL, and one gate connection line GCL can be connected to at least one gate line GAL. Therefore, signals can be input to the pixel circuit PC through the gate connection line GCL and the gate line GAL. At the same time, at least part of the gate connection line GCL is in a different layer from the gate line GAL and is connected to the gate line GAL through the contact hole. That is to say, in the process of connecting the gate connection line GCL to the gate line GAL, it needs to be switched through the contact hole.
  • the gate connection line GCL connected to the first gate line GAL1, the second gate line GAL2 and the fourth gate line GAL4, due to the higher frequency of the pulse signal it transmits, it can satisfy different reset stages and writing stages. and the requirements of the light-emitting stage, and this high-frequency pulse signal is more susceptible to the influence of static electricity.
  • the interference of static electricity can be weakened.
  • the first gate line GAL1 connected to the n-row pixel circuit PC and the first reset connected to the n+1-row pixel circuit PC can be
  • the second gate line GAL2 of the transistor T1 is connected to the same gate shift register unit GGOAs through the same gate connection line GCL.
  • This connection method allows the first gate line GAL1 and the fourth gate line GAL4 connected to the same pixel circuit PC to be connected through the same gate.
  • Line GCL is connected to the same gate shift register cell GGOAs.
  • the gate connection line GCL may include a first connection part GCL1 and a second connection part GCL2 connected to each other.
  • the first connection part GCL1 may be connected to the gate shift register unit GGOAs (output terminal GOUT), And passing through the bus area LA, the second connection part GCL2 may be located in the pixel area AA or the bus area LA and be connected to at least one gate line GAL. At least one of the first connection part GCL1 and the second connection part GCL2 is in a different layer from the gate line GAL.
  • the first connection part GCL1 and the gate line GAL are arranged on the same layer, and the second connection part GCL2 and the gate line GAL are on different layers.
  • the first connection portion GCL1 is located on the first gate layer GAT1
  • the second connection portion GCL2 can be located on the source and drain layer SD or the second gate layer GAT2, as long as it can be connected to the gate line GAL through the contact hole.
  • the first connection part GCL1 may extend along the row direction X and be connected to the output end of the gate shift register unit GGOAs through the contact hole. , and is connected to the second gate line GAL2. Since the first connection portion GCL1 and the gate line GAL are arranged on the same layer, they can be formed into an integrated structure with the second gate line GAL2.
  • the second connection part GCL2 is located on the source and drain layer SD and extends along the column direction Y.
  • the second connection part GCL2 can be connected to the first connection part GCL1 through the contact hole, and is connected to the first gate line GAL1 through the contact hole.
  • the second connection part GCL2 may be located in the display area and between the reset bus LVI and the column of pixel circuits PC closest to the bus area LA. That is, the second connection part GCL2 is located on the side of the reset bus LVI away from the test bus.
  • the first connection part GCL1 passes through the bus area LA along the row direction X and overlaps with each bus L.
  • the second connection part GCL2 is arranged adjacent to the reset bus LVI, that is, there is no other wiring between the reset bus LVI and the second connection part GCL2.
  • the distance between the second connection part GCL2 and the reset bus line LVI along the row direction X may be 3 ⁇ m-10 ⁇ m, for example, the distance may be 4.5 ⁇ m.
  • it can prevent the second connection part GCL2 from being too close to the reset bus LVI, causing the parasitic capacitance to increase too much, which is beneficial to reducing power consumption.
  • it can prevent the distance from being too far, causing the width of the peripheral area to increase too much. It is not conducive to reducing the border width.
  • the width of the second connection part GCL2 is 20%-40% of the width of the reset bus.
  • the width of the second connection part GCL2 is 3.5 ⁇ m, and the width of the reset bus is 10 ⁇ m.
  • connection method and film layer of the first connection part GCL1 and the second connection part GCL2 are the same as the above-mentioned first embodiment, and will not be detailed here. narrate.
  • the difference is that the second connection part GCL2 can be located in the bus area LA, but in order to avoid a short circuit with the bus L, it can be set apart from the bus L, for example, between a test bus LT and a reset bus LVI.
  • connection method of the first connection part GCL1 and the second connection part GCL2 is the same as the above-mentioned first and second embodiments, and will not be described in detail here. .
  • the difference is that the second connection part GCL2 is located on the second gate layer GAT2 and extends along the column direction Y.
  • the second connection part GCL2 can be connected to the first connection part GCL1 through the contact hole, and to the first gate line through the contact hole. GAL1 connection.
  • the second connection part GCL2 can be located in the display area and between the reset bus LVI and the column of pixel circuits PC closest to the bus area LA; or it can also be located in the bus area LA and spaced apart from the bus L.
  • the first connection part GCL1 can also be located on the second gate layer GAT2, and the second connection part GCL2 is on the same layer as the gate line, that is, located on the first gate layer.
  • the first connection part GCL1 may pass through the bus area LA along the row direction
  • the second connection part GCL2 may be connected to the first gate line GAL1.
  • both ends of the second connection part GCL2 can be in contact with the first gate line GAL1 and the second gate line GAL2 respectively.
  • holes are connected, and the second connection part GCL2 can be connected to the first connection part GCL1 through contact holes. That is to say, the second connection part GCL2 is provided with at least three contact holes.
  • the circuit layer CL may also include a light-shielding layer, which may be disposed on one side of the substrate SU and covered by an insulating layer, and the semiconductor layer SEL may be disposed on a side of the insulating layer away from the substrate SU. one side.
  • the light-shielding layer may have a light-shielding portion that overlaps with the channel of the driving transistor to block light from irradiating the driving transistor.
  • the second connection part GCL2 may be located on the light shielding layer.
  • the gate connection line GCL may not be limited to the structures of the first connection part GCL1 and the second connection part GCL2 described above, and may include more line segments, at least part of which are located on the first The gate layer GAT1, and the others can be located in at least one of the second gate layer GAT2 and the source and drain layer SD, as long as the connection between the gate shift register unit GGOAs and the first gate line GAL1 and the second gate line GAL2 can be realized, It only needs to be that they are not in direct contact with the bus, so I won’t list them one by one here.
  • the gate connection line GCL is located on the same layer.
  • its first connection portion GCL1 and its second connection portion GCL2 are provided on the same layer, but are on a different layer from the gate line and the bus line, so they need to be connected through contacts.
  • the holes are connected to the grid lines.
  • the gate connection line GCL is located on the second gate layer GAT2, and its first connection portion GCL1 can extend along the row direction X and pass through the bus area LA, and It is connected to the gate shift register unit GGOAs and is connected to the second gate line GAL2 through the contact hole.
  • the second connection part GCL2 and the first connection part GCL1 have an integrated structure and extend along the column direction Y and are connected to the first gate line GAL1 Connection via contact holes.
  • the circuit layer CL may also include a light-shielding layer, which may be disposed on one side of the substrate and covered by an insulating layer, and the semiconductor layer SEL may be disposed on a side of the insulating layer away from the substrate SU. side.
  • the light-shielding layer may have a light-shielding portion that overlaps with the channel of the driving transistor to block light from irradiating the driving transistor.
  • the gate connection line GCL may be located on the light-shielding layer, and its specific structure and connection method may refer to the first embodiment of the second category, which will not be described in detail here.
  • the circuit layer CL also includes a light emission control circuit EGOA, which may be provided in the control area WA.
  • the light-emitting control circuit EGOA includes a plurality of light-emitting shift register units EGOAs cascaded along the column direction Y.
  • the structure and working principle of the light-emitting shift register units EGOAs are similar to the gate shift register units GGOAs, which can control the light emission of each row of pixel circuits PC.
  • the control transistors are turned on and off in sequence.
  • the light-emitting shift register unit EGOAs may be connected to the third gate line GAL3 and output the light-emitting control signal EM to the third gate line GAL3.
  • the light-emitting shift register units EGOAs may be connected to the third gate line GAL3 to which the two rows of pixel circuits PC are connected.
  • the light emission control circuit EGOA may be located on a side of the gate driving circuit GGOA away from the pixel area AA, that is, outside the gate driving circuit GGOA, and is connected to the gate driving circuit EGOA.
  • GGOA is distributed at intervals.
  • the number of the light-emitting control circuit EGOA and the gate driving circuit GGOA is both two, and the gate driving circuit GGOA is separated on both sides of the pixel area AA, and the light-emitting control circuit EGOA is located outside the gate driving circuit GGOA.
  • a row of pixel circuits PC can be connected to two light-emitting shift register units EGOAs and two gate shift register units GGOAs to prevent the response speed of the same row of pixel circuits PC from being too different due to signal attenuation.
  • the number of the light emitting control circuit EGOA and the gate driving circuit GGOA can be one, and can be separated on both sides of the pixel area AA, as long as signals can be transmitted to each row of pixel circuits PC. That is, it will help shorten the width of the control area to reduce the border.
  • the circuit layer CL may also include a plurality of light-emitting connection lines ECL.
  • One light-emitting shift register unit EGOAs is connected to one light-emitting connection line ECL, and one light-emitting connection line ECL At least part of the region is located on a different layer from the third gate line GAL3, and is connected to a third gate line GAL3 through a contact hole.
  • the resistance can be increased by introducing a contact hole, thereby improving the The ability to block static electricity.
  • the light-emitting connection line CGL may include a third connection part CGL1 and a fourth connection part CGL2.
  • the third connection part CGL1 is provided in the same layer as the gate line GAL, that is, located on the first gate layer.
  • GAT1 and the third connection part CGL1 is connected to the light-emitting shift register unit EGOAs and passes through the bus area LA in the direction.
  • the fourth connection part CGL2 is located on the source and drain layer SD or the second gate electrode layer GAT2, and is connected to the third connection part CGL1 and the third gate line GAL3 through the contact hole.
  • the light-emitting connection line ECL may be located on the second gate layer GAT2 and connected to the light-emitting shift register unit EGOAs and the third gate line GAL3 through the contact hole.
  • the structure and connection method of the light-emitting connection line ECL can refer to the gate connection line GCL mentioned above, the third connection part ECL1 can refer to the first connection part GCL1, and the fourth connection part ECL2 can refer to GCL2, as long as the resistance can be increased through the contact hole.
  • the light-emitting connection line ECL cannot be in direct contact with the bus line L and the gate connection line GCL to avoid short circuit.
  • the reset signal lines (the second reset signal line VIL2 connected to the pixel circuit PC of the nth row and the first reset signal line VIL1 connected to the pixel circuit PC of the n+1th row) are arranged along the row. Extends in the direction , and the reset connection line RCL is connected to the reset bus line LVI, the reset signal line can be located on the second gate layer GAT2, and is connected to the reset connection line RCL through the contact hole.
  • the reset connection line RCL overlaps the fourth connection part CGL2 and the second connection part GCL2 but can maintain insulation.
  • connection between the reset signal line and the reset bus LVI can also be achieved by using the reset connection line RCL of other film layers, as long as the short circuit with the fourth connection part CGL2 and the second connection part GCL2 can be avoided.
  • an embodiment of the present disclosure provides a display panel, which may include a driving backplane BP and a light emitting device LD, wherein:
  • the driving backplane BP can be the driving backplane BP in any of the above embodiments, and its structure will not be described in detail here.
  • the light emitting device LD may be disposed on a side of the circuit layer CL away from the substrate SU and connected to the pixel circuit PC. There can be multiple light-emitting devices LD, and each light-emitting device LD can be connected to a pixel circuit PC, and the same pixel circuit PC can be connected to one or more light-emitting devices LD.
  • the light-emitting device LD may be an OLED (organic light-emitting diode), a QLED (quantum dot light-emitting diode), a Micro LED or a Mini LED, etc., and may include a first electrode ANO, a second electrode CAT and a second electrode located between the first electrode ANO and the second electrode The luminescent layer EL between CAT,
  • the first electrode ANO can be disposed on the surface of the circuit layer CL away from the substrate SU, for example, the second flat layer PLN2 is on the surface away from the substrate SU, and the light-emitting layer EL can include layers stacked in a direction away from the driving backplane BP. Hole injection layer, hole transport layer, luminescent material layer, electron transport layer and electron injection layer.
  • Each light-emitting device LD can share the second electrode CAT. That is to say, the second electrode CAT can be a continuous whole-layer structure, and the second electrode CAT can extend to the peripheral area and can receive the second power signal VSS.
  • the first electrode ANO is distributed in an array to ensure that each light-emitting device LD can emit light independently.
  • a pixel definition layer PDL can be provided on the surface where the first electrode ANO is provided, which can have openings exposing each first electrode ANO, and the light-emitting layer EL is connected to the first electrode ANO in the opening.
  • One electrode ANO is stacked.
  • Each light-emitting device LD can at least share a light-emitting material layer, so that the light-emitting color of each light-emitting device LD is the same.
  • a color film layer can be provided on the side of the light-emitting device LD away from the substrate SU. Through the color film layer The filter part corresponding to each light-emitting device LD realizes color display.
  • the light-emitting material layers of each light-emitting device LD can also be made independent, so that the light-emitting device LD can directly emit monochromatic light, and the light-emitting colors of different light-emitting devices LD can be different, thereby achieving color display.
  • the display panel may also include an encapsulation layer covering each light-emitting device LD, and may also include other film layers such as a touch layer and a transparent cover plate disposed on a side of the encapsulation layer away from the substrate SU, which will not be described in detail here.
  • the present disclosure also provides a display device, which may include the display panel of any of the above embodiments.
  • the display panel is a display panel according to any of the above embodiments.
  • the display device of the present disclosure can be an electronic device with a display function such as a mobile phone, a tablet computer, a television, etc., which will not be listed here.

Abstract

一种驱动背板、显示面板及显示装置。驱动背板(BP)具有像素区(AA)和包括电路区(CA)和总线区(LA)的控制区(WA)；驱动背板(BP)包括衬底(SU)和电路层(CL)，电路层(CL)包括多个像素电路(PC)；一行像素电路(PC)与至少一个栅线(GAL)连接；栅极驱动电路(GGOA)设于控制区(WA)且包括级联的多个栅移位寄存器单元(GGOAs)；总线(L)设于总线区(LA)内且至少部分位于栅极驱动电路(GGOA)和像素区(AA)之间；一栅移位寄存器单元(GGOAs)与一栅连接线(GCL)连接，一栅连接线(GCL)的至少部分区域与栅线(GAL)不同层，且通过接触孔与至少一栅线(GAL)连接；栅连接线(GCL)与总线(L)绝缘设置。

Description

驱动背板、显示面板及显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种驱动背板、显示面板及显示装置。
背景技术
OLED(有机电致发光二极管)显示面板具有自发光、广色域、高对比度、可柔性化、高响应可柔性化等优点，具有广泛的应用前景。但是，现有显示面板可能会出现黑屏、闪烁等显示画面异常的现象。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开提供一种驱动背板、显示面板及显示装置。
根据本公开的一个方面，提供一种驱动背板，所述驱动背板具有像素区和所述像素区外的控制区，所述控制区包括电路区和分隔于所述电路区和所述像素区之间的总线区；所述电路层包括：
多个像素电路，阵列分布于所述像素区；
多个栅线，沿行方向延伸，且沿列方向分布，一行所述像素电路与至少一个所述栅线连接；
栅极驱动电路，设于所述控制区，且包括沿列方向级联的多个栅移位寄存器单元；
总线，设于所述总线区内，且至少部分位于所述栅极驱动电路和所述像素区之间，所述总线位于所述栅线远离所述衬底的一侧；
多个栅连接线，一所述栅移位寄存器单元与一所述栅连接线连接，一所述栅连接线的至少部分区域与所述栅线不同层，且通过接触孔与至少一所述栅线连接；所述栅连接线与所述总线绝缘设置。
在本公开的一种示例性实施方式中，所述栅连接线包括相互连接的 第一连接部和第二连接部，所述第一连接部与所述栅移位寄存器单元连接，且穿过所述总线区，所述第二连接部与所述总线和所述像素电路间隔分布，且与至少一所述栅线连接；所述第一连接部和所述第二连接部中至少一个与所述栅线不同层。
在本公开的一种示例性实施方式中，所述第一连接部与所述栅线同层设置，所述第二连接部与所述栅线不同层。
在本公开的一种示例性实施方式中，所述第一连接部和所述第二连接部同层设置，且与所述栅线和所述总线不同层。
在本公开的一种示例性实施方式中，所述电路层还包括电源线、数据线和复位信号线，所述电源线和所述数据线均沿列方向延伸，且沿所述行方向分布，所述电源线和所述数据线与所述总线同层设置；所述复位信号线沿所述行方向延伸，且沿列方向分布，所述复位信号线与所述栅线和所述总线位于不同层；
所述栅线包括第一栅线和第二栅线；
所述像素电路包括存储电容和多个晶体管，所述晶体管包括驱动晶体管、写入晶体管、补偿晶体管和第一复位晶体管；所述补偿晶体管和所述写入晶体管的栅极与所述第一栅线连接；所述驱动晶体管的第一极与电源线连接，第二极与发光器件连接；所述补偿晶体管连接所述驱动晶体管的第二极和栅极；所述写入晶体管的第一极与所述数据线连接，第二极与所述驱动晶体管的第一极连接；所述第一复位晶体管的栅极与所述第二栅线连接，第一极与所述复位信号线连接，第二极与所述驱动晶体管的栅极连接；所述存储电容的第一极板与所述驱动晶体管的栅极连接，第二极板与所述电源线连接；
连接第n行所述像素电路的第一栅线和连接第n+1行所述像素电路的第二栅线通过同一所述栅连接线与同一所述栅移位寄存器单元连接。
在本公开的一种示例性实施方式中，所述电路层包括：
半导体层，设于所述衬底一侧，且包括各所述晶体管的沟道；
第一栅绝缘层，覆盖所述半导体层；
第一栅极层，设于所述第一栅绝缘层远离所述衬底的表面，且包括所述栅线、所述第一极板和各所述晶体管的栅极；
第二栅绝缘层，覆盖所述第一栅极层；
第二栅极层，设于所述第二栅绝缘层远离所述衬底的表面，且包括所述第二极板和所述复位信号线；
介电层，覆盖所述第二栅极层；
源漏层，设于所述介电层远离所述衬底的一侧，且包括所述总线、所述电源线和所述数据线。
在本公开的一种示例性实施方式中，若所述第一连接部与所述栅线同层设置，且与所述第二连接部不同层：
所述第一连接部与所述第二栅线连接；所述第二连接部位于所述源漏层，且沿所述列方向延伸，所述第二连接部通过接触孔与所述第一栅线连接。
在本公开的一种示例性实施方式中，若所述第一连接部和所述第二连接部同层设置：
所述栅连接线位于所述第二栅极层。
在本公开的一种示例性实施方式中，所述第一连接部通过接触孔与所述栅移位寄存器单元和所述第二栅线连接；所述第二连接部沿列方向延伸，且与所述第一连接部连接，所述第二连接部通过接触孔与所述第一栅线连接。
在本公开的一种示例性实施方式中，所述栅线还包括第三栅线；所述像素电路还包括第二复位晶体管、第一发光控制晶体管和第二发光控制晶体管；
所述第一发光控制晶体管的栅极与第三栅线连接，第一极与所述电源线连接，第二极与所述驱动晶体管的第一极连接；
所述第二发光控制晶体管的栅极与所述第三栅线连接，第一极与所述驱动晶体管的第二极连接，第二极与所述发光器件连接；
所述第二复位晶体管的栅极与所述第一栅线连接，第一极与所述复位信号线连接，第二极与所述第二发光控制晶体管的第二极连接。
在本公开的一种示例性实施方式中，所述电路层还包括：
发光控制电路，设于所述控制区，所述发光控制电路包括沿列方向级联的多个发光移位寄存器单元；
多个发光连接线，一所述发光移位寄存器单元与一所述发光连接线连接，一所述发光连接线的至少部分区域与所述第三栅线位于不同层，且通过接触孔与一所述第三栅线连接。
在本公开的一种示例性实施方式中，所述发光连接线位于所述第二栅极层，且通过接触孔与所述发光移位寄存器单元和所述第三栅线连接。
在本公开的一种示例性实施方式中，所述发光连接线包括第三连接部和第四连接部，所述第三连接部与所述栅线同层设置，且与所述发光移位寄存器单元连接，所述第三连接部沿所述方向穿过所述总线区；所述第四连接部位于所述源漏层或第二栅极层，且通过接触孔与所述第三连接部和所述第三栅线连接。
在本公开的一种示例性实施方式中，第n行所述像素电路的第二复位晶体管与第n+1行所述像素电路的第二栅线连接。
在本公开的一种示例性实施方式中，所述总线包括位于源漏层的测试总线、复位总线和电源总线，所述电源线与所述电源总线连接，所述复位信号线与所述复位总线连接。
在本公开的一种示例性实施方式中，所述复位总线位于所述测试总线和所述像素区之间，所述第二连接部位于所述复位总线远离所述测试总线的一侧，且与所述复位总线相邻设置；所述第二连接部与所述复位总线沿行方向的距离为3μm-10μm。
在本公开的一种示例性实施方式中，所述第二连接部的宽度为所述复位总线的宽度的20％-40％。
在本公开的一种示例性实施方式中，所述驱动背板控制区包括引出区，所述引出区沿所述行方向延伸，且与所述像素区沿列方向间隔分布；所述总线、所述数据线和所述电源线均连接至所述引出区；
所述总线区包括沿行方向分布于所述像素区两侧的侧总线区和连接于两所述侧总线区之间的连接总线区，所述连接总线区位于所述引出区和所述像素区之间；
所述电源总线位于所述连接总线区内。
根据本公开的一个方面，提供一种显示面板，包括上述任意一项所述的驱动背板。
根据本公开的一个方面，提供一种显示装置，包括上述任意一项所述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开显示面板一实施方式的局部截面示意图。
图2为本公开驱动背板一实施方式中各区域的分布示意图。
图3为本公开驱动背板一实施方式中电路分布示意图。
图4为本公开驱动背板一实施方式中像素电路的原理图。
图5为本公开驱动背板一实施方式中半导体层的局部俯视图。
图6为本公开驱动背板一实施方式中第一栅极层的局部俯视图。
图7为本公开驱动背板一实施方式中第二栅极层的局部俯视图。
图8为本公开驱动背板一实施方式中源漏层的局部俯视图。
图9为本公开驱动背板一实施方式中像素电路的局部俯视图。
图10为本公开驱动背板一实施方式中栅移位寄存器单元的原理图。
图11为本公开驱动背板的第一类的第一实施方式的局部示意图。
图12为本公开驱动背板的第一类的第二实施方式的局部示意图。
图13为本公开驱动背板的第一类的第三实施方式的局部示意图。
图14为本公开驱动背板的第一类的第四实施方式的局部示意图。
图15为本公开驱动背板的第二类的第一实施方式的局部示意图。
图16为本公开驱动背板另一实施方式中电路分布示意图。
图17为本公开驱动背板的电源总线的一种实施方式的局部示意图。
图18为本公开驱动背板的电源总线的另一种实施方式的局部示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
本文中的行方向X和列方向Y仅为两个相互垂直的方向，在本公开的附图中，行方向X可以是横向，列方向Y可以是纵向，但并不限于此，若显示面板发生旋转，则行方向X和列方向Y的实际朝向可能发生变化。
本文中的A特征和B特征“交叠”是指A特征在衬底上的正投影和B特征在衬底上的正投影至少部分重合。文中的A特征和B特征“不交叠”是指A特征在衬底上的正投影和B特征在衬底上的正投影的重叠区域的面积为零。
本文中的A特征和B特征“同层”是指A特征和B特征可以同时形成。A特征和B特征“不同层”是指A特征和B特征在垂直于衬底的方向上间隔分布，且二者被其它膜层分隔。
如图2所示，本公开的显示面板可包括驱动背板BP和设于驱动背板BP一侧的发光器件LD，通过驱动背板BP中的驱动电路可驱动发光器件LD发光，以显示图像。
发光器件LD可以是OLED(有机发光二极管)、QLED(量子点发光二极管)、Micro LED或Mini LED等，其可以包括第一电极ANO、第二电极CAT和位于第一电极ANO和第二电极CAT间的发光层EL。
显示面板至少可划分为可发光的显示区和显示区外的不发光的外围区，驱动电路可包括位于显示区内的像素电路和位于外围区的外围电路， 外围电路一方面可通过像素电路与发光器件LD连接，向发光器件LD的第一电极ANO施加第一电源信号VDD，另一方面，外围电路也可与发光器件LD的第二电极CAT连接，并向第二电极CAT施加第二电源信号VSS，通过控制像素电路可控制通过发光器件LD的电流，从而控制发光器件LD的亮度。
如图1和图2所示，基于上述对显示面板的划分，相应的，本公开的驱动背板BP至少可划分出像素区AA和像素区AA外的控制区WA，像素区AA为驱动背板BP中对应于显示区的区域，控制区WA为驱动背板BP中对应于外围区的区域。进一步的，控制区WA可包括电路区CA和分隔于电路区CA和像素区AA之间的总线区LA。
如图1-3以及图11-图15所示，本公开的驱动背板BP可包括衬底SU和设于衬底SU一侧的电路层CL，衬底SU可为聚酰亚胺等柔性透明材质，也可以是玻璃等硬质透明材质，且衬底SU可以是多层或单层结构。电路层CL可包括像素电路PC、栅线、栅极驱动电路、总线和栅连接线，其中：
像素电路PC的数量为多个，且阵列分布于像素区AA，从而得到多行和多列像素电路PC，一像素电路PC可与至少一发光器件连接，用于驱动发光器件发光。
栅线GAL至少部分位于像素区AA，且其数量有多个，各栅线GAL均沿行方向X延伸，且沿列方向Y分布，一行像素电路PC与至少一个栅线GAL连接。
栅极驱动电路GGOA可设于控制区WA，且包括沿列方向Y级联的多个栅移位寄存器单元GGOAs。栅连接线GCL的数量有多个，且一栅移位寄存器单元GGOAs可与一栅连接线GCL连接，从而可通过栅连接线GCL和栅线GAL向像素电路PC输入信号。同时，一栅连接线GCL的至少部分区域与栅线GAL不同层，且通过接触孔与至少一栅线GAL连接。
总线L设于总线区LA内，且至少部分位于栅极驱动电路GGOA和像素区AA之间，总线L与栅连接线GCL绝缘设置。
本公开实施方式的驱动背板BP，可使连接栅线GAL和栅移位寄存 器单元GGOAs的栅连接线GCL的至少部分区域与栅线GAL位于不同层，从而需要通过接触孔实现连接，而接触孔的存在可以增大栅连接线GCL整体的阻抗，可提高阻挡静电的能力，对其它电路起到一定的保护作用，有利于保证电信号的稳定传输，避免出现黑屏、闪烁等显示异常现象，特别是针对传输高频脉冲信号的栅线GAL而言，可以减弱静电对信号的干扰。
下面对像素电路PC和驱动电路进行详细说明：
像素电路PC可包括多个晶体管，还可以包括电容，其可以是3T1C、7T1C等像素电路PC，nTmC表示一个像素电路PC包括n个晶体管(用字母“T”表示)和m个电容(用字母“C”表示)。
如图4所示，以一个7T1C结构的像素电路PC为例，其可包括第一复位晶体管T1、补偿晶体管T2、驱动晶体管T3、写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6、第二复位晶体管T7和存储电容Cst，其中：
第一复位晶体管T1的栅极用于接收第一复位控制信号RE1，第一极用于接收复位信号VI，第二极与驱动晶体管T3的栅极存储电容Cst的第一极板连接于N1节点，存储电容Cst的第二极板用于接收第一电源信号VDD。补偿晶体管T2的栅极用于接收扫描信号GA，第一极与驱动晶体管T3的第二极连接于N2节点，第二极与驱动晶体管T3的栅极连接于N1节点。写入晶体管T4的栅极用于接收扫描信号GA，第一极用于接收数据信号DA，第二极与驱动晶体管T3的第一极连接于N3节点。第一发光控制晶体管T5的栅极用于接收发光控制信号EM，第一极用于接收第一电源信号VDD，第二极与驱动晶体管T3的第一极连接。第二发光控制晶体管T6的栅极用于接收发光控制信号EM，第一极与驱动晶体管T3的第二极连接于N2节点，第二极与发光器件的第一电极连接于N4节点。第二复位晶体管T7的栅极用于接收复位控制信号REL，第一极用于接收复位信号VI，第二极与第二发光控制晶体管T6的第二极连接于N4节点。
下面对像素电路PC的工作原理进行说明：
像素电路PC的各晶体管均可以为P型低温多晶硅晶体管，因P型 低温多晶硅晶体管具有较高的载流子迁移率，从而有利于实现高分辨率、高反应速度、高像素密度、高开口率的显示面板。P型低温多晶硅晶体管可在向其栅极输入高电平时关断，在输入低电平信号时导通。当然，晶体管也可以是N型低温多晶硅晶体管，在高电平时导通，本文中仅以P型低温多晶体硅晶体管为例进行说明。
在复位阶段：第一复位控制信号RE1为低电平信号，第一复位晶体管T1导通，驱动晶体管T3的栅极和存储电容Cst的第一极板被写入复位信号VI。由此，对N1节点进行复位，实现初始化，消除上一帧图像的数据的影响。
在写入阶段：通过扫描信号GA可使写入晶体管T4和补偿晶体管T2导通，向驱动晶体管T3的栅极和存储电容Cst的第一极板Cst1写入数据信号DA，即经过N3节点和N2节点向N1节点写入数据信号DA，直至电位达到Vdata+vth。其中，Vdata为数据信号Da的电压，Vth为驱动晶体管T3的阈值电压。写入晶体管T4和补偿晶体管T2的扫描信号GA可为同一信号。同时，第二复位控制信号RE2为低电平信号，使第二复位晶体管T7导通，发光器件LD的第一电极和第二发光控制晶体管T6的第二极被写入第二复位信号VIN2，对N4节点进行复位，实现初始化，进一步消除上一帧图像的数据的影响。
在发光阶段：发光控制信号EM为低电平信号，第一发光控制晶体管T5和第二发光控制晶体管T6导通，驱动晶体管T3在存储电容Cst存储的电压Vdata+Vth和第一电源信号VDD的作用下导通，此时，发光器件LD发光。
进一步的，如图3、图5-图9所示，为了便于向像素电路PC输入信号，电路层除了栅线GAL，还包括电源线VDL、数据线DAL、第一复位信号线VIL1和第二复位信号线VIL2，其中：
电源线VDL可沿列方向Y延伸，且沿行方向X分布，并与第一发光控制晶体管T5和存储电容Cst的第二极板Cst2连接，用于传输第一电源信号VDD。数据线DAL也可沿列方向Y延伸，并沿行方向X分布，且与写入晶体管T4的第一极连接，用于传输数据信号DA。
第一复位信号线VIL1和第二复位信号线VIL2均沿行方向X延伸， 且沿列方向Y分布。第一复位信号线VIL1可与第一复位晶体管T1的第一极连接，用于传输复位信号VI。第二复位信号线VIL2可与第二复位晶体管T7的第一极连接，用于传输复位信号VI，两复位信号VI可以相同，也可以不同。
为了简化结构，在一些实施方式中，可利用同一复位信号线同时向第n行像素电路PC的第二复位晶体管T7和第n+1行像素电路PC的第一复位晶体管T1输入复位信号，也就是说，可将连接第n行像素电路PC的第二复位信号线VIL2复用为连接第n+1行像素电路PC的第一复位信号线VIL1，为此，可使第n行像素电路PC的第二复位晶体管T7的第一极与第n+1行像素电路PC的第一复位晶体管T1的第一极连接，且与同一复位信号线(第一复位信号线VIL1和第二复位信号线VIL2)连接，如此一来，可以减少复位信号线的数量。
栅线GAL的数量可以有多个，且均沿行方向X延伸，并沿列方向Y分布。栅线GAL可用于传输扫描信号GA、第一复位控制信号RE1、第二复位控制信号RE2和发光控制信号EM，从而可控制除驱动晶体管T3外的其它晶体管的导通和关断。例如，栅线GAL可包括第一栅线GAL1、第二栅线GAL2、第三栅线GAL3以及第四栅线GAL4，其中：
第一栅线GAL1可同时与写入晶体管T4和补偿晶体管T2的栅极连接，同时向写入晶体管T4和补偿晶体管T2传输扫描信号GA。第二栅线GAL2可与第一复位晶体管T1的栅极连接，用于传输第一复位控制信号RE1。第三栅线GAL3可同时与第一发光控制晶体管T5和第二发光控制晶体管T6的栅极连接，用于发光控制信号EM。第四栅线GAL4可与第二复位晶体管T7的栅极连接，用于传输第二复位控制信号RE2。
由于写入晶体管T4、补偿晶体管T2与第二复位晶体管T2均在发光阶段导通，因而，可使连接同一像素电路PC的第一栅线GAL1和第四栅线GAL4同时接收信号，该信号可同时作为扫描信号GA和第二复位控制信号RE2。同时，可使连接n行像素电路PC的第一栅线GAL1和连接n+1行像素电路PC的第一复位晶体管T1的第二栅线GAL2连接，使得第n行像素电路PC处于写入阶段的同时，第n+1行像素电路PC可处于复位阶段。
基于此，可使第n行像素电路PC的第二复位晶体管T7连接的第四栅线GAL4与第n+1行像素电路PC的第一复位晶体管T7连接的第二栅线GAL2是同一栅线GAL，也就是说，连接第n行像素电路PC的第四栅线GAL4复用为第n+1行像素电路PC的第二栅线GAL2，有利于简化结构，缩短刷新时间。
基于上述的像素电路PC，在一些实施方式中，如图2所示，电路层CL包括半导体层SEL、第一栅绝缘层GI1、第一栅极层GAT1、第二栅绝缘层GI2、第二栅极层GAT2、介电层ILD、源漏层SD和平坦层PLN，其中：
如图5和图9所示，半导体层SEL可设于衬底SU一侧，且包括各晶体管的沟道，半导体层SEL的材料可以是低温多晶硅等。其中，第n行像素电路PC的第二复位晶体管T7的沟道可与第n+1行像素电路PC的第一复位晶体管T1的沟道连接。
第一栅绝缘层GI1可覆盖半导体层SEL，其材料可采用氮化硅、氧化硅等绝缘材料。
如图6和图9所示，第一栅极层GAT1可设于第一栅绝缘层GI1远离衬底SU的表面，第一栅极层GAT1的材料可采用金属、一些金属氧化物或其它导电材料，且第一栅极层GAT1可包括各个栅线GAL和存储电容Cst的第一极板Cst1
第二栅绝缘层GI2可覆盖第一栅极层GAT1，其材料可采用氮化硅、氧化硅等绝缘材料，且第二栅绝缘层GI2的材料可与第一栅绝缘层GI1相同。
如图7和图9所示，第二栅极层GAT2可设于第二栅绝缘层GI2远离衬底SU的表面，第二栅极层GAT2的材料可采用金属、一些金属氧化物或其它导电材料，且第二栅极层GAT2可包括第一复位信号线VIL1、第二复位信号线VIL2和第二极板Cst2。
若连接第n行像素电路PC的第二复位信号线VIL2复用为连接第n+1行像素电路PC的第一复位信号线VIL1，则第n行像素电路PC的第二复位晶体管T7的沟道可与第n+1行像素电路PC的第一复位晶体管T1的沟道之间的半导体层SEL可与第一复位信号线VIL1连接。
在本公开的一些实施方式中，补偿晶体管T2可为双栅晶体管，具有两个沟道。第二栅极层GAT2还可包括遮挡部SL，其可设于第一复位信号线VIL1和第二极板Cst2之间，且与补偿晶体管T2的两沟道之间的区域交叠，减小补偿晶体管T2的漏电。
介电层ILD可覆盖第二栅极层GAT2，且介电层ILD也可采用氮化硅、氧化硅等绝缘材料。
如图8和图9所示，源漏层SD设于介电层ILD远离衬底SU的表面，源漏层SD可采用金属、一些金属氧化物或其它导电材料，且第一源漏层SD可包括数据线DAL和电源线VDL，同时，还可包括一传输部SDc，传输部SDc与第n行像素电路PC的第二复位晶体管T7的沟道和第n+1行像素电路PC的第一复位晶体管T1的沟道之间的半导体层SEL交叠，且通过接触孔连接；同时，传输部SDc还通过接触孔与上文中的复用为第二复位信号线VIL2的第一复位信号线VIL1连接，从而可向第n行的第二复位晶体管T7和第n+1行的第一复位晶体管T1传输复位信号。
如图3、图10、图13图14所示，栅极驱动电路GGOA可包括多个级联的栅移位寄存器单元GGOAs，可为多行栅线GAL提供信号，从而控制多行栅线GAL连接的晶体管依次打开，同时，由数据线向其连接的像素电路PC提供数据信号，以形成显示图像的各灰阶所需要的灰度电压，从而控制发光器件的亮度，进而显示一帧图像。
栅极驱动电路GGOA的数量可为一个，位于像素区AA的一侧，栅移位寄存器单元GGOAs可驱动至少一行像素电路PC；或者，栅极驱动电路GGOA的数量可以是两个，且位于像素区AA的两侧，两栅极驱动电路GOA的栅移位寄存器单元GGOAs可一一对应设置，且同一行像素电路PC可同时接收两侧的相对应的栅移位寄存器单元GGOAs提供的信号。
如图10所示，该栅移位寄存器单元GGOAs包括8个晶体管和2个电容，其中包括输入晶体管T1、第一控制晶体管T2、第二控制晶体管T3、输出控制晶体管T4、栅极输出晶体管T5、第一降噪晶体管T6、第 二降噪晶体管T7以及稳压晶体管T8、第一电容C1和第二电容C2。
栅移位寄存器单元GGOAs级联，第一级栅移位寄存器单元GGOAs中的输入晶体管T21的第一极和输入端IN连接，输入端IN用于与触发信号线GSTV连接，以接收触发信号STV作为输入信号，而其它各级栅移位寄存器单元GGOAs中的输入晶体管T1的第一极和上一级栅移位寄存器单元GGOAs的输出端电连接，以接收上一级栅移位寄存器单元GGOAs的输出端GOUT输出的输出信号作为输入信号，由此实现移位输出，以用于对显示区的像素电路PC进行逐行扫描。
如图10所示，输入晶体管T1的栅极和第一时钟信号端CK(第一时钟信号端CK和第一子时钟信号线GCK连接)连接，以接收第一时钟信号，输入晶体管T1的第二极和输入端IN连接，输入晶体管T1的第一极和第一节点N1连接。例如，当该栅移位寄存器单元GGOAs为第一级栅移位寄存器单元GGOAs时，输入端IN与触发信号线GSTV连接，以接收触发信号，当该栅移位寄存器单元GGOAs为除第一级栅移位寄存器单元GGOAs以外的其他各级栅移位寄存器单元GGOAs时，输入端IN与其上级栅移位寄存器单元GGOAs的输出端GOUT连接。
第一控制晶体管T2的栅极和第一节点N1连接，第一控制晶体管T2的第二极和第一时钟信号端CK连接，以接收第一时钟信号，第一控制晶体管T2的第一极和第二节点N2连第二控制晶体管T3的栅极和第一时钟信号端CK连接，以接收第一时钟信号，第二控制晶体管的第二极和第二驱动电源线VGL连接，以接收第二电压，第二控制晶体管T3的第一极和第二节点N2连接。
输出控制晶体管T4的栅极和第二节点N2连接，输出控制晶体管T4的第一极和第一驱动电源线VGH连接，以接收第一电压，输出控制晶体管T4的第二极和输出端GOUT连接。
第一电容的第一极和第二节点N2连接，第一电容C1的第二极和第一驱动电源线VGH连接。
输出晶体管T5的栅极和第三节点N3连接，输出晶体管T5的第一极和第二时钟信号端CB连接，输出晶体管T5的第二极和输出端GOUT连接。
第二电容C2的第一极和第三节点N3连接，第二电容C2的第二极和输出端GOUT连接。
第一降噪晶体管T6的栅极和第二节点N2连接，第一降噪晶体管T6的第一极和第一驱动电源线VGH连接，以接收第一电压，第一降噪晶体管T6的第二极和第二降噪晶体管T7的第二极连接。
第二降噪晶体管T7的栅极和第二时钟信号端CB(第二时钟信号端CB和第二子时钟信号线GCB连接)连接，以接收第二时钟信号，第二降噪晶体管T7的第一极和第一节点N1连接。
稳压晶体管T8的栅极和第二驱动电源线VGL连接，以接收第二电压，稳压晶体管T8的第二极和第一节点N1连接，稳压晶体管T8的第一极和第三节点N3连接。
图10中的栅移位寄存器单元GGOAs中的晶体管均是以P型晶体管为例进行说明的，即各个晶体管在栅极接入低电平时导通，而在接入高电平时截止。此时，晶体管的第一极可以是源极，晶体管的第二极可以是漏极。
该栅极扫描栅移位寄存器单元的工作原理可参考本领域的介绍，在此不在赘述。
需要说明的是，上述栅移位寄存器单元GGOAs的电路的晶体管和电容的标记(T1-T8)与上文中的像素电路PC对晶体管标记(T1-T4)相同，但只是针对不同电路采用了相同的标记，晶体管的标记相同不代表同一晶体管。
针对上述的栅极驱动电路GGOA，其各晶体管的沟道可位于半导体层SEL，各晶体管的栅极和电容的一极板位于第一栅极层GAT1，电容的另一极板可位于第二栅极层GAT2。第一驱动电源线VGH、第二驱动电源线VGL、触发信号线GSTV、第一子时钟信号线GCK和第二子时钟信号线GCB位于源漏层SD。且第一驱动电源线VGH、第二驱动电源线VGL、触发信号线GSTV、第一子时钟信号线GCK和第二子时钟信号线GCB均位于栅极驱动电路GGOA远离显示区的一侧。
如图3、图16-图18所示，总线L位于总线区LA内，且均连接至 引出区BA，总线L至少可包括电源总线LVD和复位总线LVI，各电源线VDL均与电源总线LVD连接，以便同时传输第一电源信号VDD。复位总线LVI可与第一复位信号线VIL1和第二复位信号线VIL2连接，用于传输复位信号VI。同时，总线L还可包括测试总线LT，其可传输测试信号，用于对显示面板的显示效果进行测试，相应的，外围区还可具有与测试总线LT连接的测试单元，用于发出测试信号。测试总线LT可位于复位总线LVI远离显示区的一侧，测试总线LT的数量可以是多个，例如两个，其可间隔分布于复位总线LVI远离显示区的一侧。电源总线LVD可位于复位总线LVI靠近显示区的一侧。
可使通过缩短电源总线LVD的方式，减少其的占用空间，以便使外围区的范围变窄，举例而言：
在本公开的一些实施方式中，如图3所示，驱动背板的控制区WA可包括引出区BA，引出区BA可沿行方向X延伸，且与像素区AA沿列方向Y间隔分布。引出区BA可设有绑定区，各总线L、数据线DAL、电源线VDL以及上述的第一驱动电源线VGH、第二驱动电源线VGL、触发信号线GSTV、第一子时钟信号线GCK和第二子时钟信号线GCB均可连接至引出区BA的绑定区，以便通过绑定区与柔性电路板绑定，而柔性电路板可设置控制芯片，且能与一控制主板绑定，由此，可通过控制芯片和控制主板对显示面板进行控制，实现图像显示和测试等功能。
进一步的，如图3和图17所示，在本公开的一些实施方式中，总线区LA可包括沿行方向X分布与像素区AA两侧的侧总线区LA1和连接于两个侧总线区LA1之间的连接总线区LA2，连接总线区LA2可位于引出区BA和像素区AA之间。复位总线LVI和测试总线LT均可有连接总线区LA2延伸至两个侧总线区LA1内。复位总线LVI的宽度可大于其它总线L的宽度，其电源总线LVD可以是各总线L中最接近像素区AA的总线L，即电源总线LVD和像素区AA之间没有其它总线L。电源总线LVD可仅位于连接总线区LA2内，而不延伸至侧总线区LA1内，有利于缩窄外围区在行方向X上的宽度，提高屏占比。
在本公开的另一些实施方式中，如图13、14和17所示，电源总线LVD可延伸至侧总线区LA1内，且围绕于像素区AA外。
如图11-图15所示，栅连接线GCL的数量有多个，且一栅移位寄存器单元GGOAs可与一栅连接线GCL连接，一栅连接线GCL可与至少一栅线GAL连接，从而可通过栅连接线GCL和栅线GAL向像素电路PC输入信号。同时，栅连接线GCL的至少部分区域与栅线GAL不同层，并通过接触孔与栅线GAL连接，也就是说，栅连接线GCL在与栅线GAL连接的过程中，需要通过接触孔转接，而接触孔的存在，会使栅连接线GCL的阻抗增大，有利于提高对静电的屏蔽能力。此外，对于与第一栅线GAL1、第二栅线GAL2和第四栅线GAL4连接的栅连接线GCL而言，由于其传输的脉冲信号的频率较高，以满足不同复位阶段、写入阶段和发光阶段的要求，而这写高频的脉冲信号更容易受到静电影响，而通过增大至少一部分栅连接线GCL的电阻，可减弱静电的干扰。
举例而言，基于上文中像素电路PC的实施方式中对栅线GAL的复用方式，可使连接n行像素电路PC的第一栅线GAL1和连接n+1行像素电路PC的第一复位晶体管T1的第二栅线GAL2通过同一栅连接线GCL与同一栅移位寄存器单元GGOAs连接，该连接方式可使连接同一像素电路PC的第一栅线GAL1和第四栅线GAL4通过同一栅连接线GCL与同一栅移位寄存器单元GGOAs连接。下面，基于该连接方式，对栅连接线GCL的具体实现方式进行示例性说明：
如图11-图15所示，栅连接线GCL可包括相互连接的第一连接部GCL1和第二连接部GCL2，第一连接部GCL1可与栅移位寄存器单元GGOAs(输出端GOUT)连接，且穿过总线区LA，第二连接部GCL2可位于像素区AA或总线区LA内，且与至少一栅线GAL连接。第一连接部GCL1和第二连接部GCL2中至少一个与栅线GAL不同层。
在本公开的第一类实施方式中，如图11和图14所示，第一连接部GCL1与栅线GAL同层设置，第二连接部GCL2与栅线GAL不同层。例如，第一连接部GCL1位于第一栅极层GAT1，第二连接部GCL2可以位于源漏层SD或第二栅极层GAT2，只要可通过接触孔与栅线GAL连接即可。
在第一类的第一实施方式中，如图11、图13和图14所示，第一连 接部GCL1可沿行方向X延伸，且通过接触孔与栅移位寄存器单元GGOAs的输出端连接，且与第二栅线GAL2连接，由于第一连接部GCL1与栅线GAL同层设置，因而可与第二栅线GAL2为一体成型的一体结构。
第二连接部GCL2位于源漏层SD，且沿列方向Y延伸，第二连接部GCL2可通过接触孔与第一连接部GCL1连接，并通过接触孔与第一栅线GAL1连接。第二连接部GCL2可以位于显示区，且位于复位总线LVI和距离总线区LA最近的一列像素电路PC之间，即第二连接部GCL2位于复位总线LVI远离测试总线的一侧。
进一步的，第一连接部GCL1沿行方向X穿过总线区LA，与各个总线L均交叠。第二连接部GCL2与复位总线LVI相邻设置，即复位总线LVI和第二连接部GCL2之间没有其它走线。第二连接部GCL2与复位总线LVI沿行方向X的距离可为3μm-10μm，例如，该距离可以是4.5μm。一方面可以避免第二连接部GCL2与复位总线LVI距离过近而导致寄生电容增过大，从而有利于降低功耗，另一方面，可防止距离过远而导致外围区的宽度增加过多，而不利于缩减边框宽度。
第二连接部GCL2的宽度为复位总线的宽度的20％-40％，例如，第二连接部GCL2的宽度为3.5μm，复位总线的宽度为10μm。
在第一类的第二实施方式中，如图12所示，第一连接部GCL1和第二连接部GCL2的连接方式和所处的膜层与上述第一实施方式相同，在此不再详述。不同点在于：第二连接部GCL2可以位于总线区LA内，但为了避免与总线L发生短路，可使其与总线L间隔设置，例如，设于一测试总线LT和复位总线LVI之间。
在第一类的第三实施方式中，如图15所示，第一连接部GCL1和第二连接部GCL2的连接方式与上述第一实施方式和第二实施方式相同，在此不再详述。不同点在于：第二连接部GCL2位于第二栅极层GAT2，且沿列方向Y延伸，第二连接部GCL2可通过接触孔与第一连接部GCL1连接，并通过接触孔与第一栅线GAL1连接。相应的，第二连接部GCL2可以位于显示区，且位于复位总线LVI和距离总线区LA最近的一列像素电路PC之间；或者，也可位于总线区LA，且与总线L间隔设置。
在第一类的第三实施方式中，如图15所示，还可以使第一连接部GCL1位于第二栅极层GAT2，第二连接部GCL2与栅线同层，即位于第一栅极层GAT1。第一连接部GCL1可沿行方向X穿过总线区LA，并通过接触孔与栅移位寄存器单元GOA连接，且通过接触孔与第二连接部GCL2和第二栅线GAL2连接。第二连接部GCL2可与第一栅线GAL1连接。
在第一类的第四实施方式中，如图14所示，基于上述的第一实施方式，可使第二连接部GCL2的两端分别与第一栅线GAL1和第二栅线GAL2通过接触孔连接，且第二连接部GCL2可通过接触孔与第一连接部GCL1连接，也就是说，第二连接部GCL2至少设有三个接触孔。
在第一类的第五实施方式中，电路层CL还可包括遮光层，其可设于衬底SU一侧，并被绝缘层覆盖，半导体层SEL可设于该绝缘层远离衬底SU的一侧。遮光层可具有遮挡与驱动晶体管的沟道交叠的遮光部，用于阻挡光线照射驱动晶体管。第二连接部GCL2可位于该遮光层。
在第一类的其它实施方式中，栅连接线GCL也可以不限于上述的第一连接部GCL1和第二连接部GCL2的结构，可以包括更多段线段，这些线段中的至少一部分位于第一栅极层GAT1，其它则可位于第二栅极层GAT2和源漏层SD中的至少一层，只要能实现栅移位寄存器单元GGOAs和第一栅线GAL1和第二栅线GAL2的连接，且不会与总线直接接触即可，在此不再一一列举。
在本公开的第二类实施方式中，栅连接线GCL位于同一层，例如，其第一连接部GCL1和第二连接部GCL2同层设置，但与栅线和总线不同层，从而需要通过接触孔与栅线连接。
在第二类的第一实施方式中，如图15所示，栅连接线GCL位于第二栅极层GAT2，其第一连接部GCL1可沿行方向X延伸，且穿过总线区LA，并与栅移位寄存器单元GGOAs连接，且与第二栅线GAL2通过接触孔连接，第二连接部GCL2与第一连接部GCL1为一体结构，且沿列方向Y延伸，并与第一栅线GAL1通过接触孔连接。
在第二类的第二实施方式中，电路层CL还可包括遮光层，其可设 于衬底一侧，并被绝缘层覆盖，半导体层SEL可设于该绝缘层远离衬底SU的一侧。遮光层可具有遮挡与驱动晶体管的沟道交叠的遮光部，用于阻挡光线照射驱动晶体管。栅连接线GCL可位于该遮光层，其具体结构和连接方式可参考第二类的第一实施方式，在此不再详述。
进一步的，如图11、图12和图15所示，为了控制发光控制晶体管的通/断时序，电路层CL还包括发光控制电路EGOA，其可设于控制区WA。发光控制电路EGOA包括沿列方向Y级联的多个发光移位寄存器单元EGOAs，发光移位寄存器单元EGOAs的结构和工作原理与栅移位寄存器单元GGOAs相似，其可控制各行像素电路PC的发光控制晶体管依次导通和关断。例如，发光移位寄存器单元EGOAs可与第三栅线GAL3连接，向第三栅线GAL3输出发光控制信号EM。在本公开的一些实施方式中，发光移位寄存器单元EGOAs可以两行像素电路PC所连接的第三栅线GAL3连接。
举例而言：在一些实施方式中，如图3所示，发光控制电路EGOA可位于栅极驱动电路GGOA远离像素区AA的一侧，即栅极驱动电路GGOA的外侧，且与栅极驱动电路GGOA间隔分布，进一步的，发光控制电路EGOA和栅极驱动电路GGOA的数量均为两个，且栅极驱动电路GGOA分隔于像素区AA两侧，发光控制电路EGOA位于栅极驱动电路GGOA的外侧，一行像素电路PC可连接两个发光移位寄存器单元EGOAs和两个栅移位寄存器单元GGOAs，以防止因信号衰减而导致同一行像素电路PC响应速度差别过大。
在一些实施方式中，如图16所示，发光控制电路EGOA和栅极驱动电路GGOA的数量均可以是一个，且可分隔于像素区AA的两侧，只要能向每一行像素电路PC传输信号即可，有利于缩短控制区的宽度，以减小边框。
为了实现发光移位寄存器单元EGOAs与第三栅线GAL3的连接，电路层CL还可包括多个发光连接线ECL，一发光移位寄存器单元EGOAs与一发光连接线ECL连接，一发光连接线ECL的至少部分区域与第三栅线GAL3位于不同层，且通过接触孔与一第三栅线GAL3连接。
发明人发现，虽然发光器件LD的发光时间要长于复位和写入的时间，且作为脉冲信号，发光控制信号EM的频率比扫描信号GA和复位控制信号RE1和RE2的频率低，但发光控制信号EM仍有可能收到静电的影响，因此，还可以通过在发光移位寄存器单元EGOAs与第三栅线GAL3之间引入接触孔，增大阻抗，从而提高抗静电的能力。
与上述栅连接线GCL的结构类似，发光连接线ECL至多有一部分与栅线GAL同层，从而需要接触孔才能与第三栅线GAL3连接，由此，可通过引入接触孔增大电阻，提高阻挡静电的能力。
如图11、图12和图15所示，发光连接线CGL可包括第三连接部CGL1和第四连接部CGL2，第三连接部CGL1与栅线GAL同层设置，即位于第一栅极层GAT1，且第三连接部CGL1与发光移位寄存器单元EGOAs连接，并沿方向穿过总线区LA。第四连接部CGL2位于源漏层SD或第二栅极层GAT2，且通过接触孔与第三连接部CGL1和第三栅线GAL3连接。
此外，发光连接线ECL可位于第二栅极层GAT2，且通过接触孔与发光移位寄存器单元EGOAs和第三栅线GAL3连接。
发光连接线ECL的结构和连接方式可参考上文中的栅连接线GCL，第三连接部ECL1可参考第一连接部GCL1，第四连接部ECL2可参考GCL2，只要能通过接触孔增大电阻即可，在此不再进行详细的举例说明。但应注意的是，发光连接线ECL不能与总线L和栅连接线GCL直接接触，避免短路。
进一步的，针对上述第二类实施方式，复位信号线(连接第n行像素电路PC的第二复位信号线VIL2和连接第n+1行像素电路PC的第一复位信号线VIL1)，沿行方向X延伸，且通过复位连接线RCL与复位总线LVI连接，为了避免第四连接部CGL2和第二连接部GCL2与复位连接线RCL交叉，可使其复位连接线RCL位于第一栅极层GAT1，且复位连接线RCL与复位总线LVI连接，复位信号线可位于第二栅极层GAT2，且通过接触孔与复位连接线RCL连接。复位连接线RCL与第四连接部CGL2和第二连接部GCL2交叠，但能保持绝缘。
当然，还可以通过利用其它膜层的复位连接线RCL，实现复位信号线与复位总线LVI的连接，只要能避免与第四连接部CGL2和第二连接部GCL2短路即可。
如图2所示，本公开实施方式提供一种显示面板，其可包括驱动背板BP和发光器件LD，其中：
驱动背板BP可以是上述任意实施方式的驱动背板BP，在此不再详述其结构。
发光器件LD可设于电路层CL远离衬底SU的一侧，且与像素电路PC连接。发光器件LD的数量可以有多个，且每个发光器件LD可连接一个像素电路PC，同一像素电路PC可以连接一个或多个发光器件LD。该发光器件LD可以是OLED(有机发光二极管)、QLED(量子点发光二极管)、Micro LED或Mini LED等，其可以包括第一电极ANO、第二电极CAT和位于第一电极ANO和第二电极CAT间的发光层EL，
以OLED为例，第一电极ANO可设于电路层CL远离衬底SU的表面，例如第二平坦层PLN2远离衬底SU的表面，发光层EL可包括沿远离驱动背板BP的方向层叠的空穴注入层、空穴传输层、发光材料层、电子传输层和电子注入层。各个发光器件LD可共用第二电极CAT，也就是说，第二电极CAT可以是连续的整层结构，且第二电极CAT可延伸至外围区，并可接收第二电源信号VSS，第一电极ANO则阵列分布，确保各发光器件LD可以独立发光。此外，为了限定发光器件LD的发光范围，防止串扰，可在设置第一电极ANO的表面设置像素定义层PDL，其可设有露出各第一电极ANO的开口，发光层EL在开口内与第一电极ANO层叠。
各发光器件LD可至少共用发光材料层，使得各发光器件LD的发光颜色相同，此时，为了实现彩色显示，可在发光器件LD远离衬底SU的一侧设置彩膜层，通过彩膜层中与各发光器件LD对应的滤光部，实现彩色显示。当然，各个发光器件LD的发光材料层也可以使独立的，使得发光器件LD可以直接发出单色光，且不同发光器件LD的发光颜色可以不同，从而实现彩色显示。
此外，显示面板还可包括覆盖各发光器件LD的封装层，还可以包括设置在封装层远离衬底SU的一侧的触控层、透明盖板等其它膜层，在此不再详述。
本公开还提供一种显示装置，该显示装置可包括上述任意实施方式的显示面板。该显示面板为上述任意实施方式的显示面板，其具体结构和有益效果可参考上文中显示面板的实施方式，在此不再赘述。本公开的显示装置可以是手机、平板电脑、电视等具有显示功能的电子设备，在此不再一一列举。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (20)

  1. 一种驱动背板，所述驱动背板具有像素区和所述像素区外的控制区，所述控制区包括电路区和分隔于所述电路区和所述像素区之间的总线区；所述驱动背板包括衬底和设于所述衬底一侧的电路层，所述电路层包括：
    多个像素电路，阵列分布于所述像素区；
    多个栅线，沿行方向延伸，且沿列方向分布，一行所述像素电路与至少一个所述栅线连接；
    栅极驱动电路，设于所述控制区，且包括沿列方向级联的多个栅移位寄存器单元；
    总线，设于所述总线区内，且至少部分位于所述栅极驱动电路和所述像素区之间；
    多个栅连接线，一所述栅移位寄存器单元与一所述栅连接线连接，一所述栅连接线的至少部分区域与所述栅线不同层，且通过接触孔与至少一所述栅线连接；所述栅连接线与所述总线绝缘设置。
  2. 根据权利要求1所述的驱动背板，其中，所述栅连接线包括相互连接的第一连接部和第二连接部，所述第一连接部与所述栅移位寄存器单元连接，且穿过所述总线区，所述第二连接部与所述总线和所述像素电路间隔分布，且与至少一所述栅线连接；所述第一连接部和所述第二连接部中至少一个与所述栅线不同层。
  3. 根据权利要求2所述的驱动背板，其中，所述第一连接部与所述栅线同层设置，所述第二连接部与所述栅线不同层。
  4. 根据权利要求2所述的驱动背板，其中，所述第一连接部和所述第二连接部同层设置，且与所述栅线和所述总线不同层。
  5. 根据权利要求2-4任一项所述的驱动背板，其中，所述电路层还包括电源线、数据线和复位信号线，所述电源线和所述数据线均沿列方向延伸，且沿所述行方向分布，所述电源线和所述数据线与所述总线同层设置；所述复位信号线沿所述行方向延伸，且沿列方向分布，所述复位信号线与所述栅线和所述总线位于不同层；
    所述栅线包括第一栅线和第二栅线；
    所述像素电路包括存储电容和多个晶体管，所述晶体管包括驱动晶体管、写入晶体管、补偿晶体管和第一复位晶体管；所述补偿晶体管和所述写入晶体管的栅极与所述第一栅线连接；所述驱动晶体管的第一极与电源线连接，第二极与发光器件连接；所述补偿晶体管连接所述驱动晶体管的第二极和栅极；所述写入晶体管的第一极与所述数据线连接，第二极与所述驱动晶体管的第一极连接；所述第一复位晶体管的栅极与所述第二栅线连接，第一极与所述复位信号线连接，第二极与所述驱动晶体管的栅极连接；所述存储电容的第一极板与所述驱动晶体管的栅极连接，第二极板与所述电源线连接；
    连接第n行所述像素电路的第一栅线和连接第n+1行所述像素电路的第二栅线通过同一所述栅连接线与同一所述栅移位寄存器单元连接。
  6. 根据权利要求5所述的驱动背板，其中，所述电路层包括：
    半导体层，设于所述衬底一侧，且包括各所述晶体管的沟道；
    第一栅绝缘层，覆盖所述半导体层；
    第一栅极层，设于所述第一栅绝缘层远离所述衬底的表面，且包括所述栅线、所述第一极板和各所述晶体管的栅极；
    第二栅绝缘层，覆盖所述第一栅极层；
    第二栅极层，设于所述第二栅绝缘层远离所述衬底的表面，且包括所述第二极板和所述复位信号线；
    介电层，覆盖所述第二栅极层；
    源漏层，设于所述介电层远离所述衬底的一侧，且包括所述总线、所述电源线和所述数据线。
  7. 根据权利要求6所述的驱动背板，其中，若所述第一连接部与所述栅线同层设置，且与所述第二连接部不同层：
    所述第一连接部与所述第二栅线连接；所述第二连接部位于所述源漏层，且沿所述列方向延伸，所述第二连接部通过接触孔与所述第一栅线连接。
  8. 根据权利要求6所述的驱动背板，其中，若所述第一连接部和所述第二连接部同层设置：
    所述栅连接线位于所述第二栅极层。
  9. 根据权利要求8所述的驱动背板，其中，所述第一连接部通过接触孔与所述栅移位寄存器单元和所述第二栅线连接；所述第二连接部沿列方向延伸，且与所述第一连接部连接，所述第二连接部通过接触孔与所述第一栅线连接。
  10. 根据权利要求6所述的驱动背板，其中，所述栅线还包括第三栅线；所述像素电路还包括第二复位晶体管、第一发光控制晶体管和第二发光控制晶体管；
    所述第一发光控制晶体管的栅极与第三栅线连接，第一极与所述电源线连接，第二极与所述驱动晶体管的第一极连接；
    所述第二发光控制晶体管的栅极与所述第三栅线连接，第一极与所述驱动晶体管的第二极连接，第二极与所述发光器件连接；
    所述第二复位晶体管的栅极与所述第一栅线连接，第一极与所述复位信号线连接，第二极与所述第二发光控制晶体管的第二极连接。
  11. 根据权利要求10所述的驱动背板，其中，所述电路层还包括：
    发光控制电路，设于所述控制区，所述发光控制电路包括沿列方向级联的多个发光移位寄存器单元；
    多个发光连接线，一所述发光移位寄存器单元与一所述发光连接线连接，一所述发光连接线的至少部分区域与所述第三栅线位于不同层，且通过接触孔与一所述第三栅线连接。
  12. 根据权利要求11所述的驱动背板，其中，所述发光连接线位于所述第二栅极层，且通过接触孔与所述发光移位寄存器单元和所述第三栅线连接。
  13. 根据权利要求11所述的驱动背板，其中，所述发光连接线包括第三连接部和第四连接部，所述第三连接部与所述栅线同层设置，且与所述发光移位寄存器单元连接，所述第三连接部沿所述方向穿过所述总线区；所述第四连接部位于所述源漏层或第二栅极层，且通过接触孔与所述第三连接部和所述第三栅线连接。
  14. 根据权利要求11所述的驱动背板，其中，第n行所述像素电路的第二复位晶体管与第n+1行所述像素电路的第二栅线连接。
  15. 根据权利要求6-13任一项所述的驱动背板，其中，所述总线包 括位于源漏层的测试总线、复位总线和电源总线，所述电源线与所述电源总线连接，所述复位信号线与所述复位总线连接。
  16. 根据权利要求15所述的驱动背板，其中，所述复位总线位于所述测试总线和所述像素区之间，所述第二连接部位于所述复位总线远离所述测试总线的一侧，且与所述复位总线相邻设置；所述第二连接部与所述复位总线沿行方向的距离为3μm-10μm。
  17. 根据权利要求15所述的驱动背板，其中，所述第二连接部的宽度为所述复位总线的宽度的20％-40％。
  18. 根据权利要求15所述的驱动背板，其中，所述驱动背板控制区包括引出区，所述引出区沿所述行方向延伸，且与所述像素区沿列方向间隔分布；所述总线、所述数据线和所述电源线均连接至所述引出区；
    所述总线区包括沿行方向分布于所述像素区两侧的侧总线区和连接于两所述侧总线区之间的连接总线区，所述连接总线区位于所述引出区和所述像素区之间；
    所述电源总线位于所述连接总线区内。
  19. 一种显示面板，包括权利要求1-18任一项所述的驱动背板。
  20. 一种显示装置，包括权利要求19所述的显示面板。
PCT/CN2022/096167 2022-05-31 2022-05-31 驱动背板、显示面板及显示装置 WO2023230817A1 (zh)

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