WO2023236012A1 - 显示面板及其制备方法、显示装置 - Google Patents

显示面板及其制备方法、显示装置 Download PDF

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Publication number
WO2023236012A1
WO2023236012A1 PCT/CN2022/097171 CN2022097171W WO2023236012A1 WO 2023236012 A1 WO2023236012 A1 WO 2023236012A1 CN 2022097171 W CN2022097171 W CN 2022097171W WO 2023236012 A1 WO2023236012 A1 WO 2023236012A1
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WIPO (PCT)
Prior art keywords
pixel
sub
base substrate
active
conductive
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PCT/CN2022/097171
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English (en)
French (fr)
Inventor
包征
王明强
李子骞
张燚
魏向东
陈功
杨皓天
王畅
张家祥
张斌
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/578,731 priority Critical patent/US20240339084A1/en
Priority to CN202280001671.2A priority patent/CN117546228A/zh
Priority to PCT/CN2022/097171 priority patent/WO2023236012A1/zh
Publication of WO2023236012A1 publication Critical patent/WO2023236012A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G09G2330/023—Power management, e.g. power saving using energy recovery or conservation

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel, a preparation method thereof, and a display device.
  • each sub-pixel is driven by a corresponding pixel driving circuit to emit light.
  • the voltage of the data signal on the data line is unstable, which affects the display quality.
  • the purpose of the present disclosure is to overcome the above-mentioned shortcomings of the prior art and provide a display panel, a preparation method thereof, and a display device.
  • a display panel including: a display area, the display area including a plurality of pixel units distributed in an array along the row and column directions, the pixel unit at least including a first sub-pixel and a second sub-pixel, And the maximum gray scale value voltage of the first sub-pixel is less than the maximum gray scale value voltage of the second sub-pixel; a source drive circuit is located on one side of the display area, and the source drive circuit is used to output data signal and switch control signal; a switch circuit, located on one side of the display area, the switch circuit includes a plurality of switch units, the control end of the switch unit is used to receive the switch control signal, and the first end is used to The data signal is received, and the second end is connected to the data line; wherein, the first sub-pixel in any n-th column pixel unit and the first sub-pixel in the (n+1)-th column pixel unit are connected to the data line respectively through the data line. Two adjacent switch units are connected, and n is an odd number
  • the pixel unit further includes a third sub-pixel, and the second sub-pixel and the third sub-pixel in the same pixel unit are connected to each other through the data line respectively. Two adjacent switch units or two separated switch units are connected.
  • the plurality of switch units are arranged in one-to-one correspondence with multiple columns of sub-pixels.
  • the display panel includes a plurality of repeating units distributed along a row direction, the repeating units include first pixel units and second pixel units adjacent in the row direction and adjacent pixel units in the row direction.
  • the switch unit is connected to the data line of the first sub-pixel in the second pixel unit.
  • the first sub-pixel is an R sub-pixel.
  • the switch unit is a transistor.
  • the switch circuit includes a plurality of ninth transistors and a plurality of tenth transistors, the ninth transistors and the tenth transistors are arranged in sequence; the m-th column sub-pixel and the m-th sub-pixel are The (m+1) column sub-pixels are different sub-pixels in the same column pixel unit.
  • the ninth transistor corresponding to the m-th column sub-pixel is connected to the data line of the m-th column sub-pixel.
  • the ninth transistor corresponding to the (m+1)-th column sub-pixel The transistor is connected to the data line of the corresponding sub-pixel in the pixel unit of the next column, where m is a positive integer greater than or equal to 1.
  • the tenth transistor is connected to the data line of the corresponding sub-pixel in the next column of pixel units through a transfer line, and the transfer line and the data line are located on different conductive layers.
  • the display panel further includes: a base substrate including the display area; an active layer located on one side of the base substrate, the The active layer includes: a plurality of fifth active parts, the fifth active parts are used to form the channel region of the tenth transistor; a plurality of sixth active parts, the sixth active parts are connected to One side of the fifth active part; a first conductive layer, located on a side of the active layer facing away from the base substrate, the first conductive layer includes: a plurality of second gate lines, the third The orthographic projection of the second gate line on the base substrate covers the orthographic projection of the fifth active part on the base substrate, and part of the structure of the second gate line is used to form the gate of the tenth transistor.
  • the third conductive layer is located on the side of the first conductive layer away from the base substrate.
  • the third conductive layer includes: a plurality of data lines, one of which is connected to a column of sub-pixels; a plurality of sixth Conductive wires are provided corresponding to the sixth active part, and the sixth conductive wires are connected to the sixth active part through via holes; wherein, the adapter wires are respectively connected to the sixth conductive wires and the sixth active part through via holes. Corresponding data lines in adjacent pixel units.
  • the transfer line is located on the first conductive layer.
  • an angle between an orthographic projection of the adapter line on the base substrate and an orthographic projection of the sixth conductive line connected thereto on the base substrate is greater than or equal to 60 ° and less than or equal to 120°; the angle formed by the intersection of the orthographic projection of the transfer line on the base substrate and the orthographic projection of the data line on the base substrate is greater than or equal to 60° and less than or equal to 120°.
  • the active layer further includes: a fourth active part connected to a side of the fifth active part away from the sixth active part;
  • a conductive layer further includes: a plurality of second connection lines connected to the source driving circuit;
  • the third conductive layer further includes: a plurality of fourth conductive lines connected with the fourth active The fourth conductive line is arranged corresponding to the fourth active part through a via hole; a plurality of third conductive lines are arranged corresponding to the second connection line, and the third conductive line is connected through a via hole.
  • the holes are connected to the corresponding second connection lines;
  • the display panel also includes: a second conductive layer located between the first conductive layer and the third conductive layer; the second conductive layer includes: A second transfer part is provided corresponding to the fifth active part, and the front projection of the second transfer part on the base substrate is located on the front projection of the fourth active part on the base substrate.
  • the projection and the second connection line are between the front projection of the base substrate, and the second transfer part is connected to the corresponding third conductive line and the fourth conductive line through via holes respectively.
  • the active layer further includes: a plurality of second active parts located in the non-display area in an orthographic projection of the base substrate, the second active parts
  • the first active part is used to form the channel region of the ninth transistor; a plurality of first active parts are provided corresponding to the second active part, and the first active part is connected to the second active part.
  • the second active part is connected to its corresponding data line through a via hole;
  • the first conductive layer also includes: a plurality of first gate lines, the first gate lines cover all areas in the orthographic projection of the substrate.
  • the orthographic projection of the second active part on the base substrate, a partial structure of the first gate line is used to form the gate of the ninth transistor; a plurality of first connection lines, the first connection lines Connect the source driving circuit; the second conductive layer also includes: a plurality of first transfer parts, which are provided corresponding to the second active part, the first transfer parts are on the base substrate The orthographic projection is located between the orthographic projection of the first active part on the base substrate and the orthographic projection of the first connection line on the base substrate; the third conductive layer also includes: a plurality of third A conductive wire, the first conductive wire is connected to the corresponding first active part and the first adapter part through a via hole; a plurality of second conductive wires, the second conductive wire is connected through a via hole The corresponding first connection line and the first adapter part.
  • the switch circuit includes a plurality of switch selection circuits, and the switch selection circuit includes a plurality of the switch units.
  • a method for preparing a display panel is also provided for preparing the display panel described in the above embodiments of the present disclosure.
  • the method includes: providing a base substrate, the base substrate including a display panel. area and a non-display area at least partially surrounding the display area; using a deposition process to form an active layer in the non-display area on one side of the base substrate, wherein the active layer includes a fifth active part and a A sixth active part on one side of the fifth active part, the fifth active part is used to form a channel region of the tenth transistor; a deposition process is used to form a layer on the active layer away from the liner.
  • a first conductive layer is formed on one side of the base substrate, wherein the first conductive layer includes a plurality of second gate lines and a plurality of transfer lines, and the second gate lines cover the orthographic projection of the base substrate.
  • the orthographic projection of the fifth active part on the base substrate, the partial structure of the second gate line is used to form the gate of the tenth transistor; the transfer lines are respectively connected to the sixth conductive parts through via holes.
  • a deposition process is used to form a third conductive layer on the side of the first conductive layer facing away from the base substrate, wherein the third conductive layer includes a plurality of data lines and a plurality of A sixth conductive line, one of the data lines connected to a column of sub-pixels, the sixth conductive line is provided corresponding to the sixth active part, the sixth conductive line is connected to the sixth active part through a via hole .
  • the method before using a deposition process to form a first conductive layer on a side of the active layer facing away from the base substrate, further includes: using a deposition process to form a first conductive layer on a side of the active layer facing away from the base substrate. depositing a first inorganic material on the base substrate and the active layer to form a first gate insulating layer; using a deposition process to form a first conductive layer on a side of the active layer facing away from the base substrate, The method includes: depositing the first conductive material on the first gate insulating layer using a deposition process to form the first conductive layer.
  • the method further includes: using a deposition process to Depositing a second inorganic material on the first conductive layer to form a second gate insulating layer; using a deposition process to deposit a first conductive material on the second gate insulating layer to form a second conductive layer; using a patterning process to form a second conductive layer on the second gate insulating layer.
  • the conductive layer forms a plurality of second transfer parts, wherein the second transfer parts are provided corresponding to the fifth active part, and the second transfer parts are located on the orthographic projection of the base substrate.
  • the fourth active part is between the orthographic projection of the base substrate and the second connecting line on the orthographic projection of the base substrate, and the second transfer parts are respectively connected to the corresponding corresponding ones through via holes.
  • the third conductive line and the fourth conductive line using a deposition process to deposit a first inorganic material or a second inorganic material on the second conductive layer to form an interlayer dielectric layer; using an etching process to deposit the interlayer dielectric layer on the second conductive layer.
  • Multiple via holes are formed on the electrical layer.
  • using a deposition process to form a third conductive layer on a side of the first conductive layer facing away from the base substrate includes: using a deposition process to form a third conductive layer on the interlayer dielectric layer.
  • a second conductive material is deposited on the third conductive layer to form a third conductive layer; an etching process is used to form a plurality of the data lines and a plurality of the sixth conductive lines on the third conductive layer.
  • the method further includes planarizing the third conductive layer.
  • a display device including the display panel according to any embodiment of the present disclosure.
  • Figure 1 is a schematic circuit structure diagram of a pixel driving circuit in a display panel according to an embodiment of the present disclosure
  • Figure 2 is a timing diagram of each node in a driving method of the pixel driving circuit in Figure 1;
  • Figure 3 is a schematic diagram of switching of data signals according to an embodiment of the present disclosure
  • Figure 4 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • Figure 5 is a schematic diagram of the connection between some switch units and pixel columns in Figure 4.
  • Figure 6 is a timing diagram of each switching unit when each sub-pixel in Figure 5 is at the maximum gray scale value voltage
  • Figure 7 is a schematic diagram of the connection between some switch units and pixel columns in Figure 4 according to another embodiment of the present disclosure.
  • Figure 8 is a cross-sectional view corresponding to the position of the tenth transistor along the dashed line AA in Figure 4;
  • Figure 9 is a cross-sectional view corresponding to the position of the ninth transistor along the dotted line BB direction in Figure 4;
  • Figure 10 is a schematic diagram of an orthographic overlay of a patch cord and a data line according to an embodiment of the present disclosure
  • 11 to 20b are process flow diagrams of a display panel manufacturing method according to an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • the display area of the display panel of the present disclosure includes pixel units distributed in an array along the row and column directions. Each pixel unit can have multiple sub-pixels, and each sub-pixel can provide a driving current through a corresponding pixel driving circuit to drive it to perform light-emitting display.
  • the pixel driving circuit in the display panel of the present disclosure may be a 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure, etc. In an exemplary embodiment of the present disclosure, the pixel driving circuit has a 7T1C structure.
  • FIG. 1 is a schematic circuit structure diagram of the pixel driving circuit in a display panel according to an embodiment of the present disclosure.
  • the pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C.
  • the first electrode of the first transistor T1 is connected to the node N
  • the second electrode is connected to the first initial signal terminal Vinit1, and the gate is connected to the reset signal terminal Re1
  • the first electrode of the second transistor T2 is connected to the first electrode of the driving transistor T3, and the first electrode of the first transistor T1 is connected to the node N.
  • the diode is connected to the node N; the gate is connected to the gate drive signal terminal Gate; the gate of the drive transistor T3 is connected to the node N; the first pole of the fourth transistor T4 is connected to the data signal terminal Da, and the second pole is connected to the second pole of the drive transistor T3.
  • the gate is connected to the gate drive signal terminal Gate;
  • the first pole of the fifth transistor T5 is connected to the second pole of the drive transistor T3, the second pole is connected to the first power supply terminal VDD, and the gate is connected to the enable signal terminal EM;
  • the sixth transistor T5 The first pole of the transistor T6 is connected to the first pole of the driving transistor T3, and the gate is connected to the enable signal terminal EM;
  • the first pole of the seventh transistor T7 is connected to the second pole of the sixth transistor T6, and the second pole is connected to the second initial signal terminal. Vinit2, the gate is connected to the reset signal terminal Re2.
  • the capacitor C is connected between the gate of the driving transistor T3 and the first power terminal VDD.
  • the pixel driving circuit can be connected to a light-emitting unit OLED for driving the light-emitting unit OLED to emit light.
  • the light-emitting unit OLED can be connected between the second pole of the sixth transistor T6 and the second power terminal VSS.
  • the transistors T1 - T7 may all be P-type transistors or N-type transistors, or some may be P-type transistors and some may be N-type transistors.
  • the first to seventh transistors T1 to T7 are all P-type transistors or all to N-type transistors, or the first transistor T1 and the second transistor T2 are P-type transistors, and the third to seventh transistors T3 to T7 are N-type transistors. type transistors, etc.
  • the transistors used in each embodiment of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • FIG. 2 is a timing diagram of each node in a driving method of the pixel driving circuit in Figure 1.
  • Gate represents the timing of the gate drive signal terminal Gate
  • Re1 represents the timing of the reset signal terminal Re1
  • Re2 represents the timing of the reset signal terminal Re2
  • EM represents the timing of the enable signal terminal EM
  • Da represents the timing of the data signal terminal Da.
  • the driving method of the pixel driving circuit may include a reset phase t1, a compensation phase t2, and a light emitting phase t3.
  • the reset phase t1 the reset signal terminal Re1 outputs a low-level signal
  • the first transistor T1 is turned on
  • the first initial signal terminal Vinit1 inputs an initial signal to the node N.
  • N writes the voltage Vdata+Vth, where Vdata is the voltage of the driving signal, Vth is the threshold voltage of the driving transistor T3, and the second initial signal terminal Vinit2 inputs an initial signal to the second pole of the sixth transistor T6.
  • Light-emitting stage t3 The enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata+Vth stored in the capacitor C.
  • the driving transistor output current formula I ( ⁇ WCox/2L)(Vgs-Vth) 2 , where ⁇ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, and L driver The length of the transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor.
  • the pixel driving circuit can avoid the influence of the threshold voltage of the driving transistor on its output current.
  • the fourth transistor T4 is turned on, and the source driver circuit provides the corresponding data signal to the sub-pixel through the data line. During the process of turning on the fourth transistor T4, it is necessary to ensure that the data output by the data signal terminal The signal voltage Vdata remains stable to avoid abnormal display problems.
  • FIG 3 is a schematic diagram of data signal switching according to an embodiment of the present disclosure.
  • the Gate signal represents the gate drive signal of the fourth transistor T4 in Figure 1
  • the Source signal represents the data signal Da in Figure 1
  • the value V1 is the data signal voltage corresponding to the first sub-pixel
  • the second voltage value V2 is the data signal voltage corresponding to the second sub-pixel.
  • the data signal Da needs to go through the Failing time Tf and the Rising time Tr (Source Settle time) to reach a stable state.
  • the written data signal Da may not be a complete signal, thus affecting the display quality and causing the display question.
  • the present disclosure connects sub-pixels with the same maximum gray-scale value voltage in adjacent pixel units to two adjacent switch units.
  • the source driver The circuit S-IC can continuously output the data signal Da with the same voltage value to provide the data signal Da for the two sub-pixels, so that the stable data signal Da can be obtained during the time when the corresponding fourth transistor T4 of the two sub-pixels is turned on.
  • Tf time and Tr time There is no Tf time and Tr time in Figure 3, which can improve the display quality.
  • Figure 4 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • Figure 5 is a schematic diagram of the connection between some switch units and pixel columns in Figure 4.
  • the display panel may include a display area AA and a non-display area surrounding or at least partially surrounding the display area AA.
  • the display area AA may include a plurality of pixel units distributed in an array along the row and column directions.
  • the pixel unit at least includes a first sub-pixel and a second sub-pixel, and the first sub-pixel
  • the maximum gray scale value voltage is less than the maximum gray scale value voltage of the second sub-pixel;
  • the non-display area can include a source drive circuit S-IC and a switch circuit M.
  • the source drive circuit S-IC can be used to output the data signal Da and switch control. signal;
  • the switch circuit M may include multiple switch units, the control end of the switch unit is used to receive the switch control signal, the first end is used to receive the data signal Da, and the second end is connected to the data line Data; wherein, any nth column pixel unit The first subpixel in and the first subpixel in the (n+1)th column pixel unit are respectively connected to two adjacent switch units through data lines, and n is an odd number greater than or equal to 1.
  • the display panel provided by the present disclosure includes pixel units distributed in a multi-row and multi-column array.
  • the pixel unit at least includes sub-pixels with different maximum gray-scale value voltages.
  • Each column of sub-pixels is connected to a switch unit through a data line Data, and the corresponding Two sub-pixels with the same maximum gray-scale value voltage in adjacent pixel units are connected to two adjacent switch units through corresponding data lines Data.
  • the source The driving circuit S-IC controls the transmission of the data signal Da of the first sub-pixel in the adjacent column pixel unit through two adjacent switch units without the need for data voltage switching.
  • the pole driving circuit S-IC can reduce the number of switching times of data signals Da with different voltage values, thereby allowing the source driving circuit S-IC to output a data signal Da with a stable voltage to ensure display quality.
  • the disclosed display panel does not need to add new processes and masks, and the solution is simple and easy to implement.
  • a display unit may include a first sub-pixel, a second sub-pixel and a third sub-pixel.
  • the maximum gray-scale value voltage of the first sub-pixel is the same as the maximum gray-scale value voltage of the second sub-pixel and the maximum gray-scale value voltage of the third sub-pixel.
  • the gray scale value voltages are different.
  • the first subpixel may be an R subpixel
  • the second subpixel may be a G subpixel
  • the third subpixel may be a B subpixel.
  • the maximum gray scale value voltage of the R subpixel is the same as the G subpixel.
  • the maximum gray-scale value voltages of the G sub-pixel and the B sub-pixel are the same or nearly the same.
  • the maximum gray-scale value voltage of the R sub-pixel may be, for example, 1V
  • the maximum gray-scale value voltage of the G sub-pixel and the B sub-pixel may be, for example, 6.2V.
  • the maximum gray scale value voltage described in this disclosure can be understood as the voltage value of the data signal Da corresponding to the maximum gray scale value of the sub-pixel, that is, the voltage of the data signal Da corresponding to the sub-pixel gray scale value of 255. value.
  • FIG. 6 is a timing diagram of each switching unit when each sub-pixel in FIG. 5 is at the maximum gray scale value voltage.
  • the R sub-pixel in the n-th column pixel unit and the R sub-pixel in the (n+1)-th column pixel unit can be connected to two adjacent switch units using the data line Data, and the source driving circuit S -IC can first control one switch unit to open to output the data signal Da to the R sub-pixel in the n-th column pixel unit, and then control another switch unit adjacent to it to open to output the data signal Da to the (n+1)-th column pixel unit.
  • the R sub-pixel outputs the data signal Da.
  • the source driver circuit S-IC does not need to perform level switching when outputting the two data signals Da.
  • the R sub-pixels of the column output the data signal Da, there is no Tf time and Tr time shown in Figure 3, so the two columns of R sub-pixels can obtain a stable data signal Da.
  • the display can be improved Improve the display quality of the panel and improve the display effect.
  • the data signal Da output by the source driving circuit S-IC needs to be level switched less times within 1H, the data processing frequency of the source driving circuit S-IC is reduced, thereby reducing the overall
  • the power consumption of the source drive circuit S-IC helps the source drive circuit S-IC output a data signal Da with a stable voltage, further ensuring the display effect.
  • the display panel provided by the present disclosure is particularly suitable for displaying achromatic pictures or displaying achromatic pictures in at least part of the area.
  • the data signal voltages of the same sub-pixel in adjacent display units are the same or at least partly the same.
  • the data signal voltages of the same sub-pixel in adjacent display units in the area are the same.
  • AOD Always On Display, always-on mode
  • the display panel structure based on the present disclosure can reduce The number of transitions of the data signal Da in the black area can further reduce the AOD power consumption of smart wearable products.
  • some APP backgrounds such as memo backgrounds and WeChat chat backgrounds, etc.
  • Most R sub-pixels have the same Source voltage
  • most G sub-pixels have the same Source voltage
  • Most B sub-pixels have the same Source voltage.
  • Smart wearable products or terminal products based on the display panel of the disclosure can reduce the number of data signal transitions, thereby not only reducing power consumption, but also reducing Tr and Tf during the data signal Da transition process. The influence can improve the display quality.
  • the source driver circuit S-IC (Source Driver Integrated Circuit, S-IC) is disposed on one side of the display panel, and the source driver circuit S-IC is connected to multiple pieces of data
  • the lines Data are connected to output data signals Da to sub-pixels in different columns through the plurality of data lines Data.
  • the display panel may also include a timing controller (TCON).
  • the timing controller may process each frame of image data and generate data signals Da and D corresponding to each frame of image data.
  • the control signal includes a switch control signal, which is used to control the switching unit in the non-display area on and off.
  • the data signal Da is transmitted to the source driving circuit S-IC.
  • the source driving circuit S-IC converts the received data signal Da into a data voltage and writes it to the corresponding sub-pixel in the display panel.
  • the timing controller TCON can be connected to the printed circuit board (X-Printed Circuit Board, X-PCB) through the flexible circuit board (Flexible Printed Circuit, FPC), and then through the printed circuit board X -PCB connection source driver circuit S-IC.
  • T-CON outputs its control signal to the source driver circuit S-IC through the X-PCB, and T-CON can control the source driver circuit S-IC to input data voltage to the data line Data.
  • the switch circuit M may include multiple switch selection circuits Mux.
  • Each switch in the switch selection circuit Mux is a switch unit.
  • the switch selection circuit Mux may be, for example, a 1:6 MUX switch. , 1:9MUX switch, etc.
  • the control end of the switch unit is connected to the source drive circuit S-IC to obtain the switch control signal output by the source drive circuit S-IC.
  • the first end of the switch unit is connected to receive the data signal Da output by the source drive circuit S-IC.
  • the second end of the switch unit is connected to the corresponding sub-pixel through the data line Data, so as to output the corresponding data signal Da to the connected sub-pixel.
  • multiple switch units are arranged in one-to-one correspondence with multiple columns of sub-pixels, that is, one switch unit controls the transmission of the data signal Da of one column of sub-pixels. Because the data signal voltages of the G sub-pixel and the B sub-pixel are the same or nearly the same, therefore, for the G sub-pixel and the B sub-pixel in the same pixel unit, two adjacent or non-adjacent switching units can be used to perform switching on them. Transmission control of data signals.
  • the G sub-pixel in the n-th column pixel unit is connected to the 3n-th switching unit
  • the B sub-pixel in the n-th column pixel unit is connected to the (3n+2)-th switching unit
  • n is an odd number greater than or equal to 1
  • the G sub-pixel and B sub-pixel in the same pixel unit are respectively connected to two non-adjacent switch units through the data line Data.
  • FIG. 7 is a schematic diagram of the connection between part of the switch unit and the pixel column in FIG. 4 according to another embodiment of the present disclosure. As shown in FIG.
  • the G sub-pixel in the (n+1)th column pixel unit is The data line Data is connected to the (3n+2)th switch unit, the data line Data of the B sub-pixel in the (n+1)th column pixel unit is connected to the (3n+3)th switch unit, and the nth column pixel
  • the B sub-pixel of the unit is connected to the (3n+1) switching unit, and the G sub-pixel of the n-th column pixel unit is connected to the 3n-th switching unit, thereby realizing the G sub-pixel and B in the (n+1)-th column pixel unit.
  • the data line Data of the sub-pixel is connected to the same switch unit, and n is an odd number greater than or equal to 1. Comparing Figure 5, we can see that this connection method can further reduce the number of overlapping traces, thereby simplifying the wiring difficulty.
  • the non-display area of the display panel usually includes other wiring, so it is necessary to conduct flexible wiring based on the overall wiring situation of the non-display area, and satisfy the requirements of the data lines Data and R sub-pixels in the n-th column pixel unit.
  • flexible wiring is performed based on the principle of reducing the overall wiring difficulty.
  • n is an odd number greater than or equal to 1. .
  • connection structure of the pixel unit and the switch unit shown in FIG. 5 may be used as a repeating unit or the connection structure shown in FIG. 6 may be used as a repeating unit.
  • a repeating unit may include a first pixel unit and a second pixel unit that are adjacent in the row direction.
  • the sub-pixels in the first pixel unit and the second pixel unit are arranged in the same manner, and both may include three seeds: R, G, and B.
  • one repeating unit may further include six of the switch units arranged sequentially in the row direction.
  • the switch unit located in the first column is connected to the data line of the R sub-pixel in the first pixel unit, and the switch unit located in the second column is connected to the second pixel unit.
  • the data lines of the R sub-pixels are connected, so that the display panel as a whole has the above-mentioned connection relationship between the switch unit and the sub-pixel column, which can improve the display quality and reduce the overall power consumption of the source driving circuit S-IC.
  • the switching unit may be implemented by a transistor, such as a thin film transistor TFT.
  • the switch circuit M described in the present disclosure may include a plurality of transistors, the control end of the transistor receives the switch control signal output by the source drive circuit S-IC, and the first end of the transistor receives the data output by the source drive circuit S-IC. Signal Da, the second terminal of the transistor is connected to the sub-pixel of the corresponding column through the data line Data.
  • the switch circuit M may include a plurality of ninth transistors T9 and a plurality of tenth transistors T10.
  • the ninth transistors T9 and the tenth transistors T10 are arranged in sequence; the m-th column sub-pixel and the (m+1)-th subpixel The column sub-pixels are different sub-pixels in the same column pixel unit.
  • the ninth transistor T9 corresponding to the m-th column sub-pixel is connected to the data line Data of the m-th column sub-pixel, and the tenth transistor T10 corresponding to the (m+1)-th column sub-pixel is connected The data line Data of the corresponding sub-pixel in the next column of pixel units, where m is a positive integer greater than or equal to 1.
  • a plurality of transistors in the switch circuit M correspond to each column of sub-pixels, that is, a ninth transistor T9 is connected to the data line Data of one column of sub-pixels, and a tenth transistor T10 is connected to the data line Data of the next column of sub-pixels, and the sequence is repeated.
  • the ninth transistor T9 and the data line Data connected thereto are connected through a wiring line, and the wiring line does not overlap with the wiring lines of other transistors connected to the data line Data.
  • the tenth transistor T10 and the data line Data connected thereto are connected through another line, and there is an overlap between the other line and the line connecting other data lines Data.
  • the non-display area and display area AA of the display panel of the present disclosure can share a film layer, that is, the active layer of the non-display area and the active layer of the display area AA are the same film layer, and the first conductive layer of the non-display area
  • the second conductive layer in the non-display area and the second conductive layer in the display area AA are the same film layer
  • the third conductive layer in the non-display area and the second conductive layer in the display area AA are the same film layer.
  • the third conductive layer is the same film layer, and the film layers may have the same insulating layer.
  • Figure 8 is a cross-sectional view along the dotted line AA direction corresponding to the position of the tenth transistor in Figure 4.
  • Figure 9 is a cross-sectional view along the dotted line BB direction corresponding to the ninth transistor position in Figure 4.
  • the active layer 10 may include a plurality of second active parts 12 and a plurality of fifth active parts 15 , the second active parts 12 may be used to form a channel region of the ninth transistor T9 , and the fifth active parts 15 It can be used to form the channel region of the tenth transistor T10.
  • the active layer 10 may further include a plurality of first active parts 11 , a plurality of third active parts 13 , a plurality of fourth active parts 14 and a plurality of sixth active parts 16 .
  • the first active parts 11 and The third active part 13 and the second active part 12 are arranged in one-to-one correspondence, and the first active part 11 and the third active part 13 are respectively connected to both ends of the second active part 12 to respectively form a third active part 13 .
  • the fourth active part 14 and the sixth active part 16 are arranged in one-to-one correspondence with the fifth active part 15, and the fourth active part 14 and the sixth active part 16 are respectively connected to the fifth active part.
  • the first active part 11 may be connected to the first conductive line 41 of the third conductive layer 40 through a via hole, and the first conductive line 41 may be connected to the first conductive line 41 of the first conductive layer 20 through the first transfer part 31 or directly through the via hole.
  • the connection line 21 is such that the first end of the ninth transistor T9 is connected to the source driving circuit S-IC through the first connection line 21 .
  • the fourth active part 14 can be connected to the fourth conductive line 44 of the third conductive layer 40 through a via hole, and the fourth conductive line 44 is connected to the first conductive layer through the second transfer part 32 or directly through the via hole. 20, so that the first end of the tenth transistor T10 is connected to the source driving circuit S-IC through the second connection line 22.
  • the first conductive layer 20 may be the Gate1 layer of the display area AA, and the first conductive layer 20 may include a plurality of first gate lines G1 and a plurality of second gate lines.
  • the line G2, the orthographic projection of the first gate line G1 and the second gate line G2 on the base substrate 10 can all extend along the first direction, and the orthographic projection of the first gate line G1 on the base substrate 10 can cover the second active portion. 12
  • part of the structure of the first gate line G1 forms the gate of the ninth transistor T9.
  • the first gate line G1 can be connected to the source driving circuit S-IC to obtain the corresponding switch control signal.
  • the orthographic projection of the second gate line G2 on the base substrate 10 can cover the orthographic projection of the fifth active part 15 on the base substrate 10 .
  • Part of the structure of the second gate line G2 forms the gate of the tenth transistor T10 .
  • the line G2 is also connected to the source driving circuit S-IC to obtain the switching control signal output by the source driving circuit S-IC.
  • the first conductive layer 20 may also include a plurality of first connection lines 21.
  • the orthographic projection of the first connection lines 21 on the base substrate 10 may extend along the second direction.
  • One end of the first connection lines 21 may be connected to the source driving circuit S. -IC to obtain the data signal Da output by the source driving circuit S-IC.
  • the other end of the first connection line 21 can be connected to the second conductive line 42 located on the third conductive layer 40 through a via hole.
  • the second conductive line 42 and The first adapter portion 31 and the first conductive line 41 connected thereto are connected to the first active portion 11 , thereby connecting the first end of the ninth transistor T9 to the source driving circuit S-IC.
  • the first conductive layer 20 may also include a plurality of second connection lines 22 , the orthographic projection of the second connection lines 22 on the substrate 10 may extend along the second direction, and one end of the second connection lines 22 may be connected to the source.
  • the other end of the driving circuit S-IC can be connected to the third conductive line 43 located on the third conductive layer 40 through a via hole.
  • the third conductive line 43 and the second adapter 32 and fourth conductive line 44 connected thereto are connected to the third conductive line 43 .
  • the fourth active part connects the first end of the tenth transistor T10 to the source driving circuit S-IC.
  • the first conductive layer 20 may also include a transfer line 23 , which may be provided in one-to-one correspondence with the sixth active part 16 .
  • the transfer line 23 is on the substrate.
  • the orthographic projection of the substrate 10 may extend along the first direction, one end of the transfer line 23 may be connected to the sixth conductive line 46 of the third conductive layer 40 through a via hole, and the other end may be connected to adjacent pixels in the third conductive layer 40 through a via hole.
  • the data line Data of the unit is used to connect the second end of the tenth transistor T10 to the data line Data of the corresponding sub-pixel in the adjacent pixel unit.
  • the transfer line 23 on the first conductive layer 20
  • the second end of the tenth transistor T10 can be connected to the data line Data of the corresponding sub-pixel in the adjacent pixel unit, thereby avoiding the connection with the data line Data of other sub-pixels.
  • the other traces of the third conductive layer 40 are connected.
  • the transfer wire 23 on the first conductive layer 20 so that the transfer wire 23 and the data line Data of the third conductive layer 40 are further apart, and more insulating layers are provided for electrical isolation, the size of the transfer wire 23 can be reduced.
  • the parasitic capacitance between the data line Data and the data line Data reduces the signal impact on the data line Data and ensures the display effect.
  • the transfer line 23 may also be located on the second conductive layer 30, and the present disclosure is not limited thereto.
  • the second conductive layer 30 may be the Gate2 layer of the display area AA, and the second conductive layer 30 may include a first transfer part 31 and a second transfer part 32 , the first adapter portion 31 is provided correspondingly to the first connection line 21 of the first conductive layer 20 , that is, one first adapter portion 31 is correspondingly connected to one first connection line 21 .
  • the orthographic projection of the first adapter portion 31 on the base substrate 10 may be located between the orthographic projection of the first connection line 21 on the base substrate 10 and the orthographic projection of the first active portion 11 on the base substrate 10 , and, An adapter part 31 can connect the first conductive line 41 and the second conductive line 42 of the third conductive layer 40 through via holes respectively, so that the first conductive line 41 and the second conductive line 42 can be connected through the first adapter part 31 Make electrical connections.
  • the second adapter part 32 can be provided corresponding to the second connection line 22 , that is, one second connection line 22 is connected to one second adapter part 32 , and the second adapter part 32 is in the orthographic projection of the base substrate 10
  • the second connection line 22 can be located between the orthographic projection of the base substrate 10 and the fourth active portion 14 on the orthographic projection of the base substrate 10
  • the second transfer portion 32 can be connected to the third conductive layer through via holes respectively. 40 of the third conductive wire 43 and the fourth conductive wire 44 , so that the third conductive wire 43 and the fourth conductive wire 44 are electrically connected through the second adapter 32 .
  • first transfer part 31 and the second transfer part 32 may also be located on other conductive layers, such as the first conductive layer 20 , etc., that is, the first conductive line 41 and the second conductive line 41 .
  • the conductive line 42 can also be transferred at the first conductive layer 20, and the third conductive line 43 and the fourth conductive line 44 can also be transferred at the first conductive layer 20, depending on whether there are other traces at this position. Disclosure is not limited to this.
  • the third conductive layer 40 may be the SD layer of the display area AA.
  • the third conductive layer 40 may include a plurality of data lines Data.
  • One data line Data connects one column of sub-pixels to provide data to the column of sub-pixels.
  • the third conductive layer 40 may also include a first conductive line 41 and a second conductive line 42.
  • the first conductive line 41 may be respectively connected to one end of the first active part 11 and the first adapter part 31 through a via hole.
  • the line 42 can be connected to the other end of the first transfer portion 31 through the via hole and the first connection line 21 of the first conductive layer 20 through the via hole, respectively, thereby connecting the first end of the ninth transistor T9 to the first connection line.
  • 21 is further connected to the source driving circuit S-IC to obtain the data signal Da output by the source driving circuit S-IC.
  • the third conductive layer 40 may also include a third conductive line 43 and a fourth conductive line 44.
  • the fourth conductive line 44 may be connected to one end of the fourth active part 14 and the second transfer part 32 through a via hole respectively.
  • the wire 43 may be connected to the other end of the second transfer part 32 and the second connection wire 22 respectively through the via holes, thereby connecting the first end of the tenth transistor T10 to the second connection wire 22 through the third conductive wire 43 and the fourth conductive wire 44 .
  • the connection line 22 is further connected to the source driving circuit S-IC to obtain the data signal Da output by the source driving circuit S-IC.
  • the third conductive layer 40 may also include sixth conductive lines 46.
  • the sixth conductive lines 46 are arranged in one-to-one correspondence with the sixth active parts 16. That is, one sixth active part 16 is connected to one sixth conductive line 46.
  • the wire 46 can pass through the sixth active part 16 through the via hole and one end of the adapter wire 23 respectively.
  • the other end of the adapter wire 23 extends to the corresponding data line Data, and is connected to the data line Data at the corresponding position through the via hole, so as to achieve through the third
  • the six-conducting wire 46 and the adapter wire 23 connect the second end of the tenth transistor T10 to the data line Data of the sub-pixel in the adjacent pixel unit.
  • FIG. 10 is a schematic diagram of an orthographic overlay of a patch cord and a data line according to an embodiment of the present disclosure.
  • the patch cord 23 is in the orthographic projection of the substrate 10 and connected thereto.
  • the angle ⁇ between the orthographic projection of the sixth conductive line 46 on the base substrate 10 is greater than or equal to 60° and less than or equal to 120°, for example, it can be 60°, 70°, 80°, 90°, 100°, 110°, 120°. ° etc.
  • the angle ⁇ formed by the intersection of the orthographic projection of the transfer line 23 on the base substrate 10 and the orthographic projection of the data line Data on the base substrate 10 is greater than or equal to 60° and less than or equal to 120°, and may be, for example, 60°, 70°, or 80°. , 90°, 100°, 110°, 120°, etc.
  • the included angle ⁇ and the included angle ⁇ may be the same or different.
  • the above-mentioned included angle ⁇ and included angle ⁇ can both be set to 90°, that is, the orthographic projection of the adapter line 23 on the base substrate 10 and the orthographic projection of the data base substrate 10 and the The orthographic projections of the sixth conductive lines 46 on the base substrate 10 all intersect perpendicularly, which can minimize the overlapping area.
  • the parasitic capacitance between the transfer line 23 and the data line Data can be minimized.
  • the present disclosure also provides a method for manufacturing a display panel, which can be used to form a display panel with the structure shown in FIG. 8 .
  • a display panel preparation method As shown in Figures 11 to 20b, it is a process flow chart of a display panel preparation method according to an embodiment of the present disclosure.
  • the preparation method may include:
  • the base substrate 10 includes a display area AA and a non-display area at least partially surrounding the display area AA. As shown in FIG. 11 , the base substrate 10 can be made of transparent glass, quartz glass, etc. When the display panel is a flexible display panel, the base substrate 10 can also be made of organic materials such as polyimide (PI). flexible substrate.
  • PI polyimide
  • a plasma enhanced chemical vapor deposition (PECVD) process can also be used to deposit a buffer material to form a buffer layer covering the base substrate 10 .
  • the buffer material may be, for example, at least one of silicon nitride, silicon oxide, or silicon oxynitride, wherein the buffer layer may have a single-layer structure or a multi-layer structure.
  • the buffer materials of different layers may be the same or different.
  • a sputtering process can be used to deposit semiconductor material on the base substrate 10 to form the active layer 10.
  • the semiconductor material may be, for example, polysilicon material.
  • the formed ninth transistor T9 and the tenth transistor T10 may be P-type low-temperature polysilicon thin film transistors.
  • the active layer 10 can be exposed, developed and etched to produce a plurality of fifth active portions 15, a plurality of sixth active portions 16 and a plurality of fourth active portions 14, Among them, the fifth active part 15 is used to form the channel region of the tenth transistor T10.
  • the fourth active part 14 and the fifth active part 15 are respectively connected to both sides of the fourth active part 14 to form the tenth transistor.
  • the active layer 10 may further include a plurality of first active parts 11 , a plurality of second active parts 12 and a plurality of third active parts 13 .
  • the source part 12 is used to form a channel region of the ninth transistor T9.
  • the first active part 11 and the third active part 13 are respectively located on both sides of the second active part 12 and are used to form a first channel region of the ninth transistor T9. end and second end.
  • a PECVD process may be used to deposit a first inorganic material to form the first gate insulating layer GI1 , and the first inorganic material may be, for example, SiO2 .
  • the first conductive material may be Mo, for example.
  • Sputter equipment can be used to deposit the first conductive layer 20 covering the first gate insulating layer GI1, and perform an etching process on the first conductive layer 20 to obtain a plurality of second gate lines G2 and a plurality of transfer lines 23.
  • the orthographic projection of the second gate line G2 on the base substrate 10 may extend along the first direction and may cover the orthographic projection of the fifth active part 15 on the base substrate 10 , and part of the structure of the second gate line G2 is used to form The gate of the tenth transistor T10; the orthographic projection of the transfer line 23 on the base substrate 10 can extend along the first direction, and the transfer line 23 can connect the sixth conductive line 46 and the corresponding data line in the adjacent pixel unit through via holes respectively. Data, so as to connect the second end of the tenth transistor T10 with the data line Data of the corresponding sub-pixel in the adjacent pixel unit through the transfer line 23 in the first conductive layer 20 .
  • a plurality of second connection lines 22 can also be formed on the first conductive layer 20 by etching, and the orthographic projection of the second connection lines 22 on the base substrate 1 can be along the second Extending in the direction, the second connection line 22 and the transfer line 23 are located on both sides of the second gate line G2, so that the first end of the tenth transistor T10 is connected to the source driving circuit S-IC through the second connection line 22.
  • a plurality of first gate lines G1 and a plurality of first connection lines 21 can also be formed on the first conductive layer 20 by etching.
  • the first gate lines G1 are formed on the base substrate.
  • the orthographic projection of 1 may extend along the first direction and may cover the orthographic projection of the second active part 12 on the base substrate 1 , and the partial structure of the first gate line G1 is used to form the gate of the ninth transistor T9 .
  • the orthographic projection of the first connection line 21 on the base substrate 1 may extend along the second direction.
  • the first connection line 21 is connected to the source driving circuit S-IC, and the first terminal of the ninth transistor T9 is connected through the first connection line 21 . Connect to the source driver circuit S-IC.
  • a second inorganic material may also be deposited using a PECVD process to form the second gate insulating layer GI2.
  • the second inorganic material may be SiNx, for example.
  • a Sputter device may also be used to deposit the second conductive layer 30 covering the second gate insulating layer GI2.
  • the material of the second conductive layer 30 may be Mo, for example.
  • an etching process can be used to form a plurality of second transfer portions 32 and a plurality of first transfer portions 31 on the second conductive layer 30 , wherein the orthographic projection of the second transfer portions 32 on the base substrate 1 can be located on the first between the front projection of the four active parts 14 on the base substrate 1 and the front projection of the second connection line 22 on the base substrate 1 , the second transfer part 32 can be connected to the corresponding third conductive line 43 through a via hole. and fourth conductive line 44.
  • the orthographic projection of the first transfer part 31 on the base substrate 1 may be located between the orthographic projection of the first active part 11 on the base substrate 1 and the orthographic projection of the first connection line 21 on the base substrate 1 .
  • the connecting portion 31 can be connected to the first conductive line 41 and the second conductive line 42 through via holes respectively.
  • the PECVD process may also be used to deposit the first inorganic material or the second inorganic material to form the interlayer dielectric layer ILD, and then as shown in Figure 18a and Figure 18b, a dry etching process can be used to form multiple via holes on the interlayer dielectric layer.
  • S40 Use a deposition process to deposit a second conductive material on the side of the first conductive layer 20 facing away from the base substrate 1 to form a third conductive layer 40.
  • Sputter equipment can be used to deposit a second conductive material to form a third conductive layer 40, and then an etching process is used to form the third conductive layer 40 into a plurality of data lines Data and a plurality of sixth conductive lines 46.
  • the orthographic projection of the line Data on the base substrate 1 may extend along the second direction, and one data line Data connects one column of sub-pixels.
  • the sixth conductive line 46 is provided corresponding to the sixth active part 16.
  • the orthographic projection of the sixth conductive line 46 on the base substrate 1 may extend along the second direction.
  • the sixth conductive line 46 is connected to the sixth active part 16 through a via hole. .
  • an etching process can also be used to form a plurality of fourth conductive lines 44 and a plurality of third conductive lines 43 on the third conductive layer 40 , and the fourth conductive lines 44 pass through the via holes.
  • the fourth active part 14 and the second transfer part 32 are connected, and the third conductive wire 43 connects the second transfer part 32 and the second connection wire 22 through the via hole, so as to pass through the third conductive wire 43 and the second transfer part 32.
  • the fourth conductive line 44 and the second connection line 22 connect the first end of the tenth transistor T10 to the source driving circuit S-IC.
  • an etching process can also be used to form a plurality of first conductive lines 41 and a plurality of second conductive lines 42 on the third conductive layer 40.
  • the first conductive lines 41 are first
  • the conductive wire 41 connects the first active part 11 and the first transfer part 31 through the via hole
  • the second conductive wire 42 connects the first transfer part 31 and the first connection wire 21 through the via hole, so that the first conductive wire 42 41.
  • the first transfer part 31, the second conductive line 42 and the first connection line 21 connect the first end of the ninth transistor T9 to the source driving circuit S-IC.
  • a spin coating process Coating
  • a curing process may also be used to form a planarization layer.
  • the present disclosure also provides a display device, including the display panel described in any of the above embodiments.
  • the display device can be a display device such as a mobile phone, a tablet computer, or a smart watch.

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Abstract

本公开提供一种显示面板及其制备方法、显示装置。该显示面板包括：显示区(AA)，显示区(AA)包括沿行列方向阵列分布的多个像素单元，像素单元包括多个子像素，且至少一个子像素具有不同于其他子像素的最大灰阶值电压；源极驱动电路(S-IC)，位于显示区(AA)的一侧，源极驱动电路(S-IC)用于输出数据信号和开关控制信号；开关电路(M)，位于显示区(AA)的一侧，开关电路(M)包括多个开关单元，开关单元的控制端用于接收开关控制信号，第一端用于接收数据信号，第二端连接数据线；其中，在任意第n列像素单元和第(n+1)列像素单元中，具有相同的最大灰阶值电压的两个子像素分别通过数据线与相邻的两个开关单元连接，n为大于等于1的奇数。 (图5)

Description

显示面板及其制备方法、显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示面板及其制备方法、显示装置。
背景技术
在OLED显示面板中，各子像素通过对应的像素驱动电路驱动子像素进行发光。相关技术中，数据线上的数据信号电压不稳定，影响显示画质。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于克服上述现有技术的不足，提供一种显示面板及其制备方法、显示装置。
根据本公开的一个方面，提供一种显示面板，包括：显示区，所述显示区包括沿行列方向阵列分布的多个像素单元，所述像素单元至少包括第一子像素和第二子像素，且所述第一子像素的最大灰阶值电压小于所述第二子像素的最大灰阶值电压；源极驱动电路，位于所述显示区的一侧，所述源极驱动电路用于输出数据信号和开关控制信号；开关电路，位于所述显示区的一侧，所述开关电路包括多个开关单元，所述开关单元的控制端用于接收所述开关控制信号，第一端用于接收所述数据信号，第二端连接数据线；其中，任意第n列像素单元中的第一子像素和第(n+1)列像素单元中的第一子像素分别通过所述数据线与相邻的两个开关单元连接，n为大于等于1的奇数。
在本公开的一种示例性实施例中，所述像素单元还包括第三子像素，在同一像素单元中的所述第二子像素和所述第三子像素分别通过所述数据线与相邻的两个开关单元或间隔的两个开关单元连接。
在本公开的一种示例性实施例中，所述多个开关单元与多列子像素一一对应设置。
在本公开的一种示例性实施例中，所述显示面板包括沿行方向分布的多个重复单元，所述重复单元包括在行方向上相邻的第一像素单元和第二像素单元以及在行方向上依次排列的六个所述开关单元；在所述重复单元内，位于第一列的所述开关单元与所述第一像素单元中的第一子像素的数据线连接，位于第二列的所述开关单元与所述第二像素单元中的第一子像素的数据线连接。
在本公开的一种示例性实施例中，所述第一子像素为R子像素。
在本公开的一种示例性实施例中，所述开关单元为晶体管。
在本公开的一种示例性实施例中，所述开关电路包括多个第九晶体管和多个第十晶体管，所述第九晶体管和所述第十晶体管依次间隔排列；第m列子像素与第(m+1)列子像素为同一列像素单元中的不同子像素，对应于第m列子像素的第九晶体管连接第m列子像素的数据线，对应于第(m+1)列子像素的第十晶体管连接下一列像素单元中对应子像素的数据线，其中，m为大于等于1的正整数。
在本公开的一种示例性实施例中，所述第十晶体管通过转接线连接下一列像素单元中对应子像素的数据线，且所述转接线与所述数据线位于不同导电层。
在本公开的一种示例性实施例中，所述显示面板还包括：衬底基板，所述衬底基板包括所述显示区；有源层，位于所述衬底基板的一侧，所述有源层包括：多个第五有源部，所述第五有源部用于形成所述第十晶体管的沟道区；多个第六有源部，所述第六有源部连接于所述第五有源部的一侧；第一导电层，位于所述有源层背离所述衬底基板的一侧，所述第一导电层包括：多条第二栅线，所述第二栅线在所述衬底基板的正投影覆盖所述第五有源部在所述衬底基板的正投影，所述第二栅线的部分结构用于形成所述第十晶体管的栅极；第三导电层，位于所述第一导电层背离所述衬底基板的一侧，所述第三导电层包括：多条数据线，一条所述数据线连接一列子像素；多条第六导电线，与所述第六有源部对应设置，所述第六导电线通过过孔连接所述第六有源部；其中，所述转 接线分别通过过孔连接所述第六导电线和相邻像素单元中的对应数据线。
在本公开的一种示例性实施例中，所述转接线位于所述第一导电层。
在本公开的一种示例性实施例中，所述转接线在所述衬底基板的正投影和与其连接的所述第六导电线在所述衬底基板的正投影的夹角大于等于60°且小于等于120°；所述转接线在所述衬底基板的正投影与所述数据线在所述衬底基板的正投影相交形成的夹角大于等于60°且小于等于120°。
在本公开的一种示例性实施例中，所述有源层还包括：第四有源部，连接于所述第五有源部远离所述第六有源部的一侧；所述第一导电层还包括：多条第二连接线，所述第二连接线连接所述源极驱动电路；所述第三导电层还包括：多条第四导电线，与所述第四有源部对应设置，所述第四导电线通过过孔连接与其对应的所述第四有源部；多条第三导电线，与所述第二连接线对应设置，所述第三导电线通过过孔连接与其对应的所述第二连接线；所述显示面板还包括：第二导电层，位于所述第一导电层和所述第三导电层之间，所述第二导电层包括：多个第二转接部，与所述第五有源部对应设置，所述第二转接部在所述衬底基板的正投影位于所述第四有源部在所述衬底基板的正投影和所述第二连接线在所述衬底基板的正投影之间，所述第二转接部分别通过过孔连接与其对应的所述第三导电线和所述第四导电线。
在本公开的一种示例性实施例中，所述有源层还包括：多个第二有源部，在所述衬底基板的正投影位于所述非显示区，所述第二有源部用于形成所述第九晶体管的沟道区；多个第一有源部，与所述第二有源部对应设置，所述第一有源部连接于所述第二有源部的一侧；多个第三有源部，与所述第二有源部对应设置，所述第三有源部连接于所述第二有源部远离所述第一有源部的一侧，所述第二有源部通过过孔连接与其对应的数据线；所述第一导电层还包括：多条第一栅线，所述第一栅线在所述衬底基板的正投影覆盖所述第二有源部在所述衬底基板的正投影，所述第一栅线的部分结构用于形成所述第九晶体管的栅极；多条第一连接线，所述第一连接线连接所述源极驱动电路；所述第二导电层还包括：多个第一转接部，与所述第二有源部对应设置，所述第一转接部在所述 衬底基板的正投影位于所述第一有源部在所述衬底基板的正投影和所述第一连接线在所述衬底基板的正投影之间；所述第三导电层还包括：多条第一导电线，所述第一导电线通过过孔连接与其对应的所述第一有源部和所述第一转接部；多条第二导电线，所述第二导电线通过过孔连接与其对应的所述第一连接线和所述第一转接部。
在本公开的一种示例性实施例中，所述开关电路包括多个开关选择电路，所述开关选择电路包括多个所述开关单元。
根据本公开的另一方面，还提供一种显示面板的制备方法，用于制备本公开上述实施例所述的显示面板，所述方法包括：提供一衬底基板，所述衬底基板包括显示区和至少部分围绕所述显示区的非显示区；利用沉积工艺在所述衬底基板一侧的非显示区形成有源层，其中，所述有源层包括第五有源部和连接于所述第五有源部一侧的第六有有源部，所述第五有源部用于形成所述第十晶体管的沟道区；利用沉积工艺在所述有源层背离所述衬底基板的一侧形成第一导电层，其中，所述第一导电层包括多条第二栅线和多条转接线，所述第二栅线在所述衬底基板的正投影覆盖所述第五有源部在所述衬底基板的正投影，所述第二栅线的部分结构用于形成所述第十晶体管的栅极；所述转接线分别通过过孔连接所述第六导电线和相邻像素单元中的对应数据线；利用沉积工艺在第一导电层背离所述衬底基板的一侧形成第三导电层，其中，所述第三导电层包括多条数据线和多条第六导电线，一条所述数据线连接一列子像素，所述第六导电线与所述第六有源部对应设置，所述第六导电线通过过孔连接所述第六有源部。
在本公开的一种示例性实施例中，在所述利用沉积工艺在所述有源层背离所述衬底基板的一侧形成第一导电层之前，所述方法还包括：利用沉积工艺在所述衬底基板和所述有源层上沉积第一无机材料形成第一栅绝缘层；所述利用沉积工艺在所述有源层背离所述衬底基板的一侧形成第一导电层，包括：利用沉积工艺在所述第一栅绝缘层上沉积所述第一导电材料形成所述第一导电层。
在本公开的一种示例性实施例中，在所述利用沉积工艺在所述有源层背离所述衬底基板的一侧形成第一导电层之后，所述方法还包括：利 用沉积工艺在所述第一导电层上沉积第二无机材料形成第二栅绝缘层；利用沉积工艺在所述第二栅绝缘层上沉积第一导电材料形成第二导电层；利用构图工艺在所述第二导电层形成多个第二转接部，其中，所述第二转接部与所述第五有源部对应设置，所述第二转接部在所述衬底基板的正投影位于所述第四有源部在所述衬底基板的正投影和所述第二连接线在所述衬底基板的正投影之间，所述第二转接部分别通过过孔连接与其对应的所述第三导电线和所述第四导电线；利用沉积工艺在所述第二导电层上沉积第一无机材料或第二无机材料形成层间介电层；利用刻蚀工艺在所述层间介电层上形成多个过孔。
在本公开的一种示例性实施例中，所述利用沉积工艺在第一导电层背离所述衬底基板的一侧形成第三导电层，包括：利用沉积工艺在所述层间介电层上沉积第二导电材料形成第三导电层；利用刻蚀工艺在所述第三导电层上形成多条所述数据线和多条所述第六导电线。
在本公开的一种示例性实施例中，在形成所述第三导电层之后，所述方法还包括：平坦化所述第三导电层。
根据本公开的第三方面，还提供一种显示装置，包括本公开任意实施例所述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为根据本公开一种实施方式显示面板中像素驱动电路的电路结构示意图；
图2为图1中像素驱动电路一种驱动方法中各节点的时序图；
图3为根据本公开一种实施方式的数据信号的切换示意图；
图4为根据本公开一种实施方式的显示面板的结构示意图；
图5为图4中部分开关单元与像素列的连接示意图；
图6为图5中各子像素均为最大灰阶值电压时各开关单元的时序图；
图7为根据本公开另一种实施方式的图4中部分开关单元与像素列的连接示意图；
图8为图4中沿虚线AA方向对应第十晶体管位置的剖视图；
图9为图4中沿虚线BB方向对应第九晶体管位置的剖视图；
图10为根据本公开一种实施方式的转接线与数据线的正投影交叠示意图；
图11～图20b为根据本公开一种实施方式中显示面板制备方法的工艺流程图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
本公开显示面板的显示区包括沿行列方向阵列分布的像素单元，每一像素单元可以多个子像素，各子像素可通过对应的像素驱动电路为其提供驱动电流而驱动其进行发光显示。本公开显示面板中的像素驱动电路可以是4T1C、5T1C、5T2C、6T1C或7T1C结构等。在本公开的一示例性实施例中，像素驱动电路为7T1C结构，图1为根据本公开一种实施方式显示面板中像素驱动电路的电路结构示意图。该像素驱动电路可以包括：第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、电容C。其中，第一晶体管T1的第一极连接节点N，第二极连接第一初始信号端Vinit1，栅极连接复位信号端Re1；第二晶体管T2第一极连接驱动晶体管T3的第一极，第二极连接节点N；栅极连接栅极驱动信号端Gate；驱动晶体 管T3的栅极连接节点N；第四晶体管T4的第一极连接数据信号端Da，第二极连接驱动晶体管T3的第二极，栅极连接栅极驱动信号端Gate；第五晶体管T5的第一极连接驱动晶体管T3的第二极，第二极连接第一电源端VDD，栅极连接使能信号端EM；第六晶体管T6第一极连接驱动晶体管T3的第一极，栅极连接使能信号端EM；第七晶体管T7的第一极连接第六晶体管T6的第二极，第二极连接第二初始信号端Vinit2，栅极连接复位信号端Re2。电容C连接于驱动晶体管T3的栅极和第一电源端VDD之间。该像素驱动电路可以连接一发光单元OLED，用于驱动该发光单元OLED发光，发光单元OLED可以连接于第六晶体管T6的第二极和第二电源端VSS之间。其中，晶体管T1-T7可以均为P型晶体管或N型晶体管，或者部分为P型晶体管，部分为N型晶体管。例如，第一晶体管T1～第七晶体管T7均为P型晶体管或者均为N型晶体管，或者，第一晶体管T1和第二晶体管T2为P型晶体管，第三晶体管T3～第七晶体管T7为N型晶体管等。
需要说明的是，本公开各实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。
图2为图1中像素驱动电路一种驱动方法中各节点的时序图。其中，Gate表示栅极驱动信号端Gate的时序，Re1表示复位信号端Re1的时序，Re2表示复位信号端Re2的时序，EM表示使能信号端EM的时序，Da表示数据信号端Da的时序。该像素驱动电路的驱动方法可以包括复位阶段t1、补偿阶段t2，发光阶段t3。在复位阶段t1：复位信号端Re1输出低电平信号，第一晶体管T1导通，第一初始信号端Vinit1向节点N输入初始信号。在补偿阶段t2：复位信号端Re2、栅极驱动信号端Gate输出低电平信号，第四晶体管T4、第二晶体管T2、第七晶体管T7导通，同时数据信号端Da输出驱动信号以向节点N写入电压Vdata+Vth，其中Vdata为驱动信号的电压，Vth为驱动晶体管T3的阈值电压，第二初始信号端Vinit2向第六晶体管T6的第二极输入初始信号。发光阶段t3：使能信号端EM输出低电平信号，第六晶体管T6、第五晶体管T5导通， 驱动晶体管T3在电容C存储的电压Vdata+Vth作用下发光。根据驱动晶体管输出电流公式I＝(μWCox/2L)(Vgs-Vth) 2，其中，μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电压。本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth) 2。该像素驱动电路能够避免驱动晶体管阈值电压对其输出电流的影响。
应该理解的是，在补偿阶段t2，第四晶体管T4打开，源极驱动电路通过数据线向子像素提供对应的数据信号，在第四晶体管T4打开的过程中，需要保证数据信号端输出的数据信号电压Vdata保持稳定不变，以避免显示异常问题。
图3为根据本公开一种实施方式的数据信号的切换示意图，图中，Gate信号表示图1中第四晶体管T4的栅极驱动信号，Source信号表示图1中的数据信号Da，第一电压值V1为第一子像素对应的数据信号电压，第二电压值V2为第二子像素对应的数据信号电压。如图3所示，数据信号Da需要经过Failing时间Tf和Rising时间Tr(Source Settle time)方可达到稳定状态。因为Tf和Tr时间的影响，若是在Tf和/或Tr时间内向图1中的第四晶体管T4写数据信号Da，所写入的数据信号Da可能非完整信号，从而影响显示画质，造成显示问题。
针对上述技术问题，本公开通过将相邻像素单元中具有相同的最大灰阶值电压的子像素连接相邻的两个开关单元，当这两个子像素所需要显示的亮度相同时，源极驱动电路S-IC可连续输出电压值相同的数据信号Da为这两个子像素提供数据信号Da，从而这两个子像素各自对应的第四晶体管T4打开的时间内均能够获取到稳定的数据信号Da，不存在图3中的Tf时间和Tr时间，能够改善显示画质。下面结合附图对本公开方案进行详细说明。
图4为根据本公开一种实施方式的显示面板的结构示意图，图5为图4中部分开关单元与像素列的连接示意图，如图4、图5所示，该显示面板可以包括显示区AA和围绕或至少部分围绕显示区AA的非显示区，显示区AA可以包括沿行列方向阵列分布的多个像素单元，像素单 元至少包括第一子像素和第二子像素，且第一子像素的最大灰阶值电压小于第二子像素的最大灰阶值电压；非显示区可以包括源极驱动电路S-IC和开关电路M，源极驱动电路S-IC可用于输出数据信号Da和开关控制信号；开关电路M可以包括多个开关单元，开关单元的控制端用于接收开关控制信号，第一端用于接收数据信号Da，第二端连接数据线Data；其中，任意第n列像素单元中的第一子像素和第(n+1)列像素单元中的第一子像素分别通过数据线与相邻的两个开关单元连接，n为大于等于1的奇数。
本公开提供的显示面板，包括多行多列阵列分布的像素单元，像素单元至少包括具有不同的最大灰阶值电压的子像素，每一列子像素通过一条数据线Data连接一个开关单元，将相邻的像素单元中具有相同的最大灰阶值电压的两个子像素通过对应的数据线Data连接至相邻的两个开关单元，当显示面板为非彩色显示或者部分区域非彩色显示时，源极驱动电路S-IC通过两个相邻的开关单元对相邻列像素单元中的第一子像素的数据信号Da进行传输控制，无需进行数据电压切换，相比于常规的电路结构，本公开源极驱动电路S-IC可以减少不同电压值的数据信号Da的切换次数，由此可使得源极驱动电路S-IC输出电压稳定的数据信号Da，保证显示画质。本公开显示面板无需增加新的工艺和Mask，方案简单、易行。
通常，一个显示单元可以包括第一子像素、第二子像素和第三子像素，第一子像素的最大灰阶值电压与第二子像素的最大灰阶值电压以及第三子像素的最大灰阶值电压不同，通过将相邻像素单元中的第一子像素连接相邻的两个开关单元，可以减少不同的数据信号电压的切换次数。在示例性实施例中，第一子像素可以为R子像素，第二子像素可以为G子像素，第三子像素可以为B子像素，R子像素的最大灰阶值电压与G子像素和B子像素的最大灰阶值电压不同，G子像素和B子像素的最大灰阶值电压相同或接近相同。R子像素的最大灰阶值电压例如可以为1V，G子像素和B子像素的最大灰阶值电压例如可以为6.2V。
本公开所述的最大灰阶值电压可以理解为，子像素的灰阶值最大时所对应的数据信号Da的电压值，亦即子像素的灰阶值为255时对应的 数据信号Da的电压值。
在示例性实施例中，图6为图5中各子像素均为最大灰阶值电压时各开关单元的时序图，如图6所示，对于第n列像素单元和第(n+1)列像素单元，可将第n列像素单元中的R子像素和第(n+1)列像素单元中的R子像素分别使用数据线Data连接相邻的两个开关单元，源极驱动电路S-IC可先控制一个开关单元打开以向第n列像素单元中的R子像素输出数据信号Da后，再控制与其相邻的另一开关单元打开以向第(n+1)列像素单元中的R子像素输出数据信号Da。当这两列像素单元中的R子像素的数据信号电压相同时，如图6所示，源极驱动电路S-IC输出这两路数据信号Da时无需进行电平切换，即在向这两列的R子像素输出数据信号Da时，不存在图3所示的Tf时间和Tr时间，从而这两列R子像素能够获取到稳定的数据信号Da，显然，通过这样的设置，可以改善显示面板的显示画质，提高显示效果。
此外，因为在1H时间内源极驱动电路S-IC输出的数据信号Da需要进行电平切换的次数得以减少，从而降低了源极驱动电路S-IC对于数据的处理频率，从而整体上降低了源极驱动电路S-IC的功耗，有助于源极驱动电路S-IC输出电压稳定的数据信号Da，进一步保证显示效果。
可以理解的是，本公开提供的显示面板尤其适用于显示非彩色画面或者至少部分区域显示非彩色画面的情况，该情况下相邻的显示单元中的同一种子像素的数据信号电压相同或者至少部分区域中相邻显示单元中的同一种子像素的数据信号电压相同。例如，在智能手环、智能手表等智能穿戴产品中，对于AOD(Always On Display，常亮模式)低功耗画面，在指针或表盘位置是正常显示，在其他区域是黑色，而显示黑色区域的不同像素列的R子像素的数据信号电压相同，不同像素列的G子像素的数据信号电压相同，不同像素列的B子像素的数据信号电压相同，因此基于本公开的显示面板结构能够减少黑色区域内数据信号Da的跳变次数，从而可以进一步降低智能穿戴产品的AOD功耗。又例如，在上述的智能穿戴设备或终端产品中，一些APP背景(如备忘录背景及微信聊天背景等)接近纯白色画面，大部分R子像素Source电压一致，大部分G子像素Source电压一致，大部分B子像素Source电压一致，基 于本公开显示面板的智能穿戴产品或终端产品能够减少数据信号的跳变次数，从而不仅能降低功耗，还减少了数据信号Da跳变过程中Tr和Tf的影响，能够改善显示画质。
如图4所示，在示例性实施例中，源极驱动电路S-IC(Source Driver Integrated Circuit，S-IC)设置在显示面板的一侧，且源极驱动电路S-IC与多条数据线Data相连，以通过多条数据线Data向不同列的子像素输出数据信号Da。
如图4所示，在示例性实施例中，显示面板还可以包括时序控制器(TCON)，时序控制器可对每一帧图像数据进行处理，生成每一帧图像数据对应的数据信号Da和控制信号，控制信号中包含开关控制信号，用于对非显示区的开关单元进行通断控制。数据信号Da被传送到源极驱动电路S-IC，源极驱动电路S-IC将所接收的数据信号Da转换成数据电压，写入显示面板中相应的子像素。
如图4所示，在示例性实施例中，时序控制器TCON可通过柔性电路板(Flexible PrintedCircuit，FPC)连接印刷电路板(X-Printed Circuit Board，X-PCB)，再通过印刷电路板X-PCB连接源极驱动电路S-IC。T-CON通过X-PCB向源极驱动电路S-IC输出其控制信号，T-CON可以控制源极驱动电路S-IC向数据线Data输入数据电压。
如图5所示，在示例性实施例中，开关电路M可以包括多个开关选择电路Mux，开关选择电路Mux中的每个开关为一个开关单元，开关选择电路Mux例如可以为1:6MUX开关、1:9MUX开关等。开关单元的控制端与源极驱动电路S-IC连接，以获取源极驱动电路S-IC输出的开关控制信号，开关单元的第一端连接接收源极驱动电路S-IC输出的数据信号Da，开关单元的第二端通过数据线Data连接对应的子像素，以向所连接的子像素输出对应的数据信号Da。通过使用开关选择电路Mux组成开关电路M，可以减少源极驱动电路S-IC与显示区AA之间的走线数量，节省空间。
如图5所示，在示例性实施例中，多个开关单元与多列子像素一一对应设置，即一个开关单元控制一列子像素的数据信号Da的传输。因 为G子像素和B子像素的数据信号电压相同或接近相同，因此，对于同一像素单元中的G子像素和B子像素，可以使用相邻的或不相邻的两个开关单元对其进行数据信号的传输控制。举例而言，可以如图5所示，第n列像素单元中的G子像素连接第3n个开关单元，第n列像素单元中的B子像素连接第(3n+2)个开关单元，n为大于等于1的奇数，即同一像素单元中的G子像素和B子像素分别通过数据线Data连接不相邻的两个开关单元。这样设置的好处在于，在开关单元依次排列后，除了需要连接相邻像素单元中的R子像素列的开关单元外，其他的开关单元可以按照排列顺序依次连接各列子像素的数据线Data，该布线方式可以降低时序信号的控制难度。
当然，在其他实施例中，也可以使用相邻的两个开关单元连接同一像素单元中的G子像素和B子像素的数据线Data。示例性的，图7为根据本公开另一种实施方式的图4中部分开关单元与像素列的连接示意图，如图7所示，将第(n+1)列像素单元中的G子像素的数据线Data连接第(3n+2)个开关单元，将第(n+1)列像素单元中的B子像素的数据线Data连接第(3n+3)个开关单元，将第n列像素单元的B子像素连接(3n+1)个开关单元，第n列像素单元的G子像素连接第3n个开关单元，从而实现在第(n+1)列像素单元中的G子像素和B子像素的数据线Data连接至相同的开关单元，n为大于等于1的奇数。对比图5可以看出，该连接方式可以进一步减少需要交叠的走线数量，从而简化布线难度。
应该理解的是，显示面板的非显示区通常还包括其他走线，因此需要综合非显示区的整体走线情况进行灵活布线，在满足第n列像素单元中的R子像素的数据线Data和第(n+1)列像素单元中的R子像素的数据线Data连接相邻的两个开关单元的情况下，以在整体上降低布线难度为原则进行灵活布线，n为大于等于1的奇数。
在示例性实施例中，可以以图5所示的像素单元与开关单元的连接结构作为一个重复单元或者可以以图6所示的连接结构作为一个重复单元进行重复。一个重复单元例如可以包括在行方向上相邻的第一像素单元和第二像素单元，第一像素单元和第二像素单元中子像素的排列方式 相同，且均可以包括R、G、B三种子像素，一个重复单元还可以包括在行方向上依次排列的六个所述开关单元。如图5、图6所示，在一个重复单元内，位于第一列的开关单元与第一像素单元中的R子像素的数据线连接，位于第二列的开关单元与第二像素单元中的R子像素的数据线连接，从而显示面板在整体上具有上文所述的开关单元与子像素列的连接关系，能够改善显示画质，降低源极驱动电路S-IC的整体功耗。
在示例性实施例中，开关单元可以通过晶体管来实现，例如薄膜晶体管TFT。换言之，本公开所述的开关电路M可以包括多个晶体管，晶体管的控制端接收源极驱动电路S-IC输出的开关控制信号，晶体管的第一端接收源极驱动电路S-IC输出的数据信号Da，晶体管的第二端通过数据线Data连接对应列的子像素。
在示例性实施例中，开关电路M可以包括多个第九晶体管T9和多个第十晶体管T10，第九晶体管T9和第十晶体管T10依次间隔排列；第m列子像素与第(m+1)列子像素为同一列像素单元中的不同子像素，对应于第m列子像素的第九晶体管T9连接第m列子像素的数据线Data，对应于第(m+1)列子像素的第十晶体管T10连接下一列像素单元中对应子像素的数据线Data，其中，m为大于等于1的正整数。其中，开关电路M中的多个晶体管与各列子像素一一对应，即一个第九晶体管T9连接一列子像素的数据线Data，一个第十晶体管T10连接下一列子像素的数据线Data，依次重复。第九晶体管T9和与其连接的数据线Data之间通过走线连接，该走线与其他晶体管连接数据线Data的走线之间没有交叠。第十晶体管T10和与其连接的数据线Data之间通过另一走线连接，该另一走线与连接其他接数据线Data的走线之间存在交叠。因此，第九晶体管T9与对应数据线Data的走线和第十晶体管T10与对应数据线Data的走线存在差异，下面结合附图对第九晶体管T9和第十晶体管T10的走线结构作进一步说明。
应该理解的是，本公开显示面板的非显示区和显示区AA可以共用膜层，即非显示区的有源层与显示区AA的有源层为同一膜层，非显示 区的第一导电层与显示区AA的第一导电层为同一膜层，非显示区的第二导电层与显示区AA的第二导电层为同一膜层，非显示区的第三导电层与显示区AA的第三导电层为同一膜层，并且，膜层之间可以具有相同的绝缘层。
图8为图4中沿虚线AA方向对应第十晶体管位置的剖视图，图9为图4中沿虚线BB方向对应第九晶体管位置的剖视图，如图8、图9所示，在示例性实施例中，有源层10可以包括多个第二有源部12和多个第五有源部15，第二有源部12可用于形成第九晶体管T9的沟道区，第五有源部15可用于形成第十晶体管T10的沟道区。有源层10还可以包括多个第一有源部11、多个第三有源部13、多个第四有源部14和多个第六有源部16，第一有源部11和第三有源部13与第二有源部12一一对应设置，并且，第一有源部11和第三有源部13分别连接于第二有源部12的两端，以分别形成第九晶体管T9的第一端和第二端。同样地，第四有源部14和第六有源部16与第五有源部15一一对应设置，并且第四有源部14和第六有源部16分别连接于第五有源部15的两端，以分别形成第十晶体管T10的第一端和第二端。第一有源部11可通过过孔连接第三导电层40的第一导电线41，由第一导电线41通过第一转接部31或直接通过过孔连接第一导电层20的第一连接线21，使得第九晶体管T9的第一端通过第一连接线21连接源极驱动电路S-IC。同样地，第四有源部14可通过过孔连接第三导电层40的第四导电线44，由第四导电线44通过第二转接部32或直接通过过孔连接位于第一导电层20的第二连接线22，使得第十晶体管T10的第一端通过第二连接线22连接源极驱动电路S-IC。
如图8、图9所示，在示例性实施例中，第一导电层20可以为显示区AA的Gate1层，第一导电层20可以包括多条第一栅线G1和多条第二栅线G2，第一栅线G1和第二栅线G2在衬底基板10的正投影均可以沿第一方向延伸，第一栅线G1在衬底基板10的正投影可以覆盖第二有源部12在衬底基板10的正投影，第一栅线G1的部分结构形成第九晶体管T9的栅极，第一栅线G1可连接源极驱动电路S-IC以获取对应的开关控制信号。第二栅线G2在衬底基板10的正投影可以覆盖第五有源 部15在衬底基板10的正投影，第二栅线G2的部分结构形成第十晶体管T10的栅极，第二栅线G2同样连接源极驱动电路S-IC，以获取源极驱动电路S-IC输出的开关控制信号。
第一导电层20还可以包括多条第一连接线21，第一连接线21在衬底基板10的正投影可以沿第二方向延伸，第一连接线21的一端可以连接源极驱动电路S-IC以获取源极驱动电路S-IC输出的数据信号Da，第一连接线21的另一端可通过过孔连接位于第三导电层40的第二导电线42，由第二导电线42和与其连接的第一转接部31、第一导电线41连接第一有源部11，从而将第九晶体管T9的第一端连接至源极驱动电路S-IC。类似地，第一导电层20还可以包括多条第二连接线22，第二连接线22在衬底基板10的正投影可以沿第二方向延伸，第二连接线22的一端可连接源极驱动电路S-IC，另一端可通过过孔连接位于第三导电层40的第三导电线43，由第三导电线43和与其连接的第二转接部32、第四导电线44连接第四有源部，将第十晶体管T10的第一端连接源极驱动电路S-IC。
如图8、图9所示，在示例性实施例中，第一导电层20还可以包括转接线23，转接线23可以与第六有源部16一一对应设置，转接线23在衬底基板10的正投影可以沿第一方向延伸，转接线23的一端可通过过孔连接第三导电层40的第六导电线46，另一端可通过过孔连接第三导电层40中相邻像素单元的数据线Data，以将第十晶体管T10的第二端连接至相邻像素单元中相应子像素的数据线Data。即通过在第一导电层20设置转接线23，可以将第十晶体管T10的第二端与相邻像素单元中对应子像素的数据线Data进行连接，从而可以避让与其他子像素的数据线Data相连接的第三导电层40的其他走线。并且，通过在第一导电层20设置转接线23，使得转接线23与第三导电层40的数据线Data之间间隔较远，间隔更多的绝缘层进行电气隔离，可以减小转接线23与数据线Data之间的寄生电容，减小对数据线Data的信号影响，保证显示效果。当然，在其他实施例中，转接线23也可以位于第二导电层30，本公开不限于此。
如图8、图9所示，在示例性实施例中，第二导电层30可以为显示 区AA的Gate2层，第二导电层30可以包括第一转接部31和第二转接部32，第一转接部31与第一导电层20的第一连接线21对应设置，即一个第一转接部31对应连接一条第一连接线21。第一转接部31在衬底基板10的正投影可以位于第一连接线21在衬底基板10的正投影和第一有源部11在衬底基板10的正投影之间，并且，第一转接部31可分别通过过孔连接第三导电层40的第一导电线41和第二导电线42，从而通过该第一转接部31将第一导电线41和第二导电线42进行电连接。同样地，第二转接部32可以与第二连接线22对应设置，即一条第二连接线22对应连接一个第二转接部32，第二转接部32在衬底基板10的正投影可以位于第二连接线22在衬底基板10的正投影和第四有源部14在衬底基板10的正投影之间，并且第二转接部32可分别通过过孔连接第三导电层40的第三导电线43和第四导电线44，从而通过该第二转接部32将第三导电线43和第四导电线44进行电连接。应该理解的是，在其他实施例中，第一转接部31和第二转接部32也可以位于其他导电层，例如可以位于第一导电层20等，即第一导电线41和第二导电线42还可以在第一导电层20进行转接以及第三导电线43和第四导电线44还可以在第一导电层20进行转接，具体取决于该位置是否存在其他走线，本公开不限于此。
如图8、图9所示，第三导电层40可以为显示区AA的SD层，第三导电层40可以包括多条数据线Data，一条数据线Data连接一列子像素，以向该列子像素提供数据信号Da。第三导电层40还可以包括第一导电线41和第二导电线42，第一导电线41可通过过孔分别连接第一有源部11和第一转接部31的一端，第二导电线42可分别通过过孔连接第一转接部31的另一端以及通过过孔连接第一导电层20的第一连接线21，从而将第九晶体管T9的第一端连接至第一连接线21进而连接源极驱动电路S-IC，以获取源极驱动电路S-IC输出的数据信号Da。
第三导电层40还可以包括第三导电线43和第四导电线44，第四导电线44可分别通过过孔连接第四有源部14和第二转接部32的一端，第三导电线43可分别通过过孔连接第二转接部32的另一端和第二连接线22，从而通过第三导电线43和第四导电线44将第十晶体管T10的第一 端连接至第二连接线22进而连接源极驱动电路S-IC，以获取源极驱动电路S-IC输出的数据信号Da。
第三导电层40还可以包括第六导电线46，第六导电线46与第六有源部16一一对应设置，即一个第六有源部16连接一条第六导电线46，第六导电线46可分别通过过孔第六有源部16和转接线23的一端，转接线23的另一端延伸至对应的数据线Data处，并通过过孔连接对应位置的数据线Data，实现通过第六导电线46和转接线23将第十晶体管T10的第二端连接相邻像素单元中子像素的数据线Data。
图10为根据本公开一种实施方式的转接线与数据线的正投影交叠示意图，如图10所示，在示例性实施例中，转接线23在衬底基板10的正投影和与其连接的第六导电线46在衬底基板10的正投影的夹角α大于等于60°且小于等于120°，例如可以为60°，70°，80°，90°，100°，110°，120°等。转接线23在衬底基板10的正投影与数据线Data在衬底基板10的正投影相交形成的夹角β大于等于60°且小于等于120°，例如可以为60°，70°，80°，90°，100°，110°，120°等。通过将转接线23在衬底基板10的正投影和数据线Data在衬底基板10的正投影之间的夹角设置为上述角度范围内，可以减小二者的交叠面积，从而有利于进一步减小转接线23和数据线Data之间所产生的寄生电容，降低对数据线Data上的数据信号Da的影响。并且可以理解的是，夹角α和夹角β可以相同或不同。在本公开的一优选实施例中，可以将上述夹角α和夹角β均设置为90°，即转接线23在衬底基板10的正投影与数据现在衬底基板10的正投影以及与第六导电线46在衬底基板10的正投影均垂直相交，可以使得交叠面积最小，相应地，能够最小化转接线23与数据线Data间的寄生电容。
本公开还提供一种显示面板的制备方法，该制备方法可用于形成具有图8所示结构的显示面板。如图11～20b所示，为根据本公开一种实施方式中显示面板制备方法的工艺流程图，所述制备方法可以包括：
S10、提供一衬底基板10，衬底基板10包括显示区AA和至少部分围绕显示区AA的非显示区。如图11所示，衬底基板10可以是透明玻 璃、或石英玻璃等，在显示面板为柔性显示面板时，衬底基板10还可以为聚酰亚胺(Polyimide，简称PI)等有机材料制作的柔性衬底。
在一些实施例中，还可以利用等离子体增强化学的气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)工艺沉积缓冲材料，形成覆盖衬底基板10的缓冲层。缓冲材料例如可以为氮化硅、氧化硅或氮氧化硅中的至少一种，其中，缓冲层可以是单层结构，也可以是多层结构。在缓冲层为多层结构的情况下，不同层的缓冲材料可以相同，也可以不同。
S20、在衬底基板10一侧的非显示区形成有源层10。如图12a所示，可以利用溅射工艺(Sputter)在衬底基板10上沉积半导体材料形成有源层10。半导体材料例如可以为多晶硅材料，相应地，所形成的第九晶体管T9和第十晶体管T10可以为P型低温多晶硅薄膜晶体管。
在示例性实施例中，可对有源层10进行曝光、显影和刻蚀后制作得到多个第五有源部15、多个第六有源部16和多个第四有源部14，其中，第五有源部15用于形成第十晶体管T10的沟道区，第四有源部14和第五有源部15分别连接于第四有源部14的两侧，形成第十晶体管T10的第一端和第二端。
在示例性实施例中，如图12b所示，有源层10还可以包括多个第一有源部11、多个第二有源部12和多个第三有源部13，第二有源部12用于形成第九晶体管T9的沟道区，第一有源部11和第三有源部13分别位于第二有源部12的两侧，用于形成第九晶体管T9的第一端和第二端。
在示例性实施例中，如图13a、图13b所示，在形成有源层10后，可以利用PECVD工艺沉积第一无机材料形成第一栅极绝缘层GI1，第一无机材料例如可以为SiO2。
S30、在有源层10背离衬底基板10的一侧形成第一导电层20。
在示例性实施例中，如图14a所示，第一导电材料例如可以为Mo。可以利用Sputter设备沉积覆盖第一栅极绝缘层GI1的第一导电层20，并对第一导电层20进行刻蚀工艺，得到多条第二栅线G2和多条转接线23。其中，第二栅线G2在衬底基板10的正投影可以沿第一方向延伸并且可以覆盖第五有源部15在衬底基板10的正投影，第二栅线G2的部 分结构用于形成第十晶体管T10的栅极；转接线23在衬底基板10的正投影可以沿第一方向延伸，转接线23可分别通过过孔连接第六导电线46和相邻像素单元中的对应数据线Data，以通过该转接线23的在第一导电层20进行转接而将第十晶体管T10的第二端与相邻像素单元中对应子像素的数据线Data进行连接。
在示例性实施例中，如图14a所示，还可以在第一导电层20上刻蚀形成多条第二连接线22，第二连接线22在衬底基板1的正投影可以沿第二方向延伸，第二连接线22和转接线23位于第二栅线G2的两侧，从而通过该第二连接线22将第十晶体管T10的第一端连接源极驱动电路S-IC。
在示例性实施例中，如图14b所示，还可以在第一导电层20上刻蚀形成多条第一栅线G1和多条第一连接线21，第一栅线G1在衬底基板1的正投影可以沿第一方向延伸并且可以覆盖第二有源部12在衬底基板1的正投影，第一栅线G1的部分结构用于形成第九晶体管T9的栅极。第一连接线21在衬底基板1的正投影可以沿第二方向延伸，第一连接线21连接源极驱动电路S-IC，通过该第一连接线21将第九晶体管T9的第一端连接至源极驱动电路S-IC。
在示例性实施例中，如图15a、图15b所示，在形成第一导电层20之后，还可以在利用PECVD工艺沉积第二无机材料形成第二栅极绝缘层GI2。第二无机材料例如可以为SiNx。
在示例性实施例中，如图16a、图16b所示，还可以利用Sputter设备沉积覆盖第二栅极绝缘层GI2的第二导电层30，第二导电层30的材料例如可以为Mo。然后可以利用刻蚀工艺将第二导电层30形成多个第二转接部32和多个第一转接部31，其中，第二转接部32在衬底基板1的正投影可以位于第四有源部14在衬底基板1的正投影和第二连接线22在衬底基板1的正投影之间，第二转接部32可分别通过过孔连接与其对应的第三导电线43和第四导电线44。第一转接部31在衬底基板1的正投影可以位于第一有源部11在衬底基板1的正投影和第一连接线21在衬底基板1的正投影之间，第一转接部31可分别通过过孔连接第一导电线41和第二导电线42。
在示例性实施例中，如图17a、图17b所示，在形成第二导电层30之后，还可以利用PECVD工艺沉积第一无机材料或第二无机材料形成层间介电层ILD，然后如图18a、如图18b所示，可以利用干刻工艺在层间介电层上形成多个过孔。
S40、利用沉积工艺在第一导电层20背离衬底基板1的一侧沉积第二导电材料形成第三导电层40。如图19a所示，可以利用Sputter设备沉积第二导电材料，形成第三导电层40，然后利用刻蚀工艺将第三导电层40形成多条数据线Data和多条第六导电线46，数据线Data在衬底基板1的正投影可以沿第二方向延伸，一条数据线Data连接一列子像素。第六导电线46与第六有源部16对应设置，第六导电线46在衬底基板1的正投影可以沿第二方向延伸，第六导电线46通过过孔连接第六有源部16。
在示例性实施例中，如图19a所示，还可以利用刻蚀工艺在第三导电层40形成多条第四导电线44和多条第三导电线43，第四导电线44通过过孔连接第四有源部14和第二转接部32，第三导电线43通过过孔连接第二转接部32和第二连接线22，以通过第三导电线43、第二转接部32、第四导电线44和第二连接线22将第十晶体管T10的第一端连接源极驱动电路S-IC。
在示例性实施例中，如图19b所示，还可以利用刻蚀工艺在第三导电层40上形成多条第一导电线41和多条第二导电线42，第一导电线41第一导电线41通过过孔连接第一有源部11和第一转接部31，第二导电线42通过过孔连接第一转接部31和第一连接线21，从而通过该第一导电线41、第一转接部31、第二导电线42和第一连接线21将第九晶体管T9的第一端连接至源极驱动电路S-IC。
在示例性实施例中，如图20a、图20b所示，在形成第三导电层40后，还可以利用旋涂工艺(Coating)、固化工艺(Curing)形成平坦化层。
本公开还提供一种显示装置，包括上述任意实施例所述的显示面板。该显示装置可以为手机、平板电脑、智能手表等显示装置。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想 到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (20)

  1. 一种显示面板，其中，包括：
    显示区，所述显示区包括沿行列方向阵列分布的多个像素单元，所述像素单元至少包括第一子像素和第二子像素，且所述第一子像素的最大灰阶值电压小于所述第二子像素的最大灰阶值电压；
    源极驱动电路，位于所述显示区的一侧，所述源极驱动电路用于输出数据信号和开关控制信号；
    开关电路，位于所述显示区的一侧，所述开关电路包括多个开关单元，所述开关单元的控制端用于接收所述开关控制信号，第一端用于接收所述数据信号，第二端连接数据线；
    其中，任意第n列像素单元中的第一子像素和第(n+1)列像素单元中的第一子像素分别通过所述数据线与相邻的两个开关单元连接，n为大于等于1的奇数。
  2. 根据权利要求1所述的显示面板，其中，所述像素单元还包括第三子像素，在同一像素单元中的所述第二子像素和所述第三子像素分别通过所述数据线与相邻的两个开关单元或间隔的两个开关单元连接。
  3. 根据权利要求1所述的显示面板，其中，所述多个开关单元与多列子像素一一对应设置。
  4. 根据权利要求3所述的显示面板，其中，所述显示面板包括沿行方向分布的多个重复单元，所述重复单元包括在行方向上相邻的第一像素单元和第二像素单元以及在行方向上依次排列的六个所述开关单元；
    在所述重复单元内，位于第一列的所述开关单元与所述第一像素单元中的第一子像素的数据线连接，位于第二列的所述开关单元与所述第二像素单元中的第一子像素的数据线连接。
  5. 根据权利要求1-4任一项所述的显示面板，其中，所述第一子像素为R子像素。
  6. 根据权利要求4所述的显示面板，其中，所述开关单元为晶体管。
  7. 根据权利要求6所述的显示面板，其中，所述开关电路包括多个第九晶体管和多个第十晶体管，所述第九晶体管和所述第十晶体管依次间隔排列；
    第m列子像素与第(m+1)列子像素为同一列像素单元中的不同子像素，对应于第m列子像素的第九晶体管连接第m列子像素的数据线，对应于第(m+1)列子像素的第十晶体管连接下一列像素单元中对应子像素的数据线，其中，m为大于等于1的正整数。
  8. 根据权利要求7所述的显示面板，其中，所述第十晶体管通过转接线连接下一列像素单元中对应子像素的数据线，且所述转接线与所述数据线位于不同导电层。
  9. 根据权利要求8所述的显示面板，其中，所述显示面板还包括：
    衬底基板，所述衬底基板包括所述显示区；
    有源层，位于所述衬底基板的一侧，所述有源层包括：
    多个第五有源部，所述第五有源部用于形成所述第十晶体管的沟道区；
    多个第六有源部，所述第六有源部连接于所述第五有源部的一侧；
    第一导电层，位于所述有源层背离所述衬底基板的一侧，所述第一导电层包括：
    多条第二栅线，所述第二栅线在所述衬底基板的正投影覆盖所述第五有源部在所述衬底基板的正投影，所述第二栅线的部分结构用于形成所述第十晶体管的栅极；
    第三导电层，位于所述第一导电层背离所述衬底基板的一侧，所述第三导电层包括：
    多条数据线，一条所述数据线连接一列子像素；
    多条第六导电线，与所述第六有源部对应设置，所述第六导电线通过过孔连接所述第六有源部；
    其中，所述转接线分别通过过孔连接所述第六导电线和相邻像素单元中的对应数据线。
  10. 根据权利要求9所述的显示面板，其中，所述转接线位于所述第一导电层。
  11. 根据权利要求9所述的显示面板，其中，所述转接线在所述衬底基板的正投影和与其连接的所述第六导电线在所述衬底基板的正投影的夹角大于等于60°且小于等于120°；
    所述转接线在所述衬底基板的正投影与所述数据线在所述衬底基板的正投影相交形成的夹角大于等于60°且小于等于120°。
  12. 根据权利要求9所述的显示面板，其中，
    所述有源层还包括：
    第四有源部，连接于所述第五有源部远离所述第六有源部的一侧；
    所述第一导电层还包括：
    多条第二连接线，所述第二连接线连接所述源极驱动电路；
    所述第三导电层还包括：
    多条第四导电线，与所述第四有源部对应设置，所述第四导电线通过过孔连接与其对应的所述第四有源部；
    多条第三导电线，与所述第二连接线对应设置，所述第三导电线通过过孔连接与其对应的所述第二连接线；
    所述显示面板还包括：
    第二导电层，位于所述第一导电层和所述第三导电层之间，所述第二导电层包括：
    多个第二转接部，与所述第五有源部对应设置，所述第二转接部在所述衬底基板的正投影位于所述第四有源部在所述衬底基板的正投影和所述第二连接线在所述衬底基板的正投影之间，所述第二转接部分别通过过孔连接与其对应的所述第三导电线和所述第四导电线。
  13. 根据权利要求9所述的显示面板，其中，
    所述有源层还包括：
    多个第二有源部，在所述衬底基板的正投影位于所述非显示区，所述第二有源部用于形成所述第九晶体管的沟道区；
    多个第一有源部，与所述第二有源部对应设置，所述第一有源部连接于所述第二有源部的一侧；
    多个第三有源部，与所述第二有源部对应设置，所述第三有源部连接于所述第二有源部远离所述第一有源部的一侧，所述第二有源部通过过孔连接与其对应的数据线；
    所述第一导电层还包括：
    多条第一栅线，所述第一栅线在所述衬底基板的正投影覆盖所述第 二有源部在所述衬底基板的正投影，所述第一栅线的部分结构用于形成所述第九晶体管的栅极；
    多条第一连接线，所述第一连接线连接所述源极驱动电路；
    所述第二导电层还包括：
    多个第一转接部，与所述第二有源部对应设置，所述第一转接部在所述衬底基板的正投影位于所述第一有源部在所述衬底基板的正投影和所述第一连接线在所述衬底基板的正投影之间；
    所述第三导电层还包括：
    多条第一导电线，所述第一导电线通过过孔连接与其对应的所述第一有源部和所述第一转接部；
    多条第二导电线，所述第二导电线通过过孔连接与其对应的所述第一连接线和所述第一转接部。
  14. 根据权利要求1所述的显示面板，其中，所述开关电路包括多个开关选择电路，所述开关选择电路包括多个所述开关单元。
  15. 一种显示面板的制备方法，其中，用于制备权利要求10所述的显示面板，所述方法包括：
    提供一衬底基板，所述衬底基板包括显示区和至少部分围绕所述显示区的非显示区；
    利用沉积工艺在所述衬底基板一侧的非显示区形成有源层，其中，所述有源层包括第五有源部和连接于所述第五有源部一侧的第六有有源部，所述第五有源部用于形成所述第十晶体管的沟道区；
    利用沉积工艺在所述有源层背离所述衬底基板的一侧形成第一导电层，其中，所述第一导电层包括多条第二栅线和多条转接线，所述第二栅线在所述衬底基板的正投影覆盖所述第五有源部在所述衬底基板的正投影，所述第二栅线的部分结构用于形成所述第十晶体管的栅极；所述转接线分别通过过孔连接所述第六导电线和相邻像素单元中的对应数据线；
    利用沉积工艺在第一导电层背离所述衬底基板的一侧形成第三导电层，其中，所述第三导电层包括多条数据线和多条第六导电线，一条所述数据线连接一列子像素，所述第六导电线与所述第六有源部对应设置， 所述第六导电线通过过孔连接所述第六有源部。
  16. 根据权利要求15所述的方法，其中，在所述利用沉积工艺在所述有源层背离所述衬底基板的一侧形成第一导电层之前，所述方法还包括：
    利用沉积工艺在所述衬底基板和所述有源层上沉积第一无机材料形成第一栅绝缘层；
    所述利用沉积工艺在所述有源层背离所述衬底基板的一侧形成第一导电层，包括：
    利用沉积工艺在所述第一栅绝缘层上沉积所述第一导电材料形成所述第一导电层。
  17. 根据权利要求15所述的方法，其中，在所述利用沉积工艺在所述有源层背离所述衬底基板的一侧形成第一导电层之后，所述方法还包括：
    利用沉积工艺在所述第一导电层上沉积第二无机材料形成第二栅绝缘层；
    利用沉积工艺在所述第二栅绝缘层上沉积第一导电材料形成第二导电层；
    利用构图工艺在所述第二导电层形成多个第二转接部，其中，所述第二转接部与所述第五有源部对应设置，所述第二转接部在所述衬底基板的正投影位于所述第四有源部在所述衬底基板的正投影和所述第二连接线在所述衬底基板的正投影之间，所述第二转接部分别通过过孔连接与其对应的所述第三导电线和所述第四导电线；
    利用沉积工艺在所述第二导电层上沉积第一无机材料或第二无机材料形成层间介电层；
    利用刻蚀工艺在所述层间介电层上形成多个过孔。
  18. 根据权利要求17所述的方法，其中，所述利用沉积工艺在第一导电层背离所述衬底基板的一侧形成第三导电层，包括：
    利用沉积工艺在所述层间介电层上沉积第二导电材料形成第三导电层；
    利用刻蚀工艺在所述第三导电层上形成多条所述数据线和多条所述 第六导电线。
  19. 根据权利要求18所述的方法，其中，在形成所述第三导电层之后，所述方法还包括：
    平坦化所述第三导电层。
  20. 一种显示装置，其中，包括权利要求1-14任一项所述的显示面板。
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