WO2023245444A9 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023245444A9
WO2023245444A9 PCT/CN2022/100229 CN2022100229W WO2023245444A9 WO 2023245444 A9 WO2023245444 A9 WO 2023245444A9 CN 2022100229 W CN2022100229 W CN 2022100229W WO 2023245444 A9 WO2023245444 A9 WO 2023245444A9
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WO
WIPO (PCT)
Prior art keywords
base substrate
orthographic projection
transistor
row
conductive layer
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PCT/CN2022/100229
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English (en)
French (fr)
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WO2023245444A1 (zh
Inventor
张跳梅
于子阳
陈文波
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280001833.2A priority Critical patent/CN116097442B/zh
Priority to CN202311190523.2A priority patent/CN117276286A/zh
Priority to PCT/CN2022/100229 priority patent/WO2023245444A1/zh
Publication of WO2023245444A1 publication Critical patent/WO2023245444A1/zh
Publication of WO2023245444A9 publication Critical patent/WO2023245444A9/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technology, and specifically, to a display panel and a display device.
  • the inorganic dielectric layer between the SD1 layer and the Gate layer has the risk of breaking, which can easily cause the SD1 layer and the Gate layer to be short-circuited, causing display problems.
  • the purpose of the present disclosure is to overcome the above-mentioned shortcomings of the prior art and provide a display panel and a display device.
  • a display panel includes a pixel driving circuit.
  • the pixel driving circuit includes a driving transistor and a second transistor.
  • a first electrode of the second transistor is connected to a first electrode of the driving transistor.
  • the gate electrode, the second electrode is connected to the first electrode of the driving transistor;
  • the display panel also includes: a base substrate; a first conductive layer located on one side of the base substrate, the first conductive layer includes: a first conductive part, the first conductive part is used to form the gate of the driving transistor; a second active layer is located on the side of the first conductive layer away from the base substrate, the second active layer
  • the active layer includes: a second active part used to form a channel region of the second transistor; an eighth active part connected to one side of the second active part; a third conductive layer located on the A side of the second active layer facing away from the base substrate.
  • the third conductive layer includes: a first gate line extending along the first direction in the orthographic projection of the base substrate and covering the second active layer. part, the partial structure of the first gate line is used to form the top gate of the second transistor, the eighth active part is in the orthographic projection of the substrate and the first conductive part is in the substrate
  • the orthographic projection of the base substrate is respectively located on both sides of the first gate line on the orthographic projection of the base substrate; a dielectric layer is located on the side of the third conductive layer facing away from the base substrate; a fourth conductive layer layer, located on the side of the dielectric layer away from the base substrate, the fourth conductive layer includes: a first bridge portion, respectively connected to the eighth active portion and the first conductive portion through via holes ;
  • the first gate line includes a sixth side and a seventh side that are oppositely arranged and have the same extension direction, and at least part of the structure of the sixth side is connected to the first bridge in the orthographic projection of the substrate.
  • the sixth side includes a first segment
  • the seventh side includes a second segment
  • the first segment is located in front of the base substrate.
  • the projection is perpendicular to the orthographic projection of the first bridge portion on the base substrate, and the orthographic projection of the second segment on the base substrate is the same as the orthographic projection of the first bridge portion on the base substrate.
  • Vertical; the orthographic projection of the first segment on the substrate is parallel to the orthographic projection of the second segment on the substrate, or the first segment is on the substrate.
  • the straight line of the orthographic projection intersects the straight line of the orthographic projection of the second segment on the base substrate.
  • the length at which the orthographic projection of the sixth side on the base substrate intersects with the orthographic projection of the first bridge portion on the base substrate is S1, so The length of the orthographic projection of the first segment on the substrate is S2, and S2/S1 is greater than or equal to 0.7 and less than or equal to 1; the orthographic projection of the seventh side on the substrate is equal to the length of the orthographic projection of the substrate.
  • the intersection length of the first bridge portion in the orthographic projection of the base substrate is S3, the length of the second segment in the orthographic projection of the base substrate is S4, and S4/S3 is greater than or equal to 0.7 and less than or equal to 1.
  • the display panel further includes: a second conductive layer located between the first conductive layer and the second active layer, the second conductive layer includes: The second gate line extends along the first direction in the orthographic projection of the base substrate and covers the orthographic projection of the second active portion in the base substrate. Part of the structure of the second gate line is In forming the bottom gate of the second transistor; wherein the second gate line includes a third side and a fourth side that are oppositely arranged and extend along its extension direction, and the first bridge portion is on the substrate The orthographic projection of the substrate perpendicularly intersects the orthographic projection of at least part of the third side on the base substrate and the orthographic projection of at least part of the fourth side on the base substrate.
  • the second gate line includes a second extension portion, and the second extension portion is located at the first bridge portion at the orthogonal projection of the substrate substrate.
  • the second extension portion On the orthographic projection of the base substrate and overlapping with the first extension portion on the orthographic projection of the base substrate, the second extension portion includes a third side and a fourth side that are oppositely arranged and have the same extension direction. ; The orthographic projection of the third side on the base substrate is located at a position where the orthographic projection of the fourth side on the base substrate is far away from the orthographic projection of the first conductive portion on the base substrate.
  • the first side in the orthographic projection of the base substrate is located in the orthographic projection of the second side in the base substrate and away from the first conductive portion in the orthographic projection of the base substrate
  • the distance in the second direction between the orthographic projection of any first node on the third side on the base substrate and the orthographic projection of the first side on the base substrate is L1
  • the distance in the second direction between the orthographic projection of the first node on the substrate and the fourth side on the substrate is L2
  • the distance between the second direction and the first The directions intersect L1/L2 is greater than or equal to 0.25 and less than or equal to 0.8
  • the orthographic projection of any second node on the fourth side on the base substrate and the orthogonal projection of the second side on the base substrate The distance projected in the second direction is L3, and the distance in the second direction between the orthographic projection of the second node on the base substrate and the orthographic projection of the third side on the base substrate is L4.
  • L3/L4 is greater than or equal to 0.25 and less than or equal to 0.8.
  • the orthographic projection of the first extension portion on the base substrate covers the orthographic projection of the third side on the base substrate, and the second extension portion The orthographic projection of the base substrate covers the second side on the orthographic projection of the base substrate; or, the first extension portion covers the third side on the orthographic projection of the base substrate.
  • the second extension portion covers the first side in the orthographic projection of the base substrate In the orthographic projection of the base substrate and the second side in the orthographic projection of the base substrate; or, the first extension portion covers the fourth side in the orthographic projection of the base substrate In an orthographic projection of the base substrate, the second extension portion covers an orthographic projection of the first side in the orthographic projection of the base substrate.
  • an overlapping area of the orthographic projection of the first extension portion on the base substrate and the orthographic projection of the second extension portion on the base substrate is in the The size in the second direction is L5, L1/L5 is greater than or equal to 0.6 and less than or equal to 1, and L3/L5 is greater than or equal to 0.6 and less than or equal to 1.
  • the pixel driving circuit includes a fifth transistor and a sixth transistor.
  • the first electrode of the fifth transistor is connected to the second electrode of the driving transistor.
  • the sixth transistor The first electrode is connected to the first electrode of the driving transistor;
  • the display panel also includes: a first active layer located between the base substrate and the first conductive layer, the first active layer It includes: a fifth active part used to form a channel region of the fifth transistor; a sixth active part used to form a channel region of the sixth transistor; wherein the fifth active part and The sixth active part has a sixth distance L6 in the first direction, L1/L6 is greater than or equal to 5%, and L2/L6 is greater than or equal to 5%.
  • L1 is 1.3 ⁇ m or more
  • L2 is 1.3 ⁇ m or more
  • the second gate line includes a second extension portion, and the second extension portion is located at the first bridge portion at the orthogonal projection of the substrate substrate.
  • the orthographic projection of the base substrate overlaps with the first extension portion in the orthographic projection of the base substrate; the second extension portion covers the first extension portion in the orthographic projection of the base substrate.
  • the orthographic projection of the base substrate, and the second extension portion has a first centerline in the first direction in the orthographic projection of the base substrate, and the first extension portion has a orthographic projection of the base substrate.
  • the second extension portion has a first width in the second direction in the orthographic projection of the base substrate, the first extension portion
  • the orthographic projection of the base substrate has a second width in a second direction, and the second direction intersects the first direction; wherein, at the same position, the ratio of the first width to the second width It is 1.5 ⁇ 3.
  • the first gate line has a first component and a second component connected along its extension direction, and the first component is located directly in front of the substrate.
  • the width projected in the second direction is greater than the width of the orthogonal projection of the first component on the substrate in the second direction, and the second direction intersects the first direction;
  • the second grid The line has a third component and a fourth component connected along its extension direction, and the width of the third component in the orthographic projection of the substrate in the second direction is greater than the width of the fourth component in the second direction.
  • the first gate line has a first component and a second component, and the width of the first component in the second direction is greater than the width of the first component in the second direction.
  • the width of the second direction intersects with the first direction;
  • the second gate line has a third component and a fourth component, and the third component is in the second direction.
  • the width is greater than the width of the fourth component in the second direction; wherein, the orthographic projection of the first component on the base substrate and the orthographic projection of the third component on the base substrate Both cover the orthographic projection of the second active part on the base substrate, and the orthographic projection of the third component part on the base substrate covers the orthographic projection of the first component part on the base substrate. Projection; the orthographic projection of the first bridge portion on the base substrate intersects the orthographic projection of the first component on the base substrate and the orthographic projection of the third component on the base substrate.
  • the display panel includes a plurality of the pixel driving circuits distributed in an array along a first direction and a second direction, the first direction being a row direction, and the second direction is the column direction; the pixel driving circuit is used to drive the light-emitting unit to emit light.
  • the pixel driving circuit also includes a pair of fourth transistors and a seventh transistor. The first pole of the fourth transistor is connected to the second pole of the driving transistor.
  • the gate electrode is connected to the third gate line, the second electrode is connected to the data line;
  • the first electrode of the seventh transistor is connected to the first electrode of the light-emitting unit, the second electrode is connected to the second initial signal line, and the gate electrode is connected to the third Reset signal line;
  • the display panel further includes: a first active layer located between the base substrate and the first conductive layer;
  • the first active layer includes: a fourth active portion for forming a channel region of the fourth transistor; a seventh active portion used to form a channel region of the seventh transistor;
  • the first conductive layer further includes: the third gate line, on the liner
  • the orthographic projection of the base substrate extends along the first direction and covers the orthographic projection of the fourth active part on the base substrate, and part of the structure of the third gate line is used to form the gate of the fourth transistor.
  • the third reset signal line extends along the first direction in the orthographic projection of the base substrate and covers the seventh active portion, and part of the structure of the third reset signal line is used to form the The gate of the seventh transistor; wherein, the third gate line of the pixel driving circuit of this row is multiplexed as the third reset signal line of the pixel driving circuit of the previous row.
  • the pixel driving circuit further includes a storage capacitor, a first electrode of the storage capacitor is connected to the gate of the driving transistor, and a second electrode is connected to the first power line;
  • the first conductive part is also used to form a first electrode of the storage capacitor
  • the display panel also includes:
  • a fifth conductive layer is located on the side of the fourth conductive layer facing away from the base substrate.
  • the fifth conductive layer includes:
  • the first power line extends along the second direction in the orthographic projection of the base substrate, and the second direction intersects the first direction; a second conductive layer is located between the first conductive layer and Between the second active layers, the second conductive layer includes: a second conductive part, the orthographic projection of the second conductive part on the base substrate and the first conductive part on the substrate The orthographic projection portions of the substrate overlap, the second conductive portion is used to form a second electrode of the storage capacitor, and the second conductive portion is connected to the first power line through a via hole.
  • the first direction is a row direction
  • the second direction is a column direction
  • the display panel includes a plurality of repeating units distributed along the row and column directions, and the repeating units include For two adjacent pixel driving circuits in the row direction, each column of the pixel driving circuit is provided with one first power line and one second conductive portion; in the same repeating unit, two of the first power lines are The power lines are connected; in the adjacent repeating units in the row direction, the adjacent second conductive parts are connected.
  • two pixel driving circuits adjacent in the row direction are mirror images of each other.
  • the pixel driving circuit includes a fifth transistor, a first electrode of the fifth transistor is connected to a second electrode of the driving transistor, and the second electrode is connected to the first power supply. line;
  • the display panel further includes: a first active layer located between the base substrate and the first conductive layer;
  • the first active layer includes: a fifth active portion for forming the the channel region of the fifth transistor;
  • the first conductive layer further includes: an enable signal line extending along the first direction in the orthographic projection of the base substrate and covering the fifth active portion, Part of the structure of the enable signal line is used to form the gate of the fifth transistor;
  • a fifth conductive layer is located on a side of the fourth conductive layer facing away from the base substrate, and the fifth conductive layer includes:
  • the first power line extends in a second direction in an orthographic projection of the base substrate, and the second direction intersects the first direction;
  • the fourth conductive layer further includes: a second bridge portion, The second bridge portion is connected to the second electrode of the fifth transistor through a first via
  • the first direction is a row direction
  • the second direction is a column direction
  • the display panel includes a plurality of repeating units distributed along the row and column directions, and the repeating units include There are two adjacent pixel driving circuits in the row direction; the second bridge portions are arranged in one-to-one correspondence with the pixel driving circuits. In the adjacent repeating units in the row direction, the adjacent second bridge portions are opposite to each other. Connect and share the first via.
  • the display panel further includes: a fifth conductive layer located on a side of the fourth conductive layer facing away from the base substrate, the fifth conductive layer includes: A power line extending along a second direction in the orthographic projection of the base substrate, and the second direction intersects the first direction; wherein the first power line covers the orthographic projection of the base substrate
  • the first bridge portion is an orthographic projection of the base substrate.
  • the gate electrode of the second transistor is connected to the first gate line, and the second electrode of the second transistor is connected to the first electrode of the driving transistor; the second electrode has The source layer further includes: a first active part used to form a channel region of the first transistor; a second active part used to form a channel region of the second transistor; the display panel further includes: A second conductive layer is located between the first conductive layer and the second active layer.
  • the second conductive layer includes: a second gate line, along the orthographic projection of the base substrate along the first The direction extends and covers the orthographic projection of the second active part on the base substrate, part of the structure of the second gate line is used to form the bottom gate of the second transistor, and the first gate line is The orthographic projection of the base substrate covers the orthographic projection of the second active part on the base substrate, and the partial structure of the first gate line is used to form the top gate of the second transistor; first reset A signal line extending along the first direction in an orthographic projection of the base substrate and covering an orthographic projection of the first active portion in the base substrate, and a partial structure of the first reset signal line is used for Forming a bottom gate of the first transistor; the front projection of the first power line on the base substrate covers the front projection of the first active part on the base substrate and the second active part Orthographic projection of the base substrate.
  • the second electrode of the first transistor is connected to the first initial signal line, and the second electrode of the second transistor is connected to the first electrode of the driving transistor;
  • the pixel The driving circuit also includes a sixth transistor, the first electrode of the sixth transistor is connected to the first electrode of the driving transistor;
  • the display panel also includes: a second conductive layer located between the first conductive layer and the third conductive layer.
  • the second conductive layer includes: the first initial signal line extending along the first direction in the orthographic projection of the substrate; a first active layer located on the substrate Between the base substrate and the first conductive layer, the first active layer includes: a third active part for forming a channel region of the driving transistor; a sixth active part for forming the The channel region of the sixth transistor; an eleventh active part connected between the third active part and the sixth active part; the second active layer further includes: a second active part , used to form the channel region of the second transistor; the ninth active part is connected between the second active part and the eighth active part; the fourteenth active part is connected to the The side of the second active part away from the eighth active part; the fourth conductive layer further includes: a third bridge part connected to the fourteenth active part and connected to the first through a via hole The initial signal line; the fourth bridge part is connected to the eleventh active part through a via hole and connected to the fourteenth active part through another via hole.
  • the display panel includes a plurality of the pixel driving circuits distributed in an array along a first direction and a second direction, the first direction being a row direction, and the second direction is the column direction;
  • the display panel includes a plurality of repeating units distributed along the row and column directions, and the repeating units include two of the pixel driving circuits;
  • the two pixel driving circuits share the third bridge portion.
  • the pixel driving circuit further includes a fifth transistor, a sixth transistor, and a seventh transistor, and a first electrode of the fifth transistor is connected to a second electrode of the driving transistor.
  • the second pole of the fifth transistor is connected to the first power line
  • the first pole of the sixth transistor is connected to the first pole of the driving transistor
  • the second pole of the sixth transistor is connected to the seventh the first electrode of the transistor
  • the display panel further includes: a first active layer located between the base substrate and the first conductive layer;
  • the first active layer includes: a fifth active portion, used to form the channel region of the fifth transistor; a sixth active part used to form the channel region of the sixth transistor; a seventh active part used to form the channel region of the seventh transistor ;
  • the first conductive layer further includes: an enable signal line extending along the first direction in the orthographic projection of the base substrate and covering the fifth active part and the sixth active part, so Part of the structure of the enable signal line is used to form the gate of the fifth transistor, and part of the structure is used
  • the first direction extends and covers the seventh active part, and part of the structure of the third reset signal line is used to form the gate of the seventh transistor; a second conductive layer is located on the first conductive layer Between the second active layer and the second active layer, the second conductive layer includes: the first initial signal line extending along the first direction in the orthographic projection of the base substrate; a fifth conductive layer located on The side of the fourth conductive layer facing away from the base substrate, the fifth conductive layer including: the first power line extending along the second direction in the orthographic projection of the base substrate, the The second direction intersects the first direction; the fourth conductive layer further includes: a second bridge portion, the second bridge portion is connected to the second electrode of the fifth transistor through a via hole, and is connected to the second electrode of the fifth transistor through another via hole.
  • the hole is connected to the first power line; wherein, in the same pixel driving circuit, the orthographic projection of the first conductive part on the base substrate is located between the orthographic projection of the enable signal line on the base substrate and the The first gate line is between the orthographic projection of the base substrate; in the same pixel driving circuit, the first gate line is between the orthographic projection of the base substrate, and the third reset signal line is between the orthographic projection of the substrate and the base substrate.
  • the orthographic projection of the base substrate and the first initial signal line are sequentially distributed in the direction away from the first conductive portion on the orthographic projection of the base substrate.
  • the gate of the first transistor is connected to a second reset signal line;
  • the second active layer further includes: a first active portion for forming the first the channel region of the transistor;
  • the display panel further includes: a second conductive layer located between the first conductive layer and the second active layer;
  • the second conductive layer includes: a first reset signal line,
  • the orthographic projection of the base substrate extends along the first direction and covers the orthographic projection of the first active portion on the base substrate, and a partial structure of the first reset signal line is used to form the The bottom gate of the first transistor;
  • the third conductive layer further includes: a second reset signal line extending along the first direction in the orthographic projection of the base substrate and covering the first active portion in the In the orthographic projection of the base substrate, part of the structure of the second reset signal line is used to form the top gate of the first transistor; wherein, the orthographic projection of the first reset signal line on the base substrate is located on the The first initial signal line is between the orthographic projection of the base substrate and the third reset signal line
  • the first direction is a row direction
  • the second direction is a column direction
  • the pixel driving circuit further includes a fourth transistor, and a first electrode of the fourth transistor Connect the second pole of the driving transistor, and the second pole is connected to the data signal line
  • the fifth conductive layer also includes: a data line extending along the second direction in the orthographic projection of the base substrate
  • the third The four conductive layers also include: a sixth bridge portion connected to the data line through a via hole and connected to the second electrode of the fourth transistor through another via hole
  • the display panel includes a plurality of repeating lines distributed along the row and column directions.
  • the repeating unit includes two of the pixel driving circuits, and each column of the pixel driving circuit is provided with one of the first power lines and one of the data lines; wherein, in the same repeating unit, two of the first power lines and one of the data lines are provided.
  • a power line is connected, and the two data lines are distributed on both sides of the front projection of the base substrate on the front projection of the two first power lines on the base substrate.
  • the pixel driving circuit further includes a fourth transistor, the first electrode of the fourth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the data signal line;
  • the first transistor and the second transistor are N-type transistors; the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are P-type transistors.
  • the display panel includes a plurality of the pixel driving circuits distributed in an array along a first direction and a second direction, the first direction being a row direction, and the second direction is the column direction; the display panel includes a plurality of sub-pixels distributed in an array along the row-column direction, and the sub-pixels include the pixel driving circuit; the display panel also includes: a fifth conductive layer located away from the fourth conductive layer On one side of the base substrate, the fifth conductive layer includes: a first power line extending along the second direction in the orthographic projection of the base substrate; a plurality of virtual pixel rows, the virtual pixel rows Located between two adjacent rows of sub-pixels, the virtual pixel row includes a plurality of row virtual sub-pixels, and the row virtual sub-pixels include a row virtual pixel driving circuit.
  • the row dummy pixel driving circuit includes a row dummy transistor and a row dummy signal line, and the row dummy transistor and the row dummy signal line are connected to each other to form an integral structure.
  • the overall structure is connected to the first power line.
  • the display panel includes a plurality of the pixel driving circuits distributed in an array along a first direction and a second direction, the first direction being a row direction, and the second direction is the column direction; the pixel driving circuit is used to drive the light-emitting unit to emit light.
  • the pixel driving circuit also includes a fourth transistor, a sixth transistor and a seventh transistor. The first electrode of the fourth transistor is connected to the driving transistor.
  • the second electrode, the gate electrode is connected to the third gate line, the second electrode is connected to the data line;
  • the first electrode of the sixth transistor is connected to the first electrode of the driving transistor, and the second electrode is connected to the first electrode of the light-emitting unit ;
  • the first electrode of the seventh transistor is connected to the first electrode of the light-emitting unit, the second electrode is connected to the second initial signal line, and the gate electrode is connected to the third reset signal line;
  • the seventh transistor in the pixel driving circuit of this row is in The front projection of the base substrate is located on the side of the virtual pixel row on the front projection of the base substrate away from the sixth transistor in the pixel driving circuit of the current row on the front projection of the base substrate;
  • the display The panel further includes a first active layer located between the base substrate and the first conductive layer, the first active layer including a fourth active portion for forming the fourth transistor.
  • a sixth active part used to form the channel region of the sixth transistor
  • a seventh active part used to form the channel region of the seventh transistor
  • a third conductive part at least partially located In the area where the virtual pixel row is located, the third conductive portion extends along the second direction in the orthographic projection of the base substrate, and the third conductive portion is used to connect the sixth transistor in the pixel driving circuit of this row.
  • the first conductive layer also includes: the third gate line extending along the first direction in the orthographic projection of the base substrate And covering the orthographic projection of the fourth active part on the base substrate, part of the structure of the third gate line is used to form the gate of the fourth transistor; the third reset signal line is The orthographic projection of the base substrate extends along the first direction and covers the seventh active part, and part of the structure of the third reset signal line is used to form the gate of the seventh transistor; wherein, this row The third gate line of the pixel driving circuit is multiplexed as the third reset signal line of the pixel driving circuit of the previous row.
  • the row virtual pixel driving circuit further includes a row virtual storage capacitor
  • the row virtual signal lines include a row virtual second initial signal line, a row virtual third reset signal line, a row virtual third reset signal line, A virtual gate line and a row virtual enable signal line.
  • the row virtual transistor includes a row virtual driving transistor and a row virtual fifth transistor.
  • the orthogonal projection of the row virtual fifth transistor on the substrate substrate is consistent with the row virtual driving transistor.
  • the transistor has a first fracture area between the orthographic projections of the base substrate, the third conductive part is located in the first fracture area in the orthographic projection of the base substrate, and the row of virtual storage capacitors has a first fracture area.
  • the orthographic projection of the two electrodes on the base substrate, the orthographic projection of the row virtual second initial signal line on the base substrate, the orthographic projection of the row virtual third reset signal line on the base substrate, The orthographic projection of the row virtual gate line on the substrate and the orthographic projection of the row virtual enable signal line on the substrate are both disconnected in the first fracture area.
  • the third conductive portion is located on the first conductive layer;
  • the row dummy pixel driving circuit includes a row dummy first transistor, and a first row dummy transistor
  • the first electrode is connected to the gate of the row virtual driving transistor, the second electrode is connected to the row virtual first initial signal line, and the gate is connected to the row virtual second reset signal line;
  • the row virtual signal line also includes the row virtual second reset signal line , the row of virtual second reset signal lines is located on the third conductive layer, the row of virtual second reset signal lines extend along the first direction in the orthographic projection of the substrate and is located on the first fracture between the area and the area where the pixel driving circuit of the previous row is located;
  • the display panel also includes: a fifth bridge portion located on the fourth conductive layer, the fifth bridge portion is connected to the third conductive portion and the third conductive portion through via holes respectively.
  • the second pole of the sixth transistor in the pixel driving circuit of this row, and the orthographic projection of the fifth bridge portion on the substrate intersects with the orthographic projection
  • the display panel further includes: a plurality of virtual pixel columns, the virtual pixel column is located between two adjacent columns of sub-pixels, the virtual pixel column includes a plurality of column virtual sub-pixels.
  • the column dummy sub-pixel includes a column dummy pixel driving circuit, the column dummy pixel driving circuit includes a channel region of a column dummy reset transistor, and the channel region of the column dummy reset transistor is on the base substrate
  • the orthographic projection has a second fracture area; the first conductive layer also includes a third reset signal line, the third reset signal line extends along the first direction and passes through the orthographic projection of the substrate substrate. The second fracture zone.
  • the virtual pixel column further includes a column virtual storage capacitor and a column virtual signal line.
  • the first electrode of the column virtual storage capacitor is connected to the enable signal line.
  • Virtual signal lines and columns of virtual transistors are connected into an integral structure, and the integral structure is connected to the first power line.
  • a display device including the display panel according to any embodiment of the present disclosure.
  • the first bridge portion located on the fourth conductive layer connects the eighth active portion and the first conductive portion, and connects the first electrode of the second transistor T to the gate electrode of the driving transistor T.
  • the first The orthographic projection of the bridge portion on the base substrate perpendicularly intersects the orthographic projection of the two sides of the first extending portion in the first gate line on the base substrate.
  • the distance between the third conductive layer and the fourth conductive layer can be reduced.
  • the stress of the dielectric layer between the first bridge portion and the first gate line can cause the structures on both sides of the first gate line to have the same stress environment, so that the dielectric layer between the fourth conductive layer and the third conductive layer Stress is evenly distributed, thereby reducing the risk of breakage of the dielectric layer.
  • Figure 1 is a schematic circuit structure diagram of a pixel driving circuit in a display panel according to an embodiment of the present disclosure
  • Figure 2 is a timing diagram of each node in a driving method of the pixel driving circuit in Figure 1;
  • Figure 3 is a structural layout of a display panel according to an embodiment of the present disclosure.
  • Figure 4 is a structural layout of the first conductive layer in Figure 3;
  • Figure 5 is a structural layout of the second conductive layer in Figure 3;
  • Figure 6 is a structural layout of the second active layer in Figure 3.
  • Figure 7 is a structural layout of the third conductive layer in Figure 3.
  • Figure 8 is a structural layout of the fourth conductive layer in Figure 3.
  • Figure 8a is a top view of the stack of the first gate line and the first bridge portion according to an embodiment of the present disclosure
  • Figure 8b is a top view of the stack of the first gate line and the first bridge portion according to another embodiment of the present disclosure.
  • Figure 8c is a top view of the stack of the first gate line and the first bridge portion according to another embodiment of the present disclosure.
  • Figure 8d is a top view of the first bridge portion and the second gate line stack according to an embodiment of the present disclosure
  • Figure 9 is a structural layout of the first active layer in Figure 3.
  • Figure 10 is a structural layout of the fifth conductive layer in Figure 3.
  • Figure 11 is the structural layout of the light shielding layer in Figure 3;
  • Figure 12 is a stacked structure layout of the second conductive layer, the second active layer and the third conductive layer in Figure 3;
  • Figure 13 is a layout of the stacked structure of the second conductive layer, the third conductive layer and the fourth conductive layer in Figure 12;
  • Figure 13a is a stacked top view of the first grid line, the second grid line and the first bridge portion according to an embodiment of the present disclosure
  • Figure 13b is a stacked top view of the first gate line, the second gate line and the first bridge portion according to another embodiment of the present disclosure
  • Figure 13c is a stacked top view of the first grid line, the second grid line and the first bridge portion according to yet another embodiment of the present disclosure
  • Figure 13d is a stacked top view of the first gate line, the second gate line and the first bridge portion according to another embodiment of the present disclosure
  • Figure 14 is a stacked structure layout of the first active layer and the first conductive layer in Figure 3;
  • Figure 15 is a stacked layout of the first conductive layer and the active layer in two adjacent pixel driving circuits in the column direction;
  • Figure 16 is a lamination layout of the second active layer and the fifth conductive layer in Figure 3;
  • Figure 17 is a stacked structure layout of the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer in Figure 3;
  • Figure 18 is a stacked structure layout of the second conductive layer and the fifth conductive layer in the two repeating units;
  • Figure 19 is the structural layout of the fourth conductive layer in the two repeating units.
  • Figure 20 is a schematic diagram of a pixel arrangement structure according to an embodiment of the present disclosure.
  • Figure 21 is a schematic diagram of a gate driver on array (GOA) load of a display area in related technology
  • Figure 22 is a schematic diagram of the GOA load of the display area according to an embodiment of the present disclosure.
  • Figure 23 is a structural layout of the display panel in the dotted box area in Figure 20;
  • Figure 24 is a structural layout of the first conductive layer in Figure 23;
  • Figure 25 is a structural layout of the fourth conductive layer in Figure 23;
  • Figure 26 is a stacked structure layout of the first conductive layer and the fourth conductive layer in Figure 23;
  • Figure 27 is a structural layout of the first active layer in Figure 23;
  • Figure 28 is a structural layout of the second conductive layer in Figure 23;
  • Figure 29 is a structural layout of the second active layer in Figure 23;
  • Figure 30 is a structural layout of the third conductive layer in Figure 23;
  • Figure 31 is a structural layout of the fifth conductive layer in Figure 23;
  • Fig. 32 is a cross-sectional view along the AA direction in Fig. 23.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • FIG. 1 is a schematic circuit structure diagram of a pixel driving circuit in a display panel according to an embodiment of the present disclosure.
  • the pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor C.
  • the second electrode of the first transistor T1 is connected to the first initial signal terminal INIT1
  • the first electrode is connected to the first node N1
  • the gate is connected to the first reset signal terminal RE1
  • the first electrode of the second transistor T2 is connected to the gate of the driving transistor T3.
  • the second pole is connected to the third node N3, and the gate is connected to the first gate drive signal terminal GATE1; the gate of the drive transistor T3 is connected to the first node N1; the second pole of the fourth transistor T4 is connected to the data signal terminal DATA, and the gate of the fourth transistor T4 is connected to the data signal terminal DATA.
  • One pole is connected to the second pole of the driving transistor T3, and the gate is connected to the second gate driving signal terminal GATE2; the first pole of the fifth transistor T5 is connected to the second pole of the driving transistor T3, and the second pole is connected to the first power supply terminal VDD.
  • the gate is connected to the enable signal terminal EM; the first electrode of the sixth transistor T6 is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the second electrode of the seventh transistor T7 is connected to the second initial signal terminal INIT2, The first electrode is connected to the second electrode of the sixth transistor T6, and the gate electrode is connected to the second reset signal terminal RE2.
  • the storage capacitor C is connected between the gate of the driving transistor T3 and the first power terminal VDD.
  • the pixel driving circuit can be connected to a light-emitting unit OLED for driving the light-emitting unit OLED to emit light.
  • the light-emitting unit OLED can be connected between the second pole of the sixth transistor T6 and the second power terminal VSS.
  • the first transistor T1 and the second transistor T2 may be N-type transistors.
  • the first transistor T1 and the second transistor T2 may be N-type metal oxide transistors.
  • N-type metal oxide transistors have smaller leakage. current, so that the light-emitting phase can be avoided, the node N leaks through the first transistor T1 and the second transistor T2.
  • the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors.
  • the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 can be a P-type low-temperature polycrystalline silicon transistor.
  • the P-type low-temperature polycrystalline silicon transistor has high carrier mobility, which is conducive to achieving high resolution, high response speed, high pixel density, and high Aperture ratio of the display panel.
  • the first initial signal terminal INIT1 and the second initial signal terminal can output the same or different voltage signals according to actual conditions.
  • the transistors used in each embodiment of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • FIG 2 it is a timing diagram of each node in a driving method of the pixel driving circuit in Figure 1.
  • G1 represents the timing of the first gate drive signal terminal GATE1
  • G2 represents the timing of the second gate drive signal terminal GATE2
  • Re1 represents the timing of the first reset signal terminal RE1
  • Re2 represents the timing of the second reset signal terminal RE2.
  • EM represents the timing of the enable signal terminal EM
  • Da represents the timing of the data signal terminal DATA.
  • the driving method of the pixel driving circuit may include a first reset stage t1, a compensation stage t2, a second reset stage t3, and a light emitting stage t4.
  • the first reset phase t1 the first reset signal terminal RE1 outputs a high level signal, the first transistor T1 is turned on, and the first initial signal terminal INIT1 inputs an initial signal to the first node N1.
  • the compensation stage t2 the first gate drive signal terminal GATE1 outputs a high-level signal, the second gate drive signal terminal GATE2 outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and at the same time the data signal terminal DATA
  • the driving signal is output to write the voltage Vdata+Vth (that is, the sum of the voltages Vdata and Vth) to the second node N2, where Vdata is the voltage of the driving signal, and Vth is the threshold voltage of the driving transistor T3.
  • the second reset signal terminal RE2 outputs a low-level signal
  • the seventh transistor T7 is turned on
  • the second initial signal terminal INIT2 inputs an initial signal to the second pole of the sixth transistor T6.
  • Light-emitting stage t4 The enable signal terminal EM outputs a low-level signal
  • the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata+Vth stored in the capacitor C.
  • the driving transistor output current formula I ( ⁇ WCox/2L)(Vgs-Vth) 2 , where ⁇ is the carrier mobility; Cox is the gate storage capacitance per unit area, W is the width of the driving transistor channel, L The length of the drive transistor channel, Vgs is the gate-source voltage difference of the drive transistor, and Vth is the threshold voltage of the drive transistor.
  • the pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.
  • the display panel provided by this exemplary embodiment may include a plurality of pixel driving circuits distributed in arrays along the first direction and the second direction.
  • the pixel driving circuit is used to drive the light-emitting device to emit light.
  • the first direction and the second direction intersect.
  • the pixel driving circuit It includes a driving transistor T3 and a second transistor T2.
  • the first electrode of the second transistor T2 is connected to the gate of the driving transistor T3, and the second electrode is connected to the first electrode of the driving transistor T3.
  • the pixel driving circuit may be as shown in FIG. 1 .
  • the pixel driving circuit in the display panel may also have other structures, such as 8T1C, 9T1C, etc.
  • FIG. 3 is a structural layout of a display panel according to an embodiment of the present disclosure.
  • FIG. 4 is a structural layout of the first conductive layer in FIG. 3 .
  • FIG. 5 is a structural layout of the second conductive layer in FIG. 3 .
  • FIG. 6 is a structural layout of FIG. 3
  • the structural layout of the second active layer in Figure 7 is the structural layout of the third conductive layer in Figure 3.
  • Figure 8 is the structural layout of the fourth conductive layer in Figure 3.
  • the display panel can It includes: a base substrate, a first conductive layer 2, a second conductive layer 3, a second active layer 4, a third conductive layer 5, a dielectric layer, and a fourth conductive layer 6, where the first conductive layer 2 is located
  • the first conductive layer 2 may include a first conductive part 21, which may be used to form the gate of the driving transistor T3;
  • the second active layer 4 is located on the first conductive layer 2 facing away from the substrate.
  • the second active layer 4 may include a second active part 42 and an eighth active part 48.
  • the second active part 42 may be used to form a channel region of the second transistor T2.
  • the eighth active part 48 is connected to one side of the second active part 42; the third conductive layer 5 is located on the side of the second active layer 4 facing away from the base substrate.
  • the third conductive layer 5 may include a first gate line G1.
  • the orthographic projection of G1 on the substrate extends along the first direction and covers the second active portion 42 . Part of the structure of the first gate line G1 can be used to form the top gate of the second transistor T2 .
  • the eighth active portion 48 is on the substrate.
  • the orthographic projection of the substrate and the orthographic projection of the first conductive portion 21 on the substrate are respectively located on both sides of the orthographic projection of the first gate line G1 on the substrate; the dielectric layer is located on a side of the third conductive layer 5 facing away from the substrate.
  • the fourth conductive layer 6 is located on the side of the dielectric layer facing away from the base substrate.
  • the fourth conductive layer 6 may include a first bridge part 61, and the first bridge part 61 may be connected to the eighth active part 48 and the eighth active part 48 through via holes respectively.
  • the first conductive part 21; wherein, the first gate line G1 may include sixth and seventh sides that are oppositely arranged and have the same extension direction. At least part of the sixth side is formed between the orthographic projection of the base substrate and the first The orthographic projection of the bridge portion on the base substrate is perpendicular, and the orthographic projection of at least part of the seventh side structure on the base substrate is perpendicular to the orthographic projection of the first bridge portion on the base substrate.
  • the first bridge portion 61 located on the fourth conductive layer 6 connects the eighth active portion 48 and the first conductive portion 21, and connects the first electrode of the second transistor T2 to the driving transistor T3.
  • the gate electrode, the orthographic projection of the first bridge portion 61 on the base substrate perpendicularly intersects with the orthographic projection of the two sides of the first gate line G1 on the base substrate, on the one hand, it can reduce the size of the third conductive layer 5
  • the stress of the dielectric layer between the fourth conductive layer 6 and the fourth conductive layer 6 can make the structural stress environment of the first bridge portion 61 on both sides of the first gate line G1 the same or similar, so that the fourth conductive layer 6 and the third conductive layer 6
  • the stress of the dielectric layer between the conductive layers 5 is evenly distributed, thereby reducing the risk of fracture of the dielectric layer.
  • a certain structure A extending in direction B means that A may include a main part and a secondary part connected to the main part.
  • the main part is a line, line segment or bar-shaped body, and the main part extends in direction B.
  • the length of the main part extending along direction B is greater than the length of the minor part extending along other directions.
  • the first direction X may be the row direction
  • the second direction Y may be the column direction.
  • the display panel may include a plurality of pixel driving circuits, and the plurality of pixel driving circuits may include a first pixel driving circuit P1 and a second pixel driving circuit P2 adjacently distributed in the row direction
  • the pixel driving circuit P2 can be arranged in mirror symmetry.
  • the first pixel driving circuit P1 and the second pixel driving circuit P2 may form a repeating unit, and the display panel may include a plurality of repeating units distributed in an array in the row direction X and the column direction Y.
  • the first gate line G1 may include a sixth side 56 and a seventh side 57
  • the sixth side 56 may include a first segment 561
  • the seventh side 57 A second segment 571 may be included.
  • Figure 8a is a top view of the stack of the first gate line and the first bridge portion according to an embodiment of the present disclosure.
  • the first segment 561 is in the orthographic projection of the base substrate and the second segment 571 is in The orthographic projections of the base substrate can be parallel to each other, and the orthographic projection of the first bridge portion 61 on the base substrate is perpendicular to the orthographic projection of the first segment 561 on the base substrate and the orthographic projection of the second segment 571 on the base substrate.
  • Figure 8b is a top view of the stack of the first gate line and the first bridge portion according to another embodiment of the present disclosure.
  • the orthographic projection of the first segment 561 on the base substrate and the second segment 571 may also be non-parallel, that is, the straight-line extension of the orthographic projection of the first side on the base substrate and the straight-line extension of the orthographic projection of the second side on the base substrate have intersection points.
  • the first bridge portion 61 is set correspondingly according to the specific structure of the first segment 561 and the second segment 571, so that the front projection of the first bridge portion 61 on the base substrate is consistent with the front projection of the first segment 561 on the base substrate.
  • the projection and the orthographic projection of the second segment 571 on the substrate substrate respectively intersect perpendicularly.
  • the first bridge part 61 may include two components, one component is perpendicularly intersected with the orthographic projection of the first segment 561 on the substrate substrate, and the other component is located on the orthogonal projection of the substrate substrate.
  • the projection perpendicularly intersects the orthographic projection of the second segment 571 on the base substrate, so that the orthographic projection of the first bridge 61 on the base substrate is the same as the orthographic projection of the first segment 561 on the base substrate and the orthographic projection of the second segment 571 on the base substrate.
  • the orthographic projections of the substrate substrate are all vertically intersecting, thereby reducing the stress of the dielectric layer.
  • the sixth side 56 may also include other segments, and the orthographic projection of the other segments on the base substrate may not be perpendicular to the orthographic projection of the first bridge portion 61 on the base substrate.
  • FIG. 8c is a top view of the stack of the first grid line and the first bridge part according to yet another embodiment of the present disclosure.
  • the sixth side 56 may also include a third segment, and The orthographic projection of the third segment on the base substrate intersects but is not perpendicular to the orthographic projection of the first bridge portion 61 on the base substrate.
  • the orthographic projection of the first bridge portion 61 on the base substrate can be arranged to perpendicularly intersect with the orthographic projection of the main part of the sixth side 56 on the base substrate.
  • the main component of the sixth side 56 An orthographic projection of the base substrate intersects perpendicularly with an orthographic projection of the first bridge portion on the base substrate.
  • the length of the first segment 561 in the orthographic projection of the base substrate is S2
  • the length of the sixth side 56 in the orthographic projection of the base substrate and the first bridge portion are in the orthogonal projection of the base substrate.
  • S2/S1 can be set to be greater than or equal to 0.7 and less than or equal to 1
  • S2/S1 can be, for example, 0.7, 0.8, 0.9, 1, etc. That is, in the portion where the sixth side 56 intersects the orthographic projection of the base substrate and the first bridge portion on the orthographic projection of the base substrate, the proportion of the vertically intersecting portion and the entire overlapping portion is greater than the set value to satisfy
  • the orthographic projection of the main part of the overlapping portion of the sixth side 56 and the first bridge portion on the base substrate perpendicularly intersects with the orthographic projection of the first bridge portion on the base substrate, which can also play a role in reducing the stress of the dielectric layer, thereby Helps prevent dielectric layer breakage.
  • the length of the orthographic projection of the second segment 571 on the base substrate is S4
  • S4/S3 is greater than or equal to 0.7 and less than or equal to 1.
  • the display panel may also include a light-shielding layer, a first active layer 1, a second conductive layer 3, and a fifth conductive layer 7, wherein the base substrate, the light-shielding layer, the third An active layer 1, a first conductive layer 2, a second conductive layer 3, a second active layer 4, a third conductive layer 5, a fourth conductive layer 6, and a fifth conductive layer 7 are stacked in sequence, and one of the above functional layers There can be an insulation layer between them.
  • the first conductive layer 2 may be a first gate metal layer (Gate1 layer)
  • the second conductive layer 3 may be a second gate metal layer (Gate2 layer)
  • the third conductive layer 5 may be a third gate metal layer (Gate3 layer).
  • the fourth conductive layer 6 may be the first metal wiring layer (SD1 layer)
  • the fifth conductive layer 7 may be the second metal wiring layer (SD2 layer).
  • Figure 9 is a structural layout of the first active layer in Figure 3.
  • Figure 10 is a structural layout of the fifth conductive layer in Figure 3.
  • Figure 11 is a structural layout of the light shielding layer in Figure 3.
  • Figure 12 is a structural layout of the second conductive layer in Figure 3. layer, the second active layer and the third conductive layer.
  • Figure 13 is the stack structure layout of the second conductive layer, the third conductive layer and the fourth conductive layer in Figure 12.
  • Figure 14 is the layout of the stack structure in Figure 3.
  • Figure 15 is the stacked layout of the first conductive layer and the active layer in two pixel driving circuits adjacent in the column direction.
  • Figure 16 is the stacked structure layout of the first active layer and the first conductive layer in Figure 3.
  • Figure 17 is the stacked structure layout of the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer in Figure 3.
  • Figure 18 is the two The stacked structural layout of the second conductive layer and the fifth conductive layer in the repeating unit.
  • Figure 19 is the structural layout of the fourth conductive layer in the two repeating units.
  • the second transistor T2 may be an oxide transistor, and the second transistor T2 may have a double-gate structure.
  • the second active layer 4 may include a second active portion 42.
  • the second active part 42 is used to form a channel region of the second transistor T2.
  • the second conductive layer 3 may include a second gate line G2, which may be used to form a bottom gate of the second transistor T2. Specifically, as shown in FIG.
  • the orthographic projection of the first gate line G1 on the base substrate can cover the orthographic projection of the second active part 42 on the base substrate, and part of the structure of the first gate line G1 is used to form the third
  • the top gate of the second transistor T2 and the orthographic projection of the second gate line G2 on the base substrate can cover the orthographic projection of the second active part 42 on the base substrate, and part of the structure of the second gate line G2 can form the second transistor T2 bottom gate. Therefore, the orthographic projection of the first bridge portion 61 on the base substrate in this exemplary embodiment also has an overlapping portion with the orthographic projection of the second gate line G2 on the base substrate.
  • the orthographic projection of the first bridge portion 61 on the base substrate may perpendicularly intersect the orthographic projection of at least part of the structure of the second gate line G2 on the base substrate.
  • FIG. 8d is a top view of the first bridge part and the second gate line stack according to an embodiment of the present disclosure.
  • the second gate line G2 may include a second extension part 33.
  • the two extension parts 33 may include a third side 331 and a fourth side 332 that are oppositely arranged.
  • the front projection of the first bridge part on the base substrate may be aligned with the partial segment A of the third side 331 on the front side of the base substrate.
  • the projections intersect perpendicularly and/or intersect perpendicularly with the orthographic projection of the fourth side portion segment B on the base substrate. This structure is also beneficial to reducing the stress of the dielectric layer, thereby reducing the risk of dielectric layer breakage.
  • the second gate line G2 and the first gate line G1 have a certain protruding height in the direction perpendicular to the plane of the base substrate, and the first bridge portion 61 needs to pass over the second gate line G2 and the first gate line.
  • the raised structure formed by the line G1 connects the eighth active portion 48 and the first conductive portion 21 located on both sides of the gate line, that is, the first bridge portion 61 forms a climbing or descending slope on one side of the first gate line G1 structure, forming a downhill or climbing structure on the other side of the first grid line G1.
  • the present disclosure can further improve the structures of the first gate line G1 and the second gate line G2 to further reduce the breakage of the dielectric layer between the fourth conductive layer 6 and the third conductive layer 5 risk.
  • Figure 13a is a stacked top view of the first gate line, the second gate line and the first bridge portion according to an embodiment of the present disclosure.
  • the first grid line G1 may have a first extension portion 51
  • the first extension portion 51 may have a first side 511 and a second side 512 arranged oppositely
  • the second grid line G2 may have a
  • the second extension part 33 has a third side 331 and a fourth side 332 arranged oppositely, and the orthographic projection of the first side 511 on the base substrate is located on the second side 512 on the base substrate.
  • the orthographic projection of the first conductive part 21 is on the side of the orthographic projection of the base substrate.
  • the third side 331 is located on the orthographic projection of the base substrate.
  • the fourth side 332 is on the orthographic projection of the base substrate away from the first conductive part.
  • 21 is on the orthographic projection side of the base substrate, that is, the first side is adjacent to the third side, and the second side is adjacent to the fourth side.
  • the orthographic projection of the first extension portion 51 on the base substrate may be the portion where the orthographic projection of the first grid line G1 on the base substrate overlaps with the orthographic projection of the first bridge portion 61 on the base substrate.
  • the orthographic projection of the second extension portion 33 on the base substrate may be a portion where the orthographic projection of the second grid line G2 on the base substrate overlaps with the orthographic projection of the first bridge portion 61 on the base substrate. It can be understood that the orthographic projection of other structures of the first gate line G1 and the other structures of the second gate line G2 on the base substrate may not be perpendicular to or intersect with the orthographic projection of the first bridge portion 61 on the base substrate.
  • the orthographic projection of the second extension portion 33 on the base substrate can completely cover the orthographic projection of the first extension portion 51 on the base substrate, and the first side
  • the distance between 511 and the third side 331 and the distance 332 between the second side 512 and the fourth side are both greater than zero, which is equivalent to the second extension part 33 being on both sides of the first extension part 51 in the second direction Y.
  • the width of the extension section of the second extension part 33 in the column direction can be increased.
  • the slope between the second extension part 33 and the first extension part 51 can be reduced.
  • the second extension part 33 can be made There is a certain distance between the slope of the first extension part 51 and the slope of the first extension part 51. In this way, the first bridge part 61 forms a climbing structure on both sides of the second extension part 33 and the first extension part 51.
  • the dielectric layer can be reduced.
  • the stress of the dielectric layer can be released in time, so the risk of fracture of the dielectric layer can be effectively reduced.
  • the distance in the second direction Y between the orthographic projection of any first node on the third side 331 on the base substrate and the orthographic projection of the first side 511 on the base substrate is L1
  • the distance in the second direction Y between the orthographic projection of the first node on the substrate and the orthographic projection of the fourth side 332 on the substrate is L2
  • L1/L2 can be set to be greater than or equal to 0.25 and less than or equal to 0.8, For example, it can be 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, etc. to increase the length of the extended section of the first side that the third side exceeds in the second direction.
  • the fourth side 332 of the second extension part 33 may have a similar structure to the second side 512 of the first extension part 51 , and any second node on the fourth side 332 is between the orthographic projection of the substrate and the substrate.
  • the distance between the orthographic projection of the second side 512 on the base substrate in the second direction Y is L3.
  • the orthographic projection of the second node on the base substrate and the orthographic projection of the third side on the base substrate are in the second direction Y.
  • L4 The distance on is L4, and L3/L4 can be set to be greater than or equal to 0.25 and less than or equal to 0.8, for example, it can be 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, etc.
  • the width of the overlapping area in the second direction Y between the orthographic projection of the first extension part 51 on the base substrate and the orthographic projection of the second extension part 33 on the base substrate is L5, where L1/L5 can be set to 0.6 ⁇ 1, for example, it can be 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1, etc.
  • L3/L5 can be set to 0.6 ⁇ 1, for example, it can be 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1, etc.
  • the interval of the slopes on both sides of the first extension part 51 can be increased. distance, so that after the dielectric layer goes uphill on one side of the first extension part 51, it can have a certain buffer time before going downhill on the other side of the first extension part 51.
  • the stress of the dielectric layer is reduced and can be release, thereby further reducing the risk of breakage of the dielectric layer.
  • the orthographic projection of the second extension portion 33 on the substrate may cover the orthographic projection of the first extension 51 on the substrate, and the second extension 33 is on the substrate.
  • the orthographic projection of the substrate has a first centerline in the first direction
  • the orthographic projection of the base substrate may be centered on the second extension 33 within the orthographic projection of the base substrate.
  • the second extension part 33 has a first width in the second direction Y in the orthographic projection of the base substrate, and the first extension part 51 has a second width in the second direction Y in the orthographic projection of the base substrate. At the same position, the first extension part 33 has a first width in the second direction Y.
  • the ratio of the width to the second width may be 1.5-3, for example, 1.5, 1.7, 1.8, 2.0, 2.2, 2.4, 2.6, 2.8, 3.0, etc.
  • the same position described in this exemplary embodiment can be understood as a point on one side of the first extension part 51 on the orthographic projection of the substrate along the second direction Y to the other side on the substrate.
  • the orthographic projection is used as a line segment to obtain the first line segment.
  • the orthographic projection of a point on one side of the second extension part on the substrate is used as a line segment along the second direction Y to the orthographic projection of the other side on the substrate to obtain The second line segment, the straight line of the first line segment coincides with the straight line of the second line segment.
  • the orthographic projection of the second extension part 33 on the base substrate may cover one side of the orthographic projection of the first extension part 51 on the base substrate without covering the other side.
  • the orthographic projection of the first extension part 51 on the base substrate may cover one side of the orthographic projection of the second extension part 33 on the base substrate without covering the other side.
  • FIG. 13b is a stacked top view of the first grid line, the second grid line and the first bridge part according to another embodiment of the present disclosure. As shown in FIG.
  • the first extension part 51 has oppositely arranged The first side 511 and the second side 512
  • the second extension part 33 has a third side 331 and a fourth side 332 arranged oppositely
  • the first side 511 is adjacent to the third side 331
  • the second The side 512 is adjacent to the fourth side 332 .
  • the second extension part 33 has a first width d1 in the second direction Y in the orthographic projection of the base substrate, and the first extension part 51 has a second width d2 in the second direction Y in the orthographic projection of the base substrate;
  • the first side 511 is adjacent to the third side 331 and has a first distance L1 in the second direction Y;
  • the second side 512 is adjacent to the fourth side 332 and has a second distance L2 in the second direction Y;
  • the orthographic projection of 33 on the base substrate may cover the first side 511, and the orthographic projection of the first extension part 51 on the base substrate may cover the fourth side 332.
  • the climbing difficulty of the dielectric layer can also be reduced by increasing the first distance L1 and the second distance L2, so that the stress of the dielectric layer between the fourth conductive layer 6 and the third conductive layer 5 can be eliminated in time. release, thereby reducing the risk of breakage of the dielectric layer.
  • the ratio of the first distance L1 to the second width d2 at the same position may be 0.25 ⁇ 0.8, for example, it may be 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8 etc.
  • the ratio of the second distance L2 to the second width d2 may be 0.25 ⁇ 0.8, for example, it may be 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, etc.
  • the width of a certain extended portion in the second direction Y can be understood as the difference between any point on one side of the extended portion in the orthographic projection of the substrate and the other side in the orthogonal projection of the substrate. The distance projected in the second direction Y.
  • the orthographic projection of the first gate line G1 on the base substrate and the orthographic projection of the second gate line G2 on the base substrate do not overlap with the orthographic projection of other adjacent structures in the column direction on the base substrate. , that is, after the present disclosure widens the width of the first extending portion 51 in the first gate line G1 and/or the second extending portion 33 in the second gate line G2 in the column direction, it will not crowd out the width in the column direction. Space for other structures.
  • the first distance L1 may be set to be greater than or equal to 1.3 ⁇ m, for example, it may be 1.3 ⁇ m, 1.4 ⁇ m, 1.5 ⁇ m, 1.6 ⁇ m, 1.8 ⁇ m, etc.
  • the second distance L2 may be set to 1.3 ⁇ m or greater, for example, 1.3 ⁇ m, 1.4 ⁇ m, 1.5 ⁇ m, 1.6 ⁇ m, 1.8 ⁇ m, etc.
  • the boundary between the first extension portion 51 in the first gate line G1 and the orthographic projection of the substrate substrate and the second extension portion in the second gate line G2 can be added. 33 The distance between the orthographic projection boundaries of the base substrate.
  • the first active layer 1 may include a fifth active part 15 and a sixth active part 16, and the fifth active part 15 may be used to form a channel region of the fifth transistor T5,
  • the sixth active part 16 may be used to form the channel region of the sixth transistor T6, wherein the orthographic projection of the fifth active part 15 on the base substrate and the orthogonal projection of the sixth active part 16 on the base substrate are on the first
  • the ratio of the distance L2 to the sixth distance L6 may be set to be greater than or equal to 5%, for example, it may be 5%, 6%, 7%, 8%, etc.
  • the details can be set according to the pixel size.
  • the distance in the first direction X between the orthographic projection of the fifth active part 15 on the base substrate and the orthographic projection of the sixth active part 16 on the base substrate can be understood as,
  • the third active portion 15 in the orthographic projection of the base substrate is far away from the pixel driving circuit.
  • the side of the orthogonal projection of the base substrate and the sixth active portion 16 are far away from the pixel driving circuit in the orthographic projection of the base substrate.
  • the distance between the sides of the third active part in the orthographic projection of the base substrate that is, the distance between the outer edges of the two active parts in the orthographic projection of the base substrate.
  • the first gate line G1 may have a first component 52 and a second component 53 , and the first component 52 has a width greater than the second component 53 in the second direction Y.
  • the orthographic projection of the first component part 52 on the base substrate can cover the orthographic projection of the second active part 42 on the base substrate, forming the bottom gate of the second transistor T2.
  • the second gate line G2 may have a third component part 34 and a fourth component part 35. The width of the third component part 34 in the second direction Y may be greater than the width of the fourth component part 35 in the second direction Y.
  • the orthographic projection of the third component part 34 on the base substrate may cover the orthographic projection of the second active part 42 on the base substrate to form the top gate of the second transistor T2.
  • the orthographic projection of the third component part 34 on the base substrate may cover the orthographic projection of the first component part 52 on the base substrate.
  • Figure 13c is a stacked top view of the first gate line, the second gate line and the first bridge portion according to yet another embodiment of the present disclosure.
  • the fourth conductive layer 6 is The orthographic projection of the first bridge portion 61 on the base substrate may overlap with the orthographic projection of the first component portion 52 on the base substrate and the orthographic projection of the second component portion 53 on the base substrate, and the first bridge portion 61
  • the orthographic projection on the base substrate may also overlap with the orthographic projection of the third component part 34 on the base substrate and the orthographic projection of the fourth component part 35 on the base substrate.
  • the orthographic projection of the first bridge portion 61 on the base substrate may be the same as the orthographic projection of the first component portion 52 on the base substrate, and the orthographic projection of the third component portion 34 on the base substrate.
  • the orthographic projection part overlaps, and does not overlap with the orthographic projection of the second component part 53 on the base substrate and the orthographic projection of the fourth component part 35 on the base substrate. That is, the orthographic projection of the first bridge portion 61 on the base substrate only overlaps with the orthographic projection of the widened portions of the first gate line G1 and the second gate line G2 in the column direction on the base substrate, but does not overlap with the first gate line G1 and the second gate line G2.
  • the unwidened portions of G1 and the second gate line G2 do not overlap in the orthographic projection of the base substrate.
  • Figure 13d is a stacked top view of a first gate line, a second gate line and a first bridge portion according to another embodiment of the present disclosure.
  • the first bridge portion 61 The orthographic projection on the base substrate may overlap with the orthographic projection of the second component part 53 on the base substrate, the orthographic projection of the fourth component part 35 on the base substrate, and overlap with the first component part 52 on the orthographic projection of the base substrate.
  • the orthographic projection and the orthographic projection of the third component part 34 on the base substrate do not overlap, that is, the orthographic projection of the first bridge part 61 on the base substrate only overlaps with the first gate line G1 and the second gate line G2 in the column direction.
  • the widened portion overlaps in the orthographic projection of the base substrate, but does not overlap with the widened portions of the first gate line G1 and the second gate line G2 in the orthographic projection of the base substrate.
  • the light-shielding layer may include a plurality of light-shielding parts 10 distributed in the row direction X and the column direction Y, and adjacent light-shielding parts 10 may be connected to each other.
  • the light-shielding layer may be a conductor structure, for example, the light-shielding layer may be a light-shielding metal layer.
  • the first active layer 1 may also include a third active part 13 , a fourth active part 13 and a fourth active part 16 .
  • the active portion 17 may be used to form a channel region of the seventh transistor T7.
  • the first active layer 1 may also include a ninth active part 19, an eleventh active part 111, a twelfth active part 112, a thirteenth active part 113, a fifteenth active part 115,
  • the sixteenth active part 116 of which the ninth active part 19 is connected to the side of the seventh active part 17 away from the fourth node in the pixel driving circuit of the previous row, is used to form the second pole of the seventh transistor T7.
  • the eleventh active part 111 is connected between the third active part 13 and the sixth active part 16.
  • the eleventh active part 111 forms the third node N3 in FIG. 1 and connects the third node of the sixth transistor T6.
  • One pole is connected to the first pole of the drive transistor T3.
  • the twelfth active part 112 is connected between the third active part 13, the fourth active part 14, and the fifth active part 15.
  • the twelfth active part 112 forms the second node N2 in Figure 1
  • the first electrode of the fourth transistor T4 and the first electrode of the fifth transistor T5 are connected to the second electrode of the driving transistor T3.
  • the thirteenth active part 113 is connected between the sixth active part 16 and the seventh active part 17 .
  • the thirteenth active part 113 is used to form the fourth node N4 in FIG. 1 , and connects the sixth transistor T6
  • the second electrode is connected to the first electrode of the seventh transistor T7. It should be noted that in this exemplary embodiment, the seventh active part 17 for pixel driving in this row is located in the pixel driving circuit of the next row.
  • the thirteenth active part 113 is actually located in the pixel driving circuit of this row and the pixel driving circuit of the next row. between the next row of pixel driver circuits.
  • the fifteenth active part 115 is connected to the side of the fifth active part 15 away from the twelfth active part 112 and forms the second electrode of the fifth transistor T5.
  • the fifteenth active part 115 can pass through the via hole H1
  • the second bridge portion 62 located on the fourth conductive layer 6 is connected to connect the second electrode of the fifth transistor T5 to the first power line Vdd through the second bridge portion 62 .
  • the sixteenth active part 116 is connected to the side of the fourth active part 14 away from the twelfth active part 112 to form the second pole of the fourth transistor T4.
  • the sixteenth active part 116 can pass through the via hole H6
  • the sixth bridge portion 66 located on the fourth conductive layer 6 is connected to connect the second electrode of the fourth transistor T4 to the data line Data through the sixth bridge portion 66 .
  • the first active layer 11 may be formed of polysilicon semiconductor material.
  • the transistors in the display panel of the present disclosure may be P-type low-temperature polysilicon thin film transistors.
  • the orthographic projection of the first conductive portion 21 in the first conductive layer 2 on the base substrate can cover the orthographic projection of the third active portion 13 on the base substrate.
  • the first The conductive portion 21 may be used to form the gate electrode of the driving transistor T3 and the first electrode of the storage capacitor C.
  • the first conductive layer 2 may also include an enable signal line EM, a third reset signal line Re3, and a third gate line G3, wherein the enable signal line EM may be used to provide the enable signal terminal EM in FIG. 1, and the enable signal
  • the orthographic projection of the line EM on the base substrate may extend along the first direction , part of the structure is used to form the gate of the sixth transistor T6.
  • the third gate line G3 may be used to provide the second gate driving signal terminal GATE2 in FIG. 1 .
  • the third gate line G3 extends along the first direction X in the orthographic projection of the substrate and covers the fourth active portion 14 on the substrate.
  • part of the structure of the third gate line G3 is used to form the gate of the fourth transistor T4 and provide the second gate driving signal to the gate of the fourth transistor T4.
  • the third reset signal line Re3 may be used to provide the second reset signal terminal Re1 in FIG. 1 .
  • the orthographic projection of the third reset signal line Re3 on the substrate may extend along the first direction X and cover the seventh active part 17 .
  • Part of the structure of the three reset signal lines Re3 is used to form the gate of the seventh transistor T7 and provide the second reset signal to the gate of the seventh transistor T7.
  • the third gate line G3 of the pixel driving circuit of this row can be multiplexed as the third reset signal line Re3 of the pixel driving circuit of the previous row. This setting can improve the integration level of the pixel driving circuit and reduce the layout area of the pixel driving circuit.
  • the orthographic projection of the third reset signal line Re3 on the base substrate may cover the orthographic projection of the eighth active part 48 on the base substrate to form the first node N1 in FIG. 1 .
  • the display panel can use the first conductive layer 2 as a mask to perform conductive processing on the active layer. That is, the active layer covered by the first conductive layer 2 forms the channel region of the transistor, and is not covered by the third conductive layer 2 . The area covered by a conductive layer 2 forms a conductor structure.
  • the orthographic projection of a certain structure A on the base substrate described in this exemplary embodiment covers the orthographic projection of another structure B on the base substrate can be understood as the projection of B on the plane of the base substrate.
  • the contour is completely inside the contour of A projected in the same plane.
  • the second conductive layer 3 may include a first initial signal line Vinit1, a first reset signal line Re1, a second gate line G2, and a second conductive portion 32, where,
  • the first initial signal line Vinit1 can be used to provide the first initial signal terminal INIT1 in Figure 1.
  • the orthographic projection of the first initial signal line Vinit1 on the substrate can extend along the first direction X.
  • the first initial signal line Vinit1 can pass through the first
  • the third bridge portion 63 in the four conductive layers is connected to the fourteenth active portion 414 located in the second active layer 4, so that the second electrode of the first transistor T1 is connected to the first initial signal line Vinit1.
  • the first reset signal line Re1 may be used to provide the first reset signal terminal RE1 in FIG.
  • the orthographic projection of the first reset signal line Re1 on the substrate may extend along the first direction X and cover the first active part 41 on the substrate. In the orthographic projection of the base substrate, part of the structure of the first reset signal line Re1 is used to form the bottom gate of the first transistor T1.
  • the second gate line G2 may be used to provide the first gate driving signal terminal GATE1 in FIG. 1 .
  • the orthographic projection of the second gate line G2 on the substrate may extend along the first direction X and cover the second active part 42 on the substrate. In the orthographic projection of the base substrate, part of the structure of the second gate line G2 is used to form the bottom gate of the second transistor T2.
  • the orthographic projection of the second conductive portion 32 on the base substrate overlaps with the orthographic projection of the first conductive portion 21 on the base substrate.
  • the second conductive portion 32 can be used to form the second electrode of the storage capacitor C.
  • the second conductive portion 32 The first power line Vdd located on the fifth conductive layer 7 can be connected through the via H2, so that the second electrode of the storage capacitor C is connected to the first power line Vdd.
  • the eighth active part 48 in the second active layer 4 may be used to form the first node N1 in FIG. 1 .
  • the eighth active part 48 is connected to the first node N1 in FIG. 1 .
  • the first pole of the transistor T1 and the first pole of the second transistor T2 connect the first pole of the first transistor T1 and the first pole of the second transistor T2 to the first node N1.
  • the eighth active part 48 can
  • the first bridge portion 61 on the fourth conductive layer 6 is connected through the via hole H27, and the first node N1 is connected to the gate of the driving transistor T3 through the first bridge portion 61 through the via hole H43.
  • the second active layer 4 may also include a first active part 41, a tenth active part 410, and a fourteenth active part 414, wherein the first active part 41 may be used to form a channel region of the first transistor T1 , the eighth active part 48 connects the first pole of the second transistor T2 to the first node N1.
  • the tenth active part 410 is connected to the side of the second active part 42 away from the eighth active part 48 .
  • the tenth active part 410 can be connected to the fourth bridge part 64 located on the fourth conductive layer 6 through the via H5 , to connect the second pole of the second transistor T2 to the third node N3 through the fourth bridge portion 64 .
  • the fourteenth active part 414 is connected to an end of the first active part 41 away from the eighth active part 48 . At the same time, the fourteenth active part 414 can be connected to the third bridge located on the fourth conductive layer 6 through the via H3
  • the second electrode of the first transistor T1 is connected to the first initial signal line Vinit1 of the second conductive layer 3 through the third bridge portion 63 .
  • the second active layer 4 may be formed of indium gallium zinc oxide.
  • the first transistor T1 and the second transistor T2 may be N-type metal oxide thin film transistors.
  • the third conductive layer 5 may include a second reset signal line Re2 and a first gate line G1 , wherein the orthographic projection of the second reset signal line Re2 on the substrate may be along the The first direction
  • the orthographic projection of the first gate line G1 on the base substrate may extend along the first direction top gate.
  • the display panel can use the third conductive layer 5 as a mask to conduct conduction processing on the second active layer 4, that is, the area of the second active layer 4 covered by the third conductive layer 5 can form the channel of the transistor.
  • the area in the second active layer 4 that is not covered by the third conductive layer 5 forms a conductor structure.
  • the first bridge portion 61 in the fourth conductive layer 6 may include a first sub-connection portion 611 , a second sub-connection portion 612 and a third sub-connection portion 613 .
  • the sub-connection part 611 is connected between the second sub-connection part 612 and the third sub-connection part 613.
  • the orthographic projection of the first sub-connection part 611 on the base substrate can be connected to the side of the first extension part 51 in the first gate line G1. The edges intersect perpendicularly in the orthographic projection of the substrate.
  • the fourth conductive layer 6 may also include a second bridge part 62, a third bridge part 63, a fourth bridge part 64, and a sixth bridge part 66, wherein the second bridge part 62 may be connected to the fifteenth bridge part through the first via hole H1.
  • the active part 115, and the second bridge part 62 can also be connected to the first power line Vdd of the fifth conductive layer 7 through another via hole H2, thereby connecting the second electrode of the fifth transistor T5 to the first power line Vdd.
  • the second bridge portion 62 can also be connected to the second conductive portion 32 through the via hole H28, thereby connecting the second electrode of the storage capacitor C to the first power line Vdd.
  • the orthographic projection of the third bridge portion 63 on the base substrate may extend along the first direction 414 , thereby connecting the second pole of the first transistor T1 to the first initial signal line Vinit1 through the third bridge portion 63 .
  • the fourth bridge portion 64 can connect the eleventh active portion 111 through the via hole H4 and the tenth active portion 410 through the via hole H5, thereby connecting the second electrode of the second transistor T2 to the third node.
  • the sixth bridge portion 66 can be connected to the data line Data located on the fifth conductive layer 7 through the via hole H7 and connected to the sixteenth active portion 116 through the via hole H6 to connect the second electrode of the fourth transistor T4 to the data line Data.
  • the fourth conductive layer 6 may also include a second initial signal line Vinit2.
  • the second initial signal line Vinit2 may be used to provide the second initial signal terminal INIT2 in Figure 1. Part of the structure of the second initial signal line Vinit2 is bent. , to avoid the first bridge portion 61 and connect to the second initial signal line Vinit2 in the adjacent pixel driving circuit in the row direction.
  • the second initial signal line Vinit2 can be connected to the ninth active portion 19 through the via hole H9, thereby connecting
  • the second electrode of the seventh transistor T7 is connected to the second initial signal line Vinit2.
  • the first initial signal line Vinit1 is used to provide a first initialization signal
  • the second initial signal line Vinit2 is used to provide a second initialization signal.
  • the first initialization signal and the second initialization signal may not be equal, therefore,
  • the pixel driving circuit can provide different initialization signals to the first node N1 and the first electrode of the light-emitting device according to actual needs.
  • the effective level voltage of the first initialization signal can be set to -3V
  • the effective level voltage of the second initialization signal can be set to -4V, which can ensure that the display screen has low brightness in the black state and improve the screen display effect.
  • the fifth conductive layer 7 may include a first power line Vdd and a data line Data.
  • the first power line Vdd is in the orthographic projection of the base substrate, and the data line Data is in the orthogonal projection of the base substrate.
  • the orthographic projections of can all extend along the second direction Y, wherein the first power line Vdd can be used to provide the first power terminal VDD in FIG. 1, and the first power line Vdd can be connected to the fourth conductive layer 6 through the via H2.
  • the second bridge portion 62 connects the second pole of the fifth transistor T5 and the second pole of the storage capacitor C to the first power line Vdd through the second bridge portion 62 .
  • the data line Data can be used to provide the data signal terminal DATA in Figure 1.
  • the data line Data can be connected to the sixth bridge portion 66 of the fourth conductive layer 6 through the via H7, so that the fourth transistor T4 can be connected through the sixth bridge portion 66.
  • the second pole is connected to the data line Data.
  • a certain structure A extending in direction B means that A may include a main part and a secondary part connected to the main part.
  • the main part is a line, line segment or bar-shaped body, and the main part extends in direction B.
  • the length of the main part extending along direction B is greater than the length of the minor part extending along other directions.
  • the orthographic projection of the first power line Vdd on the base substrate can cover the orthographic projection of the eighth active part 48 on the base substrate, so that the first power line Vdd can Shielding and stabilizing one node can prevent static electricity or other signals in the circuit from interfering with the first node, thereby reducing crosstalk and further improving display uniformity.
  • the orthographic projection of the first power line Vdd on the base substrate can cover the orthographic projection of other structures of the second active layer 4 on the base substrate, that is, the first power line Vdd can The active layer 4 is shielded to block interference from other signals to the second active layer 4 , thereby improving the stability of the second active layer 4 .
  • the orthographic projection of the first conductive part 21 on the substrate may be located between the orthographic projection of the enable signal line EM on the substrate and the first gate line.
  • G1 is between the orthographic projection of the base substrate, and in the same pixel driving circuit, the first gate line G1 is an orthographic projection of the base substrate, the third reset signal line Re3 is an orthographic projection of the base substrate, and the first reset signal line
  • the orthographic projection of Re1 on the base substrate and the orthographic projection of the first initial signal line Vinit1 on the base substrate may be sequentially distributed in a direction away from the first conductive part 21 .
  • the orthographic projection of the first gate line G1 on the base substrate and the orthographic projection of the second gate line G2 on the base substrate may partially overlap
  • the orthographic projection of the first reset signal line Re1 on the base substrate and the second reset signal Orthographic projections of the line Re2 on the base substrate may partially overlap.
  • the second initial signal line Vinit2 may include a first signal line extension part Vinit2-1, a second signal line extension part Vinit2-2 and a third signal line extension part Vinit2-3.
  • the first signal line extension part The orthographic projection of Vinit2-1 on the substrate can extend along the first direction X and be located between the orthographic projection of the third reset signal line Re3 on the substrate and the orthographic projection of the first gate line G1 on the substrate, and the second The orthographic projection of the signal line extension part Vinit2-2 on the base substrate may extend along the second direction Y, and the orthographic projection of the third signal line extension part Vinit2-3 on the base substrate may extend along the first direction X and be located at the third reset position. Between the orthographic projection of the signal line Re3 on the base substrate and the orthogonal projection of the first reset signal line Re1 on the base substrate.
  • the plurality of pixel driving circuits may include a first pixel driving circuit P1 and a second pixel driving circuit P2 that are adjacently distributed in the row direction X.
  • the first pixel driving circuit P1 and the second pixel driving circuit P2 may be arranged in mirror symmetry.
  • the first pixel driving circuit P1 and the second pixel driving circuit P2 may form a repeating unit Q
  • the display panel may include a plurality of repeating units Q distributed in an array in the row direction X and the column direction Y. And among the two adjacent repeating units Q in the row direction, the first pixel driving circuit P1 in one repeating unit Q is adjacent to the second pixel driving circuit P2 in the other adjacent repeating unit Q.
  • the second pixel driving circuit P2 in Q is arranged adjacent to the first pixel driving circuit P1 in another repeating unit Q.
  • the first pixel driving circuit P1 and the second pixel driving circuit P2 are arranged in mirror symmetry, and the first power supply in the first pixel driving circuit P1
  • the line Vdd and the first power line Vdd in the second pixel driving circuit P2 may be connected as a whole, and the second conductive part 32 may not be connected.
  • the first pixel driving The first power line Vdd in the circuit P1 and the first power line Vdd in the second pixel driving circuit P2 in the adjacent repeating unit Q may not be connected, and the second conductive portion 32 in the first pixel driving circuit P1 and the phase
  • the second conductive part 32 in the second pixel driving circuit P2 in the adjacent repeating unit Q is connected, so that the power line VDD and the second conductive part 32 can form a grid structure, and the power line of the grid structure can reduce the power supply thereon. signal voltage drop.
  • the data line Data in the first pixel driving circuit P1 and the data line Data in the second pixel driving circuit P2 are not connected, and the two data lines Data are distributed in two both sides of the first power line Vdd.
  • the second bridge portion 62 in the first pixel driving circuit P1 and the second pixel driving center in the adjacent repeating unit Q are The second bridge portions 62 may be connected to each other, and the first pixel driving circuit P1 and the second pixel driving circuit P2 in the adjacent repeating unit Q may share a first via H1, and the two sub-pixels share a first via H1 , which can save the space occupied by sub-pixels and help improve the space utilization of the display panel.
  • the first pixel driving circuit P1 and the second pixel driving circuit P2 can share a third bridge portion 63, thereby saving the space occupied by the sub-pixels. It is beneficial to improve the space utilization of the display panel.
  • the problem that comes with it is that the loading of the array gate drive (Gate driver On Array, GOA) signal will be different between the area where the virtual pixel row is not inserted in the effective display area and the area where the virtual pixel row is inserted.
  • the scanning signal line Gate of this row continues to drive the seventh transistor T7 of this row, in the area where no dummy pixel row is inserted, one row of GOA drives one row of scanning signal line Gate and one row of reset signal line Reset, but in the area where no dummy pixel row is inserted, In the area where the virtual pixel rows are inserted, one row of GOA drives one row of scanning signal lines Gate and two rows of reset signal lines Reset.
  • Figure 23 is a structural layout of the display panel in the dotted box area in Figure 20.
  • Figure 24 is a structural layout of the first conductive layer in Figure 23.
  • Figure 25 is a structural layout of the fourth conductive layer in Figure 23.
  • Figure 26 is a structural layout of the fourth conductive layer in Figure 23.
  • Figure 27 is the structural layout of the first active layer in Figure 23.
  • Figure 28 is the structural layout of the second conductive layer in Figure 23.
  • Figure 29 is the structural layout of the second conductive layer in Figure 23.
  • Figure 30 is the structural layout of the third conductive layer in Figure 23, and
  • Figure 31 is the structural layout of the fifth conductive layer in Figure 23; the display panel can include all the structures of the display panel shown in Figure 3 .
  • the display panel may also include multiple virtual pixel rows.
  • the virtual pixel rows may be located between two adjacent rows of sub-pixels.
  • the pixel driving circuit in the row above the virtual pixel row The orthographic projection of the seventh transistor on the base substrate is located in the area where the orthographic projection of the pixel driving circuit of the next row of the virtual pixel driving circuit on the base substrate is located.
  • the virtual pixel row may include a plurality of virtual pixel driving circuits, the virtual pixel driving circuit may include virtual transistors and virtual signal lines, the virtual transistors and the virtual signal lines are connected to each other into an integral structure, and the integral structure is connected to the first power supply line. Further, the virtual pixel row may include a third conductive part 23.
  • the orthographic projection of the third conductive part 23 on the base substrate may extend along the second direction Y and be at least partially located in the area where the virtual pixel row is located.
  • the third conductive part 23 may be used
  • the second electrode of the sixth transistor T6 in the pixel driving circuit of the upper row of the virtual pixel row is connected to the first electrode of the seventh transistor T7 of the pixel driving circuit of the lower row of the virtual pixel row.
  • the third conductive part 23 may be located on the first conductive layer 2 , and one end of the third conductive part 23 may be connected to the seventh bridge part 67 located on the fourth conductive layer 6 through a via hole, and the seventh bridge part 67 may be connected to The fourth node N4 in the pixel driving circuit of the next row is connected to the third conductive part 23 and the fourth node of the pixel driving circuit of the next row through the seventh bridge part 67 .
  • the other end of the third conductive part 23 is connected to the fourth node N4 in the pixel driving circuit of the previous row, so that the first electrode of the seventh transistor T7 in the next row of the virtual pixel row is connected to the virtual pixel through the third conductive part 23
  • the second pole of the sixth transistor T6 in the row above is connected.
  • the GOA load at this time can be shown in Figure 22.
  • the area where the virtual pixel row is located can be understood as the orthographic projection of the virtual transistor in the virtual pixel row on the substrate, the orthographic projection of the virtual signal line on the substrate, and the connection of the virtual transistor.
  • the third conductive portion 23 can be located on the first conductive layer 2, that is, close to the underlying metal layer of the base substrate, which can reduce or weaken the connection between the metal lines and Parasitic capacitance of the anode metal.
  • the display panel may also include a fifth bridge portion 65 located on the fourth conductive layer 6 .
  • the fifth bridge portion 65 is located in the virtual pixel row.
  • the fifth bridge portion 65 can pass through the via hole H40 Connect the fourth node N4 in the pixel driving circuit of the previous row of the virtual pixel row, and connect the third conductive part 23 through the via H, so that through the cooperation of the third conductive part 23, the fifth bridge part 65 and the seventh bridge part 67, The fourth node of the next row of virtual pixels is connected to the fourth node of the previous row of virtual pixels.
  • the third conductive layer 5 may also be located on the second conductive layer 3 or the third conductive layer 5 or the fourth conductive layer 6 or the fifth conductive layer 7 .
  • the orthographic projection of the virtual signal line on the base substrate extends along the first direction X, and does not overlap with the orthographic projection of the third conductive portion 23 on the base substrate, This prevents parasitic capacitance between the signal line and the third conductive part 23 and helps provide a stable reset signal to the fourth node through the third conductive part 23 .
  • the first active layer 1 may include a row of virtual third active parts 118 , a row of virtual seventh active parts 119 , and a row of virtual eighth active parts. Department 120.
  • the orthographic projection of the row dummy seventh active part 119 on the substrate may extend along the column direction, and the row dummy seventh active part 119 may be used to form the row dummy fifth transistor.
  • the row dummy seventh active part 119 has The source portion 119 has a first break region M1 between the orthographic projection of the base substrate and the row-row dummy third active portion 118 in the present dummy pixel driving circuit.
  • the first conductive layer 2 may include a row virtual third reset signal line 210, a row virtual first conductive part 220, and a row virtual enable signal line 230.
  • the row dummy first conductive part 210 is connected to the row dummy enable signal line 230 .
  • the orthographic projection of the row of virtual first conductive portions 220 on the base substrate covers the orthographic projection of the row of virtual third active portions 118 on the base substrate.
  • the second conductive layer 3 may include a row virtual second conductive part 310 , a row virtual first reset signal line 320 , and a row virtual first initial signal line 330 , the row dummy second gate line 340, the row dummy second connection portion 350, wherein the orthographic projection of the row dummy second conductive portion 310 on the base substrate and the orthographic projection of the row dummy first conductive portion 210 on the base substrate Partially overlapping, the row dummy second conductive portion 310 can be used to form the gate electrode of the row dummy driving transistor and the second electrode of the row dummy storage capacitor, and in two adjacent repeating units in the row direction, the row dummy second conductive portion 310 Part 310 is not connected.
  • the row virtual first reset signal lines 320 may extend along the first direction X in an orthographic projection of the substrate, and in the virtual pixel driving circuits of the same row, the row virtual first reset signal lines 320 may be connected to each other.
  • the orthographic projection of the row virtual first signal line 330 on the substrate overlaps with the orthographic projection of the row virtual first active portion 420 on the substrate.
  • the row dummy second gate line 340 is connected to the row dummy second conductive portion 310 .
  • the orthographic projection of the row dummy second connection portion 350 on the base substrate may extend along the column direction and overlap with the orthographic projection of the row dummy seventh active portion on the base substrate.
  • the second active layer 4 may include a row virtual first active part 420 , a row virtual second active part 430 , and a row virtual ninth active part. part 440, wherein the orthographic projection of the row virtual first active part 420 on the substrate overlaps with the orthographic projection of the row virtual first initial signal line 330 on the substrate.
  • the third conductive layer 5 may include a row of virtual second reset signal lines 510 , and the orthographic projection of the row of virtual second reset signal lines 510 on the substrate may be Extending along the first direction
  • the third conductive part 23 may be connected to the fourth node N4 in the pixel driving circuit of the previous row by disposing the fifth bridge part 65 in the virtual pixel row.
  • the fourth conductive layer 6 may include a row of virtual third connection portions 610 and a row of virtual fourth connection portions 620 , where the row of virtual third connection portions 610
  • the row virtual first initial signal line 330 can be connected through the via hole H10, and the row virtual first reset signal line 320 can be connected through the via hole H11.
  • the row virtual third connection part 610 can also be connected to the row virtual eighth active signal line through the via hole H12.
  • the row dummy second active part 430 is connected through the via hole H13
  • the row dummy second gate line 340 is connected through the via hole H14
  • the row dummy first conductive part 220 and the row dummy third active part are connected through the via hole H15.
  • the row dummy third connection part 610 can also be connected to the first power line Vdd through the via H16, thereby connecting the row dummy first initial signal line 330, the row dummy first reset signal line 320, the row dummy eighth active The portion 120, the row dummy second active portion 430, the row dummy second gate line 340, the row dummy first conductive portion 220 and the row dummy third active portion 118 are connected to the first power line Vdd.
  • the row virtual fourth connection part 620 can be connected to the row virtual third active part 118 through the via hole H17, to the row virtual ninth active part 440 through the via hole H18, and then connected to the first row virtual third connection part 610. Power line Vdd.
  • the row dummy second conductive portion 310 in the current row dummy pixel driving circuit is in the orthographic projection of the substrate, and the row dummy third reset signal line 210 is in the substrate.
  • the front projection of the base substrate, the front projection of the row virtual second gate line 340 on the base substrate, and the front projection of the row virtual enable signal line 230 on the base substrate are all disconnected in the first fracture area M1, and the third conductive portion
  • the orthographic projection of 23 on the base substrate is located in the first fracture area M1, thereby avoiding parasitic capacitance between the third conductive part 23 and other conductive structures, and helping to provide a stable reset signal to the fourth node.
  • the display panel may also include multiple virtual pixel columns.
  • the virtual pixel columns are located between two adjacent columns of sub-pixels.
  • the virtual pixel columns include multiple columns of virtual sub-pixels.
  • the column virtual sub-pixels The pixel includes a column dummy pixel drive circuit, the column dummy pixel drive circuit includes a column dummy transistor, and the channel region of the column dummy reset transistor has a second fracture region M2 in the orthographic projection of the substrate, that is, the column dummy reset transistor in the column dummy transistor.
  • the channel region has a fracture structure, and the third reset signal line Re3 of the normal sub-pixel extends along the first direction in the orthographic projection of the base substrate and passes through the second fracture region, so that the third reset signal line Re3 does not interact with other
  • the conductive structure forms a parasitic capacitance, which can avoid or reduce signal interference to the third reset signal line Re3.
  • the first active layer 1 may include a column virtual fourth active part 130 , a column virtual seventh active part 140 , a column virtual third active part 118 , a column virtual fifth connection part 150 , a column virtual sixth connection part 160 , a column virtual seventh connection part 170 , a column virtual eighth connection part 180 , a column virtual ninth connection part 190 and a column virtual tenth connection part 191 , wherein the orthographic projection of the column virtual fifth connection portion 150 on the base substrate and the orthographic projection of the column virtual sixth connection portion 160 on the base substrate can both extend along the column direction.
  • the column virtual fifth connection portion 150 and the column virtual fifth connection portion 150 can extend along the column direction.
  • the six connection portions 160 are disposed oppositely on both sides of the column virtual third active portion 118 and are both connected to the column virtual third active portion 118 .
  • the column virtual fifth connection part 150 can connect the fifteenth active part 115 in the adjacent pixel driving circuit in the row direction, thereby connecting the column virtual fifth connection part 150 to the first power line through the fifteenth active part 115 Vdd.
  • the column dummy sixth connection part 160 can connect the fifteenth active part 115 in the adjacent pixel driving circuit in the row direction, so as to connect the column dummy through the fifteenth active part 115 in the adjacent pixel driving circuit in the row direction.
  • the sixth connection part 160 is connected to the first power line Vdd.
  • the structure of the virtual pixel driving circuit in the virtual pixel where the virtual pixel column and the virtual pixel row intersect may be different from the structure of the virtual pixel driving circuit in the virtual pixel column and the virtual pixel row.
  • the virtual seventh connection part 170 and the virtual eighth connection part 180 are located in the virtual pixel where the virtual pixel column and the virtual pixel row intersect, and the virtual seventh connection part 170 and the virtual eighth connection part 180 are on the front side of the substrate.
  • the projections may extend along the column direction, and the virtual seventh connection part 170 and the virtual eighth connection part 180 are relatively disposed on both sides of the virtual third active part 118 in the virtual pixel and are connected to the virtual third active part 118 connected.
  • Partial structures of the virtual ninth connection part 190 and part of the virtual tenth connection part 191 are located in the virtual pixel where the virtual pixel column and the virtual pixel row intersect, and the virtual ninth connection part 190 located in the virtual pixel is respectively connected with the virtual pixel.
  • the virtual seventh connection part 170 in the pixel is connected to the virtual seventh active part 119 in the adjacent row virtual pixel driving circuit, and the virtual tenth connection part 191 in the virtual pixel is connected to the virtual tenth connection part 191 in the virtual pixel.
  • the eighth connection part 180 is connected to the row dummy seventh active part 119 in the adjacent row dummy pixel driving circuit.
  • the first conductive layer 2 may include a column virtual first conductive part 220 , and the orthographic projection of the column virtual first conductive part 220 on the base substrate may cover the corresponding column.
  • the column virtual third active portion 118 is located in the column, and the column virtual first conductive portion 220 is connected to the enable signal line EM in the adjacent pixel driving circuit in the row direction, so that the virtual first conductive portion 220 is connected to the virtual first conductive portion 220 through the enable signal line.
  • the conductive part 220 provides a stable electrical signal to prevent the virtual first conductive part 220 from floating and being susceptible to static electricity or other signal interference.
  • the virtual first conductive part 220 is connected to the virtual enable signal line 230, and is further connected to the first power supply line Vdd.
  • the second conductive layer 3 may include a column virtual third conductive part 360 , and the orthographic projection of the column virtual third conductive part 360 on the base substrate may be consistent with the column.
  • the virtual first conductive portions 220 overlap in the orthographic projection portion of the base substrate, and the column virtual third conductive portions 360 can be used to connect the second conductive portions 32 in adjacent pixel driving circuit circuits.
  • the display panel may include repeating units distributed in the row and column directions.
  • One repeating unit includes a first pixel driving circuit and a second pixel driving circuit arranged in mirror symmetry.
  • the first pixel driving circuit and the row direction The second pixel driving circuit in another adjacent repeating unit is arranged adjacently.
  • the second conductive portion 32 in the first pixel driving circuit is connected to the second conductive portion 32 in the second pixel driving circuit in the other repeating repeating unit.
  • the second conductive portion 32 of the first pixel driving circuit in one repeating unit can be connected to the other through the dummy third conductive portion 360 in the dummy pixel column.
  • the second conductive portions 32 of the second pixel driving circuit in a repeating unit are connected, so that the second conductive portions 32 in two adjacent repeating units in the row direction are connected.
  • the virtual third conductive part 360 may have the same structure as the virtual third conductive part 23360 in the virtual pixel column.
  • the fourth conductive layer 6 may include a column virtual fourth conductive part 630 , and the column virtual fourth conductive part 630 may be connected to the column virtual fourth conductive part through the via H19
  • the active part 130 and the column dummy seventh active part 140 are connected to the column dummy ninth connection part 190 and the column dummy tenth connection part 191 through the via hole H20, and the first power line Vdd is connected to the column dummy connection part 191 through the via hole H21.
  • the virtual fourth conductive part 630 connects the column virtual fourth active part 130 , the column virtual seventh active part 140 , the column virtual ninth connection part 190 and the column virtual tenth connection part 191 to the first power line Vdd.
  • part of the structure of the second bridge part 62 in the adjacent pixel driving circuit may be located in the virtual pixel column, and part of the structure of the second bridge part 62 located in the virtual pixel column may be connected to the columns in the virtual pixel column through the via H22
  • the virtual fifth connection part 150 is used to connect the column virtual fifth connection part 150 to the first power line Vdd and provide a stable voltage signal for the column virtual fifth connection part 150 .
  • the partial structure of the second bridge portion 62 in the pixel driving circuit adjacent to the column virtual sixth connection portion 160 located in the virtual pixel column can be connected to the column virtual sixth connection portion 160 through the via H22 at this position. , thereby connecting the column virtual sixth connection part 160 to the first power line Vdd, and providing a stable voltage signal for the column virtual sixth connection part 160 .
  • part of the structure of the second bridge part 62 can also be located in the virtual pixel where the virtual pixel column and the virtual pixel row intersect, and this part of the structure can be connected to the corresponding virtual seventh connection part 170 through the via hole H23.
  • H24 connects the virtual third reset signal line 210 at the corresponding position, thereby connecting the virtual seventh connection part 170 and the virtual third reset signal line 210 to the first power line Vdd to provide a stable voltage signal.
  • the second bridge portion 62 in the pixel driving circuit adjacent to the virtual eighth connection portion 180 in the row direction can be connected to the virtual eighth connection portion 180 at the corresponding position through the via hole H23 at the corresponding position.
  • H24 connects the virtual third reset signal line 210 at the corresponding position to connect the virtual eighth connection part 180 to the first power line Vdd.
  • the fourth conductive layer 6 may also include a virtual fifth conductive part 640.
  • the virtual fifth conductive part 640 may be located in the virtual pixel where the virtual pixel row and the virtual pixel column intersect.
  • the virtual fifth conductive part 640 may be connected through the via H25
  • the first power line, the orthographic projection of the virtual fifth conductive part 640 on the substrate substrate may extend along the row direction and be located on the orthographic projection of the virtual third reset signal line 210 on the substrate substrate, and the virtual third conductive part 360 may be on the substrate substrate. between the orthographic projections.
  • part of the structure of the virtual fourth conductive part 630 may be located in a virtual pixel where the virtual pixel row and the virtual pixel column intersect, and the virtual fourth conductive part 630 located in the virtual pixel is connected to the virtual third conductive part 360 through the via H26 , connect the dummy first conductive part 220 through the via hole H50, so as to connect the dummy third conductive part 360 and the dummy first conductive part 220 to the first power line.
  • the fifth conductive layer 7 may include a first power supply line Vdd, which is used to provide a floating conductive structure in the virtual pixel column.
  • Vdd a first power supply line
  • the display panel may include a first insulating layer 81, a second insulating layer 82, a third insulating layer 83, a fourth insulating layer 84, a fifth insulating layer 85, a first dielectric layer 86, and a first flattening layer 87, wherein, Base substrate 80, light shielding layer, first insulating layer 81, first active layer 1, second insulating layer 82, first conductive layer 2, third insulating layer 83, second conductive layer 3, fourth insulating layer 84 , the second active layer 4, the fifth insulating layer 85, the third conductive layer 5, the first dielectric layer 86, the fourth conductive layer 6, the first planar layer 87, the fifth conductive layer 7, the second planar layer 88 Layer the settings one by one.
  • the first insulating layer 81 and the second insulating layer 82 may be silicon oxide layers, and the first dielectric layer 86 may be a silicon nitride layer.
  • the base substrate may include a glass substrate, a barrier layer, and a polyimide layer that are stacked in sequence.
  • the barrier layer may be an inorganic material.
  • the material of the first conductive layer 2 and the second conductive layer 3 may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or laminate.
  • the material of the third conductive layer 5 and the fourth conductive layer 6 may include metal materials, for example, it may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or laminate, or it may be titanium /aluminum/titanium laminate.
  • the present disclosure also provides a display device, including the display panel described in any of the above embodiments.

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Abstract

本公开提供一种显示面板，显示面板包括：第一导电层(2)、第二有源层(4)、第三导电层(5)、介电层和第四导电层(6)，第一导电层(2)包括第一导电部(21)，第二有源层(4)包括第八有源部(48)，第四导电层(6)包括第一桥接部(61)，第一桥接部(61)分别通过过孔连接第八有源部(48)和第一导电部(21)；其中，第一栅线(G1)包括第一延伸部(51)，第一延伸部(51)在衬底基板的正投影位于第一桥接部(61)在衬底基板的正投影上，第一延伸部(51)包括相对设置且与其延伸方向相同的第一侧边(511)和第二侧边(512)，第一桥接部(61)在衬底基板的正投影垂直相交于第一侧边(511)在衬底基板的正投影和第二侧边(512)在衬底基板的正投影，由此可防止介电层断裂。 (图3)

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示面板及显示装置。
背景技术
近年来，随着显示行业的迅猛发展，消费者对于显示边框的要求越来越严格，窄边框甚至零边框逐渐成为了潮流和趋势。
相关技术中，SD1层和Gate层之间的无机介质层存在断裂风险，容易引起SD1层和Gate层短接，造成显示问题。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于克服上述现有技术的不足，提供一种显示面板及显示装置。
根据本公开的一个方面，提供一种显示面板，所述显示面板包括像素驱动电路，所述像素驱动电路包括驱动晶体管、第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第一极；所述显示面板还包括：衬底基板；第一导电层，位于所述衬底基板的一侧，所述第一导电层包括：第一导电部，所述第一导电部用于形成所述驱动晶体管的栅极；第二有源层，位于所述第一导电层背离所述衬底基板的一侧，所述第二有源层包括：第二有源部，用于形成所述第二晶体管的沟道区；第八有源部，连接于所述第二有源部的一侧；第三导电层，位于所述第二有源层背离所述衬底基板的一侧，所述第三导电层包括：第一栅线，在所述衬底基板的正投影沿第一方向延伸且覆盖所述第二有源部，所述第一栅线的部分结构用于形成所述第二晶体管的顶栅，所述第八有源部在所述衬底基板的正投影和所述第一导电 部在所述衬底基板的正投影分别位于所述第一栅线在所述衬底基板的正投影的两侧；介电层，位于所述第三导电层背离所述衬底基板的一侧；第四导电层，位于所述介电层背离所述衬底基板的一侧，所述第四导电层包括：第一桥接部，分别通过过孔连接所述第八有源部和所述第一导电部；其中，第一栅线包括相对设置且与其延伸方向相同的第六侧边和第七侧边，所述第六侧边至少部分结构在所述衬底基板的正投影与所述第一桥接部在所述衬底基板的正投影垂直，所述第七侧边至少部分结构在所述衬底基板的正投影与所述第一桥接部在所述衬底基板的正投影垂直。
在本公开的一种示例性实施例中，所述第六侧边包括第一分段，所述第七侧边包括第二分段，所述第一分段在所述衬底基板的正投影与所述第一桥接部在所述衬底基板的正投影垂直，所述第二分段在所述衬底基板的正投影与所述第一桥接部在所述衬底基板的正投影垂直；所述第一分段在所述衬底基板的正投影平行于所述第二分段在所述衬底基板的正投影，或者，所述第一分段在所述衬底基板的正投影所在直线与所述第二分段在所述衬底基板的正投影所在直线相交。
在本公开的一种示例性实施例中，所述第六侧边在所述衬底基板的正投影与所述第一桥接部在所述衬底基板的正投影相交的长度为S1，所述第一分段在所述衬底基板的正投影的长度为S2，所述S2/S1大于等于0.7且小于等于1；所述第七侧边在所述衬底基板的正投影与所述第一桥接部在所述衬底基板的正投影相交的长度为S3，所述第二分段在所述衬底基板的正投影的长度为S4，S4/S3大于等于0.7且小于等于1。
在本公开的一种示例性实施例中，所述显示面板还包括：第二导电层，位于所述第一导电层和所述第二有源层之间，所述第二导电层包括：第二栅线，在所述衬底基板的正投影沿所述第一方向延伸且覆盖所述第二有源部在所述衬底基板的正投影，所述第二栅线的部分结构用于形成所述第二晶体管的底栅；其中，所述第二栅线包括相对设置且沿其延伸方向延伸的第三侧边和第四侧边，所述第一桥接部在所述衬底基板的正投影垂直相交于至少部分所述第三侧边在所述衬底基板的正投影和至少部分所述第四侧边在所述衬底基板的正投影。
在本公开的一种示例性实施例中，所述第二栅线包括第二延伸部，所述第二延伸部在所述衬底基板的正投影位于所述第一桥接部在所述衬底基板的正投影上且与所述第一延伸部在所述衬底基板的正投影交叠，所述第二延伸部包括相对设置且与其延伸方向相同的第三侧边和第四侧边；所述第三侧边在所述衬底基板的正投影位于所述第四侧边在所述衬底基板的正投影远离所述第一导电部在所述衬底基板的正投影的一侧；所述第一侧边在所述衬底基板的正投影位于所述第二侧边在所述衬底基板的正投影远离所述第一导电部在所述衬底基板的正投影的一侧；所述第三侧边上任意的第一节点在所述衬底基板的正投影与所述第一侧边在所述衬底基板的正投影在第二方向上的距离为L1，所述第一节点在所述衬底基板的正投影与所述第四侧边在所述衬底基板的正投影在第二方向上的距离为L2，所述第二方向与所述第一方向相交，L1/L2大于等于0.25且小于等于0.8；所述第四侧边上的任意第二节点在所述衬底基板的正投影与所述第二侧边在所述衬底基板的正投影在第二方向上的距离为L3，所述第二节点在所述衬底基板的正投影与所述第三侧边在所述衬底基板的正投影在第二方向上的距离为L4，L3/L4大于等于0.25且小于等于0.8。
在本公开的一种示例性实施例中，所述第一延伸部在所述衬底基板的正投影覆盖所述第三侧边在所述衬底基板的正投影，所述第二延伸部在所述衬底基板的正投影覆盖所述第二侧边在所述衬底基板的正投影；或，所述第一延伸部在所述衬底基板的正投影覆盖所述第三侧边在所述衬底基板的正投影和所述第四侧边在所述衬底基板的正投影；或，所述第二延伸部在所述衬底基板的正投影覆盖所述第一侧边在所述衬底基板的正投影和所述第二侧边在所述衬底基板的正投影；或，所述第一延伸部在所述衬底基板的正投影覆盖所述第四侧边在所述衬底基板的正投影，所述第二延伸部在所述衬底基板的正投影覆盖所述第一侧边在所述衬底基板的正投影。
在本公开的一种示例性实施例中，所述第一延伸部在所述衬底基板的正投影与所述第二延伸部在所述衬底基板的正投影的交叠区域在所述第二方向的尺寸为L5，L1/L5大于等于0.6且小于等于1，L3/L5大于等于0.6且小于等于1。
在本公开的一种示例性实施例中，所述像素驱动电路包括第五晶体管、第六晶体管，所述第五晶体管的第一极连接所述驱动晶体管的第二极，所述第六晶体管的第一极连接所述驱动晶体管的第一极；所述显示面板还包括：第一有源层，位于所述衬底基板和所述第一导电层之间，所述第一有源层包括：第五有源部，用于形成所述第五晶体管的沟道区；第六有源部，用于形成所述第六晶体管的沟道区；其中，所述第五有源部与所述第六有源部在所述第一方向上具有第六距离L6，L1/L6大于等于5％，L2/L6大于等于5％。
在本公开的一种示例性实施例中，L1大于等于1.3μm，L2大于等于1.3μm。
在本公开的一种示例性实施例中，所述第二栅线包括第二延伸部，所述第二延伸部在所述衬底基板的正投影位于所述第一桥接部在所述衬底基板的正投影上且与所述第一延伸部在所述衬底基板的正投影交叠；所述第二延伸部在所述衬底基板的正投影覆盖所述第一延伸部在所述衬底基板的正投影，且所述第二延伸部在所述衬底基板的正投影在第一方向具有第一中心线，所述第一延伸部在所述衬底基板的正投影具有第二中心线，所述第一中心线与所述第二中心线重叠；所述第二延伸部在所述衬底基板的正投影在第二方向具有第一宽度，所述第一延伸部在所述衬底基板的正投影在第二方向具有第二宽度，所述第二方向与所述第一方向相交；其中，同一位置处，所述第一宽度与所述第二宽度之比为1.5～3。
在本公开的一种示例性实施例中，所述第一栅线具有沿其延伸方向相连接的第一组成部和第二组成部，所述第一组成部在所述衬底基板的正投影在第二方向的宽度大于所述第一组成部在所述衬底基板的正投影在所述第二方向的宽度，所述第二方向与所述第一方向相交；所述第二栅线具有沿其延伸方向相连接的第三组成部和第四组成部，所述第三组成部在所述衬底基板的正投影在所述第二方向的宽度大于所述第四组成部在所述衬底基板的正投影在所述第二方向的宽度；其中，所述第一组成部在所述衬底基板的正投影、所述第三组成部在所述衬底基板的正投影均覆盖所述第二有源部在所述衬底基板的正投影，且所述第三组成部 在所述衬底基板的正投影覆盖所述第一组成部在所述衬底基板的正投影；所述第一桥接部在所述衬底基板的正投影与所述第一组成部在所述衬底基板的正投影、所述第二组成部在所述衬底基板的正投影部分交叠，且所述第一桥接部在所述衬底基板的正投影还与所述第三组成部在所述衬底基板的正投影、所述第四组成部在所述衬底基板的正投影部分交叠。
在本公开的一种示例性实施例中，所述第一栅线具有第一组成部和第二组成部，所述第一组成部在第二方向的宽度大于所述第一组成部在所述第二方向的宽度，所述第二方向与所述第一方向相交；所述第二栅线具有第三组成部和第四组成部，所述第三组成部在所述第二方向的宽度大于所述第四组成部在所述第二方向的宽度；其中，所述第一组成部在所述衬底基板的正投影、所述第三组成部在所述衬底基板的正投影均覆盖所述第二有源部在所述衬底基板的正投影，且所述第三组成部在所述衬底基板的正投影覆盖所述第一组成部在所述衬底基板的正投影；所述第一桥接部在所述衬底基板的正投影与所述第一组成部在所述衬底基板的正投影、所述第三组成部在所述衬底基板的正投影相交。
在本公开的一种示例性实施例中，所述显示面板包括沿第一方向和第二方向阵列分布的多个所述像素驱动电路，所述第一方向为行方向，所述第二方向为列方向；所述像素驱动电路用于驱动发光单元发光，所述像素驱动电路还包括对第四晶体管和第七晶体管，所述第四晶体管的第一极连接所述驱动晶体管的第二极，栅极连接第三栅线，第二极连接数据线；所述第七晶体管的第一极连接所述发光单元的第一电极，第二极连接第二初始信号线，栅极连接第三复位信号线；所述显示面板还包括：第一有源层，位于所述衬底基板和所述第一导电层之间，所述第一有源层包括：第四有源部，用于形成所述第四晶体管的沟道区；第七有源部，用于形成所述第七晶体管的沟道区；所述第一导电层还包括：所述第三栅线，在所述衬底基板的正投影沿所述第一方向延伸且覆盖所述第四有源部在所述衬底基板的正投影，所述第三栅线的部分结构用于形成所述第四晶体管的栅极；所述第三复位信号线，在所述衬底基板的正投影沿所述第一方向延伸且覆盖所述第七有源部，所述第三复位信号线的部分结构用于形成所述第七晶体管的栅极；其中，本行像素驱动电路 的第三栅线复用为上一行像素驱动电路的第三复位信号线。
在本公开的一种示例性实施例中，所述像素驱动电路还包括存储电容，所述存储电容的第一极连接所述驱动晶体管的栅极，第二极连接第一电源线；
所述第一导电部还用于形成所述存储电容的第一电极；
所述显示面板还包括：
第五导电层，位于所述第四导电层背离所述衬底基板的一侧，所述第五导电层包括：
所述第一电源线，在所述衬底基板的正投影沿所述第二方向延伸，所述第二方向与所述第一方向相交；第二导电层，位于所述第一导电层和所述第二有源层之间，所述第二导电层包括：第二导电部，所述第二导电部在所述衬底基板的正投影与所述第一导电部在所述衬底基板的正投影部分交叠，所述第二导电部用于形成所述存储电容的第二电极，所述第二导电部通过过过孔连接所述第一电源线。
在本公开的一种示例性实施例中，所述第一方向为行方向，所述第二方向为列方向；所述显示面板包括沿行列方向分布的多个重复单元，所述重复单元包括在行方向上相邻的两个所述像素驱动电路，每列所述像素驱动电路对应设置一条所述第一电源线和一个所述第二导电部；同一重复单元中，两条所述第一电源线相连接；在行方向相邻的重复单元中，相邻所述第二导电部相连接。
在本公开的一种示例性实施例中，在同一重复单元中，在行方向相邻的两个所述像素驱动电路互为镜像。
在本公开的一种示例性实施例中，所述像素驱动电路包括第五晶体管，所述第五晶体管的第一极连接所述驱动晶体管的第二极，第二极连接所述第一电源线；所述显示面板还包括：第一有源层，位于所述衬底基板和所述第一导电层之间，所述第一有源层包括：第五有源部，用于形成所述第五晶体管的沟道区；所述第一导电层还包括：使能信号线，在所述衬底基板的正投影沿所述第一方向延伸且覆盖所述第五有源部，所述使能信号线的部分结构用于形成所述第五晶体管的栅极；第五导电层，位于所述第四导电层背离所述衬底基板的一侧，所述第五导电层包 括：所述第一电源线，在所述衬底基板的正投影沿第二方向延伸，所述第二方向与所述第一方向相交；所述第四导电层还包括：第二桥接部，所述第二桥接部通过第一过孔连接所述第五晶体管的第二极，且通过另一过孔连接所述第一电源线。
在本公开的一种示例性实施例中，所述第一方向为行方向，所述第二方向为列方向；所述显示面板包括沿行列方向分布的多个重复单元，所述重复单元包括在行方向上相邻的两个所述像素驱动电路；所述第二桥接部与所述像素驱动电路一一对应设置，在行方向相邻的重复单元中，相邻所述第二桥接部相连接且共用所述第一过孔。
在本公开的一种示例性实施例中，所述显示面板还包括：第五导电层，位于所述第四导电层背离所述衬底基板的一侧，所述第五导电层包括：第一电源线，在所述衬底基板的正投影沿第二方向延伸，所述第二方向与所述第一方向相交；其中，所述第一电源线在所述衬底基板的正投影覆盖所述第一桥接部在所述衬底基板的正投影。
在本公开的一种示例性实施例中，所述第二晶体管的栅极连接第一栅线，所述第二晶体管的第二极连接所述驱动晶体管的第一极；所述第二有源层还包括：第一有源部，用于形成所述第一晶体管的沟道区；第二有源部，用于形成所述第二晶体管的沟道区；所述显示面板还包括：第二导电层，位于所述第一导电层和所述第二有源层之间，所述第二导电层包括：第二栅线，在所述衬底基板的正投影沿所述第一方向延伸且覆盖所述第二有源部在所述衬底基板的正投影，所述第二栅线的部分结构用于形成所述第二晶体管的底栅，且所述第一栅线在所述衬底基板的正投影覆盖所述第二有源部在所述衬底基板的正投影，所述第一栅线的部分结构用于形成所述第二晶体管的顶栅；第一复位信号线，在所述衬底基板的正投影沿所述第一方向延伸且覆盖所述第一有源部在所述衬底基板的正投影，所述第一复位信号线的部分结构用于形成所述第一晶体管的底栅；所述第一电源线在所述衬底基板的正投影覆盖所述第一有源部在所述衬底基板的正投影和所述第二有源部在所述衬底基板的正投影。
在本公开的一种示例性实施例中，所述第一晶体管的第二极连接第一初始信号线，所述第二晶体管的第二极连接所述驱动晶体管的第一极； 所述像素驱动电路还包括第六晶体管，所述第六晶体管的第一极连接所述驱动晶体管的第一极；所述显示面板还包括：第二导电层，位于所述第一导电层和所述第二有源层之间，所述第二导电层包括：所述第一初始信号线，在所述衬底基板的正投影沿所述第一方向延伸；第一有源层，位于所述衬底基板和所述第一导电层之间，所述第一有源层包括：第三有源部，用于形成所述驱动晶体管的沟道区；第六有源部，用于形成所述第六晶体管的沟道区；第十一有源部，连接于所述第三有源部和所述第六有源部之间；所述第二有源层还包括：第二有源部，用于形成所述第二晶体管的沟道区；第九有源部，连接于所述第二有源部和所述第八有源部之间；第十四有源部，连接于所述第二有源部远离所述第八有源部的一侧；所述第四导电层还包括：第三桥接部，连接所述第十四有源部且通过过孔连接所述第一初始信号线；第四桥接部，通过一过孔连接所述第十一有源部且通过另一过孔连接所述第十四有源部。
在本公开的一种示例性实施例中，所述显示面板包括沿第一方向和第二方向阵列分布的多个所述像素驱动电路，所述第一方向为行方向，所述第二方向为列方向；
所述显示面板包括沿行列方向分布的多个重复单元，所述重复单元包括两个所述像素驱动电路；
同一重复单元中，两个所述像素驱动电路共用所述第三桥接部。
23、根据权利要求21所述的显示面板，其中，所述像素驱动电路还包括第五晶体管、第六晶体管、第七晶体管，所述第五晶体管的第一极连接所述驱动晶体管的第二极，所述第五晶体管的第二极连接所述第一电源线，所述第六晶体管的第一极连接驱动晶体管的第一极，所述第六晶体管的第二极连接所述第七晶体管的第一极；所述显示面板还包括：第一有源层，位于所述衬底基板和所述第一导电层之间，所述第一有源层包括：第五有源部，用于形成所述第五晶体管的沟道区；第六有源部，用于形成所述第六晶体管的沟道区；第七有源部，用于形成所述第七晶体管的沟道区；所述第一导电层还包括：使能信号线，在所述衬底基板的正投影沿所述第一方向延伸且覆盖所述第五有源部和所述第六有源部，所述使能信号线的部分结构用于形成所述第五晶体管的栅极、部分结构 用于形成所述第六晶体管的栅极；第三复位信号线，在所述衬底基板的正投影沿所述第一方向延伸且覆盖所述第七有源部，所述第三复位信号线的部分结构用于形成所述第七晶体管的栅极；第二导电层，位于所述第一导电层和所述第二有源层之间，所述第二导电层包括：所述第一初始信号线，在所述衬底基板的正投影沿所述第一方向延伸；第五导电层，位于所述第四导电层背离所述衬底基板的一侧，所述第五导电层包括：所述第一电源线，在所述衬底基板的正投影沿所述第二方向延伸，所述第二方向与所述第一方向相交；所述第四导电层还包括：第二桥接部，所述第二桥接部通过过孔连接所述第五晶体管的第二极，且通过另一过孔连接所述第一电源线；其中，同一像素驱动电路中，所述第一导电部在所述衬底基板的正投影位于所述使能信号线在所述衬底基板的正投影和所述第一栅线在所述衬底基板的正投影之间；同一像素驱动电路中，所述第一栅线在所述衬底基板的正投影、所述第三复位信号线在所述衬底基板的正投影、所述第一初始信号线在所述衬底基板的正投影沿远离所述第一导电部的方向依次分布。
在本公开的一种示例性实施例中，所述第一晶体管的栅极连接第二复位信号线；所述第二有源层还包括：第一有源部，用于形成所述第一晶体管的沟道区；所述显示面板还包括：第二导电层，位于所述第一导电层和所述第二有源层之间，所述第二导电层包括：第一复位信号线，在所述衬底基板的正投影沿所述第一方向延伸且覆盖所述第一有源部在所述衬底基板的正投影，所述第一复位信号线的部分结构用于形成所述第一晶体管的底栅；所述第三导电层还包括：第二复位信号线，在所述衬底基板的正投影沿所述第一方向延伸且覆盖所述第一有源部在所述衬底基板的正投影，所述第二复位信号线的部分结构用于形成所述第一晶体管的顶栅；其中，所述第一复位信号线在所述衬底基板的正投影位于所述第一初始信号线在所述衬底基板的正投影与所述第三复位信号线在所述衬底基板的正投影之间。
在本公开的一种示例性实施例中，所述第一方向为行方向，所述第二方向为列方向；所述像素驱动电路还包括第四晶体管，所述第四晶体管的第一极连接所述驱动晶体管的第二极，第二极连接数据信号线；所 述第五导电层还包括：数据线，在所述衬底基板的正投影沿所述第二方向延伸；所述第四导电层还包括：第六桥接部，通过一过孔连接所述数据线且通过另一过孔连接所述第四晶体管的第二极；所述显示面板包括沿行列方向分布的多个重复单元，所述重复单元包括两个所述像素驱动电路，每列所述像素驱动电路对应设置一条所述第一电源线和一条所述数据线；其中，同一重复单元中，两条所述第一电源线相连接，且两条所述数据线在所述衬底基板的正投影分布于两条所述第一电源线在所述衬底基板的正投影的两侧。
在本公开的一种示例性实施例中，所述像素驱动电路还包括第四晶体管，所述第四晶体管的第一极连接所述驱动晶体管的第二极，第二极连接数据信号线；所述第一晶体管、第二晶体管为N型晶体管；所述驱动晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管为P型晶体管。
在本公开的一种示例性实施例中，所述显示面板包括沿第一方向和第二方向阵列分布的多个所述像素驱动电路，所述第一方向为行方向，所述第二方向为列方向；所述显示面板包括沿行列方向阵列分布的多个子像素，所述子像素包括所述像素驱动电路；所述显示面板还包括：第五导电层，位于所述第四导电层背离所述衬底基板的一侧，所述第五导电层包括：第一电源线，在所述衬底基板的正投影沿所述第二方向延伸；多个虚拟像素行，所述虚拟像素行位于相邻两行子像素之间，所述虚拟像素行包括多个行虚拟子像素，所述行虚拟子像素包括行虚拟像素驱动电路。
在本公开的一种示例性实施例中，所述行虚拟像素驱动电路包括行虚拟晶体管和行虚拟信号线，且所述行虚拟晶体管和所述行虚拟信号线相互连接成一整体结构，所述整体结构连接至所述第一电源线。
在本公开的一种示例性实施例中，所述显示面板包括沿第一方向和第二方向阵列分布的多个所述像素驱动电路，所述第一方向为行方向，所述第二方向为列方向；所述像素驱动电路用于驱动发光单元发光，所述像素驱动电路还包括第四晶体管、第六晶体管和第七晶体管，所述第四晶体管的第一极连接所述驱动晶体管的第二极，栅极连接第三栅线， 第二极连接数据线；所述第六晶体管的第一极连接所述驱动晶体管的第一极，第二极连接所述发光单元的第一电极；所述第七晶体管的第一极连接所述发光单元的第一电极，第二极连接第二初始信号线，栅极连接第三复位信号线；本行像素驱动电路中的第七晶体管在所述衬底基板的正投影位于所述虚拟像素行在所述衬底基板的正投影远离本行像素驱动电路中的第六晶体管在所述衬底基板的正投影的一侧；所述显示面板还包括：第一有源层，位于所述衬底基板和所述第一导电层之间，所述第一有源层包括：第四有源部，用于形成所述第四晶体管的沟道区；第六有源部，用于形成所述第六晶体管的沟道区；第七有源部，用于形成所述第七晶体管的沟道区；第三导电部，至少部分位于所述虚拟像素行所在区域，所述第三导电部在所述衬底基板的正投影沿所述第二方向延伸，所述第三导电部用于连接本行像素驱动电路中第六晶体管的第二极和本行像素驱动电路中第七晶体管的第一极；所述第一导电层还包括：所述第三栅线，在所述衬底基板的正投影沿所述第一方向延伸且覆盖所述第四有源部在所述衬底基板的正投影，所述第三栅线的部分结构用于形成所述第四晶体管的栅极；所述第三复位信号线，在所述衬底基板的正投影沿所述第一方向延伸且覆盖所述第七有源部，所述第三复位信号线的部分结构用于形成所述第七晶体管的栅极；其中，本行像素驱动电路的第三栅线复用为上一行像素驱动电路的第三复位信号线。
在本公开的一种示例性实施例中，所述行虚拟像素驱动电路还包括行虚拟存储电容，所述行虚拟信号线包括行虚拟第二初始信号线、行虚拟第三复位信号线、行虚拟栅线和行虚拟使能信号线，所述行虚拟晶体管包括行虚拟驱动晶体管和行虚拟第五晶体管，所述行虚拟第五晶体管在所述衬底基板的正投影与所述行虚拟驱动晶体管在所述衬底基板的正投影之间具有第一断口区，所述第三导电部在所述衬底基板的正投影位于所述第一断口区，且所述行虚拟存储电容的第二电极在所述衬底基板的正投影、所述行虚拟第二初始信号线在所述衬底基板的正投影、所述行虚拟第三复位信号线在所述衬底基板的正投影、所述行虚拟栅线在所述衬底基板的正投影和所述行虚拟使能信号线在所述衬底基板的正投影均在所述第一断口区断开。
在本公开的一种示例性实施例中，所述第三导电部位于所述第一导电层；所述行虚拟像素驱动电路包括行虚拟第一晶体管，所述行虚拟第一晶体管的第一极连接行虚拟驱动晶体管的栅极，第二极连接行虚拟第一初始信号线，栅极连接行虚拟第二复位信号线；所述行虚拟信号线还包括所述行虚拟第二复位信号线，所述行虚拟第二复位信号线位于所述第三导电层，所述行虚拟第二复位信号线在所述衬底基板的正投影沿所述第一方向延伸且位于所述第一断口区和上一行像素驱动电路所在区域之间；所述显示面板还包括：第五桥接部，位于所述第四导电层，所述第五桥接部分别通过过孔连接所述第三导电部和本行像素驱动电路中第六晶体管的第二极，且所述第五桥接部在所述衬底基板的正投影与所述第二复位信号线在所述衬底基板的正投影相交。
在本公开的一种示例性实施例中，所述显示面板还包括：多个虚拟像素列，所述虚拟像素列位于相邻两列子像素之间，所述虚拟像素列包括多个列虚拟子像素，所述列虚拟子像素包括列虚拟像素驱动电路，所述列虚拟像素驱动电路包括列虚拟复位晶体管的沟道区，且所述列虚拟复位晶体管的沟道区在所述衬底基板的正投影具有第二断口区；所述第一导电层还包括第三复位信号线，所述第三复位信号线在所述衬底基板的正投影沿所述第一方向延伸且穿过所述第二断口区。
在本公开的一种示例性实施例中，所述虚拟像素列还包括列虚拟存储电容和列虚拟信号线，所述列虚拟存储电容的第一电极连接所述使能信号线，所述列虚拟信号线和列所述虚拟晶体管连接为整体结构，且所述整体结构连接至所述第一电源线。
根据本公开的另一个方面，还提供一种显示装置，包括本公开任意实施例所述的显示面板。
本公开提供的显示面板，位于第四导电层的第一桥接部连接第八有源部和第一导电部，将第二晶体管T的第一极连接至驱动晶体管T的栅极，该第一桥接部在衬底基板的正投影垂直相交于第一栅线中的第一延伸部的两个侧边在衬底基板的正投影，一方面可减小位于第三导电层和第四导电层之间的介电层的应力，另一方面可使得第一桥接部位于第一栅线两侧的结构具有相同的应力环境，从而第四导电层和第三导电层之 间的介电层的应力均匀分布，由此可以降低介电层的断裂风险。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为根据本公开一种实施方式显示面板中像素驱动电路的电路结构示意图；
图2为图1中像素驱动电路一种驱动方法中各节点的时序图；
图3为根据本公开一种事实方式的显示面板的结构版图；
图4为图3中第一导电层的结构版图；
图5为图3中第二导电层的结构版图；
图6为图3中第二有源层的结构版图；
图7为图3中第三导电层的结构版图；
图8为图3中第四导电层的结构版图；
图8a为根据本公开一种实施方式的第一栅线与第一桥接部的叠层俯视图；
图8b为根据本公开另一种实施方式的第一栅线与第一桥接部的叠层俯视图；
图8c为根据本公开又一种实施方式的第一栅线与第一桥接部的叠层俯视图；
图8d为根据本公开一种实施方式的第一桥接部与第二栅线叠层的俯视图；
图9为图3中第一有源层的结构版图；
图10为图3中第五导电层的结构版图；
图11为图3中遮光层的结构版图；
图12为图3中第二导电层、第二有源层和第三导电层的叠层结构版图；
图13为图12中第二导电层、第三导电层和第四导电层的叠层结构版图；
图13a为根据本公开一种实施方式的第一栅线、第二栅线和第一桥接部的叠层俯视图；
图13b为根据本公开另一种实施方式的第一栅线、第二栅线和第一桥接部的叠层俯视图；
图13c为根据本公开又一种实施方式的第一栅线、第二栅线和第一桥接部的叠层俯视图；
图13d为根据本公开另一种实施方式的第一栅线、第二栅线和第一桥接部的叠层俯视图；
图14为图3中第一有源层和第一导电层的叠层结构版图；
图15为列方向相邻的两个像素驱动电路中第一导电层和有源层的叠层版图；
图16为图3中第二有源层和第五导电层的叠层版图；
图17为图3中第一导电层、第二导电层、第三导电层和第四导电层的叠层结构版图；
图18为两个重复单元中的第二导电层和第五导电层的叠层结构版图；
图19为两个重复单元中的第四导电层的结构版图；
图20为根据本公开一种实施方式的像素排列结构示意图；
图21为相关技术中一种显示区域的阵列栅极驱动(Gate driver On Array，GOA)负载示意图；
图22为根据本公开一种实施方式的显示区域的GOA负载示意图；
图23为图20中虚线框区域显示面板的结构版图；
图24为图23中第一导电层的结构版图；
图25为图23中第四导电层的结构版图；
图26为图23中第一导电层和第四导电层的叠层结构版图；
图27为图23中第一有源层的结构版图；
图28为图23中第二导电层的结构版图；
图29为图23中第二有源层的结构版图；
图30为图23中第三导电层的结构版图；
图31为图23中第五导电层的结构版图；
图32为图23中沿AA方向的剖视图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
图1为根据本公开一种实施方式显示面板中像素驱动电路的电路结构示意图。该像素驱动电路可以包括：第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、存储电容C。其中，第一晶体管T1的第二极连接第一初始信号端INIT1，第一极连接第一节点N1，栅极连接第一复位信号端RE1；第二晶体管T2第一极连接驱动晶体管T3的栅极，第二极连接第三节点N3，栅极连接第一栅极驱动信号端GATE1；驱动晶体管T3的栅极连接第一节点N1；第四晶体管T4的第二极连接数据信号端DATA，第一极连接驱动晶体管T3的第二极，栅极连接第二栅极驱动信号端GATE2；第五晶体管T5的第一极连接驱动晶体管T3的第二极，第二极连接第一电源端VDD，栅极连接使能信号端EM；第六晶体管T6第一极连接驱动晶体管T3的第一极，栅极连接使能信号端EM；第七晶体管T7的第二极连接第二初始信号端INIT2，第一极连接第六晶体管T6的第二极，栅极连接第二复位信号端RE2。存储电容C连接于驱动晶体管T3的栅极和第一电源端VDD之间。该像素驱动电路可以连接一发光单元OLED，用于驱动该发光单元OLED发光，发光单元OLED可以连接于第六晶体管T6的第二极和第二电源端VSS之间。其中，其中，第一晶体管T1 和第二晶体管T2可以为N型晶体管，例如，第一晶体管T1和第二晶体管T2可以为N型金属氧化物晶体管，N型金属氧化物晶体管具有较小的漏电流，从而可以避免发光阶段，节点N通过第一晶体管T1和第二晶体管T2漏电。同时，驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型晶体管，例如，驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型低温多晶体硅晶体管，P型低温多晶体硅晶体管具有较高的载流子迁移率，从而有利于实现高分辨率、高反应速度、高像素密度、高开口率的显示面板。第一初始信号端INIT1和第二初始信号端可以根据实际情况输出相同或不同电压信号。
需要说明的是，本公开各实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。
如图2所示，为图1中像素驱动电路一种驱动方法中各节点的时序图。其中，G1表示第一栅极驱动信号端GATE1的时序，G2表示第二栅极驱动信号端GATE2的时序，Re1表示第一复位信号端RE1的时序，Re2表示第二复位信号端RE2的时序，EM表示使能信号端EM的时序，Da表示数据信号端DATA的时序。该像素驱动电路的驱动方法可以包括第一复位阶段t1、补偿阶段t2，第二复位阶段t3、发光阶段t4。在第一复位阶段t1：第一复位信号端RE1输出高电平信号，第一晶体管T1导通，第一初始信号端INIT1向第一节点N1输入初始信号。在补偿阶段t2：第一栅极驱动信号端GATE1输出高电平信号，第二栅极驱动信号端GATE2输出低电平信号，第四晶体管T4、第二晶体管T2导通，同时数据信号端DATA输出驱动信号以向第二节点N2写入电压Vdata+Vth(即电压Vdata与Vth之和)，其中Vdata为驱动信号的电压，Vth为驱动晶体管T3的阈值电压。在第二复位阶段t3，第二复位信号端RE2输出低电平信号，第七晶体管T7导通，第二初始信号端INIT2向第六晶体管T6的第二极输入初始信号。发光阶段t4：使能信号端EM输出低电平信号，第六晶体管T6、第五晶体管T5导通，驱动晶体管T3在电容C存 储的电压Vdata+Vth作用下发光。
根据驱动晶体管输出电流公式I＝(μWCox/2L)(Vgs-Vth) 2，其中，μ为载流子迁移率；Cox为单位面积栅极存储电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电压。本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth) 2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。
本示例性实施例提供的显示面板可以包括沿第一方向和第二方向阵列分布的多个像素驱动电路，像素驱动电路用于驱动发光器件发光，第一方向和第二方向相交，像素驱动电路包括驱动晶体管T3和第二晶体管T2，第二晶体管T2的第一极连接驱动晶体管T3的栅极，第二极连接所述驱动晶体管T3的第一极。该像素驱动电路可以如图1所示，当然，在其他示例性实施例中，该显示面板中的像素驱动电路还可以为其他结构，例如，8T1C、9T1C等。图3为根据本公开一种事实方式的显示面板的结构版图，图4为图3中第一导电层的结构版图，图5为图3中第二导电层的结构版图，图6为图3中第二有源层的结构版图，图7为图3中第三导电层的结构版图，图8为图3中第四导电层的结构版图，如图3-8所示，该显示面板可以包括：衬底基板、第一导电层2、第二导电层3、第二有源层4、第三导电层5、介电层、第四导电层6，其中，第一导电层2，位于衬底基板的一侧，第一导电层2可包括第一导电部21，第一导电部21可用于形成驱动晶体管T3的栅极；第二有源层4位于第一导电层2背离衬底基板的一侧，第二有源层4可包括第二有源部42和第八有源部48，第二有源部42可用于形成第二晶体管T2的沟道区，第八有源部48连接于第二有源部42的一侧；第三导电层5位于第二有源层4背离衬底基板的一侧，第三导电层5可包括第一栅线G1，第一栅线G1在衬底基板的正投影沿第一方向延伸且覆盖第二有源部42，第一栅线G1的部分结构可用于形成第二晶体管T2的顶栅，第八有源部48在衬底基板的正投影和第一导电部21在衬底基板的正投影分别位于第一栅线G1在衬底基板的正投影的两侧；介电层位于第三导电层5背离衬底基板的一侧；第四导电层6位于介电层背离衬底基板的一侧，第四导电层6 可包括第一桥接部61，第一桥接部61可分别通过过孔连接第八有源部48和第一导电部21；其中，第一栅线G1可包括相对设置且与其延伸方向相同的第六侧边和第七侧边，第六侧边至少部分结构在衬底基板的正投影与第一桥接部在衬底基板的正投影垂直，第七侧边至少部分结构在衬底基板的正投影与第一桥接部在衬底基板的正投影垂直。
本示例性实施例提供的显示面板，位于第四导电层6的第一桥接部61连接第八有源部48和第一导电部21，将第二晶体管T2的第一极连接至驱动晶体管T3的栅极，该第一桥接部61在衬底基板的正投影垂直相交于第一栅线G1中的两个侧边在衬底基板的正投影，一方面可减小位于第三导电层5和第四导电层6之间的介电层的应力，另一方面可使得第一桥接部61位于第一栅线G1两侧的结构应力环境相同或相似，从而第四导电层6和第三导电层5之间的介电层的应力均匀分布，由此可以降低介电层的断裂风险。
本示例性实施例中，某一结构A沿B方向延伸是指，A可以包括主要部分和与主要部分连接的次要部分，主要部分为线、线段或条形状体，主要部分沿B方向伸展，且主要部分沿B方向伸展的长度大于次要部分沿其他方向伸展的长度。
如图3所示，本示例性实施例中，第一方向X可以为行方向，第二方向Y可以为列方向。该显示面板可以包括多个像素驱动电路，多个像素驱动电路可以包括在行方向X上相邻分布的第一像素驱动电路P1和第二像素驱动电路P2，第一像素驱动电路P1和第二像素驱动电路P2可以镜像对称设置。其中，第一像素驱动电路P1和第二像素驱动电路P2可以形成一重复单元，该显示面板可以包括在行方向X和列方向Y上阵列分布的多个重复单元。
如图7所示，本示例性实施例中，第一栅线G1可包括第六侧边56和第七侧边57，第六侧边56可包括第一分段561，第七侧边57可包括第二分段571。
图8a为根据本公开一种实施方式的第一栅线与第一桥接部的叠层俯视图，如图8a所示，第一分段561在衬底基板的正投影和第二分段571在衬底基板的正投影可以相互平行，第一桥接部61在衬底基板的正 投影与第一分段561在衬底基板的正投影和第二分段571在衬底基板的正投影均垂直。图8b为根据本公开另一种实施方式的第一栅线与第一桥接部的叠层俯视图，如图8b所示，第一分段561在衬底基板的正投影和第二分段571在衬底基板的正投影也可以不平行，即第一侧边在衬底基板的正投影的直线延伸段与第二侧边在衬底基板的正投影的直线延伸段具有交点，此时可根据第一分段561和第二分段571的具体结构来对应设置第一桥接部61，以使得第一桥接部61在衬底基板的正投影与第一分段561在衬底基板的正投影和第二分段571在衬底基板的正投影分别垂直相交。例如，第一桥接部61可包括两个组成部，一个组成部在衬底基板的正投影与第一分段561在衬底基板的正投影垂直相交，另一组成部在衬底基板的正投影与第二分段571在衬底基板的正投影垂直相交，从而第一桥接部61在衬底基板的正投影与第一分段561在衬底基板的正投影和第二分段571在衬底基板的正投影均为垂直相交，由此减小介质层应力。
可以理解的是，第六侧边56还可以包括其他分段，且其他分段在衬底基板的正投影与第一桥接部61在衬底基板的正投影可以不垂直。示例性的，图8c为根据本公开又一种实施方式的第一栅线与第一桥接部的叠层俯视图，如图8c所示，第六侧边56还可以包括第三分段，且第三分段在衬底基板的正投影与第一桥接部61在衬底基板的正投影相交但不垂直。此结构下，可将第一桥接部61在衬底基板的正投影设置为与第六侧边56的主体部分在衬底基板的正投影垂直相交，换言之，第六侧边56的主要组成部分在衬底基板的正投影与第一桥接部在衬底基板的正投影是垂直相交。继续参考图8c，本示例性实施例中，第一分段561在衬底基板的正投影的长度为S2，第六侧边56在衬底基板的正投影与第一桥接部在衬底基板的正投影相交的长度为S1＝S2+S2'，S2/S1可以设置为大于等于0.7且小于等于1，S2/S1例如可以为0.7，0.8，0.9，1等。即第六侧边56在衬底基板的正投影与第一桥接部在衬底基板的正投影相交的部分中，设置垂直相交的部分与整个交叠部分所占比例大于设定值，以满足第六侧边56与第一桥接部交叠部的主体部分在衬底基板的正投影与第一桥接部在衬底基板的正投影垂直相交，同样可以起到降低介 质层应力的作用，从而有助于防止介质层断裂。类似地，第二分段571在衬底基板的正投影的长度为S4，第七侧边57在衬底基板的正投影与第一桥接部在衬底基板的正投影相交的长度为S3＝S4+S4'，S4/S3大于等于0.7且小于等于1。
应该理解的是，本公开用语“第一”、“第二”和“第三”等仅作为标记使用，用于区别不同结构的名称，不是对其对象的数量限制，也没有顺序关系。
如图3所示，本示例性实施例中，显示面板还可以包括遮光层、第一有源层1、第二导电层3、第五导电层7，其中，衬底基板、遮光层、第一有源层1、第一导电层2、第二导电层3、第二有源层4、第三导电层5、第四导电层6、第五导电层7依次层叠设置，上述功能层之间可以设置有绝缘层。第一导电层2可以为第一栅金属层(Gate1层)，第二导电层3可以为第二栅金属层(Gate2层)，第三导电层5可以为第三栅金属层(Gate3层)，第四导电层6可以为第一金属走线层(SD1层)，第五导电层7可以为第二金属走线层(SD2层)。
图9为图3中第一有源层的结构版图，图10为图3中第五导电层的结构版图，图11为图3中遮光层的结构版图，图12为图3中第二导电层、第二有源层和第三导电层的叠层结构版图，图13为图12中第二导电层、第三导电层和第四导电层的叠层结构版图，图14为图3中第一有源层和第一导电层的叠层结构版图，图15为列方向相邻的两个像素驱动电路中第一导电层和有源层的叠层版图，图16为图3中第二有源层和第五导电层的叠层版图，图17为图3中第一导电层、第二导电层、第三导电层和第四导电层的叠层结构版图，图18为两个重复单元中的第二导电层和第五导电层的叠层结构版图，图19为两个重复单元中的第四导电层的结构版图。
本示例性实施例中，第二晶体管T2可以为氧化物晶体管，并且第二晶体管T2可以为双栅结构，如图6所示，第二有源层4可以包括第二有源部42，该第二有源部42用于形成第二晶体管T2的沟道区。如图9所示，第二导电层3可以包括第二栅线G2，该第二栅线G2可用于形成第二晶体管T2的底栅。具体而言，如图12所示，第一栅线G1在衬底基 板的正投影可以覆盖第二有源部42在衬底基板的正投影，第一栅线G1的部分结构用于形成第二晶体管T2的顶栅，第二栅线G2在衬底基板的正投影可以覆盖第二有源部42在衬底基板的正投影，第二栅线G2的部分结构可以形成第二晶体管T2的底栅。因此，本示例性实施例中的第一桥接部61在衬底基板的正投影还与第二栅线G2在衬底基板的正投影具有交叠部分。
如图3、13所示，本示例性实施例中，第一桥接部61在衬底基板的正投影可以与第二栅线G2的至少部分结构在衬底基板的正投影垂直相交。示例性的，图8d为根据本公开一种实施方式的第一桥接部与第二栅线叠层的俯视图，如图图8d所示，第二栅线G2可以包括第二延伸部33，第二延伸部33可以包括相对设置的第三侧边331和第四侧边332，第一桥接部在衬底基板的正投影可以与第三侧边331的部分分段A在衬底基板的正投影垂直相交和/或与第四侧边的部分分段B在衬底基板的正投影垂直相交。此结构同样有利于减小介电层的应力，从而降低介电层断裂风险。
可以知道的是，第二栅线G2和第一栅线G1在垂直于衬底基板平面的方向上具有一定的凸起高度，第一桥接部61需要翻过第二栅线G2和第一栅线G1形成的凸起结构将位于栅线两侧的第八有源部48和第一导电部21进行连接，即第一桥接部61在第一栅线G1的一侧形成爬坡或下坡结构，在第一栅线G1的另一侧形成下坡或爬坡结构。本公开在上述实施例的基础上可进一步对第一栅线G1和第二栅线G2的结构进行改进，以进一步降低第四导电层6与第三导电层5之间的介电层的断裂风险。
图13a为根据本公开一种实施方式的第一栅线、第二栅线和第一桥接部的叠层俯视图，如图3、13、13a所示，本示例性实施例中，在与第一桥接部61交叠的位置，第一栅线G1可以具有第一延伸部51，第一延伸部51具有相对设置的第一侧边511和第二侧边512，第二栅线G2可以具有第二延伸部33，第二延伸部33具有相对设置的第三侧边331和第四侧边332，并且第一侧边511在衬底基板的正投影位于第二侧边512在衬底基板的正投影远离第一导电部21在衬底基板的正投影的一侧，第 三侧边331在衬底基板的正投影位于第四侧边332在衬底基板的正投影远离第一导电部21在衬底基板的正投影的一侧，即第一侧边与第三侧边相邻，第二侧边与第四侧边相邻。其中，第一延伸部51在衬底基板的正投影可以为第一栅线G1在衬底基板的正投影与第一桥接部61在衬底基板的正投影交叠的部分。第二延伸部33在衬底基板的正投影可以为第二栅线G2在衬底基板的正投影与第一桥接部61在衬底基板的正投影交叠的部分。可以理解的是，第一栅线G1的其他结构、第二栅线G2的其他结构在衬底基板的正投影可以与第一桥接部61在衬底基板的正投影不垂直或者不相交。
如图3、13、13a所示，本示例性实施例中，第二延伸部33在衬底基板的正投影可以完全覆盖第一延伸部51在衬底基板的正投影，并且第一侧边511与第三侧边331的距离以及第二侧边512与第四侧边的距离332均大于零，相当于在第二方向Y上第二延伸部33在第一延伸部51的两侧均有延伸段，由此第二栅线G2可对第一栅线G1形成包边结构。在此基础上，可增加第二延伸部33的延伸段在列方向的宽度，一方面降低第二延伸部33与第一延伸部51之间的坡度，另一方面可以使得第二延伸部33的坡度和第一延伸部51的坡度间隔一定的距离，这样第一桥接部61在第二延伸部33和第一延伸部51的两侧形成的爬坡结构，一方面可减小介电层的应力，另一方面介电层的应力能够被及时释放，因此可有效降低介电层的断裂风险。示例性的，如图13a所示，第三侧边331上任意的第一节点在衬底基板的正投影与第一侧边511在衬底基板的正投影在第二方向Y上的距离为L1，第一节点在衬底基板的正投影与第四侧边332在衬底基板的正投影在第二方向Y上的距离为L2，L1/L2可设置为大于等于0.25且小于等于0.8，例如可以为0.25，0.3，0.35，0.4，0.45，0.5，0.55，0.6，0.65，0.7，0.75，0.8等，以增加第三侧边在第二方向上超出的第一侧边的延伸段的长度，起到减小介质层应力且及时释放介质层应力的作用。同样地，第二延伸部33的第四侧边332可以与第一延伸部51的第二侧边512具有类似结构，第四侧边332上的任意第二节点在衬底基板的正投影与第二侧边512在衬底基板的正投影在第二方向Y上的距离为L3，第二节点在衬底基板的正投影与第三侧边在衬底基 板的正投影在第二方向Y上的距离为L4，L3/L4可设置为大于等于0.25且小于等于0.8，例如可以为0.25，0.3，0.35，0.4，0.45，0.5，0.55，0.6，0.65，0.7，0.75，0.8等。
如图13a所示，本示例性实施例中，第一延伸部51在衬底基板的正投影与第二延伸部33在衬底基板的正投影的交叠区域在第二方向Y的宽度为L5，其中，L1/L5可以设置为0.6～1，例如可以为0.6,0.65,0.7,0.75,0.8,0.85,0.9,0.95,1等。类似地，L3/L5可以设置为0.6～1，例如可以为0.6,0.65,0.7,0.75,0.8,0.85,0.9,0.95,1等。通过增加第一延伸部51在衬底基板的正投影与第二延伸部33在衬底基板的正投影的交叠区域在列向的宽度，可以增加第一延伸部51两侧的坡度的间隔距离，从而介电层在第一延伸部51的一侧上坡后，可以有一定的缓冲时间再在第一延伸部51的另一侧下坡，介电层的应力得以减小且可以被释放，因而可以进一步降低介电层的断裂风险。
如图13a所示，在其他示例性实施例中，第二延伸部33在衬底基板的正投影可以覆盖第一延伸部51在衬底基板的正投影，且第二延伸部33在衬底基板的正投影在第一方向X具有第一中心线，第一延伸部51在衬底基板的正投影具有第二中心线，第一中心线与第二中心线重叠，即第一延伸部51在衬底基板的正投影可以居中分布于第二延伸部33在衬底基板的正投影内。第二延伸部33在衬底基板的正投影在第二方向Y具有第一宽度，第一延伸部51在衬底基板的正投影在第二方向Y具有第二宽度，同一位置处，第一宽度与第二宽度之比可以为1.5～3，例如为1.5，1.7，1.8，2.0，2.2，2.4，2.6，2.8，3.0等。通过增加第二延伸部33在第二方向Y的宽度，可增加第一延伸部51在衬底基板的正投影的边界与同一侧的第二延伸部33在衬底基板的正投影的边界之间的距离，从而使得第二延伸部33形成的凸起结构与第一延伸部51形成的凸起结构之间具有一定长度的平缓过渡段，即介电层在第二延伸部33的一侧爬坡后会先进行一定距离的平缓过渡后再爬越第一延伸部51的凸起坡，从而一方面可以减小介电层的应力，另一方面介电层的应力能够被及时释放，因此可降低第三导电层5和第四导电层6之间的介电层发生断裂的风险。
本示例性实施例中所述的同一位置可以理解为，第一延伸部51的一个侧边上的某一点在衬底基板的正投影沿第二方向Y向另一侧边在衬底基板的正投影作线段，得到第一线段，第二延伸部的一个侧边上的一点在衬底基板的正投影沿第二方向Y向另一侧边在衬底基板的正投影作线段，得到第二线段，第一线段所在直线与第二线段所在直线重合。
如图13所示，在其他示例性实施例中，第二延伸部33在衬底基板的正投影可以覆盖第一延伸部51在衬底基板的正投影的一个侧边而不覆盖另一侧边，或者，第一延伸部51在衬底基板的正投影可以覆盖第二延伸部33在衬底基板的正投影的一个侧边而不覆盖另一侧边。示例性的，图13b为根据本公开另一种实施方式的第一栅线、第二栅线和第一桥接部的叠层俯视图，如图13b所示，第一延伸部51具有相对设置的第一侧边511和第二侧边512，第二延伸部33具有相对设置的第三侧边331和第四侧边332，并且第一侧边511与第三侧边331相邻，第二侧边512与第四侧边332相邻。第二延伸部33在衬底基板的正投影在第二方向Y具有第一宽度d1，第一延伸部51在衬底基板的正投影在第二方向Y具有第二宽度d2；第一侧边511与第三侧边331相邻且在第二方向Y具有第一距离L1，第二侧边512与第四侧边332相邻且在第二方向Y具有第二距离L2；第二延伸部33在衬底基板的正投影可以覆盖第一侧边511，且第一延伸部51在衬底基板的正投影可以覆盖第四侧边332。此结构下，同样可以通过增加第一距离L1和第二距离L2来降低介电层的爬坡难度，使得第四导电层6与第三导电层5之间的介电层的应力可以被及时释放，从而降低介电层的断裂风险。示例性的，第一距离L1与同一位置处的第二宽度d2之比可以为0.25～0.8，例如可以为0.25，0.3，0.35，0.4，0.45，0.5，0.55，0.6，0.65，0.7，0.75，0.8等。类似地，第二距离L2与第二宽度d2之比可以为0.25～0.8，例如可以为0.25，0.3，0.35，0.4，0.45，0.5，0.55，0.6，0.65，0.7，0.75，0.8等。
本示例性实施例中，某一延伸部在第二方向Y的宽度可以理解为，该延伸部的一个侧边的任意一点在衬底基板的正投影与另一侧边在衬底基板的正投影在第二方向Y上的距离。
应该理解的是，第一栅线G1在衬底基板的正投影、第二栅线G2在 衬底基板的正投影均与列方向上相邻的其他结构在衬底基板的正投影不交叠，即本公开在对第一栅线G1中的第一延伸部51和/或第二栅线G2中的第二延伸部33在列方向的宽度进行加宽设置后，不会挤占列方向的其他结构的空间。示例性的，在上述实施例的基础上，第一距离L1可设置为大于等于1.3μm，例如可以为1.3μm，1.4μm，1.5μm，1.6μm，1.8μm等。同样地，第二距离L2可设置为大于等于1.3μm，例如可以为1.3μm，1.4μm，1.5μm，1.6μm，1.8μm等。此外，应该理解的是，在像素空间允许的情况下，可增加第一栅线G1中的第一延伸部51在衬底基板的正投影的边界与第二栅线G2中的第二延伸部33在衬底基板的正投影的边界之间的距离。示例性的，如图9所示，第一有源层1可以包括第五有源部15和第六有源部16，第五有源部15可用于形成第五晶体管T5的沟道区，第六有源部16可用于形成第六晶体管T6的沟道区，其中，第五有源部15在衬底基板的正投影与第六有源部16在衬底基板的正投影在第一方向X上可具有第六距离L6，第一距离L1与第六距离L6之比可设置为大于等于5％，例如可以为5％，6％，7％，8％等；同样地，第二距离L2与第六距离L6之比可设置为大于等于5％，例如可以为5％，6％，7％，8％等。具体可根据像素尺寸进行设定。本示例性实施例中，第五有源部15在衬底基板的正投影与第六有源部16在衬底基板的正投影在第一方向X上的距离可以理解为，第五有源部15在衬底基板的正投影远离本像素驱动电路中的第三有源部在衬底基板的正投影的侧边与第六有源部16在衬底基板的正投影远离本像素驱动电路中的第三有源部在衬底基板的正投影的侧边之间的距离，即两个有源部在衬底基板的正投影的外侧边边界之间的距离。
如图12所示，本示例性实施例中，第一栅线G1可以具有第一组成部52和第二组成部53，第一组成部52在第二方向Y的宽度大于第二组成部53在第二方向Y的宽度，该第一组成部52在衬底基板的正投影可以覆盖第二有源部42在衬底基板的正投影，形成第二晶体管T2的底栅。同样地，第二栅线G2可具有第三组成部34和第四组成部35，第三组成部34在第二方向Y的宽度可大于第四组成部35在第二方向Y的宽度，该第三组成部34在衬底基板的正投影可以覆盖第二有源部42在衬底基 板的正投影，形成第二晶体管T2的顶栅。同时，第三组成部34在衬底基板的正投影可以覆盖第一组成部52在衬底基板的正投影。
图13c为根据本公开又一种实施方式的第一栅线、第二栅线和第一桥接部的叠层俯视图，如图13c所示，本示例性实施例中，位于第四导电层6的第一桥接部61在衬底基板的正投影可以与第一组成部52在衬底基板的正投影、第二组成部53在衬底基板的正投影部分交叠，并且第一桥接部61在衬底基板的正投影还可以与第三组成部34在衬底基板的正投影、第四组成部35在衬底基板的正投影部分交叠。
如图13a所示，在其他示例性实施例中，第一桥接部61在衬底基板的正投影可以与第一组成部52在衬底基板的正投影、第三组成部34在衬底基板的正投影部分交叠，且与第二组成部53在衬底基板的正投影、第四组成部35在衬底基板的正投影不交叠。即第一桥接部61在衬底基板的正投影仅与第一栅线G1和第二栅线G2在列方向的加宽部分在衬底基板的正投影存在交叠，而与第一栅线G1和第二栅线G2未加宽的部分在衬底基板的正投影不交叠。
图13d为根据本公开另一种实施方式的第一栅线、第二栅线和第一桥接部的叠层俯视图，如图13d所示，在其他示例性实施例中，第一桥接部61在衬底基板的正投影可以与第二组成部53在衬底基板的正投影、第四组成部35在衬底基板的正投影部分交叠，且与第一组成部52在衬底基板的正投影、第三组成部34在衬底基板的正投影不交叠，即第一桥接部61在衬底基板的正投影仅与第一栅线G1和第二栅线G2在列方向的未加宽部分在衬底基板的正投影存在交叠，而与第一栅线G1和第二栅线G2加宽的部分在衬底基板的正投影不交叠。
如图11所示，本示例性实施例中，遮光层可以包括在行方向X和列方向Y上分布的多个遮光部10，相邻遮光部10之间可以相互连接。遮光层可以为导体结构，例如，遮光层可以为遮光金属层。
如图9所示，本示例性实施例中，第一有源层1除了可以包括第五有源部15和第六有源部16外，还可以包括第三有源部13、第四有源部14和第七有源部17，其中，第三有源部13可用于形成驱动晶体管T3的沟道区，第四有源部14可用于形成第四晶体管T4的沟道区，第七有 源部17可用于形成第七晶体管T7的沟道区。此外，第一有源层1还可以包括第九有源部19、第十一有源部111、第十二有源部112、第十三有源部113、第十五有源部115、第十六有源部116，其中，第九有源部19连接于第七有源部17远离上一行像素驱动电路中第四节点的一侧，用于形成第七晶体管T7的第二极。第十一有源部111连接于第三有源部13和第六有源部16之间，该第十一有源部111形成图1中的第三节点N3，将第六晶体管T6的第一极连接至驱动晶体管T3的第一极。第十二有源部112连接于第三有源部13和第四有源部14、第五有源部15之间，该第十二有源部112形成图1中的第二节点N2，将第四晶体管T4的第一极、第五晶体管T5的第一极连接至驱动晶体管T3的第二极。第十三有源部113连接于第六有源部16和第七有源部17之间，第十三有源部113用于形成图1中的第四节点N4，将第六晶体管T6的第二极与第七晶体管T7的第一极进行连接。需要注意的是，本示例性实施例中，本行像素驱动的第七有源部17位于下一行像素驱动电路中，因此，第十三有源部113实质上是位于本行像素驱动电路和下一行像素驱动电路之间。第十五有源部115连接于第五有源部15远离第十二有源部112的一侧，形成第五晶体管T5的第二极，该第十五有源部115可通过过孔H1连接位于第四导电层6的第二桥接部62，以通过该第二桥接部62将第五晶体管T5的第二极连接至第一电源线Vdd。第十六有源部116连接于第四有源部14远离第十二有源部112的一侧，形成第四晶体管T4的第二极，该第十六有源部116可通过过孔H6连接位于第四导电层6的第六桥接部66，以通过该第六桥接部66将第四晶体管T4的第二极连接至数据线Data。第一有源层11可以由多晶硅半导体材料形成，相应的，本公开显示面板中的晶体管可以为P型低温多晶硅薄膜晶体管。
如图4所示，本示例性实施例中，第一导电层2中的第一导电部21在衬底基板的正投影可覆盖第三有源部13在衬底基板的正投影，第一导电部21可用于形成驱动晶体管T3的栅极和存储电容C的第一电极。第一导电层2还可以包括使能信号线EM、第三复位信号线Re3和第三栅线G3，其中，使能信号线EM可用于提供图1中的使能信号端EM，使能信号线EM在衬底基板的正投影可以沿第一方向X延伸且覆盖第五有 源部15和第六有源部16，使能信号线EM的部分结构用于形成第五晶体管T5的栅极、部分结构用于形成第六晶体管T6的栅极。第三栅线G3可用于提供图1中的第二栅极驱动信号端GATE2，该第三栅线G3在衬底基板的正投影沿第一方向X延伸且覆盖第四有源部14在衬底基板的正投影，第三栅线G3的部分结构用于形成第四晶体管T4的栅极，向第四晶体管T4的栅极提供第二栅极驱动信号。第三复位信号线Re3可用于提供图1中的第二复位信号端Re1，第三复位信号线Re3在衬底基板的正投影可以沿第一方向X延伸且覆盖第七有源部17，第三复位信号线Re3的部分结构用于形成第七晶体管T7的栅极，向第七晶体管T7的栅极提供第二复位信号。如图15所示，本示例性实施例中，本行像素驱动电路的第三栅线G3可复用为上一行像素驱动电路的第三复位信号线Re3。该设置可以提高像素驱动电路的集成度，降低像素驱动电路的布图面积。同时，第三复位信号线Re3在衬底基板的正投影可以覆盖第八有源部48在衬底基板的正投影，以形成图1中的第一节点N1。
本示例性实施例中，显示面板可以以第一导电层2为掩膜对有源层进行导体化处理，即被第一导电层2覆盖的有源层形成晶体管的沟道区，未被第一导电层2覆盖的区域形成导体结构。
应该理解的是，本示例性实施例中所述的某一结构A在衬底基板的正投影覆盖另一结构B在衬底基板的正投影可以理解为，B在衬底基板平面的投影的轮廓完全位于A在同一平面内投影的轮廓的内部。
如图5、14所示，本示例性实施例中，第二导电层3可以包括第一初始信号线Vinit1、第一复位信号线Re1、第二栅线G2、第二导电部32，其中，第一初始信号线Vinit1可用于提供图1中的第一初始信号端INIT1，第一初始信号线Vinit1在衬底基板的正投影可以沿第一方向X延伸，第一初始信号线Vinit1可通过第四导电层中的第三桥接部63连接位于第二有源层4中的第十四有源部414，使得第一晶体管T1的第二极连接第一初始信号线Vinit1。第一复位信号线Re1可用于提供图1中的第一复位信号端RE1，第一复位信号线Re1在衬底基板的正投影可以沿第一方向X延伸且覆盖第一有源部41在衬底基板的正投影，第一复位信号线Re1的部分结构用于形成第一晶体管T1的底栅。第二栅线G2可用于提供图 1中的第一栅极驱动信号端GATE1，第二栅线G2在衬底基板的正投影可以沿第一方向X延伸且覆盖第二有源部42在衬底基板的正投影，第二栅线G2的部分结构用于形成第二晶体管T2的底栅。第二导电部32在衬底基板的正投影与第一导电部21在衬底基板的正投影部分交叠，第二导电部32可用于形成存储电容C的第二电极，第二导电部32可通过过孔H2连接位于第五导电层7的第一电源线Vdd，以使得存储电容C的第二电极连接至第一电源线Vdd。
如图6所示，本示例性实施例中，第二有源层4中的第八有源部48可用于形成图1中的第一节点N1，第八有源部48一方面连接第一晶体管T1的第一极和第二晶体管T2的第一极，将第一晶体管T1的第一极和第二晶体管T2的第一极连接至第一节点N1，同时，第八有源部48可通过过孔H27连接位于第四导电层6的第一桥接部61，通过第一桥接部61通过过孔H43将第一节点N1连接至驱动晶体管T3的栅极。第二有源层4还可以包括第一有源部41、第十有源部410、第十四有源部414，其中，第一有源部41可用于形成第一晶体管T1的沟道区，第八有源部48将第二晶体管T2的第一极连接至第一节点N1。第十有源部410连接于第二有源部42远离第八有源部48的一侧，该第十有源部410可通过过孔H5连接位于第四导电层6的第四桥接部64，以通过第四桥接部64将第二晶体管T2的第二极连接至第三节点N3。第十四有源部414连接于第一有源部41远离第八有源部48的一端，同时，第十四有源部414可通过过孔H3连接位于第四导电层6的第三桥接部63，通过第三桥接部63将第一晶体管T1的第二极连接至第二导电层3的第一初始信号线Vinit1。第二有源层4可以由氧化铟镓锌形成，相应的，第一晶体管T1、第二晶体管T2可以为N型的金属氧化物薄膜晶体管。
如图7所示，本示例性实施例中，第三导电层5可以包括第二复位信号线Re2和第一栅线G1，其中，第二复位信号线Re2在衬底基板的正投影可以沿第一方向X延伸且覆盖第一有源部41在衬底基板的正投影，第二复位信号线Re2的部分结构用于形成第一晶体管T1的顶栅。第一栅线G1在衬底基板的正投影可以沿第一方向X延伸且覆盖第二有源部42在衬底基板的正投影，第一栅线G1的部分结构用于形成第二晶 体管T2的顶栅。此外，该显示面板可以利用第三导电层5为掩膜对第二有源层4进行导体化处理，即第二有源层4中被第三导电层5覆盖的区域可以形成晶体管的沟道区，第二有源层4中未被第三导电层5覆盖的区域形成导体结构。
如图8所示，本示例性实施例中，第四导电层6中的第一桥接部61可以包括第一子连接部611、第二子连接部612和第三子连接部613，第一子连接部611连接于第二子连接部612和第三子连接部613之间，第一子连接部611在衬底基板的正投影可以与第一栅线G1中第一延伸部51的侧边在衬底基板的正投影垂直相交。第四导电层6还可以包括第二桥接部62、第三桥接部63、第四桥接部64、第六桥接部66，其中，第二桥接部62可通过第一过孔H1连接第十五有源部115，并且第二桥接部62还可通过另一过孔H2连接第五导电层7的第一电源线Vdd，从而将第五晶体管T5的第二极连接至第一电源线Vdd。此外，第二桥接部62还可以通过过孔H28连接第二导电部32，从而将存储电容C的第二电极连接至第一电源线Vdd。第三桥接部63在衬底基板的正投影可以沿第一方向X延伸，该第三桥接部63可通过过孔H8连接第一初始信号线Vinit1，并通过过孔H3连接第十四有源部414，从而通过该第三桥接部63将第一晶体管T1的第二极连接至第一初始信号线Vinit1。第四桥接部64可通过过孔H4连接第十一有源部111且通过过孔H5连接第十有源部410，从而将第二晶体管T2的第二极连接至第三节点。第六桥接部66可通过过孔H7连接位于第五导电层7的数据线Data且通过过孔H6连接第十六有源部116，以将第四晶体管T4的第二极连接至数据线Data。此外，第四导电层6还可以包括第二初始信号线Vinit2，第二初始信号线Vinit2可用于提供图1中的第二初始信号端INIT2，第二初始信号线Vinit2的部分结构进行弯折设置，以避让第一桥接部61，并且与行方向上相邻的像素驱动电路中的第二初始信号线Vinit2连接，第二初始信号线Vinit2可通过过孔H9连接第九有源部19，从而将第七晶体管T7的第二极连接至第二初始信号线Vinit2。本示例性实施例中，第一初始信号线Vinit1用于提供第一初始化信号，第二初始信号线Vinit2用于提供第二初始化信号，第一初始化信号与第二初始化信号可以不相等，因此， 该像素驱动电路可以根据实际需求向第一节点N1和发光器件的第一电极提供不同的初始化信号。例如，可以将第一初始化信号的有效电平电压设置为-3V，将第二初始化信号的有效电平电压设置为-4V，可以确保显示屏幕在黑态下具有低亮度，改善画面显示效果。
如图10所示，本示例性实施例中，第五导电层7可包括第一电源线Vdd和数据线Data，第一电源线Vdd在衬底基板的正投影、数据线Data在衬底基板的正投影均可以沿第二方向Y延伸，其中，第一电源线Vdd可用于提供图1中的第一电源端VDD，第一电源线Vdd可通过过孔H2连接位于第四导电层6的第二桥接部62，从而通过该第二桥接部62将第五晶体管T5的第二极以及存储电容C的第二极连接第一电源线Vdd。数据线Data可用于提供图1中的数据信号端DATA，数据线Data可通过过孔H7连接第四导电层6的第六桥接部66，从而通过该第六桥接部66将第四晶体管T4的第二极连接数据线Data。
本示例性实施例中，某一结构A沿B方向延伸是指，A可以包括主要部分和与主要部分连接的次要部分，主要部分为线、线段或条形状体，主要部分沿B方向伸展，且主要部分沿B方向伸展的长度大于次要部分沿其他方向伸展的长度。
如图16所示，本示例性实施例中，第一电源线Vdd在衬底基板的正投影可以覆盖第八有源部48在衬底基板的正投影，从而第一电源线Vdd可以对第一节点进行屏蔽稳压，可防止电路中的静电或其他信号对第一节点的干扰，由此减弱串扰现象，进一步提高显示均一性。进一步的，如图16所示，第一电源线Vdd在衬底基板的正投影可以覆盖第二有源层4的其他结构在衬底基板的正投影，即通过第一电源线Vdd对第二有源层4进行屏蔽，屏蔽掉其他信号对第二有源层4的干扰，从而提高第二有源层4的稳定性。
如图17所示，本示例性实施例中，同一像素驱动电路中，第一导电部21在衬底基板的正投影可以位于使能信号线EM在衬底基板的正投影和第一栅线G1在衬底基板的正投影之间，并且同一像素驱动电路中，第一栅线G1在衬底基板的正投影、第三复位信号线Re3在衬底基板的正投影、第一复位信号线Re1在衬底基板的正投影、第一初始信号线 Vinit1在衬底基板的正投影可以沿远离第一导电部21的方向依次分布。此外，第一栅线G1在衬底基板的正投影与第二栅线G2在衬底基板的正投影可以部分交叠，第一复位信号线Re1在衬底基板的正投影和第二复位信号线Re2在衬底基板的正投影可以部分交叠。如图17所示，第二初始信号线Vinit2可以包括第一信号线延伸部Vinit2-1、第二信号线延伸部Vinit2-2和第三信号线延伸部Vinit2-3，第一信号线延伸部Vinit2-1在衬底基板的正投影可以沿第一方向X延伸且位于第三复位信号线Re3在衬底基板的正投影和第一栅线G1在衬底基板的正投影之间，第二信号线延伸部Vinit2-2在衬底基板的正投影可以沿第二方向Y延伸，第三信号线延伸部Vinit2-3在衬底基板的正投影可以沿第一方向X延伸且位于第三复位信号线Re3在衬底基板的正投影和第一复位信号线Re1在衬底基板的正投影之间。
如图3所示，本示例性实施例中，多个像素驱动电路中可以包括在行方向X上相邻分布的第一像素驱动电路P1和第二像素驱动电路P2，第一像素驱动电路P1和第二像素驱动电路P2可以镜像对称设置。其中，第一像素驱动电路P1和第二像素驱动电路P2可以形成一重复单元Q，该显示面板可以包括在行方向X和列方向Y上阵列分布的多个重复单元Q。并且在行方向上相邻的两个重复单元Q中，一个重复单元Q中的第一像素驱动电路P1与相邻的另一重复单元Q中的第二像素驱动电路P2相邻设置，一个重复单元Q中的第二像素驱动电路P2与另一重复单元Q中的第一像素驱动电路P1相邻设置。
如图18所示，本示例性实施例中，在一个重复单元Q中，第一像素驱动电路P1和第二像素驱动电路P2为镜像对称设置，并且第一像素驱动电路P1中的第一电源线Vdd和第二像素驱动电路P2中的第一电源线Vdd可以连接为一整体，同时第二导电部32可以不连接，而在行方向上相邻的两个重复单元Q中，第一像素驱动电路P1中的第一电源线Vdd与相邻重复单元Q中的第二像素驱动电路P2中的第一电源线Vdd可以不连接，且第一像素驱动电路P1中的第二导电部32和相邻重复单元Q中的第二像素驱动电路P2中的第二导电部32相连接，从而电源线VDD和第二导电部32可以形成网格结构，该网格结构的电源线可以降 低其上电源信号的压降。此外，如图18所示，同一重复单元Q中，第一像素驱动电路P1中的数据线Data和第二像素驱动电路P2中的数据线Data不连接，且两条数据线Data分布于两条第一电源线Vdd的两侧。
如图19所示，本示例性实施例中，在行方向相邻的两个重复单元Q中，第一像素驱动电路P1中第二桥接部62和相邻重复单元Q中第二像素驱动中的第二桥接部62可以相互连接，并且第一像素驱动电路P1和相邻重复单元Q中的第二像素驱动电路P2可以共用一个第一过孔H1，两个子像素共用一个第一过孔H1，可以节省子像素的占用空间，有利于提高对显示面板的空间利用率。
如图19所示，本示例性实施例中，在一个重复单元Q中，第一像素驱动电路P1和第二像素驱动电路P2可以共用一个第三桥接部63，从而节省子像素的占用空间，有利于提高对显示面板的空间利用率。
近年来，随着显示行业的迅猛发展，消费者对于显示边框的要求越来越严格，窄边框甚至零边框逐渐成为了潮流和趋势，将扇出(Fanout)走线压缩到有效显示(Active Area，AA)区内也已经不再是概念，而是成为了现实。有一种将扇出走线放入有效显示区内的方法是将有效显示区的像素通过纵向压缩，如图20所示，在位于有效显示区靠近边框区域一侧的GOP(Gate On Panel)区采用密排的压缩后的像素，而在有效显示区内的非GOP区采用压缩后的像素插入虚拟(Dummy)像素的方式排列，在图20中，P表示正常子像素，H表示插入的虚拟像素行，V表示插入的虚拟像素列。
但是，随之而来的问题是，有效显示区内没有插虚拟像素行的区域和插虚拟像素行的区域的阵列栅极驱动(Gate driver On Array，GOA)信号的负载(Loading)会有差别，如图21示，如果继续采用本行的扫描信号线Gate驱动本行第七晶体管T7，在没有插虚拟像素行的区域，一行GOA驱动一行扫描信号线Gate和一行复位信号线Reset，但是在插虚拟像素行的区域，一行GOA驱动一行扫描信号线Gate和两行复位信号线Reset，这就说明插虚拟像素行的区域的GOA比没有插虚拟像素行的区域的GOA的负载增加一行，这对于显示是非常不利的。这是因为， 插虚拟像素行的区域的GOA负载较大，会导致其充电时间和没有插虚拟像素行的区域的充电时间有差别，从而使得显示面板的显示效果较差。
本公开提供的显示面板通过对版图结构进行改进还可以解决上述问题。图23为图20中虚线框区域显示面板的结构版图，图24为图23中第一导电层的结构版图，图25为图23中第四导电层的结构版图，图26为图23中第一导电层和第四导电层的叠层结构版图，图27为图23中第一有源层的结构版图，图28为图23中第二导电层的结构版图，图29为图23中第二有源层的结构版图，图30为图23中第三导电层的结构版图，图31为图23中第五导电层的结构版图；该显示面板可以包括图3所示显示面板的所有结构。
如图23、24所示，本示例性实施例中，显示面板还可以包括多个虚拟像素行，虚拟像素行可以位于相邻两行子像素之间，虚拟像素行上一行像素驱动电路中的第七晶体管在衬底基板的正投影位于虚拟像素驱动电路下一行像素驱动电路在衬底基板的正投影所在区域。虚拟像素行可以包括多个虚拟像素驱动电路，虚拟像素驱动电路可以包括虚拟晶体管和虚拟信号线，虚拟晶体管和虚拟信号线相互连接为一个整体结构，并且该整体结构连接至第一电源线。进一步的，虚拟像素行可以包括第三导电部23，该第三导电部23在衬底基板的正投影可以沿第二方向Y延伸且至少部分位于虚拟像素行所在区域，第三导电部23可用于连接虚拟像素行上一行像素驱动电路中的第六晶体管T6的第二极和虚拟像素行下一行像素驱动电路中第七晶体管T7的第一极。示例性的，该第三导电部23可以位于第一导电层2，第三导电部23的一端可通过过孔连接位于第四导电层6的第七桥接部67，该第七桥接部67连接下一行像素驱动电路中的第四节点N4，从而通过该第七桥接部67将第三导电部23与下一行像素驱动电路的第四节点相连接。第三导电部23的另一端与上一行像素驱动电路中的第四节点N4相连接，从而通过该第三导电部23将虚拟像素行的下一行的第七晶体管T7的第一极与虚拟像素行上一行的第六晶体管T6的第二极相连接，此时的GOA负载可以如图22所示，可以看出，在插入虚拟像素行行的两行像素驱动电路中，虚拟像素行上一行的正常像素中连接OLED的第四节点N4依然是通过虚拟像素行下 一行正常像素的第七晶体管T7进行初始化，使得每一行的P-Gate GOA驱动一行Gate信号，实现了跨虚拟像素行区域和正常区域设计的高度一致性，从而在第四晶体管T4和第七晶体管T7共用一个Gate行信号的情况下，避免了跨虚拟像素行P-Gate GOA loading增大一倍的问题，从而解决了显示异常的问题。
本示例性实施例中，虚拟像素行所在区域可以理解为虚拟像素行中的虚拟晶体管在所述衬底基板的正投影、虚拟信号线在所述衬底基板的正投影以及连接所述虚拟晶体管和所述虚拟信号线的导电结构在所述衬底基板的正投影共同覆盖的区域。如图23、24、25所示，本示例性实施例中，第三导电部23可以位于第一导电层2，即靠近衬底基板的底层金属层，这样可以减小或削弱该金属线与阳极的金属的寄生电容。在此基础上，如图26所示，显示面板还可以包括位于第四导电层6的第五桥接部65，该第五桥接部65位于虚拟像素行，第五桥接部65可通过过孔H40连接虚拟像素行上一行像素驱电路中的第四节点N4，且通过过孔H连接第三导电部23，从而通过第三导电部23、第五桥接部65和第七桥接部67的配合将虚拟像素行下一行的第四节点连接至虚拟像素像素行上一行的第四节点。当然，在其他示例性实施例中，该第三导电层5也可以位于第二导电层3或第三导电层5或第四导电层6或第五导电层7。此外，本示例性实施例中，在虚拟像素行中，虚拟信号线在衬底基板的正投影沿第一方向X延伸，且与第三导电部23在衬底基板的正投影不交叠，这样可防止信号线与第三导电部23产生寄生电容，有助于通过第三导电部23向第四节点提供稳定的复位信号。
如图27所示，本示例性实施例中，虚拟像素行中，第一有源层1可包括行虚拟第三有源部118、行虚拟第七有源部119、行虚拟第八有源部120。行虚拟第七有源部119在衬底基板的正投影可以沿列方向延伸，行虚拟第七有源部119可用于形成行虚拟第五晶体管，本示例性实施例中，行虚拟第七有源部119在衬底基板的正投影与本虚拟像素驱动电路中的行行虚拟第三有源部118在衬底基板的正投影之间具有第一断口区M1。
如图24所示，本示例性实施例中，虚拟像素行中，第一导电层2 可以包括行虚拟第三复位信号线210、行虚拟第一导电部220、行虚拟使能信号线230，其中，行虚拟第一导电部210与行虚拟使能信号线230相连接。行虚拟第一导电部220在衬底基板的正投影覆盖行虚拟第三有源部118在衬底基板的正投影。
如图28所示，本示例性实施例中，虚拟像素行中，第二导电层3可以包括行虚拟第二导电部310、行虚拟第一复位信号线320、行虚拟第一初始信号线330、行虚拟第二栅线340、行虚拟第二连接部350，其中，其中，行虚拟第二导电部310在衬底基板的正投影与行虚拟第一导电部210在衬底基板的正投影部分交叠，行虚拟第二导电部310可用于形成行虚拟驱动晶体管的栅极和行虚拟存储电容的第二电极，并且，在行方向相邻的两个重复单元中，行虚拟第二导电部310不连接。行虚拟第一复位信号线320在衬底基板的正投影可以沿第一方向X延伸，同一行的各虚拟像素驱动电路中，行虚拟第一复位信号线320可以相互连接。行虚拟第一初始信号线330在衬底基板的正投影与行虚拟第一有源部420在衬底基板的正投影部分交叠。行虚拟第二栅线340与行虚拟第二导电部310相连接。行虚拟第二连接部350在衬底基板的正投影可沿列方向延伸与行虚拟第七有源部在衬底基板的正投影部分交叠。
如图29所示，本示例性实施例中，虚拟像素行中，第二有源层4可以包括行虚拟第一有源部420、行虚拟第二有源部430、行虚拟第九有源部440，其中，行虚拟第一有源部420在衬底基板的正投影与行虚拟第一初始信号线330在衬底基板的正投影部分交叠。
如图30所示，本示例性实施例中，虚拟像素行中，第三导电层5可以包括行虚拟第二复位信号线510，行虚拟第二复位信号线510在衬底基板的正投影可以沿第一方向X延伸且与虚拟第一复位信号线在衬底基板的正投影部分交叠，同一行的各虚拟像素驱动电路中，行虚拟第二复位信号线510可以相互连接。本示例性实施例中，可通过在虚拟像素行中设置第五桥接部65将第三导电部23连接至上一行像素驱动电路中的第四节点N4。
如图25所示，本示例性实施例中，虚拟像素行中，第四导电层6可以包括行虚拟第三连接部610、行虚拟第四连接部620，其中，行虚拟 第三连接部610可通过过孔H10连接行虚拟第一初始信号线330，且通过过孔H11连接行虚拟第一复位信号线320，行虚拟第三连接部610还可通过过孔H12连接行虚拟第八有源部120、通过过孔H13连接行虚拟第二有源部430、通过过孔H14连接行虚拟第二栅线340、通过过孔H15连接行虚拟第一导电部220和行虚拟第三有源部118，此外，行虚拟第三连接部610还可通过过孔H16连接第一电源线Vdd，从而将行虚拟第一初始信号线330、行虚拟第一复位信号线320、行虚拟第八有源部120、行虚拟第二有源部430、行虚拟第二栅线340、行虚拟第一导电部220和行虚拟第三有源部118连接至第一电源线Vdd。行虚拟第四连接部620可通过过孔H17连接行虚拟第三有源部118、通过过孔H18连接行虚拟第九有源部440，进而通过行行虚拟第三连接部610连接至第一电源线Vdd。
如图23所示，本示例性实施例中，如上所述，本行虚拟像素驱动电路中的行虚拟第二导电部310在衬底基板的正投影、行虚拟第三复位信号线210在衬底基板的正投影、行虚拟第二栅线340在衬底基板的正投影和行虚拟使能信号线230在衬底基板的正投影均在第一断口区M1断开，并且第三导电部23在衬底基板的正投影位于第一断口区M1，从而可避免第三导电部23与其他导电结构产生寄生电容，有助于向第四节点提供稳定的复位信号。
如图23所示，本示例性实施例中，显示面板还可以包括多个虚拟像素列，虚拟像素列位于相邻两列子像素之间，虚拟像素列包括多个列虚拟子像素，列虚拟子像素包括列虚拟像素驱动电路，列虚拟像素驱动电路包括列虚拟晶体管，列虚拟复位晶体管的沟道区在衬底基板的正投影具有第二断口区M2，即列虚拟晶体管中的列虚拟复位晶体管的沟道区为断裂结构，正常子像素的第三复位信号线Re3在衬底基板的正投影沿第一方向延伸且穿过该第二断口区，从而第三复位信号线Re3不会与其他导电结构形成寄生电容，可避免或降低对第三复位信号线Re3的信号干扰。
如图27所示，本示例性实施例中，虚拟像素列中，第一有源层1可以包括列虚拟第四有源部130、列虚拟第七有源部140、列虚拟第三有 源部118、列虚拟第五连接部150、列虚拟第六连接部160、列虚拟第七连接部170、列虚拟第八连接部180、列虚拟第九连接部190和列虚拟第十连接部191，其中，列虚拟第五连接部150在衬底基板的正投影、列虚拟第六连接部160在衬底基板的正投影均可以沿列方向延伸，列虚拟第五连接部150和列虚拟第六连接部160相对设置于列虚拟第三有源部118的两侧且均与列虚拟第三有源部118相连接。列虚拟第五连接部150可连接行方向上相邻像素驱动电路中的第十五有源部115，从而通过该第十五有源部115将列虚拟第五连接部150连接至第一电源线Vdd。同样地，列虚拟第六连接部160可连接行方向上相邻像素驱动电路中的第十五有源部115，以通过行方向上相邻像素驱动电路中的第十五有源部115将列虚拟第六连接部160连接至第一电源线Vdd。
本示例性实施例中，虚拟像素列和虚拟像素行相交的虚拟像素中的虚拟像素驱动电路的结构与虚拟像素列和虚拟像素行中的虚拟像素驱动电路结构可以不同。示例性的，虚拟第七连接部170和虚拟第八连接部180位于虚拟像素列和虚拟像素行相交的虚拟像素中，虚拟第七连接部170和虚拟第八连接部180在衬底基板的正投影均可以沿列方向延伸，且虚拟第七连接部170和虚拟第八连接部180相对设置于该虚拟像素中的虚拟第三有源部118的两侧且与该虚拟第三有源部118相连接。虚拟第九连接部190的部分结构、虚拟第十连接部191的部分结构位于虚拟像素列和虚拟像素行相交的虚拟像素中，且位于该虚拟像素中的虚拟第九连接部190分别与该虚拟像素中的虚拟第七连接部170和相邻的行虚拟像素驱动电路中的行虚拟第七有源部119相连接，位于该虚拟像素中的虚拟第十连接部191与该虚拟像素中的虚拟第八连接部180和相邻的行虚拟像素驱动电路中的行虚拟第七有源部119相连接。
如图24所示，本示例性实施例中，虚拟像素列中，第一导电层2可以包括列虚拟第一导电部220，列虚拟第一导电部220在衬底基板的正投影可以覆盖对应位置的列虚拟第三有源部118，且该列虚拟第一导电部220与行方向上相邻的像素驱动电路中的使能信号线EM相连接，以通过使能信号线为该虚拟第一导电部220提供稳定的电信号，避免该虚拟第一导电部220浮空而容易受到静电或其他信号干扰。此外，在虚 拟像素列和虚拟像素行相交的虚拟像素中，虚拟第一导电部220与虚拟使能信号线230相连接，并进而连接至第一电源线Vdd。
如图28所示，本示例性实施例中，虚拟像素列中，第二导电层3可以包括列虚拟第三导电部360，列虚拟第三导电部360在衬底基板的正投影可以与列虚拟第一导电部220在衬底基板的正投影部分交叠，列虚拟第三导电部360可用于连接相邻像素驱动电路电路中的第二导电部32。具体而言，如上述实施例所述，显示面板可以包括行列方向分布的重复单元，一个重复单元包括镜像对称设置的第一像素驱动电路和第二像素驱动电路，第一像素驱动电路与行方向相邻的另一重复单元中的第二像素驱动电路相邻设置。行方向上相邻的两个重复单元中，第一像素驱动电路中的第二导电部32与另一重复重复单元中第二像素驱动电路中的第二导电部32相连接。当在行方向上相邻的两个重复单元中插入虚拟像素列时，则一个重复单元中的第一像素驱动电路的第二导电部32可通过虚拟像素列中的虚拟第三导电部360与另一重复单元中的第二像素驱动电路的第二导电部32相连接，从而使得行方向相邻的两个重复单元中的第二导电部32相连接。此外，虚拟像素列和虚拟像素行相交的虚拟像素中，虚拟第三导电部360可以与虚拟像素列中的虚拟第三导电部23360具有相同的结构。
如图25所示，本示例性实施例中，虚拟像素列中，第四导电层6可以包括列虚拟第四导电部630，列虚拟第四导电部630可通过过孔H19连接列虚拟第四有源部130和列虚拟第七有源部140、通过过孔H20连接列虚拟第九连接部190和列虚拟第十连接部191、以及通过过孔H21连接第一电源线Vdd，从而通过列虚拟第四导电部630将列虚拟第四有源部130、列虚拟第七有源部140、列虚拟第九连接部190和列虚拟第十连接部191连接至第一电源线Vdd，为其提供稳定电压信号。此外，相邻像素驱动电路中的第二桥接部62的部分结构可位于虚拟像素列中，且第二桥接部62位于虚拟像素列中的部分结构可通过过孔H22连接虚拟像素列中的列虚拟第五连接部150，以将列虚拟第五连接部150连接至第一电源线Vdd，为列虚拟第五连接部150提供稳定电压信号。同样地，与列虚拟第六连接部160相邻的像素驱动电路中的第二桥接部62在位于 虚拟像素列中的部分结构可通过该位置的过孔H22连接该列虚拟第六连接部160，从而将列虚拟第六连接部160连接至第一电源线Vdd，为列虚拟第六连接部160提供稳定电压信号。进一步的，第二桥接部62的部分结构还可以位于虚拟像素列和虚拟像素行相交的虚拟像素中，且此部分结构可通过过孔H23连接对应位置的虚拟第七连接部170、通过过孔H24连接对应位置的虚拟第三复位信号线210，从而将虚拟第七连接部170和虚拟第三复位信号线210连接至第一电源线Vdd，为其提供稳定的电压信号。同样地，在行方向是行与虚拟第八连接部180相邻的像素驱动电路中的第二桥接部62可通过对应位置的过孔H23连接对应位置的虚拟第八连接部180、通过过孔H24连接对应位置的虚拟第三复位信号线210，以将虚拟第八连接部180连接至第一电源线Vdd。此外，第四导电层6还可以包括虚拟第五导电部640，虚拟第五导电部640可位于虚拟像素行和虚拟像素列相交的虚拟像素中，虚拟第五导电部640可通过过孔H25连接第一电源线，虚拟第五导电部640在衬底基板的正投影可以沿行方向延伸且位于虚拟第三复位信号线210在衬底基板的正投影和虚拟第三导电部360在衬底基板的正投影之间。此外，虚拟第四导电部630的部分结构可位于虚拟像素行和虚拟像素列相交的虚拟像素中，且位于该虚拟像素中的虚拟第四导电部630通过过孔H26连接虚拟第三导电部360、通过过孔H50连接虚拟第一导电部220，以将虚拟第三导电部360和虚拟第一导电部220连接至第一电源线。
如图31所示，本示例性实施例中，虚拟像素列中，第五导电层7可以包括第一电源线Vdd，该第一电源线Vdd用于为虚拟像素列中浮空的导电结构提供稳定的电压信号，可防止浮空的导电结构受到静电影响。
如图32所示，为图23中沿虚线AA的部分剖视图。该显示面板可以包括第一绝缘层81、第二绝缘层82、第三绝缘层83、第四绝缘层84、第五绝缘层85、第一介电层86、第一平坦层87，其中，衬底基板80、遮光层、第一绝缘层81、第一有源层1、第二绝缘层82、第一导电层2、第三绝缘层83、第二导电层3、第四绝缘层84、第二有源层4、第五绝缘层85、第三导电层5、第一介电层86、第四导电层6、第一平坦层87、第五导电层7、第二平坦层88依次层叠设置。第一绝缘层81、第二绝缘 层82可以氧化硅层，第一介电层86可以为氮化硅层。衬底基板可以包括依次层叠设置的玻璃基板、阻挡层、聚酰亚胺层，阻挡层可以为无机材料。第一导电层2、第二导电层3的材料可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等。第三导电层5、第四导电层6的材料可以包括金属材料，例如可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层。
本公开还提供一种显示装置，包括上述任意实施例所述的显示面板。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (34)

  1. 一种显示面板，其中，所述显示面板包括像素驱动电路，所述像素驱动电路包括驱动晶体管、第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第一极；所述显示面板还包括：
    衬底基板；
    第一导电层，位于所述衬底基板的一侧，所述第一导电层包括：
    第一导电部，所述第一导电部用于形成所述驱动晶体管的栅极；
    第二有源层，位于所述第一导电层背离所述衬底基板的一侧，所述第二有源层包括：
    第二有源部，用于形成所述第二晶体管的沟道区；
    第八有源部，连接于所述第二有源部的一侧；
    第三导电层，位于所述第二有源层背离所述衬底基板的一侧，所述第三导电层包括：
    第一栅线，在所述衬底基板的正投影沿第一方向延伸且覆盖所述第二有源部，所述第一栅线的部分结构用于形成所述第二晶体管的顶栅，所述第八有源部在所述衬底基板的正投影和所述第一导电部在所述衬底基板的正投影分别位于所述第一栅线在所述衬底基板的正投影的两侧；
    介电层，位于所述第三导电层背离所述衬底基板的一侧；
    第四导电层，位于所述介电层背离所述衬底基板的一侧，所述第四导电层包括：
    第一桥接部，分别通过过孔连接所述第八有源部和所述第一导电部；
    其中，第一栅线包括相对设置且与其延伸方向相同的第六侧边和第七侧边，所述第六侧边至少部分结构在所述衬底基板的正投影与所述第一桥接部在所述衬底基板的正投影垂直，所述第七侧边至少部分结构在所述衬底基板的正投影与所述第一桥接部在所述衬底基板的正投影垂直。
  2. 根据权利要求1所述的显示面板，其中，所述第六侧边包括第一分段，所述第七侧边包括第二分段，所述第一分段在所述衬底基板的正投影与所述第一桥接部在所述衬底基板的正投影垂直，所述第二分段在所述衬底基板的正投影与所述第一桥接部在所述衬底基板的正投影垂直；
    所述第一分段在所述衬底基板的正投影平行于所述第二分段在所述衬底基板的正投影，或者，所述第一分段在所述衬底基板的正投影所在直线与所述第二分段在所述衬底基板的正投影所在直线相交。
  3. 根据权利要求2所述的显示面板，其中，所述第六侧边在所述衬底基板的正投影与所述第一桥接部在所述衬底基板的正投影相交的长度为S1，所述第一分段在所述衬底基板的正投影的长度为S2，所述S2/S1大于等于0.7且小于等于1；
    所述第七侧边在所述衬底基板的正投影与所述第一桥接部在所述衬底基板的正投影相交的长度为S3，所述第二分段在所述衬底基板的正投影的长度为S4，S4/S3大于等于0.7且小于等于1。
  4. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    第二导电层，位于所述第一导电层和所述第二有源层之间，所述第二导电层包括：
    第二栅线，在所述衬底基板的正投影沿所述第一方向延伸且覆盖所述第二有源部在所述衬底基板的正投影，所述第二栅线的部分结构用于形成所述第二晶体管的底栅；
    其中，所述第二栅线包括相对设置且沿其延伸方向延伸的第三侧边和第四侧边，所述第一桥接部在所述衬底基板的正投影垂直相交于至少部分所述第三侧边在所述衬底基板的正投影和至少部分所述第四侧边在所述衬底基板的正投影。
  5. 根据权利要求4所述的显示面板，其中，所述第一栅线包括第一延伸部，所述第一延伸部在所述衬底基板的正投影位于所述第一桥接部在所述衬底基板的正投影上，所述第一延伸部包括相对设置且与其延伸方向相同的第一侧边和第二侧边；
    所述第二栅线包括第二延伸部，所述第二延伸部在所述衬底基板的正投影位于所述第一桥接部在所述衬底基板的正投影上且与所述第一延伸部在所述衬底基板的正投影交叠，所述第二延伸部包括相对设置且与其延伸方向相同的第三侧边和第四侧边；
    所述第三侧边在所述衬底基板的正投影位于所述第四侧边在所述衬底基板的正投影远离所述第一导电部在所述衬底基板的正投影的一侧；
    所述第一侧边在所述衬底基板的正投影位于所述第二侧边在所述衬底基板的正投影远离所述第一导电部在所述衬底基板的正投影的一侧；
    所述第三侧边上任意的第一节点在所述衬底基板的正投影与所述第一侧边在所述衬底基板的正投影在第二方向上的距离为L1，所述第一节点在所述衬底基板的正投影与所述第四侧边在所述衬底基板的正投影在第二方向上的距离为L2，所述第二方向与所述第一方向相交，L1/L2大于等于0.25且小于等于0.8；
    所述第四侧边上的任意第二节点在所述衬底基板的正投影与所述第二侧边在所述衬底基板的正投影在第二方向上的距离为L3，所述第二节点在所述衬底基板的正投影与所述第三侧边在所述衬底基板的正投影在第二方向上的距离为L4，L3/L4大于等于0.25且小于等于0.8。
  6. 根据权利要求5所述的显示面板，其中，所述第一延伸部在所述衬底基板的正投影覆盖所述第三侧边在所述衬底基板的正投影，所述第二延伸部在所述衬底基板的正投影覆盖所述第二侧边在所述衬底基板的正投影；
    或，所述第一延伸部在所述衬底基板的正投影覆盖所述第三侧边在所述衬底基板的正投影和所述第四侧边在所述衬底基板的正投影；
    或，所述第二延伸部在所述衬底基板的正投影覆盖所述第一侧边在所述衬底基板的正投影和所述第二侧边在所述衬底基板的正投影；
    或，所述第一延伸部在所述衬底基板的正投影覆盖所述第四侧边在所述衬底基板的正投影，所述第二延伸部在所述衬底基板的正投影覆盖所述第一侧边在所述衬底基板的正投影。
  7. 根据权利要求5所述的显示面板，其中，所述第一延伸部在所述衬底基板的正投影与所述第二延伸部在所述衬底基板的正投影的交叠区域在所述第二方向的宽度为L5，L1/L5大于等于0.6且小于等于1，L3/L5大于等于0.6且小于等于1。
  8. 根据权利要求5所述的显示面板，其中，所述像素驱动电路包括第五晶体管、第六晶体管，所述第五晶体管的第一极连接所述驱动晶体管的第二极，所述第六晶体管的第一极连接所述驱动晶体管的第一极；
    所述显示面板还包括：
    第一有源层，位于所述衬底基板和所述第一导电层之间，所述第一有源层包括：
    第五有源部，用于形成所述第五晶体管的沟道区；
    第六有源部，用于形成所述第六晶体管的沟道区；
    其中，所述第五有源部与所述第六有源部在所述第一方向上具有第六距离L6，L1/L6大于等于5％，L2/L6大于等于5％。
  9. 根据权利要求5所述的显示面板，其中，L1大于等于1.3μm，L2大于等于1.3μm。
  10. 根据权利要求6所述的显示面板，其中，所述第二栅线包括第二延伸部，所述第二延伸部在所述衬底基板的正投影位于所述第一桥接部在所述衬底基板的正投影上且与所述第一延伸部在所述衬底基板的正投影交叠；
    所述第二延伸部在所述衬底基板的正投影覆盖所述第一延伸部在所述衬底基板的正投影，且所述第二延伸部在所述衬底基板的正投影在第一方向具有第一中心线，所述第一延伸部在所述衬底基板的正投影具有第二中心线，所述第一中心线与所述第二中心线重叠；
    所述第二延伸部在所述衬底基板的正投影在第二方向具有第一宽度，所述第一延伸部在所述衬底基板的正投影在第二方向具有第二宽度，所述第二方向与所述第一方向相交；
    其中，同一位置处，所述第一宽度与所述第二宽度之比为1.5～3。
  11. 根据权利要求6所述的显示面板，其中，所述第一栅线具有沿其延伸方向相连接的第一组成部和第二组成部，所述第一组成部在所述衬底基板的正投影在第二方向的宽度大于所述第一组成部在所述衬底基板的正投影在所述第二方向的宽度，所述第二方向与所述第一方向相交；
    所述第二栅线具有沿其延伸方向相连接的第三组成部和第四组成部，所述第三组成部在所述衬底基板的正投影在所述第二方向的宽度大于所述第四组成部在所述衬底基板的正投影在所述第二方向的宽度；
    其中，所述第一组成部在所述衬底基板的正投影、所述第三组成部在所述衬底基板的正投影均覆盖所述第二有源部在所述衬底基板的正投影，且所述第三组成部在所述衬底基板的正投影覆盖所述第一组成部在 所述衬底基板的正投影；
    所述第一桥接部在所述衬底基板的正投影与所述第一组成部在所述衬底基板的正投影、所述第二组成部在所述衬底基板的正投影部分交叠，且所述第一桥接部在所述衬底基板的正投影还与所述第三组成部在所述衬底基板的正投影、所述第四组成部在所述衬底基板的正投影部分交叠。
  12. 根据权利要求6所述的显示面板，其中，所述第一栅线具有第一组成部和第二组成部，所述第一组成部在第二方向的宽度大于所述第一组成部在所述第二方向的宽度，所述第二方向与所述第一方向相交；
    所述第二栅线具有第三组成部和第四组成部，所述第三组成部在所述第二方向的宽度大于所述第四组成部在所述第二方向的宽度；
    其中，所述第一组成部在所述衬底基板的正投影、所述第三组成部在所述衬底基板的正投影均覆盖所述第二有源部在所述衬底基板的正投影，且所述第三组成部在所述衬底基板的正投影覆盖所述第一组成部在所述衬底基板的正投影；
    所述第一桥接部在所述衬底基板的正投影与所述第一组成部在所述衬底基板的正投影、所述第三组成部在所述衬底基板的正投影相交。
  13. 根据权利要求1所述的显示面板，其中，所述显示面板包括沿第一方向和第二方向阵列分布的多个所述像素驱动电路，所述第一方向为行方向，所述第二方向为列方向；
    所述像素驱动电路用于驱动发光单元发光，所述像素驱动电路还包括对第四晶体管和第七晶体管，所述第四晶体管的第一极连接所述驱动晶体管的第二极，栅极连接第三栅线，第二极连接数据线；所述第七晶体管的第一极连接所述发光单元的第一电极，第二极连接第二初始信号线，栅极连接第三复位信号线；所述显示面板还包括：
    第一有源层，位于所述衬底基板和所述第一导电层之间，所述第一有源层包括：
    第四有源部，用于形成所述第四晶体管的沟道区；
    第七有源部，用于形成所述第七晶体管的沟道区；
    所述第一导电层还包括：
    所述第三栅线，在所述衬底基板的正投影沿所述第一方向延伸且覆 盖所述第四有源部在所述衬底基板的正投影，所述第三栅线的部分结构用于形成所述第四晶体管的栅极；
    所述第三复位信号线，在所述衬底基板的正投影沿所述第一方向延伸且覆盖所述第七有源部，所述第三复位信号线的部分结构用于形成所述第七晶体管的栅极；
    其中，本行像素驱动电路的第三栅线复用为上一行像素驱动电路的第三复位信号线。
  14. 根据权利要求1所述的显示面板，其中，所述像素驱动电路还包括存储电容，所述存储电容的第一极连接所述驱动晶体管的栅极，第二极连接第一电源线；
    所述第一导电部还用于形成所述存储电容的第一电极；
    所述显示面板还包括：
    第五导电层，位于所述第四导电层背离所述衬底基板的一侧，所述第五导电层包括：
    所述第一电源线，在所述衬底基板的正投影沿所述第二方向延伸，所述第二方向与所述第一方向相交；
    第二导电层，位于所述第一导电层和所述第二有源层之间，所述第二导电层包括：
    第二导电部，所述第二导电部在所述衬底基板的正投影与所述第一导电部在所述衬底基板的正投影部分交叠，所述第二导电部用于形成所述存储电容的第二电极，所述第二导电部通过过过孔连接所述第一电源线。
  15. 根据权利要求14所述的显示面板，其中，所述第一方向为行方向，所述第二方向为列方向；
    所述显示面板包括沿行列方向分布的多个重复单元，所述重复单元包括在行方向上相邻的两个所述像素驱动电路，每列所述像素驱动电路对应设置一条所述第一电源线和一个所述第二导电部；
    同一重复单元中，两条所述第一电源线相连接；
    在行方向相邻的重复单元中，相邻所述第二导电部相连接。
  16. 根据权利要求15所述的显示面板，其中，在同一重复单元中， 在行方向相邻的两个所述像素驱动电路互为镜像。
  17. 根据权利要求1所述的显示面板，其中，所述像素驱动电路包括第五晶体管，所述第五晶体管的第一极连接所述驱动晶体管的第二极，第二极连接所述第一电源线；所述显示面板还包括：
    第一有源层，位于所述衬底基板和所述第一导电层之间，所述第一有源层包括：
    第五有源部，用于形成所述第五晶体管的沟道区；
    所述第一导电层还包括：
    使能信号线，在所述衬底基板的正投影沿所述第一方向延伸且覆盖所述第五有源部，所述使能信号线的部分结构用于形成所述第五晶体管的栅极；
    第五导电层，位于所述第四导电层背离所述衬底基板的一侧，所述第五导电层包括：
    所述第一电源线，在所述衬底基板的正投影沿第二方向延伸，所述第二方向与所述第一方向相交；
    所述第四导电层还包括：
    第二桥接部，所述第二桥接部通过第一过孔连接所述第五晶体管的第二极，且通过另一过孔连接所述第一电源线。
  18. 根据权利要求17所述的显示面板，其中，所述第一方向为行方向，所述第二方向为列方向；
    所述显示面板包括沿行列方向分布的多个重复单元，所述重复单元包括在行方向上相邻的两个所述像素驱动电路；
    所述第二桥接部与所述像素驱动电路一一对应设置，在行方向相邻的重复单元中，相邻所述第二桥接部相连接且共用所述第一过孔。
  19. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    第五导电层，位于所述第四导电层背离所述衬底基板的一侧，所述第五导电层包括：
    第一电源线，在所述衬底基板的正投影沿第二方向延伸，所述第二方向与所述第一方向相交；
    其中，所述第一电源线在所述衬底基板的正投影覆盖所述第一桥接 部在所述衬底基板的正投影。
  20. 根据权利要求19所述的显示面板，其中，所述第二晶体管的栅极连接第一栅线，所述第二晶体管的第二极连接所述驱动晶体管的第一极；
    所述第二有源层还包括：
    第一有源部，用于形成所述第一晶体管的沟道区；
    第二有源部，用于形成所述第二晶体管的沟道区；
    所述显示面板还包括：
    第二导电层，位于所述第一导电层和所述第二有源层之间，所述第二导电层包括：
    第二栅线，在所述衬底基板的正投影沿所述第一方向延伸且覆盖所述第二有源部在所述衬底基板的正投影，所述第二栅线的部分结构用于形成所述第二晶体管的底栅，且所述第一栅线在所述衬底基板的正投影覆盖所述第二有源部在所述衬底基板的正投影，所述第一栅线的部分结构用于形成所述第二晶体管的顶栅；
    第一复位信号线，在所述衬底基板的正投影沿所述第一方向延伸且覆盖所述第一有源部在所述衬底基板的正投影，所述第一复位信号线的部分结构用于形成所述第一晶体管的底栅；
    所述第一电源线在所述衬底基板的正投影覆盖所述第一有源部在所述衬底基板的正投影和所述第二有源部在所述衬底基板的正投影。
  21. 根据权利要求1所述的显示面板，其中，所述第一晶体管的第二极连接第一初始信号线，所述第二晶体管的第二极连接所述驱动晶体管的第一极；所述像素驱动电路还包括第六晶体管，所述第六晶体管的第一极连接所述驱动晶体管的第一极；
    所述显示面板还包括：
    第二导电层，位于所述第一导电层和所述第二有源层之间，所述第二导电层包括：
    所述第一初始信号线，在所述衬底基板的正投影沿所述第一方向延伸；
    第一有源层，位于所述衬底基板和所述第一导电层之间，所述第一 有源层包括：
    第三有源部，用于形成所述驱动晶体管的沟道区；
    第六有源部，用于形成所述第六晶体管的沟道区；
    第十一有源部，连接于所述第三有源部和所述第六有源部之间；
    所述第二有源层还包括：
    第二有源部，用于形成所述第二晶体管的沟道区；
    第九有源部，连接于所述第二有源部和所述第八有源部之间；
    第十四有源部，连接于所述第二有源部远离所述第八有源部的一侧；
    所述第四导电层还包括：
    第三桥接部，连接所述第十四有源部且通过过孔连接所述第一初始信号线；
    第四桥接部，通过一过孔连接所述第十一有源部且通过另一过孔连接所述第十四有源部。
  22. 根据权利要求21述的显示面板，其中，所述显示面板包括沿第一方向和第二方向阵列分布的多个所述像素驱动电路，所述第一方向为行方向，所述第二方向为列方向；
    所述显示面板包括沿行列方向分布的多个重复单元，所述重复单元包括两个所述像素驱动电路；
    同一重复单元中，两个所述像素驱动电路共用所述第三桥接部。
  23. 根据权利要求21所述的显示面板，其中，所述像素驱动电路还包括第五晶体管、第六晶体管、第七晶体管，所述第五晶体管的第一极连接所述驱动晶体管的第二极，所述第五晶体管的第二极连接所述第一电源线，所述第六晶体管的第一极连接驱动晶体管的第一极，所述第六晶体管的第二极连接所述第七晶体管的第一极；所述显示面板还包括：
    第一有源层，位于所述衬底基板和所述第一导电层之间，所述第一有源层包括：
    第五有源部，用于形成所述第五晶体管的沟道区；
    第六有源部，用于形成所述第六晶体管的沟道区；
    第七有源部，用于形成所述第七晶体管的沟道区；
    所述第一导电层还包括：
    使能信号线，在所述衬底基板的正投影沿所述第一方向延伸且覆盖所述第五有源部和所述第六有源部，所述使能信号线的部分结构用于形成所述第五晶体管的栅极、部分结构用于形成所述第六晶体管的栅极；
    第三复位信号线，在所述衬底基板的正投影沿所述第一方向延伸且覆盖所述第七有源部，所述第三复位信号线的部分结构用于形成所述第七晶体管的栅极；
    第二导电层，位于所述第一导电层和所述第二有源层之间，所述第二导电层包括：
    所述第一初始信号线，在所述衬底基板的正投影沿所述第一方向延伸；
    第五导电层，位于所述第四导电层背离所述衬底基板的一侧，所述第五导电层包括：
    所述第一电源线，在所述衬底基板的正投影沿所述第二方向延伸，所述第二方向与所述第一方向相交；
    所述第四导电层还包括：
    第二桥接部，所述第二桥接部通过过孔连接所述第五晶体管的第二极，且通过另一过孔连接所述第一电源线；
    其中，同一像素驱动电路中，所述第一导电部在所述衬底基板的正投影位于所述使能信号线在所述衬底基板的正投影和所述第一栅线在所述衬底基板的正投影之间；
    同一像素驱动电路中，所述第一栅线在所述衬底基板的正投影、所述第三复位信号线在所述衬底基板的正投影、所述第一初始信号线在所述衬底基板的正投影沿远离所述第一导电部的方向依次分布。
  24. 根据权利要求23所述的显示面板，其中，所述第一晶体管的栅极连接第二复位信号线；
    所述第二有源层还包括：
    第一有源部，用于形成所述第一晶体管的沟道区；
    所述显示面板还包括：
    第二导电层，位于所述第一导电层和所述第二有源层之间，所述第二导电层包括：
    第一复位信号线，在所述衬底基板的正投影沿所述第一方向延伸且覆盖所述第一有源部在所述衬底基板的正投影，所述第一复位信号线的部分结构用于形成所述第一晶体管的底栅；
    所述第三导电层还包括：
    第二复位信号线，在所述衬底基板的正投影沿所述第一方向延伸且覆盖所述第一有源部在所述衬底基板的正投影，所述第二复位信号线的部分结构用于形成所述第一晶体管的顶栅；
    其中，所述第一复位信号线在所述衬底基板的正投影位于所述第一初始信号线在所述衬底基板的正投影与所述第三复位信号线在所述衬底基板的正投影之间。
  25. 根据权利要求23所述的显示面板，其中，所述第一方向为行方向，所述第二方向为列方向；所述像素驱动电路还包括第四晶体管，所述第四晶体管的第一极连接所述驱动晶体管的第二极，第二极连接数据信号线；
    所述第五导电层还包括：
    数据线，在所述衬底基板的正投影沿所述第二方向延伸；
    所述第四导电层还包括：
    第六桥接部，通过一过孔连接所述数据线且通过另一过孔连接所述第四晶体管的第二极；
    所述显示面板包括沿行列方向分布的多个重复单元，所述重复单元包括两个所述像素驱动电路，每列所述像素驱动电路对应设置一条所述第一电源线和一条所述数据线；
    其中，同一重复单元中，两条所述第一电源线相连接，且两条所述数据线在所述衬底基板的正投影分布于两条所述第一电源线在所述衬底基板的正投影的两侧。
  26. 根据权利要求23所述的显示面板，其中，所述像素驱动电路还包括第四晶体管，所述第四晶体管的第一极连接所述驱动晶体管的第二极，第二极连接数据信号线；
    所述第一晶体管、第二晶体管为N型晶体管；所述驱动晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管为P型晶体管。
  27. 根据权利要求1所述的显示面板，其中，所述显示面板包括沿第一方向和第二方向阵列分布的多个所述像素驱动电路，所述第一方向为行方向，所述第二方向为列方向；所述显示面板包括沿行列方向阵列分布的多个子像素，所述子像素包括所述像素驱动电路；所述显示面板还包括：
    第五导电层，位于所述第四导电层背离所述衬底基板的一侧，所述第五导电层包括：
    第一电源线，在所述衬底基板的正投影沿所述第二方向延伸；
    多个虚拟像素行，所述虚拟像素行位于相邻两行子像素之间，所述虚拟像素行包括多个行虚拟子像素，所述行虚拟子像素包括行虚拟像素驱动电路。
  28. 根据权利要求27所述的显示面板，其中，所述行虚拟像素驱动电路包括行虚拟晶体管和行虚拟信号线，且所述行虚拟晶体管和所述行虚拟信号线相互连接成一整体结构，所述整体结构连接至所述第一电源线。
  29. 根据权利要求28所述的显示面板，其中，所述显示面板包括沿第一方向和第二方向阵列分布的多个所述像素驱动电路，所述第一方向为行方向，所述第二方向为列方向；所述像素驱动电路用于驱动发光单元发光，所述像素驱动电路还包括第四晶体管、第六晶体管和第七晶体管，所述第四晶体管的第一极连接所述驱动晶体管的第二极，栅极连接第三栅线，第二极连接数据线；所述第六晶体管的第一极连接所述驱动晶体管的第一极，第二极连接所述发光单元的第一电极；所述第七晶体管的第一极连接所述发光单元的第一电极，第二极连接第二初始信号线，栅极连接第三复位信号线；
    本行像素驱动电路中的第七晶体管在所述衬底基板的正投影位于所述虚拟像素行在所述衬底基板的正投影远离本行像素驱动电路中的第六晶体管在所述衬底基板的正投影的一侧；所述显示面板还包括：
    第一有源层，位于所述衬底基板和所述第一导电层之间，所述第一有源层包括：
    第四有源部，用于形成所述第四晶体管的沟道区；
    第六有源部，用于形成所述第六晶体管的沟道区；
    第七有源部，用于形成所述第七晶体管的沟道区；
    第三导电部，至少部分位于所述虚拟像素行所在区域，所述第三导电部在所述衬底基板的正投影沿所述第二方向延伸，所述第三导电部用于连接本行像素驱动电路中第六晶体管的第二极和本行像素驱动电路中第七晶体管的第一极；
    所述第一导电层还包括：
    所述第三栅线，在所述衬底基板的正投影沿所述第一方向延伸且覆盖所述第四有源部在所述衬底基板的正投影，所述第三栅线的部分结构用于形成所述第四晶体管的栅极；
    所述第三复位信号线，在所述衬底基板的正投影沿所述第一方向延伸且覆盖所述第七有源部，所述第三复位信号线的部分结构用于形成所述第七晶体管的栅极；
    其中，本行像素驱动电路的第三栅线复用为上一行像素驱动电路的第三复位信号线。
  30. 根据权利要求29所述的显示面板，其中，所述行虚拟像素驱动电路还包括行虚拟存储电容，所述行虚拟信号线包括行虚拟第二初始信号线、行虚拟第三复位信号线、行虚拟栅线和行虚拟使能信号线，所述行虚拟晶体管包括行虚拟驱动晶体管和行虚拟第五晶体管，所述行虚拟第五晶体管在所述衬底基板的正投影与所述行虚拟驱动晶体管在所述衬底基板的正投影之间具有第一断口区，所述第三导电部在所述衬底基板的正投影位于所述第一断口区，且所述行虚拟存储电容的第二电极在所述衬底基板的正投影、所述行虚拟第二初始信号线在所述衬底基板的正投影、所述行虚拟第三复位信号线在所述衬底基板的正投影、所述行虚拟栅线在所述衬底基板的正投影和所述行虚拟使能信号线在所述衬底基板的正投影均在所述第一断口区断开。
  31. 根据权利要求30所述的显示面板，其中，所述第三导电部位于所述第一导电层；所述行虚拟像素驱动电路包括行虚拟第一晶体管，所述行虚拟第一晶体管的第一极连接行虚拟驱动晶体管的栅极，第二极连接行虚拟第一初始信号线，栅极连接行虚拟第二复位信号线；
    所述行虚拟信号线还包括所述行虚拟第二复位信号线，所述行虚拟第二复位信号线位于所述第三导电层，所述行虚拟第二复位信号线在所述衬底基板的正投影沿所述第一方向延伸且位于所述第一断口区和上一行像素驱动电路所在区域之间；
    所述显示面板还包括：
    第五桥接部，位于所述第四导电层，所述第五桥接部分别通过过孔连接所述第三导电部和本行像素驱动电路中第六晶体管的第二极，且所述第五桥接部在所述衬底基板的正投影与所述第二复位信号线在所述衬底基板的正投影相交。
  32. 根据权利要求31所述的显示面板，其中，所述显示面板还包括：
    多个虚拟像素列，所述虚拟像素列位于相邻两列子像素之间，所述虚拟像素列包括多个列虚拟子像素，所述列虚拟子像素包括列虚拟像素驱动电路，所述列虚拟像素驱动电路包括列虚拟复位晶体管的沟道区，且所述列虚拟复位晶体管的沟道区在所述衬底基板的正投影具有第二断口区；
    所述第一导电层还包括第三复位信号线，所述第三复位信号线在所述衬底基板的正投影沿所述第一方向延伸且穿过所述第二断口区。
  33. 根据权利要求32所述的显示面板，其中，所述虚拟像素列还包括列虚拟存储电容和列虚拟信号线，所述列虚拟存储电容的第一电极连接所述使能信号线，所述列虚拟信号线和列所述虚拟晶体管连接为整体结构，且所述整体结构连接至所述第一电源线。
  34. 一种显示装置，其中，包括权利要求1-33任一项所述的显示面板。
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