WO2024027775A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024027775A1
WO2024027775A1 PCT/CN2023/110837 CN2023110837W WO2024027775A1 WO 2024027775 A1 WO2024027775 A1 WO 2024027775A1 CN 2023110837 W CN2023110837 W CN 2023110837W WO 2024027775 A1 WO2024027775 A1 WO 2024027775A1
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WO
WIPO (PCT)
Prior art keywords
base substrate
orthographic projection
electrode
transistor
line
Prior art date
Application number
PCT/CN2023/110837
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English (en)
French (fr)
Other versions
WO2024027775A9 (zh
Inventor
王蓉
何帆
何翼
董向丹
于海博
仝可蒙
王琦伟
蔡文哲
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2024027775A1 publication Critical patent/WO2024027775A1/zh
Publication of WO2024027775A9 publication Critical patent/WO2024027775A9/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • the display panel has a wider frame.
  • a display panel includes a display area and a fan-out area located in the display area.
  • the display panel further includes: a substrate substrate, a plurality of data lines, a plurality of third One data fan-out line and a plurality of second data fan-out lines.
  • a plurality of data lines are located in the display area, the orthographic projections of the data lines on the substrate are spaced apart along the first direction and extend along the second direction, and the first direction and the second direction intersect;
  • a plurality of first data fan-out lines are located in the fan-out area, and the orthographic projections of the first data fan-out lines on the substrate are spaced apart along the second direction and extend along the first direction, and
  • a first data fan-out line is provided corresponding to the data line, and the first data fan-out line is connected to the corresponding data line;
  • a plurality of second data fan-out lines are located in the fan-out area, and the second data fan-out line
  • the orthographic projections on the base substrate are spaced apart along the first direction and extend along the second direction.
  • the second data fan-out lines are arranged corresponding to the first data fan-out lines.
  • the fan-out line is connected to the corresponding first data fan-out line.
  • the display panel further includes: a plurality of first signal lines and a plurality of second signal lines.
  • the plurality of first signal lines are located in the display area, and the first signal lines are located in the display area.
  • the orthographic projection on the substrate extends along the first direction and is spaced apart along the second direction.
  • the plurality of first signal lines include first sub-signal lines, and at least one of the first sub-signal lines Part of the structure is used to form the first data fan-out line; a plurality of second signal lines are located in the display area and are located on different conductive layers from the first signal lines, and the second signal lines are on the base substrate
  • the orthographic projection on the screen extends along the second direction and is distributed at intervals along the first direction.
  • the plurality of second signal lines include second sub-signal lines, and at least part of the structure of the second sub-signal line is used for The second data fan-out line is formed.
  • the minimum distance in the second direction between the orthographic projections of two adjacent first signal lines on the substrate is S1, and the minimum distance between the two adjacent first signal lines is S1.
  • the maximum distance of the orthographic projection of a line on the substrate in the second direction is S2, where (S2-S1)/S1 is greater than or equal to 0 and less than or equal to 0.2; and/or, two adjacent The minimum distance in the first direction of the orthographic projection of the second signal line on the base substrate is S3, and the orthographic projection of two adjacent second signal lines on the base substrate is in the first direction.
  • the maximum distance in one direction is S4, where (S4-S3)/S3 is greater than or equal to 0 and less than or equal to 0.2.
  • the first sub-signal line further includes a first analog line spaced apart from the first data fan-out line
  • the second sub-signal line further includes a first analog line spaced apart from the second data fan-out line.
  • Fan-out lines are second analog lines arranged at intervals; the fan-out area includes a first fan-out area and a second fan-out area, the first data fan-out line is located in the first fan-out area, and the second data fan-out area
  • the outlet line is located in the second fan-out area;
  • the plurality of first signal lines also include a third analog line, and the third analog line is located in a display area outside the first fan-out area; the plurality of third analog lines are located in the second fan-out area.
  • the two signal lines also include a fourth analog line, and the fourth analog line is located in the display area outside the second fan-out area.
  • the display panel further includes a pixel driving circuit and a light-emitting unit, the pixel driving circuit is connected to the first electrode of the light-emitting unit; the display panel further includes: a common electrode layer, The common electrode layer is used to form the second electrode of the light-emitting unit; wherein the first analog line, the second analog line, the third analog line, and the fourth analog line are connected to the common electrode. layer.
  • the first analog line is connected to a fourth analog line that intersects its orthographic projection on the substrate through a via hole; the third analog line is connected through a via hole The second simulation line and the fourth simulation line intersect with its orthographic projection on the substrate.
  • the display panel further includes a frame area located around the display area, the frame area includes a first frame area and a second frame area arranged oppositely, and the fan-out area is located The side close to the second frame area; the display panel also includes: an electrode ring and a power circuit.
  • the electrode ring is located in the frame area and connected to the common electrode layer.
  • the electrode ring is located in the third At least part of the structure of a frame area connects the second analog line and the fourth analog line; a power circuit is bound to the second frame area, and the power circuit connects the electrode ring and is located in the second frame area At least part of the structure, the power circuit is used to provide a power signal to the electrode ring.
  • the first fan-out area includes a first sub-fan-out area and a second sub-fan-out area, and the first sub-fan-out area and the second sub-fan-out area are located in the The second fan-out area is on both sides in the first direction; the plurality of second signal lines also include at least one fifth analog line, and part of the structure of the fifth analog line is located in the second fan-out area. , and the fifth analog line is respectively connected to the first analog line and the third analog line that intersect with its orthographic projection on the base substrate through via holes.
  • a plurality of first signal lines are located on the same conductive layer, and a plurality of second signal lines are located on the same conductive layer; the conductive layer where the second signal lines are located is located on the first The signal line is located on the side of the conductive layer facing away from the base substrate.
  • the display panel further includes: a first source drain layer and a second source drain layer.
  • the first source drain layer is located on one side of the base substrate.
  • the first source drain layer layer includes the first signal line;
  • a second source-drain layer is located on a side of the first source-drain layer facing away from the base substrate, and the second source-drain layer includes the second signal line and the data line;
  • the orthographic projection of the second signal line on the base substrate is located between the orthographic projections of two adjacent data lines on the base substrate.
  • the first signal line includes a plurality of first via contact portions and a first extension portion, and the plurality of first via hole contact portions are located on the front surface of the substrate substrate. Projections are spaced apart along the first direction, the first extension is connected to the first via contact, and the orthographic projection of the first via contact on the base substrate is on the second The size in the direction is greater than the size of the orthogonal projection of the first extension portion on the substrate in the second direction; the second signal line includes a plurality of second via contact portions and a second extension department, several of the aforementioned Orthographic projections of two via hole contact portions on the base substrate are spaced apart along the second direction, the second extension portion is connected to the second via hole contact portion, and the second via hole contact portion is on The size of the orthographic projection on the base substrate in the first direction is greater than the size of the orthogonal projection of the second extension portion on the base substrate in the first direction; wherein, the first A via hole contact part and the second via hole contact part are provided corresponding
  • the minimum distance in the first direction between the orthographic projections of adjacent first via contact portions on the base substrate is S5, and the adjacent first via contact portions have a minimum distance of S5 in the first direction.
  • the maximum distance of the orthographic projection of the hole contact portion on the base substrate in the first direction is S6, where (S6-S5)/S5 is greater than or equal to 0 and less than or equal to 0.2; and/or adjacent
  • the minimum distance in the second direction of the orthographic projection of the second via hole contact portion on the base substrate is S7, and the orthographic projection of the adjacent second via hole contact portion on the base substrate is The maximum distance in the second direction is S8, where (S8-S7)/S7 is greater than or equal to 0 and less than or equal to 0.2.
  • the plurality of first via hole contact portions includes a first real hole contact portion
  • the plurality of second via hole contact portions includes a second real hole contact portion and a second through hole contact portion.
  • Virtual hole contact portion; the first real hole contact portion and the corresponding second real hole contact portion are connected through via holes, and the second virtual hole contact portion and its orthogonal projection on the base substrate
  • the first signal lines are insulated and arranged to intersect.
  • the plurality of first via hole contact portions further include a first dummy hole contact portion, and the first dummy hole contact portion and the corresponding second dummy hole contact portion Insulation settings.
  • the display panel includes: a first flat layer, the first flat layer is located between the first source and drain layer and the second source and drain layer, the first flat layer The thickness is less than or equal to 1.6um.
  • the display panel further includes: a passivation layer and a first flat layer.
  • the passivation layer is located between the conductive layer where the first signal line is located and the conductive layer where the second signal line is located. between; the first flat layer is located between the passivation layer and the conductive layer where the second signal line is located; wherein a first opening is formed on the first flat layer, and the first opening is the substrate.
  • the orthographic projection on the substrate at least partially overlaps the orthographic projection of the second virtual hole contact portion on the base substrate.
  • the display panel further includes: a passivation layer and a first flat layer.
  • the passivation layer is located between the conductive layer where the first signal line is located and the conductive layer where the second signal line is located. between; the first flat layer is located between the passivation layer and the conductive layer where the second signal line is located; wherein, a second opening is formed on the passivation layer, and the second opening is located between the passivation layer and the conductive layer where the second signal line is located.
  • the orthographic projection on the base substrate at least partially overlaps the orthographic projection of the second virtual hole contact portion on the base substrate.
  • the size of the orthographic projection of the break between the first data fan-out line and the first analog line on the substrate in the first direction is 1.5um- 3.5um; and/or, the size of the orthographic projection of the break between the second data fan-out line and the second analog line on the substrate in the second direction is 1.5um-3.5um.
  • the data lines whose orthographic projections on the substrate are located on adjacent sides of the second signal line include a third extension, a fourth extension, and a fifth extension. part, the fourth extension part is connected between the third extension part and the fifth extension part; at least part of the structure of the second via hole contact part and the fourth extension part is on the first direction, and the dimensions of the orthographic projection of the fourth extension portion on the base substrate and the orthographic projection of the second extension portion on the base substrate in the first direction are larger than the The dimensions of the orthographic projection of the third extension portion on the base substrate and the orthographic projection of the second extension portion on the base substrate in the first direction, and the fourth extension portion is The size of the orthographic projection on the base substrate and the orthographic projection of the second extension portion on the base substrate in the first direction is larger than the orthogonal projection of the fifth extension portion on the base substrate. The projection and the dimension of the orthographic projection of the second extension portion on the base substrate in the first direction.
  • the display panel further includes a pixel driving circuit and a light-emitting unit.
  • the pixel driving circuit is connected to the first electrode of the light-emitting unit.
  • the display panel further includes: an electrode layer. Located on one side of the base substrate, the electrode layer includes a plurality of electrode parts, the electrode parts are used to form the first electrode of the light-emitting unit; the first data fan-out line and the first analog line.
  • the orthographic projection of the fracture on the base substrate does not overlap with the orthographic projection of the electrode portion on the base substrate; and/or, the second data fan-out line and the second analog
  • the orthographic projection of the fracture between the lines on the base substrate and the electrode portion are The orthographic projections on the base substrate do not overlap.
  • the display panel further includes a pixel driving circuit and a light-emitting unit.
  • the pixel driving circuit is connected to the first electrode of the light-emitting unit.
  • the display panel further includes: an electrode layer. Located on one side of the base substrate, the electrode layer includes a plurality of electrode parts, the electrode parts are used to form the first electrode of the light-emitting unit; the first via contact part is on the base substrate.
  • the orthographic projection of the second via hole contact portion on the base substrate and the orthographic projection of the electrode portion on the substrate do not overlap. Orthographic projections on the base substrate do not overlap.
  • the display panel further includes a plurality of pixel driving circuits and a plurality of light-emitting units, and the plurality of pixel driving circuits are array-distributed along the first direction and the second direction,
  • the pixel driving circuit is connected to the first electrode of the light-emitting unit;
  • the pixel driving circuit includes a driving transistor, a sixth transistor, and a seventh transistor, and the first electrode of the sixth transistor is connected to the second electrode of the driving transistor.
  • the second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit, the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode of the seventh transistor is connected to the light-emitting unit. the first electrode.
  • the display panel also includes: a first active layer and a first gate layer.
  • the first active layer is located on one side of the base substrate.
  • the first active layer includes a sixth active part and a seventh active part. Active part, the sixth active part is used to form a channel region of the sixth transistor, the seventh active part is used to form a channel region of the seventh transistor;
  • the first gate layer is located The side of the first active layer facing away from the base substrate, the first gate layer including an enable signal line and a second reset signal line, the enable signal line on the base substrate
  • the orthographic projection extends along the first direction and covers the orthographic projection of the sixth active part on the base substrate, and the orthographic projection of the second reset signal line on the base substrate extends along the first direction.
  • One direction extends and covers the orthographic projection of the seventh active part on the base substrate; wherein the first direction is the row direction, and the orthographic projection of the first signal line on the base substrate It is located between the orthographic projection of the enable signal line on the base substrate and the orthographic projection of the second reset signal line on the base substrate in the same row of pixel driving circuits.
  • the display panel further includes a plurality of pixel driving circuits and a plurality of light-emitting units, and the plurality of pixel driving circuits are array-distributed along the first direction and the second direction,
  • the pixel driving circuit is connected to the first electrode of the light-emitting unit;
  • the pixel driving circuit includes a driving transistor, a sixth transistor, and a first transistor.
  • the sixth transistor has The first electrode is connected to the second electrode of the driving transistor, the second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit, the first electrode of the first transistor is connected to the first initial signal line, and the The second electrode of the first transistor is connected to the gate of the driving transistor.
  • the display panel also includes: a first gate layer and a second gate layer.
  • the first gate layer is located on one side of the base substrate.
  • the first gate layer includes an enable signal line.
  • the enable signal line The partial structure of the signal line is used to form the gate of the sixth transistor; the second gate layer is located on the side of the first gate layer facing away from the base substrate, and the second gate layer includes the The first initial signal line; the orthographic projection of the first extension part of the first signal line on the base substrate is located in the pixel driving circuit of this row.
  • the first initial signal line is on the base substrate. between the front projection and the front projection of the enable signal line in the adjacent next row of pixel driving circuits on the base substrate.
  • the display panel includes a plurality of repeating units distributed in an array in the first direction and the second direction, and the repeating units include n rows and m columns of sub-repeating units, n, m is a positive integer greater than or equal to 1;
  • the sub-repeating unit includes two pixel driving circuits distributed adjacently in the first direction, and the two pixel driving circuits in the same sub-repeating unit are arranged in mirror symmetry; in the A plurality of the repeating units distributed in the second direction form a repeating unit column, and one of the second signal lines is provided between two adjacent repeating unit columns in the first direction; in the first A plurality of the repeating units distributed in the direction form a repeating unit row, and each of the repeating unit rows is provided with one first signal line.
  • the display panel further includes a light-emitting unit, the pixel driving circuit is connected to the first electrode of the light-emitting unit, the display panel further includes an electrode layer, and the electrode layer includes a plurality of electrodes. part, the electrode part is used to form the first electrode of the light-emitting unit; wherein, in the two adjacent sub-repeating units in the first direction, the two adjacent data lines are on the base substrate
  • the orthographic projection on the second signal line intersects the orthographic projection of the same electrode portion on the base substrate, and is located on both sides of the orthographic projection of the second signal line on the base substrate.
  • m is a positive integer greater than or equal to 2; in the adjacent repeating unit columns in the first direction, two adjacent data lines are on the substrate.
  • the minimum distance of the orthographic projection in the first direction is L1; in the two sub-repeating units located in the same repeating unit and adjacent in the first direction, two adjacent data lines
  • the minimum distance of the orthographic projection on the base substrate in the first direction is L2; where L1 is greater than L2.
  • n is a positive integer greater than or equal to 2; the display panel further includes a light-emitting unit, and the pixel driving circuit includes a driving transistor, a sixth transistor, and a seventh transistor.
  • the sixth transistor The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit, the gate electrode of the sixth transistor is connected to the enable signal line, and the gate electrode of the sixth transistor is connected to the enable signal line.
  • the first electrode of the seventh transistor is connected to the second initial signal line, the second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit, and the gate electrode of the seventh transistor is connected to the second reset signal line; the same
  • the repeating unit row includes a first pixel driving circuit row including a plurality of pixel driving circuits distributed along the first direction and a second pixel driving circuit row including A plurality of pixel driving circuits distributed along the first direction; the orthographic projection of the first signal line on the substrate is located in the first pixel driving circuit row and the enable signal line is on the substrate.
  • the minimum distance in the second direction between the orthographic projection of the energy signal line on the base substrate and the orthographic projection of the second reset signal line on the base substrate is L3; in the second pixel In the driving circuit row, the minimum distance in the second direction between the orthographic projection of the enable signal line on the base substrate and the orthographic projection of the second reset signal line on the base substrate is L4; among them, L3 is larger than L4.
  • the display panel includes a pixel driving circuit and a light-emitting unit.
  • the pixel driving circuit includes a driving transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, and a sixth transistor. , seventh transistor, capacitor; the first electrode of the first transistor is connected to the first initial signal line, and the second electrode is connected to the gate electrode of the driving transistor; the first electrode of the second transistor is connected to the gate electrode of the driving transistor.
  • the gate electrode, the second electrode is connected to the second electrode of the driving transistor; the first electrode of the fourth transistor is connected to the data line, and the second electrode is connected to the first electrode of the driving transistor; the fifth transistor The first pole is connected to the power line, the second pole is connected to the first pole of the driving transistor; the first pole of the sixth transistor is connected to the second pole of the driving transistor, and the second pole is connected to the first pole of the light-emitting unit. electrode; the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode is connected to the first electrode of the light-emitting unit; the first electrode of the capacitor is connected to the gate of the driving transistor, and the second electrode Connect the power cord.
  • the display panel further includes: a first active layer, a first gate layer, a second active layer, and a third gate layer.
  • the first active layer is located on one side of the substrate base,
  • the first active layer includes a third active part, a fourth active part, a fifth active part, a sixth active part and a seventh active part, and the third active part is used to form the A channel region of a driving transistor, the fourth active portion is used to form a channel region of the fourth transistor, the fifth active portion is used to form a channel region of the fifth transistor, and the third active portion is used to form a channel region of the fifth transistor.
  • the six active parts are used to form the channel region of the sixth transistor, the seventh active part is used to form the channel region of the seventh transistor; the first gate layer is located on the first active layer On the side away from the substrate, the first gate layer includes a first gate line, an enable signal line, a second reset signal line, and a first conductive part.
  • the first gate line is on the substrate.
  • the orthographic projection on the substrate extends along the first direction and covers the orthographic projection of the fourth active part on the substrate substrate, and the orthographic projection of the enable signal line on the substrate substrate extends along the The first direction extends and covers the orthographic projection of the fifth active part on the base substrate and the orthographic projection of the sixth active part on the base substrate, and the second reset signal line
  • An orthographic projection on the base substrate extends along the first direction and covers an orthographic projection of the seventh active portion on the base substrate, and the first conductive portion is on the base substrate
  • the orthographic projection covers the orthographic projection of the third active part on the base substrate; the second active layer is located on the side of the first gate layer facing away from the base substrate, and the second active layer
  • the source layer includes a first active part and a second active part.
  • the first active part is used to form a channel region of the first transistor.
  • the second active part is used to form the second transistor. channel region;
  • the third gate layer is located on the side of the second active layer facing away from the base substrate, the third gate layer includes a second gate line and a first reset signal line, and the third gate layer includes a second gate line and a first reset signal line.
  • the orthographic projection of the two gate lines on the base substrate extends along the first direction and covers the orthographic projection of the second active part on the base substrate, and the first reset signal line is on the
  • the orthographic projection on the base substrate extends along the first direction and covers the orthographic projection of the first active part on the base substrate; wherein the second reset signal line is on the base substrate
  • the orthographic projection of the enable signal line on the base substrate, the orthographic projection of the first conductive part on the base substrate, the orthographic projection of the second gate line on the base substrate , the orthographic projection of the first gate line on the base substrate, and the orthographic projection of the first reset signal line on the base substrate are sequentially distributed along the second direction.
  • the first direction is the row direction
  • the second direction is the column direction
  • the first gate line in the pixel driving circuit of this row is multiplexed into the pixel driving circuit of the adjacent row.
  • the second reset signal line is the first direction.
  • the transistor, the sixth transistor, and the seventh transistor are P-type transistors
  • the first transistor and the second transistor are N-type transistors.
  • the second signal line includes a plurality of second via contact portions, and the orthographic projection of the plurality of second via contact portions on the substrate is along the first line.
  • the orthographic projection of two adjacent second via hole contact portions on the substrate in the second direction in the second direction The distance is A1
  • the orthographic projection of the break between the second data fan-out line and the second analog line on the substrate substrate in the second direction is A2;
  • A1/A2 is greater than or equal to 27 and Less than or equal to 68.
  • a display device which includes the above-mentioned display panel.
  • Figure 1 is a schematic structural diagram of an exemplary embodiment of a display panel of the present disclosure
  • Figure 2 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • Figure 3 is a partial enlarged view of the first area K1 in Figure 2;
  • Figure 4 is a partial structural layout of the conductive layer where the first signal line is located in Figure 3;
  • Figure 5 is a partial structural layout of the conductive layer where the second signal line is located in Figure 3;
  • Figure 6 is a partial enlarged view of the second area K2 in Figure 2;
  • Figure 7 is a partial structural layout of the conductive layer where the first signal line is located in Figure 6;
  • Figure 8 is a partial structural layout of the conductive layer where the second signal line is located in Figure 6;
  • Figure 9 is a partial enlarged view of the third area K3 in Figure 2;
  • Figure 10 is a partial structural layout of the conductive layer where the first signal line is located in Figure 9;
  • Figure 11 is a partial structural layout of the conductive layer where the second signal line is located in Figure 9;
  • Figure 12 is a partial enlarged view of the fourth area K4 in Figure 2;
  • Figure 13 is a partial structural layout of the conductive layer where the first signal line is located in Figure 12;
  • Figure 14 is a partial structural layout of the conductive layer where the second signal line is located in Figure 12;
  • Figure 15 is a partial enlarged view of the fifth area K5 in Figure 2;
  • Figure 16 is a partial structural layout of the conductive layer where the first signal line is located in Figure 15;
  • Figure 17 is a partial structural layout of the conductive layer where the second signal line is located in Figure 15;
  • Figure 18 is a partial enlarged view of the sixth area K6 in Figure 2;
  • Figure 19 is a partial structural layout of the conductive layer where the first signal line is located in Figure 18;
  • Figure 20 is a partial structural layout of the conductive layer where the second signal line is located in Figure 18;
  • Figure 21 is a partial enlarged view of the seventh area K7 in Figure 2;
  • Figure 22 is a structural layout of the conductive layer where the first signal line is located in Figure 21;
  • Figure 23 is a structural layout of the conductive layer where the second signal line is located in Figure 21;
  • Figure 24 is a structural layout of another exemplary embodiment of a display panel of the present disclosure.
  • Figure 25 is a structural layout of the conductive layer where the first signal line is located in Figure 24;
  • Figure 26 is a structural layout of the conductive layer where the second signal line is located in Figure 24;
  • Figure 27 is a structural layout of the electrode layer in Figure 24;
  • Figure 28 is a partial cross-sectional view of the display panel shown in Figure 3 along the dotted line CC;
  • Figure 29 is a schematic structural diagram of another exemplary embodiment of the display panel of the present disclosure.
  • Figure 30 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • Figure 31 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • Figure 32 is a schematic circuit structure diagram of the pixel driving circuit in the display panel of the present disclosure.
  • Figure 33 is a timing diagram of each node in a driving method of the pixel driving circuit in Figure 32;
  • Figure 34 is a partial layout of the sixth area K6 in Figure 2;
  • Figure 35 is the structural layout of the occlusion layer in Figure 34;
  • Figure 36 is a structural layout of the first active layer in Figure 34;
  • Figure 37 is a structural layout of the first gate layer in Figure 34;
  • Figure 38 is a structural layout of the second gate layer in Figure 34;
  • Figure 39 is a structural layout of the second active layer in Figure 34;
  • Figure 40 is a structural layout of the third gate layer in Figure 34;
  • Figure 41 is a structural layout of the first source and drain layer in Figure 34;
  • Figure 42 is a structural layout of the second source and drain layer in Figure 34;
  • Figure 43 is the structural layout of the electrode layer in Figure 34;
  • Figure 44 is a structural layout of the occlusion layer and the first active layer in Figure 34;
  • Figure 45 is a structural layout of the shielding layer, the first active layer, and the first gate layer in Figure 34;
  • Figure 46 is a structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in Figure 34;
  • Figure 47 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in Figure 34;
  • Figure 48 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer and the third gate layer in Figure 34;
  • Figure 49 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer and the first source and drain layer in Figure 34;
  • Figure 50 shows the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source and drain layer, and the second source and drain layer in Figure 34 structural layout;
  • Figure 51 is the structural layout of a single repeating unit in Figure 34;
  • Figure 52 is the structural layout of the occlusion layer in Figure 51;
  • Figure 53 is a structural layout of the first active layer in Figure 51;
  • Figure 54 is a structural layout of the first gate layer in Figure 51;
  • Figure 55 is a structural layout of the second gate layer in Figure 51;
  • Figure 56 is a structural layout of the second active layer in Figure 51;
  • Figure 57 is a structural layout of the third gate layer in Figure 51;
  • Figure 58 is a structural layout of the first source and drain layer in Figure 51;
  • Figure 59 is a structural layout of the second source and drain layer in Figure 51;
  • Figure 60 is the structural layout of the electrode layer in Figure 51;
  • Figure 61 is a structural layout of the shielding layer and the first active layer in Figure 51;
  • Figure 62 is a structural layout of the shielding layer, the first active layer, and the first gate layer in Figure 51;
  • Figure 63 is a structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in Figure 51;
  • Figure 64 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in Figure 51;
  • Figure 65 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer and the third gate layer in Figure 51;
  • Figure 66 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source and drain layer in Figure 51;
  • Figure 67 shows the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source and drain layer, and the second source and drain layer in Figure 51 structural layout;
  • FIG. 68 is a partial cross-sectional view of the display panel shown in FIG. 51 taken along the dotted line EE.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments. To those skilled in the art.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • FIG. 1 it is a schematic structural diagram of an exemplary embodiment of a display panel of the present disclosure.
  • the display panel may include a display area AA, and a fan-out area FT located in the display area AA.
  • the display panel also includes a base substrate, a plurality of data lines Da, a first data fan-out line Fa1, and a second data fan-out line Fa2.
  • the data line Da is located in the display area AA
  • the orthographic projection of the data line Da on the substrate is distributed at intervals along the first direction X and extends along the second direction Y.
  • the first direction X and the second direction Y may intersect. , for example, the first direction X may be the row direction, and the second direction Y may be the column direction.
  • the first data fan-out line Fa1 is located in the fan-out area FT.
  • the orthographic projection of the first data fan-out line Fa1 on the substrate may be distributed at intervals along the second direction Y and extend along the first direction X.
  • a data fan-out line Fa1 is provided corresponding to the data line Da, and the first data fan-out line Fa1 is connected to the corresponding data line Da.
  • the second data fan-out lines Fa2 are located in the fan-out area FT.
  • the orthographic projections of the second data fan-out lines Fa2 on the substrate are spaced apart along the first direction X and extend along the second direction Y.
  • the second data fan-out lines Fa2 corresponds to the first data fan-out line Fa1 It is provided that the second data fan-out line Fa2 is connected to the corresponding first data fan-out line Fa1.
  • the display panel provided by this exemplary embodiment sets the fan-out area in the display area, avoiding setting the fan-out area in the frame area, thereby reducing the area of the lower frame and lower corner area of the display panel, that is, achieving a narrow frame setting.
  • the dividing line XX divides the display area AA into two display areas distributed in the first direction X.
  • the data line Da on the side far away from the dividing line XX is connected to the second data fan-out line Fa2 on the side close to the dividing line XX through the first data fan-out line Fa1.
  • the fan-out area FT may include a first fan-out area FT1 and a second fan-out area FT2.
  • the first data fan-out line Fa1 is located in the first fan-out area FT1
  • the second data fan-out line Fa2 is located in the second fan-out area FT2.
  • the first fan-out area FT1 may include a first sub-fan-out area FT11 and a second sub-fan-out area FT12.
  • the first sub-fan-out area FT11 and the second sub-fan-out area FT12 are located in the second fan-out area FT2 in the first direction. X on both sides.
  • the first data fan-out line Fa1 and the second data fan-out line Fa2 may also be arranged in other ways.
  • the data line Da on the side close to the separation line XX is connected to the second data fan-out line Fa2 on the side close to the separation line XX through the first data fan-out line Fa1; or, the data line Da on the side far away from the separation line XX passes through the first data fan-out line Fa2.
  • the fan-out line Fa1 is connected to the second data fan-out line Fa2 on the side away from the separation line XX.
  • the length of the first data fan-out line Fa1 may also gradually increase from the upper frame to the lower frame.
  • the display panel is provided with a first data fan-out line Fa1 and a second data fan-out line Fa2 in the fan-out area FT, and the first data fan-out line Fa1 and the second data fan-out line are not provided in the display area outside the fan-out area FT.
  • Fan-out line Fa2 Since the first data fan-out line Fa1 and the second data fan-out line Fa2 have light-reflecting and light-shielding effects, when the display panel is in the screen-off state, the fan-out area of the display panel and other display areas have different light-reflecting and light-transmitting effects, resulting in a display A dark shadow appears on the panel.
  • this exemplary embodiment also provides another display panel, as shown in FIG. 2 , which is a schematic structural diagram of another exemplary embodiment of the display panel of the present disclosure.
  • the display panel may include a plurality of first signal lines H1 and a plurality of second signal lines V2.
  • the first signal line H1 is located in the display area AA, and the orthographic projection of the first signal line H1 on the substrate extends along the first direction X and is spaced apart along the second direction Y,
  • the plurality of first signal lines H1 include a first sub-signal line H11 and a third analog line Dm3.
  • the first sub-signal line H11 includes a first data fan-out line Fa1 and a first analog line Dm1 arranged at intervals; a third analog line Dm3 is located in the display area AA outside the first fan-out area FT1.
  • the second signal line V2 is located in the display area AA, and the second signal line V2 is located in the display area AA.
  • the signal line V2 and the first signal line H1 are located on different conductive layers.
  • the orthographic projection of the second signal line V2 on the base substrate extends along the second direction Y and is spaced apart along the first direction X.
  • the plurality of second signal lines V2 include second sub-signal lines V22 and fourth analog lines Dm4.
  • the second sub-signal line V22 includes a second data fan-out line Fa2 and a second analog line Dm2 arranged at intervals; a fourth analog line Dm4 is located in the display area AA outside the second fan-out area FT2.
  • this exemplary embodiment can make the density of signal lines in the entire display area AA close to Consistent, thus solving the technical problem of Shadow mentioned above. It should be noted that when the first data fan-out line Fa1 and the second data fan-out line Fa2 are distributed in other ways, the present disclosure can also eliminate the above shadow by adding analog lines.
  • the plurality of first signal lines H1 may be located on the same conductive layer, and the plurality of second signal lines V2 may be located on the same conductive layer; the conductive layer where the second signal line V2 is located may be located on any
  • the first signal line H1 is located on a side of the conductive layer facing away from the base substrate.
  • the first signal line H1 may be located on the first source-drain layer of the display panel, and the second signal line V2 may be located on the second source-drain layer of the display panel.
  • the data line Da may also be located on the second source-drain layer of the display panel, and the orthographic projection of the second signal line V2 on the base substrate may be located on the center of the two adjacent data lines Da on the base substrate. between orthographic projections.
  • first signal line and the second signal line may also be located on other conductive layers.
  • first signal line may also be located on the first gate layer, the second gate layer in the display panel.
  • the gate layer, the third gate layer, the first signal line and the second signal line can also be located on the additional conductive layer.
  • first signal line and the second signal line can also be located on the same conductive layer.
  • Figure 3 is a partially enlarged view of the first area K1 in Figure 2
  • Figure 4 is a partial structural layout of the conductive layer where the first signal line is located in Figure 3
  • Figure 5 is a partial structural layout of the conductive layer where the first signal line is located in Figure 3. 2.
  • the first area K1 is partially located in the first sub-fan-out area FT11
  • the first area K1 is partially located in the second fan-out area FT2
  • the first area K1 is partially located in the first sub-fan-out area FT11 away from the second fan-out area FT2. display area.
  • the first data fan-out line Fa1 can be connected to the data line Da through the via hole H, and connected to the second data fan-out line Fa2 through the via hole H.
  • the black circle in Figure 2 represents the location of the via hole
  • the black square in Figure 3 represents the location of the via hole.
  • FIG. 6 is a partially enlarged view of the second area K2 in Figure 2
  • Figure 7 FIG. 6 is a partial structural layout of the conductive layer where the first signal line is located.
  • FIG. 8 is a partial structural layout of the conductive layer where the second signal line is located in FIG. 6 .
  • the second area K2 is located in the display area of the first sub-fan-out area FT11 away from the second fan-out area FT2.
  • the fourth analog line Dm4 is connected through the via hole H to the first analog line Dm1 that intersects its orthographic projection on the base substrate.
  • the black square in Figure 6 indicates the location of the via.
  • the display area of the second sub-fan-out area FT12 away from the second fan-out area FT2 may have the same structure as the second area K2.
  • Figure 9 is a partial enlarged view of the third area K3 in Figure 2
  • Figure 10 is a partial structural layout of the conductive layer where the first signal line is located in Figure 9
  • Figure 11 is a partial structural layout of the conductive layer where the first signal line is located in Figure 9. 2.
  • the third area K3 is located in the first sub-fan-out area FT11.
  • the first data fan-out line Fa1 is not connected to the second analog line Dm2 and the fourth analog line Dm4 that intersect with its orthographic projection on the base substrate.
  • the structures of the first sub-fan-out area FT11 and the second sub-fan-out area FT12 may be the same.
  • Figure 12 is a partial enlarged view of the fourth area K4 in Figure 2
  • Figure 13 is a partial structural layout of the conductive layer where the first signal line is located in Figure 12
  • Figure 14 is a partial structural layout of the conductive layer in Figure 12 2. Partial structural layout of the conductive layer where the signal line is located.
  • the fourth area K4 is located in the second fan-out area FT2.
  • the second data fan-out line Fa2 is not connected to the first analog line Dm1 that intersects its orthographic projection on the base substrate.
  • Figure 15 is a partially enlarged view of the fifth area K5 in Figure 2
  • Figure 16 is a partial structural layout of the conductive layer where the first signal line is located in Figure 15
  • Figure 17 is a partial structural layout of the conductive layer where the first signal line is located in Figure 15. 2.
  • the fifth area K5 is located at the middle position of the second fan-out area FT2 in the first direction X.
  • the second signal lines V2 also include a fifth analog line Dm5.
  • the fifth analog line Dm5 connects the first analog line Dm1 and the third analog line Dm3 that intersect with its orthographic projection on the base substrate through via holes.
  • the black square in Figure 15 indicates the location of the via hole.
  • Figure 18 is a partial enlarged view of the sixth area K6 in Figure 2
  • Figure 19 is a partial structural layout of the conductive layer where the first signal line is located in Figure 18
  • Figure 20 is a partial structural layout of the conductive layer in Figure 18 2.
  • the sixth area K6 is located in the display area on the side of the fan-out area away from the lower frame of the display panel.
  • the sixth area K6 in the sixth area K6, the The three analog lines Dm3 are connected to the fourth analog line Dm4 that intersects its orthographic projection on the base substrate through via holes.
  • the black square in Figure 18 indicates the location of the via holes.
  • the minimum distance in the second direction Y between the orthographic projections of two adjacent first signal lines H1 on the substrate is S1.
  • the maximum distance between the orthographic projections of two adjacent first signal lines H1 on the substrate in the second direction Y is S2, where (S2-S1)/S1 can be greater than or equal to 0 and less than or equal to 0.2 , for example, (S2-S1)/S1 can be equal to 0, 0.05, 0.1, 0.2, etc.
  • (S2-S1)/S1 is equal to 0, that is, the orthographic projection of the first signal line H1 on the substrate is equally spaced in the second direction Y.
  • the minimum distance between the orthographic projections of two adjacent second signal lines V2 on the substrate in the first direction X is S3.
  • the maximum distance of the orthographic projection of line V2 on the substrate in the first direction X is S4, where (S4-S3)/S3 is greater than or equal to 0 and less than or equal to 0.2, for example, (S4-S3) /S3 can be equal to 0, 0.05, 0.1, 0.2, etc.
  • (S4-S3)/S3 is equal to 0, that is, the orthographic projection of the second signal line V2 on the substrate is equally spaced in the first direction X. This arrangement can make the first signal line H1 and the second signal line V2 evenly distributed in the display area, thereby further eliminating the above-mentioned dark shadow problem.
  • the display panel may further include a pixel driving circuit and a light-emitting unit, and the pixel driving circuit is connected to the first electrode of the light-emitting unit.
  • the display panel may further include: a common electrode layer used to form a second electrode of the light emitting unit.
  • the first analog line Dm1, the second analog line Dm2, the third analog line Dm3, and the fourth analog line Dm4 may be connected to the common electrode layer.
  • the first analog line Dm1, the second analog line Dm2, the third analog line Dm3, and the fourth analog line Dm4 may be connected to the common electrode layer through via holes located in the frame area around the display area.
  • the first analog line Dm1, the second analog line Dm2, the third analog line Dm3, and the fourth analog line Dm4 forming a grid structure can reduce the resistance of the common electrode layer itself, thereby reducing the luminescence at different positions of the display panel.
  • the voltage difference between the second electrode of the unit and this setting can improve the uniformity of display on the display panel.
  • Figure 21 is a partially enlarged view of the seventh area K7 in Figure 2
  • Figure 22 is the structural layout of the conductive layer where the first signal line is located in Figure 21
  • Figure 23 is where the second signal line is located in Figure 21
  • Conductive layer structure layout As shown in Figure 2, the display panel may further include a frame area BB located around the display area AA.
  • the frame area BB includes a first frame area BB1 and a second frame area BB2 arranged oppositely.
  • the fan-out The area FT is located on the side close to the second frame area BB2.
  • the display panel may also include an electrode ring VSS and a power circuit (not shown).
  • the electrode ring VSS is located in the frame area BB.
  • the electrode ring VSS can be a ring-shaped structure located in the frame area BB.
  • the electrode ring VSS can be connected to the common electrode layer at different positions.
  • the partial structure of the electrode ring VSS located in the first frame area BB1 is connected to the second analog line Dm2 and the fourth analog line Dm4.
  • the power circuit can be bound to the second frame area BB2, and the power circuit is connected to at least part of the structure of the electrode ring VSS located in the second frame area BB2, and the power circuit can be used to provide power to the electrode ring VSS.
  • VSS provides the power signal.
  • the common electrode layer on the side away from the power circuit has a large voltage drop. This application provides power voltage to the second analog line Dm2 and the fourth analog line Fm4 through the electrode ring VSS located in the first frame area BB1, thereby reducing the voltage drop.
  • the electrode ring VSS may include a first electrode ring 4VSS and a second electrode ring 5VSS, the orthographic projection of the first electrode ring 4VSS on the substrate and the orthographic projection of the second electrode ring 5VSS on the substrate.
  • the orthographic projection at least partially overlaps, and the second electrode ring 5VSS is connected to the first electrode ring 4VSS through a via hole.
  • the black square in Figure 21 indicates the location of the via hole.
  • the electrode ring with a double conductive layer can reduce the self-resistance of the electrode ring.
  • a power connection line VDDx may also be provided in the first frame area B1.
  • the power connection line VDDx may include a first power connection line 4VDD and a second power connection line 5VDD.
  • the first power connection line 4VDD and the second power connection line 5VDD are in the lining.
  • the front projections on the base substrate at least partially overlap, and the first power connection line 4VDD and the second power connection line 5VDD are connected through via holes.
  • the power connection line VDDx can be connected to the power line VDD located in the display area.
  • the first signal line H1 may include a plurality of first via contact portions Ht1 and a first extension portion Lt1.
  • the plurality of first via hole contact portions The orthographic projection of Ht1 on the base substrate is spaced apart along the first direction X, the first extension part Lt1 is connected to the first via contact part Ht1, and the first via contact part Ht1 is in The size of the orthogonal projection on the base substrate in the second direction Y is larger than the size of the first extension part Lt1 on the base substrate in the second direction Y.
  • the second signal line V2 may include a plurality of second via contact portions Ht2 and a second extension portion Lt2, and the orthographic projection of the plurality of second via contact portions Ht2 on the base substrate is along the first line.
  • the second extension portion Lt2 is connected to the second via hole contact portion Ht2, and the orthographic projection of the second via hole contact portion Ht2 on the base substrate is in the first direction.
  • the size in X is larger than the size in the first direction X of the orthogonal projection of the second extension part Lt2 on the base substrate.
  • the first via hole contact portion Ht1 and the second via hole contact portion Ht2 are provided correspondingly, and the orthographic projection of the first via hole contact portion Ht1 on the base substrate and the corresponding second via hole Orthographic projections of the contact portion Ht2 on the base substrate at least partially overlap.
  • the first via hole contact portion Ht1 may include a first real hole contact portion Htr1 and a first virtual hole contact portion Htd1
  • the second via hole contact portion Ht2 may include a second real hole.
  • the first real hole contact portion Htr1 and the corresponding second real hole contact portion Htr2 are connected through via holes, that is, the first signal line H1 and the second signal line V2 can pass through the first real hole contact portion Htr1 and the second real hole contact portion Htr2.
  • the two real hole contact parts Htr2 are connected through holes.
  • the first dummy hole contact portion Htd1 and the corresponding second dummy hole contact portion Htd2 are insulated.
  • the first virtual hole contact portion Htd1 can simulate the reflection phenomenon of the first real hole contact portion Htr1, and the second virtual hole contact portion Htd2 can simulate the reflection phenomenon of the second real hole contact portion Htr2. Therefore, the first virtual hole contact portion Htd1 and the second virtual hole contact portion Htd2 can improve the shadow problem under the screen of the display panel.
  • the first virtual hole contact portion Htd1 can simulate the parasitic capacitance of the first real hole contact portion Htr1
  • the second virtual hole contact portion Htd2 can simulate the parasitic capacitance of the second real hole contact portion Htr2, so that the first virtual hole contact portion Htd1 .
  • the second virtual hole contact portion Htd2 can improve the display uniformity of the display panel.
  • the orthographic projections of the first dummy hole contact portion Htd1 and the second dummy hole contact portion Htd2 on the base substrate overlap. Therefore, from the perspective of reflection, the display panel can optionally provide the first dummy hole contact portion Htd1 or the second dummy hole contact portion Htd2.
  • the minimum distance in the first direction X between the orthographic projection of the adjacent first via contact portion Ht1 on the substrate is S5
  • the maximum distance of the orthographic projection of the adjacent first via contact portion Ht1 on the base substrate in the first direction Equal to 0.2, for example, (S6-S5)/S5 can be equal to 0, 0.05, 0.1, 0.2, etc.
  • (S6-S5)/S5 is equal to 0, the orthographic projection of the first via hole contact portion Ht1 on the base substrate is equally spaced in the first direction X.
  • the first via contact portions Ht1 distributed at equal intervals can further improve the shadow problem under the display panel.
  • the minimum distance of the orthographic projection of the adjacent second via hole contact portion Ht2 on the substrate in the second direction Y is S7
  • (S8-S7)/S7 Can be equal to 0, 0.05, 0.1, 0.2, etc.
  • the display panel further includes a pixel driving circuit and a light-emitting unit.
  • the pixel driving circuit is connected to the first electrode of the light-emitting unit.
  • the display panel further includes a pixel for forming the first electrode of the light-emitting unit. electrode layer.
  • Figure 24 is a structural layout of another exemplary embodiment of the display panel of the present disclosure.
  • Figure 25 is a structural layout of the conductive layer where the first signal line is located in Figure 24.
  • Figure 26 is The structural layout of the conductive layer where the second signal line is located in Figure 24 is shown
  • Figure 27 is the structural layout of the electrode layer in Figure 24.
  • the electrode layer may include a plurality of electrode parts, and the plurality of electrode parts include a first electrode part R, a second electrode part B, and a third electrode part G.
  • the first electrode part R may be used to form the first electrode of the red light-emitting unit;
  • the second electrode part B may be used to form the first electrode of the blue light-emitting unit;
  • the third electrode part G may be used to form the first electrode of the green light-emitting unit.
  • the display panel further includes a pixel definition layer located on a side of the electrode layer facing away from the base substrate, and a pixel opening for forming a light-emitting unit is formed on the pixel definition layer.
  • the orthographic projection of the first electrode part R on the base substrate coincides with the orthographic projection of its corresponding pixel opening on the base substrate on the pixel definition layer
  • the orthographic projection of the third electrode part G on the base substrate coincides with the orthographic projection of its corresponding pixel opening on the base substrate.
  • the orthographic projection of the pixel opening on the base substrate coincides with the orthographic projection of the second electrode portion B on the base substrate and the orthographic projection of the corresponding pixel opening on the base substrate.
  • the orthographic projection of the break D1 between the first data fan-out line Fa1 and the first analog line Dm1 on the base substrate is the same as the orthographic projection of the electrode portion on the base substrate.
  • the orthographic projection of the break D2 between the second data fan-out line Fa2 and the second analog line Dm2 on the base substrate does not overlap with the orthographic projection of the electrode portion on the base substrate. Orthographic projections do not overlap. This arrangement can improve the flatness of the electrode portion, and a luminescent material layer with higher flatness can be formed on the electrode portion with higher flatness, thereby improving the uniformity of display on the display panel.
  • the first real hole contact portion Htr1 and the second real hole contact portion Htr2 are connected through a via hole.
  • the second real hole contact portion Htr2 will have a depression facing the substrate at the position of the via hole.
  • the hole contact part Htr2 will have a strong reflection phenomenon in the recessed position.
  • the second dummy hole contact portion Htd2 is relatively flat, the second dummy hole contact portion Htd2 has weak reflection, and the second dummy hole contact portion Htd2 is relatively flat.
  • Htd2 Inconsistent reflective capabilities with the second real hole contact portion Htr2 may easily cause dark shadows to appear on the display panel when the screen is off.
  • FIG. 28 it is a partial cross-sectional view of the display panel shown in FIG. 3 along the dotted line CC.
  • the first signal line is located on the first source and drain layer
  • the second signal line is located on the second source and drain layer.
  • the display panel may also include a passivation layer 97 and a first planar layer 98 located on one side of the base substrate 90.
  • the passivation layer 97 is located between the first source and drain layer and the second source and drain layer.
  • the first planarization layer 98 is located between the passivation layer 97 and the second source and drain layer.
  • the thickness of the first flat layer 98 is much greater than the thickness of the passivation layer 97 .
  • the depth of the recess of the second real hole contact portion Htr2 at the via hole position can be reduced by reducing the thickness of the passivation layer 97 and/or the first flat layer 98 , thereby improving the above shadow problem.
  • the thickness of the first flat layer 98 may be less than or equal to 1.6um.
  • the thickness of the first flat layer 98 may be 1.2um, 1.3um, 1.4um, 1.5um, or 1.6um; the passivation layer 97
  • the thickness of the passivation layer 97 may be 1000 angstroms to 5000 angstroms.
  • the thickness of the passivation layer 97 may be 1000 angstroms, 2000 angstroms, 3000 angstroms, 4000 angstroms, or 5000 angstroms.
  • FIG. 29 it is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure. Only the first flat layer 98 can be provided between the first source and drain layer and the second source and drain layer in the display panel. This arrangement can also reduce the depth of the depression of the second real hole contact portion Htr2 at the via hole position, thereby improving The aforementioned shadow issue.
  • FIG. 30 it is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • a first opening H3 is formed on the first flat layer 98 , and the orthographic projection of the first opening H3 on the base substrate is located where the second virtual hole contact portion Htd2 is located.
  • the orthographic projections on the substrate at least partially overlap.
  • This arrangement allows the second dummy hole contact portion Htd2 to form a groove facing the base substrate 90 , thereby improving the uniformity of light reflection in the display area by increasing the light reflection capability of the second dummy hole contact portion Htd2.
  • the first opening H3 may be an opening that penetrates the first flat layer 98 , or it may be a blind hole that does not penetrate the first flat layer 98 .
  • FIG. 31 it is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • a second opening H2 is formed on the passivation layer 97 , and the orthographic projection of the second opening H2 on the base substrate is in contact with the second virtual hole contact portion Htd2.
  • the orthographic projections on the base substrate at least partially overlap.
  • This arrangement allows the second dummy hole contact portion Htd2 to form a recessed groove facing the base substrate 90 , thereby improving the uniformity of light reflection in the display area by increasing the light reflection capability of the second dummy hole contact portion Htd2.
  • the second opening H2 may penetrate through the passivation layer 97
  • the opening may also be a blind hole that does not penetrate the passivation layer 97 .
  • the second via hole contact portion Ht2 since the orthographic projections of the first via hole contact portion Ht1 and the second via hole contact portion Ht2 on the base substrate overlap, the second via hole contact portion Ht2 has a higher resistance than other positions. bulge.
  • the first via hole contact portion Ht1 is formed in the The orthographic projection on the base substrate and the orthographic projection of the electrode portion on the base substrate do not overlap; the orthographic projection of the second via hole contact portion Ht2 on the base substrate and the electrode portion Orthographic projections on the base substrate do not overlap.
  • the data line Da includes a third extension part Lt3, a fourth extension part Lt4, and a fifth extension part Lt5.
  • the fourth extension part The portion Lt4 is connected between the third extension portion Lt3 and the fifth extension portion Lt5.
  • the data lines Da located on adjacent sides of the second signal line V2 refer to data lines with no other data lines between them and the second signal line V2.
  • At least part of the structures of the second via contact portion Ht2 and the fourth extension portion Lt4 are oppositely arranged in the first direction X, and the orthogonal projection of the fourth extension portion Lt4 on the substrate substrate.
  • the size of the orthographic projection of the second extension part Lt2 on the base substrate in the first direction The dimensions of the orthographic projection of the two extending portions Lt2 on the base substrate in the first direction X, the orthographic projection of the fourth extending portion Lt4 on the base substrate and the size of the second extending portion Lt2
  • the size of the orthographic projection on the base substrate in the first direction The dimension of the orthographic projection on the base substrate in the first direction X.
  • structure A and structure B are arranged oppositely in the first direction.
  • the size of the orthographic projection of the break D1 between the first data fan-out line Fa1 and the first analog line Dm1 on the substrate in the first direction X can be 1.5um-3.5um.
  • the size of the orthographic projection of the fracture D1 on the substrate in the first direction X can be 1.5um, 2um, 2.5um, 3um, 3.5um, etc.
  • the size in the second direction Y is 1.5um-3.5um.
  • the size of the orthographic projection of the fracture D2 on the substrate in the second direction Y is 1.5um, 2um, 2.5um, 3um, 3.5um, etc.
  • the orthographic projections of two adjacent second via hole contact portions Ht2 on the substrate in the second direction Y are on the third The distance Y in the two directions is A1, and the size of the orthographic projection of the break D2 between the second data fan-out line Fa2 and the second analog line Dm2 on the substrate in the second direction Y is A2;
  • A1/A2 can be greater than or equal to 27 and less than or equal to 68.
  • A1/A2 can be equal to 27, 28, 29, 35, 40, 54, 50, 55, 60, 65, 66, 67, etc.
  • the pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C.
  • the first electrode of the fourth transistor T4 is connected to the data signal terminal Da
  • the second electrode of the fourth transistor T4 is connected to the first electrode of the driving transistor T3, and the gate electrode of the fourth transistor T4 is connected to the first gate driving signal terminal G1
  • the first pole of the fifth transistor T5 is connected to the first power terminal VDD
  • the second pole of the fifth transistor T5 is connected to the first pole of the driving transistor T3, and the gate of the fifth transistor T5 is connected to the enable signal terminal EM
  • the gate is connected to the node N
  • the first electrode of the second transistor T2 is connected to the node N
  • the second electrode of the second transistor T2 is connected to the second electrode of the driving transistor T3, and the gate of the second transistor T2 is connected to the second gate driving signal terminal.
  • the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3
  • the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7
  • the gate electrode of the sixth transistor T6 is connected to the enable signal terminal EM.
  • the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate electrode of the seventh transistor T7 is connected to the second reset signal terminal Re2; the second electrode of the first transistor T1 is connected to the node N, and the first electrode of the first transistor T1
  • the first initial signal terminal Vinit1 is connected, the gate of the first transistor T1 is connected to the first reset signal terminal Re1; the first electrode of the capacitor C is connected to the node N, and the second electrode of the capacitor C is connected to the first power terminal VDD.
  • the pixel driving circuit can be connected to a light-emitting unit OLED.
  • the pixel driving circuit is used to drive the light-emitting unit OLED to emit light.
  • the first electrode of the light-emitting unit OLED can be connected to the second pole of the sixth transistor T6, and the second electrode of the light-emitting unit can be connected to The second power terminal VSS, the first of the light-emitting unit
  • the electrode may be the anode of the light-emitting unit
  • the second electrode of the light-emitting unit may be the cathode of the light-emitting unit.
  • the first transistor T1 and the second transistor T2 may be N-type transistors.
  • the first transistor T1 and the second transistor T2 may be N-type metal oxide transistors. N-type transistors have smaller leakage current, thereby avoiding In the light-emitting phase, node N leaks electricity through the first transistor T1 and the second transistor T2.
  • the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors.
  • the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 can be P-type low-temperature polycrystalline silicon transistors.
  • P-type transistors have high carrier mobility, which is conducive to achieving high resolution, high response speed, high pixel density, and high aperture ratio display. panel.
  • the first initial signal terminal and the second initial signal terminal may output the same or different voltage signals according to actual conditions.
  • FIG. 33 it is a timing diagram of each node in a driving method of the pixel driving circuit in Figure 32.
  • G1 represents the timing of the first gate drive signal terminal G1
  • G2 represents the timing of the second gate drive signal terminal G2
  • Re1 represents the timing of the first reset signal terminal Re1
  • Re2 represents the timing of the second reset signal terminal Re2.
  • EM represents the timing of the enable signal terminal EM
  • Da represents the timing of the data signal terminal Da.
  • the driving method of the pixel driving circuit may include a reset phase t1, a data writing phase t2, and a light emitting phase t3.
  • the first reset signal terminal Re1 outputs a high-level signal
  • the second reset signal terminal Re2 outputs a low-level signal
  • the first transistor T1 and the seventh transistor T7 are turned on
  • the first initial signal terminal Vinit1 is connected to the node N
  • the first initial signal is input
  • the second initial signal terminal Vinit2 inputs the second initial signal to the first electrode of the light-emitting unit OLED.
  • the second gate drive signal terminal G2 outputs a high-level signal
  • the first gate drive signal terminal G1 outputs a low-level signal
  • the fourth transistor T4 and the second transistor T2 are turned on, and at the same time the data signal
  • the terminal Da outputs the data signal to write the compensation voltage Vdata+Vth to the node N, where Vdata is the voltage of the data signal, and Vth is the threshold voltage of the driving transistor T3.
  • the enable signal terminal EM outputs a low-level signal
  • the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in the capacitor C.
  • the pixel driving circuit can avoid the influence of the driving transistor threshold on its output current. It should be understood that in other exemplary embodiments, the pixel driving circuit may also have other driving methods.
  • the seventh transistor T7 may drive the third pixel of the light-emitting unit during the period between the data writing stage t2 and the light-emitting stage t3. One electrode performs reset.
  • the display panel may include a base substrate, a shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, and a third gate layered in sequence. layer, a first source-drain layer, a second source-drain layer, and an electrode layer, wherein an insulating layer may be provided between the adjacent layers.
  • Figure 34 is a partial layout of the sixth area K6 in Figure 2
  • Figure 35 is a structural layout of the occlusion layer in Figure 34
  • Figure 36 is a structural layout of the first active layer in Figure 34
  • Figure 37 is the structural layout of the first gate layer in Figure 34
  • Figure 38 is the structural layout of the second gate layer in Figure 34
  • Figure 39 is the structural layout of the second active layer in Figure 34
  • Figure 40 is the structural layout of the second active layer in Figure 34
  • the structural layout of the third gate layer Figure 41 is the structural layout of the first source and drain layer in Figure 34
  • Figure 42 is the structural layout of the second source and drain layer in Figure 34
  • Figure 43 is the structural layout of the electrode layer in Figure 34
  • Figure 44 is the structural layout of the shielding layer and the first active layer in Figure 34
  • Figure 45 is the structural layout of the shielding layer, the first active layer and the first gate layer in Figure 34
  • Figure 46 is the shielding layer in Figure 34 layer, the first active layer, the first gate layer, and the second gate layer.
  • Figure 47 shows the shielding layer, the first active layer, the first gate layer, and the second gate layer in Figure 34.
  • the structural layout of the second active layer is the structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in Figure 34
  • Figure 49 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source and drain layer in Figure 34
  • Figure 50 is the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source and drain layer, and the second source and drain layer in Figure 34 Structural layout.
  • the display panel may include a plurality of pixel driving circuits shown in FIG. 32 .
  • the plurality of pixel driving circuits may include a first pixel driving circuit P1 and a second pixel driving circuit P2 adjacently distributed in the first direction X, and the first pixel driving circuit P1 and the second pixel driving circuit P2 It can be set in mirror symmetry using the mirror symmetry plane DD.
  • the mirror symmetry plane DD may be perpendicular to the substrate.
  • the orthographic projection of the first pixel driving circuit P1 on the base substrate and the orthographic projection of the second pixel driving circuit P2 on the base substrate are The projection can be arranged symmetrically with the intersection line of the mirror symmetry plane DD and the substrate as the symmetry axis.
  • the first pixel driving circuit P1 and the second pixel driving circuit P2 may form a sub-repeating unit, and the display panel may include a plurality of sub-repeating units distributed in an array in the first direction X and the second direction Y. Among them, four sub-repeating units distributed in a two-by-two array can form a repeating unit Pc.
  • Figure 51 is the structural layout of a single repeating unit in Figure 34
  • Figure 52 is the structural layout of the occlusion layer in Figure 51
  • Figure 53 is the structural layout of the first active layer in Figure 51
  • Figure 54 is the structural layout of the first gate layer in Figure 51
  • Figure 55 is the structural layout of the second gate layer in Figure 51
  • Figure 56 is the structural layout of the second active layer in Figure 51
  • Figure 57 is the structural layout of the second active layer in Figure 51
  • Figure 58 is the structural layout of the first source and drain layer in Figure 51.
  • Figure 59 is the structural layout of the second source and drain layer in Figure 51.
  • Figure 60 is the structural layout of the electrode layer in Figure 51.
  • Figure 61 is a structural layout of the shielding layer and the first active layer in Figure 51.
  • Figure 62 is a structural layout of the shielding layer, the first active layer and the first gate layer in Figure 51.
  • Figure 63 is the shielding layer in Figure 51. , the structural layout of the first active layer, the first gate layer, and the second gate layer.
  • Figure 64 shows the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second gate layer in Figure 51 The structural layout of the two active layers.
  • Figure 65 is the structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in Figure 51.
  • Figure 66 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer and the first source and drain layer in Figure 51, Figure 67 It is the structure of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source and drain layer, and the second source and drain layer in Figure 51 territory.
  • the above-mentioned first signal line and second signal line can be added to the display panel by compressing repeating units.
  • a plurality of the repeating units distributed in the first direction A corresponding second signal line V2 is provided between them.
  • the shielding layer may include multiple shielding parts 61, and adjacent shielding parts 61 may be connected to each other.
  • the minimum distance in the first direction Among the two sub-repeating units adjacent in the unit and in the first direction X, the minimum distance in the first direction X between the orthographic projection of the adjacent shielding portion 61 on the base substrate is L6. Among them, L6 is smaller than L5.
  • the minimum distance in the second direction Y between the orthographic projections of adjacent shielding portions 61 on the base substrate is L16; in the case of two repeating units located in the same repeating unit and adjacent in the second direction Y In the sub-repeating unit, the minimum distance in the second direction Y between the orthographic projections of adjacent shielding portions 61 on the base substrate is L15. Among them, L15 is smaller than L16. It should be understood that in other exemplary embodiments, the display panel may not include the blocking layer.
  • the first active layer may include a third active portion 73, a fourth active portion 74, a fifth active portion 75, and a sixth active portion 76 , the seventh active part 77.
  • the third active part 73 may be used to form a channel region of the driving transistor T3; the fourth active part 74 may be used to form a channel region of the fourth transistor T4; and the fifth active part 75 may be used to form a channel region of the fourth transistor T4.
  • the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; and the seventh active portion 77 can be used to form the channel region of the seventh transistor T7.
  • the first active layer also includes a ninth active part 79 , a tenth active part 710 , an eleventh active part 711 , a twelfth active part 712 , and a thirteenth active part 713 .
  • the ninth active part 79 is connected to the side of the fifth active part 75 away from the third active part 73
  • the ninth active part 79 is connected to adjacent sub-repeating units in the first direction X. between two fifth active parts 75 .
  • the tenth active part 710 is connected between the sixth active part 76 and the seventh active part 77
  • the eleventh active part 711 is connected between the sixth active part 76 and the third active part 73
  • the The twelve active parts 712 are connected to an end of the fourth active part 74 away from the third active part 73
  • the thirteenth active part 713 is connected to an end of the seventh active part 77 away from the sixth active part 76 .
  • the orthographic projection of the shielding portion 61 on the base substrate can cover the orthographic projection of the third active portion 73 on the base substrate, and the shielding portion 61 can reduce the impact of light on the driving characteristics of the driving transistor T3. As shown in FIG.
  • the dimension on X is L7; in the two sub-repeating units located in the same repeating unit and adjacent in the first direction
  • the size of the orthographic projection of the active portion 79 on the base substrate in the first direction X is L8, where L7 is larger than L8.
  • the minimum distance in the second direction Y between the orthographic projections of the adjacent twelfth active portion 712 and the ninth active portion 79 on the base substrate is L18; in Among the two sub-repeating units located in the same repeating unit and adjacent in the second direction Y, the adjacent twelfth active portion 712 and the ninth active portion 79 are on the right side of the base substrate.
  • the minimum distance projected in the second direction Y is L17, where L18 is greater than L17.
  • the first active layer may be made of polysilicon Accordingly, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type low-temperature polysilicon thin film transistors.
  • the first gate layer may include: a first conductive portion 11, a first gate line G1, an enable signal line EM, and a second reset signal line Re2.
  • the first gate line G1 can be used to provide the first gate drive signal terminal in Figure 32;
  • the enable signal line EM can be used to provide the enable signal terminal in Figure 32;
  • the second reset signal line Re2 can be used to provide the enable signal terminal in Figure 32 The second reset signal terminal in .
  • the orthographic projection of the first gate line G1 on the base substrate, the orthographic projection of the enable signal line EM on the base substrate, and the orthographic projection of the second reset signal line Re2 on the base substrate can all extend along the first direction X. .
  • the orthographic projection of the first gate line G1 on the base substrate covers the orthographic projection of the fourth active part 74 on the base substrate, and part of the structure of the first gate line G1 is used to form the gate electrode of the fourth transistor.
  • the orthographic projection of the enable signal line EM on the base substrate covers the orthographic projection of the fifth active part 75 on the base substrate and the orthographic projection of the sixth active part 76 on the base substrate.
  • the enable signal line EM Part of the structure may be used to form gates of the fifth transistor T5 and the sixth transistor T6 respectively.
  • the orthographic projection of the second reset signal line Re2 on the base substrate can cover the orthographic projection of the seventh active part 77 on the base substrate, and part of the structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7 pole.
  • the orthographic projection of the first conductive portion 11 on the base substrate covers the orthographic projection of the third active portion 73 on the base substrate.
  • the first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first capacitor C. electrode.
  • the first gate line G1 in the pixel driving circuit of this row can be multiplexed as the second reset signal line Re2 in the pixel driving circuit of the next row.
  • the display panel can be driven row by row from top to bottom.
  • the shielding layer can also be connected to a stable power supply terminal.
  • the shielding layer can be connected to the first power supply terminal, the first initial signal terminal, the second initial signal terminal, etc. in Figure 32.
  • the shielding portion 61 can shield the impact of other signals on the driving transistor T3. Noise impact.
  • a plurality of repeating units distributed in the first direction The pixel driving circuit row Ph1 includes a plurality of pixel driving circuits distributed along the first direction X, and the second pixel driving circuit row Ph2 includes a plurality of pixel driving circuits distributed along the first direction. As shown in FIG.
  • the orthographic projection of the enable signal line EM on the base substrate and the second reset signal line Re2 are on the base substrate.
  • the minimum distance of the orthographic projection on the second direction Y is L3;
  • the orthographic projection of the enable signal line EM on the base substrate and the orthographic projection of the second reset signal line Re2 on the base substrate are at the same position.
  • the distance in the second direction is L4, where L3 is greater than L4.
  • the minimum distance in the first direction Among the two adjacent sub-repeating units in the first direction X is L20.
  • L20 is smaller than L19.
  • the display panel can use the first gate layer as a mask to conduct conduction processing on the first active layer, that is, the area of the first active layer covered by the first gate layer can form the channel region of the transistor. A region of the first active layer not covered by the first gate layer forms a conductor structure.
  • the second gate layer may include: a first initial signal line Vinit1, a third reset signal line 2Re1, a third gate line 2G2, and a plurality of second conductive parts. twenty two.
  • the first initial signal line Vinit1 is used to provide the first initial signal terminal in Figure 32
  • the third reset signal line 2Re1 can be used to provide the first reset signal terminal in Figure 32
  • the third gate line 2G2 can be used to provide The second gate drive signal terminal in Figure 32.
  • the orthographic projection of the first initial signal line Vinit1 on the base substrate, the orthographic projection of the third reset signal line 2Re1 on the base substrate, and the orthographic projection of the third gate line 2G2 on the base substrate can all be along the first direction X. extend.
  • the second gate layer may further include a plurality of connecting portions 23 . In the sub-repeating units adjacent in the first direction X, the connecting portions 23 are connected to adjacent sub-repeating units in the first direction X. between the two second conductive parts 22 . As shown in FIG.
  • connection portion 23 connected between the adjacent second conductive portions 22 is on the base substrate
  • the size of the orthographic projection on the first direction X is L9, and L10 is larger than L9.
  • the size of the orthographic projection of the adjacent second conductive portion and the first initial signal line Vinit1 on the base substrate in the first direction X is L22;
  • the orthographic projection of the adjacent second conductive portion and the first initial signal line Vinit1 on the substrate is in the first direction X
  • the size is L21, L22 is larger than L21.
  • adjacent second conductive portions 22 in the same repeating unit may also be connected.
  • the second active layer may include an active part 8, and the active part 8 may include: a first active part 81, a second active part 82, a third The fourteenth active part 814, the fifteenth active part 815, and the sixteenth active part 816.
  • the first active part 81 is used to form a channel region of the first transistor T1
  • the second active part 82 is used to form a channel region of the second transistor T2.
  • the fifteenth active part 815 is connected between the first active part 81 and the second active part 82 .
  • the fourteenth active part 814 is connected to an end of the first active part 81 away from the second active part 82
  • the sixteenth active part 816 is connected to an end of the second active part 82 away from the first active part 81 .
  • the minimum distance in the first direction X between the orthographic projections of active portions 8 adjacent in the first direction X on the base substrate is L11;
  • the orthographic projection of the active portion 8 adjacent in the first direction X on the base substrate The minimum distance in the first direction X is L12, and L11 is greater than L12.
  • the minimum distance in the second direction Y between the orthographic projections of the active portions 8 adjacent in the second direction Y on the base substrate is L24;
  • the orthographic projection of the active portion 8 adjacent in the second direction Y on the base substrate is in the second direction Y.
  • the minimum distance is L23, and L24 is larger than L23.
  • the second active layer may be formed of indium gallium zinc oxide, and accordingly, the first transistor T1 and the second transistor T2 may be N-type metal oxide thin film transistors.
  • the orthographic projection of the third gate line 2G2 on the base substrate can cover the orthographic projection of the second active part 82 on the base substrate, and part of the structure of the third gate line 2G2 can be used to form the bottom gate of the second transistor T2.
  • the orthographic projection of the third reset signal line 2Re1 on the base substrate can cover the orthographic projection of the first active part 81 on the base substrate, and part of the structure of the third reset signal line 2Re1 can be used to form the bottom of the first transistor T1 gate.
  • the third gate layer may include a first reset signal line 3Re1 and a second gate line 3G2. Both the orthographic projection of the first reset signal line 3Re1 on the base substrate and the orthographic projection of the second gate line 3G2 on the base substrate can extend along the first direction X.
  • the first reset signal line 3Re1 can be used to provide the first reset signal terminal in FIG. 32
  • the orthographic projection of the first reset signal line 3Re1 on the base substrate can cover the orthographic projection of the first active part 81 on the base substrate.
  • part of the structure of the first reset signal line 3Re1 can be used to form the top gate of the first transistor T1, and at the same time, the first reset signal line 3Re1 can be connected to the third reset signal line 2Re1 through a via hole located in the frame area of the display panel.
  • the second gate line 3G2 may be used to provide the second gate in FIG. 32
  • the orthographic projection of the second gate line 3G2 on the base substrate can cover the orthographic projection of the second active part 82 on the base substrate, and part of the structure of the second gate line 3G2 can be used to form the second transistor T2
  • the second gate line 3G2 can be connected to the third gate line 2G2 through a via hole located in the frame area of the display panel.
  • the minimum distance in the second direction Y between the orthographic projections of the adjacent second gate line 3G2 and the first reset signal line 3Re1 on the substrate is For L14, in the sub-repeating unit located in the same repeating unit and adjacent in the second direction Y, the orthographic projection of the adjacent second gate line 3G2 and the first reset signal line 3Re1 on the substrate is in the second direction Y
  • the minimum distance is L13, and L14 is greater than L13.
  • the display panel can use the third gate layer as a mask to conduct conduction processing on the second active layer, that is, the area of the second active layer covered by the third gate layer can form the channel region of the transistor. A region of the second active layer not covered by the third gate layer forms a conductor structure.
  • the first source and drain layer may include: the above-mentioned first signal line H1, the second initial signal line Vinit2, the first bridge portion 41, and the second bridge portion 42 , the third bridge portion 43, the fourth bridge portion 44, the fifth bridge portion 45, and the sixth bridge portion 46.
  • the first bridge part 41 is connected to the connection part 23 and the ninth active part 79 through via holes respectively, so as to connect the first electrode of the fifth transistor and the second electrode of the capacitor C. Adjacent sub-repeating units in the first direction X share the same first bridge portion 41 .
  • the second bridge portion 42 may be connected to the tenth active portion 710 through a via hole to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.
  • the third bridge portion 43 can be connected to the eleventh active portion 711 and the sixteenth active portion 816 respectively through via holes to connect the second electrode of the second transistor T2, the first electrode of the sixth transistor T6, and the driving transistor T3. the second pole.
  • the fourth bridge portion 44 can be connected to the fifteenth active portion 815 and the first conductive portion 11 through via holes respectively, so as to connect the first electrode of the second transistor T2 and the gate electrode of the driving transistor.
  • An opening 221 is formed on the second conductive part 22, and the orthographic projection of the via hole connected between the first conductive part 11 and the fourth bridge part 44 on the substrate is located within the orthographic projection of the opening 221 on the substrate. So that the via hole and the second conductive part 22 are insulated from each other.
  • the fifth bridge part 45 may be connected to the twelfth active part 712 through a via hole to connect the first electrode of the fourth transistor.
  • the sixth bridge part 46 may be connected to the fourteenth active part 814 and the first initial signal line Vinit1 through via holes respectively, so as to connect the first pole of the first transistor and the first initial signal terminal. In the same repeating unit, two adjacent pixel driving circuits may share the same sixth bridge portion 46 .
  • the second initial signal line Vinit2 can be used to provide the second initial signal terminal in FIG. 32, and the orthographic projection of the second initial signal line Vinit2 on the substrate can be Extending along the first direction A plurality of the repeating units distributed in the first direction
  • the front projection on the base substrate is located on the front projection of the enable signal line EM on the base substrate in the first pixel driving circuit row Ph1 and the second reset in the first pixel driving circuit row Ph1
  • the signal line Re2 is between orthographic projections on the base substrate.
  • the orthographic projection of the first signal line H1 on the base substrate does not overlap with the orthographic projections of the first gate layer and the third gate layer on the base substrate.
  • the orthographic projection of the first signal line H1 on the base substrate does not overlap.
  • the maximum dimension of the orthographic projection of the first bridge portion 41 shared by adjacent sub-repeating units in the first direction X on the base substrate in the first direction X is L16, and L15 is larger than L16.
  • the maximum distance in the second direction Y between the orthographic projection of the first bridge portion 41 on the base substrate and the orthographic projection of the second initial signal line Vinit2 on the base substrate in the first pixel driving circuit row Ph1 is L26
  • the maximum distance in the second direction Y between the orthographic projection of the first bridge portion 41 on the base substrate and the orthographic projection of the second initial signal line Vinit2 on the base substrate in the driving circuit row Ph2 is L25
  • L26 is greater than L25.
  • the second source and drain layer may include: the above-mentioned second signal line V2 , a plurality of power lines VDD, a plurality of data lines Da, and the seventh bridge portion 57 .
  • one second signal line V2 is provided correspondingly between adjacent repeating units in the first direction X.
  • the orthographic projection of the power line VDD on the base substrate and the orthographic projection of the data line Da on the base substrate can both extend along the second direction Y.
  • the power line VDD can be used to provide the first power terminal in Figure 32
  • the data line Da can be used to provide the data signal terminal in Figure 32.
  • Each column of pixel driving circuits may be provided with a corresponding power line VDD, and the power line VDD may be connected to the first bridge portion 41 through a via hole to connect the first pole of the fifth transistor and the first power terminal.
  • the data line Da may be connected to the fifth bridge portion 45 through a via hole to connect the first electrode of the fourth transistor and the data signal terminal.
  • the seventh bridge portion 57 may be connected to the second bridge portion 42 through a via hole to connect the second pole of the seventh transistor.
  • adjacent power lines VDD are connected to each other, so that the power line VDD and the second conductive portion 22 can form a grid structure.
  • the power lines of the grid structure can reduce the voltage drop of the power signal thereon.
  • the power line VDD may include a first power line segment VDD1, a second power line segment VDD2, and a third power line segment VDD3.
  • the second power line segment VDD2 is connected to the first power line segment.
  • the size of the orthographic projection of the second power line segment VDD2 on the substrate in the first direction X may be larger than the orthogonal projection of the first power line segment VDD1 on the substrate.
  • the size in the first direction X, and the orthogonal projection size of the second power line segment VDD2 on the substrate substrate in the first direction The size of the orthographic projection in the first direction X.
  • the orthographic projection of the second power line segment VDD2 on the base substrate can also cover the orthographic projection of the first active part 81 on the base substrate and the orthographic projection of the second active part 82 on the base substrate.
  • the power line segment VDD2 can reduce the impact of light on the characteristics of the first transistor T1 and the second transistor T2.
  • the orthographic projection of the power line VDD on the base substrate can also at least partially overlap with the orthographic projection of the fourth bridge portion 44 on the base substrate, and the power line VDD can be used to shield the fourth bridge portion 44 from other signals. Noise interference, thereby improving the stability of the gate voltage of the driving transistor T3. As shown in FIG.
  • the orthographic projection of two adjacent data lines Da on the substrate is in the first direction X.
  • the minimum distance is L1; in the two sub-repeating units located in the same repeating unit and adjacent in the first direction X, the distance between two adjacent data lines Da on the base substrate
  • the distance of the orthographic projection in the first direction X is L2, where L1 is greater than L2.
  • the pixel electrode layer may include a plurality of electrode parts: a first electrode part R, a second electrode part B, and a third electrode part G.
  • the first electrode portion R, the third electrode portion G, the second electrode portion B, and the third electrode portion G are sequentially distributed alternately in the first direction X.
  • the plurality of electrode parts form a plurality of electrode rows.
  • the plurality of electrode rows include sequentially adjacent first electrode rows ROW1, second electrode rows ROW2, third electrode rows ROW3, and fourth electrode rows ROW4.
  • the first electrode row ROW1 is included in The first electrode portion R and the second electrode portion B are distributed alternately in the second direction Y;
  • the second electrode row ROW2 includes a plurality of third electrode portions G distributed in the second direction Y;
  • the third electrode row ROW3 includes The second electrode parts B and the first electrode parts R are distributed alternately in the second direction Y;
  • the fourth electrode row ROW4 includes a plurality of third electrode parts G distributed in the second direction Y.
  • the orthographic projection of the two third electrode portions G located in adjacent electrode rows of the same electrode column on the base substrate is on the second
  • the minimum distance S5 in the direction Y is greater than the orthogonal projection size S6 of the first electrode portion R on the base substrate in the second direction Y, or is greater than the second electrode portion B on the base substrate.
  • the dimension S7 of the orthographic projection in the second direction Y is greater than the orthographic projection of the first electrode portion R on the base substrate coincides with the orthographic projection of its corresponding pixel opening on the base substrate on the pixel definition layer
  • the orthographic projection of the third electrode portion G on the base substrate coincides with the orthographic projection of the pixel on the base substrate.
  • the orthographic projection of the corresponding pixel opening on the definition layer on the base substrate coincides with the orthographic projection of the second electrode portion B on the base substrate and the orthographic projection of the corresponding opening on the pixel definition layer on the base substrate.
  • two second power line segments VDD2 in adjacent power lines VDD are connected.
  • the orthographic projections of the two adjacent data lines Da on the base substrate are located where the same third electrode portion G is located.
  • the orthographic projections on the base substrate intersect and are located on both sides of the orthographic projection of the second signal line V2 on the base substrate.
  • the orthographic projection of the second signal line V2 on the base substrate intersects with the third electrode portion. This arrangement can improve the flatness of the electrode portion, thereby improving the uniformity of display on the display panel.
  • the black square drawn on the side of the first source and drain layer facing away from the base substrate indicates the side of the first source and drain layer connection facing the base substrate.
  • the via holes of other levels; the black squares drawn on the side of the second source and drain layer facing away from the substrate indicate the via holes of the second source and drain layer connecting to other levels on the side facing the substrate; the black squares drawn on the side of the electrode layer facing away from the substrate.
  • the black squares on the side of the substrate represent vias where the electrode layer connects to other levels on the side of the substrate facing the substrate.
  • the black square only represents the location of the via hole. Different via holes represented by black squares at different positions can penetrate different insulation layers.
  • one second signal line V2 is provided correspondingly between two adjacent repeating unit columns in the first direction, and one first signal line H1 is provided correspondingly in the same repeating unit row.
  • the repeating unit includes two rows and two columns of sub-repeating units. It should be understood that in other exemplary embodiments, the repeating unit may also include sub-repeating units with other numbers of rows and columns.
  • the display panel may further include a first insulating layer 91, a second insulating layer 92, a third insulating layer 93, a fourth insulating layer 94, a fifth insulating layer 95, a first dielectric layer 96, a passivation layer 97, a first Flat layer 98, second flat layer 99, wherein the base substrate 90, shielding layer, first insulating layer 91, first Active layer, second insulating layer 92, first gate layer, third insulating layer 93, second gate layer, fourth insulating layer 94, second active layer, fifth insulating layer 95, third gate layer, the first dielectric layer 96, the first source-drain layer, the passivation layer 97, the first planarization layer 98, the second source-drain layer, and the second planarization layer 99 are stacked in sequence.
  • the first insulating layer 91 , the second insulating layer 92 , the third insulating layer 93 , the fourth insulating layer 94 and the fifth insulating layer 95 can be a single-layer structure or a multi-layer structure, and the first insulating layer 91 and the second insulating layer 92.
  • the material of the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the first dielectric layer 96 can be silicon nitride.
  • the material of the first flat layer 98 and the second flat layer 99 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG) and other materials.
  • Passivation layer 97 may be a silicon oxide layer.
  • the base substrate 90 may include a glass substrate, a barrier layer, and a polyimide layer that are stacked in sequence.
  • the barrier layer may be an inorganic material.
  • the material of the first gate layer, the second gate layer, and the third gate layer may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or a laminate or other conductive layer.
  • the material of the first source and drain layer and the second source and drain layer may include a metal material, for example, it may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or laminate, etc., or it may be titanium /Aluminum/Titanium laminate and other conductive layers.
  • the sheet resistance of any one of the first source-drain layer and the second source-drain layer may be smaller than the sheet resistance of any one of the first gate layer, the second gate layer, and the third gate layer. Therefore, in this exemplary embodiment, the first data fan-out line and the second data fan-out line have smaller resistance.
  • the scale of the drawings in this disclosure can be used as a reference in the actual process, but is not limited thereto, for example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line, It can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the figures described in this disclosure are only structural schematic diagrams.
  • the qualifiers such as first and second are only used to define different structure names and have no specific order meaning.
  • the same structural layer can be formed through the same patterning process.
  • the orthographic projection of a certain structure on the base substrate extends along a certain direction. It can be understood that the orthographic projection of the structure on the base substrate extends straightly or in a bend along the direction.
  • the display panel may be a flexible display panel or a non-flexible display panel.
  • This exemplary embodiment also provides a display device, which includes the above-mentioned display panel.
  • the display device can be a display device such as a mobile phone, a tablet computer, or a television.

Abstract

本公开涉及显示技术领域，提出一种显示面板和显示装置。显示面板包括显示区、位于显示区的扇出区，显示面板还包括：衬底基板、多条数据线、多条第一数据扇出线、多条第二数据扇出线。数据线在衬底基板上的正投影沿第一方向间隔分布且沿第二方向延伸，第一方向和第二方向相交；第一数据扇出线在衬底基板上的正投影沿第二方向间隔分布且沿第一方向延伸，第一数据扇出线与数据线对应设置，第一数据扇出线连接与其对应的数据线；第二数据扇出线在衬底基板上的正投影沿第一方向间隔分布且沿第二方向延伸，第二数据扇出线与第一数据扇出线对应设置，第二数据扇出线连接与其对应的第一数据扇出线。该显示面板可以实现较窄的边框设计。 (图2)

Description

显示面板及显示装置
相关申请的交叉引用
本申请要求于2022年8月4日递交的、名称为《显示面板及显示装置》的中国专利申请第202210935801.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
相关技术中，显示面板的边框较宽。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
根据本公开的一个方面，提供一种显示面板，所述显示面板包括显示区、位于所述显示区的扇出区，所述显示面板还包括：衬底基板、多条数据线、多条第一数据扇出线、多条第二数据扇出线。多条数据线位于所述显示区，所述数据线在所述衬底基板上的正投影沿第一方向间隔分布且沿第二方向延伸，所述第一方向和所述第二方向相交；多条第一数据扇出线位于所述扇出区，所述第一数据扇出线在所述衬底基板上的正投影沿所述第二方向间隔分布且沿所述第一方向延伸，所述第一数据扇出线与所述数据线对应设置，所述第一数据扇出线连接与其对应的所述数据线；多条第二数据扇出线位于所述扇出区，所述第二数据扇出线在所述衬底基板上的正投影沿所述第一方向间隔分布且沿所述第二方向延伸，所述第二数据扇出线与所述第一数据扇出线对应设置，所述第二数据扇出线连接与其对应的所述第一数据扇出线。
本公开一种示例性实施例中，述显示面板还包括：多条第一信号线、多条第二信号线，多条第一信号线位于所述显示区，所述第一信号线在所述衬底基板上的正投影沿所述第一方向延伸且沿所述第二方向间隔分布，多条所述第一信号线中包括第一子信号线，所述第一子信号线的至少部分结构用于形成所述第一数据扇出线；多条第二信号线位于所述显示区，且与所述第一信号线位于不同导电层，所述第二信号线在所述衬底基板上的正投影沿所述第二方向延伸且沿所述第一方向间隔分布，多条所述第二信号线中包括第二子信号线，所述第二子信号线的至少部分结构用于形成所述第二数据扇出线。
本公开一种示例性实施例中，相邻两所述第一信号线在所述衬底基板上的正投影在所述第二方向上的最小距离为S1，相邻两所述第一信号线在所述衬底基板上的正投影在所述第二方向上的最大距离为S2，其中，(S2-S1)/S1大于等于0且小于等于0.2；和/或，相邻两所述第二信号线在所述衬底基板上的正投影在所述第一方向上的最小距离为S3，相邻两所述第二信号线在所述衬底基板上的正投影在所述第一方向上的最大距离为S4，其中，(S4-S3)/S3大于等于0且小于等于0.2。
本公开一种示例性实施例中，所述第一子信号线还包括与所述第一数据扇出线间隔设置的第一模拟线，所述第二子信号线还包括与所述第二数据扇出线间隔设置的第二模拟线；所述扇出区包括第一扇出区和第二扇出区，所述第一数据扇出线位于所述第一扇出区，所述第二数据扇出线位于所述第二扇出区；多条所述第一信号线中还包括第三模拟线，所述第三模拟线位于所述第一扇出区以外的显示区；多条所述第二信号线中还包括第四模拟线，所述第四模拟线位于所述第二扇出区以外的显示区。
本公开一种示例性实施例中，所述显示面板还包括像素驱动电路和发光单元，所述像素驱动电路连接所述发光单元的第一电极；所述显示面板还包括：公共电极层，所述公共电极层用于形成所述发光单元的第二电极；其中，所述第一模拟线、所述第二模拟线、所述第三模拟线、所述第四模拟线连接所述公共电极层。
本公开一种示例性实施例中，所述第一模拟线通过过孔连接与其在所述衬底基板上的正投影相交的第四模拟线；所述第三模拟线通过过孔连接 与其在所述衬底基板上的正投影相交的所述第二模拟线、第四模拟线。
本公开一种示例性实施例中，所述显示面板还包括位于所述显示区周围的边框区，所述边框区包括相对设置的第一边框区和第二边框区，所述扇出区位于靠近所述第二边框区的一侧；所述显示面板还包括：电极环、电源电路，所述电极环位于所述边框区，且连接所述公共电极层，所述电极环位于所述第一边框区的至少部分结构连接所述第二模拟线和所述第四模拟线；电源电路绑定于所述第二边框区，所述电源电路连接所述电极环位于所述第二边框区的至少部分结构，所述电源电路用于向所述电极环提供电源信号。
本公开一种示例性实施例中，所述第一扇出区包括第一子扇出区和第二子扇出区，所述第一子扇出区和第二子扇出区位于所述第二扇出区在所述第一方向上两侧；多条所述第二信号线中还包括至少一条第五模拟线，所述第五模拟线的部分结构位于所述第二扇出区，且所述第五模拟线分别通过过孔连接与其在所述衬底基板上正投影相交的所述第一模拟线和第三模拟线。
本公开一种示例性实施例中，多条所述第一信号线位于同一导电层，多条所述第二信号线位于同一导电层；所述第二信号线所在导电层位于所述第一信号线所在导电层背离所述衬底基板的一侧。
本公开一种示例性实施例中，所述显示面板还包括：第一源漏层、第二源漏层，第一源漏层位于所述衬底基板的一侧，所述第一源漏层包括所述第一信号线；第二源漏层位于所述第一源漏层背离所述衬底基板的一侧，所述第二源漏层包括所述第二信号线和所述数据线；所述第二信号线在所述衬底基板上的正投影位于相邻两所述数据线在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述第一信号线包括多个第一过孔接触部和第一延伸部，多个所述第一过孔接触部在所述衬底基板上的正投影沿所述第一方向间隔分布，所述第一延伸部连接于所述第一过孔接触部，所述第一过孔接触部在所述衬底基板上的正投影在所述第二方向上的尺寸大于所述第一延伸部在所述衬底基板上的正投影在所述第二方向上的尺寸；所述第二信号线包括多个第二过孔接触部和第二延伸部，多个所述第 二过孔接触部在所述衬底基板上的正投影沿所述第二方向间隔分布，所述第二延伸部连接于所述第二过孔接触部，所述第二过孔接触部在所述衬底基板上的正投影在所述第一方向上的尺寸大于所述第二延伸部在所述衬底基板上的正投影在所述第一方向上的尺寸；其中，所述第一过孔接触部和所述第二过孔接触部对应设置，所述第一过孔接触部在所述衬底基板上的正投影和与其对应的所述第二过孔接触部在所述衬底基板上的正投影至少部分交叠，至少部分所述第一过孔接触部通过过孔连接与其对应的所述第二过孔接触部。
本公开一种示例性实施例中，相邻所述第一过孔接触部在所述衬底基板上的正投影在所述第一方向上的最小距离为S5，相邻所述第一过孔接触部在所述衬底基板上的正投影在所述第一方向上的最大距离为S6，其中，(S6-S5)/S5大于等于0且小于等于0.2；和/或，相邻所述第二过孔接触部在所述衬底基板上的正投影在所述第二方向上的最小距离为S7，相邻所述第二过孔接触部在所述衬底基板上的正投影在所述第二方向上的最大距离为S8，其中，(S8-S7)/S7大于等于0且小于等于0.2。
本公开一种示例性实施例中，多个所述第一过孔接触部中包括第一实孔接触部，多个所述第二过孔接触部中包括第二实孔接触部和第二虚孔接触部；所述第一实孔接触部和与其对应的所述第二实孔接触部通过过孔连接，所述第二虚孔接触部和与其在所述衬底基板上的正投影相交的所述第一信号线绝缘设置。
本公开一种示例性实施例中，多个所述第一过孔接触部中还包括第一虚孔接触部，所述第一虚孔接触部和与其对应的所述第二虚孔接触部绝缘设置。
本公开一种示例性实施例中，所述显示面板包括：第一平坦层，第一平坦层位于所述第一源漏层和所述第二源漏层之间，所述第一平坦层的厚度小于等于1.6um。
本公开一种示例性实施例中，所述显示面板还包括：钝化层、第一平坦层，钝化层位于所述第一信号线所在导电层和所述第二信号线所在导电层之间；第一平坦层位于所述钝化层和所述所述第二信号线所在导电层之间；其中，所述第一平坦层上形成有第一开孔，所述第一开孔在所述衬底 基板上的正投影与所述第二虚孔接触部在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述显示面板还包括：钝化层、第一平坦层，钝化层位于所述第一信号线所在导电层和所述第二信号线所在导电层之间；第一平坦层位于所述钝化层和所述所述第二信号线所在导电层之间；其中，所述钝化层上形成有第二开孔，所述第二开孔在所述衬底基板上的正投影与所述第二虚孔接触部在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述第一数据扇出线和所述第一模拟线之间断口在所述衬底基板上的正投影在所述第一方向上的尺寸为1.5um-3.5um；和/或，所述第二数据扇出线和所述第二模拟线之间断口在所述衬底基板上的正投影在所述第二方向上的尺寸为1.5um-3.5um。
本公开一种示例性实施例中，在所述衬底基板上的正投影位于所述第二信号线相邻两侧的所述数据线包括第三延伸部、第四延伸部、第五延伸部，所述第四延伸部连接于所述第三延伸部和所述第五延伸部之间；所述第二过孔接触部和所述第四延伸部的至少部分结构在所述第一方向上相对设置，且所述第四延伸部在所述衬底基板上的正投影和所述第二延伸部在所述衬底基板上的正投影在所述第一方向上的尺寸大于所述第三延伸部在所述衬底基板上的正投影和所述第二延伸部在所述衬底基板上的正投影在所述第一方向上的尺寸，所述第四延伸部在所述衬底基板上的正投影和所述第二延伸部在所述衬底基板上的正投影在所述第一方向上的尺寸大于所述第五延伸部在所述衬底基板上的正投影和所述第二延伸部在所述衬底基板上的正投影在所述第一方向上的尺寸。
本公开一种示例性实施例中，所述显示面板还包括像素驱动电路和发光单元，所述像素驱动电路连接所述发光单元的第一电极，所述显示面板还包括：电极层，电极层位于所述衬底基板的一侧，所述电极层包括多个电极部，所述电极部用于形成所述发光单元的第一电极；所述第一数据扇出线和所述第一模拟线之间的断口在所述衬底基板上的正投影与所述电极部在所述衬底基板上的正投影不交叠；和/或，所述第二数据扇出线和所述第二模拟线之间的断口在所述衬底基板上的正投影与所述电极部在 所述衬底基板上的正投影不交叠。
本公开一种示例性实施例中，所述显示面板还包括像素驱动电路和发光单元，所述像素驱动电路连接所述发光单元的第一电极，所述显示面板还包括：电极层，电极层位于所述衬底基板的一侧，所述电极层包括多个电极部，所述电极部用于形成所述发光单元的第一电极；所述第一过孔接触部在所述衬底基板上的正投影和所述电极部在所述衬底基板上的正投影不交叠；所述第二过孔接触部在所述衬底基板上的正投影和所述电极部在所述衬底基板上的正投影不交叠。
本公开一种示例性实施例中，所述显示面板还包括多个像素驱动电路和多个发光单元，多个所述像素驱动电路沿所述第一方向和所述第二方向阵列分布的，所述像素驱动电路连接所述发光单元的第一电极；所述像素驱动电路包括驱动晶体管、第六晶体管、第七晶体管，所述第六晶体管的第一极连接所述驱动晶体管的第二极，所述第六晶体管的第二极连接所述发光单元的第一电极，所述第七晶体管的第一极连接第二初始信号线，所述第七晶体管的第二极连接所述发光单元的第一电极。所述显示面板还包括：第一有源层、第一栅极层，第一有源层位于所述衬底基板的一侧，所述第一有源层包括第六有源部和第七有源部，所述第六有源部用于形成所述第六晶体管的沟道区，所述第七有源部用于形成所述第七晶体管的沟道区；第一栅极层位于所述第一有源层背离所述衬底基板的一侧，所述第一栅极层包括使能信号线和第二复位信号线，所述使能信号线在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第六有源部在所述衬底基板上的正投影，所述第二复位信号线在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第七有源部在所述衬底基板上的正投影；其中，所述第一方向为行方向，所述第一信号线在所述衬底基板上的正投影位于同一行像素驱动电路中所述使能信号线在所述衬底基板上的正投影和所述第二复位信号线在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述显示面板还包括多个像素驱动电路和多个发光单元，多个所述像素驱动电路沿所述第一方向和所述第二方向阵列分布的，所述像素驱动电路连接所述发光单元的第一电极；所述像素驱动电路包括驱动晶体管、第六晶体管、第一晶体管，所述第六晶体管的 第一极连接所述驱动晶体管的第二极，所述第六晶体管的第二极连接所述发光单元的第一电极，所述第一晶体管的第一极连接第一初始信号线，所述第一晶体管的第二极连接所述驱动晶体管的栅极。所述显示面板还包括：第一栅极层、第二栅极层，第一栅极层位于所述衬底基板的一侧，所述第一栅极层包括使能信号线，所述使能信号线的部分结构用于形成所述第六晶体管的栅极；第二栅极层位于所述第一栅极层背离所述衬底基板的一侧，所述第二栅极层包括所述第一初始信号线；所述第一信号线中的第一延伸部在所述衬底基板上的正投影位于本行像素驱动电路中所述第一初始信号线在所述衬底基板上的正投影和相邻下一行像素驱动电路中所述使能信号线在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述显示面板包括多个在所述第一方向和所述第二方向上阵列分布的重复单元，所述重复单元包括n行m列子重复单元，n、m为大于等于1的正整数；所述子重复单元包括在所述第一方向上相邻分布的两个像素驱动电路，同一所述子重复单元中两像素驱动电路镜像对称设置；在所述第二方向上分布的多个所述重复单元形成重复单元列，在所述第一方向上相邻的两所述重复单元列之间对应设置一条所述第二信号线；在所述第一方向上分布的多个所述重复单元形成重复单元行，每个所述重复单元行对应设置一条所述第一信号线。
本公开一种示例性实施例中，所述显示面板还包括发光单元，所述像素驱动电路连接所述发光单元的第一电极，所述显示面板还包括：电极层，电极层包括多个电极部，所述电极部用于形成所述发光单元的第一电极；其中，在所述第一方向上相邻两所述子重复单元中，相邻两所述数据线在所述衬底基板上的正投影与同一所述电极部在所述衬底基板上的正投影相交，且位于所述第二信号线在所述衬底基板上的正投影的两侧。
本公开一种示例性实施例中，m为大于等于2的正整数；在所述第一方向上相邻的所述重复单元列中，相邻两所述数据线在所述衬底基板上的正投影在所述第一方向上的最小距离为L1；在位于同一所述重复单元中且在所述第一方向上相邻的两所述子重复单元中，相邻两所述数据线在所述衬底基板上的正投影在所述第一方向上的最小距离为L2；其中，L1大于L2。
本公开一种示例性实施例中，n为大于等于2的正整数；所述显示面板还包括发光单元，所述像素驱动电路包括驱动晶体管、第六晶体管、第七晶体管，所述第六晶体管的第一极连接所述驱动晶体管的第二极，所述第六晶体管的第二极连接所述发光单元的第一电极，所述第六晶体管的栅极连接使能信号线，所述第七晶体管的第一极连接第二初始信号线，所述第七晶体管的第二极连接所述发光单元的第一电极，所述第七晶体管的栅极连接第二复位信号线；同一所述重复单元行包括第一像素驱动电路行和第二像素驱动电路行，所述第一像素驱动电路行包括沿所述第一方向分布的多个像素驱动电路，所述第二像素驱动电路行包括沿所述第一方向分布的多个像素驱动电路；所述第一信号线在所述衬底基板上的正投影位于所述第一像素驱动电路行中所述使能信号线在所述衬底基板上的正投影和所述第一像素驱动电路行中所述第二复位信号线在所述衬底基板上的正投影之间；在所述第一像素驱动电路行中，所述使能信号线在所述衬底基板上的正投影和所述第二复位信号线在所述衬底基板上的正投影在所述第二方向上的最小距离为L3；在所述第二像素驱动电路行中，所述使能信号线在所述衬底基板上的正投影和所述第二复位信号线在所述衬底基板上的正投影在所述第二方向上的最小距离为L4；其中，L3大于L4。
本公开一种示例性实施例中，所述显示面板包括像素驱动电路和发光单元，所述像素驱动电路包括驱动晶体管、第一晶体管、第二晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、电容；所述第一晶体管的第一极连接第一初始信号线，第二极连接所述驱动晶体管的栅极；所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极；所述第四晶体管的第一极连接所述数据线，第二极连接所述驱动晶体管的第一极；所述第五晶体管的第一极连接电源线，第二极连接所述驱动晶体管的第一极；所述第六晶体管的第一极连接所述驱动晶体管的第二极，第二极连接所述发光单元的第一电极；所述第七晶体管的第一极连接第二初始信号线，第二极连接所述发光单元的第一电极；所述电容的第一电极连接所述驱动晶体管的栅极，第二电极连接所述电源线。
本公开一种示例性实施例中，所述显示面板还包括：第一有源层、第一栅极层、第二有源层、第三栅极层。第一有源层位于所述衬底基的一侧， 所述第一有源层包括第三有源部、第四有源部、第五有源部、第六有源部、第七有源部，所述第三有源部用于形成所述驱动晶体管的沟道区，所述第四有源部用于形成所述第四晶体管的沟道区，所述第五有源部用于形成所述第五晶体管的沟道区，所述第六有源部用于形成所述第六晶体管的沟道区，所述第七有源部用于形成所述第七晶体管的沟道区；第一栅极层位于所述第一有源层背离所述衬底基板的一侧，所述第一栅极层包括第一栅线、使能信号线、第二复位信号线、第一导电部，所述第一栅线在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第四有源部在所述衬底基板上的正投影，所述使能信号线在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第五有源部在所述衬底基板上的正投影、所述第六有源部在所述衬底基板上的正投影，所述第二复位信号线在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第七有源部在所述衬底基板上的正投影，所述第一导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影；第二有源层位于所述第一栅极层背离所述衬底基板的一侧，所述第二有源层包括第一有源部、第二有源部，所述第一有源部用于形成所述第一晶体管的沟道区，所述第二有源部用于形成所述第二晶体管的沟道区；第三栅极层位于所述第二有源层背离所述衬底基板的一侧，所述第三栅极层包括第二栅线、第一复位信号线，所述第二栅线在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第二有源部在所述衬底基板上的正投影，所述第一复位信号线在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第一有源部在所述衬底基板上的正投影；其中，所述第二复位信号线在所述衬底基板上的正投影、使能信号线在所述衬底基板上的正投影、所述第一导电部在所述衬底基板上的正投影、第二栅线在所述衬底基板上的正投影、第一栅线在所述衬底基板上的正投影、所述第一复位信号线在所述衬底基板上的正投影沿所述第二方向依次分布。
本公开一种示例性实施例中，所述第一方向为行方向，所述第二方向为列方向，本行像素驱动电路中所述第一栅线复用为相邻下一行像素驱动电路中的第二复位信号线。
本公开一种示例性实施例中，所述驱动晶体管、第四晶体管、第五晶 体管、第六晶体管、第七晶体管为P型晶体管，所述第一晶体管、第二晶体管为N型晶体管。
本公开一种示例性实施例中，所述第二信号线包括多个第二过孔接触部，多个所述第二过孔接触部在所述衬底基板上的正投影沿所述第二方向间隔分布；同一所述第二信号线中，在所述第二方向上相邻两所述第二过孔接触部在所述衬底基板上的正投影在所述第二方向上的距离为A1，所述第二数据扇出线和所述第二模拟线之间断口在所述衬底基板上的正投影在所述第二方向上的尺寸为A2；A1/A2大于等于27且小于等于68。
根据本公开的一个方面，提供一种显示装置，其中，包括上述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
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图1为本公开显示面板一种示例性实施例的结构示意图；
图2为本公开显示面板另一种示例性实施例的结构示意图；
图3为图2中第一区域K1的部分放大图；
图4为图3中第一信号线所在导电层的部分结构版图；
图5为图3中第二信号线所在导电层的部分结构版图；
图6为图2中第二区域K2的部分放大图；
图7为图6中第一信号线所在导电层的部分结构版图；
图8为图6中第二信号线所在导电层的部分结构版图；
图9为图2中第三区域K3的部分放大图；
图10为图9中第一信号线所在导电层的部分结构版图；
图11为图9中第二信号线所在导电层的部分结构版图；
图12为图2中第四区域K4的部分放大图；
图13为图12中第一信号线所在导电层的部分结构版图；
图14为图12中第二信号线所在导电层的部分结构版图；
图15为图2中第五区域K5的部分放大图；
图16为图15中第一信号线所在导电层的部分结构版图；
图17为图15中第二信号线所在导电层的部分结构版图；
图18为图2中第六区域K6的部分放大图；
图19为图18中第一信号线所在导电层的部分结构版图；
图20为图18中第二信号线所在导电层的部分结构版图；
图21为图2中第七区域K7的部分放大图；
图22为图21中第一信号线所在导电层结构版图；
图23为图21中第二信号线所在导电层结构版图；
图24为本公开显示面板另一种示例性实施例的结构版图；
图25为图24中第一信号线所在导电层的结构版图；
图26为图24中第二信号线所在导电层的结构版图；
图27为图24中电极层的结构版图；
图28为图3所示显示面板沿虚线CC的部分剖视图；
图29为本公开显示面板另一种示例性实施例的结构示意图；
图30为本公开显示面板另一种示例性实施例的结构示意图；
图31为本公开显示面板另一种示例性实施例的结构示意图；
图32为本公开显示面板中像素驱动电路的电路结构示意图；
图33为图32中像素驱动电路一种驱动方法中各节点的时序图；
图34为图2中第六区域K6的局部版图；
图35为图34中遮挡层的结构版图；
图36为图34中第一有源层的结构版图；
图37为图34中第一栅极层的结构版图；
图38为图34中第二栅极层的结构版图；
图39为图34中第二有源层的结构版图；
图40为图34中第三栅极层的结构版图；
图41为图34中第一源漏层的结构版图；
图42为图34中第二源漏层的结构版图；
图43为图34中电极层的结构版图；
图44为图34中遮挡层、第一有源层的结构版图；
图45为图34中遮挡层、第一有源层、第一栅极层的结构版图；
图46为图34中遮挡层、第一有源层、第一栅极层、第二栅极层的结构版图；
图47为图34中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层的结构版图；
图48为图34中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层的结构版图；
图49为图34中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层、第一源漏层的结构版图；
图50为图34中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层、第一源漏层、第二源漏层的结构版图；
图51为图34中单个重复单元的结构版图；
图52为图51中遮挡层的结构版图；
图53为图51中第一有源层的结构版图；
图54为图51中第一栅极层的结构版图；
图55为图51中第二栅极层的结构版图；
图56为图51中第二有源层的结构版图；
图57为图51中第三栅极层的结构版图；
图58为图51中第一源漏层的结构版图；
图59为图51中第二源漏层的结构版图；
图60为图51中电极层的结构版图；
图61为图51中遮挡层、第一有源层的结构版图；
图62为图51中遮挡层、第一有源层、第一栅极层的结构版图；
图63为图51中遮挡层、第一有源层、第一栅极层、第二栅极层的结构版图；
图64为图51中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层的结构版图；
图65为图51中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层的结构版图；
图66为图51中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层、第一源漏层的结构版图；
图67为图51中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层、第一源漏层、第二源漏层的结构版图；
图68为图51所示显示面板沿虚线EE剖开的部分剖视图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
如图1所示，为本公开显示面板一种示例性实施例的结构示意图。该显示面板可以包括显示区AA，以及位于显示区AA为扇出区FT。该显示面板还包括衬底基板、多条数据线Da、第一数据扇出线Fa1、第二数据扇出线Fa2。其中，数据线Da位于所述显示区AA，且数据线Da在衬底基板上的正投影沿第一方向X间隔分布且沿第二方向Y延伸，第一方向X和第二方向Y可以相交，例如，第一方向X可以为行方向，第二方向Y可以为列方向。第一数据扇出线Fa1位于所述扇出区FT，所述第一数据扇出线Fa1在衬底基板上的正投影可以沿第二方向间Y隔分布且沿所述第一方向X延伸，第一数据扇出线Fa1与所述数据线Da对应设置，第一数据扇出线Fa1连接与其对应的所述数据线Da。第二数据扇出线Fa2位于所述扇出区FT，第二数据扇出线Fa2在所述衬底基板上的正投影沿第一方向X间隔分布且沿第二方向Y延伸，第二数据扇出线Fa2与所述第一数据扇出线Fa1对应 设置，所述第二数据扇出线Fa2连接与其对应的所述第一数据扇出线Fa1。本示例性实施例提供的显示面板将扇出区设置于显示区，避免了在边框区设置扇出区，从而可以降低显示面板下边框和下边角区域的面积，即可以实现窄边框设置。
如图1所示，分隔线XX将显示区AA分隔成在第一方向X上分布的两个显示区。远离分隔线XX一侧的数据线Da通过第一数据扇出线Fa1连接靠近分隔线XX一侧的第二数据扇出线Fa2。扇出区FT可以包括第一扇出区FT1和第二扇出区FT2，第一数据扇出线Fa1位于第一扇出区FT1，第二数据扇出线Fa2位于第二扇出区FT2。第一扇出区FT1可以包括第一子扇出区FT11和第二子扇出区FT12，第一子扇出区FT11和第二子扇出区FT12位于第二扇出区FT2在第一方向X上的两侧。
应该理解的是，在其他示例性实施例中，第一数据扇出线Fa1和第二数据扇出线Fa2还可以有其他设置方式。例如，靠近分隔线XX一侧的数据线Da通过第一数据扇出线Fa1连接靠近分隔线XX一侧的第二数据扇出线Fa2；或，远离分隔线XX一侧的数据线Da通过第一数据扇出线Fa1连接远离分隔线XX一侧的第二数据扇出线Fa2。再例如，第一数据扇出线Fa1的长度还可以自上边框向下边框方式逐渐增加。
本示例性实施例中，显示面板在扇出区FT增设有第一数据扇出线Fa1和第二数据扇出线Fa2，扇出区FT以外的显示区没有设置第一数据扇出线Fa1和第二数据扇出线Fa2。由于第一数据扇出线Fa1和第二数据扇出线Fa2具有反光和遮光作用，显示面板在息屏状态下，显示面板的扇出区和其他显示区具有不同的反光和透光效果，从而导致显示面板出现暗影。
基于此，本示例性实施例还提供另一种显示面板，如图2所示，为本公开显示面板另一种示例性实施例的结构示意图。该显示面板可以包括多条第一信号线H1，多条第二信号线V2。其中，第一信号线H1位于所述显示区AA，所述第一信号线H1在所述衬底基板上的正投影沿所述第一方向X延伸且沿所述第二方向Y间隔分布，多条所述第一信号线H1中包括第一子信号线H11、第三模拟线Dm3。所述第一子信号线H11包括间隔设置的第一数据扇出线Fa1和第一模拟线Dm1；第三模拟线Dm3位于所述第一扇出区FT1以外的显示区AA。第二信号线V2位于所述显示区AA，且第二信 号线V2与所述第一信号线H1位于不同导电层，所述第二信号线V2在所述衬底基板上的正投影沿所述第二方向Y延伸且沿所述第一方向X间隔分布，多条所述第二信号线V2中包括第二子信号线V22和第四模拟线Dm4。所述第二子信号线V22包括间隔设置的第二数据扇出线Fa2和第二模拟线Dm2；第四模拟线Dm4位于所述第二扇出区FT2以外的显示区AA。
如图2所示，本示例性实施例通过增设第一模拟线Dm1、第二模拟线Dm2、第三模拟线Dm3、第四模拟线Dm4，从而可以使得整个显示区AA中信号线的密度接近一致，从而解决了上述暗影的技术问题。需要说明的是，当第一数据扇出线Fa1和第二数据扇出线Fa2以其他方式分布时，本公开也可以通过增设模拟线的方式消除上述暗影。
本示例性实施例中，多条所述第一信号线H1可以位于同一导电层，多条所述第二信号线V2可以位于同一导电层；所述第二信号线V2所在导电层可以位于所述第一信号线H1所在导电层背离所述衬底基板的一侧。例如，第一信号线H1可以位于显示面板的第一源漏层，第二信号线V2可以位于显示面板的第二源漏层。此外，数据线Da也可以位于显示面板的第二源漏层，第二信号线V2在所述衬底基板上的正投影可以位于相邻两所述数据线Da在所述衬底基板上的正投影之间。
应该理解的是，在其他示例性实施例中，第一信号线和第二信号线也可以位于其他导电层，例如，第一信号线还可以位于显示面板中的第一栅极层、第二栅极层、第三栅极层，第一信号线和第二信号线还可以位于增设的导电层，此外，第一信号线和第二信号线也可以位于同一导电层。
如图3、4、5所示，图3为图2中第一区域K1的部分放大图，图4为图3中第一信号线所在导电层的部分结构版图，图5为图3中第二信号线所在导电层的部分结构版图。其中，第一区域K1部分位于第一子扇出区FT11，第一区域K1部分位于第二扇出区FT2，第一区域K1部分位于第一子扇出区FT11远离第二扇出区FT2的显示区。如图2-5所示，第一数据扇出线Fa1可以通过过孔H连接数据线Da，且通过过孔连接第二数据扇出线Fa2。其中，图2中黑色圆形表示过孔的位置，图3中黑色方块表示过孔的位置。
如图6、7、8所示，图6为图2中第二区域K2的部分放大图，图7 为图6中第一信号线所在导电层的部分结构版图，图8为图6中第二信号线所在导电层的部分结构版图。其中，第二区域K2位于第一子扇出区FT11远离第二扇出区FT2的显示区。如图2、6-8所示，在第二区域K2中，第四模拟线Dm4通过过孔H连接与其在衬底基板上正投影相交的第一模拟线Dm1。图6中黑色方块表示过孔的位置。此外，第二子扇出区FT12远离第二扇出区FT2的显示区可以和第二区域K2具有相同的结构。
如图9、10、11所示，图9为图2中第三区域K3的部分放大图，图10为图9中第一信号线所在导电层的部分结构版图，图11为图9中第二信号线所在导电层的部分结构版图。其中，第三区域K3位于第一子扇出区FT11。如图2、9-11所示，第一数据扇出线Fa1和与其在衬底基板上正投影相交的第二模拟线Dm2、第四模拟线Dm4不连接。第一子扇出区FT11和第二子扇出区FT12的结构可以相同。
如图12、13、14所示，图12为图2中第四区域K4的部分放大图，图13为图12中第一信号线所在导电层的部分结构版图，图14为图12中第二信号线所在导电层的部分结构版图。其中，第四区域K4位于第二扇出区FT2。如图2、12-14所示，第二数据扇出线Fa2和与其在衬底基板上正投影相交的第一模拟线Dm1不连接。
如图15、16、17所示，图15为图2中第五区域K5的部分放大图，图16为图15中第一信号线所在导电层的部分结构版图，图17为图15中第二信号线所在导电层的部分结构版图。其中，第五区域K5位于第二扇出区FT2在第一方向X上的中间位置。如图2、15-17所示，多条所述第二信号线V2中还包括第五模拟线Dm5，所述第五模拟线Dm5的部分结构位于第二扇出区FT2，且所述第五模拟线Dm5通过过孔连接与其在衬底基板上正投影相交的第一模拟线Dm1和第三模拟线Dm3，图15中黑色方块表示过孔的位置。本示例性实施例中，第五模拟线可以为一条，应该理解的是，在其他示例性实施例中，第五模拟线还可以为多条。
如图18、19、20所示，图18为图2中第六区域K6的部分放大图，图19为图18中第一信号线所在导电层的部分结构版图，图20为图18中第二信号线所在导电层的部分结构版图。第六区域K6位于扇出区远离显示面板下边框一侧的显示区。如图2、18-20所示，在第六区域K6中，第 三模拟线Dm3通过过孔连接与其在衬底基板上正投影相交的第四模拟线Dm4，图18中黑色方块表示过孔的位置。
本示例性实施例中，如图2-20所示，相邻两所述第一信号线H1在所述衬底基板上的正投影在所述第二方向Y上的最小距离为S1，相邻两所述第一信号线H1在所述衬底基板上的正投影在所述第二方向Y上的最大距离为S2，其中，(S2-S1)/S1可以大于等于0且小于等于0.2，例如，(S2-S1)/S1可以等于0、0.05、0.1、0.2等。当(S2-S1)/S1等于0时，即第一信号线H1在所述衬底基板上的正投影在所述第二方向Y上等间距分布。如图2-20所示，相邻两所述第二信号线V2在所述衬底基板上的正投影在所述第一方向X上的最小距离为S3，相邻两所述第二信号线V2在所述衬底基板上的正投影在所述第一方向X上的最大距离为S4，其中，(S4-S3)/S3大于等于0且小于等于0.2，例如，(S4-S3)/S3可以等于0、0.05、0.1、0.2等。当(S4-S3)/S3等于0时，即第二信号线V2在所述衬底基板上的正投影在所述第一方向X上等间距分布。该设置可以使得第一信号线H1和第二信号线V2在显示区均匀分布，从而进一步消除上述暗影问题。
本示例性实施例中，显示面板还可以包括像素驱动电路和发光单元，所述像素驱动电路连接所述发光单元的第一电极。所述显示面板还可以包括：公共电极层，所述公共电极层用于形成所述发光单元的第二电极。其中，所述第一模拟线Dm1、所述第二模拟线Dm2、所述第三模拟线Dm3、所述第四模拟线Dm4可以连接所述公共电极层。例如，所述第一模拟线Dm1、所述第二模拟线Dm2、所述第三模拟线Dm3、所述第四模拟线Dm4可以通过位于显示区周围边框区的过孔连接公共电极层。形成网格结构的第一模拟线Dm1、所述第二模拟线Dm2、所述第三模拟线Dm3、所述第四模拟线Dm4可以降低公共电极层自身电阻，从而降低显示面板不同位置上发光单元第二电极的电压差，该设置可以提高显示面板显示的均一性。
如图21-23所示，图21为图2中第七区域K7的部分放大图，图22为图21中第一信号线所在导电层结构版图，图23为图21中第二信号线所在导电层结构版图。如图2所示，所述显示面板还可以包括位于所述显示区AA周围的边框区BB，所述边框区BB包括相对设置的第一边框区BB1和第二边框区BB2，所述扇出区FT位于靠近所述第二边框区BB2的一侧。 所述显示面板还可以包括：电极环VSS、电源电路(未画出)。所述电极环VSS位于所述边框区BB，电极环VSS可以为位于边框区BB的环形结构，电极环VSS可以在不同位置连接公共电极层。电极环VSS位于所述第一边框区BB1的部分结构连接所述第二模拟线Dm2和所述第四模拟线Dm4。电源电路可以绑定于所述第二边框区BB2，且所述电源电路连接所述电极环VSS位于所述第二边框区BB2的至少部分结构，所述电源电路可以用于向所述电极环VSS提供电源信号。远离电源电路一侧的公共电极层具有较大的压降，本申请通过位于第一边框区BB1的电极环VSS向第二模拟线Dm2和所述第四模拟线Fm4提供电源电压，从而可以降低公共电极层在第二方向Y上的压降。
如图21-23所示，电极环VSS可以包括第一电极环4VSS和第二电极环5VSS，第一电极环4VSS在衬底基板上的正投影和第二电极环5VSS在衬底基板上的正投影至少部分交叠，第二电极环5VSS通过过孔连接第一电极环4VSS，图21中黑色方块表示过孔位置。双层导电层的电极环可以降低电极环的自身电阻。第一边框区B1中还可以设置有电源连接线VDDx，电源连接线VDDx可以包括第一电源连接线4VDD和第二电源连接线5VDD，第一电源连接线4VDD和第二电源连接线5VDD在衬底基板上的正投影至少部分交叠，第一电源连接线4VDD和第二电源连接线5VDD通过过孔连接。电源连接线VDDx可以连接位于显示区的电源线VDD。
本示例性实施例中，如图2-20所示，所述第一信号线H1可以包括多个第一过孔接触部Ht1和第一延伸部Lt1，多个所述第一过孔接触部Ht1在所述衬底基板上的正投影沿所述第一方向X间隔分布，所述第一延伸部Lt1连接于所述第一过孔接触部Ht1，所述第一过孔接触部Ht1在所述衬底基板上的正投影在所述第二方向Y上的尺寸大于所述第一延伸部Lt1在所述衬底基板上的正投影在所述第二方向Y上的尺寸。所述第二信号线V2可以包括多个第二过孔接触部Ht2和第二延伸部Lt2，多个所述第二过孔接触部Ht2在所述衬底基板上的正投影沿所述第二方向Y间隔分布，所述第二延伸部Lt2连接于所述第二过孔接触部Ht2，所述第二过孔接触部Ht2在所述衬底基板上的正投影在所述第一方向X上的尺寸大于所述第二延伸部Lt2在所述衬底基板上的正投影在所述第一方向X上的尺寸。其中，所 述第一过孔接触部Ht1和所述第二过孔接触部Ht2对应设置，所述第一过孔接触部Ht1在所述衬底基板上的正投影和与其对应的所述第二过孔接触部Ht2在所述衬底基板上的正投影至少部分交叠。
如图2-20所示，所述第一过孔接触部Ht1可以包括第一实孔接触部Htr1和第一虚孔接触部Htd1，所述第二过孔接触部Ht2可以包括第二实孔接触部Htr2和第二虚孔接触部Htd2。所述第一实孔接触部Htr1和与其对应的所述第二实孔接触部Htr2通过过孔连接，即第一信号线H1和第二信号线V2可以通过第一实孔接触部Htr1和第二实孔接触部Htr2过孔连接。第一虚孔接触部Htd1和与其对应的所述第二虚孔接触部Htd2绝缘设置。第一虚孔接触部Htd1可以模拟第一实孔接触部Htr1的反光现象，第二虚孔接触部Htd2可以模拟第二实孔接触部Htr2的反光现象。从而第一虚孔接触部Htd1、第二虚孔接触部Htd2可以改善显示面板息屏下的暗影问题。此外，第一虚孔接触部Htd1可以模拟第一实孔接触部Htr1的寄生电容，第二虚孔接触部Htd2可以模拟第二实孔接触部Htr2的寄生电容，从而第一虚孔接触部Htd1、第二虚孔接触部Htd2可以提高显示面板的显示均一性。
本示例性实施例中，第一虚孔接触部Htd1和第二虚孔接触部Htd2在衬底基板上的正投影交叠。从而从反光角度出发，显示面板可以择一设置第一虚孔接触部Htd1或第二虚孔接触部Htd2。
本示例性实施例中，如图2-20所示，相邻所述第一过孔接触部Ht1在所述衬底基板上的正投影在所述第一方向X上的最小距离为S5，相邻所述第一过孔接触部Ht1在所述衬底基板上的正投影在所述第一方向X上的最大距离为S6，其中，(S6-S5)/S5可以大于等于0且小于等于0.2，例如，(S6-S5)/S5可以等于0、0.05、0.1、0.2等。当(S6-S5)/S5等于0时，第一过孔接触部Ht1在衬底基板上的正投影在第一方向X上等间距分布。等间距分布的第一过孔接触部Ht1可以进一步改善显示面板息屏下的暗影问题。如图2-20所示，相邻所述第二过孔接触部Ht2在所述衬底基板上的正投影在所述第二方向Y上的最小距离为S7，相邻所述第二过孔接触部Ht2在所述衬底基板上的正投影在所述第二方向Y上的最大距离为S8，其中，(S8-S7)/S7大于等于0且小于等于0.2。例如，(S8-S7)/S7 可以等于0、0.05、0.1、0.2等。当(S8-S7)/S7等于0时，第二过孔接触部Ht2在所述衬底基板上的正投影在所述第二方向Y上等间距分布，等间距分布的第二过孔接触部Ht2可以进一步改善显示面板息屏下的暗影问题。
本示例性实施例中，显示面板还包括像素驱动电路和发光单元，所述像素驱动电路连接所述发光单元的第一电极，所述显示面板还包括用于形成所述发光单元第一电极的电极层。如图24、25、26、27所示，图24为本公开显示面板另一种示例性实施例的结构版图，图25为图24中第一信号线所在导电层的结构版图，图26为图24中第二信号线所在导电层的结构版图，图27为图24中电极层的结构版图。电极层可以包括多个电极部，多个电极部中包括第一电极部R、第二电极部B、第三电极部G。第一电极部R可以用于形成红色发光单元的第一电极；第二电极部B可以用于形成蓝色发光单元的第一电极；第三电极部G可以用于形成绿色发光单元的第一电极。其中，该显示面板还包括包括位于电极层背离衬底基板一侧的像素定义层，像素定义层上形成有用于形成发光单元的像素开口。第一电极部R在衬底基板上的正投影和像素定义层上与其对应的像素开口在衬底基板上的正投影重合，第三电极部G在衬底基板上的正投影和与其对应的像素开口在衬底基板上的正投影重合，第二电极部B在衬底基板上的正投影和与其对应的像素开口在衬底基板上的正投影重合。
如图24-27所示，所述第一数据扇出线Fa1和所述第一模拟线Dm1之间断口D1在所述衬底基板上的正投影与所述电极部在所述衬底基板上的正投影不交叠；所述第二数据扇出线Fa2和所述第二模拟线Dm2之间断口D2在所述衬底基板上的正投影与所述电极部在所述衬底基板上的正投影不交叠。该设置可以提高电极部的平坦度，平坦度较高的电极部上可以形成平坦度较高的发光材料层，从而该设置提高显示面板显示的均一性。
本示例性实施例中，第一实孔接触部Htr1和第二实孔接触部Htr2通过过孔连接，第二实孔接触部Htr2在过孔位置会出现面向衬底基板的凹陷，第二实孔接触部Htr2在凹陷位置会出现较强的反光现象。然而，由于第一虚孔接触部Htd1和第二虚孔接触部Htd2并不连接，第二虚孔接触部Htd2较为平坦，第二虚孔接触部Htd2的反光较弱，第二虚孔接触部Htd2 和第二实孔接触部Htr2不一致的反光能力容易导致显示面板息屏状态下出现暗影。
如图28所示，为图3所示显示面板沿虚线CC的部分剖视图。第一信号线位于第一源漏层，第二信号线位于第二源漏层，该显示面板还可以包括位于衬底基板90一侧的钝化层97、第一平坦层98，钝化层97位于第一源漏层和第二源漏层之间。第一平坦层98位于钝化层97和第二源漏层之间。第一平坦层98的厚度远大于钝化层97的厚度。本示例性实施例中，可以通过减小钝化层97和/或第一平坦层98的厚度减小第二实孔接触部Htr2在过孔位置处的凹陷深度，从而改善上述暗影问题。本示例性实施例中，第一平坦层98的厚度可以小于等于1.6um，例如，第一平坦层98的厚度可以为1.2um、1.3um、1.4um、1.5um、1.6um；钝化层97的厚度可以为1000埃到5000埃，例如，钝化层97的厚度可以为1000埃、2000埃、3000埃、4000埃、5000埃。
如图29所示，为本公开显示面板另一种示例性实施例的结构示意图。该显示面板中的第一源漏层和第二源漏层之间可以仅设置第一平坦层98，该设置同样可以降低第二实孔接触部Htr2在过孔位置处的凹陷深度，从而改善上述暗影问题。
如图30所示，为本公开显示面板另一种示例性实施例的结构示意图。本示例性实施例中，第一平坦层98上形成有第一开孔H3，所述第一开孔H3在所述衬底基板上的正投影与所述第二虚孔接触部Htd2在所述衬底基板上的正投影至少部分交叠。该设置可以使得第二虚孔接触部Htd2形成面向衬底基板90的凹槽，从而通过增加第二虚孔接触部Htd2反光能力提高显示区反光的均一度。其中，第一开孔H3可以为贯穿第一平坦层98的开孔，也可以为没有贯穿第一平坦层98的盲孔。
如图31所示，为本公开显示面板另一种示例性实施例的结构示意图。本示例性实施例中，所述钝化层97上形成有第二开孔H2，所述第二开孔H2在所述衬底基板上的正投影与所述第二虚孔接触部Htd2在所述衬底基板上的正投影至少部分交叠。该设置可以使得第二虚孔接触部Htd2形成面向衬底基板90凹陷的凹槽，从而通过增加第二虚孔接触部Htd2反光能力提高显示区反光的均一度。其中，第二开孔H2可以为贯穿钝化层97的 开孔，也可以为没有贯穿钝化层97的盲孔。
本示例性实施例中，由于第一过孔接触部Ht1和第二过孔接触部Ht2在衬底基板上的正投影交叠，从而第二过孔接触部Ht2相比其他位置具有较高的凸起。同时，由于第二实孔接触部Htr2的局部区域具有凹槽，为了提高电极部的平坦度，如图24所示，本示例性实施例中，所述第一过孔接触部Ht1在所述衬底基板上的正投影和所述电极部在所述衬底基板上的正投影不交叠；所述第二过孔接触部Ht2在所述衬底基板上的正投影和所述电极部在所述衬底基板上的正投影不交叠。
如图26所示，在位于第二信号线V2相邻两侧的数据线Da中，数据线Da包括第三延伸部Lt3、第四延伸部Lt4、第五延伸部Lt5，所述第四延伸部Lt4连接于所述第三延伸部Lt3和所述第五延伸部Lt5之间。其中，位于第二信号线V2相邻两侧的数据线Da是指，与第二信号线V2之间没有其他数据线的数据线。所述第二过孔接触部Ht2和所述第四延伸部Lt4的至少部分结构在所述第一方向X上相对设置，且所述第四延伸部Lt4在所述衬底基板上的正投影和所述第二延伸部Lt2在所述衬底基板上的正投影在所述第一方向X上的尺寸大于所述第三延伸部Lt3在所述衬底基板上的正投影和所述第二延伸部Lt2在所述衬底基板上的正投影在所述第一方向X上的尺寸，所述第四延伸部Lt4在所述衬底基板上的正投影和所述第二延伸部Lt2在所述衬底基板上的正投影在所述第一方向X上的尺寸大于所述第五延伸部Lt5在所述衬底基板上的正投影和所述第二延伸部Lt2在所述衬底基板上的正投影在所述第一方向X上的尺寸。其中，结构A和结构B在第一方向上相对设置，可以理解为，结构A在衬底基板上的正投影在第一方向上无限移动所覆盖区域和结构B在衬底基板上的正投影在第一方向上无限移动所覆盖区域重合。该设置可以使得第二过孔接触部Ht2具有充分的设置空间。
如图24-27所示，所述第一数据扇出线Fa1和所述第一模拟线Dm1之间断口D1在所述衬底基板上的正投影在所述第一方向X上的尺寸可以为1.5um-3.5um，例如，断口D1在所述衬底基板上的正投影在所述第一方向X上的尺寸可以为1.5um、2um、2.5um、3um、3.5um等。所述第二数据扇出线Fa2和所述第二模拟线Dm2之间断口D2在所述衬底基板上的正投影 在所述第二方向Y上的尺寸为1.5um-3.5um，例如，断口D2在所述衬底基板上的正投影在所述第二方向Y上的尺寸为1.5um、2um、2.5um、3um、3.5um等。当断口D1在所述衬底基板上的正投影在所述第一方向X上的尺寸和断口D2在所述衬底基板上的正投影在所述第二方向Y上的尺寸较小时，显示面板不会出现明显的暗影。
本示例性实施例中，同一所述第二信号线中，在所述第二方向Y上相邻两所述第二过孔接触部Ht2在所述衬底基板上的正投影在所述第二方向上Y的距离为A1，所述第二数据扇出线Fa2和所述第二模拟线Dm2之间断口D2在所述衬底基板上的正投影在所述第二方向Y上的尺寸为A2；A1/A2可以大于等于27且小于等于68，例如，A1/A2可以等于27、28、29、35、40、54、50、55、60、65、66、67等。
如图32所示，为本公开显示面板中像素驱动电路的电路结构示意图。该像素驱动电路可以包括：驱动晶体管T3、第一晶体管T1、第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、电容C。其中，第四晶体管T4的第一极连接数据信号端Da，第四晶体管T4的第二极连接驱动晶体管T3的第一极，第四晶体管T4的栅极连接第一栅极驱动信号端G1；第五晶体管T5的第一极连接第一电源端VDD，第五晶体管T5的第二极连接驱动晶体管T3的第一极，第五晶体管T5的栅极连接使能信号端EM；驱动晶体管T3的栅极连接节点N；第二晶体管T2的第一极连接节点N，第二晶体管T2的第二极连接驱动晶体管T3的第二极，第二晶体管T2的栅极连接第二栅极驱动信号端G2；第六晶体管T6的第一极连接驱动晶体管T3的第二极，第六晶体管T6第二极连接第七晶体管T7的第二极，第六晶体管T6栅极连接使能信号端EM，第七晶体管T7的第一极连接第二初始信号端Vinit2，第七晶体管T7的栅极连接第二复位信号端Re2；第一晶体管T1的第二极连接节点N，第一晶体管T1的第一极连接第一初始信号端Vinit1，第一晶体管T1的栅极连接第一复位信号端Re1；电容C的第一电极连接节点N，电容C的第二电极连接第一电源端VDD。该像素驱动电路可以连接一发光单元OLED，像素驱动电路用于驱动该发光单元OLED发光，发光单元OLED的第一电极可以连接于第六晶体管T6的第二极，发光单元的第二电极可以连接第二电源端VSS，发光单元的第一 电极可以为发光单元的阳极，发光单元的第二电极可以为发光单元的阴极。其中，第一晶体管T1和第二晶体管T2可以为N型晶体管，例如，第一晶体管T1和第二晶体管T2可以为N型金属氧化物晶体管，N型晶体管具有较小的漏电流，从而可以避免发光阶段，节点N通过第一晶体管T1和第二晶体管T2漏电。同时，驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型晶体管，例如，驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型低温多晶体硅晶体管，P型晶体管具有较高的载流子迁移率，从而有利于实现高分辨率、高反应速度、高像素密度、高开口率的显示面板。第一初始信号端和第二初始信号端可以根据实际情况输出相同或不同电压信号。
如图33所示，为图32中像素驱动电路一种驱动方法中各节点的时序图。其中，G1表示第一栅极驱动信号端G1的时序，G2表示第二栅极驱动信号端G2的时序，Re1表示第一复位信号端Re1的时序，Re2表示第二复位信号端Re2的时序，EM表示使能信号端EM的时序，Da表示数据信号端Da的时序。该像素驱动电路的驱动方法可以包括复位阶段t1、数据写入阶段t2，发光阶段t3。在复位阶段t1：第一复位信号端Re1输出高电平信号，第二复位信号端Re2输出低电平信号，第一晶体管T1、第七晶体管T7导通，第一初始信号端Vinit1向节点N输入第一初始信号，第二初始信号端Vinit2向发光单元OLED的第一电极输入第二初始信号。在数据写入阶段t2：第二栅极驱动信号端G2输出高电平信号，第一栅极驱动信号端G1输出低电平信号，第四晶体管T4、第二晶体管T2导通，同时数据信号端Da输出数据信号以向节点N写入补偿电压Vdata+Vth，其中Vdata为数据信号的电压，Vth为驱动晶体管T3的阈值电压。在发光阶段t3：使能信号端EM输出低电平信号，第六晶体管T6、第五晶体管T5导通，驱动晶体管T3在电容C存储的补偿电压Vdata+Vth作用下驱动发光单元发光。
驱动晶体管输出电流公式如下：
I＝(μWCox/2L)(Vgs-Vth)2
其中，I为驱动晶体管输出电流；μ为载流子迁移率；Cox为单位面 积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电压。本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth)2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。应该理解的是，在其他示例性实施例中，该像素驱动电路还可以有其他驱动方法，例如，第七晶体管T7可以在数据写入阶段t2和发光阶段t3之间的时段对发光单元的第一电极进行复位。
本示例性实施例中，显示面板可以包括依次层叠设置的衬底基板、遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层、第一源漏层、第二源漏层、电极层，其中，上述相邻层级之间可以设置有绝缘层。如图34-50所示，图34为图2中第六区域K6的局部版图，图35为图34中遮挡层的结构版图，图36为图34中第一有源层的结构版图，图37为图34中第一栅极层的结构版图，图38为图34中第二栅极层的结构版图，图39为图34中第二有源层的结构版图，图40为图34中第三栅极层的结构版图，图41为图34中第一源漏层的结构版图，图42为图34中第二源漏层的结构版图，图43为图34中电极层的结构版图，图44为图34中遮挡层、第一有源层的结构版图，图45为图34中遮挡层、第一有源层、第一栅极层的结构版图，图46为图34中遮挡层、第一有源层、第一栅极层、第二栅极层的结构版图，图47为图34中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层的结构版图，图48为图34中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层的结构版图，图49为图34中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层、第一源漏层的结构版图，图50为图34中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层、第一源漏层、第二源漏层的结构版图。该显示面板可以包括多个图32所示的像素驱动电路。如图50所示，多个像素驱动电路中可以包括在第一方向X上相邻分布第一像素驱动电路P1和第二像素驱动电路P2，第一像素驱动电路P1和第二像素驱动电路P2可以以镜像对称面DD镜像对称设置。其中，镜像对称面DD可以垂直于衬底基板。且第一像素驱动电路P1在衬底基板上的正投影和第二像素驱动电路P2在衬底基板上的正 投影可以以镜像对称面DD与衬底基板的交线为对称轴对称设置。其中，第一像素驱动电路P1和第二像素驱动电路P2可以形成一子重复单元，该显示面板可以包括在第一方向X和第二方向Y上阵列分布的多个子重复单元。其中，二乘二阵列分布的四个子重复单元可以形成一重复单元Pc。如图51-67所示，图51为图34中单个重复单元的结构版图，图52为图51中遮挡层的结构版图，图53为图51中第一有源层的结构版图，图54为图51中第一栅极层的结构版图，图55为图51中第二栅极层的结构版图，图56为图51中第二有源层的结构版图，图57为图51中第三栅极层的结构版图，图58为图51中第一源漏层的结构版图，图59为图51中第二源漏层的结构版图，图60为图51中电极层的结构版图，图61为图51中遮挡层、第一有源层的结构版图，图62为图51中遮挡层、第一有源层、第一栅极层的结构版图，图63为图51中遮挡层、第一有源层、第一栅极层、第二栅极层的结构版图，图64为图51中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层的结构版图，图65为图51中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层的结构版图，图66为图51中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层、第一源漏层的结构版图，图67为图51中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层、第一源漏层、第二源漏层的结构版图。
本示例性实施例可以通过压缩重复单元的方式在显示面板中增设上述的第一信号线和第二信号线。其中，在所述第一方向X上分布的多个所述重复单元形成重复单元行，每个所述重复单元行对应设置一条第一信号线H1；在第一方向X上相邻的重复单元之间对应设置一条所述第二信号线V2。
如图34、35、44、51、52、61所示，遮挡层可以包括多个遮挡部61、相邻遮挡部61之间可以相互连接。如图35所示，在第一方向X上相邻的重复单元中，相邻遮挡部61在衬底基板上的正投影在第一方向X上的最小距离为L5；在位于同一所述重复单元中且在所述第一方向X上相邻的两所述子重复单元中，相邻遮挡部61在衬底基板上的正投影在第一方向X上的最小距离为L6。其中，L6小于L5。在第二方向Y上相邻的重复单元 中，相邻遮挡部61在衬底基板上的正投影在第二方向Y上的最小距离为L16；在位于同一所述重复单元中且在所述第二方向Y上相邻的两所述子重复单元中，相邻遮挡部61在衬底基板上的正投影在第二方向Y上的最小距离为L15。其中，L15小于L16。应该理解的是，在其他示例性实施例中，该显示面板也可以不包括遮挡层。
如图34、36、45、51、53、62所示，第一有源层可以包括第三有源部73、第四有源部74、第五有源部75、第六有源部76、第七有源部77。其中，第三有源部73可以用于形成驱动晶体管T3的沟道区；第四有源部74可以用于形成第四晶体管T4的沟道区；第五有源部75可以用于形成第五晶体管T5的沟道区；第六有源部76可以用于形成第六晶体管T6的沟道区；第七有源部77可以用于形成第七晶体管T7的沟道区。第一有源层还包括第九有源部79、第十有源部710、第十一有源部711、第十二有源部712、第十三有源部713。其中，第九有源部79连接于第五有源部75远离第三有源部73的一侧，且第九有源部79连接于在第一方向X上相邻子重复单元中相邻两第五有源部75之间。第十有源部710连接于第六有源部76和第七有源部77之间，第十一有源部711连接于第六有源部76和第三有源部73之间，第十二有源部712连接于第四有源部74远离第三有源部73的一端，第十三有源部713连接于第七有源部77远离第六有源部76的一端。其中，遮挡部61在衬底基板上的正投影可以覆盖第三有源部73在衬底基板上的正投影，遮挡部61可以降低光照对驱动晶体管T3驱动特性的影响。如图36所示，在第一方向X上相邻的重复单元中，连接于相邻第五有源部75之间的第九有源部79在衬底基板上的正投影在第一方向X上的尺寸为L7；在位于同一所述重复单元中且在所述第一方向X上相邻的两所述子重复单元中，连接于相邻第五有源部75之间的第九有源部79在衬底基板上的正投影在第一方向X上的尺寸为L8，其中，L7大于L8。在第二方向Y上相邻的重复单元中，相邻第十二有源部712和第九有源部79在衬底基板上的正投影在第二方向Y上的最小距离为L18；在位于同一所述重复单元中且在所述第二方向Y上相邻的两所述子重复单元中，相邻第十二有源部712和第九有源部79在衬底基板上的正投影在第二方向Y上的最小距离为L17，其中L18大于L17。第一有源层可以由多晶硅 材料形成，相应的，驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型的低温多晶硅薄膜晶体管。
如图34、37、45、51、54、62所示，第一栅极层可以包括：第一导电部11、第一栅线G1、使能信号线EM、第二复位信号线Re2。第一栅线G1可以用于提供图32中第一栅极驱动信号端；使能信号线EM可以用于提供图32中的使能信号端；第二复位信号线Re2可以用于提供图32中的第二复位信号端。第一栅线G1在衬底基板上的正投影、使能信号线EM在衬底基板上的正投影、第二复位信号线Re2在衬底基板上的正投影均可以沿第一方向X延伸。第一栅线G1在衬底基板上的正投影覆盖第四有源部74在衬底基板上的正投影，第一栅线G1的部分结构用于形成第四晶体管的栅极。使能信号线EM在衬底基板上的正投影覆盖第五有源部75在衬底基板上的正投影、第六有源部76在衬底基板上的正投影，使能信号线EM的部分结构可以分别用于形成第五晶体管T5、第六晶体管T6的栅极。第二复位信号线Re2在衬底基板上的正投影可以覆盖第七有源部77在衬底基板上的正投影，第二复位信号线Re2的部分结构可以用于形成第七晶体管T7的栅极。第一导电部11在衬底基板上的正投影覆盖第三有源部73在衬底基板上的正投影，第一导电部11可以用于形成驱动晶体管T3的栅极和电容C的第一电极。如图45、62所示，本行像素驱动电路中的第一栅线G1可以复用为下一行像素驱动电路中的第二复位信号线Re2，该显示面板可以自上向下逐行驱动，也可以自下向上逐行驱动。该设置可以提高像素驱动电路的集成度，降低像素驱动电路的布图面积。遮挡层还可以连接一稳定电源端，例如，遮挡层可以连接图32中的第一电源端、第一初始信号端、第二初始信号端等，遮挡部61可以屏蔽其他信号对驱动晶体管T3的噪音影响。如图50所示，在第一方向X上分布的多个重复单元形成重复单元行，同一所述重复单元行包括第一像素驱动电路行Ph1和第二像素驱动电路行Ph2，所述第一像素驱动电路行Ph1包括沿所述第一方向X分布的多个像素驱动电路，所述第二像素驱动电路行Ph2包括沿所述第一方向分布的多个像素驱动电路。如图37所示，在所述第一像素驱动电路行Ph1中，所述使能信号线EM在所述衬底基板上的正投影和所述第二复位信号线Re2在所述衬底基板上的正投影在所述第二方向Y上的最小距离为L3； 在所述第二像素驱动电路行Ph2中，所述使能信号线EM在所述衬底基板上的正投影和所述第二复位信号线Re2在所述衬底基板上的正投影在所述第二方向上的距离为L4，其中，L3大于L4。在第一方向X上相邻的重复单元中，相邻第一导电部11在衬底基板上的正投影在第一方向X上的最小距离为L19；在位于同一所述重复单元中且在所述第一方向X上相邻的两所述子重复单元中，相邻第一导电部11在衬底基板上的正投影在第一方向X上的最小距离为L20。其中，L20小于L19。此外，该显示面板可以利用第一栅极层为掩膜对第一有源层进行导体化处理，即第一有源层中被第一栅极层覆盖的区域可以形成晶体管的沟道区，第一有源层中未被第一栅极层覆盖的区域形成导体结构。
如图34、38、46、51、55、63所示，第二栅极层可以包括：第一初始信号线Vinit1、第三复位信号线2Re1、第三栅线2G2、多个第二导电部22。其中，第一初始信号线Vinit1用于提供图32中的第一初始信号端，第三复位信号线2Re1可以用于提供图32中的第一复位信号端，第三栅线2G2可以用于提供图32中的第二栅极驱动信号端。第一初始信号线Vinit1在衬底基板上的正投影、第三复位信号线2Re1在衬底基板上的正投影、第三栅线2G2在衬底基板上的正投影均可以沿第一方向X延伸。如图38、55所示，第二栅极层还可以包括多个连接部23，在第一方向X上相邻的子重复单元中，连接部23连接于在第一方向X上相邻的两第二导电部22之间。如图38所示，在第一方向X上相邻的重复单元中，连接于相邻第二导电部22之间的连接部23在衬底基板上的正投影在第一方向X上的尺寸为L10；在位于同一所述重复单元中且在所述第一方向X上相邻的两所述子重复单元中，连接于相邻第二导电部22之间的连接部23在衬底基板上的正投影在第一方向X上的尺寸为L9，L10大于L9。在第二方向Y上相邻的重复单元中，相邻第二导电部和第一初始信号线Vinit1在衬底基板上的正投影在第一方向X上的尺寸为L22；在位于同一所述重复单元中且在所述第二方向Y上相邻的两所述子重复单元中，相邻第二导电部和第一初始信号线Vinit1在衬底基板上的正投影在第一方向X上的尺寸为L21，L22大于L21。此外，在其他示例性实施例中，在同一重复单元中，相邻第二导电部22也可以相连接。
如图34、39、47、51、56、64所示，第二有源层可以包括有源部8，有源部8可以包括：第一有源部81、第二有源部82、第十四有源部814、第十五有源部815、第十六有源部816。第一有源部81用于形成第一晶体管T1的沟道区，第二有源部82用于形成第二晶体管T2的沟道区。第十五有源部815连接于第一有源部81和第二有源部82之间。第十四有源部814连接于第一有源部81远离第二有源部82的一端，第十六有源部816连接于第二有源部82远离第一有源部81的一端。如图39所示，在第一方向X上相邻的重复单元中，在第一方向X上相邻的有源部8在衬底基板上的正投影在第一方向X上的最小距离为L11；位于同一所述重复单元中且在所述第一方向X上相邻的两所述子重复单元中，在第一方向X上相邻的有源部8在衬底基板上的正投影在第一方向X上的最小距离为L12，L11大于L12。在第二方向Y上相邻的重复单元中，在第二方向Y上相邻的有源部8在衬底基板上的正投影在第二方向Y上的最小距离为L24；位于同一所述重复单元中且在所述第二方向Y上相邻的两所述子重复单元中，在第二方向Y上相邻的有源部8在衬底基板上的正投影在第二方向Y上的最小距离为L23，L24大于L23。其中，第二有源层可以由氧化铟镓锌形成，相应的，第一晶体管T1、第二晶体管T2可以为N型的金属氧化物薄膜晶体管。第三栅线2G2在衬底基板上的正投影可以覆盖第二有源部82在衬底基板上的正投影，第三栅线2G2的部分结构可以用于形成第二晶体管T2的底栅。第三复位信号线2Re1在衬底基板上的正投影可以覆盖第一有源部81在衬底基板上的正投影，第三复位信号线2Re1的部分结构可以用于形成第一晶体管T1的底栅。
如图34、40、48、51、57、65所示，第三栅极层可以包括第一复位信号线3Re1、第二栅线3G2。第一复位信号线3Re1在衬底基板上的正投影、第二栅线3G2在衬底基板上的正投影均可以沿第一方向X延伸。第一复位信号线3Re1可以用于提供图32中的第一复位信号端，第一复位信号线3Re1在衬底基板上的正投影可以覆盖第一有源部81在衬底基板上的正投影，第一复位信号线3Re1的部分结构可以用于形成第一晶体管T1的顶栅，同时，第一复位信号线3Re1可以通过位于显示面板边框区的过孔连接第三复位信号线2Re1。第二栅线3G2可以用于提供图32中的第二栅极 驱动信号端，第二栅线3G2在衬底基板上的正投影可以覆盖第二有源部82在衬底基板上的正投影，第二栅线3G2的部分结构可以用于形成第二晶体管T2的顶栅，同时，第二栅线3G2可以通过位于显示面板边框区的过孔连接第三栅线2G2。如图40所示，在第二方向Y上相邻的重复单元中，相邻第二栅线3G2和第一复位信号线3Re1在衬底基板上的正投影在第二方向Y上的最小距离为L14，位于同一重复单元中且在第二方向Y上相邻的子重复单元中，相邻第二栅线3G2和第一复位信号线3Re1在衬底基板上的正投影在第二方向Y上的最小距离为L13，L14大于L13。此外，该显示面板可以利用第三栅极层为掩膜对第二有源层进行导体化处理，即第二有源层中被第三栅极层覆盖的区域可以形成晶体管的沟道区，第二有源层中未被第三栅极层覆盖的区域形成导体结构。
如图34、41、49、51、58、66所示，第一源漏层可以包括：上述的第一信号线H1、第二初始信号线Vinit2、第一桥接部41、第二桥接部42、第三桥接部43、第四桥接部44、第五桥接部45、第六桥接部46。其中，第一桥接部41分别通过过孔连接连接部23、第九有源部79，以连接第五晶体管的第一极和电容C的第二电极。在第一方向X上相邻子重复单元共用同一第一桥接部41。第二桥接部42可以通过过孔连接第十有源部710，以连接第六晶体管T6的第二极和第七晶体管T7的第二极。第三桥接部43可以分别通过过孔连接第十一有源部711、第十六有源部816，以连接第二晶体管T2的第二极、第六晶体管T6的第一极、驱动晶体管T3的第二极。第四桥接部44可以分别通过过孔连接第十五有源部815、第一导电部11，以连接第二晶体管T2的第一极和驱动晶体管的栅极。第二导电部22上形成有开口221，连接于第一导电部11和第四桥接部44之间的过孔在衬底基板上的正投影位于开口221在衬底基板上的正投影以内，以使该过孔与第二导电部22相互绝缘。第五桥接部45可以通过过孔连接第十二有源部712，以连接第四晶体管的第一极。第六桥接部46可以分别通过过孔连接第十四有源部814、第一初始信号线Vinit1，以连接第一晶体管的第一极和第一初始信号端。其中，同一重复单元中，相邻两像素驱动电路可以共用同一第六桥接部46。第二初始信号线Vinit2可以用于提供图32中的第二初始信号端，第二初始信号线Vinit2在衬底基板上的正投影可 以沿第一方向X延伸，第二初始信号线Vinit2可以通过过孔连接第十三有源部713，以连接第七晶体管的第一极和第二初始信号端。在所述第一方向X上分布的多个所述重复单元形成重复单元行，每个所述重复单元行对应设置一条所述第一信号线H1，所述第一信号线H1在所述衬底基板上的正投影位于所述第一像素驱动电路行Ph1中所述使能信号线EM在所述衬底基板上的正投影和所述第一像素驱动电路行Ph1中所述第二复位信号线Re2在所述衬底基板上的正投影之间。第一信号线H1在衬底基板上的正投影与第一栅极层、第三栅极层在衬底基板上的正投影不交叠，第一信号线H1在衬底基板上的正投影仅与部分第一有源层、位于第二栅极层的第一初始信号线在衬底基板上的正投影交叠，该设置可以减小第一信号线的寄生电容，以及降低第一信号线与其他信号线之间的耦合作用。在第一方向X上相邻重复单元列中，相邻子重复单元共用的第一桥接部41在衬底基板上的正投影在第一方向X上的最大尺寸为L15；位于同一重复单元中，在第一方向X上相邻子重复单元共用的第一桥接部41在衬底基板上的正投影在第一方向X上的最大尺寸为L16，L15大于L16。第一像素驱动电路行Ph1中第一桥接部41在衬底基板上的正投影和第二初始信号线Vinit2在衬底基板上的正投影在第二方向Y的最大距离为L26，第二像素驱动电路行Ph2中第一桥接部41在衬底基板上的正投影和第二初始信号线Vinit2在衬底基板上的正投影在第二方向Y的最大距离为L25，L26大于L25。
如图34、42、50、51、59、67所示，第二源漏层可以包括：上述的第二信号线V2、多条电源线VDD、多条数据线Da、第七桥接部57。其中，在第一方向X上相邻的重复单元之间对应设置一条所述第二信号线V2。电源线VDD在衬底基板上的正投影、数据线Da在衬底基板上的正投影均可以沿第二方向Y延伸。电源线VDD可以用于提供图32中的第一电源端，数据线Da可以用于提供图32中的数据信号端。每列像素驱动电路可以对应设置一条电源线VDD，电源线VDD可以通过过孔连接第一桥接部41，以连接第五晶体管的第一极和第一电源端。数据线Da可以通过过孔连接第五桥接部45，以连接第四晶体管的第一极和数据信号端。第七桥接部57可以通过过孔连接第二桥接部42，以连接第七晶体管的第二极。在同一子 重复单元中，相邻电源线VDD相互连接，从而电源线VDD、第二导电部22可以形成网格结构，该网格结构的电源线可以降低其上电源信号的压降。
如图34、42、50、51、59、67所示，电源线VDD可以包括第一电源线段VDD1、第二电源线段VDD2、第三电源线段VDD3，第二电源线段VDD2连接于第一电源线段VDD1和第三电源线段VDD3之间，第二电源线段VDD2在所述衬底基板上的正投影在第一方向X上的尺寸可以大于第一电源线段VDD1在所述衬底基板上的正投影在第一方向X上的尺寸，且所述第二电源线段VDD2在所述衬底基板上的正投影在第一方向X上的尺寸可以大于所述第三电源线段VDD3在所述衬底基板上的正投影在第一方向X上的尺寸。此外，第二电源线段VDD2在衬底基板上的正投影还可以覆盖第一有源部81在衬底基板上的正投影、第二有源部82在衬底基板上的正投影，第二电源线段VDD2可以降低光照对第一晶体管T1、第二晶体管T2的特性影响。此外，电源线VDD在衬底基板上的正投影还可以与第四桥接部44在衬底基板上的正投影至少部分交叠，电源线VDD可以用于屏蔽其他信号对第四桥接部44的噪音干扰，从而提高驱动晶体管T3栅极电压的稳定性。如图42所示，在所述第一方向X上相邻的所述重复单元列中，相邻两所述数据线Da在所述衬底基板上的正投影在所述第一方向X上的最小距离为L1；在位于同一所述重复单元中且在所述第一方向X上相邻的两所述子重复单元中，相邻两所述数据线Da在所述衬底基板上的正投影在所述第一方向X上的距离为L2，其中，L1大于L2。
如图34、43、51、60所示，像素电极层可以包括多个电极部：第一电极部R、第二电极部B、第三电极部G。同一电极行中，第一电极部R、第三电极部G、第二电极部B、第三电极部G在第一方向X上依次交替分布。多个电极部形成多个电极列，多个电极列包括依次相邻的第一电极列ROW1、第二电极列ROW2、第三电极列ROW3、第四电极列ROW4，第一电极列ROW1包括在第二方向Y上依次交替分布的第一电极部R、第二电极部B；第二电极列ROW2包括多个在第二方向Y上分布的第三电极部G；第三电极列ROW3包括在第二方向Y上依次交替分布的第二电极部B、第一电极部R；第四电极列ROW4包括多个在第二方向Y上分布的第三电极部G。位于同一电极列相邻电极行的两个第三电极部G在所述衬底基板上的正投影在第二 方向Y上的最小距离S5大于所述第一电极部R在所述衬底基板上的正投影在第二方向Y上的尺寸S6，或者大于所述第二电极部B所述衬底基板上的正投影在第二方向Y上的尺寸S7。其中，第一电极部R在衬底基板上的正投影和像素定义层上与其对应的像素开口在衬底基板上的正投影重合，第三电极部G在衬底基板上的正投影和像素定义层上与其对应的像素开口在衬底基板上的正投影重合，第二电极部B在衬底基板上的正投影和像素定义层上与其对应的开口在衬底基板上的正投影重合。在同一重复单元中，相邻电源线VDD中两第二电源线段VDD2相连接。
如图34所示，在所述第一方向上相邻两所述子重复单元中，相邻两所述数据线Da在所述衬底基板上的正投影与同一第三电极部G在所述衬底基板上的正投影相交，且位于所述第二信号线V2在所述衬底基板上的正投影的两侧。该第二信号线V2在所述衬底基板上的正投影和该第三电极部相交。该设置可以提高电极部的平坦度，从而提高显示面板显示的均一性。
需要说明的是，如图34、49、50、51、66、67所示，画于第一源漏层背离衬底基板一侧的黑色方块表示第一源漏层连接面向衬底基板一侧的其他层级的过孔；画于第二源漏层背离衬底基板一侧的黑色方块表示第二源漏层连接面向衬底基板一侧的其他层级的过孔；画于电极层背离衬底基板一侧的黑色方块表示电极层连接面向衬底基板一侧的其他层级的过孔。该黑色方块仅表示过孔的位置，不同位置黑色方块所表示的不同过孔可以贯穿于不同绝缘层。
本示例性实施例中，在所述第一方向上相邻的两所述重复单元列之间对应设置一条所述第二信号线V2，同一重复单元行对应设置一条第一信号线H1。本示例性实施例中，重复单元包括两行两列子重复单元，应该理解的是，在其他示例性实施例中，重复单元还可以包括其他行列数的子重复单元。
如图68所示，为图51所示显示面板沿虚线EE剖开的部分剖视图。该显示面板还可以包括第一绝缘层91、第二绝缘层92、第三绝缘层93、第四绝缘层94、第五绝缘层95、第一介电层96、钝化层97、第一平坦层98、第二平坦层99，其中，衬底基板90、遮挡层、第一绝缘层91、第一 有源层、第二绝缘层92、第一栅极层、第三绝缘层93、第二栅极层、第四绝缘层94、第二有源层、第五绝缘层95、第三栅极层、第一介电层96、第一源漏层、钝化层97、第一平坦层98、第二源漏层、第二平坦层99依次层叠设置。第一绝缘层91、第二绝缘层92、第三绝缘层93、第四绝缘层94、第五绝缘层95可以为单层结构或多层结构，且第一绝缘层91、第二绝缘层92、第三绝缘层93、第四绝缘层94、第五绝缘层95的材料可以为氮化硅，氧化硅，氮氧化硅中的至少一种；第一介电层96可以为氮化硅层；第一平坦层98、第二平坦层99的材料可以为有机材料，例如聚酰亚胺(PI)、聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)、硅-玻璃键合结构(SOG)等材料。钝化层97可以为氧化硅层。衬底基板90可以包括依次层叠设置的玻璃基板、阻挡层、聚酰亚胺层，阻挡层可以为无机材料。第一栅极层、第二栅极层、第三栅极层的材料可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等导电层。第一源漏层、第二源漏层的材料可以包括金属材料，例如可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层等导电层。第一源漏层、第二源漏层中任意一层的方块电阻可以小于第一栅极层、第二栅极层、第三栅极层中任意一层的方块电阻。从而，本示例性实施例中，第一数据扇出线和第二数据扇出线具有较小的电阻。
需要说明的是，本公开中的附图比例可以作为实际工艺中的参考，但不限于此，例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图。此外，第一、第二等限定词仅用于限定不同的结构名称，其并没有特定顺序的含义，同一结构层可以通过同一构图工艺形成。在本示例性实施例中，某一结构在衬底基板上的正投影沿某一方向延伸，可以理解为，该结构在衬底基板上的正投影沿该方向直线延伸或弯折延伸。
本示例性实施例中，显示面板可以为柔性显示面板也可以为非柔性显示面板。
本示例性实施例还提供一种显示装置，其中，包括上述的显示面板。该显示装置可以为手机、平板电脑、电视等显示装置。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (33)

  1. 一种显示面板，其中，所述显示面板包括显示区、位于所述显示区的扇出区，所述显示面板还包括：
    衬底基板；
    多条数据线，位于所述显示区，所述数据线在所述衬底基板上的正投影沿第一方向间隔分布且沿第二方向延伸，所述第一方向和所述第二方向相交；
    多条第一数据扇出线，位于所述扇出区，所述第一数据扇出线在所述衬底基板上的正投影沿所述第二方向间隔分布且沿所述第一方向延伸，所述第一数据扇出线与所述数据线对应设置，所述第一数据扇出线连接与其对应的所述数据线；
    多条第二数据扇出线，位于所述扇出区，所述第二数据扇出线在所述衬底基板上的正投影沿所述第一方向间隔分布且沿所述第二方向延伸，所述第二数据扇出线与所述第一数据扇出线对应设置，所述第二数据扇出线连接与其对应的所述第一数据扇出线。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    多条第一信号线，位于所述显示区，所述第一信号线在所述衬底基板上的正投影沿所述第一方向延伸且沿所述第二方向间隔分布，多条所述第一信号线中包括第一子信号线，所述第一子信号线的至少部分结构用于形成所述第一数据扇出线；
    多条第二信号线，位于所述显示区，且与所述第一信号线位于不同导电层，所述第二信号线在所述衬底基板上的正投影沿所述第二方向延伸且沿所述第一方向间隔分布，多条所述第二信号线中包括第二子信号线，所述第二子信号线的至少部分结构用于形成所述第二数据扇出线。
  3. 根据权利要求2所述的显示面板，其中，相邻两所述第一信号线在所述衬底基板上的正投影在所述第二方向上的最小距离为S1，相邻两所述第一信号线在所述衬底基板上的正投影在所述第二方向上的最大距离为S2，其中，(S2-S1)/S1大于等于0且小于等于0.2；
    和/或，相邻两所述第二信号线在所述衬底基板上的正投影在所述第一方向上的最小距离为S3，相邻两所述第二信号线在所述衬底基板上的正 投影在所述第一方向上的最大距离为S4，其中，(S4-S3)/S3大于等于0且小于等于0.2。
  4. 根据权利要求2所述的显示面板，其中，所述第一子信号线还包括与所述第一数据扇出线间隔设置的第一模拟线，所述第二子信号线还包括与所述第二数据扇出线间隔设置的第二模拟线；
    所述扇出区包括第一扇出区和第二扇出区，所述第一数据扇出线位于所述第一扇出区，所述第二数据扇出线位于所述第二扇出区；
    多条所述第一信号线中还包括第三模拟线，所述第三模拟线位于所述第一扇出区以外的显示区；
    多条所述第二信号线中还包括第四模拟线，所述第四模拟线位于所述第二扇出区以外的显示区。
  5. 根据权利要求4所述的显示面板，其中，所述显示面板还包括像素驱动电路和发光单元，所述像素驱动电路连接所述发光单元的第一电极；
    所述显示面板还包括：
    公共电极层，所述公共电极层用于形成所述发光单元的第二电极；
    其中，所述第一模拟线、所述第二模拟线、所述第三模拟线、所述第四模拟线连接所述公共电极层。
  6. 根据权利要求4所述的显示面板，其中，所述第一模拟线通过过孔连接与其在所述衬底基板上的正投影相交的第四模拟线；
    所述第三模拟线通过过孔连接与其在所述衬底基板上的正投影相交的所述第二模拟线、第四模拟线。
  7. 根据权利要求5所述的显示面板，其中，所述显示面板还包括位于所述显示区周围的边框区，所述边框区包括相对设置的第一边框区和第二边框区，所述扇出区位于靠近所述第二边框区的一侧；
    所述显示面板还包括：
    电极环，所述电极环位于所述边框区，且连接所述公共电极层，所述电极环位于所述第一边框区的至少部分结构连接所述第二模拟线和所述第四模拟线；
    电源电路，绑定于所述第二边框区，所述电源电路连接所述电极环位于所述第二边框区的至少部分结构，所述电源电路用于向所述电极环提供 电源信号。
  8. 根据权利要求4所述的显示面板，其中，所述第一扇出区包括第一子扇出区和第二子扇出区，所述第一子扇出区和第二子扇出区位于所述第二扇出区在所述第一方向上两侧；
    多条所述第二信号线中还包括至少一条第五模拟线，所述第五模拟线的部分结构位于所述第二扇出区，且所述第五模拟线分别通过过孔连接与其在所述衬底基板上正投影相交的所述第一模拟线和第三模拟线。
  9. 根据权利要求2所述的显示面板，其中，多条所述第一信号线位于同一导电层，多条所述第二信号线位于同一导电层；
    所述第二信号线所在导电层位于所述第一信号线所在导电层背离所述衬底基板的一侧。
  10. 根据权利要求9所述的显示面板，其中，所述显示面板还包括：
    第一源漏层，位于所述衬底基板的一侧，所述第一源漏层包括所述第一信号线；
    第二源漏层，位于所述第一源漏层背离所述衬底基板的一侧，所述第二源漏层包括所述第二信号线和所述数据线；
    所述第二信号线在所述衬底基板上的正投影位于相邻两所述数据线在所述衬底基板上的正投影之间。
  11. 根据权利要求2所述的显示面板，其中，所述第一信号线包括多个第一过孔接触部和第一延伸部，多个所述第一过孔接触部在所述衬底基板上的正投影沿所述第一方向间隔分布，所述第一延伸部连接于所述第一过孔接触部，所述第一过孔接触部在所述衬底基板上的正投影在所述第二方向上的尺寸大于所述第一延伸部在所述衬底基板上的正投影在所述第二方向上的尺寸；
    所述第二信号线包括多个第二过孔接触部和第二延伸部，多个所述第二过孔接触部在所述衬底基板上的正投影沿所述第二方向间隔分布，所述第二延伸部连接于所述第二过孔接触部，所述第二过孔接触部在所述衬底基板上的正投影在所述第一方向上的尺寸大于所述第二延伸部在所述衬底基板上的正投影在所述第一方向上的尺寸；
    其中，所述第一过孔接触部和所述第二过孔接触部对应设置，所述第 一过孔接触部在所述衬底基板上的正投影和与其对应的所述第二过孔接触部在所述衬底基板上的正投影至少部分交叠，至少部分所述第一过孔接触部通过过孔连接与其对应的所述第二过孔接触部。
  12. 根据权利要求11所述的显示面板，其中，相邻所述第一过孔接触部在所述衬底基板上的正投影在所述第一方向上的最小距离为S5，相邻所述第一过孔接触部在所述衬底基板上的正投影在所述第一方向上的最大距离为S6，其中，(S6-S5)/S5大于等于0且小于等于0.2；
    和/或，相邻所述第二过孔接触部在所述衬底基板上的正投影在所述第二方向上的最小距离为S7，相邻所述第二过孔接触部在所述衬底基板上的正投影在所述第二方向上的最大距离为S8，其中，(S8-S7)/S7大于等于0且小于等于0.2。
  13. 根据权利要求11所述的显示面板，其中，多个所述第一过孔接触部中包括第一实孔接触部，多个所述第二过孔接触部中包括第二实孔接触部和第二虚孔接触部；
    所述第一实孔接触部和与其对应的所述第二实孔接触部通过过孔连接，所述第二虚孔接触部和与其在所述衬底基板上的正投影相交的所述第一信号线绝缘设置。
  14. 根据权利要求13所述的显示面板，其中，多个所述第一过孔接触部中还包括第一虚孔接触部，所述第一虚孔接触部和与其对应的所述第二虚孔接触部绝缘设置。
  15. 根据权利要求10所述的显示面板，其中，所述显示面板包括：
    第一平坦层，位于所述第一源漏层和所述第二源漏层之间，所述第一平坦层的厚度小于等于1.6um。
  16. 根据权利要求13所述的显示面板，其中，所述显示面板还包括：
    钝化层，位于所述第一信号线所在导电层和所述第二信号线所在导电层之间；
    第一平坦层，位于所述钝化层和所述所述第二信号线所在导电层之间；
    其中，所述第一平坦层上形成有第一开孔，所述第一开孔在所述衬底基板上的正投影与所述第二虚孔接触部在所述衬底基板上的正投影至少部分交叠。
  17. 根据权利要求13所述的显示面板，其中，所述显示面板还包括：
    钝化层，位于所述第一信号线所在导电层和所述第二信号线所在导电层之间；
    第一平坦层，位于所述钝化层和所述所述第二信号线所在导电层之间；
    其中，所述钝化层上形成有第二开孔，所述第二开孔在所述衬底基板上的正投影与所述第二虚孔接触部在所述衬底基板上的正投影至少部分交叠。
  18. 根据权利要求4所述的显示面板，其中，所述第一数据扇出线和所述第一模拟线之间断口在所述衬底基板上的正投影在所述第一方向上的尺寸为1.5um-3.5um；
    和/或，所述第二数据扇出线和所述第二模拟线之间断口在所述衬底基板上的正投影在所述第二方向上的尺寸为1.5um-3.5um。
  19. 根据权利要求11所述的显示面板，其中，在所述衬底基板上的正投影位于所述第二信号线相邻两侧的所述数据线包括第三延伸部、第四延伸部、第五延伸部，所述第四延伸部连接于所述第三延伸部和所述第五延伸部之间；
    所述第二过孔接触部和所述第四延伸部的至少部分结构在所述第一方向上相对设置，且所述第四延伸部在所述衬底基板上的正投影和所述第二延伸部在所述衬底基板上的正投影在所述第一方向上的尺寸大于所述第三延伸部在所述衬底基板上的正投影和所述第二延伸部在所述衬底基板上的正投影在所述第一方向上的尺寸，所述第四延伸部在所述衬底基板上的正投影和所述第二延伸部在所述衬底基板上的正投影在所述第一方向上的尺寸大于所述第五延伸部在所述衬底基板上的正投影和所述第二延伸部在所述衬底基板上的正投影在所述第一方向上的尺寸。
  20. 根据权利要求4所述的显示面板，其中，所述显示面板还包括像素驱动电路和发光单元，所述像素驱动电路连接所述发光单元的第一电极，所述显示面板还包括：
    电极层，位于所述衬底基板的一侧，所述电极层包括多个电极部，所述电极部用于形成所述发光单元的第一电极；
    所述第一数据扇出线和所述第一模拟线之间的断口在所述衬底基板 上的正投影与所述电极部在所述衬底基板上的正投影不交叠；
    和/或，所述第二数据扇出线和所述第二模拟线之间的断口在所述衬底基板上的正投影与所述电极部在所述衬底基板上的正投影不交叠。
  21. 根据权利要求11所述的显示面板，其中，所述显示面板还包括像素驱动电路和发光单元，所述像素驱动电路连接所述发光单元的第一电极，所述显示面板还包括：
    电极层，位于所述衬底基板的一侧，所述电极层包括多个电极部，所述电极部用于形成所述发光单元的第一电极；
    所述第一过孔接触部在所述衬底基板上的正投影和所述电极部在所述衬底基板上的正投影不交叠；
    所述第二过孔接触部在所述衬底基板上的正投影和所述电极部在所述衬底基板上的正投影不交叠。
  22. 根据权利要求2所述的显示面板，其中，所述显示面板还包括多个像素驱动电路和多个发光单元，多个所述像素驱动电路沿所述第一方向和所述第二方向阵列分布的，所述像素驱动电路连接所述发光单元的第一电极；
    所述像素驱动电路包括驱动晶体管、第六晶体管、第七晶体管，所述第六晶体管的第一极连接所述驱动晶体管的第二极，所述第六晶体管的第二极连接所述发光单元的第一电极，所述第七晶体管的第一极连接第二初始信号线，所述第七晶体管的第二极连接所述发光单元的第一电极；
    所述显示面板还包括：
    第一有源层，位于所述衬底基板的一侧，所述第一有源层包括第六有源部和第七有源部，所述第六有源部用于形成所述第六晶体管的沟道区，所述第七有源部用于形成所述第七晶体管的沟道区；
    第一栅极层，位于所述第一有源层背离所述衬底基板的一侧，所述第一栅极层包括使能信号线和第二复位信号线，所述使能信号线在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第六有源部在所述衬底基板上的正投影，所述第二复位信号线在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第七有源部在所述衬底基板上的正投影；
    其中，所述第一方向为行方向，所述第一信号线在所述衬底基板上的 正投影位于同一行像素驱动电路中所述使能信号线在所述衬底基板上的正投影和所述第二复位信号线在所述衬底基板上的正投影之间。
  23. 根据权利要求11所述的显示面板，其中，所述显示面板还包括多个像素驱动电路和多个发光单元，多个所述像素驱动电路沿所述第一方向和所述第二方向阵列分布的，所述像素驱动电路连接所述发光单元的第一电极；
    所述像素驱动电路包括驱动晶体管、第六晶体管、第一晶体管，所述第六晶体管的第一极连接所述驱动晶体管的第二极，所述第六晶体管的第二极连接所述发光单元的第一电极，所述第一晶体管的第一极连接第一初始信号线，所述第一晶体管的第二极连接所述驱动晶体管的栅极；
    所述显示面板还包括：
    第一栅极层，位于所述衬底基板的一侧，所述第一栅极层包括使能信号线，所述使能信号线的部分结构用于形成所述第六晶体管的栅极；
    第二栅极层，位于所述第一栅极层背离所述衬底基板的一侧，所述第二栅极层包括所述第一初始信号线；
    所述第一信号线中的第一延伸部在所述衬底基板上的正投影位于本行像素驱动电路中所述第一初始信号线在所述衬底基板上的正投影和相邻下一行像素驱动电路中所述使能信号线在所述衬底基板上的正投影之间。
  24. 根据权利要求2所述的显示面板，其中，所述显示面板包括多个在所述第一方向和所述第二方向上阵列分布的重复单元，所述重复单元包括n行m列子重复单元，n、m为大于等于1的正整数；
    所述子重复单元包括在所述第一方向上相邻分布的两个像素驱动电路，同一所述子重复单元中两像素驱动电路镜像对称设置；
    在所述第二方向上分布的多个所述重复单元形成重复单元列，在所述第一方向上相邻的两所述重复单元列之间对应设置一条所述第二信号线；
    在所述第一方向上分布的多个所述重复单元形成重复单元行，每个所述重复单元行对应设置一条所述第一信号线。
  25. 根据权利要求24所述的显示面板，其中，
    所述显示面板还包括发光单元，所述像素驱动电路连接所述发光单元 的第一电极，所述显示面板还包括：
    电极层，包括多个电极部，所述电极部用于形成所述发光单元的第一电极；
    其中，在所述第一方向上相邻两所述子重复单元中，相邻两所述数据线在所述衬底基板上的正投影与同一所述电极部在所述衬底基板上的正投影相交，且位于所述第二信号线在所述衬底基板上的正投影的两侧。
  26. 根据权利要求25所述的显示面板，其中，m为大于等于2的正整数；
    在所述第一方向上相邻的所述重复单元列中，相邻两所述数据线在所述衬底基板上的正投影在所述第一方向上的最小距离为L1；
    在位于同一所述重复单元中且在所述第一方向上相邻的两所述子重复单元中，相邻两所述数据线在所述衬底基板上的正投影在所述第一方向上的最小距离为L2；
    其中，L1大于L2。
  27. 根据权利要求24所述的显示面板，其中，n为大于等于2的正整数；
    所述显示面板还包括发光单元，所述像素驱动电路包括驱动晶体管、第六晶体管、第七晶体管，所述第六晶体管的第一极连接所述驱动晶体管的第二极，所述第六晶体管的第二极连接所述发光单元的第一电极，所述第六晶体管的栅极连接使能信号线，所述第七晶体管的第一极连接第二初始信号线，所述第七晶体管的第二极连接所述发光单元的第一电极，所述第七晶体管的栅极连接第二复位信号线；
    同一所述重复单元行包括第一像素驱动电路行和第二像素驱动电路行，所述第一像素驱动电路行包括沿所述第一方向分布的多个像素驱动电路，所述第二像素驱动电路行包括沿所述第一方向分布的多个像素驱动电路；
    所述第一信号线在所述衬底基板上的正投影位于所述第一像素驱动电路行中所述使能信号线在所述衬底基板上的正投影和所述第一像素驱动电路行中所述第二复位信号线在所述衬底基板上的正投影之间；
    在所述第一像素驱动电路行中，所述使能信号线在所述衬底基板上的 正投影和所述第二复位信号线在所述衬底基板上的正投影在所述第二方向上的最小距离为L3；
    在所述第二像素驱动电路行中，所述使能信号线在所述衬底基板上的正投影和所述第二复位信号线在所述衬底基板上的正投影在所述第二方向上的最小距离为L4；
    其中，L3大于L4。
  28. 根据权利要求1所述的显示面板，其中，所述显示面板包括像素驱动电路和发光单元，所述像素驱动电路包括驱动晶体管、第一晶体管、第二晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、电容；
    所述第一晶体管的第一极连接第一初始信号线，第二极连接所述驱动晶体管的栅极；
    所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极；
    所述第四晶体管的第一极连接所述数据线，第二极连接所述驱动晶体管的第一极；
    所述第五晶体管的第一极连接电源线，第二极连接所述驱动晶体管的第一极；
    所述第六晶体管的第一极连接所述驱动晶体管的第二极，第二极连接所述发光单元的第一电极；
    所述第七晶体管的第一极连接第二初始信号线，第二极连接所述发光单元的第一电极；
    所述电容的第一电极连接所述驱动晶体管的栅极，第二电极连接所述电源线。
  29. 根据权利要求28所述的显示面板，其中，所述显示面板还包括：
    第一有源层，位于所述衬底基的一侧，所述第一有源层包括第三有源部、第四有源部、第五有源部、第六有源部、第七有源部，所述第三有源部用于形成所述驱动晶体管的沟道区，所述第四有源部用于形成所述第四晶体管的沟道区，所述第五有源部用于形成所述第五晶体管的沟道区，所述第六有源部用于形成所述第六晶体管的沟道区，所述第七有源部用于形成所述第七晶体管的沟道区；
    第一栅极层，位于所述第一有源层背离所述衬底基板的一侧，所述第一栅极层包括第一栅线、使能信号线、第二复位信号线、第一导电部，所述第一栅线在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第四有源部在所述衬底基板上的正投影，所述使能信号线在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第五有源部在所述衬底基板上的正投影、所述第六有源部在所述衬底基板上的正投影，所述第二复位信号线在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第七有源部在所述衬底基板上的正投影，所述第一导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影；
    第二有源层，位于所述第一栅极层背离所述衬底基板的一侧，所述第二有源层包括第一有源部、第二有源部，所述第一有源部用于形成所述第一晶体管的沟道区，所述第二有源部用于形成所述第二晶体管的沟道区；
    第三栅极层，位于所述第二有源层背离所述衬底基板的一侧，所述第三栅极层包括第二栅线、第一复位信号线，所述第二栅线在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第二有源部在所述衬底基板上的正投影，所述第一复位信号线在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第一有源部在所述衬底基板上的正投影；
    其中，所述第二复位信号线在所述衬底基板上的正投影、使能信号线在所述衬底基板上的正投影、所述第一导电部在所述衬底基板上的正投影、第二栅线在所述衬底基板上的正投影、第一栅线在所述衬底基板上的正投影、所述第一复位信号线在所述衬底基板上的正投影沿所述第二方向依次分布。
  30. 根据权利要求29所述的显示面板，其中，所述第一方向为行方向，所述第二方向为列方向，本行像素驱动电路中所述第一栅线复用为相邻下一行像素驱动电路中的第二复位信号线。
  31. 根据权利要求28所述的显示面板，其中，所述驱动晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管为P型晶体管，所述第一晶体管、第二晶体管为N型晶体管。
  32. 根据权利要求4所述的显示面板，其中，所述第二信号线包括多个第二过孔接触部，多个所述第二过孔接触部在所述衬底基板上的正投影 沿所述第二方向间隔分布；
    同一所述第二信号线中，在所述第二方向上相邻两所述第二过孔接触部在所述衬底基板上的正投影在所述第二方向上的距离为A1，所述第二数据扇出线和所述第二模拟线之间断口在所述衬底基板上的正投影在所述第二方向上的尺寸为A2；
    A1/A2大于等于27且小于等于68。
  33. 一种显示装置，其中，所述显示装置包括权利要求1-32任一项所述的显示面板。
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