WO2024044983A1 - 触控显示面板及显示装置 - Google Patents

触控显示面板及显示装置 Download PDF

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Publication number
WO2024044983A1
WO2024044983A1 PCT/CN2022/115927 CN2022115927W WO2024044983A1 WO 2024044983 A1 WO2024044983 A1 WO 2024044983A1 CN 2022115927 W CN2022115927 W CN 2022115927W WO 2024044983 A1 WO2024044983 A1 WO 2024044983A1
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WO
WIPO (PCT)
Prior art keywords
touch
pin
display
lead
pins
Prior art date
Application number
PCT/CN2022/115927
Other languages
English (en)
French (fr)
Inventor
屈忆
初志文
王欣欣
周洋
白露
代俊秀
冯翱远
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280002962.3A priority Critical patent/CN117957514A/zh
Priority to PCT/CN2022/115927 priority patent/WO2024044983A1/zh
Publication of WO2024044983A1 publication Critical patent/WO2024044983A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means

Definitions

  • the present disclosure relates to the field of touch technology, and specifically to a touch display panel and a display device.
  • Touch display panels are an important part of terminal equipment such as mobile phones and smart watches. While displaying images, they can also realize human-computer interaction through touch operations. However, the touch power consumption of existing touch display panels is still high.
  • the present disclosure provides a touch display panel and a display device.
  • a touch display panel has a display area, a peripheral area and a lead-out area.
  • the peripheral area is located outside the display area.
  • the lead-out area is arranged along the column direction. Outside the peripheral area, the lead-out area has a binding portion for connecting to the flexible circuit board;
  • the touch display panel includes:
  • a driver chip having at least one touch pin group and a plurality of strobe circuits.
  • the touch pin group includes a plurality of first touch pins.
  • a first touch pin of the touch pin group It includes a plurality of functional pins and at least one dummy pin; the touch layer is connected to each of the functional pins through a plurality of touch leads, and one of the functional pins is connected to at least one of the touch leads;
  • the driver chip also has a second touch pin connected to the binding part;
  • the second touch pins are connected to each of the first touch pins through the strobe circuit; at least one of the first touch pins connected to the strobe circuit is the dummy pin. ;
  • the strobe circuit connected to the functional pin is used to turn on the second touch pin and each of the functional pins connected to it in sequence; the strobe circuit connected to the dummy pin is turned off.
  • a first touch pin of a touch pin group includes a plurality of pin units, and each of the pin units includes a plurality of the functional pins and At least one of the dummy pins;
  • the strobe circuit includes a first strobe circuit and a second strobe circuit;
  • One of the strobe circuits is connected to the first touch pins in a plurality of the pin units at the same time, and one of the functional pins in each of the pin units is connected to one of the first strobe circuits. Connection, at least two of the functional pins in the same pin unit are connected to different first strobe circuits; one of the dummy pins in one of the pin units and one of the second strobe circuits Circuit connection.
  • the first touch pins in the same touch pin group are spaced apart along the column direction, and any of the pin units is in the column direction.
  • the last first touch pin is the dummy pin.
  • the first touch pins in the same touch pin group are arranged in multiple columns distributed along the row direction, and the first touch pins in two adjacent columns are The pins are distributed alternately in the column direction; the dummy pins are located in the same column.
  • the number of the touch pin groups is two, and they are located at both ends of the driver chip in the row direction.
  • a first touch pin of a touch pin group includes a plurality of pin units, at least some of the pin units include only the functional pins, At least some of the pin units include only the dummy pins; a first touch pin in one of the pin units is connected to the same strobe circuit.
  • the lead-out area further includes a bending area extending along the row direction, and the binding portion is located on a side of the bending area away from the display area;
  • the driver chip is located in the lead-out area and between the bending area and the binding part.
  • the driver chip includes two touch terminals distributed along the row direction and a first pin terminal and a second pin terminal distributed along the column direction; the touch terminal The control pin group is located on the touch end; the second pin end is located on a side of the first pin end close to the binding part, and the second touch pin is located on the second pin end. foot end;
  • the first pin terminal has a plurality of display pins; one of the touch leads is connected to one of the functional pins through a connecting wire; the driver chip at least partially overlaps with the connecting wire;
  • the touch display panel also includes:
  • a plurality of light-emitting devices located in the display area
  • a driving backplane is used to drive the light-emitting device to emit light, and includes a pixel circuit, a peripheral circuit and peripheral leads.
  • the pixel circuit is located in the display area
  • the peripheral circuit is located in the peripheral area
  • the peripheral leads are formed by the The peripheral area extends to the lead-out area, is connected to the peripheral circuit, and is connected to the driver chip through part of the display pins; the peripheral leads and the touch leads are located on different layers;
  • the touch layer is provided on a side of the light-emitting device away from the driving backplane.
  • the portion of the touch lead in the lead-out area includes two touch lead-out sections, two touch transition sections and one touch connection distributed along the column direction. section; the touch lead-out section is connected to the part of the touch lead located in the peripheral area, the touch connection section is connected to the functional pin through the connecting wire, and a touch lead-out section is connected through a The touch transition section is connected to the touch connection section, and the touch connection section is located between the two touch lead-out sections; both the touch lead-out section and the touch connection section are along the Extending in the column direction, the extension direction of the touch transition section is different from the row direction and the column direction;
  • the portion of the peripheral leads in the lead-out area is divided into two peripheral line groups distributed along the row direction;
  • the peripheral line group includes a display lead-out section, a display transition section and a first display extension section distributed along the column direction, and the display transition section is connected between the display lead-out section and the first display extension section;
  • the display lead-out section is connected to the part of the peripheral lead located in the peripheral area, and the first display extension section is connected to part of the display pin; both the display lead-out section and the first display extension section are along the column.
  • the extension direction of the display transition section is different from the row direction and column direction;
  • the two display lead-out sections are located between the two touch lead-out sections, the touch transition section and the display transition section intersect in one-to-one correspondence, and the two display lead-out sections are located between the two touch lead-out sections.
  • the touch connection section is located between the two first display extension sections.
  • the touch display panel further includes:
  • a first power bus is provided in the peripheral area, extends to the lead-out area, and is connected to the binding part for transmitting a first power signal;
  • the first power bus, the touch lead and The peripheral leads are located on different layers, and the touch leads are located on a side of the first power bus away from the peripheral leads;
  • a plurality of power lines extend along the column direction, extend from the display area to the peripheral area, and are connected to the first power bus; one column of the power lines is connected to at least one column of the pixel circuits;
  • the portion of the first power bus located in the lead-out area includes a shielding portion and a connecting portion.
  • the shielding portion is connected to the portion of the first power bus located in the peripheral area.
  • the connecting portion connects the shielding portion and the connecting portion.
  • the touch display panel further includes:
  • Data lines extend along the column direction, extend from the display area to the lead-out area, and are connected to part of the display pins.
  • One column of the data lines is connected to at least one column of the pixel circuits for transmission. data signal;
  • the part of the data line located in the lead-out area includes two data line groups distributed along the row direction, the touch lead-out section, the touch transition section, the touch connection section, the display lead-out section and the display transition section and
  • the display connection segments are all located between the two data line groups; the data line group, the first power bus and the touch lead are all located on different layers, and the touch lead is located on the first power bus
  • the data line group at least partially overlaps the shielding portion.
  • the peripheral line group further includes a second display extension section and a display connection section, the second display extension section extends along the row direction and is connected with the first display extension section.
  • the extension section is connected to one end away from the display area and extends in a direction away from the touch connection section along the row direction; the second display extension section intersects the data line group and is located on a different layer;
  • the connection section extends along the column direction, is located outside the two data line groups, and is connected to some of the display pins.
  • the display pins are divided into two display pin groups along the row direction, and the first pin end has a terminal located between the two display pin groups.
  • a dummy touch pin is provided, and the touch connection section is connected to one of the dummy touch pins.
  • the display pins of the two display pin groups each include a first display pin and a second display pin, and the peripheral leads pass through the first display pin.
  • the data line is connected to the driver chip through the second display pin;
  • the first display pin is located on a side of the second display pin away from the dummy touch pin along the row direction.
  • the driving backplane includes:
  • a first semiconductor layer is provided on one side of the substrate; the material of the first semiconductor layer is polysilicon;
  • a first gate layer is provided on a surface of the first gate insulating layer away from the substrate, and overlaps with at least a partial area of the first semiconductor layer;
  • a second gate layer is provided on the surface of the first insulating layer away from the substrate;
  • a second semiconductor layer is provided on the surface of the second insulating layer away from the substrate; the material of the second semiconductor layer is metal oxide;
  • a third gate layer is provided on a surface of the second gate insulating layer away from the substrate, and overlaps with at least part of the second semiconductor layer;
  • a first source and drain layer is provided on the surface of the third insulating layer away from the substrate;
  • a first flat layer is provided on the side of the first source and drain layer away from the substrate;
  • a second source and drain layer is provided on the surface of the first flat layer away from the substrate;
  • the light-emitting device is disposed on a side of the second flat layer away from the substrate.
  • the touch layer includes a plurality of touch electrodes distributed in an array, and one of the touch electrodes is connected to one of the touch leads.
  • the driver chip also has a first test pin; the binding part has a plurality of second test pins; and the touch display panel further includes a plurality of test lines. ;
  • connection traces is connected to one of the second test pins through one of the test lines; one of the first test pins is connected to one of the second test pins through one of the test lines.
  • a display device includes the touch display panel described in any one of the above.
  • FIG. 1 is a top view of a touch display panel according to an embodiment of the present disclosure.
  • FIG. 2 is a partial cross-sectional schematic diagram of an embodiment of the touch display panel of the present disclosure.
  • FIG. 3 is a partial top view of the touch layer in an embodiment of the touch display panel of the present disclosure.
  • FIG. 4 is a schematic diagram of a pixel circuit in an embodiment of the touch display panel of the present disclosure.
  • FIG. 5 is a partial top view of the lead-out area of the touch display panel according to an embodiment of the present disclosure.
  • FIG. 6 is a partial enlarged view of the lead-out area of the touch display panel according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of the first touch pin and the strobe circuit in an embodiment of the touch display panel of the present disclosure.
  • FIG. 8 is a schematic diagram of the touch leads, peripheral leads and data lines in the lead-out area in FIG. 6 .
  • FIG. 9 is a schematic diagram of the touch lead in the lead-out area in FIG. 6 .
  • FIG. 10 is a schematic diagram of the peripheral leads in the lead-out area in FIG. 6 .
  • FIG. 11 is a partial top view of the touch display panel in an embodiment of the present disclosure when no driver chip is provided in the lead-out area.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • the row direction and the column direction Y in this article are only two mutually perpendicular directions.
  • the row direction may be horizontal and the column direction Y may be vertical. However, it is not limited to this. If the touch display panel If rotation occurs, the actual orientation of the row and column directions Y may change.
  • overlap of feature A and feature B in this article means that the orthographic projection of feature A on the substrate and the orthographic projection of feature B on the substrate at least partially overlap.
  • the touch display panel has a display area AA, a peripheral area WA and a lead-out area FA, wherein: the peripheral area WA is located outside the display area AA, and the peripheral area WA can be a continuous or discontinuous annular area surrounding the display area AA, or it can also be a semi-enclosed area, and the shape of the peripheral area WA is not particularly limited here.
  • the lead-out area FA is located outside the peripheral area WA and extends in a direction away from the display area AA along the column direction Y.
  • the lead-out area FA has a binding part PA.
  • the binding part PA can have multiple pins.
  • At least some of the pins of the binding part PA can be connected to a flexible circuit board, and the flexible circuit board can be bound to a control circuit board. , thereby realizing the connection between the touch display panel and the control circuit board, and controlling the touch display panel to display images and implement touch functions through the control circuit board.
  • the lead-out area FA may include a bending area BA distributed along the column direction Y.
  • the bending area BA is a bendable flexible structure, and the binding part PA is located in the bending area BA away from the display area AA. side.
  • the lead-out area FA can be bent to the backlight side of the touch display panel, that is, the side opposite to the light emitting direction.
  • the flexible circuit board can be connected to the control circuit board on the backlight side of the touch display panel.
  • the lead-out area FA may not be provided with the bending area BA, but the flexible circuit board may be bent to connect the flexible circuit board and the control circuit board on the backlight side of the touch display panel. .
  • the touch display panel may include a touch layer TSP and a driver chip TIC, where:
  • the touch layer TSP is used to sense touch operations so that the touch display panel displays specified images to achieve human-computer interaction.
  • the driver chip TIC has at least one touch pin group PG and a plurality of strobe circuits Mux.
  • the touch pin group PG includes a plurality of first touch pins P1.
  • the first touch pin of one touch pin group PG Pin P1 includes multiple functional pins P1a and at least one dummy pin P1d; the touch layer TSP is connected to the functional pin P1a through multiple touch leads TL1, thereby connecting to the driver chip TIC; one functional pin P1a is connected to at least one The touch lead TL1 is connected; the driver chip TIC may also have a second touch pin P2, and the second touch pin P2 may be connected to the binding part PA.
  • the second touch pin P2 is connected to each first touch pin P1 through the strobe circuit Mux, and the first touch pins P1 connected to at least one strobe circuit Mux are all dummy pins P1d;
  • the strobe circuit Mux connected to the functional pin P1a is used to turn on the second touch pin P2 and each connected functional pin P1a in sequence; the strobe circuit Mux connected to the dummy pin P1d is turned off.
  • the touch display panel in the embodiment of the present disclosure can transmit the touch for driving the touch layer TSP to sense the touch operation through the function pin P1a in the first touch pin P1 to the touch layer TSP in the display area AA.
  • Driving signal in which the first touch pin P1 and the second touch pin P2 are selectively turned on through the strobe circuit Mux, and the touch drive signal can be transmitted. Therefore, through the control of each strobe circuit Mux To control, the touch drive signal can be transmitted to each touch lead TL1 through the function pin P1a in each first touch pin P1, so as to realize the scanning of the touch layer TSP so as to sense the touch operation.
  • the strobe circuit Mux connected to the functional pin P1a is in an open state, which can time-share the conduction of the second touch pin P2 and its connected functional pin P1a to obtain different transmission paths, and the dummy pin
  • the strobe circuit Mux connected to pin P1d can be set to a closed state to reduce energy consumption.
  • the touch display panel may at least include a driving backplane BP, a light-emitting device LD and a touch layer TSP.
  • the driving backplane BP is used to drive the light-emitting device LD to emit light.
  • the light-emitting device LD may include a light-emitting device LD located along an edge away from the driving backplane BP.
  • the first electrode ANO, the luminescent layer EL and the second electrode CAT are stacked in the direction, where:
  • the driving backplane BP may include a driving circuit for driving each light-emitting device LD to emit light independently.
  • the driving circuit may include a pixel circuit and a peripheral circuit, where the number of pixel circuits is multiple, and at least part of the pixel circuits may be provided in the display area AA. Within, of course, there may be a partial area of a part of the pixel circuit located in the peripheral area WA.
  • the pixel circuit can include multiple transistors and can also include capacitors, which can be 3T1C, 7T1C and other pixel circuits.
  • nTmC means that a pixel circuit includes n transistors (indicated by the letter "T”) and m capacitors (indicated by the letter "C" express).
  • the pixel circuit array is distributed in multiple rows and columns.
  • One pixel circuit can be connected to one light-emitting device LD.
  • one pixel circuit is connected to multiple light-emitting devices LD.
  • This article only uses a one-to-one correspondence between the pixel circuit and the light-emitting device LD. The connection is explained as an example.
  • the pixel circuit may be a 7T1C structure, which may have 7 transistors and 1 capacitor, namely a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a write transistor The transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, the second reset transistor T7 and the storage capacitor Cst.
  • the driving backplane BP may also include gate lines, reset signal lines, data lines, power lines, etc., wherein the number of gate lines and reset signal lines is multiple, and they are all along the rows.
  • the direction X passes through the display area AA and extends into the peripheral area WA, and a pixel circuit connects multiple gate lines and multiple reset signal lines.
  • Gate lines connected to the same pixel circuit may include first reset control lines, second reset control lines, scanning lines and light emitting control lines, and reset signal lines connected to the same pixel circuit may include first reset signal lines and second reset signals. Wire.
  • Both the data lines and the power lines pass through the display area AA along the column direction Y and extend into the peripheral area WA.
  • a column of pixel circuits is connected to at least one data line and a power line.
  • the first electrode of the first reset transistor T1 is connected to the first reset signal line for receiving the first reset signal Vinit1, and the second electrode is connected to the gate electrode of the driving transistor T3 and the first plate of the capacitor Cst.
  • the first electrode of the compensation transistor T2 is connected to the second electrode of the driving transistor T3, and the second electrode is connected to the gate electrode of the driving transistor T3.
  • the first electrode of the write transistor T4 is connected to the data line for receiving the data signal DA, and the second electrode is connected to the first electrode of the drive transistor T3.
  • the first electrode of the first light-emitting control transistor T5 and the second electrode plate of the capacitor Cst are connected to the power line for receiving the first power signal VDD, and the second electrode is connected to the first electrode of the driving transistor T3.
  • the first electrode of the second light emitting control transistor T6 is connected to the second electrode of the driving transistor T3, and the second electrode is connected to the first electrode ANO of a light emitting device LD.
  • the first electrode of the second reset transistor T7 is connected to the second reset signal line for receiving the second reset signal Vinit2, and the second electrode is connected to the second electrode of the second light emitting control transistor T6.
  • the second electrode CAT of the light emitting device LD may receive the second power signal VSS.
  • the gate of the first reset transistor T1 is connected to the first reset control line for inputting the first reset control signal RE1
  • the gate of the second reset transistor T7 is connected to the second reset control line.
  • the reset control line is connected and used to input the second reset control signal RE2.
  • the gates of the compensation transistor T2 and the writing transistor T4 are connected to the scan line for inputting the scan signal
  • the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are connected to the light-emitting control line for inputting the light-emitting control signal.
  • Each transistor of the above-mentioned pixel circuit can be a polycrystalline silicon transistor, that is, the channel of the transistor is polycrystalline silicon, such as a P-type low-temperature polysilicon transistor or an N-type low-temperature polysilicon transistor.
  • metal oxide transistors can also be used, that is, the channels of the transistors are metal oxides such as indium gallium zinc oxide.
  • the P-type low-temperature polysilicon transistor can be turned off when a high level is input to its gate and turned on when a low-level signal is input;
  • the N-type low-temperature polysilicon transistor can be turned off when a low level is input to its gate and turned on when a low-level signal is input. Turns on when the signal is high.
  • the metal oxide transistor can be an N-type metal oxide transistor, which can be turned on when the gate input is high level and turned off when the gate input is low level.
  • the above-mentioned 7T1C pixel circuit can adopt LTPO (LTPS+Oxide) technology.
  • the driving transistor T3, the writing transistor T4, the second reset transistor T7, and the first light emission control transistor T5 The first reset transistor T1 and the compensation transistor T2 can use N-type metal oxide transistors. Since P-type low-temperature polysilicon transistors have higher carrier mobility, they are conducive to realizing display panels with high resolution, high response speed, high pixel density, and high aperture ratio in order to obtain higher carrier mobility. Improve response speed. At the same time, leakage can be reduced through N-type metal oxide transistors.
  • the first reset transistor T1 can be turned on through the first reset control signal RE1, and the first reset signal Vinit1 can be written to the first node N1.
  • the second reset transistor T7 is turned on through the second reset control signal RE2, and the second reset signal Vinit2 is written to the fourth node N4.
  • the gate of the driving transistor T3 and the light emitting device LD can be reset.
  • the writing transistor T4 and the compensation transistor T2 are turned on through the first scanning signal Gate1 and the second scanning signal Gate2, and the data signal DA is written to the first node N1 through the third node N3 and the second node N2. , until the potential reaches Vdata+vth, where Vdata is the voltage of the data signal DA, and Vth is the threshold voltage of the driving transistor T3.
  • the first scanning signal Gate1 and the second scanning signal Gate2 may be the same signal, or they may be two synchronized signals.
  • the first scanning signal Gate1 and the second scanning signal Gate2 may be high-frequency signals, which is beneficial to reducing the load of the source signal of the driving transistor T3.
  • the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on through the light-emitting control signal EM, and the driving transistor T3 is turned on under the action of the voltage Vdata+Vth stored in the capacitor Cst and the second power supply signal VDD.
  • the light-emitting device LD emits light.
  • the first electrode of the driving transistor T3 serves as the source electrode, and the second electrode serves as the drain electrode.
  • the peripheral circuit can be connected to the light-emitting device LD through the pixel circuit, and the first power signal VDD is applied to the first electrode ANO of the light-emitting device LD through the pixel circuit.
  • the peripheral circuit can also be connected to the second electrode CAT of the light-emitting device LD. connection, and applying the second power signal VSS to the second electrode CAT, the current passing through the light-emitting device LD can be controlled by controlling the pixel circuit, thereby controlling the brightness of the light-emitting device LD.
  • the peripheral circuit may include a gate drive circuit, a light-emitting control circuit, etc., and of course may also include other circuits. The specific structure of the peripheral circuit is not particularly limited here.
  • the driving backplane BP may also include a bus located in the peripheral area WA.
  • the bus may pass from the peripheral area WA through the bending area BA, extend into the lead-out area FA, and be connected to the binding part PA.
  • the bus may include a reset signal bus, a first power bus VDB and a second power bus VSB spaced apart in a direction away from the display area AA.
  • the first reset signal line and the second reset signal line are both connected to the reset signal bus for receiving the first reset signal and the second reset signal.
  • the power line can be connected to the first power bus VDB for receiving the first power signal VDD, and the second electrode CAT of each light-emitting device LD can be connected to the second power bus VSB for receiving the second power bus number VSS.
  • the gate drive circuit may include multiple cascaded gate shift register units, which may provide reset control signals and scan signals for multiple rows of pixel circuits, thereby controlling the turn-on timing of the transistors.
  • the above-mentioned scan The first reset control line and the second reset control line are all connected to the gate drive circuit.
  • a gate shift register unit may include multiple transistors and capacitors, which may be 8T2C, 10T2C or 12T2C, etc.
  • nTmC indicates that a pixel circuit includes n transistors (indicated by the letter “T") and m capacitors ( Represented by the letter “C”), its specific structure is not specifically limited here.
  • Multiple gate shift register units are cascaded.
  • the first pole of the input transistor in the first-level gate shift register unit is connected to the input terminal.
  • the input terminal is used to receive the trigger signal as the input signal, while the other levels of gate shift registers
  • the input terminal in the unit is electrically connected to the output terminal of the upper-level gate shift register unit to receive the output signal output by the upper-level gate shift register unit as an input signal, thereby realizing a shift output for display.
  • the pixel circuit in area AA performs progressive scanning.
  • the driving backplane BP may also include peripheral leads GL located in the peripheral area WA, and at least part of the peripheral leads GL may extend through the bending area BA to Lead out area FA, and connect the peripheral circuit and driver chip TIC.
  • the peripheral leads GL may include driving power lines, trigger signal lines, clock signal lines, etc. connected to the gate shift register unit.
  • the driving power lines include a first driving power line for providing power to the gate shift register unit. and a second driving power line, and a trigger signal line for providing the above-mentioned trigger signal.
  • the clock signal line may include a first clock signal line and a second clock signal line, and is used to control the turn-on timing of at least part of the transistors.
  • the structure and specific working principle of the gate drive circuit are not particularly limited here.
  • the light-emitting control circuit may include multiple light-emitting shift register units cascaded along the column direction Y.
  • the structure and working principle of the light-emitting shift register unit are similar to the gate shift register unit, which can control the light-emitting control transistors of each row of pixel circuits to conduct sequentially. On and off.
  • the light-emitting shift register unit may be connected to the light-emitting control line and output the light-emitting control signal EM to the light-emitting control line.
  • the light-emitting shift register unit may be connected to a light-emitting control line to which two rows of pixel circuits are connected.
  • the light-emitting shift register unit can also be connected to multiple peripheral leads GL. These peripheral leads GL can include drive power lines, trigger signal lines, clock signal lines, etc., and their connection relationships will not be described in detail here.
  • the pixel circuit may not include a light emission control transistor, and accordingly, the peripheral circuit may not include a light emission control circuit.
  • At least part of the peripheral leads GL can be connected to the driver chip TIC to receive signals for controlling the peripheral circuit.
  • the driving backplane BP may include a substrate SU, a first semiconductor layer POL, a first gate insulating layer GI1, a first gate electrode layer GA1, first insulating layer IL0, second gate layer GA2, second insulating layer IL1, second semiconductor layer IGL, second gate insulating layer GI2, third gate layer GA3, third insulating layer IL2, A source and drain layer SD1, a first planarization layer PLN1, a second source and drain layer SD2, and a second planarization layer PLN2, wherein:
  • the substrate SU can be a substrate for driving the backplane BP, which can carry pixel circuits and peripheral circuits.
  • the substrate SU can be a hard or flexible structure, and it can be a single-layer or multi-layer structure, which is not specifically limited here.
  • the first semiconductor layer POL may be disposed on one side of the substrate SU and includes a channel of the driving transistor T3, the writing transistor T4, the second reset transistor T7, the first light emission control transistor T5 and the second light emission control transistor T6 in the pixel circuit. road.
  • the material of the first semiconductor layer POL may be polysilicon.
  • the first gate insulating layer GI1 may cover the first semiconductor layer POL, and the material of the first gate insulating layer GI1 may be an insulating material such as silicon nitride or silicon oxide.
  • the first gate layer GA1 may be disposed on a surface of the first gate insulating layer GI1 away from the substrate SU, and includes a first plate of the capacitor.
  • the first insulating layer IL0 may cover the first gate layer GA1, and its material may be an insulating material such as silicon nitride or silicon oxide.
  • the second gate layer GA2 may be disposed on a surface of the first insulating layer IL0 away from the substrate SU, and includes a second plate of the capacitor.
  • the second insulating layer IL1 covers the second gate layer GA2, which may be a single-layer or multi-layer structure, and the material may include inorganic insulating materials such as silicon nitride and silicon oxide, or organic insulating materials such as insulating resin.
  • the second semiconductor layer IGL may be disposed on a surface of the second insulating layer IL1 away from the substrate SU, and includes channels of the first reset transistor T1 and the compensation transistor T2.
  • the material of the second semiconductor layer IGL may include semiconductor metal oxides such as indium gallium zinc oxide (IGZO).
  • the second gate insulating layer GI2 may cover the second semiconductor layer IGL, and its material may be an insulating material such as silicon nitride or silicon oxide.
  • the third gate layer GA3 may be disposed on a surface of the second gate insulating layer GI2 away from the substrate SU.
  • the third insulating layer IL2 may cover the third gate layer GA3. It may have a single-layer or multi-layer structure, and the material may include inorganic insulating materials such as silicon nitride and silicon oxide, or organic insulating materials such as insulating resin.
  • the third insulating layer IL2 may include a dielectric layer and a multi-layer inorganic insulating layer sequentially stacked in a direction away from the substrate SU.
  • the first source and drain layer SD1 may be disposed on a surface of the third insulating layer IL2 away from the substrate SU.
  • the first planar layer PLN1 may be disposed on a side of the first source-drain layer SD1 away from the substrate SU, and its material may be an insulating material such as resin.
  • a passivation layer of an insulating material such as silicon nitride can be used to cover the first source and drain layer SD1, and then the first planarization layer PLN1 can be used to cover the passivation layer.
  • the second source and drain layer SD2 may be disposed on the surface of the first planar layer PLN1 away from the substrate SU.
  • the second flat layer PLN2 may cover the second source and drain layer SD2, and its material may be an insulating material such as resin.
  • the light emitting device LD may be disposed on a side of the second planar layer PLN2 away from the substrate SU.
  • a light-shielding layer BSM can also be provided between the substrate SU and the first semiconductor layer POL, which can be made of light-shielding metal or other materials, and can be a single-layer or multi-layer structure. At least part of the area of the light-shielding layer BSM can overlap with at least part of the channel region of the transistor to block the light irradiating the transistor to stabilize the electrical characteristics of the transistor.
  • the light-shielding layer BSM can include a plurality of light-shielding units distributed in an array. The light shielding unit can shield a channel of a driving transistor T3.
  • each light-shielding unit can be connected through a shading line, so that the light-shielding layer BSM has an integrated structure, and the second power signal VSS or the second power signal VDD is input to the light-shielding layer BSM, so that the light-shielding layer BSM can play an electrostatic shielding role. .
  • the light-shielding layer BSM can be covered by an insulating buffer layer BUF, and the first semiconductor layer POL can be provided on the surface of the buffer layer BUF facing away from the substrate SU.
  • the buffer layer BUF may have a single-layer or multi-layer structure, and its material may include insulating materials such as silicon nitride and silicon oxide.
  • each light-emitting device LD can be connected to a pixel circuit, and the same pixel circuit can be connected to one or more light-emitting devices LD.
  • the light-emitting device LD may be an OLED (organic light-emitting diode), a QLED (quantum dot light-emitting diode), a Micro LED or a Mini LED, etc., and may include a first electrode ANO, a second electrode CAT and a second electrode located between the first electrode ANO and the second electrode The luminescent layer EL between CAT, where:
  • the first electrode ANO may be disposed on one side of the driving backplane BP, for example, the surface of the second flat layer PLN2 away from the substrate SU.
  • the light-emitting layer EL may include a hole injection layer, a hole transport layer, a light-emitting material layer, an electron transport layer, and an electron injection layer stacked in a direction away from the driving backplane BP.
  • Each light-emitting device LD can share the second electrode CAT, that is to say, the second electrode CAT can be a continuous whole-layer structure, and the second electrode CAT can extend to the peripheral area WA, and can be connected to the second power bus VSB, so that Upon receiving the second power signal VSS, the first electrode ANO is distributed in an array to ensure that each light-emitting device LD can emit light independently.
  • a pixel definition layer PDL can be provided on the surface where the first electrode ANO is provided, which can have openings exposing each first electrode ANO, and the light-emitting layer EL is connected to the first electrode ANO in the opening.
  • One electrode ANO is stacked.
  • Each light-emitting device LD can at least share a light-emitting material layer, so that the light-emitting color of each light-emitting device LD is the same.
  • a color film layer can be provided on the side of the light-emitting device LD away from the substrate SU. Through the color film layer The filter part corresponding to each light-emitting device LD realizes color display.
  • the light-emitting material layers of each light-emitting device LD can also be independent, so that the light-emitting device LD can directly emit monochromatic light, and the light-emitting colors of different light-emitting devices LD can be different, thereby achieving color display.
  • the display panel can also include an encapsulation layer TFE, which can cover the light-emitting device LD to protect the light-emitting device LD and prevent external water and oxygen from corroding the light-emitting device LD.
  • the encapsulation layer TFE can be encapsulated by thin film encapsulation, which can include a first inorganic layer, an organic layer and a second inorganic layer, wherein the first inorganic layer covers the light-emitting device LD, and the organic layer can be disposed on the third inorganic layer.
  • An inorganic layer faces away from the surface of the driving backplane BP, and the boundary of the organic layer is limited to the inside of the boundary of the first inorganic layer.
  • the boundary of the orthographic projection of the organic layer on the driving backplane BP can be located in the peripheral area WA to ensure that the organic layer can Cover each light emitting device LD.
  • the second inorganic layer can cover the organic layer and the first inorganic layer that is not covered by the organic layer, can block the intrusion of water and oxygen through the second inorganic layer, and achieve planarization through the flexible organic layer.
  • the touch layer TSP can be disposed on the side of the light-emitting device LD away from the driving backplane BP.
  • the touch layer TSP can be disposed on the surface of the packaging layer TFE away from the driving backplane BP. It can use capacitive touch.
  • Control structures include self-capacitance structures and mutual-capacity structures. Take the self-contained structure as an example:
  • the touch layer TSP may include a plurality of touch electrodes TMB located in the display area AA.
  • Each touch electrode TMB is distributed in an array and is spaced apart from each other.
  • Each touch electrode TMB forms a self-capacitance with the ground.
  • the capacitance of the finger will be superimposed on the self-capacitance of the touch electrode TMB, causing the capacitance to increase. Therefore, the capacitance of the touch electrode TMB can be detected. changes to determine the position of the touch point, that is, the position of the touch electrode TMB corresponding to the touch point.
  • Each touch electrode TMB can be connected to the driver chip TIC through a touch lead TL1.
  • one touch electrode TMB can be connected to one touch lead TL1, and each touch lead TL1 extends from the display area AA to the lead-out area FA, and It is connected to the function pin P1a of the driver chip TIC to apply a touch drive signal to the touch electrode TMB and receive a touch sensing signal generated based on the capacitance change.
  • the touch electrode TMB can have a mesh structure, and the light-emitting device can correspond to the mesh of the mesh structure, thereby reducing the light blocking by the touch electrode TMB.
  • the touch layer TSP can also include a buffer layer TBU and a protective layer TOC.
  • the buffer layer TBU can serve as the base of the touch layer TSP, and can be provided on the surface of the encapsulation layer TFE away from the substrate SU.
  • Materials may include insulating materials such as silicon nitride and silicon oxide.
  • the protective layer TOC can cover the touch electrode TMB, and the material of the protective layer TOC can be a transparent insulating material such as polyimide (PI) or optical glue.
  • the touch layer TSP may also adopt a mutual capacitance structure, and its structure is not particularly limited here.
  • the driver chip TIC can be stacked on the lead-out area FA of the drive backplane BP, and is located between the bending area BA and the binding part PA, and is connected to the binding part PA.
  • the driver chip TIC can be used to output touch drive signals to the touch layer TSP and receive touch sensing signals to implement the touch function.
  • the driver chip TIC can also be used to drive the light-emitting device LD to emit light through the driver circuit to display images and realize the integration of display and touch functions.
  • the driver chip TIC can also be used only to implement the touch function, while the display image can be implemented through other chips.
  • the driver chip TIC has at least one touch pin group PG and multiple strobe circuits Mux.
  • the touch pin group PG may include multiple first touch pins P1, and some of the touch pins P1 are functional pins P1a. , part of the first touch pin P1 is a dummy pin P1d.
  • each functional pin P1a of the touch pin group PG is connected to a touch lead TL1.
  • a touch lead TL1 and a functional pin P1a can be connected through a connecting wire TL3, and a connecting wire TL3 TL3 can be an integrated structure with the touch lead TL1 connected to it.
  • the two can also be independent structures connected through a connection process.
  • the connection trace TL3 can overlap the driver chip TIC.
  • the driver chip TIC also has a second touch pin P2.
  • the second touch pin P2 can be connected to the first touch pin P1 through the strobe circuit Mux.
  • the second touch pin P2 can be connected to the binding part.
  • Some pins of the PA are connected and can be connected to the control circuit board through the flexible circuit board connection binding part PA so as to transmit the touch drive signal.
  • the strobe circuit Mux may be part of an internal circuit integrated in the driver chip TIC.
  • the first touch pin P1 of a touch pin group PG can be connected to a second touch pin P2 through a strobe circuit Mux, and the second touch pin P2 connected to a different strobe circuit Mux can different.
  • a second touch pin P2 can be connected to multiple first touch pins P1 through a strobe circuit Mux.
  • the pins of the binding part PA include the binding pin PA1, and the second touch pin P2 can be connected to the binding pin PA1, and the two can be connected one by one.
  • FIG. 7 is a schematic diagram for illustrating the connection relationship between the first touch pin P1, the strobe circuit Mux and the second touch pin P2, and does not constitute a limitation on the actual structure of the driver chip TIC.
  • the driver chip TIC may include two touch terminals TIC1 distributed along the row direction X and a first pin terminal TIC2 and a second pin terminal TIC3 distributed along the column direction Y.
  • the pin terminal TIC3 is located on the side of the first pin terminal TIC2 close to the binding part PA.
  • One touch pin group PG can be located at one touch terminal TIC1. If there are two touch pin groups PG, they are located at two touch terminals TIC1 respectively, and the touch pin groups PG of the two touch terminals TIC1
  • the driving chip TIC can be arranged symmetrically along the central axis in the column direction Y.
  • the first pin terminal TIC2 can also be provided with a plurality of display pins P3, and the driving circuit that drives the light-emitting device LD to emit light can be connected to at least part of the display pins P3, so that in the driving chip TIC Under control, the light-emitting device LD is driven to emit light.
  • the display pin P3 can be divided into two display pin groups along the row direction between pin groups.
  • the second touch pin P2 may be located at the second pin terminal TIC3.
  • the first pin terminal TIC2 may have multiple dummy touch pins Pd, and the dummy touch pins Pd may be distributed along the row direction X, and the dummy touch pins Pd may be located between two display pin groups.
  • Each touch lead TL1 is connected to each dummy touch pin Pd respectively.
  • the touch lead TL1 and the dummy touch pin Pd may be connected in a one-to-one correspondence.
  • the dummy touch pin Pd is in a floating state and does not transmit signals, which is beneficial to improving the uniformity of the connection between the first pin terminal TIC1 and the driving backplane BP.
  • the dummy touch pin Pd does not need to be connected to the touch lead TL1.
  • the number of first touch pins P1 is less than the total number of pins that can be controlled by the strobe circuit Mux, so some of the first touch pins P1 need to transmit touch drive signals.
  • These first touch pins P1 are Functional pin P1a; and there are some first touch pins P1 that do not need to transmit touch drive signals and do not need to be connected to the touch lead TL1.
  • These first touch pins P1 are dummy pins P1d.
  • each strobe circuit Mux is connected to the dummy pin P1d and the functional pin P1a, then each strobe circuit Mux needs to be turned on, but there is no need to transmit signals through the dummy pin P1d, which is not conducive to reducing energy consumption.
  • the present disclosure designs a connection method between the strobe circuit Mux and the first touch pin P1, as shown in Figures 6 and 7, so that at least one strobe circuit Mux is connected to the first touch pin P1
  • the pins P1 are all dummy pins P1d.
  • the strobe circuit Mux since there is no need for signal transmission, the strobe circuit Mux can be turned off. is turned off, only the strobe circuit Mux connected to the function pin P1a works, thereby reducing power consumption without affecting the touch function.
  • the strobe circuit Mux connected to the function pin P1a can be used to sequentially conduct the second touch pin P2 and its connected function pins P1a, that is, connecting the function pin P1a and the second touch pin P1a.
  • the control pin P2 is used to transmit the touch drive signal to the touch lead TL1 to drive the touch layer TSP.
  • the strobe circuit Mux connected to the dummy pin P1d remains off.
  • the dummy pin P1d is floating and does not need to receive control signals. Turning off the strobe circuit Mux connected to the dummy pin P1d will not affect the touch control. function and can reduce power consumption.
  • the first touch pin P1 of the touch pin group PG can be divided to obtain multiple pin units PU.
  • Each pin unit PU includes multiple functional pins P1a and at least one dummy pin. P1d.
  • the gating circuit may include a plurality of first gating circuits Mux1 and at least one second gating circuit Mux2.
  • Each first strobe circuit Mux1 can be connected to the first touch pin P1 in multiple pin units PU at the same time, and a functional pin P1a in each pin unit PU is connected to a first strobe circuit Mux1 Connection; a dummy pin P1d in a pin unit PU is connected to a second strobe circuit Mux2.
  • the functional pin P1a connected to each first strobe circuit Mux1 can come from a different pin unit PU, and the dummy pin P1d connected to each second strobe circuit Mux2 also comes from a different pin unit. PU, so that the first touch pins P1 connected to the first strobe circuit Mux1 are all functional pins P1a, and the first touch pins P1 connected to the second strobe circuit Mux2 are all dummy pins P1d.
  • the first touch pins P1 in the same touch pin group PG may be distributed at intervals along the column direction Y, and the last touch pin P1 of any pin unit PU in the column direction Y
  • One touch pin P1 is a dummy pin P1d.
  • the number of dummy pins P1d in one pin unit PU in a touch pin group PG is one.
  • the first touch pin P1 closest to the binding part PA of each pin unit PU is a dummy pin P1d.
  • the functional pin P1a in each pin unit PU is regarded as a For pin subunits, in the column direction Y, each pin subunit and the dummy pin P1d are alternately distributed.
  • the number of functional pins P1a in each pin unit PU may be three, and the number of strobe circuits Mux connected to the first touch pin P1 of the same touch pin group PG may be four.
  • the number of function pins P1a required for the touch function at one touch terminal TIC1 is less than 3/4 of the total number of first touch pins P1 of the touch terminal TIC1, and is greater than 1/2 .
  • the number of dummy pins P1d in one pin unit PU in a touch pin group PG is two.
  • the first touch pin P1 closest to the binding part PA of each pin unit PU is the dummy pin P1d.
  • the functional pin P1a in each pin unit PU is regarded as For a pin subunit, in the column direction Y, each pin subunit and the dummy pin P1d are alternately distributed.
  • the number of functional pins P1a in each pin unit PU may be three, and the number of strobe circuits Mux connected to the first touch pin P1 of the same touch pin group PG may be four.
  • the number of function pins P1a required to implement the touch function at one touch terminal TIC1 is less than 1/2 of the total number of first touch pins P1 of the touch terminal TIC1.
  • the first touch pin P1 of a touch pin group PG may include multiple pin units PU, at least some of the pin units PU only include functional pins P1a, and At least some of the pin units PU only include dummy pins P1d; the first touch pin P1 in one pin unit PU is connected to the same strobe circuit Mux. That is to say, the first touch pins P1 connected to the first strobe circuit Mux1 are all from the same pin unit PU, and are all functional pins P1a.
  • the first touch pins P1 connected to the second strobe circuit Mux2 are all from the same pin unit PU, and are all dummy pins P1d.
  • Each pin unit PU may be distributed along the column direction Y.
  • the first touch pins P1 in a touch pin group PG can be distributed in other ways, as long as the second strobe circuit Mux2 is connected to dummy pins P1d That’s it.
  • the first touch pins P1 in the same touch pin group PG can be arranged in multiple columns distributed along the row direction X, and the first touch pins in two adjacent columns are The pins P1 are alternately distributed in the column direction Y. That is to say, the first touch pins P1 in two adjacent columns can be staggered along the column direction Y.
  • each dummy pin P1d can be located in the same column.
  • the first touch pins P1 in the same touch pin group PG can be arranged in two columns along the row direction .
  • the driver chip TIC may also have a first test pin Pt, and the binding part PA may have a plurality of second test pins PA2.
  • Pin PA2 can be distributed X-spaced along the row direction with bound pin PA1.
  • the touch display panel also includes a plurality of test lines TL2.
  • a connection line TL3 can be connected to a second test pin PA2 through a test line TL2.
  • connection line TL3 Since the connection line TL3 is connected to the function pin P1a, the test line TL2 is also connected to the functional pin P1a accordingly; a first test pin Pt can be connected to a second test pin PA2 through a test line TL2, and at the same time, a connection line TL3 can be connected to a test line TL2, correspondingly , a test line TL2 is connected to a function pin P1a.
  • the first test pin Pt is located at the touch terminal TIC1 and is spaced apart from the first touch pin P1. At least part of the test line TL2 connected to the first test pin Pt can be used for grounding. Of course, it can also be used for access. Test line TL2 for test signals and other signals.
  • both touch terminals TIC1 have first test pins Pt, and the first test pins Pt of the two touch terminals TIC1 are symmetrical Distribution, the two first test pins Pt respectively belonging to the two touch terminals TIC1 can be connected through the test connection line TL5 in order to transmit the ground signal or other signals.
  • the driver chip TIC can overlap with the test connection line TL5.
  • test lines TL2 can be connected through the ground connection line TL4. As long as one of these test lines TL2 is connected, it can be realized.
  • the pin with the grounding function can realize the grounding of multiple test lines TL2.
  • the ground connection line TL4 can extend along the column direction Y, so that it can cross multiple test lines TL2.
  • the test line TL2 can be made into a multi-layer structure.
  • the ground connection line TL4 can be set on the same layer as one of the layers, and can be Other layers cross.
  • the first test pin Pt1 can realize the pin with the grounding function, while the first test pin Pt2 cannot realize the pin with the grounding function, but the first test pin Pt1 and the first The test line TL2 connected to the test pin Pt2 needs to be grounded. Therefore, the ground connection line TL4 can be used to connect the two test lines TL2 connected to the first test pin Pt1 and the first test pin Pt2, so that the two test Line TL2 can realize the grounding function. At the same time, since the ground connection line TL4 extends along the column direction Y and crosses multiple test lines TL2, it needs to be connected to two test lines TL2.
  • the test line TL2 that crosses the ground connection line TL4 can be at least divided into The first section TL21 and the second section TL22 are located on different layers.
  • the first section TL21 can intersect with the second section TL22 on different layers.
  • the first section T21 can be connected to the connecting trace TL3 or the first test pin Pt.
  • the segment T22 can be connected to the first segment T21 through the contact hole and to the second test pin PA2.
  • the first section TL21, the connecting trace TL3 and the ground connection line TL4 are arranged on the first gate layer GA1 in the same layer, and the second section TL22 is arranged on the first source and drain layer SD1; the ground connection line TL4 intersects the second section TL22 But they are different layers and can be connected to the two test lines TL2 respectively through the contact holes.
  • the binding pin PA1 can be bound to the flexible circuit board, while the second test pin PA2 is not bound to the flexible circuit board and is only used for testing touch. The purpose of the function.
  • a support bump Bum is provided on the side of the driver chip TIC close to the driver backplane BP for supporting the driver chip TIC.
  • this disclosure also proposes a new solution for the path of the leads connecting some pins in the lead-out area FA.
  • An exemplary explanation is given below:
  • the part of the touch lead TL1 in the lead-out area FA may include two touch lead-out sections TL11, two touch transition sections TL12 and a touch lead-out section TL11 distributed along the column direction Y.
  • the connection section TL13, the touch lead-out section TL11, the touch transition section TL12 and the touch connection section TL13 all include the parts of the multiple touch leads TL1 in the lead-out area FA, that is to say, the touch lead-out section TL11, the touch transition section TL11
  • the segment TL12 and the touch connection segment TL13 are both a collection of multiple touch leads TL1 in the lead-out area FA, rather than specifically referring to a specific touch lead TL1.
  • the touch lead-out section TL11 is connected to the part of the touch lead TL1 located in the peripheral area WA, and the two touch lead-out sections TL11 are spaced apart along the row direction X; the touch connection section TL13 is connected to each connection trace TL3, for example, the touch Each touch lead TL1 of the control connection section TL13 can be connected to each connection trace TL3 in a one-to-one correspondence, and thereby connected to each function pin P1a in a one-to-one correspondence.
  • the touch connection section TL13 can be connected to the dummy touch pin Pd.
  • a touch lead-out section TL11 is connected to the touch connection section TL13 through a touch transition section TL12, and the touch connection section TL13 is located between the two touch lead-out sections TL11.
  • the touch lead-out section TL11 and the touch connection section TL13 both extend along the column direction Y.
  • the extension direction of the touch transition section TL12 is different from the row direction X and the column direction Y, so that they are arranged obliquely relative to the row direction X and the column direction Y.
  • the included angle of the touch transition section TL12 can be an acute angle, of course, or it can also be a right angle or an obtuse angle.
  • the two touch lead-out sections TL11 may be symmetrical with respect to the central axis of the driving chip TIC along the column direction Y
  • the two touch transition sections TL12 may be symmetrical with respect to the central axis of the driving chip TIC along the column direction Y.
  • the part of the touch lead TL1 in the lead-out area FA can be extended in a "Y" shape, and the touch lead TL1 When entering the lead-out area FA, it is divided into two touch lead-out sections TL11. After being connected by the two touch transition sections TL12, they converge into the touch connection section TL13 and are connected to each connection trace TL3.
  • the peripheral lead GL can extend from the peripheral area WA to the lead-out area FA, and is connected to the peripheral circuit in the peripheral area WA. In the lead-out area FA, it is connected to the driver chip through part of the display pin P3 TIC connection.
  • the peripheral lead GL and the touch lead TL1 are located in different layers.
  • the touch lead TL1 can be located in the touch layer TSP
  • the peripheral lead GL can be located in the driving backplane BP.
  • the part of the peripheral leads GL in the lead-out area FA can be divided into two peripheral line groups GL1 distributed along the row direction X.
  • One peripheral line group GL1 can include a display lead-out section GL11 distributed along the column direction Y, a display transition section GL12 and a third A display extension section GL13; wherein: the display transition section GL12 can be connected between the display lead-out section GL11 and the first display extension section GL13; the display lead-out section GL11 is connected to the portion of the peripheral lead located in the peripheral area WA, and the first display extension section GL13 Connected to part of the display pin P3; the display lead-out section GL11 and the first display extension section GL13 both extend along the column direction Y, and the extension direction of the display transition section GL12 is different from the row direction X and the column direction Y, so that relative to the row direction X and The column direction Y is tilted, and the angle between the two touch transition sections TL12 can be an acute angle,
  • the two display lead-out sections GL11 are located between the two touch lead-out sections TL11, and the touch transition section TL12 and the display transition section GL12 intersect in a one-to-one correspondence. However, since the touch transition section TL12 and the display transition section TL12 The transition section GL12 is not on the same layer, so it is not connected.
  • the two display lead-out sections GL11 are located between the two touch control lead-out sections TL11, and the touch control connection section TL13 is located between the two display connection sections GL15.
  • the peripheral line group GL1 also includes a second display extension section GL14 and a display connection section GL15.
  • the second display extension section GL14 can extend along the row direction X and is connected with the first display extension section GL14.
  • the extension section GL13 is connected to one end away from the display area AA, and the second display extension section GL14 can extend along the row direction X in a direction away from the touch connection section TL13.
  • the display connection section GL15 extends along the column direction Y, is located outside the two data line groups DAL1, and is connected to part of the display pin P3.
  • the above-mentioned first power bus VDB can be located in the peripheral area WA, extend to the lead-out area FA, and be connected to the binding part PA for transmitting the first power signal.
  • the first power bus VDB, the touch lead TL1 and the peripheral lead GL are all located on different layers, and the touch lead TL1 is located on the side of the first power bus VDB away from the peripheral lead GL.
  • the power line can extend along the column direction Y, and extends from the display area AA to the peripheral area WA, and is connected to the first power bus VDB.
  • One column of power lines is connected to at least one column of pixel circuits.
  • the part of the first power bus VDB located in the lead-out area FA includes a shielding part VDB1 and a connection part VDB2.
  • the shielding part VDB1 is connected to the part of the first power bus VDB located in the peripheral area WA, and the connection part VDB2 connects the shielding part VDB1 and the binding part PA. to receive the first power signal.
  • the touch lead-out section TL11, the touch transition section TL12, the display lead-out section GL11 and the display transition section GL12 all at least partially overlap with the shielding portion VDB1. Since the first power signal is a constant signal, peripheral leads can be prevented through the shielding portion VDB1.
  • the signal in the touch lead TL1 causes interference to the signal in the touch lead TL1.
  • the orthographic projections of the touch lead-out section TL11, the touch transition section TL12, the display lead-out section GL11 and the display transition section GL12 on the substrate SU are all located within the orthographic projection of the shielding portion VDB1 on the substrate SU.
  • connection parts VDB2 is two, and they are connected to both ends of the shield part VDB1 in the row direction side of PA.
  • the peripheral line group GL1 may also include a third display extension segment GL16, one end of which is connected to an end of the second display extension segment GL14 away from the first display extension segment GL13, and may extend along the row direction X away from the first display extension segment GL13, while , the third display extension section GL16 can overlap with the connection part VDB2 and the part of the second power bus VSB located in the lead-out area FA, and the third display extension section GL16 overlaps with the connection part VDB2 and the part of the second power bus VSB located in the lead-out area FA. Located on different floors.
  • the data line DAL can extend along the column direction Y, and extends from the display area AA to the lead-out area FA, and is connected to part of the display pin P3, and one column of data line DAL is connected to at least one column of pixel circuits. Used to transmit data signals.
  • the part of the data line DAL located in the lead-out area FA may include two data line groups DAL1 distributed along the row direction GL12 and the display connection segment GL15 are both located between the two data line groups DAL1.
  • the data line group DAL1, the first power bus VDB and the touch lead TL1 are all located on different layers, and the touch lead TL1 is located on the side of the first power bus VDB away from the touch lead group.
  • the data line group DAL1 and the shielding portion VDB1 at least partially overlap, so that the shielding portion VDB1 can prevent the data signal of the data line DAL from causing interference to the signal in the touch lead TL1.
  • the second display extension section GL14 intersects the data line group DAL1 and is located on a different layer.
  • the display pins P3 of the two display pins P3 group of the first pin terminal TIC2 both include the first display pin P31 and the second display pin P32, and the peripheral lead GL passes through the first display pin P31 is connected to the driver chip TIC, and the data line DAL can be connected to the driver chip TIC through the second display pin P32.
  • the first display pin P31 may be located on a side of the second display pin P32 away from the dummy touch pin Pd along the row direction X.
  • the display pins P3 of the two display pin groups P3 may be symmetrical with respect to the central axis of the driver chip TIC along the column direction Y.
  • the second power bus VSB extends from the peripheral area WA to the lead-out area FA, and is located on the side of the first power bus VDB away from the display area AA, that is, outside the first power bus VDB.
  • the second power supply line located in the lead-out area FA The bus VSB can be connected to some pins of the binding part PA.
  • the touch connection line TL2 may include a first section TL21 and a second section TL22 located on different layers.
  • the first section TL21 is connected to the function pin P1a
  • the second section TL22 is connected to the first section TL21 and the functional pin P1a.
  • the binding part PA, and the first section TL21 and the second section TL22 are connected through the contact hole.
  • any one of the first power bus VDB, the second power bus VSB, the power line, the data line DAL, the peripheral lead GL and the touch lead TL1 it is located on the periphery
  • the part of the area WA and the part located in the lead-out area FA may be located on the same film layer, or may be located on different film layers.
  • the parts located in the lead-out area FA can also be connected by line segments located in different film layers. For example:
  • the portions of the first power bus VDB and the second power bus VSB located in the lead-out area FA may be located in at least one of the first gate layer GA1, the second gate layer GA2, and the third gate layer GA3.
  • the parts of the power line and the data line DAL located in the display area AA and the peripheral area WA may be located in at least one of the first source-drain layer SD1 and the second source-drain layer SD2, and the part of the data line DAL located in the lead-out area FA may be located in the first gate At least one of the electrode layer GA1, the second gate layer GA2 and the third gate layer GA3.
  • the portion of the peripheral lead GL located in the lead-out area FA may be located in at least one of the first gate layer GA1, the second gate layer GA2 and the third gate layer GA3, and the part of the peripheral lead GL in the lead-out area FA may be connected to The portion of the data line DAL located in the lead-out area FA is located on the same layer.
  • the display lead-out section GL11, the display transition section GL12, the first display extension section GL13, the display connection section GL15 and the third display extension section GL16 can be located on the first gate layer GA1 with the part of the data line DAL located in the lead-out area FA.
  • the second display extension section GL14 may be located on the first source-drain layer SD1, so that the second display extension section GL14 is connected to the intersection of the data line DAL located in the lead-out area FA.
  • the touch lead TL1 may be located on the same layer as the touch electrode TMB.
  • the present disclosure also provides a display device, which may include the touch display panel of any of the above embodiments.
  • the touch display panel is a touch display panel according to any of the above embodiments.
  • the display device of the present disclosure can be a mobile phone, a smart watch, a smart bracelet, a tablet computer, a television, and other electronic devices with a display function, which are not listed here.

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Abstract

一种触控显示面板及显示装置，涉及显示技术领域。触控显示面板具有显示区、外围区和引出区，外围区位于显示区外，引出区沿列方向设置于外围区外，且引出区具有用于与柔性电路板连接的绑定部；触控显示面板包括触控层和驱动芯片。驱动芯片具有触控引脚组和选通电路，触控引脚组包括第一触控引脚，第一触控引脚包括功能引脚和虚设引脚；触控层通过触控引线与功能引脚连接，且一功能引脚与一触控引线连接；驱动芯片还具有与绑定部连接的第二触控引脚；第二触控引脚通过选通电路与第一触控引脚连接；选通电路连接的第一触控引脚均为虚设引脚；与功能引脚连接的选通电路用于依次导通第二触控引脚及其连接的各功能引脚；与虚设引脚连接的选通电路关断。 (图7)

Description

触控显示面板及显示装置 技术领域
本公开涉及触控技术领域，具体而言，涉及一种触控显示面板及显示装置。
背景技术
触控显示面板是手机、智能手表等终端设备的重要组成部分，在实现图像显示的同时，可以通过触控操作实现人机交互。但是现有触控显示面板的触控的功耗仍然较高。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开提供一种触控显示面板及显示装置。
根据本公开的一个方面，提供一种触控显示面板，所述触控显示面板具有显示区、外围区和引出区，所述外围区位于所述显示区外，所述引出区沿列方向设置于所述外围区外，且所述引出区具有用于与柔性电路板连接的绑定部；
所述触控显示面板包括：
触控层；
驱动芯片，具有至少一个触控引脚组和多个选通电路，所述触控引脚组包括多个第一触控引脚，一所述触控引脚组的第一触控引脚包括多个功能引脚和至少一个虚设引脚；所述触控层通过多个触控引线与各所述功能引脚连接，且一所述功能引脚至少与一所述触控引线连接；所述驱动芯片还具有与所述绑定部连接的第二触控引脚；
所述第二触控引脚通过所述选通电路与各所述第一触控引脚连接；至少一个所述选通电路连接的所述第一触控引脚均为所述虚设引脚；
与所述功能引脚连接的选通电路用于依次导通所述第二触控引脚及 其连接的各所述功能引脚；与所述虚设引脚连接的选通电路关断。
在本公开的一种示例性实施方式中，一所述触控引脚组的第一触控引脚包括多个引脚单元，每个所述引脚单元包括多个所述功能引脚和至少一个所述虚设引脚；所述选通电路包括第一选通电路和第二选通电路；
一所述选通电路同时与多个所述引脚单元中的第一触控引脚连接，且每个所述引脚单元内的一所述功能引脚与一所述第一选通电路连接，同一所述引脚单元中的至少两个所述功能引脚所连接的第一选通电路不同；一所述引脚单元内的一所述虚设引脚与一所述第二选通电路连接。
在本公开的一种示例性实施方式中，同一所述触控引脚组中的第一触控引脚沿所述列方向间隔分布，且任一所述引脚单元在所述列方向上的最后一个第一触控引脚为所述虚设引脚。
在本公开的一种示例性实施方式中，同一所述触控引脚组中的第一触控引脚排成沿行方向分布的多列，且相邻两列所述第一触控引脚在所述列方向上交替间隔分布；所述虚设引脚位于同一列。
在本公开的一种示例性实施方式中，所述触控引脚组的数量为两个，且位于所述驱动芯片在所述行方向上的两端。
在本公开的一种示例性实施方式中，一所述触控引脚组的第一触控引脚包括多个引脚单元，至少部分所述引脚单元中仅包括所述功能引脚，至少部分所述引脚单元中仅包括所述虚设引脚；一所述引脚单元中的第一触控引脚与同一所述选通电路连接。
在本公开的一种示例性实施方式中，所述引出区还包括沿行方向延伸的弯折区，所述绑定部位于所述弯折区远离所述显示区的一侧；
所述驱动芯片设于所述引出区内，且位于所述弯折区和所述绑定部之间。
在本公开的一种示例性实施方式中，所述驱动芯片包括沿行方向分布的两个触控端和沿所述列方向分布的第一引脚端和第二引脚端；所述触控引脚组位于所述触控端；所述第二引脚端位于所述第一引脚端靠近所述绑定部的一侧，所述第二触控引脚位于所述第二引脚端；
所述第一引脚端具有多个显示引脚；一所述触控引线通过一连接走线与一所述功能引脚连接；所述驱动芯片与所述连接走线至少部分交叠；
所述触控显示面板还包括：
多个发光器件，设于所述显示区；
驱动背板，用于驱动所述发光器件发光，且包括像素电路、外围电路和外围引线，所述像素电路位于所述显示区，所述外围电路位于所述外围区，所述外围引线由所述外围区延伸至所述引出区，且与所述外围电路连接，并通过部分所述显示引脚与所述驱动芯片连接；所述外围引线与所述触控引线位于不同层；
所述触控层设于所述发光器件远离所述驱动背板的一侧。
在本公开的一种示例性实施方式中，所述触控引线在所述引出区的部分包括沿所述列方向分布的两个触控引出段、两个触控过渡段和一个触控连接段；所述触控引出段与所述触控引线位于外围区的部分连接，所述触控连接段通过所述连接走线与所述功能引脚连接，一所述触控引出段通过一所述触控过渡段与所述触控连接段连接，且所述触控连接段位于两所述触控引出段之间；所述触控引出段和所述触控连接段均沿所述列方向延伸，所述触控过渡段的延伸方向与所述行方向和列方向不同；
所述外围引线在所述引出区内的部分分为沿所述行方向分布的两个外围线组；
所述外围线组包括沿所述列方向分布的显示引出段、显示过渡段和第一显示延伸段，且所述显示过渡段连接于所述显示引出段和第一显示延伸段之间；所述显示引出段与所述外围引线位于外围区的部分连接，所述第一显示延伸段与部分所述显示引脚连接；所述显示引出段和所述第一显示延伸段均沿所述列方向延伸，所述显示过渡段的延伸方向与所述行方向和列方向不同；
两个所述显示引出段位于两所述触控引出段之间，所述触控过渡段和显示过渡段一一对应的交叉，两个所述显示引出段位于两所述触控引出段之间，所述触控连接段位于两所述第一显示延伸段之间。
在本公开的一种示例性实施方式中，所述触控显示面板还包括：
第一电源总线，设于所述外围区，并延伸至所述引出区，且与所述绑定部连接，用于传输第一电源信号；所述第一电源总线、所述触控引线和所述外围引线均位于不同层，且所述触控引线位于所述第一电源总 线远离所述外围引线的一侧；
多个电源线，沿所述列方向延伸，且由所述显示区延伸至所述外围区，并与所述第一电源总线连接；一列所述电源线与至少一列所述像素电路连接；
所述第一电源总线位于所述引出区的部分包括屏蔽部和连接部，所述屏蔽部与所述第一电源总线位于所述外围区的部分连接，所述连接部连接所述屏蔽部与所述绑定部；所述触控引出段、触控过渡段、显示引出段和显示过渡段均与所述屏蔽部至少部分交叠。
在本公开的一种示例性实施方式中，所述触控显示面板还包括：
数据线，沿所述列方向延伸，且由所述显示区延伸至所述引出区，并与部分所述显示引脚连接，一列所述数据线与至少一列所述像素电路连接，用于传输数据信号；
所述数据线位于所述引出区的部分包括沿所述行方向分布的两个数据线组，所述触控引出段、触控过渡段、触控连接段、显示引出段和显示过渡段和显示连接段均位于两所述数据线组之间；所述数据线组、所述第一电源总线与所述触控引线均位于不同层，且所述触控引线位于所述第一电源总线远离所述数据线组的一侧，所述数据线组与所述屏蔽部至少部分交叠。
在本公开的一种示例性实施方式中，所述外围线组还包括第二显示延伸段和显示连接段，所述第二显示延伸段沿所述行方向延伸，且与所述第一显示延伸段远离所述显示区的一端连接，且沿所述行方向朝远离所述触控连接段的方向延伸；所述第二显示延伸段与所述数据线组交叉且位于不同层；所述连接段沿所述列方向延伸，且位于两所述数据线组的外侧，并与部分所述显示引脚连接。
在本公开的一种示例性实施方式中，所述显示引脚沿所述行方向分为两个显示引脚组，所述第一引脚端具有位于两个所述显示引脚组之间的虚设触控引脚，所述触控连接段与一所述虚设触控引脚连接。
在本公开的一种示例性实施方式中，两个所述显示引脚组的显示引脚均包括第一显示引脚和第二显示引脚，所述外围引线通过所述第一显示引脚与所述驱动芯片连接，所述数据线通过所述第二显示引脚与所述 驱动芯片连接；
在一所述显示引脚组中，所述第一显示引脚沿行方向位于所述第二显示引脚远离所述虚设触控引脚的一侧。
在本公开的一种示例性实施方式中，所述驱动背板包括：
衬底；
第一半导体层，设于所述衬底一侧；所述第一半导体层的材料为多晶硅；
第一栅绝缘层，覆盖所述第一半导体层；
第一栅极层，设于所述第一栅绝缘层远离所述衬底的表面，且与所述第一半导体层的至少部分区域交叠；
第一绝缘层，覆盖所述第一栅极层；
第二栅极层，设于所述第一绝缘层远离所述衬底的表面；
第二绝缘层，覆盖所述第二栅极层；
第二半导体层，设于所述第二绝缘层远离所述衬底的表面；所述第二半导体层的材料为金属氧化物；
第二栅绝缘层，覆盖所述第二半导体层；
第三栅极层，设于所述第二栅绝缘层远离所述衬底的表面，且与所述第二半导体层的至少部分区域交叠；
第三绝缘层，覆盖所述第三栅极层；
第一源漏层，设于所述第三绝缘层远离所述衬底的表面；
第一平坦层，设于所述第一源漏层远离所述衬底的一侧；
第二源漏层，设于所述第一平坦层远离所述衬底的表面；
第二平坦层，覆盖所述第二源漏层；
所述发光器件设于所述第二平坦层远离所述衬底的一侧。
在本公开的一种示例性实施方式中，所述触控层包括多个阵列分布的触控电极，一所述触控电极与一所述触控引线连接。
在本公开的一种示例性实施方式中，所述驱动芯片还具有第一测试引脚；所述绑定部具有多个第二测试引脚；所述触控显示面板还包括多个测试线；
一所述连接走线通过一所述测试线与一所述第二测试引脚连接；一 所述第一测试引脚通过一所述测试线与一所述第二测试引脚连接。
根据本公开的一个方面，一种显示装置，包括上述任意一项所述的触控显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开触控显示面板一实施方式的俯视图。
图2为本公开触控显示面板一实施方式的局部截面示意图。
图3为本公开触控显示面板一实施方式中触控层的局部俯视图。
图4为本公开触控显示面板一实施方式中像素电路原理图。
图5为本公开触控显示面板一实施方式中引出区的局部俯视图。
图6为本公开触控显示面板一实施方式中引出区的局部放大图。
图7为本公开触控显示面板一实施方式中第一触控引脚和选通电路的原理图。
图8为图6中触控引线、外围引线和数据线在引出区内的示意图。
图9为图6中触控引线在引出区内的示意图。
图10为图6中外围引线在引出区内的示意图。
图11为本公开触控显示面板一实施方式中引出区未设置驱动芯片时的局部俯视图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反， 提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
本文中的行方向和列方向Y仅为两个相互垂直的方向，在本公开的附图中，行方向可以是横向，列方向Y可以是纵向，但并不限于此，若触控显示面板发生旋转，则行方向和列方向Y的实际朝向可能发生变化。
本文中的A特征和B特征“交叠”是指A特征在衬底上的正投影和B特征在衬底上的正投影至少部分重合。
本公开实施方式提供了一种触控显示面板，如图1所示，该触控显示面板具有显示区AA、外围区WA和引出区FA，其中：外围区WA位于显示区AA外，外围区WA可以是围绕显示区AA的连续或间断的环形区域，或者，也可以是半封闭的区域，在此不对外围区WA的形状做特殊限定。引出区FA位于外围区WA外，且沿列方向Y朝远离显示区AA的方向延伸。引出区FA具有绑定部PA，绑定部PA可具有多个引脚，可将绑定部PA的至少部分引脚与一柔性电路板连接，并将柔性电路板与一控制电路板绑定，从而实现触控显示面板和控制电路板的连接，通过控制电路板可控制触控显示面板显示图像以及实现触控功能。
在本公开的一些实施方式中，引出区FA可包括沿列方向Y分布的弯折区BA，弯折区BA为可弯折的柔性结构，绑定部PA位于弯折区BA远离显示区AA的一侧。通过使弯折区BA弯折，可将引出区FA弯折至触控显示面板的背光侧，即与出光方向相反的一侧。从而可在触控显示面板的背光侧将柔性电路板与控制电路板连接。
当然，在本公开的其它实施方式中，引出区FA也可以不设置弯折 区BA，而通过将柔性电路板弯折，从而在触控显示面板的背光侧将柔性电路板与控制电路板连接。
如图2、图5、图6和图7所示，触控显示面板可包括触控层TSP和驱动芯片TIC，其中：
触控层TSP用于感应触控操作，以便触控显示面板显示指定图像，从而实现人机交互。
驱动芯片TIC具有至少一个触控引脚组PG和多个选通电路Mux，触控引脚组PG包括多个第一触控引脚P1，一触控引脚组PG的第一触控引脚P1包括多个功能引脚P1a和至少一个虚设引脚P1d；触控层TSP通过多个触控引线TL1与功能引脚P1a连接，从而与驱动芯片TIC连接；一功能引脚P1a至少与一触控引线TL1连接；驱动芯片TIC还可具有第二触控引脚P2，第二触控引脚P2可与绑定部PA连接。
第二触控引脚P2通过选通电路Mux与各第一触控引脚P1连接，且至少一个选通电路Mux连接的第一触控引脚P1均为虚设引脚P1d；
与功能引脚P1a连接的选通电路Mux用于依次导通第二触控引脚P2及其连接的各功能引脚P1a；与虚设引脚P1d连接的选通电路Mux关断。
本公开实施方式的触控显示面板，可通过第一触控引脚P1中的功能引脚P1a向显示区AA内的触控层TSP传输用于驱动触控层TSP感应触控操作的触控驱动信号，其中，通过选通电路Mux选择性的将第一触控引脚P1和第二触控引脚P2导通，可传输触控驱动信号，由此，通过对各个选通电路Mux的控制，可通过各个第一触控引脚P1中的功能引脚P1a向各个触控引线TL1传输触控驱动信号，实现对触控层TSP的扫描，以便感应触控操作。
在上述过程中，与功能引脚P1a连接的选通电路Mux为打开状态，可以分时导通第二触控引脚P2及其连接的功能引脚P1a，得到不同的传输路径，而虚设引脚P1d连接的选通电路Mux则可以设置为关闭状态，以便降低能耗。
下面对本公开的触控显示面板进行详细说明：
如图2所示，触控显示面板至少可包括驱动背板BP、发光器件LD 和触控层TSP，驱动背板BP用于驱动发光器件LD发光，发光器件LD可包括沿远离驱动背板BP的方向堆叠的第一电极ANO、发光层EL和第二电极CAT，其中：
驱动背板BP可包括用于驱动各发光器件LD独立发光的驱动电路，驱动电路可包括像素电路和外围电路，其中，像素电路的数量为多个，且至少部分像素电路可设于显示区AA内，当然，可以存在一部分像素电路的部分区域位于外围区WA。像素电路可包括多个晶体管，还可以包括电容，其可以是3T1C、7T1C等像素电路，nTmC表示一个像素电路包括n个晶体管(用字母“T”表示)和m个电容(用字母“C”表示)。像素电路阵列分布呈多行和多列，一像素电路可连接一个发光器件LD，当然，也可以存在一个像素电路连接多个发光器件LD的情况，本文仅以像素电路和发光器件LD一一对应的连接为例进行说明。
在本公开的一些实施方式中，如图4所示，像素电路可以是7T1C结构，其可具有7个晶体管和1个电容，即第一复位晶体管T1、补偿晶体管T2、驱动晶体管T3、写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6、第二复位晶体管T7以及存储电容Cst。
同时，为了便于向像素电路传输信号，驱动背板BP还可包括栅线、复位信号线、数据线和电源线等，其中，栅线和复位信号线的数量均为多个，且均沿行方向X穿过显示区AA，并延伸至外围区WA内，且一像素电路连接多个栅线和多个复位信号线。连接于同一像素电路的栅线可包括第一复位控制线、第二复位控制线、扫描线和发光控制线，连接于同一像素电路的复位信号线可包括第一复位信号线和第二复位信号线。
数据线和电源线均沿列方向Y穿过显示区AA，且延伸至外围区WA内。一列像素电路至少连接一个数据线和电源线。
第一复位晶体管T1的第一极与第一复位信号线连接，用于接收第一复位信号Vinit1，第二极与驱动晶体管T3的栅极和电容Cst的第一极板连接。
补偿晶体管T2的第一极与驱动晶体管T3的第二极连接，第二极与驱动晶体管T3的栅极连接。
写入晶体管T4的第一极与数据线连接，用于接收数据信号DA，第 二极与驱动晶体管T3的第一极连接。
第一发光控制晶体管T5的第一极和电容Cst的第二极板与电源线连接，用于接收第一电源信号VDD，第二极与驱动晶体管T3的第一极连接。
第二发光控制晶体管T6的第一极与驱动晶体管T3的第二极连接，第二极与一发光器件LD的第一电极ANO连接。
第二复位晶体管T7的第一极与第二复位信号线连接，用于接收第二复位信号Vinit2，第二极与第二发光控制晶体管T6的第二极连接。发光器件LD的第二电极CAT可接收第二电源信号VSS。
同时，为了控制各晶体管的导通和关断，第一复位晶体管T1的栅极与第一复位控制线连接，用于输入第一复位控制信号RE1，第二复位晶体管T7的栅极与第二复位控制线连接，用于输入第二复位控制信号RE2。补偿晶体管T2和写入晶体管T4的栅极与扫描线连接，用于输入扫描信号，第一发光控制晶体管T5和第二发光控制晶体管T6的栅极与发光控制线连接，用于输入发光控制信号EM。
上述像素电路的各晶体管均可以采用多晶体硅晶体管，即晶体管的沟道为多晶硅，例如P型低温多晶硅晶体管或N型低温多晶硅晶体管。当然，也可以采用金属氧化物晶体管，即晶体管的沟道为铟镓锌氧化物等金属氧化物。其中，P型低温多晶硅晶体管可在向其栅极输入高电平时关断，在输入低电平信号时导通；N型低温多晶硅晶体管可在向其栅极输入低电平时关断，在输入高电平信号时导通。金属氧化物晶体管可为N型金属氧化物晶体管，其可在栅极输入高电平时导通，低电平时关断。
在本公开的一些实施方式中，上述的7T1C的像素电路可采用LTPO(LTPS+Oxide)技术，具体而言，驱动晶体管T3、写入晶体管T4、第二复位晶体管T7、第一发光控制晶体管T5和第二发光控制晶体管T6可以采用P型低温多晶硅晶体管；第一复位晶体管T1和补偿晶体管T2则可以采用N型金属氧化物晶体管。由于P型低温多晶硅晶体管具有较高的载流子迁移率，从而有利于实现高分辨率、高反应速度、高像素密度、高开口率的显示面板，以便获得较高的载流子迁移率，提高响应速 度。同时，通过N型金属氧化物晶体管可降低漏电。
下面对上述像素电路的工作原理进行说明：
在复位阶段t1：通过第一复位控制信号RE1可使第一复位晶体管T1导通，向第一节点N1写入第一复位信号Vinit1。同时，通过第二复位控制信号RE2使第二复位晶体管T7导通，向第四节点N4写入第二复位信号Vinit2。由此，可对驱动晶体管T3的栅极和发光器件LD进行复位。
在写入阶段t2：通过第一扫描信号Gate1和第二扫描信号Gate2使写入晶体管T4和补偿晶体管T2导通，经过第三节点N3和第二节点N2向第一节点N1写入数据信号DA，直至电位达到Vdata+vth，其中Vdata为数据信号DA的电压，Vth为驱动晶体管T3的阈值电压。第一扫描信号Gate1和第二扫描信号Gate2可以是同一信号，也可以是同步的两个信号。此外，第一扫描信号Gate1和第二扫描信号Gate2可以是高频信号，有利于减小驱动晶体管T3的源极信号的负载。
在发光阶段t3：通过发光控制信号EM使第一发光控制晶体管T5和第二发光控制晶体管T6导通，驱动晶体管T3在电容Cst存储的电压Vdata+Vth和第二电源信号VDD的作用下导通，在第二电源信号VDD和第一电源信号VSS的作用下，发光器件LD发光。在此过程中，驱动晶体管T3的第一极作为源极，第二极作为漏极。
外围电路一方面可通过像素电路与发光器件LD连接，通过像素电路向发光器件LD的第一电极ANO施加第一电源信号VDD，另一方面，外围电路也可与发光器件LD的第二电极CAT连接，并向第二电极CAT施加第二电源信号VSS，通过控制像素电路可控制通过发光器件LD的电流，从而控制发光器件LD的亮度。外围电路可包括栅极驱动电路和发光控制电路等，当然，还可包括其它电路，在此不对外围电路的具体结构做特殊限定。
如图5所示，驱动背板BP还可包括位于外围区WA的总线，总线可由外围区WA穿过弯折区BA，延伸至引出区FA内，且与绑定部PA连接。其中，总线可包括沿沿远离显示区AA的方向间隔分布的复位信号总线、第一电源总线VDB和第二电源总线VSB。第一复位信号线和 第二复位信号线均与复位信号总线连接，用于接收第一复位信号和第二复位信号。电源线可与第一电源总线VDB连接，用于接收第一电源信号VDD，各发光器件LD的第二电极CAT可与第二电源总线VSB连接，用于接收第二电源总线号VSS。
在本公开的一些实施方式中，栅极驱动电路可包括多个级联的栅移位寄存器单元，可为多行像素电路提供复位控制信号和扫描信号，从而控制晶体管的打开时序，上述的扫描线、第一复位控制线和第二复位控制线均与栅极驱动电路连接。
举例而言，一栅移位寄存器单元可包括多个晶体管和电容，其可以是8T2C、10T2C或12T2C等，nTmC表示一个像素电路包括n个晶体管(用字母“T”表示)和m个电容(用字母“C”表示)，在此不对其具体结构做特殊限定。
多个栅移位寄存器单元级联，第一级栅移位寄存器单元中的输入晶体管的第一极和输入端连接，输入端用于接收触发信号作为输入信号，而其它各级栅移位寄存器单元中的输入端和上一级栅移位寄存器单元的输出端电连接，以接收上一级栅移位寄存器单元输出的输出信号作为输入信号，由此实现移位输出，以用于对显示区AA的像素电路进行逐行扫描。
此外，如图3和图10所示，为了便于控制栅移位寄存器单元，驱动背板BP还可包括位于外围区WA的外围引线GL，至少部分外围引线GL可穿过弯折区BA延伸至引出区FA内，并连接外围电路和驱动芯片TIC。
外围引线GL可包括与栅移位寄存器单元连接的驱动电源线、触发信号线和时钟信号线等，举例而言，驱动电源线包括用于向栅移位寄存器单元提供电源的第一驱动电源线和第二驱动电源线，触发信号线用于提供上述的触发信号。时钟信号线可包括第一时钟信号线和第二时钟信号线，用于控制至少部分晶体管的导通时序。栅极驱动电路的结构和具体工作原理在此不做特殊限定。
发光控制电路可包括沿列方向Y级联的多个发光移位寄存器单元，发光移位寄存器单元的结构和工作原理与栅移位寄存器单元相似，其可 控制各行像素电路的发光控制晶体管依次导通和关断。例如，发光移位寄存器单元可与发光控制线连接，向发光控制线输出发光控制信号EM。在本公开的一些实施方式中，发光移位寄存器单元可与两行像素电路所连接的发光控制线连接。相应的，发光移位寄存器单元也可以与多个外围引线GL连接，这些外围引线GL可包括驱动电源线、触发信号线和时钟信号线等，在此不再详述其连接关系。
当然，在本公开的一些实施方式中，像素电路可以不包括发光控制晶体管，相应的，外围电路也可以不包括发光控制电路。
至少部分外围引线GL可与驱动芯片TIC连接，以便接收控制外围电路的信号。
如图2所示，基于上文的7T1C的像素电路，在本公开的一实施方式中，驱动背板BP可包括衬底SU、第一半导体层POL、第一栅绝缘层GI1、第一栅极层GA1、第一绝缘层IL0、第二栅极层GA2、第二绝缘层IL1，第二半导体层IGL、第二栅绝缘层GI2、第三栅极层GA3、第三绝缘层IL2、第一源漏层SD1、第一平坦层PLN1、第二源漏层SD2、第二平坦层PLN2，其中：
衬底SU可为驱动背板BP的基底，其可承载像素电路和外围电路，衬底SU可为硬质或柔性结构，其可以是单层或多层结构，在此不做特殊限定。
第一半导体层POL可设于衬底SU一侧，且包括像素电路中的驱动晶体管T3、写入晶体管T4、第二复位晶体管T7、第一发光控制晶体管T5和第二发光控制晶体管T6的沟道。第一半导体层POL的材料可以是多晶硅。
第一栅绝缘层GI1可覆盖第一半导体层POL，第一栅绝缘层GI1的材料可以是氮化硅、氧化硅等绝缘材料。
第一栅极层GA1可设于第一栅绝缘层GI1远离衬底SU的表面，且包括电容的第一极板。
第一绝缘层IL0可覆盖第一栅极层GA1，其材料可以是氮化硅、氧化硅等绝缘材料。
第二栅极层GA2可设于第一绝缘层IL0远离衬底SU的表面，且包 括电容的第二极板。
第二绝缘层IL1覆盖第二栅极层GA2，其可以是单层或多层结构，且材料可以包括氮化硅、氧化硅等无机绝缘材料，也可以包括绝缘树脂等有机绝缘材料。
第二半导体层IGL可设于第二绝缘层IL1远离衬底SU的表面，且包括第一复位晶体管T1和补偿晶体管T2的沟道。第二半导体层IGL的材料可包括铟镓锌氧化物(IGZO)等半导体金属氧化物。
第二栅绝缘层GI2可覆盖第二半导体层IGL，其材料可以是氮化硅、氧化硅等绝缘材料。
第三栅极层GA3可设于第二栅绝缘层GI2远离衬底SU的表面。
第三绝缘层IL2可覆盖第三栅极层GA3，其可以是单层或多层结构，且材料可以包括氮化硅、氧化硅等无机绝缘材料，也可以包括绝缘树脂等有机绝缘材料。例如，第三绝缘层IL2可包括沿远离衬底SU的方向依次堆叠的介电层和多层无机绝缘层。
第一源漏层SD1可设于第三绝缘层IL2远离衬底SU的表面。
第一平坦层PLN1可设于第一源漏层SD1远离衬底SU的一侧，其材料可以是树脂等绝缘材料。举例而言，可利用氮化硅等绝缘材料的钝化层覆盖第一源漏层SD1，再用第一平坦层PLN1覆盖该钝化层。
第二源漏层SD2可设于第一平坦层PLN1远离衬底SU的表面。
第二平坦层PLN2可覆盖第二源漏层SD2，其材料可以是树脂等绝缘材料。发光器件LD可设于的第二平坦层PLN2远离衬底SU的一侧。
此外，如图2所示，在衬底SU和第一半导体层POL之间，还可设置遮光层BSM，其可采用遮光的金属或其它材料，且可以是单层或多层结构。遮光层BSM的至少部分区域可与至少部分晶体管的沟道区交叠，以遮蔽照射向晶体管的光线，使得晶体管的电学特性稳定，例如，遮光层BSM可包括多个阵列分布的遮光单元，一遮光单元可遮挡一驱动晶体管T3的沟道。同时，可通过遮光线将各遮光单元连接起来，使遮光层BSM为一体结构，并向遮光层BSM输入第二电源信号VSS或第二电源信号VDD，以便通过遮光层BSM起到静电屏蔽的作用。
进一步的，如图2所示，可通过绝缘的缓冲层BUF覆盖遮光层BSM， 第一半导体层POL可设于缓冲层BUF背离衬底SU的表面。缓冲层BUF可以是单层或多层结构，其材料可以包括氮化硅、氧化硅等绝缘材料。
下面对发光器件LD进行详细说明：
如图2所示，发光器件LD的数量可以有多个，且每个发光器件LD可连接一个像素电路，同一像素电路可以连接一个或多个发光器件LD。该发光器件LD可以是OLED(有机发光二极管)、QLED(量子点发光二极管)、Micro LED或Mini LED等，其可以包括第一电极ANO、第二电极CAT和位于第一电极ANO和第二电极CAT间的发光层EL，其中：
第一电极ANO可设于驱动背板BP一侧，例如第二平坦层PLN2远离衬底SU的表面。发光层EL可包括沿远离驱动背板BP的方向层叠的空穴注入层、空穴传输层、发光材料层、电子传输层和电子注入层。各个发光器件LD可共用第二电极CAT，也就是说，第二电极CAT可以是连续的整层结构，且第二电极CAT可延伸至外围区WA，并可与第二电源总线VSB连接，以便接收第二电源信号VSS，第一电极ANO则阵列分布，确保各发光器件LD可以独立发光。此外，为了限定发光器件LD的发光范围，防止串扰，可在设置第一电极ANO的表面设置像素定义层PDL，其可设有露出各第一电极ANO的开口，发光层EL在开口内与第一电极ANO层叠。
各发光器件LD可至少共用发光材料层，使得各发光器件LD的发光颜色相同，此时，为了实现彩色显示，可在发光器件LD远离衬底SU的一侧设置彩膜层，通过彩膜层中与各发光器件LD对应的滤光部，实现彩色显示。当然，各个发光器件LD的发光材料层也可以是独立的，使得发光器件LD可以直接发出单色光，且不同发光器件LD的发光颜色可以不同，从而实现彩色显示。
此外，如图2所示，显示面板还可以包括封装层TFE，其可覆盖发光器件LD，用于保护发光器件LD，阻隔外界的水、氧对发光器件LD造成侵蚀。举例而言，封装层TFE可采用薄膜封装的方式实现封装，其可包括第一无机层、有机层和第二无机层，其中，第一无机层覆盖于发 光器件LD，有机层可设于第一无机层背离驱动背板BP的表面，且有机层的边界限定于第一无机层的边界的内侧，有机层在驱动背板BP上的正投影的边界可位于外围区WA，确保有机层能覆盖各发光器件LD。第二无机层可覆盖有机层和未被有机层覆盖的第一无机层，可通过第二无机层阻挡水氧侵入，通过具有柔性的有机层实现平坦化。
如图2所示，触控层TSP可设于发光器件LD远离驱动背板BP的一侧，例如，触控层TSP可设于封装层TFE远离驱动背板BP的表面，其可采用电容触控结构，包括自容结构和互容结构。以自容式结构为例：
如图3所示，触控层TSP可包括多个位于显示区AA的触控电极TMB，各个触控电极TMB阵列分布，且相互间隔设置。每个触控电极TMB与地构成自电容，当用户的手指触摸时，手指的电容会叠加到触控电极TMB的自电容上，使得电容量增加，从而可通过检测触控电极TMB的电容量的变化，确定出触摸点的位置，即触控点对应的触控电极TMB的位置。
各个触控电极TMB可通过触控引线TL1与驱动芯片TIC连接，例如，一个触控电极TMB可与一个触控引线TL1连接，各个触控引线TL1均由显示区AA延伸至引出区FA，并与驱动芯片TIC的功能引脚P1a连接，以便向触控电极TMB施加触控驱动信号，并接收基于电容变化而产生的触控感应信号。
进一步的，为了提高透光率，触控电极TMB可以呈网状结构，发光器件可与网状结构的网孔对应，从而减小触控电极TMB对光线的遮挡。
此外，如图2所示，触控层TSP还可包括缓冲层TBU和保护层TOC，缓冲层TBU可作为触控层TSP的基底，其可设于封装层TFE远离衬底SU的表面，其材料可包括氮化硅、氧化硅等绝缘材料。保护层TOC可覆盖触控电极TMB，保护层TOC的其材料可以是聚酰亚胺(PI)或光学胶等透明绝缘材料。
此外，在本公开的其它实施方式中，触控层TSP还可采用互容结构，在此不对其结构进行特殊限定。
下面对驱动芯片TIC进行详细说明：
如图5-图7所示，驱动芯片TIC可堆叠于驱动背板BP的引出区FA上，且位于弯折区BA和绑定部PA之间，且与绑定部PA连接。驱动芯片TIC可以用于向触控层TSP输出触控驱动信号，以及接收触控感应信号，以实现触控功能。同时，驱动芯片TIC还可用于通过驱动电路驱动发光器件LD发光，以显示图像，实现显示和触控功能的集成。当然，驱动芯片TIC也可以仅用于实现触控功能，而显示图像则可以通过其它芯片来实现。
驱动芯片TIC具有至少一个触控引脚组PG和多个选通电路Mux，触控引脚组PG可包括多个第一触控引脚P1，部分一触控引脚P1为功能引脚P1a，部分第一触控引脚P1为虚设引脚P1d。其中，触控引脚组PG的每个功能引脚P1a与一触控引线TL1连接，例如，可通过一个连接走线TL3连接一个触控引线TL1和一个功能引脚P1a，且一个连接走线TL3可与其连接的触控引线TL1为一体结构，当然，二者也可以是通过连接工艺连接的独立结构。如图5和图11所示，连接走线TL3可与驱动芯片TIC交叠。
驱动芯片TIC还具有第二触控引脚P2，第二触控引脚P2可通过选通电路Mux与第一触控引脚P1连接，同时，第二触控引脚P2可与绑定部PA的部分引脚连接，并可通过柔性电路板连接绑定部PA和控制电路板连接，从而以便传输触控驱动信号。选通电路Mux可以是集成于驱动芯片TIC的内部电路的一部分。一触控引脚组PG的第一触控引脚P1可通过一选通电路Mux与一第二触控引脚P2连接，且不同的选通电路Mux连接的第二触控引脚P2可以不同。
举例而言：如图7所示，一个第二触控引脚P2通过一选通电路Mux可与多个第一触控引脚P1连接。同时，绑定部PA的引脚包括绑定引脚PA1，第二触控引脚P2可与绑定引脚PA1连接，二者可以一一对连接的。
需要说明的是，图7是为了说明第一触控引脚P1、选通电路Mux和第二触控引脚P2的连接关系的原理图，并不构成对驱动芯片TIC的实际结构的限定。
在本公开的一些实施方式中，驱动芯片TIC可包括沿行方向X分布的两个触控端TIC1和沿列方向Y分布的第一引脚端TIC2和第二引脚端TIC3，第二引脚端TIC3位于第一引脚端TIC2靠近绑定部PA的一侧。
一触控引脚组PG可位于一触控端TIC1，若触控引脚组PG为两个，则分别位于两个触控端TIC1，且两个触控端TIC1的触控引脚组PG可以关于驱动芯片TIC沿列方向Y上中轴线对称设置。
如图5和图8所示，第一引脚端TIC2还可设有多个显示引脚P3，驱动发光器件LD发光的驱动电路可与至少部分显示引脚P3连接，以便在驱动芯片TIC的控制下，驱动发光器件LD发光。显示引脚P3可沿行方向X分为两个显示引脚组，该两个显示引脚组可关于驱动芯片TIC沿列方向Y上中轴线对称设置，虚设触控引脚Pd位于两个显示引脚组之间。第二触控引脚P2可位于第二引脚端TIC3。
第一引脚端TIC2可具有多个虚设触控引脚Pd，且虚设触控引脚Pd可沿行方向X分布，虚设触控引脚Pd可位于两显示引脚组之间。各触控引线TL1分别与各虚设触控引脚Pd连接，例如，触控引线TL1与虚设触控引脚Pd可以是一一对应的连接。虚设触控引脚Pd为浮接状态，不传输信号，有利于提高第一引脚端TIC1与驱动背板BP连接的均一性。当然，虚设触控引脚Pd也可以不与触控引线TL1连接。
发明人发现，对于一个驱动芯片TIC而言，其选通电路Mux的数量以及所有选通电路Mux所能控制的第一触控引脚P1的总数是固定的，若实现触控功能所需的第一触控引脚P1的数量少于选通电路Mux所能控制的引脚的总数，则部分第一触控引脚P1需要传输触控驱动信号，这些第一触控引脚P1即为功能引脚P1a；而还有一部分第一触控引脚P1无需传输触控驱动信号，也无需与触控引线TL1连接，这些第一触控引脚P1即为虚设引脚P1d。若每个选通电路Mux均连接虚设引脚P1d和功能引脚P1a，则每个选通电路Mux都需要打开，但又不用通过虚设引脚P1d传输信号，不利于降低能耗。
为了解决上述的问题，本公开对选通电路Mux和第一触控引脚P1的连接方式进行了设计，如图6和图7所示，使至少一个选通电路Mux 连接的第一触控引脚P1均为虚设引脚P1d，对于连接的第一触控引脚P1均为虚设引脚P1d的选通电路Mux而言，由于没有信号传输的需求，因而可将该选通电路Mux关断，仅使连接功能引脚P1a的选通电路Mux工作，从而在不影响触控功能的前提下，降低功耗。具体来说：
在实现触控功能时，与功能引脚P1a连接的选通电路Mux可用于依次导通第二触控引脚P2及其连接的各功能引脚P1a，即连通功能引脚P1a和第二触控引脚P2，以向触控引线TL1传输触控驱动信号，对触控层TSP进行驱动。同时，与虚设引脚P1d连接的选通电路Mux保持关断状态，虚设引脚P1d浮接，且不用接收控制信号，将连接虚设引脚P1d的选通电路Mux关闭，并不会影响触控功能，且可以降低功耗。
下面对第一触控引脚P1中功能引脚P1a和虚设引脚P1d的排布方式进行示例性说明：
为了便于描述，可对触控引脚组PG的第一触控引脚P1进行划分，得到多个引脚单元PU，每个引脚单元PU包括多个功能引脚P1a和至少一个虚设引脚P1d。选通电路可包括多个第一选通电路Mux1和至少一个第二选通电路Mux2。每个第一选通电路Mux1可同时与多个引脚单元PU中的第一触控引脚P1连接，且每个引脚单元PU内的一功能引脚P1a与一第一选通电路Mux1连接；一引脚单元PU内的一虚设引脚P1d与一第二选通电路Mux2连接。也就是说，每个第一选通电路Mux1所连接的功能引脚P1a可来自不同的引脚单元PU，每个第二选通电路Mux2所连接的虚设引脚P1d也来自不同的引脚单元PU，从而可使第一选通电路Mux1连接的第一触控引脚P1均为功能引脚P1a，第二选通电路Mux2连接的第一触控引脚P1均为虚设引脚P1d。
在本公开的一些实施方式中，在同一触控引脚组PG中的第一触控引脚P1可沿列方向Y间隔分布，且任一引脚单元PU在列方向Y上的最后一个第一触控引脚P1为虚设引脚P1d。举例而言：
如图6和图7所示，在一实施方式中，一触控引脚组PG中一个引脚单元PU中的虚设引脚P1d的数量为1个。在列方向Y上，每个引脚单元PU距离绑定部PA最近的一个第一触控引脚P1为虚设引脚P1d，若将每个引脚单元PU中的功能引脚P1a视为一个引脚子单元，则在列 方向Y上，各引脚子单元与虚设引脚P1d交替分布。每个引脚单元PU中的功能引脚P1a的数量可以是3个，连接同一触控引脚组PG的第一触控引脚P1的选通电路Mux的数量可以是4个。在该实施方式中，触控功能在一个触控端TIC1所需的功能引脚P1a的数量小于该触控端TIC1的第一触控引脚P1的总数的3/4，且大于1/2。
在一实施方式中，一触控引脚组PG中一个引脚单元PU中的虚设引脚P1d的数量为2个。在列方向Y上，每个引脚单元PU距离绑定部PA最近的一个第一触控引脚P1为该虚设引脚P1d，若将每个引脚单元PU中的功能引脚P1a视为一个引脚子单元，则在列方向Y上，各引脚子单元与虚设引脚P1d交替分布。每个引脚单元PU中的功能引脚P1a的数量可以是3个，连接同一触控引脚组PG的第一触控引脚P1的选通电路Mux的数量可以是4个。在该实施方式中，实现触控功能在一个触控端TIC1所需的功能引脚P1a的数量小于该触控端TIC1的第一触控引脚P1的总数1/2。
在本公开的另一些实施方式中，一触控引脚组PG的第一触控引脚P1可包括多个引脚单元PU，至少部分引脚单元PU中仅包括功能引脚P1a，还有至少部分引脚单元PU中仅包括虚设引脚P1d；一引脚单元PU中的第一触控引脚P1连接与同一选通电路Mux连接。也就是说，第一选通电路Mux1连接的第一触控引脚P1均来自同一引脚单元PU，且均为功能引脚P1a。第二选通电路Mux2连接的第一触控引脚P1均来自同一引脚单元PU，且均为虚设引脚P1d。各个引脚单元PU可沿列方向Y分布。
当然，在本公开的其它实施方式中，一触控引脚组PG中的第一触控引脚P1可以采用其它方式分布，只要能使第二选通电路Mux2连接的均为虚设引脚P1d即可。
进一步的，如图6和图7所示，同一触控引脚组PG中的第一触控引脚P1可排成沿行方向X分布的多列，且相邻两列第一触控引脚P1在列方向Y上交替间隔分布，也就是说，相邻两列第一触控引脚P1沿列方向Y可以错开设置。同时，各虚设引脚P1d可位于同一列。举例而言，同一触控引脚组PG中的第一触控引脚P1可沿行方向X排成两列，且虚 设引脚P1d位于远离驱动芯片TIC的中心的一列，即位于外侧的一列。
在本公开的一些实施方式中，为了便于对触控层TSP进行测试，驱动芯片TIC还可具有第一测试引脚Pt，绑定部PA可具有多个第二测试引脚PA2，第二测试引脚PA2可与绑定引脚PA1沿行方向X间隔分布。同时，触控显示面板还包括多个测试线TL2，一连接走线TL3可通过一测试线TL2与一第二测试引脚PA2连接，由于连接走线TL3与功能引脚P1a连接，因而测试线TL2相应的还与功能引脚P1a连接；一第一测试引脚Pt可通过一测试线TL2与一第二测试引脚PA2连接，同时，一连接走线TL3可与一测试线TL2连接，相应的，一测试线TL2与一功能引脚P1a连接。
第一测试引脚Pt位于触控端TIC1，且与第一触控引脚P1间隔分布，第一测试引脚Pt连接的至少部分测试线TL2可用于接地，当然，还可以包括用于接入测试信号等其它信号的测试线TL2。
如图5、图6、图10和图11所示，在一些实施方式中，两个触控端TIC1均具有第一测试引脚Pt，且两触控端TIC1的第一测试引脚Pt对称分布，可通过测试连接线TL5将分别属于两个触控端TIC1的两第一测试引脚Pt连接，以便传输接地信号或其它信号。驱动芯片TIC可与测试连接线TL5交叠。
如图6所示，由于触控端TIC1能实现接地的引脚有限，因而可通过接地连接线TL4连接两个或更多个与测试线TL2，这些测试线TL2中只要有一个连接了能实现接地功能的引脚，就可以实现多个测试线TL2的接地。接地连接线TL4可沿列方向Y延伸，从而可与多个测试线TL2交叉，为了避免短路，可使测试线TL2为多层结构，接地连接线TL4可与其中一层同层设置，可与其它层交叉。
举例而言：如图6所示，第一测试引脚Pt1可以实现接地功能的引脚，而第一测试引脚Pt2则无法实现接地功能的引脚，但第一测试引脚Pt1和第一测试引脚Pt2连接的测试线TL2都需要接地，因此，可利用接地连接线TL4将第一测试引脚Pt1和第一测试引脚Pt2连接的两个测试线TL2连接起来，使得该两个测试线TL2都可以实现接地功能。同时，由于接地连接线TL4沿列方向Y延伸，并与多个测试线TL2交叉，但 其需要与两个测试线TL2连接，因此，可使与接地连接线TL4交叉的测试线TL2至少分为位于不同层的第一段TL21和第二段TL22，第一段TL21可与第二段TL22不同层并交叉，第一段T21可与连接走线TL3或第一测试引脚Pt连接，第二段T22可通过接触孔与第一段T21连接，并与第二测试引脚PA2连接。例如，第一段TL21、连接走线TL3和接地连接线TL4同层设置于第一栅极层GA1，第二段TL22设于第一源漏层SD1；接地连接线TL4与第二段TL22交叉但不同层，并可通过接触孔分别与两个测试线TL2连接。
绑定部PA中的引脚并非全部与柔性电路板绑定，绑定引脚PA1可与柔性电路板绑定，而第二测试引脚PA2不与柔性电路板绑定，仅作测试触控功能的用途。
此外，如图5所示，为了支撑驱动芯片TIC，在驱动芯片TIC靠近驱动背板BP的一侧设置支撑凸块Bum，用于支撑驱动芯片TIC。
针对上述驱动背板BP、驱动芯片TIC及其引脚，本公开还针对连接部分引脚的引线在引出区FA的路径提出了新的方案，下面进行示例性说明：
如图5、图8-图10在本公开的一些实施方式中，为了适应驱动芯片TIC的显示引脚P3和虚设触控引脚Pd的位置，且便于走线，在引出区FA中，可使触控引线TL1和外围引线GL在局部交叉。举例而言：
如图5、图8和图9所示，触控引线TL1在引出区FA内的部分可包括沿列方向Y分布的两个触控引出段TL11、两个触控过渡段TL12和一个触控连接段TL13，触控引出段TL11、触控过渡段TL12和触控连接段TL13均包括多个触控引线TL1在引出区FA内的部分，也就是说，触控引出段TL11、触控过渡段TL12和触控连接段TL13均为多个触控引线TL1在引出区FA内的区域的集合，而不是特指具体的一个触控引线TL1。其中：触控引出段TL11与触控引线TL1位于外围区WA的部分连接，且两触控引出段TL11沿行方向X间隔分布；触控连接段TL13与各连接走线TL3连接，例如，触控连接段TL13的各触控引线TL1可与各连接走线TL3一一对应的连接，从而与各功能引脚P1a一一对应连接。相应的，触控连接段TL13可与虚设触控引脚Pd连接。同时，一触 控引出段TL11通过一触控过渡段TL12与触控连接段TL13连接，且触控连接段TL13位于两触控引出段TL11之间。触控引出段TL11和触控连接段TL13均沿列方向Y延伸，触控过渡段TL12的延伸方向与行方向X和列方向Y不同，从而相对于行方向X和列方向Y倾斜设置，两触控过渡段TL12的夹角可为锐角，当然，也可以是直角或钝角。进一步的，两个触控引出段TL11可关于驱动芯片TIC沿列方向Y的中轴线对称，两个触控过渡段TL12可关于驱动芯片TIC沿列方向Y的中轴线对称。
如图9所示，通过上述对触控引线TL1在引出区FA内的部分进行分段的方案，可使触控引线TL1在引出区FA内的部分呈“Y”形延伸，触控引线TL1在进入引出区FA时分为两个触控引出段TL11，经两个触控过渡段TL12连接后，汇聚于触控连接段TL13，并与各连接走线TL3连接。
同时，如图5、图8和图10所示，外围引线GL可由外围区WA延伸至引出区FA，且在外围区WA与外围电路连接，在引出区FA通过部分显示引脚P3与驱动芯片TIC连接。外围引线GL与触控引线TL1位于不同层，例如，触控引线TL1可位于触控层TSP，外围引线GL可位于驱动背板BP中。
外围引线GL在引出区FA内的部分可分为沿行方向X分布的两个外围线组GL1，一外围线组GL1可包括沿列方向Y分布的显示引出段GL11、显示过渡段GL12和第一显示延伸段GL13；其中：显示过渡段GL12可连接于显示引出段GL11和第一显示延伸段GL13之间；显示引出段GL11与外围引线位于外围区WA的部分连接，第一显示延伸段GL13与部分显示引脚P3连接；显示引出段GL11和第一显示延伸段GL13均沿列方向Y延伸，显示过渡段GL12的延伸方向与行方向X和列方向Y不同,从而相对于行方向X和列方向Y倾斜设置，两触控过渡段TL12的夹角可为锐角，当然，也可以是直角或钝角。进一步的，两个外围线组GL1可关于驱动芯片TIC沿列方向Y的中轴线对称。
如图5和图8所示，两个显示引出段GL11位于两触控引出段TL11之间，触控过渡段TL12和显示过渡段GL12一一对应的交叉，但由于触 控过渡段TL12和显示过渡段GL12不在同一层，因而不连接。两个显示引出段GL11位于两触控引出段TL11之间，触控连接段TL13位于两显示连接段GL15之间。
此外，如图5、图8和图10所示，外围线组GL1还包括第二显示延伸段GL14和显示连接段GL15，第二显示延伸段GL14可沿行方向X延伸，且与第一显示延伸段GL13远离显示区AA的一端连接，第二显示延伸段GL14可沿行方向X朝远离触控连接段TL13的方向延伸。显示连接段GL15沿列方向Y延伸，且位于两数据线组DAL1的外侧，并与部分显示引脚P3连接。
如图5、图8-图10所示，上文中的第一电源总线VDB可设于外围区WA，并延伸至引出区FA，且与绑定部PA连接，用于传输第一电源信号。第一电源总线VDB、触控引线TL1和外围引线GL均位于不同层，且触控引线TL1位于第一电源总线VDB远离外围引线GL的一侧。
电源线可沿列方向Y延伸，且由显示区AA延伸至外围区WA，并与第一电源总线VDB连接，一列电源线与至少一列像素电路连接。
第一电源总线VDB位于引出区FA的部分包括屏蔽部VDB1和连接部VDB2，屏蔽部VDB1与第一电源总线VDB位于外围区WA的部分连接，连接部VDB2连接屏蔽部VDB1与绑定部PA，以便接收第一电源信号。触控引出段TL11、触控过渡段TL12、显示引出段GL11和显示过渡段GL12均与屏蔽部VDB1至少部分交叠，由于第一电源信号为恒定的信号，从而可通过屏蔽部VDB1防止外围引线中的信号对触控引线TL1中的信号造成干扰。为了提高屏蔽效果，触控引出段TL11、触控过渡段TL12、显示引出段GL11和显示过渡段GL12在衬底SU上的正投影均位于屏蔽部VDB1在衬底SU上的正投影以内。
进一步的，连接部VDB2的数量为两个，且连接于屏蔽部VDB1在行方向X上的两端，驱动芯片TIC位于两个连接部VDB2之间，且屏蔽部VDB1位于驱动芯片TIC远离绑定部PA的一侧。
外围线组GL1还可包括第三显示延伸段GL16，其一端与第二显示延伸段GL14远离第一显示延伸段GL13的一端连接，并可沿行方向X 远离第一显示延伸段GL13延伸，同时，第三显示延伸段GL16可与连接部VDB2和第二电源总线VSB位于引出区FA的部分交叠，且第三显示延伸段GL16与连接部VDB2和第二电源总线VSB位于引出区FA的部分位于不同层。
在本公开的一些实施方式中，数据线DAL可沿列方向Y延伸，且由显示区AA延伸至引出区FA，并与部分显示引脚P3连接，一列数据线DAL与至少一列像素电路连接，用于传输数据信号。数据线DAL位于引出区FA的部分可包括沿行方向X分布的两个数据线组DAL1，触控引出段TL11、触控过渡段TL12、触控连接段TL13、显示引出段GL11和显示过渡段GL12和显示连接段GL15均位于两数据线组DAL1之间。
数据线组DAL1、第一电源总线VDB与触控引线TL1均位于不同层，且触控引线TL1位于第一电源总线VDB远离触控引线组的一侧。同时，数据线组DAL1与屏蔽部VDB1至少部分交叠，使得屏蔽部VDB1可防止数据线DAL的数据信号对触控引线TL1中的信号造成干扰。第二显示延伸段GL14与数据线组DAL1交叉且位于不同层。
基于上述的走线，第一引脚端TIC2的两个显示引脚P3组的显示引脚P3均包括第一显示引脚P31和第二显示引脚P32，外围引线GL通过第一显示引脚P31与驱动芯片TIC连接，数据线DAL可通过第二显示引脚P32与驱动芯片TIC连接。
在一显示引脚P3组中，第一显示引脚P31可沿行方向X位于第二显示引脚P32远离虚设触控引脚Pd的一侧。两个显示引脚P3组显示引脚P3可关于驱动芯片TIC沿列方向Y的中轴线对称。
此外，第二电源总线VSB由外围区WA延伸至引出区FA，且位于第一电源总线VDB远离显示区AA的一侧，即位于第一电源总线VDB的外侧，位于引出区FA的第二电源总线VSB可与绑定部PA的部分引脚连接。
此外，如图6所示，触控连接线TL2可包括位于不同层的第一段TL21 和第二段TL22，第一段TL21与功能引脚P1a连接，第二段TL22连接第一段TL21和绑定部PA，且第一段TL21和第二段TL22通过接触孔连接。
下面以上文中列举的驱动背板的各膜层为例，对部分走线所处的膜层进行说明：
如图2、图5-图10所示，对于第一电源总线VDB、第二电源总线VSB、电源线、数据线DAL、外围引线GL和触控引线TL1中的任意一个而言，其位于外围区WA的部分和位于引出区FA的部分可以位于同一膜层，也可以位于不同膜层。同时，位于引出区FA内的部分也可以由位于不同的膜层的线段连接而成。举例而言：
第一电源总线VDB和第二电源总线VSB位于引出区FA的部分可位于第一栅极层GA1、第二栅极层GA2和第三栅极层GA3中的至少一个。
电源线和数据线DAL位于显示区AA和外围区WA的部分可位于第一源漏层SD1和第二源漏层SD2中的至少一个，数据线DAL位于引出区FA的部分可位于第一栅极层GA1、第二栅极层GA2和第三栅极层GA3中的至少一个。
外围引线GL位于引出区FA的部分可位于第一栅极层GA1、第二栅极层GA2和第三栅极层GA3中的至少一个，且外围引线GL在引出区FA的部分的局部可与数据线DAL位于引出区FA的部分位于同一层。例如：显示引出段GL11、显示过渡段GL12、第一显示延伸段GL13和显示连接段GL15和第三显示延伸段GL16可与数据线DAL位于引出区FA的部分位于第一栅极层GA1，第二显示延伸段GL14则可以位于第一源漏层SD1，使得第二显示延伸段GL14与数据线DAL位于引出区FA的部分交叉但部连接。
触控引线TL1可与触控电极TMB位于同一层。
本公开还提供一种显示装置，该显示装置可包括上述任意实施方式的触控显示面板。该触控显示面板为上述任意实施方式的触控显示面板， 其具体结构和有益效果可参考上文中显示面板的实施方式，在此不再赘述。本公开的显示装置可以是手机、智能手表、智能手环、平板电脑、电视等具有显示功能的电子设备，在此不再一一列举。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (18)

  1. 一种触控显示面板，所述触控显示面板具有显示区、外围区和引出区，所述外围区位于所述显示区外，所述引出区沿列方向设置于所述外围区外，且所述引出区具有用于与柔性电路板连接的绑定部；
    所述触控显示面板包括：
    触控层；
    驱动芯片，具有至少一个触控引脚组和多个选通电路，所述触控引脚组包括多个第一触控引脚，一所述触控引脚组的第一触控引脚包括多个功能引脚和至少一个虚设引脚；所述触控层通过多个触控引线与各所述功能引脚连接，且一所述功能引脚至少与一所述触控引线连接；所述驱动芯片还具有与所述绑定部连接的第二触控引脚；
    所述第二触控引脚通过所述选通电路与各所述第一触控引脚连接；至少一个所述选通电路连接的所述第一触控引脚均为所述虚设引脚；
    与所述功能引脚连接的选通电路用于依次导通所述第二触控引脚及其连接的各所述功能引脚；与所述虚设引脚连接的选通电路关断。
  2. 根据权利要求1所述的触控显示面板，其中，一所述触控引脚组的第一触控引脚包括多个引脚单元，每个所述引脚单元包括多个所述功能引脚和至少一个所述虚设引脚；所述选通电路包括第一选通电路和第二选通电路；
    一所述选通电路同时与多个所述引脚单元中的第一触控引脚连接，且每个所述引脚单元内的一所述功能引脚与一所述第一选通电路连接，同一所述引脚单元中的至少两个所述功能引脚所连接的第一选通电路不同；一所述引脚单元内的一所述虚设引脚与一所述第二选通电路连接。
  3. 根据权利要求2所述的触控显示面板，其中，同一所述触控引脚组中的第一触控引脚沿所述列方向间隔分布，且任一所述引脚单元在所述列方向上的最后一个第一触控引脚为所述虚设引脚。
  4. 根据权利要求3所述的触控显示面板，其中，同一所述触控引脚组中的第一触控引脚排成沿行方向分布的多列，且相邻两列所述第一触控引脚在所述列方向上交替间隔分布；所述虚设引脚位于同一列。
  5. 根据权利要求4所述的触控显示面板，其中，所述触控引脚组的 数量为两个，且位于所述驱动芯片在所述行方向上的两端。
  6. 根据权利要求1所述的触控显示面板，其中，一所述触控引脚组的第一触控引脚包括多个引脚单元，至少部分所述引脚单元中仅包括所述功能引脚，至少部分所述引脚单元中仅包括所述虚设引脚；一所述引脚单元中的第一触控引脚与同一所述选通电路连接。
  7. 根据权利要求1-6任一项所述的触控显示面板，其中，所述引出区还包括沿行方向延伸的弯折区，所述绑定部位于所述弯折区远离所述显示区的一侧；
    所述驱动芯片设于所述引出区内，且位于所述弯折区和所述绑定部之间。
  8. 根据权利要求1所述的触控显示面板，其中，所述驱动芯片包括沿行方向分布的两个触控端和沿所述列方向分布的第一引脚端和第二引脚端；所述触控引脚组位于所述触控端；所述第二引脚端位于所述第一引脚端靠近所述绑定部的一侧，所述第二触控引脚位于所述第二引脚端；
    所述第一引脚端具有多个显示引脚；一所述触控引线通过一连接走线与一所述功能引脚连接；所述驱动芯片与所述连接走线至少部分交叠；
    所述触控显示面板还包括：
    多个发光器件，设于所述显示区；
    驱动背板，用于驱动所述发光器件发光，且包括像素电路、外围电路和外围引线，所述像素电路位于所述显示区，所述外围电路位于所述外围区，所述外围引线由所述外围区延伸至所述引出区，且与所述外围电路连接，并通过部分所述显示引脚与所述驱动芯片连接；所述外围引线与所述触控引线位于不同层；
    所述触控层设于所述发光器件远离所述驱动背板的一侧。
  9. 根据权利要求8所述的触控显示面板，其中，所述触控引线在所述引出区的部分包括沿所述列方向分布的两个触控引出段、两个触控过渡段和一个触控连接段；所述触控引出段与所述触控引线位于外围区的部分连接，所述触控连接段通过所述连接走线与所述功能引脚连接，一所述触控引出段通过一所述触控过渡段与所述触控连接段连接，且所述触控连接段位于两所述触控引出段之间；所述触控引出段和所述触控连 接段均沿所述列方向延伸，所述触控过渡段的延伸方向与所述行方向和列方向不同；
    所述外围引线在所述引出区内的部分分为沿所述行方向分布的两个外围线组；
    所述外围线组包括沿所述列方向分布的显示引出段、显示过渡段和第一显示延伸段，且所述显示过渡段连接于所述显示引出段和第一显示延伸段之间；所述显示引出段与所述外围引线位于外围区的部分连接，所述第一显示延伸段与部分所述显示引脚连接；所述显示引出段和所述第一显示延伸段均沿所述列方向延伸，所述显示过渡段的延伸方向与所述行方向和列方向不同；
    两个所述显示引出段位于两所述触控引出段之间，所述触控过渡段和显示过渡段一一对应的交叉，两个所述显示引出段位于两所述触控引出段之间，所述触控连接段位于两所述第一显示延伸段之间。
  10. 根据权利要求9所述的触控显示面板，其中，所述触控显示面板还包括：
    第一电源总线，设于所述外围区，并延伸至所述引出区，且与所述绑定部连接，用于传输第一电源信号；所述第一电源总线、所述触控引线和所述外围引线均位于不同层，且所述触控引线位于所述第一电源总线远离所述外围引线的一侧；
    多个电源线，沿所述列方向延伸，且由所述显示区延伸至所述外围区，并与所述第一电源总线连接；一列所述电源线与至少一列所述像素电路连接；
    所述第一电源总线位于所述引出区的部分包括屏蔽部和连接部，所述屏蔽部与所述第一电源总线位于所述外围区的部分连接，所述连接部连接所述屏蔽部与所述绑定部；所述触控引出段、触控过渡段、显示引出段和显示过渡段均与所述屏蔽部至少部分交叠。
  11. 根据权利要求9所述的触控显示面板，其中，所述触控显示面板还包括：
    数据线，沿所述列方向延伸，且由所述显示区延伸至所述引出区，并与部分所述显示引脚连接，一列所述数据线与至少一列所述像素电路 连接，用于传输数据信号；
    所述数据线位于所述引出区的部分包括沿所述行方向分布的两个数据线组，所述触控引出段、触控过渡段、触控连接段、显示引出段和显示过渡段和显示连接段均位于两所述数据线组之间；所述数据线组、所述第一电源总线与所述触控引线均位于不同层，且所述触控引线位于所述第一电源总线远离所述数据线组的一侧，所述数据线组与所述屏蔽部至少部分交叠。
  12. 根据权利要求9所述的触控显示面板，其中，所述外围线组还包括第二显示延伸段和显示连接段，所述第二显示延伸段沿所述行方向延伸，且与所述第一显示延伸段远离所述显示区的一端连接，且沿所述行方向朝远离所述触控连接段的方向延伸；所述第二显示延伸段与所述数据线组交叉且位于不同层；所述连接段沿所述列方向延伸，且位于两所述数据线组的外侧，并与部分所述显示引脚连接。
  13. 根据权利要求11所述的触控显示面板，其中，所述显示引脚沿所述行方向分为两个显示引脚组，所述第一引脚端具有位于两个所述显示引脚组之间的虚设触控引脚，所述触控连接段与一所述虚设触控引脚连接。
  14. 根据权利要求13所述的触控显示面板，其中，两个所述显示引脚组的显示引脚均包括第一显示引脚和第二显示引脚，所述外围引线通过所述第一显示引脚与所述驱动芯片连接，所述数据线通过所述第二显示引脚与所述驱动芯片连接；
    在一所述显示引脚组中，所述第一显示引脚沿行方向位于所述第二显示引脚远离所述虚设触控引脚的一侧。
  15. 根据权利要求12所述的触控显示面板，其中，所述驱动背板包括：
    衬底；
    第一半导体层，设于所述衬底一侧；所述第一半导体层的材料为多晶硅；
    第一栅绝缘层，覆盖所述第一半导体层；
    第一栅极层，设于所述第一栅绝缘层远离所述衬底的表面，且与所 述第一半导体层的至少部分区域交叠；
    第一绝缘层，覆盖所述第一栅极层；
    第二栅极层，设于所述第一绝缘层远离所述衬底的表面；
    第二绝缘层，覆盖所述第二栅极层；
    第二半导体层，设于所述第二绝缘层远离所述衬底的表面；所述第二半导体层的材料为金属氧化物；
    第二栅绝缘层，覆盖所述第二半导体层；
    第三栅极层，设于所述第二栅绝缘层远离所述衬底的表面，且与所述第二半导体层的至少部分区域交叠；
    第三绝缘层，覆盖所述第三栅极层；
    第一源漏层，设于所述第三绝缘层远离所述衬底的表面；
    第一平坦层，设于所述第一源漏层远离所述衬底的一侧；
    第二源漏层，设于所述第一平坦层远离所述衬底的表面；
    第二平坦层，覆盖所述第二源漏层；
    所述发光器件设于所述第二平坦层远离所述衬底的一侧。
  16. 根据权利要求1-14任一项所述的触控显示面板，其中，所述触控层包括多个阵列分布的触控电极，一所述触控电极与一所述触控引线连接。
  17. 根据权利要求8所述的触控显示面板，其中，所述驱动芯片还具有第一测试引脚；所述绑定部具有多个第二测试引脚；所述触控显示面板还包括多个测试线；
    一所述连接走线通过一所述测试线与一所述第二测试引脚连接；一所述第一测试引脚通过一所述测试线与一所述第二测试引脚连接。
  18. 一种显示装置，包括权利要求1-17任一项所述的触控显示面板。
PCT/CN2022/115927 2022-08-30 2022-08-30 触控显示面板及显示装置 WO2024044983A1 (zh)

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CN111710275A (zh) * 2020-06-12 2020-09-25 上海天马有机发光显示技术有限公司 一种显示面板及显示装置
CN215895423U (zh) * 2020-07-31 2022-02-22 联咏科技股份有限公司 Oled触控显示芯片及包含其的oled触控显示装置

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CN107402680A (zh) * 2016-05-20 2017-11-28 乐金显示有限公司 指纹传感器集成型触摸屏装置
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