WO2024000788A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2024000788A1
WO2024000788A1 PCT/CN2022/115996 CN2022115996W WO2024000788A1 WO 2024000788 A1 WO2024000788 A1 WO 2024000788A1 CN 2022115996 W CN2022115996 W CN 2022115996W WO 2024000788 A1 WO2024000788 A1 WO 2024000788A1
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WO
WIPO (PCT)
Prior art keywords
layer
signal line
source
substrate
reset signal
Prior art date
Application number
PCT/CN2022/115996
Other languages
English (en)
French (fr)
Inventor
胡俊艳
戴超
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Publication of WO2024000788A1 publication Critical patent/WO2024000788A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel and a display device.
  • the gate drive circuit is extended to the display area, the light-emitting units are arranged on the gate drive circuit, and the pixel units are compressed to reduce the bezel.
  • this method is only suitable for display devices with lower resolution. As the resolution increases, the pixel size cannot be further compressed, resulting in the frame of the display device still being larger, and multiple line changes are required in the process to realize the adjustment of the light-emitting unit. control, resulting in complex processes and low yields. And because the display panel will use LTPO (Low Temperature Poly-Oxide, LTPO) technology in order to reduce power consumption, this will further increase the process difficulty and reduce the yield rate.
  • LTPO Low Temperature Poly-Oxide
  • Embodiments of the present application provide a display panel and a display device to alleviate the technical problem in existing display devices that arranging the light-emitting unit on the gate driving circuit will result in low yield of the display device.
  • An embodiment of the present application provides a display panel, which includes:
  • a display area provided with a pixel light-emitting unit and a pixel drive circuit that controls the pixel light-emitting unit;
  • a non-display area is located at the periphery of the display area, the non-display area includes a gate drive circuit area, and the non-display area is provided with a reset signal line and a low potential signal line;
  • the reset signal line is connected to the pixel drive circuit
  • the low potential signal line is connected to the pixel light emitting unit
  • the gate drive circuit area is provided with a gate drive circuit
  • the reset signal line and the low potential signal line are connected to the pixel light emitting unit.
  • At least part of at least one of the potential signal lines is provided in the gate drive circuit area, and the reset signal line and the low potential signal line are insulated from the gate drive circuit.
  • the gate drive circuit includes multiple metal layers, and at least part of the reset signal line and the low potential signal line are arranged in different layers from any metal layer in the gate drive circuit. .
  • the display panel includes:
  • a semiconductor layer provided on one side of the substrate
  • a first metal layer disposed on the side of the semiconductor layer away from the substrate;
  • a second metal layer is provided on the side of the first metal layer away from the semiconductor layer;
  • a first source and drain layer is provided on the side of the second metal layer away from the first metal layer;
  • a second source-drain layer is disposed on the side of the first source-drain layer away from the second metal layer;
  • the gate driving circuit includes a transistor and a capacitor
  • the transistor includes a gate, a source and a drain
  • the capacitor includes a capacitor plate
  • the gate is disposed on the first metal layer
  • the capacitor The electrode plate is provided on the second metal layer
  • the source electrode and the drain electrode are provided on the first source-drain electrode layer, at least part of the reset signal line and the low-potential signal line are connected to the
  • the metal layers located in the first metal layer, the second metal layer, the first source-drain layer and the second source-drain layer in the gate driving circuit are arranged in different layers.
  • the display panel further includes a third source-drain layer, a first planarization layer, and a second planarization layer, and the third source-drain layer is disposed away from the second source-drain layer.
  • the first planarization layer is provided between the first source and drain layer and the second source and drain layer
  • the second planarization layer is provided on between the second source-drain layer and the third source-drain layer; at least one of the reset signal line and the low-potential signal line includes a first source-drain layer disposed on the third source-drain layer
  • the overlapping portion, and the projection of the first overlapping portion on the substrate overlaps the projection of the gate driving circuit on the substrate.
  • the reset signal line is provided on the third source-drain layer, and the projection of the reset signal line on the substrate is the same as the projection of the gate drive circuit on the substrate. There is overlap.
  • the projection of the reset signal line on the substrate coincides with the projection of the source on the substrate, or the projection of the reset signal line on the substrate coincides with the projection of the reset signal line on the substrate.
  • the projection of the drain electrode on the substrate overlaps, or the projection of the reset signal line on the substrate overlaps the projection of the gate electrode on the substrate, or the reset signal The projection of the line on the substrate coincides with the projection of the capacitor plate on the substrate.
  • the pixel driving circuit includes a first reset transistor and a second reset transistor
  • the second source-drain layer includes connection metal
  • the reset signal line passes through the second planarization layer.
  • the hole is connected to a connection metal extending from the gate drive circuit area to the display area and connected to the first reset transistor and the second reset transistor.
  • the low-potential signal line is provided on the third source-drain layer, and the projection of the low-potential signal line on the substrate is consistent with the projection of the gate drive circuit on the substrate. There is overlap in the projections.
  • the low-potential signal line includes a first part, a second part and a third part, the first part is provided on the first source-drain layer, and the second part is provided on the second Source and drain layer, the third part is provided on the third source and drain layer, the second part passes through the via hole of the first planarization layer and is connected to the first part, the third part A via hole passing through the second planarization layer is connected to the second part, and the projection of the third part on the substrate coincides with the projection of the gate driving circuit on the substrate.
  • the width of the third part is greater than the width of the first part
  • the width of the third part is greater than the width of the second part.
  • the display panel further includes a fourth source-drain layer, the fourth source-drain layer being disposed on a side of the third source-drain layer away from the second source-drain layer,
  • the reset signal line is provided on the fourth source-drain layer, and the projection of the reset signal line on the substrate coincides with the projection of the third part on the substrate.
  • the display panel further includes a light-shielding layer disposed between the substrate and the semiconductor layer, and at least one of the reset signal line and the low-potential signal line includes The second overlapping portion is provided on the light-shielding layer, and the projection of the second overlapping portion on the substrate overlaps with the projection of the gate driving circuit on the substrate.
  • the reset signal line is provided on the light-shielding layer, and the projection of the reset signal line on the substrate coincides with the projection of the gate drive circuit on the substrate.
  • the low-potential signal line includes a first part, a second part and a fourth part, the first part is provided on the first source-drain layer, and the second part is provided on the second Source and drain layers, the fourth part is provided on the light-shielding layer;
  • the display panel also includes a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, an active layer and a third metal layer, the first insulating layer being disposed on the between the semiconductor layer and the first metal layer, the second insulating layer is disposed between the first metal layer and the second metal layer, the third insulating layer is disposed on the second metal layer and the active layer, the fourth insulating layer is disposed between the active layer and the third metal layer, the fifth insulating layer is disposed between the third metal layer and the third metal layer.
  • a source and drain layer Between a source and drain layer,
  • the second part is connected to the first part through a via hole of the first planarization layer, and the first part passes through the first insulating layer, the second insulating layer, the third Vias of the insulating layer, the fourth insulating layer and the fifth insulating layer are connected to the fourth part, and the projection of the fourth part on the substrate is consistent with the gate driving circuit on the The projections on the substrate overlap, the width of the fourth part is greater than the width of the first part, and the width of the fourth part is greater than the width of the second part.
  • a display panel which includes:
  • a display area provided with a pixel light-emitting unit and a pixel drive circuit that controls the pixel light-emitting unit;
  • a non-display area is located at the periphery of the display area, the non-display area includes a gate drive circuit area, and the non-display area is provided with a reset signal line and a low potential signal line;
  • the reset signal line is connected to the pixel drive circuit
  • the low potential signal line is connected to the pixel light emitting unit
  • the gate drive circuit area is provided with a gate drive circuit
  • the reset signal line and the low potential signal line are connected to the pixel light emitting unit.
  • At least part of at least one of the potential signal lines is provided in the gate drive circuit area, and the reset signal line and the low potential signal line are insulated from the gate drive circuit.
  • the gate drive circuit includes multiple metal layers, and at least part of the reset signal line and the low potential signal line are arranged in different layers from any metal layer in the gate drive circuit. .
  • the display panel includes:
  • a semiconductor layer provided on one side of the substrate
  • a first metal layer disposed on the side of the semiconductor layer away from the substrate;
  • a second metal layer is provided on the side of the first metal layer away from the semiconductor layer;
  • a first source and drain layer is provided on the side of the second metal layer away from the first metal layer;
  • a second source-drain layer is disposed on the side of the first source-drain layer away from the second metal layer;
  • the gate driving circuit includes a transistor and a capacitor
  • the transistor includes a gate, a source and a drain
  • the capacitor includes a capacitor plate
  • the gate is disposed on the first metal layer
  • the capacitor The electrode plate is provided on the second metal layer
  • the source electrode and the drain electrode are provided on the first source-drain electrode layer, at least part of the reset signal line and the low-potential signal line are connected to the
  • the metal layers located in the first metal layer, the second metal layer, the first source-drain layer and the second source-drain layer in the gate driving circuit are arranged in different layers.
  • the display panel further includes a third source-drain layer, a first planarization layer, and a second planarization layer, and the third source-drain layer is disposed away from the second source-drain layer.
  • the first planarization layer is provided between the first source and drain layer and the second source and drain layer
  • the second planarization layer is provided on between the second source-drain layer and the third source-drain layer; at least one of the reset signal line and the low-potential signal line includes a first source-drain layer disposed on the third source-drain layer
  • the overlapping portion, and the projection of the first overlapping portion on the substrate overlaps the projection of the gate driving circuit on the substrate.
  • the reset signal line is provided on the third source-drain layer, and the projection of the reset signal line on the substrate is the same as the projection of the gate drive circuit on the substrate. There is overlap.
  • the projection of the reset signal line on the substrate coincides with the projection of the source on the substrate, or the projection of the reset signal line on the substrate coincides with the projection of the reset signal line on the substrate.
  • the projection of the drain electrode on the substrate overlaps, or the projection of the reset signal line on the substrate overlaps the projection of the gate electrode on the substrate, or the reset signal The projection of the line on the substrate coincides with the projection of the capacitor plate on the substrate.
  • the pixel driving circuit includes a first reset transistor and a second reset transistor
  • the second source-drain layer includes connection metal
  • the reset signal line passes through the second planarization layer.
  • the hole is connected to a connection metal extending from the gate drive circuit area to the display area and connected to the first reset transistor and the second reset transistor.
  • the present application provides a display panel and a display device; the display panel includes a display area and a non-display area.
  • the display area is provided with a pixel light-emitting unit and a pixel drive circuit that controls the pixel light-emitting unit.
  • the non-display area is located at the periphery of the display area.
  • the non-display area It includes a gate drive circuit area.
  • the non-display area is provided with a reset signal line and a low-potential signal line.
  • the reset signal line is connected to the pixel drive circuit, the low-potential signal line is connected to the pixel light-emitting unit, and the gate drive circuit is provided in In the gate drive circuit, at least part of at least one of the reset signal line and the low-potential signal line is provided in the gate drive circuit area, and the reset signal line and the low-potential signal line are insulated from the gate drive circuit.
  • the gate drive circuit at least part of at least one of the reset signal line and the low-potential signal line is provided in the gate drive circuit area, it can at least reduce the occupation of part of the reset signal line and the low-potential signal line in the gate drive circuit area.
  • FIG. 1 is a first schematic diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a circuit diagram of a display panel provided by an embodiment of the present application.
  • FIG. 3 is a second schematic diagram of a display panel provided by an embodiment of the present application.
  • FIG. 4 is a comparison diagram of the installation areas of various components of the current display device provided by the embodiment of the present application and the display panel of the present application.
  • FIG. 5 is a first perspective view of a display panel provided by an embodiment of the present application.
  • FIG. 6 is a second perspective view of the display panel provided by the embodiment of the present application.
  • FIG. 7 is a third perspective view of a display panel provided by an embodiment of the present application.
  • embodiments of the present application provide a display panel and a display device to alleviate the above technical problem.
  • the display panel 1 includes:
  • Display area 181 the display area 181 is provided with a pixel light-emitting unit LED and a pixel driving circuit 21 that controls the pixel light-emitting unit LED;
  • the non-display area 182 is located at the periphery of the display area 181.
  • the non-display area 182 includes a gate drive circuit area 183.
  • the non-display area 182 is provided with a reset signal line 171 and a low-potential signal line 16;
  • the reset signal line 171 is connected to the pixel driving circuit 21
  • the low potential signal line 16 is connected to the pixel light emitting unit LED
  • the gate driving circuit area 183 is provided with a gate driving circuit 22, so At least part of at least one of the reset signal line 171 and the low potential signal line 16 is provided in the gate drive circuit area 183, and the reset signal line 171 and the low potential signal line 16 are connected to the gate drive circuit region 183.
  • the pole drive circuit 22 is provided with insulation.
  • Embodiments of the present application provide a display panel that can at least reduce the size of the reset signal line and the low-potential signal line by arranging at least part of at least one of the reset signal line and the low-potential signal line in the gate drive circuit area.
  • the area occupied by the part where the line is arranged in the gate drive circuit area reduces the width of the frame required by this part, thereby reducing the frame of the display panel.
  • this solution does not require the gate drive circuit to be arranged on the light-emitting unit, reducing the The process difficulty of display panel preparation improves the yield rate of display panels.
  • Figure 1 is a cross-sectional view of the display panel. Therefore, Figure 1 does not show all the components of a single sub-pixel. Only some transistors, wiring and capacitors are shown. Therefore, it can be understood that Figure 1
  • the pixel drive circuit in Figure 1 not only includes two transistors, but also includes other components; similarly, the gate drive circuit shown in Figure 1 includes not only a single transistor, but also other components. Specifically, the pixel drive circuit includes components.
  • the device may be a plurality of components as shown in the circuit in Figure 2.
  • the low-potential signal line is marked with the number 16, and in the circuit diagram shown in Figure 2, the low-potential signal line is marked with ELVSS.
  • the only differences here are The different marking methods in the diagrams actually correspond to the low-potential signal lines in the cross-sectional view shown in Figure 1 and the low-potential signal lines in the circuit diagram shown in Figure 2.
  • the projection of the reset signal line and the low-potential signal line on the plane where the gate drive circuit is located refers to the projection of the reset signal line and the low-potential signal line on the plane where any metal layer in the gate drive circuit is located.
  • the projection can be the projection of the reset signal line and the low potential signal line on the gate layer. This projection is located in the gate drive circuit area and is insulated from the gate drive circuit.
  • the pixel light-emitting unit is labeled with LED, but this application does not limit the pixel light-emitting unit to a light-emitting diode.
  • the pixel light-emitting unit may be an organic light-emitting diode.
  • the gate driving circuit includes a transistor, the pixel driving circuit includes a connecting wire, the reset signal line is connected to the pixel driving circuit through the connecting wire, and the connecting wire At least part of the connecting trace is provided in a metal layer in the metal layer where the transistor is located, so that the connecting trace does not need to add a metal layer to avoid Increase the thickness of the display panel.
  • the pixel driving circuit includes a connecting wire
  • the reset signal line is connected to the pixel driving circuit through the connecting wire
  • the connecting wire extends from the gate driving circuit area
  • the connection wiring and the reset signal line are provided on the same metal layer.
  • the display panel includes a connection hole, the connection hole is provided in the display area, and the connection hole is located on the pixel driving circuit, and the connection wiring passes through the connection hole. .
  • the connection trace is formed by using the same metal layer as the reset signal line, so that the connection trace can be directly connected to the pixel drive circuit through the connection hole without modification. The location of the connection holes reduces process complexity.
  • the gate drive circuit includes multiple metal layers, and at least part of the reset signal line and the low potential signal line is in a different layer from any metal layer in the gate drive circuit. set up.
  • the display panel 1 includes:
  • Semiconductor layer 141 is provided on one side of the substrate 11;
  • the first metal layer 143 is provided on the side of the semiconductor layer 141 away from the substrate 11;
  • the second metal layer 145 is disposed on the side of the first metal layer 143 away from the semiconductor layer 141;
  • the first source and drain layer 151 is provided on the side of the second metal layer 145 away from the first metal layer 143;
  • the second source and drain layer 153 is disposed on the side of the first source and drain layer 151 away from the second metal layer 145;
  • the gate driving circuit 22 includes a transistor and a capacitor
  • the transistor includes a gate 143a, a source 151d and a drain 151b
  • the capacitor includes a capacitor plate 145a
  • the gate 143a is disposed on the first Metal layer 143
  • the capacitor plate 145a is provided on the second metal layer 145
  • the source electrode 151d and the drain electrode 151b are provided on the first source-drain electrode layer 151
  • the reset signal line 171 and At least part of the low-potential signal line 16 is located in the first metal layer 143 , the second metal layer 145 , the first source-drain layer 151 and the second source-drain layer 153 in the gate driving circuit 22 metal heterogeneous setting.
  • the reset signal line 171 and the low potential signal line 16 are arranged in different layers with any metal in the gate drive circuit 22.
  • the gate drive When setting the gate drive When setting the reset signal line and low-potential signal line in the circuit area to reduce the border, the reset signal line and low-potential signal line will not be set on the film layer where the gate drive circuit is located, thus avoiding the reset signal line and low-potential signal line from interfacing with each other.
  • the metal in the gate drive circuit creates a short circuit or interference.
  • the gate drive circuit includes a transistor and a capacitor.
  • the transistor includes a gate, a source, and a drain, and the capacitor includes a capacitor plate. Therefore, the reset signal line and the low-potential signal line are set at When part of the gate drive circuit is arranged on the film layer where these components are located, it will cause short circuit or interference.
  • the reset signal line and the low-potential signal line are arranged on other film layers to avoid the reset signal line and the low-potential signal line. The signal lines interfere with the components in the gate drive circuit, resulting in poor signals.
  • the embodiments of the present application only limit the reset signal line and the portion of the low-potential signal line in the gate drive circuit area to be arranged in different layers of metal in the gate drive circuit.
  • the portion of the low-potential signal line outside the gate driving circuit area is not limited.
  • the low-potential signal line also includes a portion provided on the first source and drain layer.
  • the metal layer in the gate drive circuit will cause signal interference or short circuit problems.
  • the display panel 1 further includes a third source-drain layer 154 , a first planarization layer 152 and a second planarization layer 155 .
  • the third source-drain layer 154 is disposed on a side of the second source-drain layer 153 away from the first source-drain layer 151 , and the first planarization layer 152 is disposed on the first source-drain layer 151 and the second Between the source and drain layers 153, the second planarization layer 155 is disposed between the second source and drain layers 153 and the third source and drain layers 154; the reset signal line 171 and the low At least one of the potential signal lines 16 includes a first overlapping portion disposed on the third source-drain layer 154 , and the projection of the first overlapping portion on the substrate 11 is consistent with the gate driving circuit 22 The projections on the substrate 11 overlap.
  • the reset signal line and the low-potential signal line can be set in the third source-drain layer, and will not be in the same film layer as the metal of the gate drive circuit, thus avoiding the risk of damage to the gate drive circuit.
  • the metal such as the gate
  • low-potential signal lines which can increase the width of the reset signal line and the low-potential signal line and reduce the impedance of the reset signal line and the low-potential signal line.
  • the first overlapping part refers to the part of the reset signal line and the low-potential signal line that is in the gate drive circuit area.
  • the reset signal The first overlapping part of the lines refers to the entire reset signal line. Only part of the low-potential signal line is in the gate drive circuit area.
  • the first overlapping part of the low-potential signal line refers to the third part 163 of the low-potential signal line in the gate drive circuit area. part of the pole drive circuit area.
  • the reset signal line 171 is provided on the third source-drain layer 154 , and the projection of the reset signal line 171 on the substrate 11 is consistent with the gate The projections of the pole driving circuit 22 on the substrate 11 overlap.
  • the width of the frame can be reduced, and in this process, the metal of the third source-drain layer is connected to the second source-drain layer and other metal layers through via holes. It will lead to process risks and improve the yield rate of the display panel.
  • the entire reset signal line can be arranged on the gate drive circuit, thereby eliminating the width of the frame occupied by the reset signal line and reducing the frame of the display panel.
  • the projection of the reset signal line on the substrate coincides with the projection of the source on the substrate, or the projection of the reset signal line on the substrate
  • the projection of the drain electrode on the substrate overlaps, or the projection of the reset signal line on the substrate overlaps the projection of the gate electrode on the substrate, or the reset The projection of the signal line on the substrate coincides with the projection of the capacitor plate on the substrate.
  • the projection of the reset signal line on the substrate overlaps with the projection of the gate on the substrate.
  • the third source-drain layer provided for the reset signal line may be the same as the second source-drain layer.
  • the pixel driving circuit includes a first reset transistor and a second reset transistor
  • the first source-drain layer includes connection metal
  • the reset signal line passes through the second planarization layer.
  • a via hole is connected to a connection metal extending from the gate drive circuit area to the display area and connected to the first reset transistor and the second reset transistor.
  • the reset signal line when the reset signal line is provided on the third source-drain layer, the reset signal line can be connected to the second source-drain layer in the gate drive circuit area, and then the reset signal line can be passed through the second source-drain layer.
  • the connection metal extends to the display area and is connected to the source and drain electrodes of the first reset transistor and the second reset transistor in the display area to realize signal input to the first reset transistor and the second reset transistor.
  • the reset signal line includes a first reset signal line VI-G and a second reset signal line VI-ANO.
  • the first reset signal line VI-G and the second reset signal line VI-ANO are At least one of the reset signal lines VI-ANO is provided on the third source-drain layer, and one of the first reset signal line VI-G and the second reset signal line VI-ANO is provided on the third source-drain layer.
  • the projection of part of the source and drain layer on the substrate coincides with the projection of the gate driving circuit on the substrate.
  • each reset signal line can be arranged on the third source-drain layer, so that each reset signal line is arranged in the gate drive circuit area, thereby reducing the size of the frame occupied by each reset signal line. width.
  • the low-potential signal line is provided on the third source-drain layer, and the projection of the low-potential signal line on the substrate is consistent with the projection of the gate drive circuit on the substrate. There is overlap in projections.
  • the low-potential signal line 16 includes a first part 161 , a second part 162 and a third part 163 , and the first part 161 is disposed on the first source-drain layer. 151.
  • the second part 162 is provided on the second source-drain layer 153
  • the third part 163 is provided on the third source-drain layer 154
  • the second part 162 passes through the first
  • the via hole of the planarization layer 152 is connected to the first part 161.
  • the third part 163 passes through the via hole of the second planarization layer 155 and is connected to the second part 162.
  • the third part 163 is in The projection on the substrate 11 overlaps with the projection of the gate driving circuit 22 on the substrate 11 , and the width of the third portion 163 is greater than the width of the first portion 161 .
  • the width of portion 163 is greater than the width of said second portion 162 .
  • the signal By arranging the low-potential signal line as the first part, the second part and the third part, the signal can be transmitted to the display area through the connected first part, the second part and the third part, so that the low-potential signal line can work normally, and the third part can If the three parts are arranged on the third source and drain layer, and the projection of the third part and the gate drive circuit on the substrate overlaps, the width of the frame occupied by the third part can be reduced, and since the third part is separated from the first part
  • the low-potential signal line setting area where the second part is located extends to the gate drive circuit area.
  • the width of the third part is larger, which reduces the impedance of the low-potential signal line, and the third part is connected in parallel with the second part.
  • the second part is connected in parallel with the first part, further reducing the impedance of the low-potential signal line, making the impedance of the low-potential signal line meet the driving requirements or even reducing the impedance of the low-potential signal line, thereby reducing the first and second parts
  • the width of the frame is reduced, thereby reducing the width of the frame occupied by the low-potential signal line, thereby reducing the width of the frame of the display panel.
  • the non-display area 182 also includes a low-voltage signal line area 184 , the first part 161 and the second part 162 are provided in the low-potential signal line area 184 , and the third part 163 is connected from the low-potential signal line area 184 Extending to the gate driving circuit area 183 reduces the width of the frame of the display panel.
  • the reset signal line and the low-potential signal line being disposed on the third source-drain layer as an example. It can be understood that the reset signal line and the low-potential signal line can be disposed on the third source-drain layer at the same time. pole layer to further reduce the frame of the display panel. At this time, it is only necessary to insulate the reset signal line and the low-potential signal line.
  • the reset signal line and the low-potential signal line can be set as described in the above embodiment. , which will not be described in detail here.
  • the display panel further includes a fourth source-drain layer, which is disposed on a side of the third source-drain layer away from the second source-drain layer.
  • the reset signal line is provided on the fourth source-drain layer, and the projection of the reset signal line on the substrate coincides with the projection of the third part on the substrate.
  • the third part of the low-potential signal line can be placed in all areas of the gate drive circuit, thereby further reducing the width of the frame occupied by the low-potential signal line, and the reset Setting the signal line on the fourth source-drain layer can also reduce the width of the frame occupied by the reset signal line, so that the frame of the display panel does not need to set a setting area for the reset signal line, and the width of the low-potential signal setting area is smaller , further reducing the frame of the display panel.
  • connecting metals can be provided on the third source-drain layer and the second source-drain layer respectively, so that the reset signal line is connected to the third source-drain layer.
  • the connection metal is then connected to the connection metal of the second source-drain layer, and by extending the connection metal to the display area, it is connected to the source-drain electrodes of the first reset transistor and the second reset transistor, thereby realizing the connection between the first reset transistor and the second reset transistor. Signal input for the second reset transistor.
  • the display panel 1 further includes a light-shielding layer 12 disposed between the substrate 11 and the semiconductor layer 141 , and the reset signal line 171 and at least one of the low-potential signal lines 16 includes a second overlapping portion provided on the light shielding layer 12, and the projection of the second overlapping portion on the substrate 11 is consistent with the gate driving circuit.
  • the projections of 22 on the substrate 11 overlap.
  • the space occupied by the reset signal line and the low-potential signal line can be reduced, and the frame of the display panel can be reduced without interfering with the gate drive circuit.
  • the metal is in the same film layer to avoid interference or short circuit between the metal (such as gate) in the gate drive circuit and the reset signal line and low-potential signal line.
  • the reset signal line and low-potential signal line are formed through the light-shielding layer, which can Increase the width of the reset signal line and the low-potential signal line, and reduce the impedance of the reset signal line and the low-potential signal line.
  • the second overlapping part refers to the part of the reset signal line and the low-potential signal line that is in the gate drive circuit area.
  • the reset signal The second overlapping part of the lines refers to the entire reset signal line; similarly, the second overlapping part of the low-potential signal line refers to the part of the low-potential signal line in the gate drive circuit area.
  • the reset signal line 171 is provided on the light-shielding layer 12 , and the projection of the reset signal line 171 on the substrate 11 is consistent with the gate drive circuit.
  • the projections of 22 on the substrate 11 overlap.
  • the second source and drain layer can be formed with a connection metal, and the connection metal passes through each insulation layer and the planarization layer to connect to the reset signal line, and the connection metal extends to The display area is then connected to the first reset transistor and the second reset transistor to implement signal input to the first reset transistor and the second reset transistor.
  • the low-voltage signal line includes a first part, a second part and a fourth part, the first part is provided on the first source-drain layer, and the second part is provided on the first source-drain layer. Two source and drain layers, the fourth part is provided on the light shielding layer;
  • the display panel also includes a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, an active layer and a third metal layer, the first insulating layer being disposed on the between the semiconductor layer and the first metal layer, the second insulating layer is disposed between the first metal layer and the second metal layer, the third insulating layer is disposed on the second metal layer and the active layer, the fourth insulating layer is disposed between the active layer and the third metal layer, the fifth insulating layer is disposed between the third metal layer and the third metal layer.
  • a source and drain layer Between a source and drain layer,
  • the second part is connected to the first part through a via hole of the first planarization layer, and the first part passes through the first insulating layer, the second insulating layer, the third Vias of the insulating layer, the fourth insulating layer and the fifth insulating layer are connected to the fourth part, and the projection of the fourth part on the substrate is consistent with the gate driving circuit on the The projections on the substrate overlap, the width of the fourth part is greater than the width of the first part, and the width of the fourth part is greater than the second part.
  • the signal By arranging the low-potential signal line as the first part, the second part and the fourth part, the signal can be transmitted to the display area through the connected first part, the second part and the fourth part, so that the low-potential signal line can work normally, and the third part can
  • the four parts are arranged on the light-shielding layer, and the projection of the fourth part and the gate drive circuit on the substrate overlaps, the width of the frame occupied by the fourth part can be reduced, and since the fourth part is separated from the first part and the second part
  • the low-potential signal line setting area extends to the gate drive circuit area.
  • the width of the fourth part is larger, which reduces the impedance of the low-potential signal line, making the impedance of the low-potential signal line meet the driving requirements and even reducing the low-potential
  • the impedance of the signal line can be reduced, thereby reducing the width of the first and second parts, reducing the width of the frame occupied by the low-potential signal line, thereby reducing the width of the frame of the display panel, and this setting method does not require a new film layer. Does not increase the thickness of the display panel.
  • the fourth part of the low-voltage signal line is disposed in the light-shielding layer, the problem that the distance between the light-shielding layer and the first source-drain layer is large and the metal is easy to break in the via hole can be solved through other film layers.
  • the transfer is performed, for example, through the first metal layer.
  • the embodiments of the present application are not limited to this, and the standard is that normal connection of low-voltage signal lines can be achieved.
  • the reset signal line and the low-potential signal line being arranged in the light-shielding layer as an example. It can be understood that in order to further reduce the frame, the reset signal line and the low-potential signal line can be arranged in the light-shielding layer. At this time, it is only necessary to insulate the reset signal line and the low-potential signal line.
  • the reset signal line and the low-potential signal line can be arranged as described in the above embodiments, and will not be described again here.
  • the low-potential signal line is placed in the light-shielding layer to increase the width of the gate drive circuit area occupied by the low-potential signal line and further reduce the width of the frame occupied by the low-potential signal line. The width of the display panel's border.
  • FIG. 4 (a) in FIG. 4 is a schematic diagram of the installation area of each component of the current display device, and (b) in FIG. 4 is a schematic diagram of the installation area of each part of the display panel of the present application.
  • a gate drive circuit setting area 212, a low potential signal line setting area 211 and a reset signal line setting area 213 need to be respectively set, resulting in a smaller frame of the display device. big.
  • the low-potential signal line and the reset signal line are set in the gate drive circuit area, as shown in (b) of Figure 4. It can be seen that the low-potential signal line setting area 221 and the gate drive circuit area 183 exist. Overlapping, the reset signal line setting area 222 is located in the gate driving circuit area 183, which reduces the frame of the display panel.
  • the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a first reset transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, and a second reset transistor T7. , storage capacitor Cst, boost capacitor Cboost, high potential signal line ELVDD, data line Data, first scan line P Scan (n), second scan line P Scan (n-1), third scan line N Scan (n ), the fourth scan line N Scan (n-5) and the luminescence control line EM.
  • P Scan (n) represents the current level scan line
  • P Scan (n-1) represents the previous level scan line
  • the above scan line is used to control the P-type transistor
  • N Scan(n) represents the scan line of this level
  • N Scan(n-5) represents the upper five scan lines, and these two scan lines are used to control N-type transistors.
  • the working principle of the circuit is as follows: in the first stage, the first reset transistor T4 and the second reset transistor T7 are turned on, and the reset signal output through the first reset signal line VI-G resets the gate of the first transistor T1, and the gate of the first transistor T1 is reset through the second reset transistor T7.
  • the reset signal output by the reset signal line VI-ANO resets the pixel light-emitting unit LED; in the second stage, the second transistor T2 and the third transistor T3 are turned on, and the data signal input by the data line Data is written into the gate of the first transistor T1;
  • the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on to drive the pixel light-emitting unit LED to emit light.
  • a display panel using a 7T1C (seven transistors and one capacitor) circuit can also adopt the design of the present application.
  • the substrate 11 includes a first flexible layer 111 , a barrier layer 112 and a second flexible layer 113 , and the display panel further includes Buffer layer 13.
  • the display panel further includes a first insulating layer 142 , a second insulating layer 144 , a third insulating layer 146 , a fourth insulating layer 148 and a fifth insulating layer 150 .
  • the semiconductor layer 141 includes a semiconductor pattern 141a.
  • the source 151d includes a first source portion 151a and a second source portion 151c.
  • the display panel further includes an active layer 147 and a third metal layer 149 , where the material of the semiconductor layer is low-temperature polysilicon and the material of the active layer is oxide.
  • the embodiment of the present application takes LTPO technology as an example to illustrate the structure of the display panel.
  • the embodiment of the present application is not limited thereto.
  • the display panel may adopt LTPS (Low Temperature Poly-silicon, low-temperature polysilicon) technology.
  • the second source-drain layer 153 forms a second source portion 151c, a lower portion of the source electrode 151d.
  • the second part 162 of the potential signal line and the connecting metal are insulated from the second source part 151c and the second part 162 of the low-potential signal line.
  • the connecting metal is not shown in the figure.
  • the second planarization layer 155 is formed with via holes on the connection metal and the via holes on the second part 162 of the low potential signal line.
  • the third source and drain layer 154 is formed with the reset signal line 171 and the low potential signal line.
  • the reset signal line passes through the via hole of the second planarization layer 155 and is connected to the connection metal, and then the connection metal extends to the display area and is connected to the electrodes of the first reset transistor and the second reset transistor, and the low potential signal
  • the third portion 163 of the line passes through the via hole of the second planarization layer 155 and is connected to the second portion 162 of the low potential signal line.
  • the display panel also includes a third planarization layer, a pixel electrode layer, a luminescent material layer, a pixel definition layer and a common electrode layer.
  • the third planarization layer is disposed on a side of the third source and drain layer away from the second planarization layer.
  • the pixel electrode layer is formed with a transfer metal
  • the common electrode layer passes through the via hole of the pixel definition layer and is connected to the transfer metal
  • the transfer metal passes through the via hole of the third planarization layer and is connected to The third part of the low-level signal.
  • Figures 5 to 7 are perspective views of the gate drive circuit area and low potential signal line area of the display panel.
  • Figure 5 is a perspective view of the display panel after the second source and drain layer is prepared.
  • Figure 6 is a perspective view of the display panel.
  • a perspective view after the second planarization layer is prepared.
  • FIG. 7 is a schematic diagram of the display panel after the third source and drain layer is prepared.
  • reference numeral 31 indicates the reserved connection position for the low-potential signal line after the second source and drain layer is prepared
  • reference numeral 32 indicates the reserved connection position for the reset signal line after the second source and drain layer is prepared.
  • Figure 6 indicates with reference numeral 33 the position of the connection hole for the low-potential signal line after the second planarization layer is prepared.
  • the connection hole for the reset signal line is set at the same position as the reserved connection position for the reset signal line in Figure 5
  • the reference number 34 in Figure 7 indicates the connection between the third part of the low-potential signal line and the second part of the low-level signal line.
  • the reset signal line is connected to the connecting metal.
  • embodiments of the present application provide a display device, which includes the display panel and driver chip described in any of the above embodiments.
  • Embodiments of the present application provide a display panel and a display device; the display panel includes a display area and a non-display area.
  • the display area is provided with a pixel light-emitting unit and a pixel driving circuit that controls the pixel light-emitting unit.
  • the non-display area is located at the periphery of the display area.
  • the display area includes a gate drive circuit area, and the non-display area is provided with a reset signal line and a low-potential signal line.
  • the reset signal line is connected to the pixel drive circuit, the low-potential signal line is connected to the pixel light-emitting unit, and the gate drive circuit is provided in A gate drive circuit is provided, at least part of at least one of the reset signal line and the low-potential signal line is provided in the gate drive circuit area, and the reset signal line and the low-potential signal line are insulated from the gate drive circuit.
  • the reset signal line and the low-potential signal line are insulated from the gate drive circuit.

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Abstract

本申请提供一种显示面板和显示装置；该显示面板通过使复位信号线和低电位信号线中的至少一个的至少部分位于栅极驱动电路区，则至少可以减小复位信号线和低电位信号线设置在栅极驱动电路区的部分占用的面积，减小该部分需要的边框的宽度，从而减小了显示面板的边框。

Description

显示面板和显示装置 技术领域
本申请涉及显示技术领域，尤其是涉及一种显示面板和显示装置。
 背景技术
现有显示器件为了实现窄边框，会通过将栅极驱动电路延伸至显示区，将发光单元设置在栅极驱动电路上，压缩像素单元以减小边框。但这种方式仅适用于分辨率较低的显示器件，随着分辨率的上升，无法进一步压缩像素尺寸，导致显示器件的边框仍然较大，且该过程中需要多次换线实现对发光单元的控制，导致工艺复杂，良率较低。且由于显示面板为了降低功耗，会采用LTPO（Low Temperature Poly-Oxide，LTPO）技术，这会进一步增加工艺难度，降低良率。
所以，现有显示器件存在将发光单元设置在栅极驱动电路上会导致显示器件的良率较低的技术问题。
 技术问题
本申请实施例提供一种显示面板和显示装置，用以缓解现有显示器件存在将发光单元设置在栅极驱动电路上会导致显示器件的良率较低的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种显示面板，该显示面板包括：
显示区，所述显示区设有像素发光单元和控制所述像素发光单元的像素驱动电路；
非显示区，位于所述显示区外围，所述非显示区包括栅极驱动电路区，所述非显示区设有复位信号线和低电位信号线；
其中，所述复位信号线连接至所述像素驱动电路，所述低电位信号线与像素发光单元连接，所述栅极驱动电路区设有栅极驱动电路，所述复位信号线和所述低电位信号线中的至少一个的至少部分设置于所述栅极驱动电路区，且所述复位信号线和所述低电位信号线与所述栅极驱动电路绝缘设置。
在一些实施例中，所述栅极驱动电路包括多层金属层，所述复位信号线与所述低电位信号线中的至少部分与所述栅极驱动电路中的任一金属层异层设置。
在一些实施例中，所述显示面板包括：
衬底；
半导体层，设置于所述衬底一侧；
第一金属层，设置于所述半导体层远离所述衬底的一侧；
第二金属层，设置于所述第一金属层远离所述半导体层的一侧；
第一源漏极层，设置于所述第二金属层远离所述第一金属层的一侧；
第二源漏极层，设置于所述第一源漏极层远离所述第二金属层的一侧；
其中，所述栅极驱动电路包括晶体管和电容，所述晶体管包括栅极、源极和漏极，所述电容包括电容极板，所述栅极设置于所述第一金属层，所述电容极板设置于所述第二金属层，所述源极和所述漏极设置于所述第一源漏极层，所述复位信号线和所述低电位信号线中的至少部分与所述栅极驱动电路中的位于所述第一金属层、第二金属层、第一源漏极层和第二源漏极层的金属异层设置。
在一些实施例中，所述显示面板还包括第三源漏极层、第一平坦化层和第二平坦化层，所述第三源漏极层设置于所述第二源漏极层远离所述第一源漏极层的一侧，所述第一平坦化层设置于所述第一源漏极层和所述第二源漏极层之间，所述第二平坦化层设置于所述第二源漏极层和所述第三源漏极层之间；所述复位信号线和所述低电位信号线中的至少一个包括设置于所述第三源漏极层的第一重合部分，且所述第一重合部分在所述衬底上的投影与所述栅极驱动电路在所述衬底上的投影存在重合。
在一些实施例中，所述复位信号线设置于所述第三源漏极层，所述复位信号线在所述衬底上的投影与所述栅极驱动电路在所述衬底上的投影存在重合。
在一些实施例中，所述复位信号线在所述衬底上的投影与所述源极在所述衬底上的投影存在重合，或者所述复位信号线在所述衬底上的投影与所述漏极在所述衬底上的投影存在重合，或者所述复位信号线在所述衬底上的投影与所述栅极在所述衬底上的投影存在重合，或者所述复位信号线在所述衬底上的投影与所述电容极板在所述衬底上的投影存在重合。
在一些实施例中，所述像素驱动电路包括第一复位晶体管和第二复位晶体管，所述第二源漏极层包括连接金属，所述复位信号线穿过所述第二平坦化层的过孔连接至连接金属，所述连接金属从所述栅极驱动电路区延伸至所述显示区并与所述第一复位晶体管和所述第二复位晶体管连接。
在一些实施例中，所述低电位信号线设置于所述第三源漏极层，所述低电位信号线在所述衬底上的投影与所述栅极驱动电路在所述衬底上的投影存在重合。
在一些实施例中，所述低电位信号线包括第一部分、第二部分和第三部分，所述第一部分设置于所述第一源漏极层，所述第二部分设置于所述第二源漏极层，所述第三部分设置于所述第三源漏极层，所述第二部分穿过所述第一平坦化层的过孔与所述第一部分连接，所述第三部分穿过所述第二平坦化层的过孔与所述第二部分连接，所述第三部分在所述衬底上的投影与所述栅极驱动电路在所述衬底上的投影存在重合，且所述第三部分的宽度大于所述第一部分的宽度，所述第三部分的宽度大于所述第二部分的宽度。
在一些实施例中，所述显示面板还包括第四源漏极层，所述第四源漏极层设置于所述第三源漏极层远离所述第二源漏极层的一侧，所述复位信号线设置于所述第四源漏极层，且所述复位信号线在所述衬底上的投影与所述第三部分在所述衬底上的投影存在重合。
在一些实施例中，所述显示面板还包括遮光层，所述遮光层设置于所述衬底与所述半导体层之间，所述复位信号线和所述低电位信号线中的至少一个包括设置于所述遮光层的第二重合部分，且所述第二重合部分在所述衬底上的投影与所述栅极驱动电路在所述衬底上的投影存在重合。
在一些实施例中，所述复位信号线设置于所述遮光层，且所述复位信号线在所述衬底上的投影与所述栅极驱动电路在所述衬底上的投影存在重合。
在一些实施例中，所述低电位信号线包括第一部分、第二部分和第四部分，所述第一部分设置于所述第一源漏极层，所述第二部分设置于所述第二源漏极层，所述第四部分设置于所述遮光层；
所述显示面板还包括第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层、第五绝缘层、有源层和第三金属层，所述第一绝缘层设置于所述半导体层和所述第一金属层之间，所述第二绝缘层设置于所述第一金属层和所述第二金属层之间，所述第三绝缘层设置于所述第二金属层和所述有源层之间，所述第四绝缘层设置于所述有源层和所述第三金属层之间，所述第五绝缘层设置于所述第三金属层和所述第一源漏极层之间，
其中，所述第二部分穿过所述第一平坦化层的过孔与所述第一部分连接，所述第一部分穿过所述第一绝缘层、所述第二绝缘层、所述第三绝缘层、所述第四绝缘层和所述第五绝缘层的过孔与所述第四部分连接，所述第四部分在所述衬底上的投影与所述栅极驱动电路在所述衬底上的投影存在重合，且所述第四部分的宽度大于所述第一部分的宽度，所述第四部分的宽度大于所述第二部分的宽度。
同时，本申请实施例提供一种显示装置，该显示装置包括显示面板和驱动芯片，所述显示面板包括：
显示区，所述显示区设有像素发光单元和控制所述像素发光单元的像素驱动电路；
非显示区，位于所述显示区外围，所述非显示区包括栅极驱动电路区，所述非显示区设有复位信号线和低电位信号线；
其中，所述复位信号线连接至所述像素驱动电路，所述低电位信号线与像素发光单元连接，所述栅极驱动电路区设有栅极驱动电路，所述复位信号线和所述低电位信号线中的至少一个的至少部分设置于所述栅极驱动电路区，且所述复位信号线和所述低电位信号线与所述栅极驱动电路绝缘设置。
在一些实施例中，所述栅极驱动电路包括多层金属层，所述复位信号线与所述低电位信号线中的至少部分与所述栅极驱动电路中的任一金属层异层设置。
在一些实施例中，所述显示面板包括：
衬底；
半导体层，设置于所述衬底一侧；
第一金属层，设置于所述半导体层远离所述衬底的一侧；
第二金属层，设置于所述第一金属层远离所述半导体层的一侧；
第一源漏极层，设置于所述第二金属层远离所述第一金属层的一侧；
第二源漏极层，设置于所述第一源漏极层远离所述第二金属层的一侧；
其中，所述栅极驱动电路包括晶体管和电容，所述晶体管包括栅极、源极和漏极，所述电容包括电容极板，所述栅极设置于所述第一金属层，所述电容极板设置于所述第二金属层，所述源极和所述漏极设置于所述第一源漏极层，所述复位信号线和所述低电位信号线中的至少部分与所述栅极驱动电路中的位于所述第一金属层、第二金属层、第一源漏极层和第二源漏极层的金属异层设置。
在一些实施例中，所述显示面板还包括第三源漏极层、第一平坦化层和第二平坦化层，所述第三源漏极层设置于所述第二源漏极层远离所述第一源漏极层的一侧，所述第一平坦化层设置于所述第一源漏极层和所述第二源漏极层之间，所述第二平坦化层设置于所述第二源漏极层和所述第三源漏极层之间；所述复位信号线和所述低电位信号线中的至少一个包括设置于所述第三源漏极层的第一重合部分，且所述第一重合部分在所述衬底上的投影与所述栅极驱动电路在所述衬底上的投影存在重合。
在一些实施例中，所述复位信号线设置于所述第三源漏极层，所述复位信号线在所述衬底上的投影与所述栅极驱动电路在所述衬底上的投影存在重合。
在一些实施例中，所述复位信号线在所述衬底上的投影与所述源极在所述衬底上的投影存在重合，或者所述复位信号线在所述衬底上的投影与所述漏极在所述衬底上的投影存在重合，或者所述复位信号线在所述衬底上的投影与所述栅极在所述衬底上的投影存在重合，或者所述复位信号线在所述衬底上的投影与所述电容极板在所述衬底上的投影存在重合。
在一些实施例中，所述像素驱动电路包括第一复位晶体管和第二复位晶体管，所述第二源漏极层包括连接金属，所述复位信号线穿过所述第二平坦化层的过孔连接至连接金属，所述连接金属从所述栅极驱动电路区延伸至所述显示区并与所述第一复位晶体管和所述第二复位晶体管连接。
 有益效果
本申请提供一种显示面板和显示装置；该显示面板包括显示区和非显示区，显示区设有像素发光单元和控制像素发光单元的像素驱动电路，非显示区位于显示区外围，非显示区包括栅极驱动电路区，非显示区设有复位信号线和低电位信号线，其中，复位信号线连接至像素驱动电路，低电位信号线与像素发光单元连接，栅极驱动电路设置于设有栅极驱动电路，复位信号线和低电位信号线中的至少一个的至少部分设置于栅极驱动电路区，且复位信号线和低电位信号线与栅极驱动电路绝缘设置。本申请通过使复位信号线和低电位信号线中的至少一个的至少部分设置于栅极驱动电路区，则至少可以减小复位信号线和低电位信号线设置在栅极驱动电路区的部分占用的面积，减小该部分需要的边框的宽度，从而减小了显示面板的边框，且该方案无需将栅极驱动电路设置在发光单元上，减小显示面板制备的工艺难度，提高显示面板的良率。
 附图说明
图1为本申请实施例提供的显示面板的第一种示意图。
图2为本申请实施例提供的显示面板的电路图。
图3为本申请实施例提供的显示面板的第二种示意图。
图4为本申请实施例提供的当前显示器件和本申请的显示面板的各部件的设置区域的对比图。
图5为本申请实施例提供的显示面板的第一种透视图。
图6为本申请实施例提供的显示面板的第二种透视图。
图7为本申请实施例提供的显示面板的第三种透视图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例针对现有显示器件存在将发光单元设置在栅极驱动电路上会导致显示器件的良率较低的技术问题，提供一种显示面板和显示装置，用以缓解上述技术问题。
如图1、图2所示，本申请实施例提供一种显示面板，该显示面板1包括：
显示区181，所述显示区181设有像素发光单元LED和控制所述像素发光单元LED的像素驱动电路21；
非显示区182，位于所述显示区181外围，所述非显示区182包括栅极驱动电路区183，所述非显示区182设有复位信号线171和低电位信号线16；
其中，所述复位信号线171连接至所述像素驱动电路21，所述低电位信号线16与所述像素发光单元LED连接，所述栅极驱动电路区183设有栅极驱动电路22，所述复位信号线171和所述低电位信号线16中的至少一个的至少部分设置于所述栅极驱动电路区183，且所述复位信号线171和所述低电位信号线16与所述栅极驱动电路22绝缘设置。
本申请实施例提供一种显示面板，该显示面板通过使复位信号线和低电位信号线中的至少一个的至少部分设置于栅极驱动电路区，则至少可以减小复位信号线和低电位信号线设置在栅极驱动电路区的部分占用的面积，减小该部分需要的边框的宽度，从而减小了显示面板的边框，且该方案无需将栅极驱动电路设置在发光单元上，减小显示面板制备的工艺难度，提高显示面板的良率。
需要说明的是，图1为显示面板的截面图，因此，图1中未示出单个子像素的所有元器件，仅示出了部分晶体管、走线以及电容，因此，可以理解的是，图1中的像素驱动电路不仅包括两个晶体管，还包括其他元器件；同理，图1示出的栅极驱动电路不仅包括单个晶体管，还包括其他元器件，具体的，像素驱动电路包括的元器件可以为图2中的电路示出的多个元器件。
需要说明的是，在图1所示的截面图中，对低电位信号线以标号16进行标示，在图2所示的电路图中，对低电位信号线以ELVSS进行标示，此处仅为不同图示中不同的标示方式，实际上图1所示的截面图中低电位信号线对应图2所示的电路图中低电位信号线，同理，其他截面图和电路图中存在不同标示方式的元件也是同一元件，在此不再赘述。
需要说明的是，复位信号线和低电位信号线在栅极驱动电路所处平面的投影是指复位信号线和低电位信号线在栅极驱动电路中任一金属层所处的平面的投影，以栅极驱动电路包括栅极层的金属为例，则该投影可以为复位信号线和低电位信号线在栅极层的投影，该投影位于栅极驱动电路区，且与栅极驱动电路绝缘，即复位信号线和低电位信号线中的至少一个的部分设置在栅极驱动电路区，与栅极驱动电路的投影存在重叠，即减小了复位信号线和低电位信号线中的至少一个占用的边框的宽度，减小了显示面板的边框。
需要说明的是，以LED标示像素发光单元，但本申请并不限定像素发光单元为发光二极管，像素发光单元可以为有机发光二极管。
在一种实施例中，所述栅极驱动电路包括晶体管，所述像素驱动电路包括连接走线，所述复位信号线通过所述连接走线连接至所述像素驱动电路，所述连接走线的至少部分设置于所述晶体管所处的金属层中的一金属层，通过使连接走线的至少部分设置于晶体管所处金属层中的一金属层，使得连接走线无需增加金属层，避免增加显示面板的厚度。
在一种实施例中，所述像素驱动电路包括连接走线，所述复位信号线通过所述连接走线连接至所述像素驱动电路，所述连接走线从所述栅极驱动电路区延伸至所述显示区，所述连接走线与所述复位信号线设置于同一金属层，通过将连接走线与复位信号线设置于同一层，使得在形成连接走线时，无需增加金属层，避免增加显示面板的厚度，且可以通过刻蚀同时形成连接走线和复位信号线，避免增加工艺难度。
在一种实施例中，所述显示面板包括连接孔，所述连接孔设置于所述显示区，且所述连接孔位于所述像素驱动电路上，所述连接走线穿过所述连接孔。通过将连接孔设置在显示区，且可以设置在像素驱动电路上，连接走线通过与复位信号线采用同一金属层形成，使得可以直接将连接走线通过连接孔连接至像素驱动电路，无需更改连接孔的位置，减小工艺复杂性。
在一种实施例中，所述栅极驱动电路包括多层金属层，所述复位信号线与所述低电位信号线中的至少部分与所述栅极驱动电路中的任一金属层异层设置。通过使复位信号线和低电位信号线与栅极驱动电路中的任一金属异层设置，则在设置栅极驱动电路区设置复位信号线和低电位信号线减小边框时，复位信号线和低电位信号线不会设置在栅极驱动电路所处的膜层，从而可以避免复位信号线和低电位信号线与栅极驱动电路中的金属产生短路或者干扰。
针对栅极驱动电路中各膜层的空闲空间较小，设置复位信号线或者低电位信号线会导致信号干扰或者短路等问题。在一种实施例中，如图1所示，所述显示面板1包括:
衬底11；
半导体层141，设置于所述衬底11一侧；
第一金属层143，设置于所述半导体层141远离所述衬底11的一侧；
第二金属层145，设置于所述第一金属层143远离所述半导体层141的一侧；
第一源漏极层151，设置于所述第二金属层145远离所述第一金属层143的一侧；
第二源漏极层153，设置于所述第一源漏极层151远离所述第二金属层145的一侧；
其中，所述栅极驱动电路22包括晶体管和电容，所述晶体管包括栅极143a、源极151d和漏极151b，所述电容包括电容极板145a，所述栅极143a设置于所述第一金属层143，所述电容极板145a设置于所述第二金属层145，所述源极151d和所述漏极151b设置于所述第一源漏极层151，所述复位信号线171和所述低电位信号线16中的至少部分与所述栅极驱动电路22中位于所述第一金属层143、第二金属层145、第一源漏极层151和第二源漏极层153的金属异层设置。
以图1示出的显示面板为例，从图1中可以看到，复位信号线171和低电位信号线16与栅极驱动电路22中的任一金属异层设置，则在设置栅极驱动电路区设置复位信号线和低电位信号线减小边框时，复位信号线和低电位信号线不会设置在栅极驱动电路所处的膜层，从而可以避免复位信号线和低电位信号线与栅极驱动电路中的金属产生短路或者干扰。
具体的，从图1可以看到，栅极驱动电路包括晶体管和电容，晶体管包括栅极、源极、漏极，电容包括电容极板，因此，在复位信号线和低电位信号线中设置在栅极驱动电路的部分设置在这些元件所处的膜层时，会导致短路或者干扰，本申请实施例通过将复位信号线和低电位信号线设置在其他膜层，避免复位信号线与低电位信号线与栅极驱动电路中的元器件产生干扰，导致信号不良。
需要说明的是，本申请实施例中仅限定了复位信号线和所述低电位信号线中处于栅极驱动电路区的部分与所述栅极驱动电路中的金属异层设置，对于复位信号线和低电位信号线处于栅极驱动电路区外的部分，不进行限定，例如从图1可以看到低电位信号线还包括设置于第一源漏极层的部分。
针对复位信号线或者低电位信号线设置在栅极驱动电路中金属所处膜层会导致信号干扰或者短路的问题。在一种实施例中，如图1所示，所述显示面板1还包括第三源漏极层154、第一平坦化层152和第二平坦化层155，所述第三源漏极层154设置于所述第二源漏极层153远离所述第一源漏极层151的一侧，所述第一平坦化层152设置于所述第一源漏极层151和所述第二源漏极层153之间，所述第二平坦化层155设置于所述第二源漏极层153和所述第三源漏极层154之间；所述复位信号线171和所述低电位信号线16中的至少一个包括设置于所述第三源漏极层154的第一重合部分，且所述第一重合部分在所述衬底11上的投影与所述栅极驱动电路22在所述衬底11上的投影存在重合。通过新增第三源漏极层，使得复位信号线和低电位信号线可以设置在第三源漏极层，不会与栅极驱动电路的金属处于同一膜层，从而避免栅极驱动电路内的金属（例如栅极）与复位信号线和低电位信号线产生干扰或者短路，导致栅极驱动电路和像素驱动电路的信号传输错误，且通过新增的第三源漏极层形成复位信号线和低电位信号线，可以增大复位信号线和低电位信号线的宽度，减小复位信号线和低电位信号线的阻抗。
具体的，第一重合部分是指复位信号线和低电位信号线中处于栅极驱动电路区的部分，以图1为例，复位信号线的各个部分均位于栅极驱动电路区，则复位信号线的第一重合部分指复位信号线的整体，低电位信号线仅有部分处于栅极驱动电路区，则低电位信号线的第一重合部分是指低电位信号线的第三部分163处于栅极驱动电路区的部分。
针对复位信号线设置在第二源漏极层会导致显示面板的边框较大的问题。在一种实施例中，如图1所示，所述复位信号线171设置于所述第三源漏极层154，所述复位信号线171在所述衬底11上的投影与所述栅极驱动电路22在所述衬底11上的投影存在重合。通过将复位信号线设置在第三源漏极层，可以减小边框的宽度，且该过程通过过孔将第三源漏极层的金属连接至第二源漏极层以及其他金属层，不会导致制程风险，提高显示面板的良率。
具体的，由于复位信号线的宽度较小，因此可以将复位信号线整体设置在栅极驱动电路上，从而消除复位信号线占用的边框的宽度，减小显示面板的边框。
在一种实施例中，所述复位信号线在所述衬底上的投影与所述源极在所述衬底上的投影存在重合，或者所述复位信号线在所述衬底上的投影与所述漏极在所述衬底上的投影存在重合，或者所述复位信号线在所述衬底上的投影与所述栅极在所述衬底上的投影存在重合，或者所述复位信号线在所述衬底上的投影与所述电容极板在所述衬底上的投影存在重合。在第三源漏极层设置复位信号线时，由于复位信号线的宽度较小，无需占用栅极驱动电路区的所有面积，因此，复位信号线可以与源极、漏极、栅极和电容极板在衬底上的投影存在重合，从而使得复位信号线处于栅极驱动电路所处区域，无需设置复位信号线对应的边框区域，减小显示面板的边框。
具体的，所述复位信号线在所述衬底上的投影与所述栅极在所述衬底上的投影存在重合，针对复位信号线设置的第三源漏极层，可能与第二源漏极层的金属之间产生寄生电容的问题，可以使复位信号线与栅极在衬底上的投影存在重合，由于复位信号线和栅极所处膜层的间距较大，减小寄生电容产生的可能性，避免复位信号线与其他金属之间出现寄生电容对信号产生干扰。
在一种实施例中，所述像素驱动电路包括第一复位晶体管和第二复位晶体管，所述第一源漏极层包括连接金属，所述复位信号线穿过所述第二平坦化层的过孔连接至连接金属，所述连接金属从所述栅极驱动电路区延伸至所述显示区并与所述第一复位晶体管和所述第二复位晶体管连接。通过使第一源漏极层形成连接金属，使得连接金属可以连接复位信号线以及第一复位晶体管和第二复位晶体管，实现复位信号线的正常工作。
具体的，在复位信号线设置在第三源漏极层时，可以在栅极驱动电路区将复位信号线连接至第二源漏极层，然后将复位信号线通过第二源漏极层的连接金属延伸至显示区，并在显示区与第一复位晶体管和第二复位晶体管的源漏极进行连接，实现对第一复位晶体管和第二复位晶体管的信号输入。
在一种实施例中，如图2所示，复位信号线包括第一复位信号线VI-G和第二复位信号线VI-ANO，所述第一复位信号线VI-G和所述第二复位信号线VI-ANO中的至少一个设置于所述第三源漏极层，且所述第一复位信号线VI-G和所述第二复位信号线VI-ANO中设置于所述第三源漏极层的部分在所述衬底上的投影与所述栅极驱动电路在所述衬底上的投影存在重合。
对于具有多个复位信号线的显示面板，可以将各复位信号线均设置于第三源漏极层，使各复位信号线设置于栅极驱动电路区，减小各复位信号线占用的边框的宽度。
针对低电位信号线设置在第一源漏极层和第二源漏极层会导致显示面板的边框较大的问题。在一种实施例中，所述低电位信号线设置于第三源漏极层，所述低电位信号线在所述衬底上的投影与所述栅极驱动电路在所述衬底上的投影存在重合。通过将低电位信号线设置在第三源漏极层，可以使得低电位信号线占用的边框的宽度减小，从而减小显示面板的边框，且可以通过第三源漏极层减小低电位信号线的阻抗，从而进一步减小显示面板的边框。
针对低电位信号线的宽度较大导致低电位信号线占用的边框的宽度较大的问题。在一种实施例中，如图1所示，所述低电位信号线16包括第一部分161、第二部分162和第三部分163，所述第一部分161设置于所述第一源漏极层151，所述第二部分162设置于所述第二源漏极层153，所述第三部分163设置于所述第三源漏极层154，所述第二部分162穿过所述第一平坦化层152的过孔与所述第一部分161连接，所述第三部分163穿过所述第二平坦化层155的过孔与所述第二部分162连接，所述第三部分163在所述衬底11上的投影与所述栅极驱动电路22在所述衬底11上的投影存在重合，且所述第三部分163的宽度大于所述第一部分161的宽度，所述第三部分163的宽度大于所述第二部分162的宽度。
通过将低电位信号线设置为第一部分、第二部分和第三部分，则可以通过连接的第一部分、第二部分和第三部分传输信号至显示区，使低电位信号线正常工作，而第三部分设置在第三源漏极层，且第三部分与栅极驱动电路在衬底上的投影存在重合，则可以减小第三部分占用的边框的宽度，而由于第三部分从第一部分和第二部分所处的低电位信号线设置区延伸至栅极驱动电路区，第三部分的宽度较大，减小了低电位信号线的阻抗，且第三部分与第二部分并联连接，第二部分与第一部分并联连接，进一步减小了低电位信号线的阻抗，使低电位信号线的阻抗满足驱动要求甚至减小低电位信号线的阻抗，从而可以减小第一部分和第二部分的宽度，减小低电位信号线占用的边框的宽度，从而减小显示面板的边框的宽度。
具体的，如图1所示，非显示区182还包括低电位信号线区184，第一部分161和第二部分162设置于低电位信号线区184，第三部分163从低电位信号线区184延伸至栅极驱动电路区183，减小了显示面板的边框的宽度。
上述实施例分别以复位信号线和低电位信号线设置在第三源漏极层为例进行了详细说明，可以理解的是，可以同时将复位信号线和低电位信号线设置在第三源漏极层，以进一步减小显示面板的边框，此时仅需要使复位信号线和低电位信号线绝缘设置即可，复位信号线和低电位信号线的设置方式可以如上述实施例所述进行设置，在此不再赘述。
针对将复位信号线和低电位信号线设置在第三源漏极层仍然会导致边框较大的问题。在一种实施例中，所述显示面板还包括第四源漏极层，所述第四源漏极层设置于所述第三源漏极层远离所述第二源漏极层的一侧，所述复位信号线设置于所述第四源漏极层，且所述复位信号线在所述衬底上的投影与所述第三部分在所述衬底上的投影存在重合。通过将复位信号线设置在第四源漏极层，则低电位信号线的第三部分可以设置在栅极驱动电路的所有区域，从而进一步减小低电位信号线占用的边框的宽度，而复位信号线设置在第四源漏极层，也可以减小复位信号线占用的边框的宽度，使得显示面板的边框无需设置复位信号线的设置区域，且设置的低电位信号设置区的宽度较小，进一步减小显示面板的边框。
具体的，在将复位信号线设置在第四源漏极层时，可以分别在第三源漏极层和第二源漏极层设置连接金属，使复位信号线连接到第三源漏极层的连接金属、然后连接到第二源漏极层的连接金属，并通过将连接金属延伸至显示区，与第一复位晶体管和第二复位晶体管的源漏极连接，实现对第一复位晶体管和第二复位晶体管的信号输入。
针对新增膜层设置复位信号线和低电位信号线会导致显示面板的厚度较大的技术问题。在一种实施例中，如图3所示，所述显示面板1还包括遮光层12，所述遮光层12设置于所述衬底11与所述半导体层141之间，所述复位信号线171和所述低电位信号线16中的至少一个包括设置于所述遮光层12的第二重合部分，且所述第二重合部分在所述衬底11上的投影与所述栅极驱动电路22在所述衬底11上的投影存在重合。通过将复位信号线和低电位信号线中在至少一个设置在遮光层，则可以减小复位信号线和低电位信号线占用的空间，减小显示面板的边框，且不会与栅极驱动电路的金属处于同一膜层，从而避免栅极驱动电路内的金属（例如栅极）与复位信号线和低电位信号线产生干扰或者短路，而通过遮光层形成复位信号线和低电位信号线，可以增大复位信号线和低电位信号线的宽度，减小复位信号线和低电位信号线的阻抗。
具体的，第二重合部分是指复位信号线和低电位信号线中处于栅极驱动电路区的部分，以图3为例，复位信号线的各个部分均位于栅极驱动电路区，则复位信号线的第二重合部分指复位信号线的整体；同理，低电位信号线的第二重合部分是指低电位信号线处于栅极驱动电路区的部分。
在一种实施例中，如图3所示，所述复位信号线171设置于所述遮光层12，且所述复位信号线171在所述衬底11上的投影与所述栅极驱动电路22在所述衬底11上的投影存在重合。通过将复位信号线设置在遮光层，可以减小复位信号线占用的边框的宽度，从而减小显示面板的边框，且由于无需增加膜层，不会增加显示面板的厚度。
具体的，在复位信号线设置在遮光层时，可以使第二源漏极层形成连接金属，并通过连接金属穿过各绝缘层和平坦化层连接至复位信号线，并通过连接金属延伸至显示区，然后连接至第一复位晶体管和第二复位晶体管，实现对第一复位晶体管和第二复位晶体管的信号输入。
在一种实施例中，所述低电位信号线包括第一部分、第二部分和第四部分，所述第一部分设置于所述第一源漏极层，所述第二部分设置于所述第二源漏极层，所述第四部分设置于所述遮光层；
所述显示面板还包括第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层、第五绝缘层、有源层和第三金属层，所述第一绝缘层设置于所述半导体层和所述第一金属层之间，所述第二绝缘层设置于所述第一金属层和所述第二金属层之间，所述第三绝缘层设置于所述第二金属层和所述有源层之间，所述第四绝缘层设置于所述有源层和所述第三金属层之间，所述第五绝缘层设置于所述第三金属层和所述第一源漏极层之间，
其中，所述第二部分穿过所述第一平坦化层的过孔与所述第一部分连接，所述第一部分穿过所述第一绝缘层、所述第二绝缘层、所述第三绝缘层、所述第四绝缘层和所述第五绝缘层的过孔与所述第四部分连接，所述第四部分在所述衬底上的投影与所述栅极驱动电路在所述衬底上的投影存在重合，且所述第四部分的宽度大于所述第一部分的宽度，所述第四部分的宽度大于所述第二部分。
通过将低电位信号线设置为第一部分、第二部分和第四部分，则可以通过连接的第一部分、第二部分和第四部分传输信号至显示区，使低电位信号线正常工作，而第四部分设置于遮光层，且第四部分与栅极驱动电路在衬底上的投影存在重合，则可以减小第四部分占用的边框的宽度，而由于第四部分从第一部分和第二部分所处的低电位信号线设置区延伸至栅极驱动电路区，第四部分的宽度较大，减小了低电位信号线的阻抗，使低电位信号线的阻抗满足驱动要求甚至减小低电位信号线的阻抗，从而可以减小第一部分和第二部分的宽度，减小低电位信号线占用的边框的宽度，从而减小显示面板的边框的宽度，且该设置方式无需新增膜层，不会增加显示面板的厚度。
具体的，在低电位信号线的第四部分设置于遮光层时，对于遮光层与第一源漏极层之间的间距较大，金属容易在过孔内断裂的问题，可以通过其他膜层进行转接，例如通过第一金属层进行转接，本申请实施例对此并不限定，以能够实现低电位信号线的正常连接为基准。
上述实施例分别以复位信号线和低电位信号线设置在遮光层为例进行了详细说明，可以理解的是，为了进一步减小边框，可以将复位信号线和低电位信号线设置在遮光层，此时仅需要使复位信号线和低电位信号线绝缘设置即可，复位信号线和低电位信号线的设置方式可以如上述实施例所述进行设置，在此不再赘述。
同时，对于新增第三源漏极层时，还可以通过将复位信号线设置在遮光层，将低电位信号线的第三部分设置在第三源漏极层，或者通过将复位信号线设置在第三源漏极层，将低电位信号线设置在遮光层，增大低电位信号线占用的栅极驱动电路区的宽度，进一步减小低电位信号线占用的边框的宽度，进一步减小显示面板的边框的宽度。
如图4所示，图4中的（a）为当前显示器件的各部件的设置区域的示意图，图4中的（b）为本申请显示面板的各部分的设置区域的示意图。从图4中的（a）可以看到，在显示区214外，需要分别设置栅极驱动电路设置区212、低电位信号线设置区211和复位信号线设置区213，导致显示器件的边框较大。而本申请通过将低电位信号线和复位信号线设置在栅极驱动电路区，如图4中的（b）所示，可以看到低电位信号线设置区221和栅极驱动电路区183存在重叠，复位信号线设置区222位于栅极驱动电路区183内，减小了显示面板的边框。
如图2所示，像素驱动电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第一复位晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6、第二复位晶体管T7、存储电容Cst、升压电容Cboost、高电位信号线ELVDD、数据线Data、第一扫描线P Scan（n）、第二扫描线P Scan（n-1）、第三扫描线N Scan（n）、第四扫描线N Scan（n-5）和发光控制线EM。
其中，P Scan（n）表示本级扫描线，P Scan（n-1）表示上一级扫描线，且上述扫描线用于控制P型晶体管，N Scan（n）表示本级扫描线，N Scan（n-5）表示上五级扫描线，且这两条扫描线用于控制N型晶体管。
电路的工作原理如下：在第一阶段，第一复位晶体管T4和第二复位晶体管T7打开，通过第一复位信号线VI-G输出的复位信号对第一晶体管T1的栅极复位，通过第二复位信号线VI-ANO输出的复位信号对像素发光单元LED复位；在第二阶段，第二晶体管T2和第三晶体管T3打开，将数据线Data输入的数据信号写入第一晶体管T1栅极；在第三阶段，第一发光控制晶体管T5和第二发光控制晶体管T6打开，驱动像素发光单元LED发光。
本申请实施例以图2中的电路图为例进行了详细说明，但本申请实施例不限于此，例如采用7T1C（7个晶体管一个电容）电路的显示面板也可以采用本申请的设计。
在一种实施例中，为了提高显示面板的柔性和阻隔水氧的能力，如图1所示，衬底11包括第一柔性层111、阻挡层112和第二柔性层113，显示面板还包括缓冲层13。
在一种实施例中，如图1所示，所述显示面板还包括第一绝缘层142、第二绝缘层144、第三绝缘层146、第四绝缘层148和第五绝缘层150。
在一种实施例中，如图1所示，半导体层141包括半导体图案141a。
在一种实施例中，如图1所示，源极151d包括第一源极部分151a和第二源极部分151c。
在一种实施例中，如图1所示，显示面板还包括有源层147和第三金属层149，其中，半导体层的材料为低温多晶硅，有源层的材料为氧化物。
如图1所示，本申请实施例以LTPO技术为例说明了显示面板的结构，但本申请实施例不限于此，例如显示面板可以采用LTPS（Low Temperature Poly-silicon，低温多晶硅）技术。
具体的，对于图1所示的显示面板的透视结构，对第二源漏极层至第三源漏极层的具体设计进行详细说明。如图1、图2、图3、图4、图5、图6、图7所示，在非显示区，第二源漏极层153形成有源极151d的第二源极部分151c、低电位信号线的第二部分162以及连接金属，连接金属与第二源极部分151c和低电位信号线的第二部分162绝缘设置，连接金属在图中未示出。第二平坦化层155形成有位于连接金属上的过孔以及位于低电位信号线的第二部分162上的过孔，第三源漏极层154形成有复位信号线171和低电位信号线的第三部分163，复位信号线穿过第二平坦化层155的过孔与连接金属连接，然后连接金属向显示区延伸，并与第一复位晶体管和第二复位晶体管的电极连接，低电位信号线的第三部分163穿过第二平坦化层155的过孔与低电位信号线的第二部分162连接。
具体的，显示面板还包括第三平坦化层、像素电极层、发光材料层、像素定义层和公共电极层，第三平坦化层设置于第三源漏极层远离第二平坦化层的一侧，在栅极驱动电路区，像素电极层形成有转接金属，公共电极层穿过像素定义层的过孔连接至转接金属，转接金属穿过第三平坦化层的过孔连接至低电位信号的第三部分。
具体的，图5至图7为显示面板的栅极驱动电路区和低电位信号线区的透视区，图5为显示面板制备完成第二源漏极层后的透视图，图6为显示面板制备完成第二平坦化层后的透视图，图7为显示面板制备完成第三源漏极层后的示意图。
具体的，图5中以标号31表示第二源漏极层制备后，低电位信号线预留连接的位置，以标号32表示第二源漏极层制备后，复位信号线预留的连接位置。图6以标号33表示第二平坦化层制备后，低电位信号线的连接孔的位置，同时，在与图5中复位信号线预留的连接位置的相同位置设置复位信号线的连接孔的位置，图7中以标号34表示低电位信号线的第三部分与低点位信号线的第二部分的连接处，同时，在与图5中复位信号线预留的连接位置的相同位置将复位信号线与连接金属连接。
同时，本申请实施例提供一种显示装置，该显示装置包括上述实施例任一所述的显示面板和驱动芯片。
根据上述实施例可知：
本申请实施例提供一种显示面板和显示装置；该显示面板包括显示区和非显示区，显示区设有像素发光单元和控制像素发光单元的像素驱动电路，非显示区位于显示区外围，非显示区包括栅极驱动电路区，非显示区设有复位信号线和低电位信号线，其中，复位信号线连接至像素驱动电路，低电位信号线与像素发光单元连接，栅极驱动电路设置于设有栅极驱动电路，复位信号线和低电位信号线中的至少一个的至少部分设置于栅极驱动电路区，且复位信号线和低电位信号线与栅极驱动电路绝缘设置。本申请通过使复位信号线和低电位信号线中的至少一个的至少部分设置于栅极驱动电路区，则至少可以减小复位信号线和低电位信号线设置在栅极驱动电路区的部分占用的面积，减小该部分需要的边框的宽度，从而减小了显示面板的边框，且该方案无需将栅极驱动电路设置在发光单元上，减小显示面板制备的工艺难度，提高显示面板的良率。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种显示面板和显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种显示面板，其包括：
    显示区，所述显示区设有像素发光单元和控制所述像素发光单元的像素驱动电路；
    非显示区，位于所述显示区外围，所述非显示区包括栅极驱动电路区，所述非显示区设有复位信号线和低电位信号线；
    其中，所述复位信号线连接至所述像素驱动电路，所述低电位信号线与像素发光单元连接，所述栅极驱动电路区设有栅极驱动电路，所述复位信号线和所述低电位信号线中的至少一个的至少部分设置于所述栅极驱动电路区，且所述复位信号线和所述低电位信号线与所述栅极驱动电路绝缘设置。
  2. 如权利要求1所述的显示面板，其中，所述栅极驱动电路包括多层金属层，所述复位信号线与所述低电位信号线中的至少部分与所述栅极驱动电路中的任一金属层异层设置。
  3. 如权利要求1所述的显示面板，其中，所述显示面板包括：
    衬底；
    半导体层，设置于所述衬底一侧；
    第一金属层，设置于所述半导体层远离所述衬底的一侧；
    第二金属层，设置于所述第一金属层远离所述半导体层的一侧；
    第一源漏极层，设置于所述第二金属层远离所述第一金属层的一侧；
    第二源漏极层，设置于所述第一源漏极层远离所述第二金属层的一侧；
    其中，所述栅极驱动电路包括晶体管和电容，所述晶体管包括栅极、源极和漏极，所述电容包括电容极板，所述栅极设置于所述第一金属层，所述电容极板设置于所述第二金属层，所述源极和所述漏极设置于所述第一源漏极层，所述复位信号线和所述低电位信号线中的至少部分与所述栅极驱动电路中的位于所述第一金属层、第二金属层、第一源漏极层和第二源漏极层的金属异层设置。
  4. 如权利要求3所述的显示面板，其中，所述显示面板还包括第三源漏极层、第一平坦化层和第二平坦化层，所述第三源漏极层设置于所述第二源漏极层远离所述第一源漏极层的一侧，所述第一平坦化层设置于所述第一源漏极层和所述第二源漏极层之间，所述第二平坦化层设置于所述第二源漏极层和所述第三源漏极层之间；所述复位信号线和所述低电位信号线中的至少一个包括设置于所述第三源漏极层的第一重合部分，且所述第一重合部分在所述衬底上的投影与所述栅极驱动电路在所述衬底上的投影存在重合。
  5. 如权利要求4所述的显示面板，其中，所述复位信号线设置于所述第三源漏极层，所述复位信号线在所述衬底上的投影与所述栅极驱动电路在所述衬底上的投影存在重合。
  6. 如权利要求5所述的显示面板，其中，所述复位信号线在所述衬底上的投影与所述源极在所述衬底上的投影存在重合，或者所述复位信号线在所述衬底上的投影与所述漏极在所述衬底上的投影存在重合，或者所述复位信号线在所述衬底上的投影与所述栅极在所述衬底上的投影存在重合，或者所述复位信号线在所述衬底上的投影与所述电容极板在所述衬底上的投影存在重合。
  7. 如权利要求5所述的显示面板，其中，所述像素驱动电路包括第一复位晶体管和第二复位晶体管，所述第二源漏极层包括连接金属，所述复位信号线穿过所述第二平坦化层的过孔连接至连接金属，所述连接金属从所述栅极驱动电路区延伸至所述显示区并与所述第一复位晶体管和所述第二复位晶体管连接。
  8. 如权利要求4所述的显示面板，其中，所述低电位信号线设置于所述第三源漏极层，所述低电位信号线在所述衬底上的投影与所述栅极驱动电路在所述衬底上的投影存在重合。
  9. 如权利要求8所述的显示面板，其中，所述低电位信号线包括第一部分、第二部分和第三部分，所述第一部分设置于所述第一源漏极层，所述第二部分设置于所述第二源漏极层，所述第三部分设置于所述第三源漏极层，所述第二部分穿过所述第一平坦化层的过孔与所述第一部分连接，所述第三部分穿过所述第二平坦化层的过孔与所述第二部分连接，所述第三部分在所述衬底上的投影与所述栅极驱动电路在所述衬底上的投影存在重合，且所述第三部分的宽度大于所述第一部分的宽度，所述第三部分的宽度大于所述第二部分的宽度。
  10. 如权利要求9所述的显示面板，其中，所述显示面板还包括第四源漏极层，所述第四源漏极层设置于所述第三源漏极层远离所述第二源漏极层的一侧，所述复位信号线设置于所述第四源漏极层，且所述复位信号线在所述衬底上的投影与所述第三部分在所述衬底上的投影存在重合。
  11. 如权利要求3所述的显示面板，其中，所述显示面板还包括遮光层，所述遮光层设置于所述衬底与所述半导体层之间，所述复位信号线和所述低电位信号线中的至少一个包括设置于所述遮光层的第二重合部分，且所述第二重合部分在所述衬底上的投影与所述栅极驱动电路在所述衬底上的投影存在重合。
  12. 如权利要求11所述的显示面板，其中，所述复位信号线设置于所述遮光层，且所述复位信号线在所述衬底上的投影与所述栅极驱动电路在所述衬底上的投影存在重合。
  13. 如权利要求11所述的显示面板，其中，所述低电位信号线包括第一部分、第二部分和第四部分，所述第一部分设置于所述第一源漏极层，所述第二部分设置于所述第二源漏极层，所述第四部分设置于所述遮光层；
    所述显示面板还包括第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层、第五绝缘层、有源层和第三金属层，所述第一绝缘层设置于所述半导体层和所述第一金属层之间，所述第二绝缘层设置于所述第一金属层和所述第二金属层之间，所述第三绝缘层设置于所述第二金属层和所述有源层之间，所述第四绝缘层设置于所述有源层和所述第三金属层之间，所述第五绝缘层设置于所述第三金属层和所述第一源漏极层之间，
    其中，所述第二部分穿过所述第一平坦化层的过孔与所述第一部分连接，所述第一部分穿过所述第一绝缘层、所述第二绝缘层、所述第三绝缘层、所述第四绝缘层和所述第五绝缘层的过孔与所述第四部分连接，所述第四部分在所述衬底上的投影与所述栅极驱动电路在所述衬底上的投影存在重合，且所述第四部分的宽度大于所述第一部分的宽度，所述第四部分的宽度大于所述第二部分的宽度。
  14. 一种显示装置，其包括显示面板和驱动芯片，所述显示面板包括：
    显示区，所述显示区设有像素发光单元和控制所述像素发光单元的像素驱动电路；
    非显示区，位于所述显示区外围，所述非显示区包括栅极驱动电路区，所述非显示区设有复位信号线和低电位信号线；
    其中，所述复位信号线连接至所述像素驱动电路，所述低电位信号线与像素发光单元连接，所述栅极驱动电路区设有栅极驱动电路，所述复位信号线和所述低电位信号线中的至少一个的至少部分设置于所述栅极驱动电路区，且所述复位信号线和所述低电位信号线与所述栅极驱动电路绝缘设置。
  15. 如权利要求14所述的显示装置，其中，所述栅极驱动电路包括多层金属层，所述复位信号线与所述低电位信号线中的至少部分与所述栅极驱动电路中的任一金属层异层设置。
  16. 如权利要求14所述的显示装置，其中，所述显示面板包括：
    衬底；
    半导体层，设置于所述衬底一侧；
    第一金属层，设置于所述半导体层远离所述衬底的一侧；
    第二金属层，设置于所述第一金属层远离所述半导体层的一侧；
    第一源漏极层，设置于所述第二金属层远离所述第一金属层的一侧；
    第二源漏极层，设置于所述第一源漏极层远离所述第二金属层的一侧；
    其中，所述栅极驱动电路包括晶体管和电容，所述晶体管包括栅极、源极和漏极，所述电容包括电容极板，所述栅极设置于所述第一金属层，所述电容极板设置于所述第二金属层，所述源极和所述漏极设置于所述第一源漏极层，所述复位信号线和所述低电位信号线中的至少部分与所述栅极驱动电路中的位于所述第一金属层、第二金属层、第一源漏极层和第二源漏极层的金属异层设置。
  17. 如权利要求16所述的显示装置，其中，所述显示面板还包括第三源漏极层、第一平坦化层和第二平坦化层，所述第三源漏极层设置于所述第二源漏极层远离所述第一源漏极层的一侧，所述第一平坦化层设置于所述第一源漏极层和所述第二源漏极层之间，所述第二平坦化层设置于所述第二源漏极层和所述第三源漏极层之间；所述复位信号线和所述低电位信号线中的至少一个包括设置于所述第三源漏极层的第一重合部分，且所述第一重合部分在所述衬底上的投影与所述栅极驱动电路在所述衬底上的投影存在重合。
  18. 如权利要求17所述的显示装置，其中，所述复位信号线设置于所述第三源漏极层，所述复位信号线在所述衬底上的投影与所述栅极驱动电路在所述衬底上的投影存在重合。
  19. 如权利要求18所述的显示装置，其中，所述复位信号线在所述衬底上的投影与所述源极在所述衬底上的投影存在重合，或者所述复位信号线在所述衬底上的投影与所述漏极在所述衬底上的投影存在重合，或者所述复位信号线在所述衬底上的投影与所述栅极在所述衬底上的投影存在重合，或者所述复位信号线在所述衬底上的投影与所述电容极板在所述衬底上的投影存在重合。
  20. 如权利要求18所述的显示装置，其中，所述像素驱动电路包括第一复位晶体管和第二复位晶体管，所述第二源漏极层包括连接金属，所述复位信号线穿过所述第二平坦化层的过孔连接至连接金属，所述连接金属从所述栅极驱动电路区延伸至所述显示区并与所述第一复位晶体管和所述第二复位晶体管连接。
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