WO2020057020A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2020057020A1
WO2020057020A1 PCT/CN2019/070924 CN2019070924W WO2020057020A1 WO 2020057020 A1 WO2020057020 A1 WO 2020057020A1 CN 2019070924 W CN2019070924 W CN 2019070924W WO 2020057020 A1 WO2020057020 A1 WO 2020057020A1
Authority
WO
WIPO (PCT)
Prior art keywords
metal layer
display panel
substrate
traces
display
Prior art date
Application number
PCT/CN2019/070924
Other languages
English (en)
French (fr)
Inventor
江国栋
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/318,101 priority Critical patent/US11150527B2/en
Publication of WO2020057020A1 publication Critical patent/WO2020057020A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel and a display device.
  • the non-display area of the display ie, the bezel
  • the non-display area of the display is designed to be narrower and narrower.
  • the non-display area ie, the frame of the display module
  • the non-display area is used for peripheral circuit routing.
  • a series of thin film transistors in the display area can be connected and led to the outer lead terminal area of the lower frame, thereby connecting the outer lead terminal area to the driving chip.
  • peripheral circuit wiring it is also because of the existence of peripheral circuit wiring that the frame of the display module cannot be further reduced. Therefore, a new wiring method needs to be designed to solve this problem.
  • the embodiments of the present application provide a display panel and a display device, and the wiring is arranged in the display area to reduce the area occupied by the frame.
  • This application provides a display panel, including:
  • a substrate including a display area
  • a first metal layer including a plurality of scan lines
  • a second metal layer, the second metal layer including a plurality of first traces, and a projection of the plurality of first traces on the substrate is located in the display area;
  • a driving chip, at least a part of the scan lines are connected to the driving chip through the first trace.
  • the plurality of first lines are connected to the plurality of scanning lines in a one-to-one correspondence.
  • the plurality of scanning lines are arranged along a first direction
  • the plurality of first lines are arranged along a second direction
  • the first direction and the second direction are perpendicular to each other.
  • a first insulating layer is provided between the first metal layer and the second metal layer, and a plurality of first vias are provided on the first insulating layer.
  • the first trace is connected to a scan line through a first via.
  • the projections of the plurality of vias on the substrate are located on the substrate by projections of the plurality of scan lines and the plurality of first traces on the substrate. Intersection of projections on the map.
  • the display panel further includes: a third metal layer, the third metal layer includes a plurality of second traces; and the plurality of second traces on the substrate
  • the projection is located in the display area, and part of the scan lines are connected to the driving chip through the plurality of second traces.
  • a second insulating layer is provided between the first metal layer and the third metal layer, and a plurality of second vias are provided on the second insulating layer.
  • the second trace is connected to a scan line through a second via.
  • the first metal layer is disposed between the second metal layer and the third metal layer.
  • the display panel further includes a plurality of thin film transistors, and the gates of the plurality of thin film transistors are disposed on the same layer as the first metal layer, and one scan line and one The gate connection of the thin film transistor is described.
  • the present application further provides a display device including a display panel and a packaging cover provided on the display panel, wherein the display panel includes:
  • a substrate including a display area
  • a first metal layer including a plurality of scan lines
  • a second metal layer, the second metal layer including a plurality of first traces, and a projection of the plurality of first traces on the substrate is located in the display area;
  • a driving chip, at least a part of the scan lines are connected to the driving chip through the first trace.
  • the plurality of first traces are connected to the plurality of scan lines in a one-to-one correspondence.
  • the plurality of scanning lines are arranged in a first direction
  • the plurality of first lines are arranged in a second direction
  • the first direction and the second direction are perpendicular to each other.
  • a first insulating layer is provided between the first metal layer and the second metal layer, and a plurality of first vias are provided on the first insulating layer.
  • the first trace is connected to a scan line through a first via.
  • the projections of the plurality of first vias on the substrate are located at the projections of the plurality of scan lines on the substrate and the plurality of first traces are at The intersection of the projections on the substrate.
  • the present application provides a display panel including:
  • a substrate including a display area
  • a first metal layer including a plurality of scan lines
  • a second metal layer, the second metal layer including a plurality of first traces, and a projection of the plurality of first traces on the substrate is located in the display area;
  • a driving chip at least a part of the scan lines being connected to the driving chip through the first trace;
  • the display panel further includes a third metal layer, and the third metal layer includes a plurality of second traces; a projection of the plurality of second traces on the substrate is located in the display area, and Some of the scan lines are connected to the driving chip through the plurality of second traces; the display panel further includes a plurality of thin film transistors, and the gates of the plurality of thin film transistors are on the same layer as the first metal layer. And a scan line is connected to a gate of a thin film transistor.
  • the plurality of scanning lines are arranged along a first direction
  • the plurality of first lines are arranged along a second direction
  • the first direction and the second direction are perpendicular to each other.
  • a first insulating layer is provided between the first metal layer and the second metal layer, and a plurality of first vias are provided on the first insulating layer.
  • the first trace is connected to a scan line through a first via.
  • the projections of the plurality of first vias on the substrate are located at the projections of the plurality of scan lines on the substrate and the plurality of first traces are at The intersection of the projections on the substrate.
  • a second insulating layer is provided between the first metal layer and the third metal layer, and a plurality of second vias are provided on the second insulating layer.
  • the second trace is connected to a scan line through a second via.
  • the first metal layer is disposed between the second metal layer and the third metal layer.
  • the display panel provided in this application includes: a substrate, the substrate including a display area; a first metal layer, the first metal layer includes a plurality of scan lines; a second metal layer, the second metal layer includes a plurality of first A trace, and the projections of the plurality of first traces on the substrate are located in the display area; and a driving chip, at least a part of the scan lines are connected to the driving chip through the first trace
  • the first trace is set in the display area and a separate layer is formed, so that it no longer occupies the border area, which greatly reduces the area occupied by the border.
  • FIG. 1 is a schematic diagram of a three-dimensional structure of a display panel according to an embodiment of the present application
  • FIG. 2 is a schematic diagram of an equivalent circuit of a display driving structure and a pixel electrode layer provided by an embodiment of the present application;
  • FIG. 3 is another schematic diagram of an equivalent circuit of a display driving structure and a pixel electrode layer provided by an embodiment of the present application;
  • FIG. 4 is a cross-sectional view of a display panel according to an embodiment of the present application.
  • FIG. 5 is another cross-sectional view of a display panel provided by an embodiment of the present application.
  • FIG. 6 is another schematic diagram of an equivalent circuit of a display driving structure and a pixel electrode layer provided by an embodiment of the present application.
  • FIG. 1 is a schematic diagram of a three-dimensional structure of a display panel according to an embodiment of the present application.
  • the display panel 100 includes a color filter substrate 110, an array substrate 120, and a liquid crystal layer 130 between the color filter substrate 110 and the array substrate 120.
  • the color filter substrate 110 is provided with a color filter layer 112 on a side adjacent to the liquid crystal layer 130.
  • a display driving structure 121, a common electrode layer 122 and a pixel electrode layer 123 are disposed on a side of the array substrate 120 adjacent to the liquid crystal layer 130.
  • FIG. 2 is a schematic diagram of an equivalent circuit of a display driving structure and a pixel electrode layer provided by an embodiment of the present application.
  • the pixel electrode layer 123 includes a pixel electrode 1231 corresponding to each pixel of the display panel 100.
  • the display driving structure 121 includes a plurality of scanning lines 301, a plurality of data lines 1212, and a thin film transistor 1213 connected to the intersection of the scanning line and the data line.
  • the thin film transistor 1213 is also electrically connected to the pixel electrode 1231.
  • the common electrode layer 122 is configured to cooperate with the pixel electrode 1231 to form a planar electric field to drive the liquid crystal molecules to rotate in the plane.
  • the scan line 301 extends in a first direction X
  • the data line 1212 extends in a second direction Y different from the first direction X and intersects the scan line 301 to form a plurality of pixels 1233.
  • the first direction X may be perpendicular to the second direction Y, so that the plurality of pixels 1233 are arranged in a matrix.
  • Each pixel 1233 is provided with a thin film transistor 1213 and a pixel electrode 1231.
  • the thin film transistor 1213 is connected to the scan line 301, the data line 1212, and the pixel electrode 1231, respectively.
  • the display period drives the display panel 100 for screen display.
  • the display panel 100 further includes a scan drive circuit 142 electrically connected to the scan line 301 and a data drive circuit 144 electrically connected to the data line 1212.
  • the scan drive circuit 142 is configured to apply a scan drive signal during a display period.
  • the data driving circuit 144 is configured to apply a data driving signal to the data line 1212 during the display period.
  • the display panel 100 further includes a wiring 200 and a driving chip 50 arranged in the non-display area 102, and the scanning line 301 is connected to the driving chip 50 through the wiring 200.
  • the frame of the display panel cannot be further reduced.
  • FIG. 3 is an equivalent of a display driving structure and a pixel electrode layer provided by an embodiment of the present application.
  • FIG. 4 is a cross-sectional view of a display panel according to an embodiment of the present application.
  • the display panel includes a substrate 10 including a display area 101 and a first metal layer 30 including a plurality of scanning lines.
  • the substrate 10 may be a glass substrate, a highly thermally conductive aluminum substrate, or a substrate on which polyimide (Polyimide) is formed, or a TFT (Thin Film Transistor, thin film transistor) substrate, or an OLED (Organic Light Emitting Diode, Organic light emitting diode) substrate.
  • the substrate includes a display area 101 and a non-display area 102.
  • a plurality of first traces 201 originally provided in the non-display area 102 are disposed in the display area 101, thereby reducing the occupation of the non-display area 102. The area reduces the proportion of the non-display area 102.
  • the plurality of first traces 201 are made into a single layer, that is, the second metal layer 20.
  • the plurality of scan lines 301 and the plurality of first traces 201 are disposed on different layers, so that the plurality of scan lines 301 and the plurality of first traces 201 do not interfere with each other.
  • the multiple first traces 201 are connected to the multiple scan lines 301 one by one; and the multiple scan lines 301 are arranged along the first direction X, and the multiple first traces 201 are arranged along the second direction Y.
  • One direction X is perpendicular to the second direction Y, so that each first trace 201 and each scan line 301 can have the largest contact area, and also, the first traces 201 can not be entangled with each other. Avoid mutual interference.
  • first direction X refers to the arrangement direction of the first trace 201
  • second direction Y refers to the arrangement direction of the scan line 301.
  • the positions of the first trace 201 and the scan line 301 in FIG. 3 are only It is only an indication, not a limitation of this application.
  • the scanning driving circuit, the data line, and the data driving circuit are further included.
  • the arrangement positions of the scanning driving circuit, the data line, and the data driving circuit have been shown in the foregoing. Be specific.
  • the display panel provided in this application includes a substrate 10 including a display area 101; a first metal layer 30 including a plurality of scan lines 301; a second metal layer 20 including the first
  • the two metal layers 20 include a plurality of first traces 201, and the projections of the plurality of first traces 201 on the substrate 10 are located in the display area 101; and a driving chip 50, at least part of the scan lines 301 is connected to the driving chip 50 through the first wiring 201, and the first wiring 201 is arranged in the display area 101, and a separate layer is formed, so that it no longer occupies the border area and greatly reduces the border occupied. Area.
  • a first insulating layer 40 is disposed between the first metal layer 30 and the second metal layer 20, so that the first metal layer 30 and the first metal layer 30
  • the two metal layers 20 are insulated from each other; a plurality of first vias 401 are provided on the first insulating layer 40 so that a first trace 201 passes through a first via 401 and a scan line 301 connection.
  • the projections of the plurality of first vias 401 on the substrate 10 are located between the projections of the plurality of scan lines 301 on the substrate 10 and the projections of the plurality of first traces 201 on the substrate 10. Intersection of the projections.
  • FIG. 5 is another cross-sectional view of the display panel provided in the embodiment of the present application.
  • FIG. 6 is another schematic diagram of the display driving structure and the equivalent circuit of the pixel electrode layer provided in the embodiment of the present application.
  • the display panel further includes:
  • the third metal layer 21 includes a plurality of second traces 211; a projection of the plurality of second traces 211 on the substrate 10 is located in the display area 101, and a part of The scan line 301 is connected to the driving chip 50 through the plurality of second traces 211. And because part of the scan lines 301 are connected to the driving chip 50 through the plurality of first traces 201, the number of scan lines 301 is added to the number of the first trace 201 and the second trace 211. the same. In addition, a first trace 201 of the second metal layer 20 and a scan line 301 are connected at intervals. A second trace 211 of the third metal layer 21 is connected to a scan line 301 at intervals.
  • each first trace 201 and each second trace 211 will not be short-circuited or intertwined with each other.
  • a second insulating layer 41 is disposed between the first metal layer 30 and the third metal layer 21 so that the first metal layer 30 and the third metal layer 21 are insulated from each other.
  • the second insulating layer 41 is provided with a plurality of second vias 411.
  • a second trace 211 is connected to a scan line 301 through a second via 411.
  • the first metal layer 30 is disposed between the second metal layer 20 and the third metal layer 21.
  • the display panel further includes a plurality of thin film transistors 1213.
  • the gates of the plurality of thin film transistors 1213 are disposed on the same layer as the first metal layer 30, and a scan line 301 and a gate of the thin film transistor 1213 are provided. ⁇ ⁇ Extremely connected.
  • the scanning driving circuit, the data line, and the data driving circuit are further included.
  • the arrangement positions of the scanning driving circuit, the data line, and the data driving circuit have been shown in the foregoing, and are not shown here. Be specific.
  • the present application further provides a display device including a display panel according to any one of the embodiments of the present application, and a packaging cover provided on the display panel.
  • the display panel provided in this application further includes: a third metal layer 21, the third metal layer 21 includes a plurality of second traces 211; a projection of the plurality of second traces 211 on the substrate 10 is located at Within the display area 101, a part of the scan lines 301 are connected to the driving chip 50 through the plurality of second traces 211.
  • the second trace 211 is divided into two or more metal layers and disposed on the upper and lower sides of the first metal layer 30.
  • the second trace 211 is connected to the scan line 301 through the second via 411, which increases each first trace.
  • the distance between the trace 201 and each of the second traces 211 prevents short circuits or mutual entanglement between the first and second traces 201 and 211.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optics & Photonics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示面板（100）及显示装置，包括：基板（10），基板（10）包括显示区域（101）；第一金属层（30），第一金属层（30）包括多条扫描线（301）；第二金属层（20），第二金属层（20）包括多条第一走线（201），且多条第一走线（201）在基板（10）上的投影位于显示区域（101）内；以及驱动芯片（50），至少部分扫描线（301）通过第一走线（201）连接至驱动芯片（50）。

Description

显示面板及显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板及显示装置。
 背景技术
随着显示产业的发展，用户对终端的要求越来越高，例如，用户希望终端的显示区域的占比越高越好。随之而来的是全面屏技术的出现并不断蓬勃发展，显示屏的非显示区域（即边框）被设计得越来越窄。
对于显示模组，显示区域到显示模组外边框之间的区域称为显示模组的非显示区域（即边框），包括上、下、左、右四个边框。该非显示区域用于外围电路走线，通过该非显示区域，可以将显示区域的一系列薄膜晶体管连通，并引出到下边框外引线端子区，从而将外引线端子区与驱动芯片连接。然而，也正是由于外围电路走线的存在，导致显示模组的边框无法进一步缩小，因此需要设计一种新的走线方式来解决这一问题。
 技术问题
本申请实施例提供一种显示面板及显示装置，将走线设置在显示区域内，减少了边框所占用的面积。
 技术解决方案
本申请提供了一种显示面板，包括：
基板，所述基板包括显示区域；
第一金属层，所述第一金属层包括多条扫描线；
第二金属层，所述第二金属层包括多条第一走线，且所述多条第一走线在所述基板上的投影位于所述显示区域内；以及
驱动芯片，至少部分所述扫描线通过所述第一走线连接至所述驱动芯片。
在本申请所提供的显示面板中，所述多条第一走线与所述多条扫描线一一对应连接。
在本申请所提供的显示面板中，所述多条扫描线沿第一方向排列，所述多条第一走线沿第二方向排列，且所述第一方向与所述第二方向相互垂直。
在本申请所提供的显示面板中，所述第一金属层和所述第二金属层之间设置有第一绝缘层，且所述第一绝缘层上设置有多个第一过孔，一所述第一走线通过一所述第一过孔与一所述扫描线连接。
在本申请所提供的显示面板中，所述多个过孔在所述基板上的投影位于所述多条扫描线在所述基板上的投影与所述多条第一走线在所述基板上的投影的交汇处。
在本申请所提供的显示面板中，所述显示面板还包括：第三金属层，所述第三金属层包括多条第二走线；所述多条第二走线在所述基板上的投影位于所述显示区域内，且部分所述扫描线通过所述多条第二走线连接至所述驱动芯片。
在本申请所提供的显示面板中，所述第一金属层和所述第三金属层之间设置有第二绝缘层，且所述第二绝缘层上设置有多个第二过孔，一所述第二走线通过一所述第二过孔与一所述扫描线连接。
在本申请所提供的显示面板中，所述第一金属层设置在所述第二金属层与所述第三金属层之间。
在本申请所提供的显示面板中，所述显示面板还包括多个薄膜晶体管，所述多个薄膜晶体管的栅极与所述第一金属层同层设置，且一所述扫描线与一所述薄膜晶体管的栅极连接。
本申请还提供了一种显示装置，包括显示面板，以及设置在所述显示面板上的封装盖板，其中，所述显示面板包括：
基板，所述基板包括显示区域；
第一金属层，所述第一金属层包括多条扫描线；
第二金属层，所述第二金属层包括多条第一走线，且所述多条第一走线在所述基板上的投影位于所述显示区域内；以及
驱动芯片，至少部分所述扫描线通过所述第一走线连接至所述驱动芯片。
在本申请所提供的显示装置中，所述多条第一走线与所述多条扫描线一一对应连接。
在本申请所提供的显示装置中，所述多条扫描线沿第一方向排列，所述多条第一走线沿第二方向排列，且所述第一方向与所述第二方向相互垂直。
在本申请所提供的显示装置中，所述第一金属层和所述第二金属层之间设置有第一绝缘层，且所述第一绝缘层上设置有多个第一过孔，一所述第一走线通过一所述第一过孔与一所述扫描线连接。
在本申请所提供的显示装置中，所述多个第一过孔在所述基板上的投影位于所述多条扫描线在所述基板上的投影与所述多条第一走线在所述基板上的投影的交汇处。
本申请提供了一种显示面板，其包括：
基板，所述基板包括显示区域；
第一金属层，所述第一金属层包括多条扫描线；
第二金属层，所述第二金属层包括多条第一走线，且所述多条第一走线在所述基板上的投影位于所述显示区域内；以及
驱动芯片，至少部分所述扫描线通过所述第一走线连接至所述驱动芯片；
其中，所述显示面板还包括第三金属层，所述第三金属层包括多条第二走线；所述多条第二走线在所述基板上的投影位于所述显示区域内，且部分所述扫描线通过所述多条第二走线连接至所述驱动芯片；所述显示面板还包括多个薄膜晶体管，所述多个薄膜晶体管的栅极与所述第一金属层同层设置，且一所述扫描线与一所述薄膜晶体管的栅极连接。
在本申请所提供的显示面板中，所述多条扫描线沿第一方向排列，所述多条第一走线沿第二方向排列，且所述第一方向与所述第二方向相互垂直。
在本申请所提供的显示面板中，所述第一金属层和所述第二金属层之间设置有第一绝缘层，且所述第一绝缘层上设置有多个第一过孔，一所述第一走线通过一所述第一过孔与一所述扫描线连接。
在本申请所提供的显示面板中，所述多个第一过孔在所述基板上的投影位于所述多条扫描线在所述基板上的投影与所述多条第一走线在所述基板上的投影的交汇处。
在本申请所提供的显示面板中，所述第一金属层和所述第三金属层之间设置有第二绝缘层，且所述第二绝缘层上设置有多个第二过孔，一所述第二走线通过一所述第二过孔与一所述扫描线连接。
在本申请所提供的显示面板中，所述第一金属层设置在所述第二金属层与所述第三金属层之间。
 有益效果
本申请提供的显示面板，包括：基板，所述基板包括显示区域；第一金属层，所述第一金属层包括多条扫描线；第二金属层，所述第二金属层包括多条第一走线，且所述多条第一走线在所述基板上的投影位于所述显示区域内；以及驱动芯片，至少部分所述扫描线通过所述第一走线连接至所述驱动芯片，将第一走线设置在显示区域内，并单独形成一层，使得其不再占用边框区域，大大减少了边框所占用的面积。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的显示面板的立体结构示意图；
图2为本申请实施例提供的显示驱动结构与像素电极层的等效电路示意图；
图3为本申请实施例提供的显示驱动结构与像素电极层的等效电路另一示意图；
图4为本申请实施例提供的显示面板剖面图；
图5为本申请实施例提供的显示面板的另一剖面图；
图6为本申请实施例提供的显示驱动结构与像素电极层的等效电路又一示意图。
 本发明的实施方式
请参阅图1，图1为本申请实施例提供的显示面板的立体结构示意图。如图1所示，该显示面板100包括彩色滤光片基板110、阵列基板120以及位于该彩色滤光片基板110与该阵列基板120之间的液晶层130。其中，该彩色滤光片基板110邻近该液晶层130一侧设置有彩色滤光层112。该阵列基板120邻近该液晶层130的一侧设置有显示驱动结构121、公共电极层122以及像素电极层123。
请一并参阅图2，图2为本申请实施例提供的显示驱动结构与像素电极层的等效电路示意图。该像素电极层123包括对应到显示面板100各个像素的像素电极1231。该显示驱动结构121包括布置在显示区域101的多条扫描线301、多条数据线1212及连接于该扫描线与数据线交叉处的薄膜晶体管1213，该薄膜晶体管1213还与像素电极1231电连接，用于传输数据信号至该像素电极1231。该公共电极层122用于配合该像素电极1231形成平面电场驱动液晶分子在平面内旋转。该扫描线301沿第一方向X延伸，该数据线1212沿不同于该第一方向X 的第二方向Y延伸且与该扫描线301绝缘相交以构成多个像素1233。该第一方向X 可以与该第二方向Y 垂直，从而使该多个像素1233呈矩阵式排列。其中，每一像素1233设置有薄膜晶体管1213及像素电极1231，该薄膜晶体管1213分别连接该扫描线301、该数据线1212及该像素电极1231，该像素电极1231用于与该公共电极层122在显示时段驱动该显示面板100进行画面显示。
可以理解，该显示面板100还包括与该扫描线301电连接的扫描驱动电路142及与该数据线1212电连接的数据驱动电路144，其中该扫描驱动电路142用于在显示时段施加扫描驱动信号至该扫描线301，该数据驱动电路144用于在该显示时段施加数据驱动信号至该数据线1212。
可以理解，该显示面板100还包括布置在非显示区域102的走线200及驱动芯片50，该扫描线301通过走线200与驱动芯片50连接。
由于将走线200布置在非显示区域102，导致显示面板的边框无法进一步缩小。
为了解决显示面板的边框无法进一步缩小的问题，本申请实施例提出了一种显示面板，请参阅图3与图4，图3为本申请实施例提供的显示驱动结构与像素电极层的等效电路另一示意图，图4为本申请实施例提供的显示面板剖面图，包括：基板10，所述基板包括显示区域101；第一金属层30，所述第一金属层30包括多条扫描线301；第二金属层20，所述第二金属层20包括多条第一走线201，且所述多条第一走线201在所述基板10上的投影位于所述显示区域101内；以及驱动芯片50，至少部分所述扫描线301通过所述第一走线201连接至所述驱动芯片50。
该基板10可以是玻璃基板、高导热铝基板或者是形成有PI（Polyimide，聚酰亚胺）的基板，也可以是TFT（Thin Film Transistor，薄膜晶体管）基板或者是OLED（Organic Light Emitting Diode，有机发光二极管）基板。如图3所示，该基板包括显示区域101和非显示区域102，将原本设置在非显示区域102的多条第一走线201设置在显示区域101内，从而减少了非显示区域102的占用面积，缩小了非显示区域102所占的比重。并使多条第一走线201成为单独的一层，即第二金属层20。将多条扫描线301与多条第一走线201设置在不同层，使得多条扫描线301与多条第一走线201不会相互干扰。其中，该多条第一走线201与多条扫描线301一一对应连接；且多条扫描线301沿第一方向X排列，多条第一走线201沿第二方向Y排列，且第一方向X与第二方向Y垂直，从而使得每一第一走线201和每一扫描线301能有最大的接触面积，并且，也可以使得各第一走线201之间不会相互缠绕，避免相互造成干扰。需要说明的是，第一方向X指的是第一走线201的布置方向，第二方向Y指的是扫描线301的布置方向，图3中第一走线201和扫描线301的位置仅仅只是示意，而不是对本申请的限制。
可以理解的是，尽管图3中未示出，还包括扫描驱动电路、数据线及数据驱动电路，所述扫描驱动电路、数据线及数据驱动电路的布置位置已在前文示出，在此不做具体赘述。
本申请提供的显示面板，包括：基板10，所述基板10包括显示区域101；第一金属层30，所述第一金属层30包括多条扫描线301；第二金属层20，所述第二金属层20包括多条第一走线201，且所述多条第一走线201在所述基板10上的投影位于所述显示区域101内；以及驱动芯片50，至少部分所述扫描线301通过所述第一走线201连接至所述驱动芯片50，将第一走线201设置在显示区域101内，并单独形成一层，使得其不再占用边框区域，大大减少了边框所占用的面积。
如图4所示，在一些实施例中，所述第一金属层30和所述第二金属层20之间设置有第一绝缘层40，以使得所述第一金属层30和所述第二金属层20相互绝缘；所述第一绝缘层40上设置有多个第一过孔401，以使得一所述第一走线201通过一所述第一过孔401与一所述扫描线301连接。且所述多个第一过孔401在所述基板10上的投影位于所述多条扫描线301在所述基板10上的投影与所述多条第一走线201在所述基板10上的投影的交汇处。
请结合参阅图5及图6，图5为本申请实施例提供的显示面板的另一剖面图，图6为本申请实施例提供的显示驱动结构与像素电极层的等效电路又一示意图，所述显示面板还包括：
第三金属层21，所述第三金属层21包括多条第二走线211；所述多条第二走线211在所述基板10上的投影位于所述显示区域101内，且部分所述扫描线301通过所述多条第二走线211连接至所述驱动芯片50。而由于部分所述扫描线301通过所述多条第一走线201连接至所述驱动芯片50，因此扫描线301的条数与第一走线201及第二走线211相加的条数相同。且所述第二金属层20的一所述第一走线201与一所述扫描线301间隔连接。所述第三金属层21的一所述第二走线211与一所述扫描线301间隔连接。例如，若有1，2，3，4，5，6共6条扫描线301，那么1，3，5这3条扫描线301与第一走线201连接；2，4，6这三条扫描线301与第二走线211连接。这样便增大了各第一走线201和各第二走线211之间的距离，使得各第一走线201和各第二走线211不会短路或者相互缠绕。
所述第一金属层30和所述第三金属层21之间设置有第二绝缘层41，以使得第一金属层30与第三金属层21相互绝缘。且所述第二绝缘层41上设置有多个第二过孔411，一所述第二走线211通过一所述第二过孔411与一所述扫描线301连接。所述第一金属层30设置在所述第二金属层20与所述第三金属层21之间。所述显示面板还包括多个薄膜晶体管1213，所述多个薄膜晶体管1213的栅极与所述第一金属层30同层设置，且一所述扫描线301与一所述薄膜晶体管1213的栅极连接。
可以理解的是，尽管图6中未示出，还包括扫描驱动电路、数据线及数据驱动电路，所述扫描驱动电路、数据线及数据驱动电路的布置位置已在前文示出，在此不做具体赘述。
本申请还提供了一种显示装置，包括本申请任一实施例的显示面板，以及设置在所述显示面板上的封装盖板。
本申请提供的显示面板，还包括：第三金属层21，所述第三金属层21包括多条第二走线211；所述多条第二走线211在所述基板10上的投影位于所述显示区域101内，且部分所述扫描线301通过所述多条第二走线211连接至所述驱动芯片50。通过将第二走线211分为两层或多层金属层设置在第一金属层30上下两侧，第二走线211通过第二过孔411与扫描线301连接，增大了各第一走线201和各第二走线211之间的距离，避免各第一走线201和各第二走线211之间短路或者相互缠绕。
以上对本申请实施例提供的显示面板以及显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请。同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板，其包括：
    基板，所述基板包括显示区域；
    第一金属层，所述第一金属层包括多条扫描线；
    第二金属层，所述第二金属层包括多条第一走线，且所述多条第一走线在所述基板上的投影位于所述显示区域内；以及
    驱动芯片，至少部分所述扫描线通过所述第一走线连接至所述驱动芯片。
  2. 根据权利要求1所述的显示面板，其中，所述多条第一走线与所述多条扫描线一一对应连接。
  3. 根据权利要求2所述的显示面板，其中，所述多条扫描线沿第一方向排列，所述多条第一走线沿第二方向排列，且所述第一方向与所述第二方向相互垂直。
  4. 根据权利要求3所述的显示面板，其中，所述第一金属层和所述第二金属层之间设置有第一绝缘层，且所述第一绝缘层上设置有多个第一过孔，一所述第一走线通过一所述第一过孔与一所述扫描线连接。
  5. 根据权利要求4所述的显示面板，其中，所述多个第一过孔在所述基板上的投影位于所述多条扫描线在所述基板上的投影与所述多条第一走线在所述基板上的投影的交汇处。
  6. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：第三金属层，所述第三金属层包括多条第二走线；所述多条第二走线在所述基板上的投影位于所述显示区域内，且部分所述扫描线通过所述多条第二走线连接至所述驱动芯片。
  7. 根据权利要求6所述的显示面板，其中，所述第一金属层和所述第三金属层之间设置有第二绝缘层，且所述第二绝缘层上设置有多个第二过孔，一所述第二走线通过一所述第二过孔与一所述扫描线连接。
  8. 根据权利要求7所述的显示面板，其中，所述第一金属层设置在所述第二金属层与所述第三金属层之间。
  9. 根据权利要求1所述的显示面板，其中，所述显示面板还包括多个薄膜晶体管，所述多个薄膜晶体管的栅极与所述第一金属层同层设置，且一所述扫描线与一所述薄膜晶体管的栅极连接。
  10. 一种显示装置，其包括显示面板，以及设置在所述显示面板上的封装盖板，其中，所述显示面板包括：
    基板，所述基板包括显示区域；
    第一金属层，所述第一金属层包括多条扫描线；
    第二金属层，所述第二金属层包括多条第一走线，且所述多条第一走线在所述基板上的投影位于所述显示区域内；以及
    驱动芯片，至少部分所述扫描线通过所述第一走线连接至所述驱动芯片。
  11. 根据权利要求10所述的显示装置，其中，所述多条第一走线与所述多条扫描线一一对应连接。
  12. 根据权利要求11所述的显示装置，其中，所述多条扫描线沿第一方向排列，所述多条第一走线沿第二方向排列，且所述第一方向与所述第二方向相互垂直。
  13. 根据权利要求12所述的显示装置，其中，所述第一金属层和所述第二金属层之间设置有第一绝缘层，且所述第一绝缘层上设置有多个第一过孔，一所述第一走线通过一所述第一过孔与一所述扫描线连接。
  14. 根据权利要求13所述的显示装置，其中，所述多个第一过孔在所述基板上的投影位于所述多条扫描线在所述基板上的投影与所述多条第一走线在所述基板上的投影的交汇处。
  15. 一种显示面板，其包括：
    基板，所述基板包括显示区域；
    第一金属层，所述第一金属层包括多条扫描线；
    第二金属层，所述第二金属层包括多条第一走线，且所述多条第一走线在所述基板上的投影位于所述显示区域内；以及
    驱动芯片，至少部分所述扫描线通过所述第一走线连接至所述驱动芯片；
    其中，所述显示面板还包括第三金属层，所述第三金属层包括多条第二走线；所述多条第二走线在所述基板上的投影位于所述显示区域内，且部分所述扫描线通过所述多条第二走线连接至所述驱动芯片；所述显示面板还包括多个薄膜晶体管，所述多个薄膜晶体管的栅极与所述第一金属层同层设置，且一所述扫描线与一所述薄膜晶体管的栅极连接。
  16. 根据权利要求15所述的显示面板，其中，所述多条扫描线沿第一方向排列，所述多条第一走线沿第二方向排列，且所述第一方向与所述第二方向相互垂直。
  17. 根据权利要求16所述的显示面板，其中，所述第一金属层和所述第二金属层之间设置有第一绝缘层，且所述第一绝缘层上设置有多个第一过孔，一所述第一走线通过一所述第一过孔与一所述扫描线连接。
  18. 根据权利要求17所述的显示面板，其中，所述多个第一过孔在所述基板上的投影位于所述多条扫描线在所述基板上的投影与所述多条第一走线在所述基板上的投影的交汇处。
  19. 根据权利要求15所述的显示面板，其中，所述第一金属层和所述第三金属层之间设置有第二绝缘层，且所述第二绝缘层上设置有多个第二过孔，一所述第二走线通过一所述第二过孔与一所述扫描线连接。
  20. 根据权利要求19所述的显示面板，其中，所述第一金属层设置在所述第二金属层与所述第三金属层之间。
PCT/CN2019/070924 2018-09-18 2019-01-09 显示面板及显示装置 WO2020057020A1 (zh)

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