WO2021227112A1 - 阵列基板、具有该阵列基板的显示面板及显示装置 - Google Patents

阵列基板、具有该阵列基板的显示面板及显示装置 Download PDF

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Publication number
WO2021227112A1
WO2021227112A1 PCT/CN2020/091347 CN2020091347W WO2021227112A1 WO 2021227112 A1 WO2021227112 A1 WO 2021227112A1 CN 2020091347 W CN2020091347 W CN 2020091347W WO 2021227112 A1 WO2021227112 A1 WO 2021227112A1
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WIPO (PCT)
Prior art keywords
metal layer
array substrate
patch
lines
data lines
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PCT/CN2020/091347
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English (en)
French (fr)
Inventor
朱静
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/963,254 priority Critical patent/US20230110225A1/en
Publication of WO2021227112A1 publication Critical patent/WO2021227112A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings

Definitions

  • the present invention relates to the field of display technology, and in particular to an array substrate, a display panel and a display device having the array substrate.
  • a liquid crystal display panel usually includes an array substrate, a color filter substrate, and a liquid crystal layer distributed between the array substrate and the color filter substrate.
  • FIG. 1 is a schematic diagram of wiring in an array substrate in the prior art.
  • the array substrate is divided into a display area AA' and a non-display area surrounding the display area AA'.
  • the display area AA' is provided with a plurality of scan lines 100 extending in the horizontal direction, a plurality of data lines 200 extending in the longitudinal direction and insulated and crossing the scan lines 100, and a plurality of scan switches extending in the longitudinal direction and electrically connected to the scan lines 100.
  • the non-display area includes a left frame B1', a right frame B2', an upper frame B3', and a lower frame B4'.
  • the left frame B1', the right frame B2', and the upper frame B3' are only used for packaging, and the bottom frame B4' is provided with a number of flip-chip films in addition to packaging.
  • the number of flip-chip films shown in Figure 1 is 3, which are G_COF1, G_COF2, and D_COF.
  • G_COF1 and G_COF2 are respectively electrically connected to a number of scanning adapter cables 300 to transmit scanning signals to the scanning line 100 through the scanning adapter cable 300;
  • D_COF is electrically connected to a number of data lines 200 to transmit data signals to the data line 200.
  • the scan transfer line 300 is arranged parallel to the data line 200, the load of the scan transfer line 300 is extremely large, thereby reducing the charging rate of each sub-pixel electrode in the liquid crystal display panel, resulting in poor display quality.
  • the present invention provides an array substrate, a display panel and a display device having the array substrate, to solve the technical problem of poor display image quality due to the low charging rate of each sub-pixel electrode in the existing display panel and display device.
  • the present invention provides an array substrate having a display area, a plurality of scan lines and a plurality of data lines are arranged in the display area, all the scan lines are spaced apart from each other and extend along a first direction, All the data lines are spaced apart from each other and extend in a second direction, the first direction is perpendicular to the second direction, all the scan lines are insulated and crossed with all the data lines, and a number of A patch cord unit, each of the patch cord units includes at least two patch cords connected in parallel, all the patch cords are spaced apart from each other and extend along the second direction, and each scan line corresponds to at least one patch cord unit Each of the scan lines is electrically connected to all the patch cords in all corresponding patch cord units, and each of the patch cords is used to input a scan signal to the scan line that is electrically connected.
  • each patch cord corresponds to one data line
  • different patch cords correspond to different data lines
  • all patch cords in each patch cord unit correspond to all The data lines are adjacent to each other in sequence.
  • each of the patch cords is located on the same side of the corresponding data line.
  • the array substrate includes a first metal layer and a second metal layer disposed on the first metal layer, each of the scan lines is formed in the first metal layer, and each The data line is formed in the second metal layer.
  • each of the patch cords is formed in the second metal layer.
  • the array substrate further includes a third metal layer disposed on the second metal layer, and each of the transition lines is formed in the second metal layer and the third metal layer, The portion of each transition wire located in the second metal layer is connected in parallel with the portion located in the third metal layer.
  • the array substrate further has a non-display area, and all the transition wires in each of the transition wire units extend into the non-display area and are shorted to form short wires.
  • a plurality of first chip-on-chip films and a plurality of second chip-on-chip films are provided in the non-display area;
  • the short wires are electrically connected to input scanning signals to the electrically connected parts of the short wires;
  • each of the second flip chip films corresponds to a part of the data line, and is electrically connected to a corresponding part of the data line to A data signal is input to part of the data lines that are electrically connected.
  • the present invention provides a display panel.
  • the display panel includes an array substrate, the array substrate has a display area, and a plurality of scan lines and a plurality of data lines are provided in the display area. Are spaced apart and extend in a first direction, all the data lines are spaced apart from each other and extend in a second direction, the first direction is perpendicular to the second direction, all the scan lines and all the data lines are insulated and crossed, so
  • the display area is also provided with a number of patch cord units.
  • Each patch cord unit includes at least two patch cords connected in parallel. All the patch cords are spaced apart from each other and extend along the second direction.
  • Each scan line Corresponding to at least one of the patch cord units, each of the scan lines is electrically connected to all the patch cords in all the corresponding patch cord units, and each of the patch cords is used to electrically connect to the Scan line input scan signal.
  • each patch cord corresponds to one data line
  • different patch cords correspond to different data lines
  • all patch cords in each patch cord unit correspond to all The data lines are adjacent to each other in sequence.
  • each of the patch cords is located on the same side of the corresponding data line.
  • the array substrate includes a first metal layer and a second metal layer disposed on the first metal layer, each of the scan lines is formed in the first metal layer, and each The data line is formed in the second metal layer.
  • each of the patch cords is formed in the second metal layer.
  • the array substrate further includes a third metal layer disposed on the second metal layer, and each of the transition lines is formed in the second metal layer and the third metal layer, The portion of each transition wire located in the second metal layer is connected in parallel with the portion located in the third metal layer.
  • the present invention provides a display device, the display device includes a display panel, the display panel includes an array substrate, the array substrate has a display area, the display area is provided with a number of scan lines and a number of data Line, all the scan lines are spaced apart from each other and extend along a first direction, all the data lines are spaced apart from each other and extend along a second direction, the first direction is perpendicular to the second direction, all the scan lines are connected to all The data lines are insulated and crossed, and the display area is also provided with a number of patch cord units, each of the patch cord units includes at least two patch cords connected in parallel, and all the patch cords are spaced apart from each other and along the second direction Extension, each scan line corresponds to at least one of the patch cord unit, each scan line is electrically connected to all the patch cords in all the patch cord units, and each patch cord is used for Inputting a scanning signal to the scanning line electrically connected.
  • each patch cord corresponds to one data line
  • different patch cords correspond to different data lines
  • all patch cords in each patch cord unit correspond to all The data lines are adjacent to each other in sequence.
  • each of the patch cords is located on the same side of the corresponding data line.
  • the array substrate includes a first metal layer and a second metal layer disposed on the first metal layer, each of the scan lines is formed in the first metal layer, and each The data line is formed in the second metal layer.
  • each of the patch cords is formed in the second metal layer.
  • the array substrate further includes a third metal layer disposed on the second metal layer, and each of the transition lines is formed in the second metal layer and the third metal layer, The portion of each transition wire located in the second metal layer is connected in parallel with the portion located in the third metal layer.
  • the array substrate provided by the present invention completes the scanning signal transmission function by replacing the scanning patch cords in the prior art with a patch cord unit. Since the patch cord unit includes at least two patch cords connected in parallel, the resistance of each patch cord unit is relatively high. In the prior art, the resistance of the scan transfer line is smaller, which can greatly shorten the fall time of the scan signal, thereby increasing the charging rate of each sub-pixel electrode. When the array substrate is applied to a display panel and a display device, It can improve the display quality.
  • FIG. 1 is a schematic diagram of wiring in an array substrate in the prior art.
  • FIG. 2 is a schematic diagram of wiring in an array substrate provided by an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a film layer of an array substrate provided by an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a film layer of another array substrate provided by an embodiment of the present invention.
  • the array substrate is divided into a display area AA and a non-display area surrounding the display area AA, wherein the non-display area includes a left frame B1, right frame B2, top frame B3, and bottom frame B4.
  • a number of scan lines 10 and a number of data lines 20 are provided in the display area AA.
  • all the scan lines 10 are spaced apart from each other and extend along the first direction
  • all the data lines 20 are spaced apart from each other and extend along the second direction
  • the first direction is perpendicular to the second direction.
  • the first direction is the horizontal direction in FIG. 2
  • the second direction is the vertical direction in FIG. 2.
  • the first direction may also be a vertical direction
  • the second direction is a horizontal direction.
  • each sub-pixel area 30 is provided with a sub-pixel electrode (not shown in FIG. 2) and a corresponding thin film transistor (Thin Film Transistor, TFT) (not shown in FIG. 2).
  • the gate of each TFT is electrically connected to the corresponding scan line 10
  • the source of each TFT is electrically connected to the corresponding data line 20
  • the drain of each TFT is electrically connected to the corresponding sub-pixel electrode.
  • each patch cord unit 40 includes at least two patch cords 400 connected in parallel.
  • Each patch cord unit 40 shown in FIG. 2 includes two patch cords.
  • Each scan line 10 corresponds to at least one patch cord unit 40. It should be noted that the number of patch cord units 40 corresponding to each scan line 10 is related to the driving mode of all scan lines 10. For example, if the driving mode is unilateral driving, each scan line 10 corresponds to one patch cord unit 40; if the driving mode is dual-sided driving, each scan line corresponds to two patch cord units 40, and so on.
  • the driving mode shown in FIG. 2 is bilateral driving, and at this time, each scan line 10 corresponds to two patch cord units 40. It can be understood that, in other embodiments, the driving mode of the scan line 10 may also be unilateral driving, and in this case, each scan line 10 corresponds to a patch cord unit 40.
  • Each scan line 10 is electrically connected to all the patch cords 400 in all corresponding patch cord units 40, and each patch cord 400 is used to input a scan signal to the scan line 10 that is electrically connected.
  • the scan signal transmission function is replaced by the patch cord unit 40 instead of the scan patch cord in the prior art.
  • the patch cord unit 40 includes at least two patch cords 400 connected in parallel, each patch cord unit 40 Compared with the resistance of the scanning transfer line in the prior art, the resistance of the scanning transfer line is smaller, which can greatly shorten the fall time of the scanning signal, thereby increasing the charging rate of each sub-pixel electrode.
  • the display quality can be improved.
  • each patch cord 400 corresponds to a data line 20, and different patch cords 400 correspond to different data lines 20.
  • each patch cord 400 is adjacent to the corresponding data line 20 and is located on the left side of the corresponding data line 20. It is understandable that, in other embodiments, each patch cord 400 may also be located on the right side of the corresponding data line 20; or, in other embodiments, part of the patch cord 400 may be located on the left side of the corresponding data line 20, and part of the patch cord 400 may be located on the left side of the corresponding data line 20.
  • the patch cord 400 is located on the right side of the corresponding data line 20.
  • each patch cord unit 40 includes two parallel patch cords 400, and two data lines 20 corresponding to the two parallel patch cords 400 are adjacent to each other. In other embodiments, if each patch cord unit 40 includes three parallel patch cords 400, the three data lines 20 corresponding to the three parallel patch cords 400 are adjacent in turn.
  • all patch cords 400 in the patch cord unit 40 adopt the above arrangement, which can reduce the amount of data line 20 spanning between any two adjacent patch cords 400. Quantity, thereby reducing electrostatic damage in the display area AA.
  • each patch cord 400 is located on the same side of the corresponding data line 20.
  • each sub-pixel electrode in the column of sub-pixel regions 30 is electrically connected to the same data line 20 through a corresponding TFT, and the data line 20 is referred to as the corresponding column of sub-pixel region 30. ⁇ 20 ⁇ The data line 20.
  • each transition wire 400 corresponds to a data line 20 can also be understood as that each transition wire 400 is provided in a column of sub-pixel regions 30.
  • “Different transfer lines 400 correspond to different data lines 20” can also be understood as the different transfer lines 400 are provided in the sub-pixel regions 30 in different columns.
  • “All the data lines 20 corresponding to all the patch cords 400 in each patch cord unit 40 are adjacent to each other in turn.” It can also be understood that all the column sub-pixel regions 30 where all patch cords 400 in each patch cord unit 40 are located are sequentially opposite to each other. adjacent.
  • all patch cords 400 in the patch cord unit 40 adopt the above arrangement, which can reduce the data lines spanning between any two adjacent patch cords 400.
  • all the scan lines 10 and all the data lines 20 are insulated and crossed, all the scan lines 10 and all the data lines 20 are respectively arranged in different metal layers of the array substrate.
  • each patch cord 400 adopts a single metal layer design, as shown in FIG. 3, which is a schematic diagram of a film layer of an array substrate provided by an embodiment of the present invention.
  • the array substrate includes a first metal layer 102 and a second metal layer 105 disposed on the first metal layer 102, each scan line 10 is formed in the first metal layer 102, and each data line 20 is formed in the second metal layer 105 middle.
  • the array substrate shown in FIG. 3 further includes: a first substrate 101, an active layer 103, a first insulating layer 104, a second insulating layer 106, a color resist layer 107, a flat layer 108, a pixel electrode layer 109, and Columnar septa 110.
  • the first substrate 101 is preferably a glass substrate.
  • the first metal layer 102 is disposed on the first substrate 101, and the scan line 10 and the gate of the TFT integrated with the scan line 10 are formed in the first metal layer 102.
  • the active layer 103 is provided on the first metal layer 102.
  • the first insulating layer 104 is disposed on the first substrate 101 and covers the first metal layer 102.
  • the second metal layer 105 is disposed on the first insulating layer 104, and the data line 20, the source and drain electrodes 1051 of the TFT integrated with the data line 20 and the transfer line 400 are formed in the second metal layer 105.
  • the data line 20 and the source and drain electrodes 1051 of the TFT are respectively located on the active layer 103, and the transfer line 400 is connected to the scan line 10 through the first via 111.
  • the first via 111 is formed in the first insulating layer 104 and located on the first metal layer 102.
  • the second insulating layer 106 is disposed on the first insulating layer 104 and covers the second metal layer 105.
  • the color resist layer 107 is disposed on the second insulating layer 106.
  • the flat layer 108 is provided on the color resist layer 107.
  • the pixel electrode layer 109 is disposed on the flat layer 108 and is connected to the drain 1051 of the TFT through the second via 112.
  • the second via hole 112 is formed in the second insulating layer 106, the color resist layer 107 and the flat layer 108 and is located on the drain electrode 1051 of the TFT.
  • the columnar spacer 110 is disposed on the pixel electrode layer 109.
  • each transfer line 400 adopts a bimetallic layer design, as shown in FIG. 4, which is a schematic diagram of a film layer of another array substrate provided by an embodiment of the present invention.
  • the array substrate includes a first metal layer 102, a second metal layer 105 provided on the first metal layer 102, and a third metal layer 201 provided on the second metal layer 105, and each scan line 10 is formed on the first metal layer 102
  • each data line 20 is formed in the second metal layer 105.
  • Each patch cord 400 is formed in the second metal layer 105 and the third metal layer 201, and each patch cord 400 includes a first portion 4001 located in the second metal layer 105 and a second portion 4002 located in the third metal layer 201 , And the two are connected in parallel.
  • the array substrate shown in FIG. 4 further includes: a first substrate 101, an active layer 103, a first insulating layer 104, a second insulating layer 106, a third insulating layer 202, a color resist layer 107, and a flat layer 108 , The pixel electrode layer 109 and the columnar spacer 110.
  • the first substrate 101 is preferably a glass substrate.
  • the first metal layer 102 is disposed on the first substrate 101, and the scan line 10 and the gate of the TFT integrated with the scan line 10 are formed in the first metal layer 102.
  • the active layer 103 is provided on the first metal layer 102.
  • the first insulating layer 104 is disposed on the first substrate 101 and covers the first metal layer 102.
  • the second metal layer 105 is disposed on the first insulating layer 104, and the data line 20, the source and drain electrodes 1051 of the TFT integrated with the data line 20 are formed in the second metal layer 105, and the first portion 4001 of the transfer line 400.
  • the data line 20 and the source and drain electrodes 1051 of the TFT are respectively located on the active layer 103, and the first part 4001 of the transfer line 400 is connected to the scan line 10 through the first via 111.
  • the first via 111 is formed in the first insulating layer 104 and located on the first metal layer 102.
  • the second insulating layer 106 is disposed on the first insulating layer 104 and covers the second metal layer 105.
  • the third metal layer 201 is provided on the second insulating layer 106.
  • the second part 4002 of the patch cord 400 is formed in the third metal layer 201.
  • Part 4001 is connected.
  • the third insulating layer 202 is disposed on the second insulating layer 106 and covers the third metal layer 201.
  • the color resist layer 107 is disposed on the second insulating layer 106.
  • the flat layer 108 is provided on the color resist layer 107.
  • the pixel electrode layer 109 is disposed on the flat layer 108 and is connected to the drain 1051 of the TFT through the second via 112.
  • the second via hole 112 is formed in the second insulating layer 106, the third insulating layer 202, the color resist layer 107 and the flat layer 108 and is located on the drain electrode 1051 of the TFT.
  • the columnar spacer 110 is disposed on the pixel electrode layer 109.
  • each patch cord 400 in this embodiment adopts a double metal layer design, which is formed in the second metal layer 105 and the third metal layer 201, and each patch cord 400 is located in the second metal layer 105 The part of is connected in parallel with the part of the third metal layer 201.
  • the double metal layer design can reduce the resistance of each patch cord 400, thereby making the resistance of each patch cord unit 40 smaller. Therefore, the fall time of the scan signal can be further shortened, and the charging rate of each sub-pixel electrode can be improved.
  • the display image quality can be further improved.
  • the array substrate further has a non-display area.
  • the non-display area includes a left frame B1, a right frame B2, an upper frame B3, and a lower frame B4.
  • the portions of all the patch cords 400 in each patch cord unit 40 that extend to the non-display area are shorted to form a short cord. All the short wires shown in Figure 2 are located in the lower frame B4.
  • first chip-on-chip films and several second chip-on-chip films are provided in the non-display area.
  • the several first chip-on-chip films and several second chip-on-chip films shown in FIG. 2 are all located in the lower frame B4, and the number of the first chip-on-chip films is two, which are called G_COF1 and G_COF2, respectively.
  • the number is 1, called D_COF.
  • Each of the first flip-chip films corresponds to a short wire, and is electrically connected to the corresponding short wire to input a scanning signal to the electrically connected short wire.
  • G_COF1 and G_COF2 shown in FIG. 2 respectively correspond to the short wires. And respectively connect to the corresponding short wires to input scanning signals to the electrically connected short wires.
  • Each second flip chip film corresponds to a part of the data line 20 and is electrically connected to the corresponding part of the data line 20 to input a data signal to the electrically connected part of the data line 20.
  • D_COF shown in FIG. 2 corresponds to a number of data The line 20 is electrically connected to the corresponding data lines 20 to input data signals to the electrically connected data lines 20.
  • the present invention also provides a display panel.
  • the display panel includes an array substrate.
  • FIG. 2 is a schematic diagram of wiring in the array substrate provided by an embodiment of the present invention. As shown in FIG.
  • the non-display area of area AA where the non-display area includes a left frame B1, a right frame B2, an upper frame B3, and a lower frame B4.
  • a number of scan lines 10 and a number of data lines 20 are provided in the display area AA.
  • all the scan lines 10 are spaced apart from each other and extend along the first direction
  • all the data lines 20 are spaced apart from each other and extend along the second direction
  • the first direction is perpendicular to the second direction.
  • the first direction is the horizontal direction in FIG. 2
  • the second direction is the vertical direction in FIG. 2.
  • the first direction may also be a vertical direction
  • the second direction is a horizontal direction.
  • each sub-pixel area 30 is provided with a sub-pixel electrode (not shown in FIG. 2) and a corresponding thin film transistor (Thin Film Transistor, TFT) (not shown in FIG. 2).
  • the gate of each TFT is electrically connected to the corresponding scan line 10
  • the source of each TFT is electrically connected to the corresponding data line 20
  • the drain of each TFT is electrically connected to the corresponding sub-pixel electrode.
  • each patch cord unit 40 includes at least two patch cords 400 connected in parallel.
  • Each patch cord unit 40 shown in FIG. 2 includes two patch cords.
  • Each scan line 10 corresponds to at least one patch cord unit 40. It should be noted that the number of patch cord units 40 corresponding to each scan line 10 is related to the driving mode of all scan lines 10. For example, if the driving mode is unilateral driving, each scan line 10 corresponds to one patch cord unit 40; if the driving mode is dual-sided driving, each scan line corresponds to two patch cord units 40, and so on.
  • the driving mode shown in FIG. 2 is bilateral driving, and at this time, each scan line 10 corresponds to two patch cord units 40. It can be understood that, in other embodiments, the driving mode of the scan line 10 may also be unilateral driving, and in this case, each scan line 10 corresponds to a patch cord unit 40.
  • Each scan line 10 is electrically connected to all the patch cords 400 in all corresponding patch cord units 40, and each patch cord 400 is used to input a scan signal to the scan line 10 that is electrically connected.
  • each The resistance of the patch cord unit 40 is smaller than that of the scan patch cord in the prior art, which can greatly shorten the fall time of the scan signal, thereby increasing the charging rate of each sub-pixel electrode, thereby improving the display quality. Effect.
  • each patch cord 400 corresponds to a data line 20, and different patch cords 400 correspond to different data lines 20.
  • each patch cord 400 is adjacent to the corresponding data line 20 and is located on the left side of the corresponding data line 20. It is understandable that, in other embodiments, each patch cord 400 may also be located on the right side of the corresponding data line 20; or, in other embodiments, part of the patch cord 400 may be located on the left side of the corresponding data line 20, and part of the patch cord 400 may be located on the left side of the corresponding data line 20.
  • the patch cord 400 is located on the right side of the corresponding data line 20.
  • each patch cord unit 40 includes two parallel patch cords 400, and two data lines 20 corresponding to the two parallel patch cords 400 are adjacent to each other. In other embodiments, if each patch cord unit 40 includes three parallel patch cords 400, the three data lines 20 corresponding to the three parallel patch cords 400 are adjacent in turn.
  • all patch cords 400 in the patch cord unit 40 adopt the above arrangement, which can reduce the amount of data line 20 spanning between any two adjacent patch cords 400. Quantity, thereby reducing electrostatic damage in the display area AA.
  • each patch cord 400 is located on the same side of the corresponding data line 20.
  • each sub-pixel electrode in the column of sub-pixel regions 30 is electrically connected to the same data line 20 through a corresponding TFT, and the data line 20 is referred to as the corresponding column of sub-pixel region 30. ⁇ 20 ⁇ The data line 20.
  • each transition wire 400 corresponds to a data line 20 can also be understood as that each transition wire 400 is provided in a column of sub-pixel regions 30.
  • “Different transfer lines 400 correspond to different data lines 20” can also be understood as the different transfer lines 400 are provided in the sub-pixel regions 30 in different columns.
  • “All the data lines 20 corresponding to all the patch cords 400 in each patch cord unit 40 are adjacent to each other in turn.” It can also be understood that all the column sub-pixel regions 30 where all patch cords 400 in each patch cord unit 40 are located are sequentially opposite to each other. adjacent.
  • all patch cords 400 in the patch cord unit 40 adopt the above arrangement, which can reduce the data lines spanning between any two adjacent patch cords 400.
  • all the scan lines 10 and all the data lines 20 are insulated and crossed, all the scan lines 10 and all the data lines 20 are respectively arranged in different metal layers of the array substrate.
  • each patch cord 400 adopts a single metal layer design, as shown in FIG. 3, which is a schematic diagram of a film layer of an array substrate provided by an embodiment of the present invention.
  • the array substrate includes a first metal layer 102 and a second metal layer 105 disposed on the first metal layer 102, each scan line 10 is formed in the first metal layer 102, and each data line 20 is formed in the second metal layer 105 middle.
  • the array substrate shown in FIG. 3 further includes: a first substrate 101, an active layer 103, a first insulating layer 104, a second insulating layer 106, a color resist layer 107, a flat layer 108, a pixel electrode layer 109, and Columnar septa 110.
  • the first substrate 101 is preferably a glass substrate.
  • the first metal layer 102 is disposed on the first substrate 101, and the scan line 10 and the gate of the TFT integrated with the scan line 10 are formed in the first metal layer 102.
  • the active layer 103 is provided on the first metal layer 102.
  • the first insulating layer 104 is disposed on the first substrate 101 and covers the first metal layer 102.
  • the second metal layer 105 is disposed on the first insulating layer 104, and the data line 20, the source and drain electrodes 1051 of the TFT integrated with the data line 20 and the transfer line 400 are formed in the second metal layer 105.
  • the data line 20 and the source and drain electrodes 1051 of the TFT are respectively located on the active layer 103, and the transfer line 400 is connected to the scan line 10 through the first via 111.
  • the first via 111 is formed in the first insulating layer 104 and located on the first metal layer 102.
  • the second insulating layer 106 is disposed on the first insulating layer 104 and covers the second metal layer 105.
  • the color resist layer 107 is disposed on the second insulating layer 106.
  • the flat layer 108 is provided on the color resist layer 107.
  • the pixel electrode layer 109 is disposed on the flat layer 108 and is connected to the drain 1051 of the TFT through the second via 112.
  • the second via hole 112 is formed in the second insulating layer 106, the color resist layer 107 and the flat layer 108 and is located on the drain electrode 1051 of the TFT.
  • the columnar spacer 110 is disposed on the pixel electrode layer 109.
  • each transfer line 400 adopts a bimetallic layer design, as shown in FIG. 4, which is a schematic diagram of a film layer of another array substrate provided by an embodiment of the present invention.
  • the array substrate includes a first metal layer 102, a second metal layer 105 provided on the first metal layer 102, and a third metal layer 201 provided on the second metal layer 105, and each scan line 10 is formed on the first metal layer 102
  • each data line 20 is formed in the second metal layer 105.
  • Each patch cord 400 is formed in the second metal layer 105 and the third metal layer 201, and each patch cord 400 includes a first portion 4001 located in the second metal layer 105 and a second portion 4002 located in the third metal layer 201 , And the two are connected in parallel.
  • the array substrate shown in FIG. 4 further includes: a first substrate 101, an active layer 103, a first insulating layer 104, a second insulating layer 106, a third insulating layer 202, a color resist layer 107, and a flat layer 108 , The pixel electrode layer 109 and the columnar spacer 110.
  • the first substrate 101 is preferably a glass substrate.
  • the first metal layer 102 is disposed on the first substrate 101, and the scan line 10 and the gate of the TFT integrated with the scan line 10 are formed in the first metal layer 102.
  • the active layer 103 is provided on the first metal layer 102.
  • the first insulating layer 104 is disposed on the first substrate 101 and covers the first metal layer 102.
  • the second metal layer 105 is disposed on the first insulating layer 104, and the data line 20, the source and drain electrodes 1051 of the TFT integrated with the data line 20 are formed in the second metal layer 105, and the first portion 4001 of the transfer line 400.
  • the data line 20 and the source and drain electrodes 1051 of the TFT are respectively located on the active layer 103, and the first part 4001 of the transfer line 400 is connected to the scan line 10 through the first via 111.
  • the first via 111 is formed in the first insulating layer 104 and located on the first metal layer 102.
  • the second insulating layer 106 is disposed on the first insulating layer 104 and covers the second metal layer 105.
  • the third metal layer 201 is provided on the second insulating layer 106.
  • the second part 4002 of the patch cord 400 is formed in the third metal layer 201.
  • Part 4001 is connected.
  • the third insulating layer 202 is disposed on the second insulating layer 106 and covers the third metal layer 201.
  • the color resist layer 107 is disposed on the second insulating layer 106.
  • the flat layer 108 is provided on the color resist layer 107.
  • the pixel electrode layer 109 is disposed on the flat layer 108 and is connected to the drain 1051 of the TFT through the second via 112.
  • the second via hole 112 is formed in the second insulating layer 106, the third insulating layer 202, the color resist layer 107 and the flat layer 108 and is located on the drain electrode 1051 of the TFT.
  • the columnar spacer 110 is disposed on the pixel electrode layer 109.
  • each patch cord 400 in this embodiment adopts a double metal layer design, which is formed in the second metal layer 105 and the third metal layer 201, and each patch cord 400 is located in the second metal layer 105 The part of is connected in parallel with the part of the third metal layer 201.
  • the double metal layer design can reduce the resistance of each patch cord 400, thereby making the resistance of each patch cord unit 40 smaller. Therefore, the fall time of the scan signal can be further shortened, the charging rate of each sub-pixel electrode can be increased, and the display image quality can be further improved.
  • the array substrate further has a non-display area.
  • the non-display area includes a left frame B1, a right frame B2, an upper frame B3, and a lower frame B4.
  • the portions of all the patch cords 400 in each patch cord unit 40 that extend to the non-display area are shorted to form a short cord. All the short wires shown in Figure 2 are located in the lower frame B4.
  • first chip-on-chip films and several second chip-on-chip films are provided in the non-display area.
  • the several first chip-on-chip films and several second chip-on-chip films shown in FIG. 2 are all located in the lower frame B4, and the number of the first chip-on-chip films is two, which are called G_COF1 and G_COF2, respectively.
  • the number is 1, called D_COF.
  • Each of the first flip-chip films corresponds to a short wire, and is electrically connected to the corresponding short wire to input a scanning signal to the electrically connected short wire.
  • G_COF1 and G_COF2 shown in FIG. 2 respectively correspond to the short wires. And respectively connect to the corresponding short wires to input scanning signals to the electrically connected short wires.
  • Each second flip chip film corresponds to a part of the data line 20 and is electrically connected to the corresponding part of the data line 20 to input a data signal to the electrically connected part of the data line 20.
  • D_COF shown in FIG. 2 corresponds to a number of data The line 20 is electrically connected to the corresponding data lines 20 to input data signals to the electrically connected data lines 20.
  • the present invention also provides a display device.
  • the display device includes a display panel, and the display panel includes an array substrate.
  • FIG. 2 is a schematic diagram of wiring in the array substrate provided by an embodiment of the present invention. As shown in FIG.
  • a number of scan lines 10 and a number of data lines 20 are provided in the display area AA.
  • all the scan lines 10 are spaced apart from each other and extend along the first direction
  • all the data lines 20 are spaced apart from each other and extend along the second direction
  • the first direction is perpendicular to the second direction.
  • the first direction is the horizontal direction in FIG. 2
  • the second direction is the vertical direction in FIG. 2.
  • the first direction may also be a vertical direction
  • the second direction is a horizontal direction.
  • each sub-pixel area 30 is provided with a sub-pixel electrode (not shown in FIG. 2) and a corresponding thin film transistor (Thin Film Transistor, TFT) (not shown in FIG. 2).
  • the gate of each TFT is electrically connected to the corresponding scan line 10
  • the source of each TFT is electrically connected to the corresponding data line 20
  • the drain of each TFT is electrically connected to the corresponding sub-pixel electrode.
  • each patch cord unit 40 includes at least two patch cords 400 connected in parallel.
  • Each patch cord unit 40 shown in FIG. 2 includes two patch cords.
  • Each scan line 10 corresponds to at least one patch cord unit 40. It should be noted that the number of patch cord units 40 corresponding to each scan line 10 is related to the driving mode of all scan lines 10. For example, if the driving mode is unilateral driving, each scan line 10 corresponds to one patch cord unit 40; if the driving mode is dual-sided driving, each scan line corresponds to two patch cord units 40, and so on.
  • the driving mode shown in FIG. 2 is bilateral driving, and at this time, each scan line 10 corresponds to two patch cord units 40. It can be understood that, in other embodiments, the driving mode of the scan line 10 may also be unilateral driving, and in this case, each scan line 10 corresponds to a patch cord unit 40.
  • Each scan line 10 is electrically connected to all the patch cords 400 in all corresponding patch cord units 40, and each patch cord 400 is used to input a scan signal to the scan line 10 that is electrically connected.
  • the patch cord unit 40 since the array substrate in the display panel replaces the scan switch wires in the prior art by the patch cord unit 40 to complete the scanning signal transmission function, and the patch cord unit 40 includes at least two patch cords 400 connected in parallel. Therefore, the resistance of each patch cord unit 40 is smaller than the resistance of the scan patch cord in the prior art, which can greatly shorten the fall time of the scan signal, thereby increasing the charging rate of each sub-pixel electrode, thereby increasing Display the effect of picture quality.
  • each patch cord 400 corresponds to a data line 20, and different patch cords 400 correspond to different data lines 20.
  • each patch cord 400 is adjacent to the corresponding data line 20 and is located on the left side of the corresponding data line 20. It is understandable that, in other embodiments, each patch cord 400 may also be located on the right side of the corresponding data line 20; or, in other embodiments, part of the patch cord 400 may be located on the left side of the corresponding data line 20, and part of the patch cord 400 may be located on the left side of the corresponding data line 20.
  • the patch cord 400 is located on the right side of the corresponding data line 20.
  • each patch cord unit 40 includes two parallel patch cords 400, and two data lines 20 corresponding to the two parallel patch cords 400 are adjacent to each other. In other embodiments, if each patch cord unit 40 includes three parallel patch cords 400, the three data lines 20 corresponding to the three parallel patch cords 400 are adjacent in turn.
  • all patch cords 400 in the patch cord unit 40 adopt the above arrangement, which can reduce the amount of data line 20 spanning between any two adjacent patch cords 400. Quantity, thereby reducing electrostatic damage in the display area AA.
  • each patch cord 400 is located on the same side of the corresponding data line 20.
  • each sub-pixel electrode in the column of sub-pixel regions 30 is electrically connected to the same data line 20 through a corresponding TFT, and the data line 20 is referred to as the corresponding column of sub-pixel region 30. ⁇ 20 ⁇ The data line 20.
  • each transition wire 400 corresponds to a data line 20 can also be understood as that each transition wire 400 is provided in a column of sub-pixel regions 30.
  • “Different transfer lines 400 correspond to different data lines 20” can also be understood as the different transfer lines 400 are provided in the sub-pixel regions 30 in different columns.
  • “All the data lines 20 corresponding to all the patch cords 400 in each patch cord unit 40 are adjacent to each other in turn.” It can also be understood that all the column sub-pixel regions 30 where all patch cords 400 in each patch cord unit 40 are located are sequentially opposite to each other. adjacent.
  • all patch cords 400 in the patch cord unit 40 adopt the above arrangement, which can reduce the data lines spanning between any two adjacent patch cords 400.
  • all the scan lines 10 and all the data lines 20 are insulated and crossed, all the scan lines 10 and all the data lines 20 are respectively arranged in different metal layers of the array substrate.
  • each patch cord 400 adopts a single metal layer design, as shown in FIG. 3, which is a schematic diagram of a film layer of an array substrate provided by an embodiment of the present invention.
  • the array substrate includes a first metal layer 102 and a second metal layer 105 disposed on the first metal layer 102, each scan line 10 is formed in the first metal layer 102, and each data line 20 is formed in the second metal layer 105 middle.
  • the array substrate shown in FIG. 3 further includes: a first substrate 101, an active layer 103, a first insulating layer 104, a second insulating layer 106, a color resist layer 107, a flat layer 108, a pixel electrode layer 109, and Columnar septa 110.
  • the first substrate 101 is preferably a glass substrate.
  • the first metal layer 102 is disposed on the first substrate 101, and the scan line 10 and the gate of the TFT integrated with the scan line 10 are formed in the first metal layer 102.
  • the active layer 103 is provided on the first metal layer 102.
  • the first insulating layer 104 is disposed on the first substrate 101 and covers the first metal layer 102.
  • the second metal layer 105 is disposed on the first insulating layer 104, and the data line 20, the source and drain electrodes 1051 of the TFT integrated with the data line 20 and the transfer line 400 are formed in the second metal layer 105.
  • the data line 20 and the source and drain electrodes 1051 of the TFT are respectively located on the active layer 103, and the transfer line 400 is connected to the scan line 10 through the first via 111.
  • the first via 111 is formed in the first insulating layer 104 and located on the first metal layer 102.
  • the second insulating layer 106 is disposed on the first insulating layer 104 and covers the second metal layer 105.
  • the color resist layer 107 is disposed on the second insulating layer 106.
  • the flat layer 108 is provided on the color resist layer 107.
  • the pixel electrode layer 109 is disposed on the flat layer 108 and is connected to the drain 1051 of the TFT through the second via 112.
  • the second via hole 112 is formed in the second insulating layer 106, the color resist layer 107 and the flat layer 108 and is located on the drain electrode 1051 of the TFT.
  • the columnar spacer 110 is disposed on the pixel electrode layer 109.
  • each transfer line 400 adopts a bimetallic layer design, as shown in FIG. 4, which is a schematic diagram of a film layer of another array substrate provided by an embodiment of the present invention.
  • the array substrate includes a first metal layer 102, a second metal layer 105 provided on the first metal layer 102, and a third metal layer 201 provided on the second metal layer 105, and each scan line 10 is formed on the first metal layer 102
  • each data line 20 is formed in the second metal layer 105.
  • Each patch cord 400 is formed in the second metal layer 105 and the third metal layer 201, and each patch cord 400 includes a first portion 4001 located in the second metal layer 105 and a second portion 4002 located in the third metal layer 201 , And the two are connected in parallel.
  • the array substrate shown in FIG. 4 further includes: a first substrate 101, an active layer 103, a first insulating layer 104, a second insulating layer 106, a third insulating layer 202, a color resist layer 107, and a flat layer 108 , The pixel electrode layer 109 and the columnar spacer 110.
  • the first substrate 101 is preferably a glass substrate.
  • the first metal layer 102 is disposed on the first substrate 101, and the scan line 10 and the gate of the TFT integrated with the scan line 10 are formed in the first metal layer 102.
  • the active layer 103 is provided on the first metal layer 102.
  • the first insulating layer 104 is disposed on the first substrate 101 and covers the first metal layer 102.
  • the second metal layer 105 is disposed on the first insulating layer 104, and the data line 20, the source and drain electrodes 1051 of the TFT integrated with the data line 20 are formed in the second metal layer 105, and the first portion 4001 of the transfer line 400.
  • the data line 20 and the source and drain electrodes 1051 of the TFT are respectively located on the active layer 103, and the first part 4001 of the transfer line 400 is connected to the scan line 10 through the first via 111.
  • the first via 111 is formed in the first insulating layer 104 and located on the first metal layer 102.
  • the second insulating layer 106 is disposed on the first insulating layer 104 and covers the second metal layer 105.
  • the third metal layer 201 is provided on the second insulating layer 106.
  • the second part 4002 of the patch cord 400 is formed in the third metal layer 201.
  • Part 4001 is connected.
  • the third insulating layer 202 is disposed on the second insulating layer 106 and covers the third metal layer 201.
  • the color resist layer 107 is disposed on the second insulating layer 106.
  • the flat layer 108 is provided on the color resist layer 107.
  • the pixel electrode layer 109 is disposed on the flat layer 108 and is connected to the drain 1051 of the TFT through the second via 112.
  • the second via hole 112 is formed in the second insulating layer 106, the third insulating layer 202, the color resist layer 107 and the flat layer 108 and is located on the drain electrode 1051 of the TFT.
  • the columnar spacer 110 is disposed on the pixel electrode layer 109.
  • each patch cord 400 in this embodiment adopts a double metal layer design, which is formed in the second metal layer 105 and the third metal layer 201, and each patch cord 400 is located in the second metal layer 105 The part of is connected in parallel with the part of the third metal layer 201.
  • the double metal layer design can reduce the resistance of each patch cord 400, thereby making the resistance of each patch cord unit 40 smaller. Therefore, the fall time of the scan signal can be further shortened, the charging rate of each sub-pixel electrode can be increased, and the display image quality can be further improved.
  • the array substrate further has a non-display area.
  • the non-display area includes a left frame B1, a right frame B2, an upper frame B3, and a lower frame B4.
  • the portions of all the patch cords 400 in each patch cord unit 40 that extend to the non-display area are shorted to form a short cord. All the short wires shown in Figure 2 are located in the lower frame B4.
  • first chip-on-chip films and several second chip-on-chip films are provided in the non-display area.
  • the several first chip-on-chip films and several second chip-on-chip films shown in FIG. 2 are all located in the lower frame B4, and the number of the first chip-on-chip films is two, which are called G_COF1 and G_COF2, respectively.
  • the number is 1, called D_COF.
  • Each of the first flip-chip films corresponds to a short wire, and is electrically connected to the corresponding short wire to input a scanning signal to the electrically connected short wire.
  • G_COF1 and G_COF2 shown in FIG. 2 respectively correspond to the short wires. And respectively connect to the corresponding short wires to input scanning signals to the electrically connected short wires.
  • Each second flip chip film corresponds to a part of the data line 20 and is electrically connected to the corresponding part of the data line 20 to input a data signal to the electrically connected part of the data line 20.
  • D_COF shown in FIG. 2 corresponds to a number of data The line 20 is electrically connected to the corresponding data lines 20 to input data signals to the electrically connected data lines 20.

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Abstract

本发明提供了一种阵列基板，通过在阵列基板的显示区中设置若干包括至少两条并联的转接线的转接线单元，可以极大缩短扫描信号的下降时间，从而提高各子像素电极的充电率，进而提高显示画质的效果。本发明还提供一种具有该阵列基板的显示面板及显示装置。本发明还提供一种具有该阵列基板的显示面板及显示装置。

Description

阵列基板、具有该阵列基板的显示面板及显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板、具有该阵列基板的显示面板及显示装置。
 背景技术
目前，制造大尺寸、高解析度和超窄边框的液晶显示面板已经成为了显示面板行业的发展趋势。液晶显示面板通常包括阵列基板、彩膜基板以及分布在阵列基板和彩膜基板之间液晶层。
图1为现有技术中的阵列基板中的走线示意图，如图1所示，该阵列基板划分为显示区AA’和围绕显示区AA’的非显示区。其中，显示区AA’中设有若干沿横向延伸的扫描线100，若干沿纵向延伸且与扫描线100绝缘交叉的数据线200，以及若干沿纵向延伸且与扫描线100电性连接的扫描转接线300。非显示区包括左边框B1’、右边框B2’、上边框B3’和下边框B4’。其中，左边框B1’、右边框B2’和上边框B3’仅作封装用，下边框B4’除了作封装用之外，还设有若干覆晶薄膜。图1中所示的覆晶薄膜的数量为3，分别为G_COF1、G_COF2和D_COF。其中，G_COF1和G_COF2分别电性连接若干扫描转接线300，以通过扫描转接线300向扫描线100传输扫描信号；D_COF电性连接若干数据线200，以向数据线200传输数据信号。
但由于扫描转接线300与数据线200平行设置，因此扫描转接线300的负载极大，从而降低了液晶显示面板中各子像素电极的充电率，导致显示画质的效果差。
 技术问题
本发明提供一种阵列基板、具有该阵列基板的显示面板及显示装置，以解决现有的显示面板及显示装置中由于各子像素电极的充电率低导致显示画质效果差的技术问题。
 技术解决方案
第一方面，本发明提供了一种阵列基板，所述阵列基板具有显示区，所述显示区中设有若干扫描线和若干数据线，所有所述扫描线相互间隔且沿第一方向延伸，所有所述数据线相互间隔且沿第二方向延伸，所述第一方向垂直于所述第二方向，所有所述扫描线与所有所述数据线绝缘交叉，所述显示区中还设有若干转接线单元，每一所述转接线单元包括至少两条并联的转接线，所有所述转接线相互间隔且沿所述第二方向延伸，每一所述扫描线对应至少一个所述转接线单元，每一所述扫描线与对应的所有所述转接线单元中的所有所述转接线电性连接，每一所述转接线用于向电性连接的所述扫描线输入扫描信号。
在一些实施例中，每一所述转接线对应一条所述数据线，不同的所述转接线对应不同的所述数据线，每一所述转接线单元中的所有所述转接线对应的所有所述数据线依次相邻。
在一些实施例中，每一所述转接线位于对应的所述数据线的同侧。
在一些实施例中，所述阵列基板包括第一金属层和设于所述第一金属层上的第二金属层，每一所述扫描线形成于所述第一金属层中，每一所述数据线形成于所述第二金属层中。
在一些实施例中，每一所述转接线形成于所述第二金属层中。
在一些实施例中，所述阵列基板还包括设于所述第二金属层上的第三金属层，每一所述转接线形成于所述第二金属层和所述第三金属层中，每一所述转接线位于所述第二金属层中的部分与位于所述第三金属层中的部分并联。
在一些实施例中，所述阵列基板还具有非显示区，每一所述转接线单元中的所有所述转接线延伸至所述非显示区中的部分短接形成短接线。
在一些实施例中，所述非显示区中设有若干第一覆晶薄膜和若干第二覆晶薄膜；每一所述第一覆晶薄膜对应部分所述短接线，并与对应的部分所述短接线电性连接以向电性连接的部分所述短接线输入扫描信号；每一所述第二覆晶薄膜对应部分所述数据线，并与对应的部分所述数据线电性连接以向电性连接的部分所述数据线输入数据信号。
第二方面，本发明提供了一种显示面板，所述显示面板包括阵列基板，所述阵列基板具有显示区，所述显示区中设有若干扫描线和若干数据线，所有所述扫描线相互间隔且沿第一方向延伸，所有所述数据线相互间隔且沿第二方向延伸，所述第一方向垂直于所述第二方向，所有所述扫描线与所有所述数据线绝缘交叉，所述显示区中还设有若干转接线单元，每一所述转接线单元包括至少两条并联的转接线，所有所述转接线相互间隔且沿所述第二方向延伸，每一所述扫描线对应至少一个所述转接线单元，每一所述扫描线与对应的所有所述转接线单元中的所有所述转接线电性连接，每一所述转接线用于向电性连接的所述扫描线输入扫描信号。
在一些实施例中，每一所述转接线对应一条所述数据线，不同的所述转接线对应不同的所述数据线，每一所述转接线单元中的所有所述转接线对应的所有所述数据线依次相邻。
在一些实施例中，每一所述转接线位于对应的所述数据线的同侧。
在一些实施例中，所述阵列基板包括第一金属层和设于所述第一金属层上的第二金属层，每一所述扫描线形成于所述第一金属层中，每一所述数据线形成于所述第二金属层中。
在一些实施例中，每一所述转接线形成于所述第二金属层中。
在一些实施例中，所述阵列基板还包括设于所述第二金属层上的第三金属层，每一所述转接线形成于所述第二金属层和所述第三金属层中，每一所述转接线位于所述第二金属层中的部分与位于所述第三金属层中的部分并联。
第三方面，本发明提供了一种显示装置，所述显示装置包括显示面板，所述显示面板包括阵列基板，所述阵列基板具有显示区，所述显示区中设有若干扫描线和若干数据线，所有所述扫描线相互间隔且沿第一方向延伸，所有所述数据线相互间隔且沿第二方向延伸，所述第一方向垂直于所述第二方向，所有所述扫描线与所有所述数据线绝缘交叉，所述显示区中还设有若干转接线单元，每一所述转接线单元包括至少两条并联的转接线，所有所述转接线相互间隔且沿所述第二方向延伸，每一所述扫描线对应至少一个所述转接线单元，每一所述扫描线与对应的所有所述转接线单元中的所有所述转接线电性连接，每一所述转接线用于向电性连接的所述扫描线输入扫描信号。
在一些实施例中，每一所述转接线对应一条所述数据线，不同的所述转接线对应不同的所述数据线，每一所述转接线单元中的所有所述转接线对应的所有所述数据线依次相邻。
在一些实施例中，每一所述转接线位于对应的所述数据线的同侧。
在一些实施例中，所述阵列基板包括第一金属层和设于所述第一金属层上的第二金属层，每一所述扫描线形成于所述第一金属层中，每一所述数据线形成于所述第二金属层中。
在一些实施例中，每一所述转接线形成于所述第二金属层中。
在一些实施例中，所述阵列基板还包括设于所述第二金属层上的第三金属层，每一所述转接线形成于所述第二金属层和所述第三金属层中，每一所述转接线位于所述第二金属层中的部分与位于所述第三金属层中的部分并联。
 有益效果
本发明提供的阵列基板，通过转接线单元代替现有技术中的扫描转接线完成扫描信号的传输功能，由于转接线单元包括至少两条并联的转接线，因此每个转接线单元的电阻相较于现有技术中扫描转接线的电阻来说更小，这样可以极大缩短扫描信号的下降时间，从而提高各子像素电极的充电率，当该阵列基板应用于显示面板及显示装置中时，能够提高显示画质的效果。
 附图说明
图1为现有技术中的阵列基板中的走线示意图。
图2为本发明的实施例提供的阵列基板中的走线示意图。
图3为本发明的实施例提供的一种阵列基板的膜层示意图。
图4为本发明的实施例提供的另一种阵列基板的膜层示意图。
 本发明的实施方式
为使本发明的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本发明进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。
图2为本发明的实施例提供的阵列基板中的走线示意图，如图2所示，该阵列基板划分为显示区AA和围绕显示区AA的非显示区，其中，非显示区包括左边框B1、右边框B2、上边框B3和下边框B4。
显示区AA中设有若干扫描线10和若干数据线20。其中，所有扫描线10相互间隔且沿第一方向延伸，所有数据线20相互间隔且沿第二方向延伸，第一方向垂直于第二方向。在本实施例中，第一方向为图2中的水平方向，第二方向为图2中的竖直方向。可以理解地，在其它实施例中，第一方向还可以为竖直方向，此时第二方向为水平方向。
所有扫描线10与所有数据线20绝缘交叉，将显示区AA划分为若干子像素区30。其中，每一子像素区30中设有子像素电极（图2中未示出）和对应的薄膜晶体管（Thin Film Transistor，TFT）（图2中未示出）。每一TFT的栅极与对应的扫描线10电性连接，每一TFT的源极与对应的数据线20电性连接，每一TFT的漏极与对应的子像素电极电性连接。
如图2所示，显示区AA中还设有若干转接线单元40，每一转接线单元40包括至少两条并联的转接线400，图2中所示的每一转接线单元40包括两条并联的转接线400。可以理解地，在其它实施例中，每一转接线单元40还可以包括三条及以上并联的转接线400。所有转接线400相互间隔且沿第二方向延伸。
每一扫描线10对应至少一个转接线单元40。需要说明的是，每一扫描线10对应的转接线单元40的数量与所有扫描线10的驱动方式相关。例如，若驱动方式为单边驱动，则每一扫描线10对应一个转接线单元40；若驱动方式为双边驱动，则每一扫描线对应两个转接线单元40，依次类推。图2中所示的驱动方式为双边驱动，此时每一扫描线10对应两个转接线单元40。可以理解地，在其它实施例中，扫描线10的驱动方式还可以为单边驱动，此时每一扫描线10对应一个转接线单元40。
每一扫描线10与对应的所有转接线单元40中的所有转接线400电性连接，每一转接线400用于向电性连接的扫描线10输入扫描信号。
本发明提供的阵列基板，通过转接线单元40代替现有技术中的扫描转接线完成扫描信号的传输功能，由于转接线单元40包括至少两条并联的转接线400，因此每个转接线单元40的电阻相较于现有技术中扫描转接线的电阻来说更小，这样可以极大缩短扫描信号的下降时间，从而提高各子像素电极的充电率，当该阵列基板应用于显示面板及显示装置中时，能够提高显示画质的效果。
在一些实施例中，每一转接线400对应一条数据线20，不同的转接线400对应不同的数据线20。图2中所示的实施例中，每一转接线400与对应的数据线20紧邻，且位于对应的数据线20的左侧。可以理解地，在其它实施例中，每一转接线400还可以位于对应的数据线20的右侧；或者，在其它实施例中，部分转接线400位于对应的数据线20的左侧，部分转接线400位于对应的数据线20的右侧。
每一转接线单元40中的所有转接线400对应的所有数据线20依次相邻。图2中所示的实施例中，每一转接线单元40包括两条并联的转接线400，这两条并联的转接线400对应的两条数据线20彼此相邻。在其它实施例中，若每一转接线单元40包括三条并联的转接线400，则这三条并联的转接线400对应的三条数据线20依次相邻。
可以理解地，对于任意一个转接线单元40来说，转接线单元40中的所有转接线400采用上述排布方式，可以减少任意相邻的两条转接线400之间所跨的数据线20的数量，从而降低显示区AA中的静电伤害。
在一些实施例中，每一转接线400位于对应的数据线20的同侧。
具体的，对于任意一列子像素区30而言，该列子像素区30中的各子像素电极通过对应的TFT电性连接同一条数据线20，将该数据线20称为该列子像素区30对应的数据线20。
因此，“每一转接线400对应一条数据线20”还可理解为，每一转接线400设于一列子像素区30中。“不同的转接线400对应不同的数据线20”还可理解为，不同的转接线400设于不同列子像素区30中。“每一转接线单元40中的所有转接线400对应的所有数据线20依次相邻”还可理解为，每一转接线单元40中的所有转接线400所处的所有列子像素区30依次相邻。
可以理解的是，对于任意一个转接线单元40来说，转接线单元40中的所有转接线400的采用上述排布方式，可以减少任意相邻的两条转接线400之间所跨的数据线20的数量，从而降低显示区AA中的静电伤害。
为了实现所有扫描线10与所有数据线20绝缘交叉的布局，将所有扫描线10与所有数据线20分别设于阵列基板的不同的金属层中。
在一些实施例中，每一转接线400采用单金属层设计，如图3所示，图3为本发明的实施例提供的一种阵列基板的膜层示意图。阵列基板包括第一金属层102和设于第一金属层102上的第二金属层105，每一扫描线10形成于第一金属层102中，每一数据线20形成于第二金属层105中。
具体的，图3中所示的阵列基板还包括：第一基板101、有源层103、第一绝缘层104、第二绝缘层106、色阻层107、平坦层108、像素电极层109和柱状隔垫物110。
其中，第一基板101优选为玻璃基板。
第一金属层102设于第一基板101上，第一金属层102中形成有扫描线10和与扫描线10一体的TFT的栅极。
有源层103设于第一金属层102上。
第一绝缘层104设于第一基板101上，且覆盖第一金属层102。
第二金属层105设于第一绝缘层104上，第二金属层105中形成有数据线20、与数据线20一体的TFT的源极、漏极1051和转接线400。其中，数据线20、TFT的源极和漏极1051分别位于有源层103上，转接线400通过第一过孔111连接扫描线10。其中，第一过孔111形成于第一绝缘层104中且位于第一金属层102上。
第二绝缘层106设于第一绝缘层104上，且覆盖第二金属层105。
色阻层107设于第二绝缘层106上。
平坦层108设于色阻层107上。
像素电极层109设于平坦层108上，且通过第二过孔112连接TFT的漏极1051。其中，第二过孔112形成于第二绝缘层106、色阻层107和平坦层108中且位于TFT的漏极1051上。
柱状隔垫物110设于像素电极层109上。
在一些实施例中，每一转接线400采用双金属层设计，如图4所示，图4为本发明的实施例提供的另一种阵列基板的膜层示意图。阵列基板包括第一金属层102、设于第一金属层102上的第二金属层105以及设于第二金属层105的第三金属层201，每一扫描线10形成于第一金属层102中，每一数据线20形成于第二金属层105中。每一转接线400形成于第二金属层105和第三金属层201中，每一转接线400包括位于第二金属层105中的第一部分4001与位于第三金属层201中的第二部分4002，且二者并联。
具体的，图4中所示的阵列基板还包括：第一基板101、有源层103、第一绝缘层104、第二绝缘层106、第三绝缘层202、色阻层107、平坦层108、像素电极层109和柱状隔垫物110。
其中，第一基板101优选为玻璃基板。
第一金属层102设于第一基板101上，第一金属层102中形成有扫描线10和与扫描线10一体的TFT的栅极。
有源层103设于第一金属层102上。
第一绝缘层104设于第一基板101上，且覆盖第一金属层102。
第二金属层105设于第一绝缘层104上，第二金属层105中形成有数据线20、与数据线20一体的TFT的源极、漏极1051和转接线400的第一部分4001。其中，数据线20、TFT的源极和漏极1051分别位于有源层103上，转接线400的第一部分4001通过第一过孔111连接扫描线10。其中，第一过孔111形成于第一绝缘层104中且位于第一金属层102上。
第二绝缘层106设于第一绝缘层104上，且覆盖第二金属层105。
第三金属层201设于第二绝缘层106上，第三金属层201中形成有转接线400的第二部分4002，转接线400的第二部分4002通过第三过孔113与接线400的第一部分4001连接。
第三绝缘层202设于第二绝缘层106上，且覆盖第三金属层201。
色阻层107设于第二绝缘层106上。
平坦层108设于色阻层107上。
像素电极层109设于平坦层108上，且通过第二过孔112连接TFT的漏极1051。其中，第二过孔112形成于第二绝缘层106、第三绝缘层202、色阻层107和平坦层108中且位于TFT的漏极1051上。
柱状隔垫物110设于像素电极层109上。
可以理解的是，本实施例中的每一转接线400采用双金属层设计，其形成于第二金属层105和第三金属层201中，且每一转接线400位于第二金属层105中的部分与其位于第三金属层201中的部分并联，相较于单金属层设计，双金属层设计能够降低每一转接线400的电阻，从而使每一转接线单元40的电阻更小。因此可以进一步缩短扫描信号的下降时间，提高各子像素电极的充电率，当该阵列基板应用于显示面板及显示装置中时，能够进一步提高显示画质的效果。
在一些实施例中，阵列基板还具有非显示区，如图2所示，非显示区包括左边框B1、右边框B2、上边框B3和下边框B4。
如图2所示，每一转接线单元40中的所有转接线400延伸至非显示区中的部分短接形成短接线。图2中所示的所有短接线均位于下边框B4中。
在一些实施例中，如图2所示，非显示区中设有若干第一覆晶薄膜和若干第二覆晶薄膜。图2中所示的若干第一覆晶薄膜和若干第二覆晶薄膜均位于下边框B4中，且第一覆晶薄膜的数量为2，分别称为G_COF1和G_COF2，第二覆晶薄膜的数量为1，称为D_COF。
每一第一覆晶薄膜对应部分短接线，并与对应的部分短接线电性连接以向电性连接的部分短接线输入扫描信号，例如，图2中所示的G_COF1和G_COF2分别对应部分短接线，并分别与对应的部分短接线电性连接以向电性连接的部分短接线输入扫描信号。每一第二覆晶薄膜对应部分数据线20，并与对应的部分数据线20电性连接以向电性连接的部分数据线20输入数据信号，例如，图2中所示的D_COF对应若干数据线20，并与对应的若干数据线20电性连接以向电性连接的若干数据线20输入数据信号。
本发明还提供一种显示面板，显示面板包括阵列基板，图2为本发明的实施例提供的阵列基板中的走线示意图，如图2所示，该阵列基板划分为显示区AA和围绕显示区AA的非显示区，其中，非显示区包括左边框B1、右边框B2、上边框B3和下边框B4。
显示区AA中设有若干扫描线10和若干数据线20。其中，所有扫描线10相互间隔且沿第一方向延伸，所有数据线20相互间隔且沿第二方向延伸，第一方向垂直于第二方向。在本实施例中，第一方向为图2中的水平方向，第二方向为图2中的竖直方向。可以理解地，在其它实施例中，第一方向还可以为竖直方向，此时第二方向为水平方向。
所有扫描线10与所有数据线20绝缘交叉，将显示区AA划分为若干子像素区30。其中，每一子像素区30中设有子像素电极（图2中未示出）和对应的薄膜晶体管（Thin Film Transistor，TFT）（图2中未示出）。每一TFT的栅极与对应的扫描线10电性连接，每一TFT的源极与对应的数据线20电性连接，每一TFT的漏极与对应的子像素电极电性连接。
如图2所示，显示区AA中还设有若干转接线单元40，每一转接线单元40包括至少两条并联的转接线400，图2中所示的每一转接线单元40包括两条并联的转接线400。可以理解地，在其它实施例中，每一转接线单元40还可以包括三条及以上并联的转接线400。所有转接线400相互间隔且沿第二方向延伸。
每一扫描线10对应至少一个转接线单元40。需要说明的是，每一扫描线10对应的转接线单元40的数量与所有扫描线10的驱动方式相关。例如，若驱动方式为单边驱动，则每一扫描线10对应一个转接线单元40；若驱动方式为双边驱动，则每一扫描线对应两个转接线单元40，依次类推。图2中所示的驱动方式为双边驱动，此时每一扫描线10对应两个转接线单元40。可以理解地，在其它实施例中，扫描线10的驱动方式还可以为单边驱动，此时每一扫描线10对应一个转接线单元40。
每一扫描线10与对应的所有转接线单元40中的所有转接线400电性连接，每一转接线400用于向电性连接的扫描线10输入扫描信号。
本发明提供的显示面板中，由于阵列基板通过转接线单元40代替现有技术中的扫描转接线完成扫描信号的传输功能，且转接线单元40包括至少两条并联的转接线400，因此每个转接线单元40的电阻相较于现有技术中扫描转接线的电阻来说更小，这样可以极大缩短扫描信号的下降时间，从而提高各子像素电极的充电率，进而提高显示画质的效果。
在一些实施例中，每一转接线400对应一条数据线20，不同的转接线400对应不同的数据线20。图2中所示的实施例中，每一转接线400与对应的数据线20紧邻，且位于对应的数据线20的左侧。可以理解地，在其它实施例中，每一转接线400还可以位于对应的数据线20的右侧；或者，在其它实施例中，部分转接线400位于对应的数据线20的左侧，部分转接线400位于对应的数据线20的右侧。
每一转接线单元40中的所有转接线400对应的所有数据线20依次相邻。图2中所示的实施例中，每一转接线单元40包括两条并联的转接线400，这两条并联的转接线400对应的两条数据线20彼此相邻。在其它实施例中，若每一转接线单元40包括三条并联的转接线400，则这三条并联的转接线400对应的三条数据线20依次相邻。
可以理解地，对于任意一个转接线单元40来说，转接线单元40中的所有转接线400采用上述排布方式，可以减少任意相邻的两条转接线400之间所跨的数据线20的数量，从而降低显示区AA中的静电伤害。
在一些实施例中，每一转接线400位于对应的数据线20的同侧。
具体的，对于任意一列子像素区30而言，该列子像素区30中的各子像素电极通过对应的TFT电性连接同一条数据线20，将该数据线20称为该列子像素区30对应的数据线20。
因此，“每一转接线400对应一条数据线20”还可理解为，每一转接线400设于一列子像素区30中。“不同的转接线400对应不同的数据线20”还可理解为，不同的转接线400设于不同列子像素区30中。“每一转接线单元40中的所有转接线400对应的所有数据线20依次相邻”还可理解为，每一转接线单元40中的所有转接线400所处的所有列子像素区30依次相邻。
可以理解的是，对于任意一个转接线单元40来说，转接线单元40中的所有转接线400的采用上述排布方式，可以减少任意相邻的两条转接线400之间所跨的数据线20的数量，从而降低显示区AA中的静电伤害。
为了实现所有扫描线10与所有数据线20绝缘交叉的布局，将所有扫描线10与所有数据线20分别设于阵列基板的不同的金属层中。
在一些实施例中，每一转接线400采用单金属层设计，如图3所示，图3为本发明的实施例提供的一种阵列基板的膜层示意图。阵列基板包括第一金属层102和设于第一金属层102上的第二金属层105，每一扫描线10形成于第一金属层102中，每一数据线20形成于第二金属层105中。
具体的，图3中所示的阵列基板还包括：第一基板101、有源层103、第一绝缘层104、第二绝缘层106、色阻层107、平坦层108、像素电极层109和柱状隔垫物110。
其中，第一基板101优选为玻璃基板。
第一金属层102设于第一基板101上，第一金属层102中形成有扫描线10和与扫描线10一体的TFT的栅极。
有源层103设于第一金属层102上。
第一绝缘层104设于第一基板101上，且覆盖第一金属层102。
第二金属层105设于第一绝缘层104上，第二金属层105中形成有数据线20、与数据线20一体的TFT的源极、漏极1051和转接线400。其中，数据线20、TFT的源极和漏极1051分别位于有源层103上，转接线400通过第一过孔111连接扫描线10。其中，第一过孔111形成于第一绝缘层104中且位于第一金属层102上。
第二绝缘层106设于第一绝缘层104上，且覆盖第二金属层105。
色阻层107设于第二绝缘层106上。
平坦层108设于色阻层107上。
像素电极层109设于平坦层108上，且通过第二过孔112连接TFT的漏极1051。其中，第二过孔112形成于第二绝缘层106、色阻层107和平坦层108中且位于TFT的漏极1051上。
柱状隔垫物110设于像素电极层109上。
在一些实施例中，每一转接线400采用双金属层设计，如图4所示，图4为本发明的实施例提供的另一种阵列基板的膜层示意图。阵列基板包括第一金属层102、设于第一金属层102上的第二金属层105以及设于第二金属层105的第三金属层201，每一扫描线10形成于第一金属层102中，每一数据线20形成于第二金属层105中。每一转接线400形成于第二金属层105和第三金属层201中，每一转接线400包括位于第二金属层105中的第一部分4001与位于第三金属层201中的第二部分4002，且二者并联。
具体的，图4中所示的阵列基板还包括：第一基板101、有源层103、第一绝缘层104、第二绝缘层106、第三绝缘层202、色阻层107、平坦层108、像素电极层109和柱状隔垫物110。
其中，第一基板101优选为玻璃基板。
第一金属层102设于第一基板101上，第一金属层102中形成有扫描线10和与扫描线10一体的TFT的栅极。
有源层103设于第一金属层102上。
第一绝缘层104设于第一基板101上，且覆盖第一金属层102。
第二金属层105设于第一绝缘层104上，第二金属层105中形成有数据线20、与数据线20一体的TFT的源极、漏极1051和转接线400的第一部分4001。其中，数据线20、TFT的源极和漏极1051分别位于有源层103上，转接线400的第一部分4001通过第一过孔111连接扫描线10。其中，第一过孔111形成于第一绝缘层104中且位于第一金属层102上。
第二绝缘层106设于第一绝缘层104上，且覆盖第二金属层105。
第三金属层201设于第二绝缘层106上，第三金属层201中形成有转接线400的第二部分4002，转接线400的第二部分4002通过第三过孔113与接线400的第一部分4001连接。
第三绝缘层202设于第二绝缘层106上，且覆盖第三金属层201。
色阻层107设于第二绝缘层106上。
平坦层108设于色阻层107上。
像素电极层109设于平坦层108上，且通过第二过孔112连接TFT的漏极1051。其中，第二过孔112形成于第二绝缘层106、第三绝缘层202、色阻层107和平坦层108中且位于TFT的漏极1051上。
柱状隔垫物110设于像素电极层109上。
可以理解的是，本实施例中的每一转接线400采用双金属层设计，其形成于第二金属层105和第三金属层201中，且每一转接线400位于第二金属层105中的部分与其位于第三金属层201中的部分并联，相较于单金属层设计，双金属层设计能够降低每一转接线400的电阻，从而使每一转接线单元40的电阻更小。因此可以进一步缩短扫描信号的下降时间，提高各子像素电极的充电率，进一步提高显示画质的效果。
在一些实施例中，阵列基板还具有非显示区，如图2所示，非显示区包括左边框B1、右边框B2、上边框B3和下边框B4。
如图2所示，每一转接线单元40中的所有转接线400延伸至非显示区中的部分短接形成短接线。图2中所示的所有短接线均位于下边框B4中。
在一些实施例中，如图2所示，非显示区中设有若干第一覆晶薄膜和若干第二覆晶薄膜。图2中所示的若干第一覆晶薄膜和若干第二覆晶薄膜均位于下边框B4中，且第一覆晶薄膜的数量为2，分别称为G_COF1和G_COF2，第二覆晶薄膜的数量为1，称为D_COF。
每一第一覆晶薄膜对应部分短接线，并与对应的部分短接线电性连接以向电性连接的部分短接线输入扫描信号，例如，图2中所示的G_COF1和G_COF2分别对应部分短接线，并分别与对应的部分短接线电性连接以向电性连接的部分短接线输入扫描信号。每一第二覆晶薄膜对应部分数据线20，并与对应的部分数据线20电性连接以向电性连接的部分数据线20输入数据信号，例如，图2中所示的D_COF对应若干数据线20，并与对应的若干数据线20电性连接以向电性连接的若干数据线20输入数据信号。
本发明还提供一种显示装置，显示装置包括显示面板，显示面板包括阵列基板，图2为本发明的实施例提供的阵列基板中的走线示意图，如图2所示，该阵列基板划分为显示区AA和围绕显示区AA的非显示区，其中，非显示区包括左边框B1、右边框B2、上边框B3和下边框B4。
显示区AA中设有若干扫描线10和若干数据线20。其中，所有扫描线10相互间隔且沿第一方向延伸，所有数据线20相互间隔且沿第二方向延伸，第一方向垂直于第二方向。在本实施例中，第一方向为图2中的水平方向，第二方向为图2中的竖直方向。可以理解地，在其它实施例中，第一方向还可以为竖直方向，此时第二方向为水平方向。
所有扫描线10与所有数据线20绝缘交叉，将显示区AA划分为若干子像素区30。其中，每一子像素区30中设有子像素电极（图2中未示出）和对应的薄膜晶体管（Thin Film Transistor，TFT）（图2中未示出）。每一TFT的栅极与对应的扫描线10电性连接，每一TFT的源极与对应的数据线20电性连接，每一TFT的漏极与对应的子像素电极电性连接。
如图2所示，显示区AA中还设有若干转接线单元40，每一转接线单元40包括至少两条并联的转接线400，图2中所示的每一转接线单元40包括两条并联的转接线400。可以理解地，在其它实施例中，每一转接线单元40还可以包括三条及以上并联的转接线400。所有转接线400相互间隔且沿第二方向延伸。
每一扫描线10对应至少一个转接线单元40。需要说明的是，每一扫描线10对应的转接线单元40的数量与所有扫描线10的驱动方式相关。例如，若驱动方式为单边驱动，则每一扫描线10对应一个转接线单元40；若驱动方式为双边驱动，则每一扫描线对应两个转接线单元40，依次类推。图2中所示的驱动方式为双边驱动，此时每一扫描线10对应两个转接线单元40。可以理解地，在其它实施例中，扫描线10的驱动方式还可以为单边驱动，此时每一扫描线10对应一个转接线单元40。
每一扫描线10与对应的所有转接线单元40中的所有转接线400电性连接，每一转接线400用于向电性连接的扫描线10输入扫描信号。
本发明提供的显示装置中，由于显示面板中的阵列基板通过转接线单元40代替现有技术中的扫描转接线完成扫描信号的传输功能，且转接线单元40包括至少两条并联的转接线400，因此每个转接线单元40的电阻相较于现有技术中扫描转接线的电阻来说更小，这样可以极大缩短扫描信号的下降时间，从而提高各子像素电极的充电率，进而提高显示画质的效果。
在一些实施例中，每一转接线400对应一条数据线20，不同的转接线400对应不同的数据线20。图2中所示的实施例中，每一转接线400与对应的数据线20紧邻，且位于对应的数据线20的左侧。可以理解地，在其它实施例中，每一转接线400还可以位于对应的数据线20的右侧；或者，在其它实施例中，部分转接线400位于对应的数据线20的左侧，部分转接线400位于对应的数据线20的右侧。
每一转接线单元40中的所有转接线400对应的所有数据线20依次相邻。图2中所示的实施例中，每一转接线单元40包括两条并联的转接线400，这两条并联的转接线400对应的两条数据线20彼此相邻。在其它实施例中，若每一转接线单元40包括三条并联的转接线400，则这三条并联的转接线400对应的三条数据线20依次相邻。
可以理解地，对于任意一个转接线单元40来说，转接线单元40中的所有转接线400采用上述排布方式，可以减少任意相邻的两条转接线400之间所跨的数据线20的数量，从而降低显示区AA中的静电伤害。
在一些实施例中，每一转接线400位于对应的数据线20的同侧。
具体的，对于任意一列子像素区30而言，该列子像素区30中的各子像素电极通过对应的TFT电性连接同一条数据线20，将该数据线20称为该列子像素区30对应的数据线20。
因此，“每一转接线400对应一条数据线20”还可理解为，每一转接线400设于一列子像素区30中。“不同的转接线400对应不同的数据线20”还可理解为，不同的转接线400设于不同列子像素区30中。“每一转接线单元40中的所有转接线400对应的所有数据线20依次相邻”还可理解为，每一转接线单元40中的所有转接线400所处的所有列子像素区30依次相邻。
可以理解的是，对于任意一个转接线单元40来说，转接线单元40中的所有转接线400的采用上述排布方式，可以减少任意相邻的两条转接线400之间所跨的数据线20的数量，从而降低显示区AA中的静电伤害。
为了实现所有扫描线10与所有数据线20绝缘交叉的布局，将所有扫描线10与所有数据线20分别设于阵列基板的不同的金属层中。
在一些实施例中，每一转接线400采用单金属层设计，如图3所示，图3为本发明的实施例提供的一种阵列基板的膜层示意图。阵列基板包括第一金属层102和设于第一金属层102上的第二金属层105，每一扫描线10形成于第一金属层102中，每一数据线20形成于第二金属层105中。
具体的，图3中所示的阵列基板还包括：第一基板101、有源层103、第一绝缘层104、第二绝缘层106、色阻层107、平坦层108、像素电极层109和柱状隔垫物110。
其中，第一基板101优选为玻璃基板。
第一金属层102设于第一基板101上，第一金属层102中形成有扫描线10和与扫描线10一体的TFT的栅极。
有源层103设于第一金属层102上。
第一绝缘层104设于第一基板101上，且覆盖第一金属层102。
第二金属层105设于第一绝缘层104上，第二金属层105中形成有数据线20、与数据线20一体的TFT的源极、漏极1051和转接线400。其中，数据线20、TFT的源极和漏极1051分别位于有源层103上，转接线400通过第一过孔111连接扫描线10。其中，第一过孔111形成于第一绝缘层104中且位于第一金属层102上。
第二绝缘层106设于第一绝缘层104上，且覆盖第二金属层105。
色阻层107设于第二绝缘层106上。
平坦层108设于色阻层107上。
像素电极层109设于平坦层108上，且通过第二过孔112连接TFT的漏极1051。其中，第二过孔112形成于第二绝缘层106、色阻层107和平坦层108中且位于TFT的漏极1051上。
柱状隔垫物110设于像素电极层109上。
在一些实施例中，每一转接线400采用双金属层设计，如图4所示，图4为本发明的实施例提供的另一种阵列基板的膜层示意图。阵列基板包括第一金属层102、设于第一金属层102上的第二金属层105以及设于第二金属层105的第三金属层201，每一扫描线10形成于第一金属层102中，每一数据线20形成于第二金属层105中。每一转接线400形成于第二金属层105和第三金属层201中，每一转接线400包括位于第二金属层105中的第一部分4001与位于第三金属层201中的第二部分4002，且二者并联。
具体的，图4中所示的阵列基板还包括：第一基板101、有源层103、第一绝缘层104、第二绝缘层106、第三绝缘层202、色阻层107、平坦层108、像素电极层109和柱状隔垫物110。
其中，第一基板101优选为玻璃基板。
第一金属层102设于第一基板101上，第一金属层102中形成有扫描线10和与扫描线10一体的TFT的栅极。
有源层103设于第一金属层102上。
第一绝缘层104设于第一基板101上，且覆盖第一金属层102。
第二金属层105设于第一绝缘层104上，第二金属层105中形成有数据线20、与数据线20一体的TFT的源极、漏极1051和转接线400的第一部分4001。其中，数据线20、TFT的源极和漏极1051分别位于有源层103上，转接线400的第一部分4001通过第一过孔111连接扫描线10。其中，第一过孔111形成于第一绝缘层104中且位于第一金属层102上。
第二绝缘层106设于第一绝缘层104上，且覆盖第二金属层105。
第三金属层201设于第二绝缘层106上，第三金属层201中形成有转接线400的第二部分4002，转接线400的第二部分4002通过第三过孔113与接线400的第一部分4001连接。
第三绝缘层202设于第二绝缘层106上，且覆盖第三金属层201。
色阻层107设于第二绝缘层106上。
平坦层108设于色阻层107上。
像素电极层109设于平坦层108上，且通过第二过孔112连接TFT的漏极1051。其中，第二过孔112形成于第二绝缘层106、第三绝缘层202、色阻层107和平坦层108中且位于TFT的漏极1051上。
柱状隔垫物110设于像素电极层109上。
可以理解的是，本实施例中的每一转接线400采用双金属层设计，其形成于第二金属层105和第三金属层201中，且每一转接线400位于第二金属层105中的部分与其位于第三金属层201中的部分并联，相较于单金属层设计，双金属层设计能够降低每一转接线400的电阻，从而使每一转接线单元40的电阻更小。因此可以进一步缩短扫描信号的下降时间，提高各子像素电极的充电率，进一步提高显示画质的效果。
在一些实施例中，阵列基板还具有非显示区，如图2所示，非显示区包括左边框B1、右边框B2、上边框B3和下边框B4。
如图2所示，每一转接线单元40中的所有转接线400延伸至非显示区中的部分短接形成短接线。图2中所示的所有短接线均位于下边框B4中。
在一些实施例中，如图2所示，非显示区中设有若干第一覆晶薄膜和若干第二覆晶薄膜。图2中所示的若干第一覆晶薄膜和若干第二覆晶薄膜均位于下边框B4中，且第一覆晶薄膜的数量为2，分别称为G_COF1和G_COF2，第二覆晶薄膜的数量为1，称为D_COF。
每一第一覆晶薄膜对应部分短接线，并与对应的部分短接线电性连接以向电性连接的部分短接线输入扫描信号，例如，图2中所示的G_COF1和G_COF2分别对应部分短接线，并分别与对应的部分短接线电性连接以向电性连接的部分短接线输入扫描信号。每一第二覆晶薄膜对应部分数据线20，并与对应的部分数据线20电性连接以向电性连接的部分数据线20输入数据信号，例如，图2中所示的D_COF对应若干数据线20，并与对应的若干数据线20电性连接以向电性连接的若干数据线20输入数据信号。
可以理解的是，对本领域普通技术人员来说，可以根据本发明的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本发明所附的权利要求的保护范围。

Claims (20)

  1. 一种阵列基板，所述阵列基板具有显示区，所述显示区中设有若干扫描线和若干数据线，所有所述扫描线相互间隔且沿第一方向延伸，所有所述数据线相互间隔且沿第二方向延伸，所述第一方向垂直于所述第二方向，所有所述扫描线与所有所述数据线绝缘交叉，其中，所述显示区中还设有若干转接线单元，每一所述转接线单元包括至少两条并联的转接线，所有所述转接线相互间隔且沿所述第二方向延伸，每一所述扫描线对应至少一个所述转接线单元，每一所述扫描线与对应的所有所述转接线单元中的所有所述转接线电性连接，每一所述转接线用于向电性连接的所述扫描线输入扫描信号。
  2. 如权利要求1所述的阵列基板，其中，每一所述转接线对应一条所述数据线，不同的所述转接线对应不同的所述数据线，每一所述转接线单元中的所有所述转接线对应的所有所述数据线依次相邻。
  3. 如权利要求2所述的阵列基板，其中，每一所述转接线位于对应的所述数据线的同侧。
  4. 如权利要求3所述的阵列基板，其中，所述阵列基板包括第一金属层和设于所述第一金属层上的第二金属层，每一所述扫描线形成于所述第一金属层中，每一所述数据线形成于所述第二金属层中。
  5. 如权利要求4所述的阵列基板，其中，每一所述转接线形成于所述第二金属层中。
  6. 如权利要求4所述的阵列基板，其中，所述阵列基板还包括设于所述第二金属层上的第三金属层，每一所述转接线形成于所述第二金属层和所述第三金属层中，每一所述转接线位于所述第二金属层中的部分与位于所述第三金属层中的部分并联。
  7. 如权利要求1所述的阵列基板，其中，所述阵列基板还具有非显示区，每一所述转接线单元中的所有所述转接线延伸至所述非显示区中的部分短接形成短接线。
  8. 如权利要求7所述的阵列基板，其中，所述非显示区中设有若干第一覆晶薄膜和若干第二覆晶薄膜；每一所述第一覆晶薄膜对应部分所述短接线，并与对应的部分所述短接线电性连接以向电性连接的部分所述短接线输入扫描信号；每一所述第二覆晶薄膜对应部分所述数据线，并与对应的部分所述数据线电性连接以向电性连接的部分所述数据线输入数据信号。
  9. 一种显示面板，其中，所述显示面板包括阵列基板，所述阵列基板具有显示区，所述显示区中设有若干扫描线和若干数据线，所有所述扫描线相互间隔且沿第一方向延伸，所有所述数据线相互间隔且沿第二方向延伸，所述第一方向垂直于所述第二方向，所有所述扫描线与所有所述数据线绝缘交叉，所述显示区中还设有若干转接线单元，每一所述转接线单元包括至少两条并联的转接线，所有所述转接线相互间隔且沿所述第二方向延伸，每一所述扫描线对应至少一个所述转接线单元，每一所述扫描线与对应的所有所述转接线单元中的所有所述转接线电性连接，每一所述转接线用于向电性连接的所述扫描线输入扫描信号。
  10. 如权利要求9所述的显示面板，其中，每一所述转接线对应一条所述数据线，不同的所述转接线对应不同的所述数据线，每一所述转接线单元中的所有所述转接线对应的所有所述数据线依次相邻。
  11. 如权利要求10所述的显示面板，其中，每一所述转接线位于对应的所述数据线的同侧。
  12. 如权利要求11所述的显示面板，其中，所述阵列基板包括第一金属层和设于所述第一金属层上的第二金属层，每一所述扫描线形成于所述第一金属层中，每一所述数据线形成于所述第二金属层中。
  13. 如权利要求12所述的显示面板，其中，每一所述转接线形成于所述第二金属层中。
  14. 如权利要求12所述的显示面板，其中，所述阵列基板还包括设于所述第二金属层上的第三金属层，每一所述转接线形成于所述第二金属层和所述第三金属层中，每一所述转接线位于所述第二金属层中的部分与位于所述第三金属层中的部分并联。
  15. 一种显示装置，其中，所述显示装置包括显示面板，所述显示面板包括阵列基板，所述阵列基板具有显示区，所述显示区中设有若干扫描线和若干数据线，所有所述扫描线相互间隔且沿第一方向延伸，所有所述数据线相互间隔且沿第二方向延伸，所述第一方向垂直于所述第二方向，所有所述扫描线与所有所述数据线绝缘交叉，所述显示区中还设有若干转接线单元，每一所述转接线单元包括至少两条并联的转接线，所有所述转接线相互间隔且沿所述第二方向延伸，每一所述扫描线对应至少一个所述转接线单元，每一所述扫描线与对应的所有所述转接线单元中的所有所述转接线电性连接，每一所述转接线用于向电性连接的所述扫描线输入扫描信号。
  16. 如权利要求15所述的显示装置，其中，每一所述转接线对应一条所述数据线，不同的所述转接线对应不同的所述数据线，每一所述转接线单元中的所有所述转接线对应的所有所述数据线依次相邻。
  17. 如权利要求16所述的显示装置，其中，每一所述转接线位于对应的所述数据线的同侧。
  18. 如权利要求17所述的显示装置，其中，所述阵列基板包括第一金属层和设于所述第一金属层上的第二金属层，每一所述扫描线形成于所述第一金属层中，每一所述数据线形成于所述第二金属层中。
  19. 如权利要求18所述的显示装置，其中，每一所述转接线形成于所述第二金属层中。
  20. 如权利要求18所述的显示装置，其中，所述阵列基板还包括设于所述第二金属层上的第三金属层，每一所述转接线形成于所述第二金属层和所述第三金属层中，每一所述转接线位于所述第二金属层中的部分与位于所述第三金属层中的部分并联。
PCT/CN2020/091347 2020-05-09 2020-05-20 阵列基板、具有该阵列基板的显示面板及显示装置 WO2021227112A1 (zh)

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