WO2020118759A1 - 阵列基板 - Google Patents

阵列基板 Download PDF

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Publication number
WO2020118759A1
WO2020118759A1 PCT/CN2018/122899 CN2018122899W WO2020118759A1 WO 2020118759 A1 WO2020118759 A1 WO 2020118759A1 CN 2018122899 W CN2018122899 W CN 2018122899W WO 2020118759 A1 WO2020118759 A1 WO 2020118759A1
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WO
WIPO (PCT)
Prior art keywords
fan
electrically connected
traces
metal layer
trace
Prior art date
Application number
PCT/CN2018/122899
Other languages
English (en)
French (fr)
Inventor
冯校亮
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/343,778 priority Critical patent/US11264407B2/en
Publication of WO2020118759A1 publication Critical patent/WO2020118759A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13456—Cell terminals located on one side of the display only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/06155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the invention relates to the field of display technology, in particular to an array substrate.
  • LCD liquid crystal displays
  • other flat display devices have been widely used in mobile phones, TVs, and individuals due to their advantages of high image quality, power saving, thin body, and wide application range.
  • Various consumer electronic products such as digital assistants, digital cameras, notebook computers, and desktop computers have become the mainstream in display devices.
  • liquid crystal display devices which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates. There are many vertical and horizontal small wires between the two glass substrates.
  • the liquid crystal molecules can be controlled to change the direction by turning on or off, and the light of the backlight module Refracted to produce a picture.
  • the existing liquid crystal display panel generally consists of a color filter substrate (CF, Color Filter), array tube substrate (TFT, Thin Film Transistor), liquid crystal (LC, Liquid Crystal) and sealant frame (Sealant) sandwiched between the color filter substrate and the array substrate.
  • the structure of the existing array substrate is shown in FIG. 1, which includes a substrate 10, a plurality of scan lines 20, a plurality of data lines 30, a plurality of fan-out traces 40 and a plurality of bonding terminals 50.
  • the substrate 10 A display area 110 and a non-display area 120 surrounding the display area 110 are included.
  • the plurality of scan lines 20 are arranged in the display area 110 at intervals in the vertical direction and extend in the horizontal direction.
  • the plurality of data lines 30 The display area 110 is arranged horizontally at intervals and extends in the vertical direction.
  • the plurality of fan-out traces 40 and the plurality of bonding terminals 50 are located in the non-display area 120, and the plurality of bonding terminals 50 is located on the upper side of the display area 110, scan lines 20 in odd rows are electrically connected to the bonding terminals 50 through fan-out traces 40 on the left side of the display area, and scan lines 20 in even rows are located on the right side of the display area
  • the fan-out trace 40 on the side is connected to the bonding terminal 50, and the data line 30 is electrically connected to the bond terminal 50 through the fan-out trace 40 located on the upper side of the display area 110.
  • This structure uses the fan-out trace electrically connected to the scanning line 20
  • the lines 40 are distributed to the left and right sides of the display area 110. All the fan-out traces 40 of the array substrate are located on the same metal line, which requires a lot of wiring space, which is not conducive to the realization of the narrow border of the display panel.
  • the object of the present invention is to provide an array substrate, which can significantly reduce the size of the frame of the display panel and improve product quality.
  • the present invention provides an array substrate, including: a substrate, multiple fan-out traces, and multiple bonding terminals;
  • the substrate includes a display area and a non-display area surrounding the display area, the plurality of fan-out traces and a plurality of bonding terminals are all provided in the non-display area, and the plurality of bonding terminals are arranged at intervals, the multiple The first ends of the fan-out traces are electrically connected to the plurality of bonding terminals, respectively, and the second ends of the plurality of fan-out traces are all electrically connected to the display area;
  • the multiple fan-out traces include multiple first fan-out traces and multiple second fan-out traces, the multiple first fan-out traces are located in the first metal layer, and the multiple second fan-out traces are located in the first A two-metal layer with an insulating layer between the first metal layer and the second metal layer, and the plurality of first fan-out traces partially overlap the plurality of second fan-out traces.
  • the display area is provided with a plurality of data lines arranged in parallel intervals and a plurality of scan lines arranged in parallel and intersecting the plurality of data lines, each data line corresponds to a corresponding one electrically connected by a fan-out trace Bonding terminals, each scan line is correspondingly electrically connected to a corresponding bonding terminal through a fan-out trace;
  • the multiple scan lines include multiple first scan lines and multiple second scan lines, and the multiple first scan lines and the multiple second scan lines are alternately arranged.
  • a first fan-out trace and a second fan-out trace partially overlapping the first fan-out trace are provided, and one of the adjacent two data lines passes through the first fan
  • the outgoing wiring is electrically connected to its corresponding bonding terminal, and the other data line is electrically connected to its corresponding bonding terminal through the second fan-out wiring.
  • a first fan-out trace and a second fan-out trace partially overlapping with the first fan-out trace are respectively provided for each adjacent two first scan-lines, one of the two adjacent first scan-lines
  • the first fan-out trace is electrically connected to the corresponding bonding terminal
  • the other first scan line is electrically connected to the corresponding bonding terminal through the second fan-out trace.
  • a first fan-out trace and a second fan-out trace partially overlapping with the first fan-out trace are provided corresponding to each adjacent two second scan-lines, one of the two adjacent second scan-lines
  • the first fan-out trace is electrically connected to the corresponding bonding terminal
  • the other second scan line is electrically connected to the corresponding bond terminal through the second fan-out trace.
  • the plurality of scan lines extend in a first direction
  • the plurality of data lines extend in a second direction perpendicular to the first direction
  • the non-display area includes a first wiring area and a first wiring area disposed oppositely in the first direction
  • the plurality of bonding terminals and the fan-out lines connecting the data lines and bonding terminals are all located in the first wiring area, and the fan-out traces connecting the first scan line and the bonding terminals start from the third wiring area Extending into the first wiring area, a fan-out trace connecting the second scan line and the bonding terminal extends from the fourth wiring area into the first wiring area.
  • the plurality of bonding terminals are located in the second metal layer, and the first fan-out trace is electrically connected to the corresponding bonding terminals through a first via that passes through the insulating layer.
  • the plurality of data lines are located in the second metal layer, and the first fan-out trace is electrically connected to the corresponding data line through a second via that passes through the insulating layer.
  • the plurality of scan lines are located in the first metal layer, and the second fan-out trace is electrically connected to the corresponding scan line through a third via that passes through the insulating layer.
  • the plurality of data lines and the plurality of scanning lines cross to define a plurality of pixel regions arranged in an array, each pixel region is provided with a switching thin film transistor and a pixel electrode, and the gate of the switching thin film transistor corresponds to electrical A scan line is connected, the source electrode is electrically connected to a data line, and the drain electrode is electrically connected to the pixel electrode in the pixel area where it is located.
  • the present invention provides an array substrate including: a substrate, a plurality of fan-out traces and a plurality of bonding terminals; the substrate includes a display area and a non-display area surrounding the display area, and the plurality of fans
  • the outgoing wiring and the plurality of bonding terminals are all provided in the non-display area, and the plurality of bonding terminals are arranged at intervals, and the first ends of the plurality of fan-out wirings are electrically connected to the plurality of bonding terminals, respectively,
  • the second ends of the plurality of fan-out traces are all electrically connected to the display area;
  • the plurality of fan-out traces include a plurality of first fan-out traces and a plurality of second fan-out traces, the plurality of first The fan-out traces are located in the first metal layer, the plurality of second fan-out traces are located in the second metal layer, and there is an insulating layer between the first metal layer and the second metal layer, and the plurality
  • FIG. 1 is a schematic diagram of an existing array substrate
  • FIG. 3 is a cross-sectional view at A in FIG. 2;
  • FIG. 4 is a cross-sectional view at B in FIG. 2;
  • FIG. 5 is a cross-sectional view at C in FIG. 2;
  • FIG. 6 is a cross-sectional view at D in FIG. 2;
  • FIG. 7 is a cross-sectional view at E in FIG. 2.
  • the present invention provides an array substrate, including: a substrate 1 , Multiple fan-out traces 2 And multiple bonding terminals 3 ;
  • the substrate 1 Including display area 11 And surround the display area 11 Non-display area 12 ,
  • the multiple fan-out traces 2 And multiple bonding terminals 3 Are located in the non-display area 12 Medium, and multiple bonding terminals 3 Arranged at intervals, the multiple fan-out traces 2
  • the first end of each is electrically connected to the plurality of bonding terminals 3
  • the multiple fan-out traces 2 The second end of the is electrically connected to the display area 11 ;
  • the multiple fan-out traces 2 Includes multiple first fan-out traces twenty one And multiple second fan-out traces twenty two , The multiple first fan-out traces twenty one Located on the first metal layer, the plurality of second fan-out traces twenty two Located in the second metal layer, with an insulating layer between the first metal layer and the second metal layer 4 , The multiple first fan-out traces twenty one With the multiple second fan-out traces twenty two Partial overlap.
  • the display area 11 Multiple data lines arranged in parallel at intervals 5 And parallel to each other and arranged with the multiple data lines 5 Multiple scan lines crossed 6 ,
  • Each data line 5 All correspond to a fan-out trace 2 Electrically connect to a corresponding bonding terminal 3
  • Each scan line 6 All corresponding through a fan-out trace 2 Electrically connect to a corresponding bonding terminal 3 ;
  • the multiple scan lines 6 Includes multiple first scan lines 61 And multiple second scan lines 62 , The multiple first scan lines 61 With multiple second scan lines 62 Alternately arranged.
  • the multiple data lines 5 With multiple scan lines 6 Multiple pixel regions arranged in an array are defined by crossing 9 , Every pixel area 9 There is a switch thin film transistor inside T1 And a pixel electrode P , The switching thin film transistor T1 Of the corresponding gate is electrically connected to a scanning line 6 , The source is electrically connected to a data line 5 , The drain is electrically connected to the pixel area 9 Pixel electrode P , As shown in the figure 2 As mentioned, each switching thin film transistor T1 The gate of the corresponding electrical connection to a scan line above 6 , The source corresponds to a data line on the left 5 .
  • the switching thin film transistor T1 Gate is located in the first metal layer, source and drain are located in the second metal layer, the pixel electrode P A transparent electrode layer located above the second metal layer, a passivation layer is provided between the transparent electrode layer and the second metal layer, the pixel electrode P Through the via hole passing through the passivation layer and the switching thin film transistor T1
  • the drain is electrically connected, that is, the film layer of the array substrate is a first metal layer, an insulating layer, a second metal layer, a passivation layer, and a transparent electrode layer in this order from bottom to top.
  • the plurality of bonding terminals 3 And multiple data lines 5 Are located in the second metal layer, the first fan-out trace twenty one Pass through the insulating layer 4 First via 81 Bonding terminal corresponding to it 3 Electrical connection, the first fan-out wiring twenty one Pass through the insulating layer 4 Second via 82 The corresponding data line 5 Electrical connection.
  • the array substrate of the present invention further includes surrounding the display area 11 Set the first ground 101 And second ground 102 , The second ground 102 Is located in the second metal layer, and its two ends are respectively electrically connected to a binding terminal 3 , The first ground 101 Located on the first metal layer, the first ground 101 Pass through the insulating layer 4 Fourth via 84 With second ground 102 Electrical connection.
  • first scan lines 61 Set up a first fan-out trace twenty one Heyi and the first fan-out trace twenty one Partially overlapping second fan-out trace twenty two ,
  • the two adjacent first scan lines 61 One of them goes through the first fan out twenty one Electrically connect the corresponding bonding terminals 3 ,
  • Another first scan line 61 Route through the second fan twenty two Electrically connect the corresponding bonding terminals 3 ;
  • the plurality of bonding terminals 3 And connect the data cable 5 And bonding terminals 3 Fan-out line 2 Are located in the first wiring area 121 , Connect the first scan line 61 And bonding terminals 3 Fan-out trace 2 From the third wiring area 123 Extend to the first wiring area 121 , Connect the second scan line 62 And bonding terminals 3 Fan-out trace 2 From the fourth wiring area 124 Extend to the first wiring area 121 in.
  • the scan lines located in odd rows 6 Are the first scan line 61 , Scan lines in even rows 6 Both scan lines 62 , The first wiring area 121 ⁇ Second wiring area 122 3. Third wiring area 123 And the fourth wiring area 124 Located in the display area 11
  • the upper, lower, left and right sides of the first scan line 61 Corresponding fan-out trace 2 Are located at the left end
  • Corresponding fan-out trace 2 are located at the right end of the cable 5
  • Corresponding fan-out trace 2 Are located at the upper end.
  • the scan line corresponding to the first row 6 Set a first fan-out trace twenty one
  • the scan line of the third row 6 Set up a second fan-out trace twenty two
  • the first fan-out trace twenty one And the second fan-out trace twenty two Scan lines from the first row 6 And the scan line of the third row 6 Leads to the left end and extends upward, and the second fan-out trace twenty two Scan lines extending beyond the first row 6 After the first fan-out trace twenty one Overlap, extending to the first wiring area 121 Turn back to the right to extend horizontally and keep overlapping until it reaches its corresponding binding terminal 3 After turning below, it turns to extend upward again, and its corresponding binding terminal 3 Electrically connected, the same scan line corresponding to the second row 6 And the scan line of the fourth row 6 A first fan-out trace set separately twenty one , Corresponding to the scan line of the third row 6 Set up a second fan-out trace twenty two .
  • the data line corresponding to the first column 5 And the data line of the second column 5 Set up a second fan-out trace twenty two And a first fan-out trace twenty one ,
  • the second fan-out trace twenty two And the first fan-out trace twenty one Route from a second fan twenty two And a first fan-out trace twenty one
  • the upper end of the terminal is extended horizontally to the right and partially overlaps to reach its corresponding binding terminal 3 Turn downward and extend upwards, respectively, and their corresponding binding terminals 3 Electrical connection.
  • Comparison chart 1 And figure 2 It can be seen that the array substrate of the present invention is located in the display area 11 Fan-out trace on the left 2 Overlapping each other, the required space is halved, located in the display area 11 Fan-out trace on the upper side 2 Also overlap one by two, the required space is also halved, located in the display area 11 Fan-out trace on the right side of 2 Similarly, the space required is also reduced by half, so that the array substrate of the present invention can reduce the upper and left borders of the display panel by half compared to the prior art, thereby achieving narrow border display.
  • the present invention provides an array substrate, including: a substrate, a plurality of fan-out traces, and a plurality of bonding terminals; the substrate includes a display area and a non-display area surrounding the display area, and the plurality of fan-out traces
  • the wires and the plurality of bonding terminals are all provided in the non-display area, and the plurality of bonding terminals are arranged at intervals, and the first ends of the plurality of fan-out traces are electrically connected to the plurality of bonding terminals, respectively.
  • the second ends of the plurality of fan-out traces are all electrically connected to the display area;
  • the plurality of fan-out traces include a plurality of first fan-out traces and a plurality of second fan-out traces, and the plurality of first fans
  • the exit traces are located in the first metal layer
  • the plurality of second fan-out traces are located in the second metal layer, there is an insulating layer between the first metal layer and the second metal layer
  • the plurality of first fan-out traces are The plurality of second fan-out traces partially overlap.

Abstract

一种阵列基板。该阵列基板包括：基板（1）、多条扇出走线（2）及多个邦定端子（3）；基板（1）包括显示区（11）及包围显示区（11）的非显示区（12），多条扇出走线（2）及多个邦定端子（3）均设于非显示区（12）中，且多个邦定端子（3）间隔排列，多条扇出走线（2）的第一端分别电性连接多个邦定端子（3），多条扇出走线（2）的第二端均电性连接显示区（11）；多条扇出走线（2）包括多条第一扇出走线（21）及多条第二扇出走线（22），多条第一扇出走线（21）位于第一金属层，多条第二扇出走线（22）位于第二金属层，第一金属层与第二金属层之间具有绝缘层（4），多条第一扇出走线（21）与多条第二扇出走线（22）部分重叠，通过将扇出走线（2）分散布置到第一金属层和第二金属层中，能够减少扇出走线（2）的布线面积，降低显示面板的边框宽度，实现窄边框显示。

Description

阵列基板 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板。
 背景技术
随着显示技术的发展，液晶显示器（Liquid Crystal Display，LCD）等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
现有市场上的液晶显示装置大部分为背光型液晶显示器，其包括液晶显示面板及背光模组（backlight module）。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
现有的液晶显示面板一般由彩膜基板（CF，Color Filter）、阵列管基板（TFT，Thin Film Transistor)、夹于彩膜基板与阵列基板之间的液晶（LC，Liquid Crystal）及密封胶框（Sealant）组成。其中，现有的阵列基板的结构如图1所示，其包括基板10、多条扫描线20、多条数据线30、多条扇出走线40及多个邦定端子50，所述基板10包括显示区110及包围所述显示区110的非显示区120，所述多条扫描线20在所述显示区110内沿竖直方向间隔排列且沿水平方向延伸，所述多条数据线30在所述显示区110内水平方向间隔排列且沿竖直方向延伸，所述多条扇出走线40及多个邦定端子50位于所述非显示区120内，且所述多个邦定端子50位于所述显示区110的上侧，奇数行的扫描线20通过位于显示区左侧的扇出走线40与所述邦定端子50电性连接，偶数行的扫描线20通过位于显示区右侧的扇出走线40与邦定端子50，数据线30通过位于显示区110上侧的扇出走线40与邦定端子50电性连接，该结构通过将与扫描线20电性连接的扇出走线40分布到显示区110的左右两侧，该阵列基板的所有扇出走线40位于同一金属线，需要占用大量的布线空间，不利于显示面板窄边框的实现。
 技术问题
本发明的目的在于提供一种阵列基板，能够显著减小显示面板的边框大小，提升产品品质。
 技术解决方案
为实现上述目的，本发明提供了一种阵列基板，包括：基板、多条扇出走线及多个邦定端子；
所述基板包括显示区及包围显示区的非显示区，所述多条扇出走线及多个邦定端子均设于所述非显示区中，且多个邦定端子间隔排列，所述多条扇出走线的第一端分别电性连接所述多个邦定端子，所述多条扇出走线的第二端均电性连接所述显示区；
所述多条扇出走线包括多条第一扇出走线及多条第二扇出走线，所述多条第一扇出走线位于第一金属层，所述多条第二扇出走线位于第二金属层，所述第一金属层与第二金属层之间具有绝缘层，所述多条第一扇出走线与所述多条第二扇出走线部分重叠。
所述显示区内设有平行间隔排列的多条数据线及平行间隔排列且与所述多条数据线交叉的多条扫描线，每一条数据线均对应通过一条扇出走线电性连接一个对应的邦定端子，每一条扫描线均对应的通过一条扇出走线电性连接一个对应的邦定端子；
所述多条扫描线包括多条第一扫描线和多条第二扫描线，所述多条第一扫描线与多条第二扫描线交替排列。
对应每相邻的两条数据线分别设置一条第一扇出走线和一与该第一扇出走线部分重叠的第二扇出走线，该相邻的两条数据线中的一条通过第一扇出走线电性连接其对应的邦定端子，另一条数据线通过第二扇出走线电性连接其对应的邦定端子。
对应每相邻的两条第一扫描线分别设置一条第一扇出走线和一与该第一扇出走线部分重叠的第二扇出走线，该相邻的两条第一扫描线中的一条通过第一扇出走线电性连接其对应的邦定端子，另一条第一扫描线通过第二扇出走线电性连接其对应的邦定端子。
对应每相邻的两条第二扫描线分别设置一条第一扇出走线和一与该第一扇出走线部分重叠的第二扇出走线，该相邻的两条第二扫描线中的一条通过第一扇出走线电性连接其对应的邦定端子，另一条第二扫描线通过第二扇出走线电性连接其对应的邦定端子。
所述多条扫描线沿第一方向延伸，所述多条数据线沿与所述第一方向垂直的第二方向延伸，所述非显示区包括沿第一方向相对设置的第一布线区和第二布线区以及沿第二方向相对设置的第三布线区及第四布线区；
所述多个邦定端子及连接所述数据线及邦定端子的扇出线均位于所述第一布线区中，连接所述第一扫描线及邦定端子的扇出走线从第三布线区延伸至第一布线区中，连接所述第二扫描线及邦定端子的扇出走线从第四布线区延伸至第一布线区中。
所述多个邦定端子位于第二金属层，所述第一扇出走线通过一穿越所述绝缘层的第一过孔与其对应的邦定端子电性连接。
所述多条数据线位于第二金属层，所述第一扇出走线通过一穿越所述绝缘层的第二过孔与其对应的数据线电性连接。
所述多条扫描线位于第一金属层，所述第二扇出走线通过一穿越所述绝缘层的第三过孔与其对应的扫描线电性连接。
所述多条数据线与多条扫描线交叉限定出阵列排布的多个像素区，每一个像素区内均设有一开关薄膜晶体管和一像素电极，所述开关薄膜晶体管的栅极对应电性连接一扫描线，源极对应电性连接一数据线，漏极电性连接其所在像素区内的像素电极。
 有益效果
本发明的有益效果：本发明提供一种阵列基板，包括：基板、多条扇出走线及多个邦定端子；所述基板包括显示区及包围显示区的非显示区，所述多条扇出走线及多个邦定端子均设于所述非显示区中，且多个邦定端子间隔排列，所述多条扇出走线的第一端分别电性连接所述多个邦定端子，所述多条扇出走线的第二端均电性连接所述显示区；所述多条扇出走线包括多条第一扇出走线及多条第二扇出走线，所述多条第一扇出走线位于第一金属层，所述多条第二扇出走线位于第二金属层，所述第一金属层与第二金属层之间具有绝缘层，所述多条第一扇出走线与所述多条第二扇出走线部分重叠，通过将扇出走线分散布置到第一金属层和第二金属层中，能够减少扇出走线的布线面积，降低显示面板的边框宽度，实现窄边框显示。
 附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的阵列基板的示意图；
图2为本发明的阵列基板的示意图；
图3为图2中A处的剖面图；
图4为图2中B处的剖面图；
图5为图2中C处的剖面图；
图6为图2中D处的剖面图；
图7为图2中E处的剖面图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图 2 至图 7 ，在本发明提供一种阵列基板，包括：基板 1 、多条扇出走线 2 及多个邦定端子 3 ；
所述基板 1 包括显示区 11 及包围显示区 11 的非显示区 12 ，所述多条扇出走线 2 及多个邦定端子 3 均设于所述非显示区 12 中，且多个邦定端子 3 间隔排列，所述多条扇出走线 2 的第一端分别电性连接所述多个邦定端子 3 ，所述多条扇出走线 2 的第二端均电性连接所述显示区 11 ；
所述多条扇出走线 2 包括多条第一扇出走线 21 及多条第二扇出走线 22 ，所述多条第一扇出走线 21 位于第一金属层，所述多条第二扇出走线 22 位于第二金属层，所述第一金属层与第二金属层之间具有绝缘层 4 ，所述多条第一扇出走线 21 与所述多条第二扇出走线 22 部分重叠。
具体地，如图 2 所示，所述显示区 11 内设有平行间隔排列的多条数据线 5 及平行间隔排列且与所述多条数据线 5 交叉的多条扫描线 6 ，每一条数据线 5 均对应通过一条扇出走线 2 电性连接一个对应的邦定端子 3 ，每一条扫描线 6 均对应的通过一条扇出走线 2 电性连接一个对应的邦定端子 3 ；
其中，所述多条扫描线 6 包括多条第一扫描线 61 和多条第二扫描线 62 ，所述多条第一扫描线 61 与多条第二扫描线 62 交替排列。
进一步地，所述多条数据线 5 与多条扫描线 6 交叉限定出阵列排布的多个像素区 9 ，每一个像素区 9 内均设有一开关薄膜晶体管 T1 和一像素电极 P ，所述开关薄膜晶体管 T1 的栅极对应电性连接一扫描线 6 ，源极对应电性连接一数据线 5 ，漏极电性连接其所在像素区 9 内的像素电极 P ，具体如图 2 所述，每一个开关薄膜晶体管 T1 的栅极对应电性连接其上方的一扫描线 6 ，源极对应电性连接左侧的一数据线 5 。
其中，所述开关薄膜晶体管 T1 的栅极位于第一金属层，源极和漏极位于第二金属层，像素电极 P 位于位于第二金属层上方的透明电极层，所述透明电极层与第二金属层之间设于钝化层，所述像素电极 P 通过穿越所述钝化层的过孔与所述开关薄膜晶体管 T1 的漏极电性连接，也即该阵列基板的膜层从下到上依次为第一金属层、绝缘层、第二金属层、钝化层及透明电极层。
进一步地，如图 3 和图 4 所示，所述多个邦定端子 3 及多条数据线 5 均位于第二金属层，所述第一扇出走线 21 通过一穿越所述绝缘层 4 的第一过孔 81 与其对应的邦定端子 3 电性连接，所述第一扇出走线 21 通过一穿越所述绝缘层 4 的第二过孔 82 与其对应的数据线 5 电性连接。
具体地，如图 5 所示，所述多条扫描线 6 位于第一金属层，所述第二扇出走线 22 通过一穿越所述绝缘层 4 的第三过孔 83 与其对应的扫描线 6 电性连接。
进一步地，如图 6 所示，为了防止静电击穿，本发明的阵列基板还包括围绕所述显示区 11 设置第一地线 101 和第二地线 102 ，所述第二地线 102 的位于第二金属层，其两端分别电性连接一绑定端子 3 ，所述第一地线 101 位于第一金属层，所述第一地线 101 通过一穿越所述绝缘层 4 的第四过孔 84 与第二地线 102 电性连接。
具体地，如图 2 所示并结合图 7 ，在本发明的实施例中，对应每相邻的两条数据线 5 分别设置一条第一扇出走线 21 和一与该第一扇出走线 21 部分重叠的第二扇出走线 22 ，该相邻的两条数据线 5 中的一条通过第一扇出走线 21 电性连接其对应的邦定端子 3 ，另一条数据线 5 通过第二扇出走线 22 电性连接其对应的邦定端子 3 ；
对应每相邻的两条第一扫描线 61 分别设置一条第一扇出走线 21 和一与该第一扇出走线 21 部分重叠的第二扇出走线 22 ，该相邻的两条第一扫描线 61 中的一条通过第一扇出走线 21 电性连接其对应的邦定端子 3 ，另一条第一扫描线 61 通过第二扇出走线 22 电性连接其对应的邦定端子 3 ；
对应每相邻的两条第二扫描线 62 分别设置一条第一扇出走线 21 和一与该第一扇出走线 21 部分重叠的第二扇出走线 22 ，该相邻的两条第二扫描线 62 中的一条通过第一扇出走线 21 电性连接其对应的邦定端子 3 ，另一条第二扫描线 62 通过第二扇出走线 22 电性连接其对应的邦定端子 3 。
进一步地，所述多条扫描线 6 沿第一方向延伸，所述多条数据线 5 沿与所述第一方向垂直的第二方向延伸，所述非显示区 12 包括沿第一方向相对设置的第一布线区 121 和第二布线区 122 以及沿第二方向相对设置的第三布线区 123 及第四布线区 124 ；
所述多个邦定端子 3 及连接所述数据线 5 及邦定端子 3 的扇出线 2 均位于所述第一布线区 121 中，连接所述第一扫描线 61 及邦定端子 3 的扇出走线 2 从第三布线区 123 延伸至第一布线区 121 中，连接所述第二扫描线 62 及邦定端子 3 的扇出走线 2 从第四布线区 124 延伸至第一布线区 121 中。
详细地，如图 2 所示，在本发明的实施例中，位于奇数行的扫描线 6 均为第一扫描线 61 、位于偶数行的扫描线 6 均为第二扫描线 62 ，所述第一布线区 121 、第二布线区 122 、第三布线区 123 及第四布线区 124 分别位于所述显示区 11 的上侧、下侧、左侧及右侧，其中第一扫描线 61 对应的扇出走线 2 均位于其左端，第二扫描线 62 对应的扇出走线 2 均位于其右端，数据线 5 对应的扇出走线 2 均位于其上端。
例如图 2 所示，对应第一行的扫描线 6 设置一条第一扇出走线 21 ，对应第三行的扫描线 6 设置一条第二扇出走线 22 ，该一条第一扇出走线 21 及第二扇出走线 22 分别从第一行的扫描线 6 及第三行的扫描线 6 的左端引出，并向上延伸，且该第二扇出走线 22 延伸至超过第一行的扫描线 6 后与该第一扇出走线 21 重叠，在延伸至第一布线区 121 后转向向右水平延伸，并保持重叠，直至到达其对应的绑定端子 3 的下方后再次转向向上延伸，分别与其对应的绑定端子 3 电性连接，相同的对应第二行的扫描线 6 和第四行的扫描线 6 分别设置的一条第一扇出走线 21 ，对应第三行的扫描线 6 设置一条第二扇出走线 22 。
例如图 2 所示，对应第一列的数据线 5 和第二列的数据线 5 分别设置一条第二扇出走线 22 和一条第一扇出走线 21 ，该一条第二扇出走线 22 和该一条第一扇出走线 21 从一条第二扇出走线 22 和一条第一扇出走线 21 的上端引出后向右水平延伸，并部分重叠，到达其对应的绑定端子 3 的下方后转向向上延伸，分别与其对应的绑定端子 3 电性连接。
对比图 1 和图 2 可知，在本发明的阵列基板中，位于显示区 11 左侧的扇出走线 2 两两重叠，所需要的空间减半，位于显示区 11 上侧的扇出走线 2 也两两重叠，所需要的空间也减半，位于显示区 11 的右侧的扇出走线 2 同样两两重叠，所需要的空间也减半，从而本发明的阵列基板相比于现有技术能够使得显示面板的上边框和左右边框均减少一半，从而实现窄边框显示。
综上所述，本发明提供一种阵列基板，包括：基板、多条扇出走线及多个邦定端子；所述基板包括显示区及包围显示区的非显示区，所述多条扇出走线及多个邦定端子均设于所述非显示区中，且多个邦定端子间隔排列，所述多条扇出走线的第一端分别电性连接所述多个邦定端子，所述多条扇出走线的第二端均电性连接所述显示区；所述多条扇出走线包括多条第一扇出走线及多条第二扇出走线，所述多条第一扇出走线位于第一金属层，所述多条第二扇出走线位于第二金属层，所述第一金属层与第二金属层之间具有绝缘层，所述多条第一扇出走线与所述多条第二扇出走线部分重叠，通过将扇出走线分散布置到第一金属层和第二金属层中，能够减少扇出走线的布线面积，降低显示面板的边框宽度，实现窄边框显示。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种阵列基板，包括：基板、多条扇出走线及多个邦定端子；
    所述基板包括显示区及包围显示区的非显示区，所述多条扇出走线及多个邦定端子均设于所述非显示区中，且多个邦定端子间隔排列，所述多条扇出走线的第一端分别电性连接所述多个邦定端子，所述多条扇出走线的第二端均电性连接所述显示区；
    所述多条扇出走线包括多条第一扇出走线及多条第二扇出走线，所述多条第一扇出走线位于第一金属层，所述多条第二扇出走线位于第二金属层，所述第一金属层与第二金属层之间具有绝缘层，所述多条第一扇出走线与所述多条第二扇出走线部分重叠。
  2. 如权利要求1所述的阵列基板，其中，所述显示区内设有平行间隔排列的多条数据线及平行间隔排列且与所述多条数据线交叉的多条扫描线，每一条数据线均对应通过一条扇出走线电性连接一个对应的邦定端子，每一条扫描线均对应的通过一条扇出走线电性连接一个对应的邦定端子；
    所述多条扫描线包括多条第一扫描线和多条第二扫描线，所述多条第一扫描线与多条第二扫描线交替排列。
  3. 如权利要求2所述的阵列基板，其中，对应每相邻的两条数据线分别设置一条第一扇出走线和一与该第一扇出走线部分重叠的第二扇出走线，该相邻的两条数据线中的一条通过第一扇出走线电性连接其对应的邦定端子，另一条数据线通过第二扇出走线电性连接其对应的邦定端子。
  4. 如权利要求2所述的阵列基板，其中，对应每相邻的两条第一扫描线分别设置一条第一扇出走线和一与该第一扇出走线部分重叠的第二扇出走线，该相邻的两条第一扫描线中的一条通过第一扇出走线电性连接其对应的邦定端子，另一条第一扫描线通过第二扇出走线电性连接其对应的邦定端子。
  5. 如权利要求2所述的阵列基板，其中，对应每相邻的两条第二扫描线分别设置一条第一扇出走线和一与该第一扇出走线部分重叠的第二扇出走线，该相邻的两条第二扫描线中的一条通过第一扇出走线电性连接其对应的邦定端子，另一条第二扫描线通过第二扇出走线电性连接其对应的邦定端子。
  6. 如权利要求2所述的阵列基板，其中，所述多条扫描线沿第一方向延伸，所述多条数据线沿与所述第一方向垂直的第二方向延伸，所述非显示区包括沿第一方向相对设置的第一布线区和第二布线区以及沿第二方向相对设置的第三布线区及第四布线区；
    所述多个邦定端子及连接所述数据线及邦定端子的扇出线均位于所述第一布线区中，连接所述第一扫描线及邦定端子的扇出走线从第三布线区延伸至第一布线区中，连接所述第二扫描线及邦定端子的扇出走线从第四布线区延伸至第一布线区中。
  7. 如权利要求1所述的阵列基板，其中，所述多个邦定端子位于第二金属层，所述第一扇出走线通过一穿越所述绝缘层的第一过孔与其对应的邦定端子电性连接。
  8. 如权利要求2所述的阵列基板，其中，所述多条数据线位于第二金属层，所述第一扇出走线通过一穿越所述绝缘层的第二过孔与其对应的数据线电性连接。
  9. 如权利要求2所述的阵列基板，其中，所述多条扫描线位于第一金属层，所述第二扇出走线通过一穿越所述绝缘层的第三过孔与其对应的扫描线电性连接。
  10. 如权利要求2所述的阵列基板，其中，所述多条数据线与多条扫描线交叉限定出阵列排布的多个像素区，每一个像素区内均设有一开关薄膜晶体管和一像素电极，所述开关薄膜晶体管的栅极对应电性连接一扫描线，源极对应电性连接一数据线，漏极电性连接其所在像素区内的像素电极。
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