WO2021012214A1 - 显示基板及显示面板 - Google Patents

显示基板及显示面板 Download PDF

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Publication number
WO2021012214A1
WO2021012214A1 PCT/CN2019/097489 CN2019097489W WO2021012214A1 WO 2021012214 A1 WO2021012214 A1 WO 2021012214A1 CN 2019097489 W CN2019097489 W CN 2019097489W WO 2021012214 A1 WO2021012214 A1 WO 2021012214A1
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WO
WIPO (PCT)
Prior art keywords
base substrate
transparent conductive
orthographic projection
pixel electrode
display
Prior art date
Application number
PCT/CN2019/097489
Other languages
English (en)
French (fr)
Inventor
赵天鑫
董骥
王世君
包智颖
张瑞辰
刘浩
彭晓青
李姣
肖文俊
许浩
冯博
陈晓晓
王洋
穆文凯
杨冰清
刘屹
纪昊亮
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/954,133 priority Critical patent/US20220128870A1/en
Priority to JP2019565933A priority patent/JP2022549533A/ja
Priority to PCT/CN2019/097489 priority patent/WO2021012214A1/zh
Priority to CN201980001120.4A priority patent/CN112639598A/zh
Publication of WO2021012214A1 publication Critical patent/WO2021012214A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134336—Matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1347—Arrangement of liquid crystal layers or cells in which the final condition of one light beam is achieved by the addition of the effects of two or more layers or cells
    • G02F1/13471—Arrangement of liquid crystal layers or cells in which the final condition of one light beam is achieved by the addition of the effects of two or more layers or cells in which all the liquid crystal cells or layers remain transparent, e.g. FLC, ECB, DAP, HAN, TN, STN, SBE-LC cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/16—Materials and properties conductive

Definitions

  • the present disclosure relates to the field of display technology, in particular to a display substrate and a display panel.
  • the transmittance of the liquid crystal display panel plays an extremely important role in the overall display performance of the liquid crystal display panel.
  • the technical problem to be solved by the present disclosure is to provide a display substrate and a display panel, which can improve the transmittance of the display device.
  • a display substrate including:
  • a signal line layer and a pixel electrode layer with insulation intervals located on one side of the base substrate the signal line layer includes a plurality of signal lines, and the pixel electrode layer includes a plurality of pixel electrodes arranged in an array;
  • the orthographic projection of the pixel electrode on the base substrate overlaps the orthographic projection of at least one signal line on the base substrate.
  • the signal line includes a data line
  • the orthographic projection of the pixel electrode on the base substrate and the orthographic projection of the two data lines adjacent to the pixel electrode on the base substrate all have a first overlapping area.
  • the signal line includes a gate line; the orthographic projection of the pixel electrode on the base substrate and the orthographic projection of the two gate lines adjacent to the pixel electrode on the base substrate all have second Two overlapping areas.
  • the width of the first overlapping area in the first direction is 0.5-1.0 m, and the first direction is perpendicular to the extension direction of the data line and parallel to the base substrate;
  • the width of the second overlapping area in the second direction is 0.5-1.0 ⁇ m, and the second direction is perpendicular to the extending direction of the gate line and parallel to the base substrate.
  • the display substrate further includes:
  • a transparent conductive layer located between the pixel electrode layer and the signal line layer, the transparent conductive layer including a transparent conductive pattern
  • the orthographic projection of the signal line on the base substrate is within the orthographic projection of the transparent conductive pattern on the base substrate.
  • the signal line includes a data line
  • the orthographic projection of the data line on the base substrate is located within the orthographic projection of the transparent conductive pattern on the base substrate
  • the pixel electrode is located on the base substrate.
  • the first direction is perpendicular to the extension direction of the data line and parallel to the base substrate.
  • the signal line includes a gate line
  • the orthographic projection of the gate line on the base substrate is located within the orthographic projection of the transparent conductive pattern on the base substrate
  • the pixel electrode is located on the base substrate.
  • the second direction is perpendicular to the extending direction of the gate line and parallel to the base substrate.
  • the transparent conductive pattern is a whole layer.
  • Embodiments of the present disclosure also provide a display panel, including the display substrate as described above, an opposite substrate arranged in a box with the display substrate, and a liquid crystal layer located between the display substrate and the opposite substrate.
  • the display substrate further includes:
  • a transparent conductive layer located between the pixel electrode layer and the signal line layer, the transparent conductive layer including a transparent conductive pattern
  • a common electrode, and the transparent conductive pattern is electrically connected to the common electrode.
  • FIG. 1 is a schematic plan view of a related art display substrate
  • FIG. 2 is a schematic cross-sectional view of a related art display panel in the CC direction of FIG. 1;
  • FIG. 3 is a schematic plan view of a display substrate according to an embodiment of the disclosure.
  • FIG. 4 is a schematic cross-sectional view of a display panel in the CC direction of FIG. 3 according to an embodiment of the disclosure
  • FIG. 5 is a schematic cross-sectional view of the display panel in the DD direction of FIG. 3 according to the embodiment of the disclosure
  • FIG. 6 is a schematic plan view of a display substrate according to another embodiment of the disclosure.
  • FIG. 7 is a schematic cross-sectional view of a display panel in the CC direction of FIG. 6 according to another embodiment of the present disclosure.
  • FIG. 8 is a schematic cross-sectional view of a display panel in the CC direction of FIG. 6 according to another embodiment of the disclosure.
  • FIG. 9 is a schematic cross-sectional view of a display panel in the DD direction of FIG. 6 in another embodiment of the disclosure.
  • FIG. 10 is a schematic structural diagram of a display device according to an embodiment of the disclosure.
  • two display panels arranged in a stack can be used to form a display device.
  • the display panel on the light emitting side is the main display panel, called Main cell, which is used to display color pictures; the other display panel is The sub-display panel, called Subcell, is used to adjust the backlight.
  • the sub-display panels mostly use vertical electric field type liquid crystal display panels as shown in FIG. 1 and FIG. 2.
  • the gate line 15 and the data line 11 in the display substrate are arranged to define a plurality of pixel regions.
  • the pixel electrode 5 is located in the pixel region.
  • the pixel electrode 5 and the signal line (including the gate line 15 and data) There is a gap between the lines 11).
  • the liquid crystal at the gap will not produce the desired deflection; because the liquid crystal display panel
  • the backlight source is used to provide the backlight. Therefore, uncontrollable light leakage occurs at this gap.
  • a black matrix 10 with a relatively large width needs to be provided on the opposite substrate to block the light leakage.
  • the transmittance of the sub-display panel is low, resulting in a low transmittance of the display device.
  • the embodiments of the present disclosure provide a display substrate and a display panel, which can improve the transmittance of the display device.
  • An embodiment of the present disclosure provides a display substrate including a signal line layer and a pixel electrode layer with insulating intervals on one side of the base substrate, the signal line layer includes a plurality of signal lines, and the pixel electrode layer includes an array A plurality of pixel electrodes arranged; wherein the orthographic projection of the pixel electrode on the base substrate overlaps the orthographic projection of at least one signal line on the base substrate.
  • the orthographic projection of the pixel electrode on the base substrate there is an overlap area between the orthographic projection of the pixel electrode on the base substrate and the orthographic projection of at least one signal line on the base substrate.
  • the pixel electrode and the signal line are on the base substrate.
  • a driving electric field is generated between the pixel electrode and the common electrode, which can deflect the liquid crystal, so that when the display substrate performs display, the liquid crystal corresponding to the overlapping area can be deflected under the action of the driving electric field. Avoid uncontrollable light leakage. In this way, there is no need to design a relatively wide black matrix at the corresponding position of the counter substrate to block the light leakage, which can increase the transmittance of the display panel, thereby increasing the transmittance of the display device.
  • the signal line layer includes a gate line layer and a data line layer
  • the gate line layer includes a plurality of gate lines
  • the data line layer includes a plurality of data lines.
  • the display substrate of this embodiment can be applied to a sub-display panel of a display device including a dual display panel, wherein a black matrix and a color filter unit are provided in the main display panel of the display device, since the main display panel still retains black
  • the matrix can prevent ambient light from irradiating the thin film transistors of the sub-display panel and affecting the performance of the thin film transistors. Therefore, the black matrix of the sub-display panel can be omitted, and it is not necessary to provide a black matrix on the sub-display panel.
  • the orthographic projection of the pixel electrode on the base substrate and the orthographic projection of the two data lines adjacent to the pixel electrode on the base substrate all have a first overlapping area.
  • a driving electric field is generated between the pixel electrode and the common electrode, which can deflect the liquid crystal, so as to avoid the pixel when displaying on the display substrate.
  • Uncontrollable light leakage occurs between the electrode and the adjacent data line.
  • the orthographic projection of the pixel electrode on the base substrate and the orthographic projection of the two gate lines adjacent to the pixel electrode on the base substrate all have a second overlapping area.
  • a driving electric field is generated between the pixel electrode and the common electrode, which can deflect the liquid crystal, so as to avoid the pixel when displaying on the display substrate.
  • Uncontrollable light leakage occurs between the electrode and the adjacent gate line.
  • the orthographic projection of the pixel electrode on the base substrate extends to the orthographic projection area of the signal line on the base substrate, that is, in the four edges of the pixel area.
  • the orthographic projection of the pixel electrode on the base substrate and the orthographic projection of the adjacent gate line on the base substrate overlap, and the orthographic projection of the pixel electrode on the base substrate and the adjacent data line
  • the orthographic projection on the base substrate has an overlapping area. It is worth noting that the orthographic projection of the pixel electrode on the base substrate does not extend to the adjacent pixel area, nor does it contact the adjacent pixel electrode.
  • the extension of the pixel electrode is determined by the width of the overlap area. The width of the overlapping area can be set according to actual needs. It is necessary to ensure that the display substrate does not leak light, and a certain distance between adjacent pixel electrodes is required.
  • the orthographic projection of the pixel electrode and the adjacent data line on the base substrate has a first overlap area, the width d of the first overlap area in the first direction is 0.5-1.0 ⁇ m, and the first overlap area
  • the direction is perpendicular to the extending direction of the data line and parallel to the base substrate; when the above value of d is adopted, it can ensure that no uncontrollable light leakage occurs between the pixel electrode and the adjacent data line, and can ensure that adjacent pixels
  • the electrodes are separated by a certain distance.
  • the width d of the second overlap area in the second direction is 0.5-1.0 ⁇ m, and the second direction extends from the gate line
  • the direction is perpendicular and parallel to the base substrate; when the above value of d is used, it can ensure that there is no uncontrollable light leakage between the pixel electrode and the adjacent gate line, and it can ensure a certain distance between adjacent pixel electrodes .
  • the size of the signal lines in this embodiment will not increase compared to the related art, and the size of the pixel electrode is only enlarged to ensure that the pixel electrode is There is an overlap area between the orthographic projection on the base substrate and the orthographic projection of the signal line on the base substrate. Since the pixel electrodes are mostly made of transparent conductive materials, expanding the size of the pixel electrodes will not affect the transmittance of the display substrate.
  • the transmittance of the display panel can be increased by more than 40%, and the display effect of the display substrate can be greatly improved.
  • the display substrate of this embodiment further includes:
  • a transparent conductive layer located between the pixel electrode layer and the signal line layer, the transparent conductive layer including a transparent conductive pattern
  • the orthographic projection of the signal line on the base substrate is within the orthographic projection of the transparent conductive pattern on the base substrate.
  • a transparent conductive pattern is arranged between the pixel electrode and the signal line, and the orthographic projection of the signal line on the base substrate is in the orthographic projection of the transparent conductive pattern on the base substrate, so that the transparent conductive pattern can shield the signal line
  • the influence of the electrical signal on the electrical signal of the pixel electrode prevents the flickering of the display screen.
  • the orthographic projection of the pixel electrode on the base substrate and the orthographic projection of the signal line on the base substrate overlap, and the orthographic projection of the signal line on the base substrate is the orthographic projection of the transparent conductive pattern on the base substrate Therefore, the orthographic projection of the pixel electrode on the base substrate and the orthographic projection of the transparent conductive pattern on the base substrate also have overlapping areas, so that after the transparent conductive pattern is connected to the common voltage signal, A storage capacitor can also be formed between the transparent conductive pattern and the pixel electrode, which can further increase the storage capacitor of the display substrate, reduce the Cpd/Ctotal value, and prevent crosstalk on the display screen.
  • Ctotal includes Cpd, Cst and Cpg
  • Cpd is the pixel electrode
  • the capacitance between the data line and the data line, Cst is the storage capacitor, and Cpg is the capacitance between the pixel electrode and the gate line. Since the transparent conductive pattern is located between the signal line and the pixel electrode, the values of Cpd and Cpg can be reduced, thereby reducing Cpd /Ctotal value.
  • the transparent conductive pattern uses a transparent material, which will not block light from passing through the display substrate and will not affect the transmittance of the display substrate.
  • the transparent conductive pattern can be connected to the fixed potential output terminal of the display substrate, and the common voltage signal is output through the fixed potential output terminal so that the transparent conductive pattern is connected to the common voltage signal; the transparent conductive pattern can also be electrically connected to the common electrode, so that the display When the substrate is working, the transparent conductive pattern can be connected to a common voltage signal.
  • the transparent conductive pattern can be made as a whole layer.
  • the transparent conductive pattern is a whole layer structure without hollow areas, the whole layer of transparent conductive material can be directly formed as a transparent
  • the conductive pattern does not require patterning of the transparent conductive material, and can also save the number of patterning processes of the display substrate.
  • the transparent conductive pattern is also located between the pixel electrode and the thin film transistor of the display substrate. The transparent conductive pattern can also shield the influence of the electrical signal of the thin film transistor on the pixel electrode and further optimize the display effect .
  • the transparent conductive pattern when the display substrate needs to connect the signal lines and pixel electrodes on both sides of the transparent conductive pattern through via holes, the transparent conductive pattern also needs to reserve via holes in other areas outside the via hole area.
  • the transparent conductive pattern is a whole layer.
  • the transparent conductive pattern may not be a whole layer.
  • a long transparent conductive pattern is arranged between the pixel electrode and the data line, and the orthographic projection of the data line on the base substrate falls into the transparent conductive pattern.
  • the orthographic projection of the pixel electrode on the base substrate and the orthographic projection of the transparent conductive pattern on the base substrate have a third overlapping area, and the size of the storage capacitor increased by the transparent conductive pattern is determined by The width of the third overlapping area in the first direction is determined, and the first direction is perpendicular to the extension direction of the data line and parallel to the base substrate; in order to ensure the storage capacitor of the liquid crystal display panel and avoid screen flicker, the third overlap
  • the width of the region in the first direction is not less than 1.5 ⁇ m.
  • a long transparent conductive pattern is arranged between the pixel electrode and the gate line, and the orthographic projection of the gate line on the base substrate falls into the orthographic projection of the transparent conductive pattern on the base substrate.
  • the size of the storage capacitor increased by the transparent conductive pattern is in the second direction from the fourth overlap area.
  • the second direction is perpendicular to the extending direction of the gate line and parallel to the base substrate; in order to ensure the storage capacitance of the liquid crystal display panel and avoid screen flicker, the width of the fourth overlapping area in the second direction is not less than 1.5 ⁇ m.
  • the electrodes of the thin film transistors of the display substrate are mostly made of opaque metal.
  • the size of the thin film transistor can be reduced in this embodiment; in addition, the data line corresponds to the thin film transistor Position, the line width of the data line can be adjusted to avoid thin film transistors. After adjusting the line width of the data line, it is necessary to ensure the orthographic projection of the data line on the base substrate and the orthographic projection of the pixel electrode on the base substrate There are still overlapping areas.
  • the display substrate of the embodiment of the present disclosure specifically includes: a base substrate 1; a gate line 15 located on the base substrate 1, a common electrode line and a gate of a thin film transistor (Not shown); the gate insulating layer 2 covering the gate line 15, the common electrode line and the gate; the data line 11 on the side of the gate insulating layer 2 away from the gate line 15 and the active layer, source and drain of the thin film transistor Electrode (not shown); the first passivation layer 3 covering the data line 11, the active layer, the source electrode and the drain electrode; the pixel electrode 5 on the side of the first passivation layer 3 away from the data line 11.
  • the size of the pixel electrode 5 of this embodiment is enlarged, and the orthographic projection of the pixel electrode 5 on the base substrate and the orthographic projection of the data line 11 and the gate line 15 on the base substrate have overlapping areas, such as As shown in FIG. 4, there is a first overlap area between the orthographic projection of the pixel electrode 5 on the base substrate 1 and the orthographic projection of the data line 11 on the base substrate 1, and the first overlap area is in the first direction.
  • the width is d1; as shown in FIG. 5, there is a second overlap area between the orthographic projection of the pixel electrode 5 on the base substrate 1 and the orthographic projection of the gate line 15 on the base substrate 1.
  • the second overlap area is The width in the second direction is d2.
  • the values of d1 and d2 can be set according to actual needs. It is necessary to ensure that the display substrate does not leak light, and a certain distance between adjacent pixel electrodes is required.
  • the black matrix can be omitted on the counter substrate.
  • the counter substrate only includes the base substrate 9 and the common electrode 7, which can improve the transmittance of the display panel.
  • the display substrate of the embodiment of the present disclosure specifically includes: a base substrate 1; a gate line 15, a common electrode line, and a gate of a thin film transistor located on the base substrate 1. (Not shown); the gate insulating layer 2 covering the gate line 15, the common electrode line and the gate; the data line 11 on the side of the gate insulating layer 2 away from the gate line 15 and the active layer, source of the thin film transistor, The drain (not shown); the first passivation layer 3 covering the data line 11, the active layer, the source and the drain; the transparent conductive pattern 14 on the side of the first passivation layer 3 away from the data line 11; covering The second passivation layer 13 of the transparent conductive pattern 14; the pixel electrode 5 on the side of the second passivation layer 13 away from the transparent conductive pattern 14.
  • a transparent conductive pattern 14 is added between the pixel electrode 5 and the data line 11 and the gate line 15.
  • the transparent conductive pattern 14 is connected to a common voltage signal, which can shield the gate line 15 and the data line 11.
  • it can avoid the parasitic capacitance between the gate line 15 and the data line 11 and the pixel electrode 5, on the other hand, it can also avoid the influence of the electrical signal on the gate line 15 and the data line 11 on the electrical signal of the pixel electrode 5, and prevent the liquid crystal
  • the disorder causes light leakage; in addition, a storage capacitor can be formed between the pixel electrode 5, thereby increasing the storage capacitor of the display substrate and providing sufficient storage capacitor for the display substrate.
  • the transparent conductive pattern 14 may be a whole layer. In this way, the storage capacitance between the transparent conductive pattern 14 and the pixel electrode 5 can be maximized. In addition, since the entire layer of transparent conductive material can be directly formed as the transparent conductive pattern, there is no need to pattern the transparent conductive material, and the display substrate can be saved. The number of composition processes. In addition, when the transparent conductive pattern 14 is a whole layer, the transparent conductive pattern 14 is also located between the pixel electrode 5 and the thin film transistor of the display substrate. The transparent conductive pattern 14 can also shield the effect of the electrical signal of the thin film transistor on the pixel electrode 5. To further optimize the display effect.
  • the transparent conductive pattern may not be a whole layer.
  • the transparent conductive pattern 14 may only occupy a partial area of the display substrate.
  • the extension direction of a part of the transparent conductive pattern 14 can be the same as the extension direction of the data line 11.
  • the orthographic projection of the data line 11 on the base substrate 1 falls into the part of the transparent conductive pattern 14 on the base substrate 1.
  • the orthographic projection of the partially transparent conductive pattern 14 on the base substrate 1 and the orthographic projection of the pixel electrode 5 on the base substrate 1 have a third overlapping area, and the third overlapping area is in the first direction.
  • the width is S1.
  • the size of the storage capacitor added by the partially transparent conductive pattern 14 is determined by S1.
  • the width S1 of the third overlapping area may not be less than 1.5 ⁇ m.
  • the extension direction of a part of the transparent conductive pattern 14 may be the same as the extension direction of the gate line 15.
  • the orthographic projection of the gate line 15 on the base substrate 1 falls into the part of the transparent conductive pattern 14 on the base substrate 1.
  • the orthographic projection of the partially transparent conductive pattern 14 on the base substrate 1 and the orthographic projection of the pixel electrode 5 on the base substrate 1 have a fourth overlap area, and the fourth overlap area is in the second direction.
  • the width is S2.
  • the size of the storage capacitor added by the partially transparent conductive pattern 14 is determined by S2.
  • the width S2 of the fourth overlapping area may not be less than 1.5 ⁇ m.
  • the transparent conductive pattern 14 may be connected to a common electrode line of a different layer through the connection structure in the via hole, and a common voltage signal is input to the transparent conductive pattern 14 through the common electrode line.
  • a connection structure can be provided for each transparent conductive pattern, so that each transparent conductive pattern is connected to the common electrode line through the connection structure; the transparent conductive pattern 14 is a whole layer
  • one or more connection structures may be provided on the entire display substrate to connect the transparent conductive pattern 14 and the common electrode line.
  • Embodiments of the present disclosure also provide a display panel, including the display substrate as described above, an opposite substrate arranged in a box with the display substrate, and a liquid crystal layer located between the display substrate and the opposite substrate.
  • the orthographic projection of the pixel electrode on the base substrate there is an overlap area between the orthographic projection of the pixel electrode on the base substrate and the orthographic projection of at least one signal line on the base substrate.
  • the pixel electrode and the signal line are on the base substrate.
  • a driving electric field is generated between the pixel electrode and the common electrode, which can deflect the liquid crystal, so that when the display substrate performs display, the liquid crystal corresponding to the overlapping area can be deflected under the action of the driving electric field. Avoid uncontrollable light leakage. In this way, there is no need to design a relatively wide black matrix at the corresponding position of the counter substrate to block the light leakage, which can increase the transmittance of the display panel, thereby increasing the transmittance of the display device.
  • the display panel of this embodiment can be applied to a display device including dual display panels, and can also be applied to a display device including only one display panel, both of which can increase the transmittance of the display device.
  • the display panel of this embodiment When the display panel of this embodiment is applied to a display device including dual display panels, the display panel of this embodiment can be used as a sub-display panel of the display device. Since the main display panel still retains a black matrix, it can prevent light from irradiating the sub-display.
  • the thin film transistors of the display panel affect the performance of the thin film transistors. Therefore, omitting the black matrix of the sub-display panel will not affect the display of the display device.
  • the display substrate further includes:
  • a transparent conductive layer located between the pixel electrode layer and the signal line layer, the transparent conductive layer including a transparent conductive pattern
  • a common electrode, and the transparent conductive pattern is electrically connected to the common electrode.
  • the material of the common electrode and the transparent conductive pattern can be the same.
  • both the common electrode and the transparent conductive pattern are made of ITO, so that the same film forming equipment can be used to form the common electrode material layer and the transparent conductive pattern material layer.
  • the transparent conductive pattern and the common electrode can input electrical signals of the same voltage, specifically, the voltage of the electrical signals can be 0V.
  • the transparent conductive pattern can be connected to the fixed potential output terminal of the display substrate, and the common voltage signal is output through the fixed potential output terminal so that the transparent conductive pattern is connected to the common voltage signal; the transparent conductive pattern can also be electrically connected to the common electrode, so that the display When the substrate is working, the transparent conductive pattern can be connected to a common voltage signal.
  • the embodiment of the present disclosure also provides a display device.
  • the display device includes a first display panel 16 and a second display panel 17 that are stacked, and the first display panel 16 is located on the side of the second display panel 17.
  • the second display panel 17 adopts the display panel described above.
  • the first display panel can be used as a main display panel, and the second display panel can be used as a sub display panel.
  • a black matrix and a color filter unit are arranged in the first display panel. Since the first display panel still retains the black matrix, it can be Avoid light shining on the thin film transistors of the second display panel and affect the performance of the thin film transistors. Therefore, omission of the black matrix of the second display panel will not affect the display of the display device.
  • the display device includes but is not limited to: radio frequency unit, network module, audio output unit, input unit, sensor, display unit, user input unit, interface unit, memory, processor, power supply and other components.
  • the structure of the above display device does not constitute a limitation on the display device, and the display device may include more or less of the above components, or combine some components, or arrange different components.
  • the display device includes, but is not limited to, a display, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, and the like.
  • the display device may be any product or component with a display function, such as an LCD TV, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.
  • a display function such as an LCD TV, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, etc.
  • the display device also includes a flexible circuit board, a printed circuit board and a backplane.

Abstract

本公开提供了一种显示基板及显示面板，属于显示技术领域。其中，显示基板，包括：衬底基板；位于所述衬底基板一侧的绝缘间隔的信号线层和像素电极层，所述信号线层包括多条信号线，所述像素电极层包括阵列排布的多个像素电极；其中，所述像素电极在所述衬底基板上的正投影与至少一条所述信号线在所述衬底基板上的正投影相交叠。本公开的技术方案能够提高显示装置的透过率。

Description

显示基板及显示面板 技术领域
本公开涉及显示技术领域，特别是指一种显示基板及显示面板。
背景技术
液晶显示面板的透过率对液晶显示面板的整体显示性能起着极为重要的作用，透过率越高，液晶显示面板的可显示亮度越高，背光源的亮度就可以做的更低，从而降低产品的制作成本，因此，业内一直都在努力提升液晶显示面板的透过率。
发明内容
本公开要解决的技术问题是提供一种显示基板及显示面板，能够提高显示装置的透过率。
为解决上述技术问题，本公开的实施例提供技术方案如下：
一方面，提供一种显示基板，包括：
衬底基板；
位于所述衬底基板一侧的绝缘间隔的信号线层和像素电极层，所述信号线层包括多条信号线，所述像素电极层包括阵列排布的多个像素电极；其中，
所述像素电极在所述衬底基板上的正投影与至少一条所述信号线在所述衬底基板上的正投影相交叠。
可选地，所述信号线包括数据线；
所述像素电极在所述衬底基板上的正投影与该像素电极相邻的两条数据线在所述衬底基板上的正投影均存在第一交叠区域。
可选地，所述信号线包括栅线；所述像素电极在所述衬底基板上的正投影与该像素电极相邻的两条栅线在所述衬底基板上的正投影均存在第二交叠区域。
所述第一交叠区域在第一方向上的宽度为0.5-1.0μm，所述第一方向与 所述数据线的延伸方向垂直且与所述衬底基板平行；
所述第二交叠区域在第二方向上的宽度为0.5-1.0μm，所述第二方向与所述栅线的延伸方向垂直且与所述衬底基板平行。
可选地，所述显示基板还包括：
位于所述像素电极层和所述信号线层之间的透明导电层，所述透明导电层包括透明导电图形；
所述信号线在所述衬底基板上的正投影位于所述透明导电图形在所述衬底基板上的正投影内。
可选地，所述信号线包括数据线，所述数据线在所述衬底基板上的正投影位于所述透明导电图形在所述衬底基板上的正投影内，所述像素电极在所述衬底基板上的正投影与所述透明导电图形在所述衬底基板上的正投影存在第三交叠区域，所述第三交叠区域在第一方向上的宽度不小于1.5μm，所述第一方向与所述数据线的延伸方向垂直且与所述衬底基板平行。
可选地，所述信号线包括栅线，所述栅线在所述衬底基板上的正投影位于所述透明导电图形在所述衬底基板上的正投影内，所述像素电极在所述衬底基板上的正投影与所述透明导电图形在所述衬底基板上的正投影存在第四交叠区域，所述第四交叠区域在第二方向上的宽度不小于1.5μm，所述第二方向与所述栅线的延伸方向垂直且与所述衬底基板平行。
可选地，所述透明导电图形为一整层。
本公开实施例还提供了一种显示面板，包括如上所述的显示基板、与所述显示基板对盒设置的对向基板以及位于所述显示基板和所述对向基板之间的液晶层。
可选地，所述显示基板还包括：
位于所述像素电极层和所述信号线层之间的透明导电层，所述透明导电层包括透明导电图形；
公共电极，所述透明导电图形与所述公共电极电连接。
附图说明
图1为相关技术显示基板的平面示意图；
图2为相关技术显示面板在图1的CC方向上的截面示意图；
图3为本公开实施例显示基板的平面示意图；
图4为本公开实施例显示面板在图3的CC方向上的截面示意图；
图5为本公开实施例显示面板在图3的DD方向上的截面示意图；
图6为本公开另一实施例显示基板的平面示意图；
图7为本公开另一实施例显示面板在图6的CC方向上的截面示意图；
图8为本公开另一实施例显示面板在图6的CC方向上的截面示意图；
图9为本公开又一实施例显示面板在图6的DD方向上的截面示意图；
图10为本公开实施例显示装置的结构示意图。
附图标记
1衬底基板
2栅绝缘层
3第一钝化层
5像素电极
6液晶层
7公共电极
9衬底基板
10黑矩阵
11数据线
13第二钝化层
14透明导电图形
15栅线
16第一显示面板
17第二显示面板
具体实施方式
为使本公开的实施例要解决的技术问题、技术方案和优点更加清楚，下 面将结合附图及具体实施例进行详细描述。
相关技术中，为了提高画面的对比度，可以采用层叠设置的两个显示面板组成显示装置，位于出光侧的显示面板为主显示面板，称为Main cell，用以显示彩色画面；另一显示面板为子显示面板，称为Sub cell，用以调节背光。其中，子显示面板大多采用如图1和图2所示的垂直电场型液晶显示面板。
如图1和图2所示，显示基板中栅线15和数据线11交叉排布限定出多个像素区域，像素电极5位于像素区域中，像素电极5与信号线(包括栅线15和数据线11)之间存在间隙，在该间隙处不存在像素电极5与公共电极7之间的驱动电场，在液晶显示面板工作时，该间隙处的液晶不会产生期望的偏转；由于液晶显示面板是利用背光源来提供背光，因此，在该间隙处会出现不可控的漏光现象，为了遮挡显示基板的漏光，需要在对向基板上设置宽度比较大的黑矩阵10来遮挡漏光，这就导致子显示面板的透过率较低，从而导致显示装置的透过率较低。
为了解决上述问题，本公开的实施例提供一种显示基板及显示面板，能够提高显示装置的透过率。
本公开的实施例提供一种显示基板，包括位于所述衬底基板一侧的绝缘间隔的信号线层和像素电极层，所述信号线层包括多条信号线，所述像素电极层包括阵列排布的多个像素电极；其中，所述像素电极在所述衬底基板上的正投影与至少一条所述信号线在所述衬底基板上的正投影相交叠。
本实施例中，像素电极在衬底基板上的正投影与至少一条信号线在衬底基板上的正投影存在交叠区域，在存在交叠区域的位置，像素电极与信号线在衬底基板上的正投影之间不存在间隙，像素电极与公共电极之间产生驱动电场，能够使得液晶偏转，这样在显示基板进行显示时，交叠区域对应的液晶能在驱动电场的作用下发生偏转，避免出现不可控的漏光现象。这样在对向基板的相应位置无需设计比较宽的黑矩阵来遮挡漏光，能够提高显示面板的透过率，进而增加显示装置的透过率。
其中，信号线层包括栅线层和数据线层，栅线层包括多条栅线，数据线层包括多条数据线。
本实施例的显示基板可以应用于包括双显示面板的显示装置的子显示面板中，其中，在显示装置的主显示面板中设置有黑矩阵和彩色滤光单元，由于主显示面板仍保留有黑矩阵，能够避免环境光线照射到子显示面板的薄膜晶体管上，影响薄膜晶体管的性能，因此，可以省去子显示面板的黑矩阵，无需在子显示面板上设置黑矩阵。
可选地，所述像素电极在所述衬底基板上的正投影与该像素电极相邻的两条数据线在所述衬底基板上的正投影均存在第一交叠区域。这样，像素电极与相邻的数据线在衬底基板上的正投影之间不存在间隙，像素电极与公共电极之间产生驱动电场，能够使得液晶偏转，这样在显示基板进行显示时，避免像素电极和相邻的数据线之间出现不可控的漏光现象。
可选地，所述像素电极在所述衬底基板上的正投影与该像素电极相邻的两条栅线在所述衬底基板上的正投影均存在第二交叠区域。这样，像素电极与相邻的栅线在衬底基板上的正投影之间不存在间隙，像素电极与公共电极之间产生驱动电场，能够使得液晶偏转，这样在显示基板进行显示时，避免像素电极和相邻的栅线之间出现不可控的漏光现象。
具体地，为了最大化避免漏光现象，在像素区域的四个边缘，像素电极在衬底基板上的正投影均延伸至信号线在衬底基板上的正投影区域内，即在像素区域的四个边缘处，像素电极在衬底基板上的正投影与相邻的栅线在衬底基板上的正投影存在交叠区域且像素电极在衬底基板上的正投影与相邻的数据线在衬底基板上的正投影存在交叠区域。值得注意的是，像素电极在衬底基板上的正投影不会延伸至相邻的像素区域，也不会与相邻的像素电极相接触，像素电极的延伸尺寸由交叠区域的宽度决定，交叠区域的宽度取值可以根据实际需要进行设定，需要保证显示基板不发生漏光，且相邻像素电极之间需要间隔一定距离。
一具体实施例中，像素电极与相邻的数据线在衬底基板上的正投影存在第一交叠区域，第一交叠区域在第一方向上的宽度d为0.5-1.0μm，第一方向与数据线的延伸方向垂直且与衬底基板平行；在d采用上述取值时，既可以保证像素电极与相邻的数据线之间不发生不可控的漏光现象，且能够保证 相邻像素电极之间间隔一定距离。
像素电极与相邻的栅线在衬底基板上的正投影存在第二交叠区域，第二交叠区域在第二方向上的宽度d为0.5-1.0μm，第二方向与栅线的延伸方向垂直且与衬底基板平行；在d采用上述取值时，既可以保证像素电极与相邻的栅线之间不发生不可控的漏光现象，且能够保证相邻像素电极之间间隔一定距离。
由于信号线大多采用不透光金属制作，为了保证显示基板的透过率，相比相关技术，本实施例中信号线的尺寸不会增大，仅通过扩大像素电极的尺寸来保证像素电极在衬底基板上的正投影与信号线在衬底基板上的正投影存在交叠区域，由于像素电极多采用透明导电材料制作，因此扩大像素电极的尺寸不会影响显示基板的透过率。
通过本公开的技术方案，可以将显示面板的透过率提高40％以上，能够大大改善显示基板的显示效果。
另外，由于像素电极在衬底基板上的正投影与信号线在衬底基板上的正投影存在交叠区域，这样在显示基板工作时，信号线与像素电极之间存在寄生电容，信号线上加载的电信号可能会影响像素电极上的电信号，导致像素电极上的电信号出现波动，显示会出现闪烁现象，为了保证显示效果，本实施例的显示基板还包括：
位于所述像素电极层和所述信号线层之间的透明导电层，所述透明导电层包括透明导电图形；
所述信号线在所述衬底基板上的正投影位于所述透明导电图形在所述衬底基板上的正投影内。
本实施例在像素电极和信号线之间设置透明导电图形，且信号线在衬底基板上的正投影位于透明导电图形在衬底基板上的正投影内，这样透明导电图形能够屏蔽信号线上电信号对像素电极上电信号的影响，防止出现显示画面闪烁现象。
在液晶显示面板进行显示时，栅线和数据线上都会加载电信号，栅线和数据线上加载的电信号都会对像素电极产生影响，一方面与像素电极之间产 生寄生电容，导致液晶紊乱，另一方面还会影响像素电极上的电信号。本实施例中，不仅在数据线和像素电极之间设置透明导电图形，还在栅线和像素电极之间设置透明导电图形，这样透明导电图形不仅能够避免数据线上电信号对像素电极的影响，还能避免栅线上电信号对像素电极的影响。
由于像素电极在衬底基板上的正投影与信号线在衬底基板上的正投影存在交叠区域，且信号线在衬底基板上的正投影位于透明导电图形在衬底基板上的正投影内，因此，像素电极在所述衬底基板上的正投影与所述透明导电图形在所述衬底基板上的正投影也存在交叠区域，这样在透明导电图形接入公共电压信号后，还可以在透明导电图形和像素电极之间形成存储电容，能够进一步增加显示基板的存储电容，减少Cpd/Ctotal值，防止显示画面出现串扰，其中，Ctotal包括Cpd、Cst和Cpg，Cpd为像素电极与数据线之间的电容，Cst为存储电容，Cpg为像素电极与栅线之间的电容，由于透明导电图形位于信号线与像素电极之间，因此能够降低Cpd和Cpg的值，进而降低Cpd/Ctotal值。透明导电图形采用透明材料，不会阻挡光线透过显示基板，不会对显示基板的透过率造成影响。
其中，透明导电图形可以与显示基板的固定电位输出端连接，通过固定电位输出端输出公共电压信号使得透明导电图形接入公共电压信号；还可以将透明导电图形与公共电极电连接，这样在显示基板工作时，透明导电图形能够接入公共电压信号。
为了最大化透明导电图形与像素电极之间的存储电容，可以将透明导电图形制作为一整层，在透明导电图形为整层结构无镂空区域时，可以直接形成整层的透明导电材料作为透明导电图形，无需对透明导电材料进行图案化处理，还可以节省显示基板的构图工艺的次数。另外，在透明导电图形为一整层时，则透明导电图形还位于像素电极和显示基板的薄膜晶体管之间，透明导电图形还能够屏蔽薄膜晶体管上电信号对像素电极的影响，进一步优化显示效果。值得注意的是，在显示基板需要通过过孔连接分别位于透明导电图形两侧的信号线和像素电极时，在透明导电图形上还需要预留有过孔，在过孔区域之外的其他区域透明导电图形为整层的。
透明导电图形也可以不是一整层的，一具体实施例中，像素电极与数据线之间设置有长条状的透明导电图形，数据线在衬底基板上的正投影落入透明导电图形在衬底基板上的正投影中，像素电极在衬底基板上的正投影与该透明导电图形在衬底基板上的正投影存在第三交叠区域，通过透明导电图形增加的存储电容的大小由第三交叠区域在第一方向上的宽度决定，第一方向与数据线的延伸方向垂直且平行于衬底基板；为了保证液晶显示面板的存储电容，避免出现画面闪烁现象，第三交叠区域在第一方向上的宽度不小于1.5μm。
另一具体实施例中，像素电极与栅线之间设置有长条状的透明导电图形，栅线在衬底基板上的正投影落入透明导电图形在衬底基板上的正投影中，像素电极在衬底基板上的正投影与该透明导电图形在衬底基板上的正投影存在第四交叠区域，通过透明导电图形增加的存储电容的大小由第四交叠区域在第二方向上的宽度决定，第二方向与栅线的延伸方向垂直且平行于衬底基板；为了保证液晶显示面板的存储电容，避免出现画面闪烁现象，第四交叠区域在第二方向上的宽度不小于1.5μm。
显示基板的薄膜晶体管的电极大多采用不透光的金属制作，为了保证显示基板的透过率，相比相关技术，本实施例可以减小薄膜晶体管的尺寸；另外，在数据线对应薄膜晶体管的位置，可以对数据线的线宽进行调整以避让薄膜晶体管，在对数据线的线宽进行调整后，需要保证数据线在衬底基板上的正投影与像素电极在衬底基板上的正投影仍存在交叠区域。
一具体实施例中，如图3-图5所示，本公开实施例的显示基板具体包括：衬底基板1；位于衬底基板1上的栅线15、公共电极线和薄膜晶体管的栅极(未图示)；覆盖栅线15、公共电极线和栅极的栅绝缘层2；位于栅绝缘层2远离栅线15一侧的数据线11和薄膜晶体管的有源层、源极、漏极(未图示)；覆盖数据线11、有源层、源极和漏极的第一钝化层3；位于第一钝化层3远离数据线11一侧的像素电极5。相比相关技术，本实施例的像素电极5的尺寸扩大，像素电极5在衬底基板上的正投影与数据线11和栅线15在衬底基板上的正投影均存在交叠区域，如图4所示，像素电极5在衬底基板1上的 正投影与数据线11在衬底基板1上的正投影之间存在第一交叠区域，第一交叠区域在第一方向上的宽度为d1；如图5所示，像素电极5在衬底基板1上的正投影与栅线15在衬底基板1上的正投影之间存在第二交叠区域，第二交叠区域在第二方向上的宽度为d2，d1和d2的取值可以根据实际需要进行设定，需要保证显示基板不发生漏光，且相邻像素电极之间需要间隔一定距离。
本实施例中，由于像素电极5在衬底基板上的正投影与数据线11和栅线15在衬底基板上的正投影均存在交叠区域，能够避免显示基板出现不可控的漏光现象，因此，在对向基板上可以省去黑矩阵，如图4和图5所示，对向基板仅包括衬底基板9和公共电极7，能够提高显示面板的透过率。
另一具体实施例中，如图6-图9所示，本公开实施例的显示基板具体包括：衬底基板1；位于衬底基板1上的栅线15、公共电极线和薄膜晶体管的栅极(未图示)；覆盖栅线15、公共电极线和栅极的栅绝缘层2；位于栅绝缘层2远离栅线15一侧的数据线11和薄膜晶体管的有源层、源极、漏极(未图示)；覆盖数据线11、有源层、源极和漏极的第一钝化层3；位于第一钝化层3远离数据线11一侧的透明导电图形14；覆盖透明导电图形14的第二钝化层13；位于第二钝化层13远离透明导电图形14一侧的像素电极5。
本实施例中，在像素电极5与数据线11以及栅线15之间增加透明导电图形14，在显示面板工作时，透明导电图形14接入公共电压信号，能够屏蔽栅线15和数据线11，一方面避免栅线15和数据线11与像素电极5之间产生寄生电容，另一方面还能够避免栅线15和数据线11上的电信号对像素电极5上电信号的影响，防止液晶紊乱造成漏光；另外，还能够与像素电极5之间形成存储电容，从而增加显示基板的存储电容，为显示基板提供足够的存储电容。
如图7所示，透明导电图形14可以为一整层。这样可以最大化透明导电图形14与像素电极5之间的存储电容，另外，由于可以直接形成整层的透明导电材料作为透明导电图形，无需对透明导电材料进行图案化处理，还可以节省显示基板的构图工艺的次数。另外，在透明导电图形14为一整层时，则透明导电图形14还位于像素电极5和显示基板的薄膜晶体管之间，透明导电 图形14还能够屏蔽薄膜晶体管上电信号对像素电极5的影响，进一步优化显示效果。
透明导电图形也可以不是一整层的，在透明导电图形不是一整层时，如图8所示，透明导电图形14可以仅占显示基板的部分区域。
如图8所示，一部分透明导电图形14的延伸方向可以与数据线11的延伸方向相同，数据线11在衬底基板1上正投影落入该部分透明导电图形14在衬底基板1上的正投影内，该部分透明导电图形14在衬底基板1上的正投影与像素电极5在衬底基板1上的正投影存在第三交叠区域，第三交叠区域在第一方向上的宽度为S1，此时通过该部分透明导电图形14增加的存储电容的大小由S1决定，为了保证液晶显示面板的存储电容，避免出现画面闪烁的现象，第三交叠区域的宽度S1可以不小于1.5μm。
如图9所示，一部分透明导电图形14的延伸方向可以与栅线15的延伸方向相同，栅线15在衬底基板1上正投影落入该部分透明导电图形14在衬底基板1上的正投影内，该部分透明导电图形14在衬底基板1上的正投影与像素电极5在衬底基板1上的正投影存在第四交叠区域，第四交叠区域在第二方向上的宽度为S2，此时通过该部分透明导电图形14增加的存储电容的大小由S2决定，为了保证液晶显示面板的存储电容，避免出现画面闪烁的现象，第四交叠区域的宽度S2可以不小于1.5μm。
具体地，透明导电图形14可以通过过孔中的连接结构与异层的公共电极线连接，通过公共电极线向透明导电图形14输入公共电压信号。在透明导电图形仅占显示基板的部分区域时，可以对应每一透明导电图形设置一连接结构，使得每一透明导电图形分别通过连接结构与公共电极线连接；在透明导电图形14为一整层时，可以在整个显示基板上设置一个或多个连接结构来连接透明导电图形14和公共电极线。
本公开实施例还提供了一种显示面板，包括如上所述的显示基板、与所述显示基板对盒设置的对向基板以及位于所述显示基板和所述对向基板之间的液晶层。
本实施例中，像素电极在衬底基板上的正投影与至少一条信号线在衬底 基板上的正投影存在交叠区域，在存在交叠区域的位置，像素电极与信号线在衬底基板上的正投影之间不存在间隙，像素电极与公共电极之间产生驱动电场，能够使得液晶偏转，这样在显示基板进行显示时，交叠区域对应的液晶能在驱动电场的作用下发生偏转，避免出现不可控的漏光现象。这样在对向基板的相应位置无需设计比较宽的黑矩阵来遮挡漏光，能够提高显示面板的透过率，进而增加显示装置的透过率。
本实施例的显示面板可以应用在包括双显示面板的显示装置中，也可以应用在仅包括一个显示面板的显示装置中，均可以提高显示装置的透过率。
在本实施例的显示面板应用在包括双显示面板的显示装置中时，本实施例的显示面板可以作为显示装置的子显示面板，由于主显示面板仍保留有黑矩阵，能够避免光线照射到子显示面板的薄膜晶体管上，影响薄膜晶体管的性能，因此，省去子显示面板的黑矩阵不会对显示装置的显示造成影响。
可选地，所述显示基板还包括：
位于所述像素电极层和所述信号线层之间的透明导电层，所述透明导电层包括透明导电图形；
公共电极，所述透明导电图形与所述公共电极电连接。
公共电极与透明导电图形的材料可以相同，比如公共电极与透明导电图形均采用ITO，这样可以利用相同的成膜设备形成公共电极材料层和透明导电图形材料层。
本公开的技术方案中，在显示面板进行显示时，透明导电图形和公共电极可以输入相同电压的电信号，具体地，电信号的电压可以为0V。
其中，透明导电图形可以与显示基板的固定电位输出端连接，通过固定电位输出端输出公共电压信号使得透明导电图形接入公共电压信号；还可以将透明导电图形与公共电极电连接，这样在显示基板工作时，透明导电图形能够接入公共电压信号。
本公开实施例还提供了一种显示装置，如图10所示，包括层叠设置的第一显示面板16和第二显示面板17，所述第一显示面板16位于所述第二显示面板17的出光侧，所述第二显示面板17采用如上所述的显示面板。
本实施例中，由于第二显示面板的透过率得到提升，因此能够在第一显示面板不变的情况下，保证画质不受影响，并且提高显示装置的透过率。
其中，第一显示面板可以作为主显示面板，第二显示面板可以作为子显示面板，在第一显示面板中设置有黑矩阵和彩色滤光单元，由于第一显示面板仍保留有黑矩阵，能够避免光线照射到第二显示面板的薄膜晶体管上，影响薄膜晶体管的性能，因此，省去第二显示面板的黑矩阵不会对显示装置的显示造成影响。
该显示装置包括但不限于：射频单元、网络模块、音频输出单元、输入单元、传感器、显示单元、用户输入单元、接口单元、存储器、处理器、以及电源等部件。本领域技术人员可以理解，上述显示装置的结构并不构成对显示装置的限定，显示装置可以包括上述更多或更少的部件，或者组合某些部件，或者不同的部件布置。在本公开实施例中，显示装置包括但不限于显示器、手机、平板电脑、电视机、可穿戴电子设备、导航显示设备等。
所述显示装置可以为：液晶电视、液晶显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置 改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (10)

  1. 一种显示基板，包括：
    衬底基板；
    位于所述衬底基板一侧的绝缘间隔的信号线层和像素电极层，所述信号线层包括多条信号线，所述像素电极层包括阵列排布的多个像素电极；其中，
    所述像素电极在所述衬底基板上的正投影与至少一条所述信号线在所述衬底基板上的正投影相交叠。
  2. 根据权利要求1所述的显示基板，其中，所述信号线包括数据线；
    所述像素电极在所述衬底基板上的正投影与该像素电极相邻的两条数据线在所述衬底基板上的正投影均存在第一交叠区域。
  3. 根据权利要求1或2所述的显示基板，其中，所述信号线包括栅线；所述像素电极在所述衬底基板上的正投影与该像素电极相邻的两条栅线在所述衬底基板上的正投影均存在第二交叠区域。
  4. 根据权利要求3所述的显示基板，其中，
    所述第一交叠区域在第一方向上的宽度为0.5-1.0μm，所述第一方向与所述数据线的延伸方向垂直且与所述衬底基板平行；
    所述第二交叠区域在第二方向上的宽度为0.5-1.0μm，所述第二方向与所述栅线的延伸方向垂直且与所述衬底基板平行。
  5. 根据权利要求1-4任一项所述的显示基板，其中，所述显示基板还包括：
    位于所述像素电极层和所述信号线层之间的透明导电层，所述透明导电层包括透明导电图形；
    所述信号线在所述衬底基板上的正投影位于所述透明导电图形在所述衬底基板上的正投影内。
  6. 根据权利要求5所述的显示基板，其中，所述信号线包括数据线，所述数据线在所述衬底基板上的正投影位于所述透明导电图形在所述衬底基板上的正投影内，所述像素电极在所述衬底基板上的正投影与所述透明导电图 形在所述衬底基板上的正投影存在第三交叠区域，所述第三交叠区域在第一方向上的宽度不小于1.5μm，所述第一方向与所述数据线的延伸方向垂直且与所述衬底基板平行。
  7. 根据权利要求5所述的显示基板，其中，所述信号线包括栅线，所述栅线在所述衬底基板上的正投影位于所述透明导电图形在所述衬底基板上的正投影内，所述像素电极在所述衬底基板上的正投影与所述透明导电图形在所述衬底基板上的正投影存在第四交叠区域，所述第四交叠区域在第二方向上的宽度不小于1.5μm，所述第二方向与所述栅线的延伸方向垂直且与所述衬底基板平行。
  8. 根据权利要求6或7所述的显示基板，其中，所述透明导电图形为一整层。
  9. 一种显示面板，其中，包括如权利要求1所述的显示基板、与所述显示基板对盒设置的对向基板以及位于所述显示基板和所述对向基板之间的液晶层。
  10. 根据权利要求9所述的显示面板，其中，所述显示基板还包括：
    位于所述像素电极层和所述信号线层之间的透明导电层，所述透明导电层包括透明导电图形；
    公共电极，所述透明导电图形与所述公共电极电连接。
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