WO2023226687A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2023226687A1
WO2023226687A1 PCT/CN2023/091446 CN2023091446W WO2023226687A1 WO 2023226687 A1 WO2023226687 A1 WO 2023226687A1 CN 2023091446 W CN2023091446 W CN 2023091446W WO 2023226687 A1 WO2023226687 A1 WO 2023226687A1
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Prior art keywords
electrode
pixel
substrate
array substrate
sub
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PCT/CN2023/091446
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English (en)
French (fr)
Inventor
万彬
王小元
陈俊明
杨国栋
蒲巡
朱嫄媛
范志成
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Publication of WO2023226687A1 publication Critical patent/WO2023226687A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the present application relates to the field of display technology, and in particular to an array substrate and a display device.
  • Display devices have become indispensable electronic products in people's lives.
  • Display devices such as smart bracelets, mobile phones, and tablet computers have greatly increased the convenience of people's lives.
  • the display device may include: an array substrate and a color filter substrate arranged opposite each other, and a liquid crystal layer located in the array substrate and the color filter substrate.
  • the array substrate may include: a substrate, and a common signal line and a common electrode located on the substrate.
  • the common signal line and the common electrode are arranged in different layers, and the common signal line and the common electrode are electrically connected through via holes.
  • the display effect of current display devices is poor.
  • Embodiments of the present application provide an array substrate and a display device, which can improve the display effect of the display device.
  • the technical solution is as follows:
  • an array substrate is provided, the array substrate has a plurality of sub-pixel areas, the array substrate includes:
  • a plurality of common signal lines located on the substrate, the common signal lines are insulated from the pixel electrode layer, and are electrically connected to the common electrode layer, the common signal lines are on the substrate There is an overlapping area between the orthographic projection of the pixel electrode layer and the orthographic projection of the pixel electrode layer on the substrate;
  • the common signal line has a plurality of electrode structures, and different electrode structures are located in different sub-pixel areas.
  • the plurality of electrode structures include: overlapping joints overlapping with the common electrode layer. electrodes, and auxiliary electrodes that are not overlapped with the common electrode layer.
  • the orthographic projection of the auxiliary electrode on the substrate and the orthographic projection of the overlapping electrode on the substrate have the same shape and area.
  • the plurality of sub-pixel regions include: sub-pixel regions of at least two colors, the plurality of electrode structures correspond to multiple sub-pixel regions in the sub-pixel region of the same color one-to-one, and the electrode structures are located in corresponding within the sub-pixel area.
  • the overlapping electrode is distributed in one of the pixel areas, and the overlapping electrode is distributed in the other pixel area.
  • the sub-pixel area where the electrode structure is distributed is a blue sub-pixel area.
  • the array substrate has a plurality of via holes
  • the common electrode layer overlaps the overlapping electrode through at least one of the via holes
  • the orthographic projection of the via hole on the substrate is consistent with the Orthographic projections of the overlapping electrodes on the substrate at least partially overlap.
  • part of the orthographic projection of the via hole on the substrate is located within the orthographic projection of the overlapping electrode on the substrate, and the other part is located within the orthographic projection of the overlapping electrode on the substrate. Outside the orthographic projection on.
  • the pixel electrode layer is closer to the substrate than the common electrode layer.
  • the pixel electrode layer includes: a pixel electrode located in the sub-pixel area, and the pixel electrode is on the substrate.
  • the orthographic projection on the substrate does not coincide with the orthographic projection of the electrode structure on the substrate.
  • the pixel electrode has a hollow structure, and in the same sub-pixel area, the orthographic projection of the electrode structure on the substrate is located within the orthographic projection of the hollow structure on the substrate. .
  • the distance between the outer boundary of the orthographic projection of the electrode structure in each sub-pixel area on the substrate and the outer boundary of the orthographic projection of the hollow structure on the substrate are equal.
  • the array substrate further includes: a plurality of data lines, a plurality of gate lines and a plurality of transistors, the plurality of transistors corresponding to the plurality of pixel electrodes in one-to-one correspondence;
  • one gate line is electrically connected to the gate electrode of each transistor in the same row of transistors, the gate line is arranged in the same layer as the common signal line and has the same material, and the extending direction of the gate line is in the same direction as the common signal line.
  • the extension directions of public signal lines are parallel;
  • One of the data lines is electrically connected to the first electrode of each transistor in the same column, and the second electrode of the transistor is electrically connected to the corresponding pixel electrode.
  • any two adjacent transistors in a column electrically connected to the same data line Transistors one of the transistors is located on one side of the data line, and the other of the transistors is located on the other side of the data line.
  • the array substrate further includes: a first insulating layer located on a side of the plurality of transistors facing away from the substrate, and a second insulating layer located between the pixel electrode layer and the common electrode layer. ;
  • the pixel electrode layer is located on a side of the first insulating layer facing away from the substrate.
  • the common electrode layer has multiple slits.
  • a display device which device includes: a color filter substrate, a liquid crystal layer, and any one of the above array substrates;
  • the array substrate and the color filter substrate are arranged opposite to each other, and the liquid crystal layer is located between the array substrate and the color filter substrate.
  • the array substrate provided by embodiments of the present application includes: a substrate, and a pixel electrode layer, a common electrode layer and a plurality of common signal lines located on the substrate.
  • the common electrode line is also provided with: an overlapping electrode that overlaps with the common electrode layer, and an auxiliary electrode that does not overlap with the common electrode layer.
  • the number of via holes provided in the array substrate for overlapping the common electrode layer and the common signal line can be effectively reduced to ensure the alignment of the alignment film during the subsequent formation of the alignment film on the array substrate.
  • the probability of liquid diffusion unevenness is low, which can ensure that after the array substrate is subsequently integrated into a display device, the display device has a low probability of uneven brightness.
  • the size of the storage capacitor in the sub-pixel area where the overlapping electrode is located is approximately the same as the size of the storage capacitance in the sub-pixel area where the auxiliary electrode is located.
  • the value of ⁇ Vp corresponding to the pixel electrode in the sub-pixel area where the overlapping electrode is located is approximately the same as the value of ⁇ Vp corresponding to the pixel electrode in the sub-pixel area where the auxiliary electrode is located.
  • the display device displays images in a column-inverted manner
  • the image displayed by the display device has a low probability of adverse phenomena such as image flickering and jitter, which is effective.
  • the display effect of the display device is improved.
  • Figure 1 is a top view of a currently common array substrate
  • Figure 2 is a cross-sectional view of the array substrate shown in Figure 1 at D-D';
  • Figure 3 is a partial enlarged view of the array substrate shown in Figure 1 at position B;
  • Figure 4 shows a schematic diagram of the polarity change of the voltage corresponding to each sub-pixel area when the display device displays in a column inversion manner
  • Figure 5 is a top view of an array substrate provided by an embodiment of the present application.
  • Figure 6 is a cross-sectional view of the array substrate shown in Figure 5 at A-A';
  • Figure 7 is a partial enlarged view of the array substrate shown in Figure 5 at C;
  • Figure 8 is a partial enlarged view of the array substrate shown in Figure 5 at D;
  • Figure 9 is a cross-sectional view of the array substrate shown in Figure 7 at B-B';
  • Figure 10 is a cross-sectional view of the array substrate shown in Figure 8 at N-N';
  • Figure 11 is a schematic structural diagram of the array substrate in a sub-pixel area shown in Figure 5;
  • Figure 12 is a schematic diagram of the film layer of the array substrate shown in Figure 11 at M-M';
  • Figure 13 is a partial enlarged view of the array substrate shown in Figure 11 at E;
  • Figure 14 is a schematic diagram of another film layer at M-M’ of the array substrate shown in Figure 11;
  • Figure 15 is a schematic structural diagram of the common electrode layer of the array substrate shown in Figure 5;
  • FIG. 16 is a schematic diagram of the film structure of a display device provided by an embodiment of the present application.
  • Figure 1 is a top view of a currently common array substrate
  • Figure 2 is a cross-sectional view of the array substrate shown in Figure 1 at D-D’.
  • the array substrate 00 may include: a substrate 01, a pixel electrode layer 02 and a common electrode layer 03 located on the substrate 01, and a plurality of common signal lines 04 located on the substrate 01, the common signal lines 04 and the pixel electrode layer 02 It is insulated and electrically connected to the common electrode layer 03.
  • the array substrate 00 has multiple sub-pixel areas 0a.
  • the array substrate 00 may also include: multiple data lines 06 and multiple gate lines 07. Any two adjacent data lines 06 are connected to any two adjacent data lines 06.
  • the gate lines 07 can surround a sub-pixel area 0a.
  • the pixel electrode layer 02 may include: pixel electrodes 021 distributed in each sub-pixel area 0a.
  • the storage capacitor Cst can maintain the pixel voltage loaded on the pixel electrode 021, so that the display device integrated with the array substrate 00 can continue to display images.
  • the multiple sub-pixel areas Oa in the array substrate 00 may include: multiple red sub-pixel areas R, multiple green sub-pixel areas G, and multiple blue sub-pixel areas (B1, B2).
  • FIG. 3 is a partial enlarged view of the array substrate shown in FIG. 1 at position B.
  • the array substrate 00 has a plurality of via holes 05
  • the common signal line 04 has an overlapping electrode 041 corresponding to the via hole 05.
  • the common electrode layer 03 overlaps with the overlapping electrode 041 of the common signal line 04 through the plurality of via holes 05, so as to The common electrode layer 03 and the common signal line 04 are electrically connected.
  • the alignment liquid used to form the alignment film will spread unevenly during the process of forming the alignment film on the array substrate 00 , which will then lead to the subsequent use of the alignment film.
  • the display device is prone to uneven brightness, which affects the display effect of the display device.
  • one via hole 05 can be provided in every six sub-pixel areas in the array substrate 00 .
  • one via hole 05 can be provided in each blue sub-pixel area B1, and no via hole 05 is provided in the blue sub-pixel area B2 adjacent to the blue sub-pixel area B1.
  • overlapping electrodes 041 are distributed in each blue sub-pixel area B1, but no overlapping electrodes 041 are distributed in each blue sub-pixel area B2. Whether the overlapping electrodes 041 are distributed in the sub-pixel area will directly affect the size of the storage capacitor formed between the pixel electrode 021 and the common electrode line 04 in the sub-pixel area.
  • the size of the storage capacitor formed between the pixel electrode 021 and the common electrode line 04 in the blue sub-pixel area B1 is different from the size of the storage capacitor formed between the pixel electrode 021 and the common electrode line 04 in the blue sub-pixel area B2.
  • Capacitors vary in size.
  • the actual potential loaded on the pixel electrode 021 in each sub-pixel area 0a in the array substrate 00 is related to the size of the storage capacitor in this sub-pixel area 0a.
  • Cgs represents the coupling voltage formed between the gate line 07 and the data line 06 in the sub-pixel area 0a.
  • Capacitance represents the liquid crystal capacitance formed by the pixel electrode 021 and the common electrode layer 03 in the sub-pixel area 0a
  • Cst represents the storage capacitance formed by the overlap between the common electrode line 04 and the pixel electrode 021
  • Vgh represents the capacitance loaded on the gate line 07 High-level voltage
  • Vgl represents the low-level voltage loaded on gate line 07.
  • the value of ⁇ Vp corresponding to the pixel electrode 021 in the blue sub-pixel area B1 is, The value of ⁇ Vp corresponding to the pixel electrode 021 in the blue sub-pixel area B2 is different.
  • the pixel electrodes in the blue sub-pixel region B1 will also The actual potential loaded on 021 is different from the actual potential loaded on the pixel electrode 021 in the blue sub-pixel area B2.
  • the display device integrated with the array substrate 00 displays a blue image in a column inversion manner, the blue image displayed by the display device is prone to undesirable phenomena such as screen flickering and jitter.
  • FIG. 4 shows a schematic diagram of the polarity change of the voltage corresponding to each sub-pixel area when the display device displays in a column-inversion manner.
  • the first frame and the second frame respectively represent: the polarity of the pixel voltage loaded on the pixel electrode 021 in each sub-pixel area 0a before column inversion, and each sub-pixel area 0a after column inversion.
  • the polarities of the pixel voltages loaded on the pixel electrodes 021 in each sub-pixel region 0a before the column inversion and after the column inversion are opposite.
  • the display device in order to ensure that the display device does not cause flicker, jitter and other undesirable phenomena in the display screen, it is necessary to ensure that the brightness of each sub-pixel area 0a before column inversion and after column inversion is close to the same.
  • the brightness of the sub-pixel area 0a is related to the voltage difference formed between the pixel electrode 021 and the common electrode layer 03 in the sub-pixel area 0a. For this reason, when the voltage difference formed between the pixel electrode 021 and the common electrode layer 03 in the sub-pixel area 0a before column inversion and after column inversion is ensured to be the same, the flicker that occurs when the display device displays a picture can be reduced. and the degree of adverse phenomena such as jitter.
  • the value of ⁇ Vp corresponding to the pixel electrode 021 in the blue sub-pixel area B1 is different from the value of ⁇ Vp corresponding to the pixel electrode 021 in the blue sub-pixel area B2, and each sub-pixel area 0a
  • the pixel electrodes all share a common electrode layer 03. In this way, if the display device designs the common voltage loaded on the common electrode layer 03 based on the value of ⁇ Vp corresponding to the pixel electrode 021 of one of the blue sub-pixel areas B1 and B2 (the following embodiment takes B1 as an example) vcom.
  • the pixel electrode 021 and the common electrode layer 03 in the sub-pixel region B1 before column inversion and after column inversion are The voltage difference formed between them is the same.
  • the sub-pixels before column inversion and after column inversion are The voltage difference formed between the pixel electrode 021 and the common electrode layer 03 in the area B2 is different. For this reason, when the display device displays a blue picture, the blue picture displayed by the display device is prone to undesirable phenomena such as flicker and jitter.
  • the display device displays a low-grayscale blue monochrome image
  • the sub-pixels corresponding to the blue sub-pixel area suffer from undesirable phenomena such as flickering and jittering, which are most obvious. It can be seen that the display effect of the current display device is poor.
  • Figure 5 is a top view of an array substrate provided by an embodiment of the present application
  • Figure 6 is a cross-sectional view of the array substrate shown in Figure 5 at A-A’.
  • the array substrate 000 has a plurality of sub-pixel areas 00a.
  • the array substrate 000 includes a substrate 100, a pixel electrode layer 200, a common electrode layer 300 and a plurality of common signal lines 400 located on the substrate 100.
  • the array substrate 000 may further include: a plurality of data lines 700 and a plurality of gate lines 800 located on the substrate 100 .
  • the plurality of data lines 700 are arranged in parallel
  • the plurality of gate lines 800 are arranged in parallel
  • the extension direction of the data lines 700 intersects the extension direction of the gate lines 800 .
  • any two adjacent data lines 700 and any two adjacent gate lines 800 can form a sub-pixel area 00a.
  • the common signal line 400 in the array substrate 000 is insulated from the pixel electrode layer 200 and is electrically connected to the common electrode layer 300 .
  • the pixel electrode layer 200 in the array substrate 000 may include: pixel electrodes 201 distributed in each sub-pixel area 00a.
  • the orthographic projection of the pixel electrode 201 in each sub-pixel area 00 a on the substrate 100 may have an overlapping area with the orthographic projection of the common signal line 400 on the substrate 100 , so that the common electrode line 400 and The overlapping portion of the pixel electrodes 201 can form a storage capacitor Cst in this sub-pixel region 00a.
  • the common signal line 400 has multiple electrode structures 400a, and different electrode structures 400a are located in different sub-pixel areas 00a.
  • the plurality of electrode structures 400a include: overlapping electrodes 401 overlapping the common electrode layer 300, and auxiliary electrodes 402 not overlapping the common electrode layer 300.
  • FIG. 7 is a partial enlarged view of the array substrate shown in FIG. 5 at position C. Because there is usually an insulating layer between the conductive layer where the common signal line 400 is located and the common electrode layer 300 . Therefore, it is necessary to provide a via V1 in the array substrate 000 so that the common electrode layer 300 can pass through The via hole V1 is electrically connected to the overlapping electrode 401 of the common signal line 400 .
  • FIG. 8 is a partial enlarged view of the array substrate shown in FIG. 5 at D.
  • the auxiliary electrode 402 in the common signal line 400 is also provided with an auxiliary electrode 402, and this auxiliary electrode 402 does not overlap with the common electrode layer 300. Therefore, there is no need to provide a via V1 for overlapping the common electrode layer 300 and the common signal line 400 in the sub-pixel area 00a where the auxiliary electrode 402 is distributed. In this way, the number of vias V1 provided in the array substrate 000 for overlapping the common electrode layer 300 and the common signal line 400 can be effectively reduced to ensure that the alignment film is formed on the array substrate 000 in the subsequent process.
  • the alignment liquid forming the alignment film has a low probability of uneven diffusion, which can ensure that after the array substrate 000 is subsequently integrated into a display device, the display device has a low probability of uneven brightness.
  • the overlap electrode 401 that overlaps with the common electrode layer 300 by simultaneously arranging in the common electrode line 400: the overlap electrode 401 that overlaps with the common electrode layer 300, and the auxiliary electrode 402 that does not overlap with the common electrode layer 300, it is possible to ensure that the overlap electrode 401
  • the size of the storage capacitor Cst in the sub-pixel area 00a where the auxiliary electrode 401 is located is approximately the same as the size of the storage capacitor Cst in the sub-pixel area 00a where the auxiliary electrode 401 is located.
  • the value of ⁇ Vp corresponding to the pixel electrode 201 in the sub-pixel area 00a where the overlapping electrode 401 is located is approximately the same as the value of ⁇ Vp corresponding to the pixel electrode 201 in the sub-pixel area 00a where the auxiliary electrode 401 is located. .
  • the display device displays a picture in a column-inverted manner, the probability of undesirable phenomena such as flickering and jitter in the picture displayed by the display device is low. The display effect of the display device is effectively improved.
  • the array substrate provided by the embodiment of the present application includes: a substrate, and a pixel electrode layer, a common electrode layer and a plurality of common signal lines located on the substrate.
  • the common electrode line is also provided with: an overlapping electrode that overlaps with the common electrode layer, and an auxiliary electrode that does not overlap with the common electrode layer.
  • the number of via holes provided in the array substrate for overlapping the common electrode layer and the common signal line can be effectively reduced to ensure the alignment of the alignment film during the subsequent formation of the alignment film on the array substrate.
  • the probability of liquid diffusion unevenness is low, which can ensure that after the array substrate is subsequently integrated into a display device, the display device has a low probability of uneven brightness.
  • the size of the storage capacitor in the sub-pixel area where the overlapping electrode is located is approximately the same as the size of the storage capacitance in the sub-pixel area where the auxiliary electrode is located.
  • the value of ⁇ Vp corresponding to the pixel electrode in the sub-pixel area where the overlapping electrode is located is approximately the same as the value of ⁇ Vp corresponding to the pixel electrode in the sub-pixel area where the auxiliary electrode is located.
  • the display device displays a picture in a column-inverted manner
  • the picture displayed by the display device has a low probability of adverse phenomena such as picture flickering and jitter, effectively improving the display efficiency.
  • the display effect of the device is not limited to picture flickering and jitter.
  • the orthographic projection of each electrode structure 400 a on the substrate 100 has the same shape and area. That is, the orthographic projection of the overlapping electrode 401 in the common signal line 400 on the substrate 100 has the same shape and area as the orthographic projection of the overlapping electrode 401 on the substrate 100 .
  • the size of the storage capacitor Cst in the sub-pixel area 00a where the overlapping electrode 401 is located is the same as the size of the storage capacitor Cst in the sub-pixel area 00a where the auxiliary electrode 401 is located, so as to further reduce the display cost.
  • multiple sub-pixel areas 00a in the array substrate 000 may include: sub-pixel areas 00a of at least two colors, multiple electrode structures 400a and multiple sub-pixel areas 00a of the same color.
  • the sub-pixel areas 00a correspond one to one, and each electrode structure 400a may be located in the corresponding sub-pixel area 00a.
  • the plurality of sub-pixel areas 00a include three-color sub-pixel areas 00a.
  • the three-color sub-pixel areas are respectively: a red sub-pixel area R, a green sub-pixel area G and a blue sub-pixel area (B1 , B2).
  • the sub-pixel areas where the electrode structures 400a are distributed are sub-pixel areas of the same color.
  • the sub-pixel area where the electrode structure 400a is distributed is the blue sub-pixel area (B1, B2).
  • the electrode structure 400a of the common electrode line 400 is usually made of an opaque metal material. Therefore, when the electrode structure 400a is distributed in the sub-pixel area 00a, the aperture ratio of the sub-pixel area 00a will be reduced.
  • the electrode structures 400a are evenly distributed in the blue sub-pixel areas (B1, B2), even if the aperture ratio of the blue sub-pixel areas (B1, B2) is small, it will not affect the overall display effect of the display device. , and at the same time, it can also ensure that the intensity of the blue light emitted by the display device when displaying the picture is low, so as to ensure that the display device has a certain degree of eye protection.
  • overlapping electrodes 401 are distributed in one sub-pixel area B1, and the other is Auxiliary electrodes 402 are distributed in one sub-pixel area B2.
  • overlapping electrodes 401 are distributed in each sub-pixel area B1, and auxiliary electrodes 402 are distributed in each sub-pixel area B2.
  • the overlapping electrodes 401 are evenly distributed in the array substrate 000
  • the auxiliary electrodes 402 are also evenly distributed in the array substrate 000
  • the via holes V1 corresponding to the overlapping electrodes 401 in the array substrate 000 are also evenly distributed within the array substrate 000.
  • the array substrate 000 has a plurality of via holes V1.
  • the common electrode layer 300 overlaps the overlapping electrode 401 through at least one via hole V1.
  • the orthographic projection of the via hole V1 on the substrate 100 is in line with the overlapping electrode 401. Orthographic projections on substrate 100 at least partially overlap.
  • the orthographic projection of the via V1 on the substrate 100 is located within the orthographic projection of the overlapping electrode 401 on the substrate 100 .
  • FIG. 9 is a cross-sectional view of the array substrate shown in FIG. 7 at B-B’.
  • Part of the orthographic projection of the via hole V1 on the substrate 100 is located within the orthographic projection of the overlapping electrode 401 on the substrate 100 , and the other part is located outside the orthographic projection of the overlapping electrode 401 on the substrate 100 . That is, the orthographic projection of the via hole V1 on the substrate 100 and the orthographic projection of the overlapping electrode 401 on the substrate 100 only partially overlap.
  • the depth of the portion of the via hole V1 that overlaps the overlapping electrode 401 is small, and the depth of the portion of the via hole V1 that does not overlap the overlapping electrode 401 is large. That is to say, the via V1 is a deep-shallow hole structure with a deeper depth in some areas and a shallower depth in some areas. This deep and shallow hole structure is conducive to the diffusion of the alignment liquid, which can further improve the uniformity of the diffusion of the alignment liquid used to form the alignment film, avoid the problem of uneven brightness caused by uneven diffusion of the alignment liquid, and improve the display The display effect of the device.
  • FIG. 10 is a cross-sectional view of the array substrate shown in FIG. 8 at N-N’.
  • the auxiliary electrode 402 does not overlap with the common electrode layer 300 , and there is no need to provide a via V1 for overlapping the common electrode layer 300 with the common signal line 400 .
  • the number of vias V1 provided in the array substrate 000 for overlapping the common electrode layer 300 and the common signal line 400 can be effectively reduced.
  • the pixel electrode layer 200 is closer to the substrate 100 than the common electrode layer 300.
  • the pixel electrode layer 200 in the array substrate 000 includes: a pixel electrode 201 located in the sub-pixel area 00a.
  • the pixel electrode 201 The orthographic projection on the substrate 100 does not coincide with the orthographic projection of the electrode structure 400 a on the substrate 100 .
  • the overlapping electrode 401 needs to pass through the pixel electrode layer 200 and be electrically connected to the common electrode 300.
  • the orthographic projection of the pixel electrode 201 on the substrate 100 When the orthographic projection of the electrode structure 400a on the substrate 100 is not coincident, overlapping electrodes can be avoided.
  • the pole 401 When the pole 401 is electrically connected to the common electrode 300, it is short-circuited with the pixel electrode 201.
  • the common electrode layer 300 can also be closer to the substrate 100 than the pixel electrode layer 200.
  • the common electrode layer 300 can be directly connected to the overlapping through the via V1.
  • the electrodes 401 are electrically connected without passing through the pixel electrode layer 200 . In this way, the orthographic projection of the pixel electrode layer 200 on the substrate 100 and the orthographic projection of the electrode structure 400a on the substrate 100 can overlap.
  • FIG. 11 is a schematic structural diagram of the array substrate in a sub-pixel area shown in FIG. 5 .
  • the pixel electrode 201 in the sub-pixel area 00a has a hollow structure 201a.
  • the orthographic projection of the electrode structure 400a on the substrate 100 is located within the orthographic projection of the hollow structure 201a on the substrate 100.
  • the overlapping electrode 401 needs to pass through the pixel electrode layer 200 and then be electrically connected to the common electrode 300.
  • the pixel electrode 201 in the pixel electrode layer 200 has a hollow structure 201a, it can avoid a short circuit with the pixel electrode 201 when the overlapping electrode 401 is electrically connected to the common electrode 300.
  • a coupling capacitance will be formed between the electrode structure 400a and the pixel electrode 201, and the size of the coupling capacitance is related to the distance between the outer boundary of the electrode structure 400a and the outer boundary of the pixel electrode 201. .
  • the outer boundary of the orthographic projection of the electrode structure 400 a in each sub-pixel area 00 a on the substrate 100 is between the outer boundary of the orthographic projection of the hollow structure 201 a on the substrate 100 .
  • the distance between them is equal. In this way, it can be ensured that the coupling capacitance formed between the electrode structure 400a and the pixel electrode 201 is close, and the size of the storage capacitance is related to the size of the coupling capacitance.
  • the area of the overlapping portion of the pixel electrode 201 and the common electrode line 400 is also the same. In this way, it can be ensured that the electrode structure 400a in each pixel area 00a is The storage capacitances between the pixel electrodes 201 are the same.
  • the array substrate 000 further includes: a plurality of transistors 900 located on the substrate 100 .
  • the plurality of transistors 900 correspond to the plurality of pixel electrodes 201 in one-to-one correspondence.
  • FIG. 12 is a schematic diagram of the film layer of the array substrate at MM' shown in FIG. 11 .
  • one gate line 800 is electrically connected to the gate electrode 904 of each transistor 900 in the same row of transistors 900.
  • the gate line 800 and the common signal line 400 are arranged in the same layer and made of the same material.
  • the extension direction of the gate line 800 is in line with the common signal line 400.
  • the extension direction is parallel; a data line 700 is in the same column of transistors 900
  • the first pole 901 of each transistor 900 is electrically connected, and the second pole 902 of the transistor 900 is electrically connected to the corresponding pixel electrode 201.
  • FIG. 13 is a partial enlarged view of the array substrate shown in FIG. 11 at position E.
  • the first electrode 901 is the source electrode of the transistor 900
  • the second electrode 902 is the drain electrode of the transistor 900 .
  • Transistor 900 includes: gate electrode 904, source electrode 901, drain electrode 902 and active layer 903.
  • the array substrate 000 also includes: a first insulating layer 500 located on the side of the plurality of transistors 900 facing away from the substrate 100, and a second insulating layer 600 located between the pixel electrode layer 200 and the common electrode layer 300;
  • the pixel electrode layer 200 is located on a side of the first insulating layer 500 away from the substrate 100 , and the pixel electrode layer 200 is closer to the substrate 100 than the common electrode layer 300 .
  • the second insulating layer 600 between the pixel electrode layer 200 and the common electrode layer 300, the overlapping portion of the common electrode layer 300 and the pixel electrode layer 200 can form a liquid crystal capacitor.
  • FIG. 14 is a schematic diagram of another film layer at position M-M’ of the array substrate shown in FIG. 11 .
  • the first insulating layer 500 is not provided between the transistor 900 and the pixel electrode 201, and the second electrode 902 of the transistor 900 and the corresponding pixel electrode 201 are directly connected together. In this way, process steps can be reduced and production costs can be reduced.
  • any two adjacent transistors 900 in a column of transistors 900 that are electrically connected to the same data line 700 one transistor 900 is located on one side of the data line 700 and the other transistor 900 is located on the other side of the data line 700 . side.
  • the polarity of the pixel voltage loaded on the pixel electrode 201 in each sub-pixel region 00a before column inversion and after column inversion is opposite, and before and after column inversion, any two adjacent sub-pixels 00a have opposite polarities.
  • the pixel voltages loaded on the pixel electrodes 201 in the pixel area 00a all have opposite polarities.
  • FIG. 15 is a schematic structural diagram of the common electrode layer of the array substrate shown in FIG. 5 .
  • the common electrode layer 300 in the array substrate 000 has a plurality of slits 301.
  • an electric field parallel to the direction of the substrate 100 can be formed between the pixel electrode 201 in each pixel area 00a and the common electrode layer 300 having a plurality of slits 301.
  • This electric field can drive the liquid crystal to deflect in a direction parallel to the substrate 100. .
  • the array substrate provided by the embodiment of the present application includes: a substrate, and a pixel electrode layer, a common electrode layer and a plurality of common signal lines located on the substrate.
  • the common electrode line is also provided with: an overlapping electrode that overlaps with the common electrode layer, and an auxiliary electrode that does not overlap with the common electrode layer.
  • the number of via holes provided in the array substrate for overlapping the common electrode layer and the common signal line can be effectively reduced to ensure the alignment of the alignment film during the subsequent formation of the alignment film on the array substrate.
  • the probability of liquid diffusion unevenness is low, which can ensure that after the array substrate is subsequently integrated into a display device, the display device has a low probability of uneven brightness.
  • the size of the storage capacitor in the sub-pixel area where the overlapping electrode is located is approximately the same as the size of the storage capacitance in the sub-pixel area where the auxiliary electrode is located.
  • the value of ⁇ Vp corresponding to the pixel electrode in the sub-pixel area where the overlapping electrode is located is approximately the same as the value of ⁇ Vp corresponding to the pixel electrode in the sub-pixel area where the auxiliary electrode is located.
  • the display device displays images in a column-inverted manner
  • the image displayed by the display device has a low probability of adverse phenomena such as image flickering and jitter, which is effective.
  • the display effect of the display device is improved.
  • FIG. 16 is a schematic diagram of the film structure of a display device provided by an embodiment of the present application.
  • the display device may include: a color filter substrate 001, a liquid crystal layer 002, and any of the above array substrates 000; the array substrate 000 and the color filter substrate 001 are arranged oppositely, and the liquid crystal layer 002 is located between the array substrate 000 and the color filter substrate 001.
  • the display device may be: a liquid crystal panel, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop, a digital photo frame, a navigator, or any other product or component with a display function.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
  • plurality refers to two or more than two, unless expressly limited otherwise.

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Abstract

一种阵列基板（000）及显示装置，属于显示技术领域。阵列基板（000）包括：衬底（100）；位于衬底（100）上的像素电极层（200）和公共电极层（300）；以及，位于衬底（100）上的多条公共信号线（400），公共信号线（400）与像素电极层（200）绝缘设置，且与公共电极层（300）电连接，公共信号线（400）在衬底（100）上的正投影与像素电极层（200）在衬底（100）上的正投影存在交叠区域；其中，公共信号线（400）具有多个电极结构（400a），不同的电极结构（400a）位于不同的子像素区域（00a）内，多个电极结构（400a）包括：与公共电极层（300）搭接的搭接电极（401），以及未与公共电极层（300）搭接的辅助电极（402）。由于在公共信号线（400）中同时设置搭接电极（401）和辅助电极（402），这样搭接电极（401）与辅助电极（402）所在的子像素区域（00a）内的存储电容（Cst）的大小近似相同，进而降低了显示装置所显示的画面出现画面闪烁和抖动等不良现象的概率。

Description

阵列基板及显示装置
本申请要求于2022年05月25日提交的申请号为202210580442.2、申请名称为“阵列基板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，特别涉及一种阵列基板及显示装置。
背景技术
目前，显示装置已经成为了人们生活中不可或缺的电子产品。诸如智能手环、手机、平板电脑等显示装置极大的增加了人们生活的便利性。
显示装置可以包括：相对设置的阵列基板和彩膜基板，以及位于阵列基板和彩膜基板中的液晶层。阵列基板可以包括：衬底，以及位于衬底上的公共信号线和公共电极，公共信号线和公共电极异层设置，且公共信号线和公共电极之间通过过孔电连接。但是，目前显示装置的显示效果较差。
发明内容
本申请实施例提供了一种阵列基板及显示装置，可以提高显示装置的显示效果，所述技术方案如下：
一方面，提供了一种阵列基板，所述阵列基板具有多个子像素区域，所述阵列基板包括：
衬底；
位于所述衬底上的像素电极层和公共电极层；
以及，位于所述衬底上的多条公共信号线，所述公共信号线与所述像素电极层绝缘设置，且与所述公共电极层电连接，所述公共信号线在所述衬底上的正投影与所述像素电极层在所述衬底上的正投影存在交叠区域；
其中，所述公共信号线具有多个电极结构，不同的所述电极结构位于不同的所述子像素区域内，所述多个电极结构包括：与所述公共电极层搭接的搭接 电极，以及未与所述公共电极层搭接的辅助电极。
可选的，所述辅助电极在所述衬底上的正投影与所述搭接电极在所述衬底上的正投影的形状和面积均相同。
可选的，所述多个子像素区域包括：至少两种颜色的子像素区域，所述多个电极结构与同一种颜色子像素区域内的多个子像素区域一一对应，所述电极结构位于对应的子像素区域内。
可选的，在所述同一种颜色子像素区域中，对于任意两个相邻的所述子像素区域，一个所述像素区域内分布有所述搭接电极，另一个所述像素区域内分布有所述辅助电极。
可选的，分布有所述电极结构的子像素区域为蓝色子像素区域。
可选的，所述阵列基板具有多个过孔，所述公共电极层通过至少一个所述过孔与所述搭接电极搭接，所述过孔在所述衬底上的正投影与所述搭接电极在所述衬底上的正投影至少部分交叠。
可选的，所述过孔在所述衬底上的正投影中的一部分位于所述搭接电极在所述衬底上的正投影内，另一部分位于所述搭接电极在所述衬底上的正投影外。
可选的，所述像素电极层相对于所述公共电极层更靠近所述衬底，所述像素电极层包括：位于所述子像素区域内的像素电极，所述像素电极在所述衬底上的正投影与所述电极结构在所述衬底上的正投影不重合。
可选的，所述像素电极具有镂空结构，在同一个所述子像素区域内，所述电极结构在所述衬底上的正投影位于所述镂空结构在所述衬底上的正投影内。
可选的，各个所述子像素区域内的所述电极结构在所述衬底上的正投影的外边界与所述镂空结构在所述衬底上的正投影的外边界之间的距离相等。
可选的，所述阵列基板还包括：多条数据线、多条栅线和多个晶体管，所述多个晶体管与多个所述像素电极一一对应；
其中，一条所述栅线与同一行所述晶体管中的各个晶体管的栅极电连接，所述栅线与所述公共信号线同层设置且材料相同，所述栅线的延伸方向与所述公共信号线的延伸方向平行；
一条所述数据线与同一列所述晶体管中的各个晶体管的第一极电连接，所述晶体管的第二极与对应的像素电极电连接。
可选的，对于与同一条所述数据线电连接的一列晶体管中任意两个相邻的 晶体管，一个所述晶体管位于所述数据线的一侧，另一个所述晶体管位于所述数据线的另一侧。
可选的，所述阵列基板还包括：位于所述多个晶体管背离所述衬底一侧的第一绝缘层，以及位于所述像素电极层与所述公共电极层之间的第二绝缘层；
其中，所述像素电极层位于所述第一绝缘层背离所述衬底的一侧。
可选的，所述公共电极层具有多个狭缝。
另一方面，提供了一种显示装置，所述装置包括：彩膜基板、液晶层和上述任意一种阵列基板；
所述阵列基板和所述彩膜基板相对设置，所述液晶层位于所述阵列基板和所述彩膜基板之间。
本申请实施例提供的技术方案带来的有益效果至少包括：
本申请实施例提供的阵列基板，包括：衬底，以及位于衬底上的像素电极层、公共电极层和多条公共信号线。公共电极线中同时设置有：与公共电极层搭接的搭接电极，以及未与公共电极层搭接的辅助电极。这样，可以有效的减少阵列基板内设置的用于让公共电极层与公共信号线搭接的过孔的数量，以保证后续在阵列基板上形成配向膜的过程中，用于形成配向膜的配向液出现扩散不均匀的概率较低，进而可以保证后续将这个阵列基板集成在显示装置内后，显示装置出现亮度不均的概率较低。并且，通过在公共电极线中同时设置搭接电极和辅助电极，可以保证搭接电极所在的子像素区域内的存储电容的大小，与辅助电极所在的子像素区域内的存储电容的大小近似相同。进而可以保证搭接电极所在的子像素区域内的像素电极所对应的△Vp的数值，与辅助电极所在的子像素区域内像素电极所对应的△Vp的数值近似相同。为此，当本申请中的阵列基板在集成在显示装置内，且显示装置以列反转的方式显示画面时，显示装置所显示的画面出现画面闪烁和抖动等不良现象的概率较低，有效的提高了显示装置的显示效果。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所 需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是目前常见的一种阵列基板的俯视图；
图2是图1示出的阵列基板在D-D’处的截面图；
图3是图1示出的阵列基板在B处的局部放大图；
图4示出的是当显示装置采用列反转的方式显示时，各个子像素区域对应的电压的极性变化示意图；
图5是本申请实施例提供的一种的阵列基板的俯视图；
图6是图5示出的阵列基板在A-A’处的截面图；
图7是图5示出的阵列基板在C处的局部放大图；
图8是图5示出的阵列基板在D处的局部放大图；
图9是图7示出的阵列基板在B-B’处的截面图；
图10是图8示出的阵列基板在N-N’处的截面图；
图11是图5示出的一个子像素区域内的阵列基板的结构示意图；
图12是图11示出的阵列基板在M-M’处的膜层示意图；
图13是图11示出的阵列基板在E处的局部放大图；
图14是图11示出的阵列基板在M-M’处的另一种膜层示意图；
图15是图5示出的阵列基板的公共电极层的结构示意图；
图16是本申请实施例提供的一种显示装置的膜层结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
请参考图1和图2，图1是目前常见的一种阵列基板的俯视图，图2是图1示出的阵列基板在D-D’处的截面图。阵列基板00可以包括：衬底01，位于衬底01上的像素电极层02和公共电极层03，以及，位于衬底01上的多条公共信号线04，公共信号线04与像素电极层02绝缘设置，且与公共电极层03电连接。
其中，阵列基板00具有多个子像素区域0a，例如，阵列基板00还可以包括：多条数据线06和多条栅线07，任意两条相邻的数据线06与任意两条相邻 的栅线07能够围成一个子像素区域0a。像素电极层02可以包括：分布在各个子像素区域0a内的像素电极021。
公共电极线04在衬底01上的正投影与像素电极021在衬底01上的正投影存在交叠区域，使得公共电极线04与像素电极021交叠的部分能够形成存储电容Cst。存储电容Cst能够保持像素电极021上加载的像素电压，使集成了这个阵列基板00的显示装置能够持续显示图像。
如图1所示，阵列基板00中的多个子像素区域0a可以包括：多个红色子像素区域R、多个绿色子像素区域G和多个蓝色子像素区域(B1、B2)。
为了更清楚的了解阵列基板的结构，请参考图3，图3是图1示出的阵列基板在B处的局部放大图。阵列基板00具有多个过孔05，公共信号线04具有与过孔05对应的搭接电极041，公共电极层03通过多个过孔05与公共信号线04的搭接电极041搭接，以实现让公共电极层03与公共信号线04电连接。需要说明的是，若阵列基板00内的过孔05的数量较多，会导致在阵列基板00上形成配向膜的过程中，用于形成配向膜的配向液扩散不均匀，进而导致后续将这个阵列基板00集成在显示装置内后，显示装置极易出现亮度不均的不良问题，影响显示装置的显示效果。为此，需要减少阵列基板00内设置的过孔05的数量，例如，可以在阵列基板00中每6个子像素区域设置一个过孔05。
在这种情况下，可以在各个蓝色子像素区域B1内均设置一个过孔05，而与蓝色子像素区域B1相邻的蓝色子像素区域B2内不设置过孔05。并且，各个蓝色子像素区域B1内均分布有搭接电极041，而各个蓝色子像素区域B2内均未分布搭接电极041。而子像素区域内是否分布搭接电极041，会直接影响这个子像素区域内的像素电极021与公共电极线04之间形成的存储电容的大小。为此，蓝色子像素区域B1内的像素电极021与公共电极线04之间形成的存储电容的大小，与蓝色子像素区域B2内的像素电极021与公共电极线04之间形成的存储电容的大小不同。
其中，阵列基板00内各个子像素区域0a内的像素电极021上加载的实际电位，与这个子像素区域0a内的存储电容的大小相关。例如，像素电极021上加载的预设电位与实际电位的差值△Vp可以通过以下公式计算得到：
△Vp＝Cgs/(Cgs+Clc+Cst)*(Vgh-Vgl)；
这里，Cgs表示子像素区域0a内的栅线07与数据线06之间形成的耦合电 容；Clc表示子像素区域0a内的像素电极021与公共电极层03形成的液晶电容；Cst表示公共电极线04与像素电极021交叠的部分形成的存储电容；Vgh表示栅线07上加载的高电平电压，Vgl表示栅线07上加载的低电平电压。
因此，当蓝色子像素区域B1内的存储电容的大小与蓝色子像素区域B2内的存储电容的大小不同时，蓝色子像素区域B1内的像素电极021所对应的△Vp的数值，与蓝色子像素区域B2内的像素电极021所对应的△Vp的数值不同。为此，即使阵列基板00向两种蓝色子像素区域内的像素电极021同时施加电位相同的信号(也即，均加载预设电位)，也会导致蓝色子像素区域B1内的像素电极021加载的实际电位与蓝色子像素区域B2内的像素电极021加载的实际电位不同。在这种情况下，当集成了这个阵列基板00的显示装置采用列反转的方式显示蓝色画面时，该显示装置所显示的蓝色画面极易出现画面闪烁和抖动等不良现象。
例如，请参考图4，图4示出的是当显示装置采用列反转的方式显示时，各个子像素区域对应的电压的极性变化示意图。在图4中，第一帧画面和第二帧画面分别表示：列反转前各个子像素区域0a内的像素电极021所加载的像素电压的极性，以及列反转后各个子像素区域0a内的像素电极021所加载的像素电压的极性。其中，列反转前和列反转后的各个子像素区域0a内的像素电极021所加载的像素电压的极性相反。
如此，为了确保显示装置在显示画面不会出现闪烁和抖动等不良现象，需要确保列反转前和列反转后的各个子像素区域0a的亮度相近相同。而显示装置在显示画面时，子像素区域0a的亮度与这个子像素区域0a内的像素电极021和公共电极层03之间形成的电压差相关。为此，在保证列反转前和列反转后的子像素区域0a内的像素电极021与公共电极层03之间形成的电压差相同时，即可减轻显示装置在显示画面时出现的闪烁和抖动等不良现象的程度。
然而，蓝色子像素区域B1内的像素电极021所对应的△Vp的数值，与蓝色子像素区域B2内的像素电极021所对应的△Vp的数值并不同，且各个子像素区域0a内的像素电极均共用一个公共电极层03。这样，若显示装置以蓝色子像素区域B1和B2中的一个(以下实施例以B1为例)的像素电极021所对应的△Vp的数值为依据，设计公共电极层03所加载的公共电压Vcom。则，可以确保在列反转前和列反转后的子像素区域B1内的像素电极021与公共电极层03 之间形成的电压差相同。但由于蓝色子像素区域B1内的像素电极021加载的实际电位与蓝色子像素区域B2内的像素电极021加载的实际电位不同，因此，在列反转前和列反转后的子像素区域B2内的像素电极021与公共电极层03之间形成的电压差是不同的。为此，当这个显示装置显示蓝色画面时，该显示装置所显示的蓝色画面极易出现画面闪烁和抖动等不良现象。尤其是，在显示装置显示低灰阶蓝色单色画面时，蓝色子像素区域对应的子像素发生闪烁和抖动等不良现象最为明显。由此可见，目前显示装置的显示效果较差。
请参考图5和图6，图5是本申请实施例提供的一种的阵列基板的俯视图，图6是图5示出的阵列基板在A-A’处的截面图。阵列基板000具有多个子像素区域00a，该阵列基板000包括：衬底100，以及位于衬底100上的像素电极层200、公共电极层300和多条公共信号线400。
示例的，阵列基板000还可以包括：位于衬底100上的多条数据线700和多条栅线800。其中，多条数据线700平行排布，多条栅线800平行排布，且数据线700的延伸方向与栅线800的延伸方向相交。在阵列基板000中，任意两条相邻的数据线700与任意两条相邻的栅线800能够围成一个子像素区域00a。
阵列基板000中的公共信号线400与像素电极层200绝缘设置，且与公共电极层300电连接。
阵列基板000中的公共信号线400在衬底100上的正投影与像素电极层200在衬底100上的正投影存在交叠区域。其中，阵列基板000中的像素电极层200可以包括：分布在各个子像素区域00a内的像素电极201。如图6所示，每个子像素区域00a内的像素电极201在衬底100上的正投影，可以与公共信号线400在衬底100上的正投影存在交叠区域，使得公共电极线400与像素电极201交叠的部分能够在这个子像素区域00a内形成存储电容Cst。
其中，公共信号线400具有多个电极结构400a，不同的电极结构400a位于不同的子像素区域00a内。多个电极结构400a包括：与公共电极层300搭接的搭接电极401，以及未与公共电极层300搭接的辅助电极402。
在本申请实施例中，请参考图7，图7是图5示出的阵列基板在C处的局部放大图。由于公共信号线400所在的导电层与公共电极层300之间通常存在绝缘层。因此，需要在阵列基板000内设置过孔V1，使得公共电极层300可以通 过过孔V1与公共信号线400的搭接电极401电连接。
请参考图8，图8是图5示出的阵列基板在D处的局部放大图。公共信号线400中的辅助电极402内除了设置有搭接电极401，还设置有辅助电极402，且这个辅助电极402未与公共电极层300搭接。因此，分布有辅助电极402的子像素区域00a内无需设置用于让公共电极层300与公共信号线400搭接的过孔V1。这样，可以有效的减少阵列基板000内设置的用于让公共电极层300与公共信号线400搭接的过孔V1的数量，以保证后续在阵列基板000上形成配向膜的过程中，用于形成配向膜的配向液出现扩散不均匀的概率较低，进而可以保证后续将这个阵列基板000集成在显示装置内后，显示装置出现亮度不均的概率较低。
并且，在本申请中，通过在公共电极线400中同时设置：与公共电极层300搭接的搭接电极401，以及未与公共电极层300搭接的辅助电极402，可以保证搭接电极401所在的子像素区域00a内的存储电容Cst的大小，与辅助电极401所在的子像素区域00a内的存储电容Cst的大小近似相同。这样，可以保证搭接电极401所在的子像素区域00a内的像素电极201所对应的△Vp的数值，与辅助电极401所在的子像素区域00a内像素电极201所对应的△Vp的数值近似相同。为此，当本申请中的阵列基板000在集成在显示装置内，且显示装置以列反转的方式显示画面时，显示装置所显示的画面出现画面闪烁和抖动等不良现象的概率较低，有效的提高了显示装置的显示效果。
综上所述，本申请实施例提供的阵列基板，包括：衬底，以及位于衬底上的像素电极层、公共电极层和多条公共信号线。公共电极线中同时设置有：与公共电极层搭接的搭接电极，以及未与公共电极层搭接的辅助电极。这样，可以有效的减少阵列基板内设置的用于让公共电极层与公共信号线搭接的过孔的数量，以保证后续在阵列基板上形成配向膜的过程中，用于形成配向膜的配向液出现扩散不均匀的概率较低，进而可以保证后续将这个阵列基板集成在显示装置内后，显示装置出现亮度不均的概率较低。并且，通过在公共电极线中同时设置搭接电极和辅助电极，可以保证搭接电极所在的子像素区域内的存储电容的大小，与辅助电极所在的子像素区域内的存储电容的大小近似相同。进而可以保证搭接电极所在的子像素区域内的像素电极所对应的△Vp的数值，与辅助电极所在的子像素区域内像素电极所对应的△Vp的数值近似相同。为此，当 本申请中的阵列基板在集成在显示装置内，且显示装置以列反转的方式显示画面时，显示装置所显示的画面出现画面闪烁和抖动等不良现象的概率较低，有效的提高了显示装置的显示效果。
在本申请中，如图5所示，各个电极结构400a在衬底100上的正投影的形状和面积均相同。也即是，公共信号线400中的搭接电极401在衬底100上的正投影与搭接电极401在衬底100上的正投影的形状和面积均相同。在这种情况下，可以保证搭接电极401所在的子像素区域00a内的存储电容Cst的大小，与辅助电极401所在的子像素区域00a内的存储电容Cst的大小相同，以进一步的降低显示装置所显示的画面出现画面闪烁和抖动等不良现象的概率。
在本申请中，如图5所示，阵列基板000内的多个子像素区域00a可以包括：至少两种颜色的子像素区域00a，多个电极结构400a与同一种颜色子像素区域00a内的多个子像素区域00a一一对应，每个电极结构400a可以位于对应的子像素区域00a内。示例性的，多个子像素区域00a包括的三种颜色的子像素区域00a，这三种颜色的子像素区域分别为：红色子像素区域R、绿色子像素区域G和蓝色子像素区域(B1、B2)。
其中，分布有电极结构400a的子像素区域为同一颜色的子像素区域。例如，在图5中，分布有电极结构400a的子像素区域为蓝色子像素区域(B1、B2)。由于公共电极线400的电极结构400a通常是由不透光金属材料制成的。因此，当子像素区域00a内分布电极结构400a时，会降低这个子像素区域00a的开口率。而为了提高显示装置的护眼性，通常需要降低显示装置显示画面时蓝光出射强度，且蓝光对显示装置的显示效果的影响较小。为此，当电极结构400a均分布在蓝色子像素区域(B1、B2)内时，即使蓝色子像素区域(B1、B2)的开口率较小，也不会影响显示装置的整体显示效果，同时还可以保证显示装置显示画面时出射的蓝光的强度较低，以保证这个显示装置具有一定的护眼性。
示例性的，如图5所示，在同一种颜色子像素区域00a中，对于任意两个相邻的子像素区域(B1、B2)，一个子像素区域B1内分布有搭接电极401，另一个子像素区域B2内分布有辅助电极402。示例的，在图5中，各个子像素区域B1均分布有搭接电极401，各个子像素区域B2内均分布有辅助电极402。
在这种情况下，搭接电极401均匀分布在阵列基板000内，辅助电极402也均匀分布在阵列基板000内，阵列基板000中与搭接电极401对应的过孔V1 也均匀分布在阵列基板000内。如此，可以进一步的提高形成配向膜的配向液扩散的均匀性，进而避免了因配向液扩散不均匀引起的亮度不均的不良问题，提高了该显示装置的显示效果。
在本申请中，阵列基板000具有多个过孔V1，公共电极层300通过至少一个过孔V1与搭接电极401搭接，过孔V1在衬底100上的正投影与搭接电极401在衬底100上的正投影至少部分交叠。
在一种可能的实现方式中，过孔V1在衬底100上的正投影位于搭接电极401在衬底100上的正投影内。
在另一种可能的实现方式中，请参考图9，图9是图7示出的阵列基板在B-B’处的截面图。过孔V1在衬底100上的正投影中的一部分位于搭接电极401在衬底100上的正投影内，另一部分位于搭接电极401在衬底100上的正投影外。也即是，过孔V1在衬底100上的正投影与搭接电极401在衬底100上的正投影仅部分交叠。
在这种情况下，过孔V1中与搭接电极401交叠的部分的深度较小，过孔V1中未与搭接电极401交叠的部分的深度较大。也即是，过孔V1属于局部区域深度较深，局部区域深度较浅的深浅孔结构。这种深浅孔结构有利于配向液的扩散，进而可以进一步的提高用于形成配向膜的配向液扩散的均匀性，避免了因配向液扩散不均匀引起的亮度不均的不良问题，提高了显示装置的显示效果。
请参考图10，图10是图8示出的阵列基板在N-N’处的截面图。其中，辅助电极402未与公共电极层300搭接，无需设置用于让公共电极层300与公共信号线400搭接的过孔V1。这样，可以有效的减少阵列基板000内设置的用于让公共电极层300与公共信号线400搭接的过孔V1的数量。
请继续参考图6至图8，像素电极层200相对于公共电极层300更靠近衬底100，阵列基板000中的像素电极层200包括：位于子像素区域00a内的像素电极201，像素电极201在衬底100上的正投影与电极结构400a在衬底100上的正投影不重合。
在这种情况下，当电极结构400a为搭接电极401时，搭接电极401需要穿过像素电极层200之后，与公共电极300电连接，而当像素电极201在衬底100上的正投影与电极结构400a在衬底100上的正投影不重合时，能够避免搭接电 极401与公共电极300电连接时，与像素电极201发生短路。
需要说明的是，在其他可能的实现方式中，公共电极层300也可以相对于像素电极层200更靠近衬底100，在此种情况下，公共电极层300可以直接通过过孔V1与搭接电极401电连接，而不必穿过像素电极层200。这样，像素电极层200在衬底100上的正投影与电极结构400a在衬底100上的正投影可以重合。
为了更清楚的了解子像素区域内的像素电极的结构。请参考图11，图11是图5示出的一个子像素区域内的阵列基板的结构示意图。子像素区域00a中的像素电极201具有镂空结构201a。在同一个子像素区域00a内，电极结构400a在衬底100上的正投影位于镂空结构201a在衬底100上的正投影内。
在这种情况下，当电极结构400a为搭接电极401时，搭接电极401需要穿过像素电极层200之后，与公共电极300电连接。而当像素电极层200中的像素电极201具有镂空结构201a时，能够避免搭接电极401与公共电极300电连接时，与像素电极201发生短路。
需要说明的是，各个像素区域00a内，电极结构400a与像素电极201之间会形成耦合电容，且该耦合电容的大小与电极结构400a的外边界与像素电极201的外边界之间的距离相关。
在本申请实施例中，如图5所示，各个子像素区域00a内的电极结构400a在衬底100上的正投影的外边界与镂空结构201a在衬底100上的正投影的外边界之间的距离相等。这样，可以保证电极结构400a与像素电极201之间形成的耦合电容相近，而存储电容的大小与耦合电容的大小相关，并且，当电极结构400a在衬底100上的正投影的外边界与镂空结构201a在衬底100上的正投影的外边界之间的距离相等时，像素电极201与公共电极线400交叠的部分的面积也相同，如此，可以确保各个像素区域00a内电极结构400a与像素电极201之间的存储电容相同。
请继续参考图11，该阵列基板000还包括：位于衬底100上的多个晶体管900，多个晶体管900与多个像素电极201一一对应。为了更清楚的了解阵列基板000的结构，请参考图12，图12是图11示出的阵列基板在M-M’处的膜层示意图。其中，一条栅线800与同一行晶体管900中的各个晶体管900的栅极904电连接，栅线800与公共信号线400同层设置且材料相同，栅线800的延伸方向与公共信号线400的延伸方向平行；一条数据线700与同一列晶体管900中 的各个晶体管900的第一极901电连接，晶体管900的第二极902与对应的像素电极201电连接。
可选的，请参考图13，图13是图11示出的阵列基板在E处的局部放大图。其中，第一极901为晶体管900的源极，第二极902为晶体管900的漏极。晶体管900包括：栅极904、源极901、漏极902和有源层903。
请继续参考图12，阵列基板000还包括：位于多个晶体管900背离衬底100一侧的第一绝缘层500，以及位于像素电极层200与公共电极层300之间的第二绝缘层600；其中，像素电极层200位于第一绝缘层500背离衬底100的一侧，且像素电极层200相对于公共电极层300更靠近衬底100。其中，通过在像素电极层200与公共电极层300之间设置第二绝缘层600，使得公共电极层300与像素电极层200的交叠部分可以形成液晶电容。
在其他的可能的实现方式中，请参考图14，图14是图11示出的阵列基板在M-M’处的另一种膜层示意图。晶体管900与像素电极201之间未设置第一绝缘层500，晶体管900的第二极902与对应的像素电极201直接搭接在一起。如此，可以减少工艺步骤，降低生产成本。
需要说明的是，对于与同一条数据线700电连接的一列晶体管900中任意两个相邻的晶体管900，一个晶体管900位于数据线700的一侧，另一个晶体管900位于数据线700的另一侧。其中，列反转前和列反转后的各个子像素区域00a内的像素电极201所加载的像素电压的极性相反，且，列反转前和列反转后，任意相邻的两个子像素区域00a内的像素电极201所加载的像素电压的极性均相反。
请参考图15，图15是图5示出的阵列基板的公共电极层的结构示意图。阵列基板000中的公共电极层300具有多个狭缝301。如此，各个像素区域00a内的像素电极201与具有多个狭缝301的公共电极层300之间可以形成平行于衬底100方向的电场，通过该电场可以驱动液晶沿平行于衬底100方向偏转。
综上所述，本申请实施例提供的阵列基板，包括：衬底，以及位于衬底上的像素电极层、公共电极层和多条公共信号线。公共电极线中同时设置有：与公共电极层搭接的搭接电极，以及未与公共电极层搭接的辅助电极。这样，可以有效的减少阵列基板内设置的用于让公共电极层与公共信号线搭接的过孔的数量，以保证后续在阵列基板上形成配向膜的过程中，用于形成配向膜的配向 液出现扩散不均匀的概率较低，进而可以保证后续将这个阵列基板集成在显示装置内后，显示装置出现亮度不均的概率较低。并且，通过在公共电极线中同时设置搭接电极和辅助电极，可以保证搭接电极所在的子像素区域内的存储电容的大小，与辅助电极所在的子像素区域内的存储电容的大小近似相同。进而可以保证搭接电极所在的子像素区域内的像素电极所对应的△Vp的数值，与辅助电极所在的子像素区域内像素电极所对应的△Vp的数值近似相同。为此，当本申请中的阵列基板在集成在显示装置内，且显示装置以列反转的方式显示画面时，显示装置所显示的画面出现画面闪烁和抖动等不良现象的概率较低，有效的提高了显示装置的显示效果。
本申请实施例还提供了一种显示装置，如图16所示，图16是本申请实施例提供的一种显示装置的膜层结构示意图。该显示装置可以包括：彩膜基板001、液晶层002和上述任意一种阵列基板000；阵列基板000和彩膜基板001相对设置，液晶层002位于阵列基板000和彩膜基板001之间。在本申请实施例中，该显示装置可以为：液晶面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间惟一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
在本申请中，术语“第一”和“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。术语“多个”指两个或两个以上，除非另有明确的限定。
以上所述仅为本申请的可选的实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (15)

  1. 一种阵列基板，其特征在于，所述阵列基板具有多个子像素区域，所述阵列基板包括：
    衬底；
    位于所述衬底上的像素电极层和公共电极层；
    以及，位于所述衬底上的多条公共信号线，所述公共信号线与所述像素电极层绝缘设置，且与所述公共电极层电连接，所述公共信号线在所述衬底上的正投影与所述像素电极层在所述衬底上的正投影存在交叠区域；
    其中，所述公共信号线具有多个电极结构，不同的所述电极结构位于不同的所述子像素区域内，所述多个电极结构包括：与所述公共电极层搭接的搭接电极，以及未与所述公共电极层搭接的辅助电极。
  2. 根据权利要求1所述的阵列基板，其特征在于，所述辅助电极在所述衬底上的正投影与所述搭接电极在所述衬底上的正投影的形状和面积均相同。
  3. 根据权利要求1所述的阵列基板，其特征在于，所述多个子像素区域包括：至少两种颜色的子像素区域，所述多个电极结构与同一种颜色子像素区域内的多个子像素区域一一对应，所述电极结构位于对应的子像素区域内。
  4. 根据权利要求3所述的阵列基板，其特征在于，在所述同一种颜色子像素区域中，对于任意两个相邻的所述子像素区域，一个所述像素区域内分布有所述搭接电极，另一个所述像素区域内分布有所述辅助电极。
  5. 根据权利要求3所述的阵列基板，其特征在于，分布有所述电极结构的子像素区域为蓝色子像素区域。
  6. 根据权利要求1所述的阵列基板，其特征在于，所述阵列基板具有多个过孔，所述公共电极层通过至少一个所述过孔与所述搭接电极搭接，所述过孔在所述衬底上的正投影与所述搭接电极在所述衬底上的正投影至少部分交叠。
  7. 根据权利要求6所述的阵列基板，其特征在于，所述过孔在所述衬底上的正投影中的一部分位于所述搭接电极在所述衬底上的正投影内，另一部分位于所述搭接电极在所述衬底上的正投影外。
  8. 根据权利要求1至5任一所述的阵列基板，其特征在于，所述像素电极层相对于所述公共电极层更靠近所述衬底，所述像素电极层包括：位于所述子像素区域内的像素电极，所述像素电极在所述衬底上的正投影与所述电极结构在所述衬底上的正投影不重合。
  9. 根据权利要求8所述的阵列基板，其特征在于，所述像素电极具有镂空结构，在同一个所述子像素区域内，所述电极结构在所述衬底上的正投影位于所述镂空结构在所述衬底上的正投影内。
  10. 根据权利要求9所述的阵列基板，其特征在于，各个所述子像素区域内的所述电极结构在所述衬底上的正投影的外边界与所述镂空结构在所述衬底上的正投影的外边界之间的距离相等。
  11. 根据权利要求8所述的阵列基板，其特征在于，所述阵列基板还包括：多条数据线、多条栅线和多个晶体管，所述多个晶体管与多个所述像素电极一一对应；
    其中，一条所述栅线与同一行所述晶体管中的各个晶体管的栅极电连接，所述栅线与所述公共信号线同层设置且材料相同，所述栅线的延伸方向与所述公共信号线的延伸方向平行；
    一条所述数据线与同一列所述晶体管中的各个晶体管的第一极电连接，所述晶体管的第二极与对应的像素电极电连接。
  12. 根据权利要求11所述的阵列基板，其特征在于，对于与同一条所述数据线电连接的一列晶体管中任意两个相邻的晶体管，一个所述晶体管位于所述数据线的一侧，另一个所述晶体管位于所述数据线的另一侧。
  13. 根据权利要求11所述的阵列基板，其特征在于，所述阵列基板还包括：位于所述多个晶体管背离所述衬底一侧的第一绝缘层，以及位于所述像素电极层与所述公共电极层之间的第二绝缘层；
    其中，所述像素电极层位于所述第一绝缘层背离所述衬底的一侧。
  14. 根据权利要求9至13任一所述的阵列基板，其特征在于，所述公共电极层具有多个狭缝。
  15. 一种显示装置，其特征在于，包括：彩膜基板、液晶层和权利要求1至14任一所述的阵列基板；
    所述阵列基板和所述彩膜基板相对设置，所述液晶层位于所述阵列基板和所述彩膜基板之间。
PCT/CN2023/091446 2022-05-25 2023-04-28 阵列基板及显示装置 WO2023226687A1 (zh)

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