WO2019051971A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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Publication number
WO2019051971A1
WO2019051971A1 PCT/CN2017/110002 CN2017110002W WO2019051971A1 WO 2019051971 A1 WO2019051971 A1 WO 2019051971A1 CN 2017110002 W CN2017110002 W CN 2017110002W WO 2019051971 A1 WO2019051971 A1 WO 2019051971A1
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WIPO (PCT)
Prior art keywords
pixel electrode
sub
electrode
conductive sheet
array substrate
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PCT/CN2017/110002
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English (en)
French (fr)
Inventor
安立扬
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深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US15/736,315 priority Critical patent/US10394097B2/en
Publication of WO2019051971A1 publication Critical patent/WO2019051971A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a display panel.
  • the liquid crystal display panel industry has undergone several decades of development.
  • the vertical alignment (VA) display mode has become a film for large-sized televisions (TVs) with its wide viewing angle, high contrast and no friction.
  • the pixel structure of a liquid crystal display generally consists of a thin film transistor device, several capacitors, and a signal line.
  • the function of the storage capacitor (Cst) is to reduce the pixel's trip voltage ⁇ V and maintain the voltage stability across the liquid crystal.
  • the invention provides an array substrate and a display panel with large storage capacitors.
  • an array substrate having a plurality of pixel units arranged in a matrix, each of the pixel units being provided with a common electrode, a first insulating layer, a sub-pixel electrode, and a second insulating layer which are sequentially stacked.
  • a conductive sheet the conductive sheet is electrically connected to the common electrode, a first front facing area is formed between the common electrode and the sub-pixel electrode, and a second positive is formed between the conductive sheet and the sub-pixel electrode The area is such that a storage capacitor is formed between the common electrode and the sub-pixel electrode and between the conductive sheet and the sub-pixel electrode.
  • the first insulating layer is provided with a first through hole to expose a portion of the common electrode, the sub-pixel electrode is spaced apart from the first through hole, and the second insulating layer is disposed to communicate with the first through hole a second through hole, the conductive sheet being connected to the common electrode through the second through hole and the first through hole.
  • Each of the pixel units has a thin film transistor, a source and a drain of the thin film transistor are disposed in the same layer as the sub-pixel electrode, and the drain is connected to the sub-pixel electrode.
  • the gate of the thin film transistor is disposed in the same layer as the common electrode.
  • Each of the pixel units has a light-transmitting region and a light-shielding region disposed around the light-transmitting region, the sub-pixel electrode is located in the light-shielding region, and the array substrate further includes a light-transmitting region.
  • a main pixel electrode electrically connected to the sub-pixel electrode.
  • the second insulating layer is provided with a third via hole to expose a portion of the sub-pixel electrode, and the main pixel electrode is connected to the sub-pixel electrode through the third via hole.
  • the conductive sheet is disposed in the same layer as the main pixel electrode, and the conductive sheet and the main pixel electrode are insulated from each other.
  • the material of the conductive sheet is the same as the material of the main pixel electrode.
  • the orthographic projection of the common electrode on the main pixel electrode is located in a peripheral region of the main pixel electrode.
  • a display panel including the above array substrate.
  • the sub-pixel electrode serves as one electrode sheet of the storage capacitor, and the conductive sheet and the common electrode collectively serve as another electrode sheet of the storage capacitor.
  • the prior art at least increases the second facing area, so the pixel unit significantly increases the capacitance value of the storage capacitor, and the capacitance values of the storage capacitor of the array substrate and the display panel are compared. Large, the uniformity of the display panel during display is improved, and the jump voltage can be effectively reduced to avoid causing display such as image sticking. abnormal.
  • FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural view of an array substrate of the display panel shown in FIG. 1.
  • FIG. 3 is a schematic structural view of a pixel unit of the array substrate shown in FIG. 2.
  • FIG. 4 is an enlarged schematic view showing the structure of A of the pixel unit shown in FIG.
  • Figure 5 is a schematic view of the structure taken along line B-B of Figure 4.
  • Figure 6 is a schematic view of the structure taken along line C-C of Figure 4.
  • FIG. 7 is another schematic diagram of the pixel unit shown in FIG.
  • Figure 8 is a schematic illustration of the structure along D-D of Figure 4.
  • FIG. 9 is a schematic structural view of another pixel unit of the array substrate shown in FIG. 2.
  • FIG. 9 is a schematic structural view of another pixel unit of the array substrate shown in FIG. 2.
  • an embodiment of the present invention provides a display panel 100 , which includes an Array substrate 1 .
  • the display panel 100 can be applied to various display devices such as a mobile phone, a television, a computer, and the like.
  • the display panel 100 further includes a color filter (CF) substrate 2 disposed opposite to the array substrate 1 and a liquid crystal (LC) between the array substrate 1 and the color filter substrate 2.
  • CF color filter
  • LC liquid crystal
  • the array substrate 1 has a plurality of pixel units 10 arranged in a matrix.
  • the array substrate 1 includes a substrate 11 and a plurality of gate lines 12 and a plurality of data lines 13 formed on the substrate 11, the plurality of gate lines 12 and the plurality of data lines 13 crossing each other The plurality of pixel units 10 are surrounded.
  • Each of the pixel units 10 is provided with a common electrode 14, a first insulating layer 15, a sub-pixel electrode 16, a second insulating layer 17, and a conductive sheet 18 which are sequentially stacked on the substrate 11.
  • the first insulating layer 15 insulates the common electrode 14 and the sub-pixel electrode 16 from each other.
  • the second insulating layer 17 insulates the sub-pixel electrode 16 and the conductive sheet 18 from each other.
  • the conductive sheet 18 is electrically connected to the common electrode 14 such that the conductive sheet 18 and the common electrode 14 have the same voltage.
  • a first facing area S1 is formed between the common electrode 14 and the sub-pixel electrode 16, and a second facing area S2 is formed between the conductive sheet 18 and the sub-pixel electrode 16 to make the common electrode
  • a storage capacitor is formed between 14 and the sub-pixel electrode 16 and between the conductive sheet 18 and the sub-pixel electrode 16.
  • the sub-pixel electrode 16 serves as one electrode sheet of the storage capacitor, and the conductive sheet 18 and the common electrode 14 collectively serve as another electrode sheet of the storage capacitor.
  • a first facing area S1 is formed between the common electrode 14 and the sub-pixel electrode 16, and a second facing area S2 is formed between the conductive sheet 18 and the sub-pixel electrode 16, and the total capacitance of the storage capacitor is
  • the facing area of the storage capacitor of the prior art is the facing area of the common electrode and the sub-pixel electrode
  • the second facing area S2 is increased, so the pixel unit 10 is significantly increased.
  • the capacitance value of the storage capacitor is increased, and the capacitance values of the storage capacitors of the array substrate 1 and the display panel 100 are relatively large, so that the uniformity of the display panel 100 during display is improved and can be effective. Reduce the jump voltage to avoid causing abnormalities such as image sticking.
  • the first insulating layer 15 and the second insulating layer 17 are made of the same material to reduce cost.
  • the first insulating layer 15 and the second insulating layer 17 may also adopt different materials.
  • the spacing between the common electrode 14 and the sub-pixel electrode 16 may also be reduced, and/or The spacing between the sub-pixel electrode 16 and the conductive sheet 18 is reduced to increase the capacitance value of the storage capacitor.
  • the capacitance value of the storage capacitor can be increased by reducing the thickness of the first insulating layer 15 and/or the second insulating layer 17.
  • the first insulating layer 15 is provided with a first through hole 151 to expose a portion of the common electrode 14 .
  • the sub-pixel electrode 16 is spaced apart from the first via hole 151, that is, there is no overlapping portion between the sub-pixel electrode 16 and the first via hole 151, and the sub-pixel electrode 16 bypasses the The first through hole 151 is provided.
  • the second insulating layer 17 is provided with a second through hole 171 that communicates with the first through hole 151 , and the second through hole 171 is disposed opposite to the first through hole 151 .
  • the conductive sheet 18 is connected to the common electrode 14 through the second through hole 171 and the first through hole 151 such that the conductive sheet 18 and the common electrode 14 have the same potential to become the The same electrode piece of the storage capacitor.
  • each of the pixel units 10 has a thin film transistor 20 .
  • the source 21 and the drain 22 of the thin film transistor 20 are disposed in the same layer as the sub-pixel electrode 16, and the drain 22 is connected to the sub-pixel electrode 16.
  • the source 21 is connected to the data line 13.
  • the gate 23 of the thin film transistor 20 is disposed in the same layer as the common electrode 14 . Place The gate 23 is connected to the gate line 12.
  • each of the pixel units 10 has a light transmitting region 101 (also referred to as an opening region) and a light shielding region disposed around the light transmitting region 101 . 102.
  • the light shielding region 102 may be blocked by a metal electrode that is opaque (such as the gate line 12, the data line 13, the common electrode 14, etc.), or may be blocked by a black matrix (BM) on the color filter substrate 2.
  • BM black matrix
  • the sub-pixel electrode 16 is located in the light shielding region 102.
  • the array substrate 1 further includes a main pixel electrode 19 located in the light transmissive region 101, and the main pixel electrode 19 is electrically connected to the sub-pixel electrode 16.
  • the conductive sheet 18 is disposed in the light shielding region 102.
  • the conductive sheet 18 is disposed opposite to the sub-pixel electrode 16 such that the second facing area S2 is as large as possible.
  • the conductive sheet 18 is disposed in the light shielding region 102, the array substrate 1 and the display panel 100 can effectively increase the capacitance of the storage capacitor without losing the aperture ratio. value.
  • the common electrode 14 is made of a metal electrode and is made of an opaque material.
  • the orthographic projection of the common electrode 14 on the substrate 11 covers the orthographic projection of the sub-pixel electrode 16 on the substrate 11. At this time, the area of the sub-pixel electrode 16 is the first facing area S1.
  • the second insulating layer 17 is provided with a third via hole 172 to expose a portion of the sub-pixel electrode 16.
  • the main pixel electrode 19 is connected to the sub-pixel electrode 16 through the third via hole 172.
  • the conductive sheet 18 is disposed in the same layer as the main pixel electrode 19, and the conductive sheet 18 and the main pixel electrode 19 are insulated from each other.
  • the material of the conductive sheet 18 is the same as the material of the main pixel electrode 19. At this time, the conductive sheet 18 and the main pixel electrode 19 can be completed by the same etching process, which simplifies the preparation process of the array substrate 1 and reduces the cost of the array substrate 1 and the display panel 100.
  • the conductive sheet 18 and the main pixel electrode 19 may be made of an indium tin oxide (ITO) material or other transparent conductive material.
  • ITO indium tin oxide
  • the material of the conductive sheet 18 may be different from the main pixel electrode 19, and the material of the conductive sheet 18 and the material of the main pixel electrode 19 may be specifically set according to requirements.
  • the orthographic projection of the common electrode 14 on the main pixel electrode 19 is located in a peripheral region of the main pixel electrode 19.
  • the main A central area of the pixel electrode 19 is surrounded by a peripheral area of the main pixel electrode 19, and an area of a central area of the main pixel electrode 19 is much larger than an area of a peripheral area of the main pixel electrode 19, the main pixel electrode 19
  • the central region is located in the light transmissive region 101, and a peripheral region of the main pixel electrode 19 overlaps with the common electrode 14 and is located in the light shielding region 102.
  • the wiring of the common electrode 14 is not disposed in the light transmitting region 101.
  • the traces of the common electrodes are often disposed in the transparent region of the pixel unit, and the traces are perpendicular to each other, and it is easy to form an oblique angle of 45° in the intersection region after the etching process.
  • the edge thereby affecting the light transmission of the liquid crystal molecules in the liquid crystal layer, causes the display panel to leak light when displayed in a dark state, resulting in low contrast of the display panel.
  • the trace of the common electrode 14 is not disposed in the transparent region 101, thereby avoiding a dark state light leakage phenomenon caused by a poor etching process, so that the display panel 100 has a better display effect.
  • a single trace 141 may also be disposed in the transparent region 101, for example, a strip parallel to the data line 13 (as shown in FIG. 9) or the gate line 12 is disposed. line. At this time, since a single trace does not form an intersection region in the transparent region 101, dark light leakage phenomenon due to poor etching process can be avoided, so that the display panel 100 has a better display effect. .

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Abstract

一种阵列基板及显示面板，阵列基板具有呈矩阵排布的多个像素单元（10），每个像素单元（10）均设有依次层叠设置的公共电极（14）、第一绝缘层（15）、次像素电极（16）、第二绝缘层（17）以及导电片（18），导电片（18）电连接公共电极（14），公共电极（14）与次像素电极（16）之间形成第一正对面积（S1），导电片（18）与次像素电极（16）之间形成第二正对面积（S2），以使公共电极（14）与次像素电极（16）之间及导电片（18）与次像素电极（16）之间共同形成存储电容。阵列基板的存储电容较大。

Description

阵列基板及显示面板
本发明要求2017年9月18日递交的发明名称为“阵列基板及显示面板”的申请号201710848747.6的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及显示面板。
背景技术
液晶显示面板行业已经历了数十年的发展，垂直配向(vertical alignment，VA)显示模式以其宽视野角、高对比度和无须摩擦配相等优势，成为大尺寸电视机(Television，TV)用薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，TFT-LCD)的常见显示模式。
液晶显示器像素(pixel)结构一般由一个薄膜晶体管器件、几个电容以及信号线构成，其中存储电容(Cst)的作用在于降低像素的跳变电压ΔV，维持液晶两端的电压稳定。通常情况下，跳变电压ΔV＝(Voff–Von)×Cgs/Ctotal，其中Voff及Von是扫描线的关闭电压和开启电压，Ctotal为像素电极的其他电容，一般包含三个电容，Ctotal＝Cgs(薄膜晶体管的寄生电容)+Cst(存储电容)+Clc(液晶电容)。从上述公式中可以看出，存储电容越大跳变电压的数值越小，如何增加存储电容以降低跳变电压为业内难题。
发明内容
本发明提供一种存储电容较大的阵列基板及显示面板。
本发明实施例采用如下技术方案：
一方面，提供一种阵列基板，具有呈矩阵排布的多个像素单元，每个所述像素单元均设有依次层叠设置的公共电极、第一绝缘层、次像素电极、第二绝缘层以及导电片，所述导电片电连接所述公共电极，所述公共电极与所述次像素电极之间形成第一正对面积，所述导电片与所述次像素电极之间形成第二正 对面积，以使所述公共电极与次像素电极之间及所述导电片与所述次像素电极之间共同形成存储电容。
其中，所述第一绝缘层设第一通孔以露出部分所述公共电极，所述次像素电极与所述第一通孔间隔设置，所述第二绝缘层设连通所述第一通孔的第二通孔，所述导电片通过所述第二通孔和所述第一通孔连接至所述公共电极。
其中，每个所述像素单元均具有薄膜晶体管，所述薄膜晶体管的源极和漏极与所述次像素电极同层设置，且所述漏极连接所述次像素电极。
其中，所述薄膜晶体管的栅极与所述公共电极同层设置。
其中，每个所述像素单元均具有透光区和设于所述透光区周边的遮光区，所述次像素电极位于所述遮光区，所述阵列基板还包括位于所述透光区的主像素电极，所述主像素电极电连接所述次像素电极。
其中，所述第二绝缘层设第三通孔以露出部分所述次像素电极，所述主像素电极通过所述第三通孔连接所述次像素电极。
其中，所述导电片与所述主像素电极同层设置，所述导电片与所述主像素电极之间彼此绝缘。
其中，所述导电片的材料与所述主像素电极的材料相同。
其中，所述公共电极在所述主像素电极上的正投影位于所述主像素电极的周边区域。
另一方面，还提供一种显示面板，包括上述阵列基板。
在本发明实施例所述的阵列基板中，所述次像素电极作为所述存储电容的一个电极片，所述导电片和所述公共电极共同作为所述存储电容的另一个电极片，所述公共电极与所述次像素电极之间形成第一正对面积，所述导电片与所述次像素电极之间形成第二正对面积，则所述存储电容的总正对面积为所述第一正对面积和所述第二正对面积的和。由于所述存储电容的电容值与其两个电极片的正对面积成正比，而本实施例所述像素单元通过增设所述导电片，使得所述存储电容的所述总正对面积相较于现有技术至少增加了所述第二正对面积，因此所述像素单元显著地增大了所述存储电容的电容值，所述阵列基板和所述显示面板的所述存储电容的电容值较大，使得所述显示面板在显示时的均一性变好，并能有效的降低跳变电压，避免引起残像(Image sticking)等显示 异常。
附图说明
为了更清楚地说明本发明的技术方案，下面将对实施方式中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以如这些附图获得其他的附图。
图1是本发明实施例提供的一种显示面板的结构示意图。
图2是图1所示显示面板的阵列基板的结构示意图。
图3是图2所示阵列基板的像素单元的结构示意图。
图4是图3所示像素单元的A处结构的放大示意图。
图5是图4中沿B-B处结构的示意图。
图6是图4中沿C-C处结构的示意图。
图7是图3所示像素单元的另一示意图。
图8是图4中沿D-D处结构的示意图。
图9是图2所示阵列基板的另一种像素单元的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
此外，以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明中所提到的方向用语，例如，“上”、“下”、“前”、“后”、“左”、“右”、“内”、“外”、“侧面”等，仅是参考附加图式的方向，因此，使用的方向用语是为了更好、更清楚地说明及理解本发明，而不是指示或暗指所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安 装”、“相连”、“连接”、“设置在……上”应做广义理解，例如，可以是固定连接，也可以是可拆卸地连接，或者一体地连接；可以是机械连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
此外，在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。若本说明书中出现“工序”的用语，其不仅是指独立的工序，在与其它工序无法明确区别时，只要能实现该工序所预期的作用则也包括在本用语中。另外，本说明书中用“～”表示的数值范围是指将“～”前后记载的数值分别作为最小值及最大值包括在内的范围。在附图中，结构相似或相同的单元用相同的标号表示。
请一并参阅1至图6，本发明实施例提供一种显示面板100，所述显示面板100包括阵列(Array)基板1。所述显示面板100可应用于各种显示设备中，例如手机、电视、电脑等。所述显示面板100还包括与所述阵列基板1相对设置的彩膜(Color Filter，CF)基板2和位于所述阵列基板1与所述彩膜基板2之间的液晶(Liquid Crystal，LC)层3。
所述阵列基板1具有呈矩阵排布的多个像素单元10。所述阵列基板1包括衬底11及形成在所述衬底11上的多条栅极线12和多条数据线13，所述多条栅极线12和所述多条数据线13彼此交叉以围设出所述多个像素单元10。
每个所述像素单元10均设有依次层叠设置在所述衬底11上的公共电极14、第一绝缘层15、次像素电极16、第二绝缘层17以及导电片18。所述第一绝缘层15使得所述公共电极14与所述次像素电极16彼此绝缘。所述第二绝缘层17使得所述次像素电极16与所述导电片18彼此绝缘。所述导电片18电连接所述公共电极14，使得所述导电片18与所述公共电极14的电压一致。所述公共电极14与所述次像素电极16之间形成第一正对面积S1，所述导电片18与所述次像素电极16之间形成第二正对面积S2，以使所述公共电极14与次像素电极16之间及所述导电片18与所述次像素电极16之间共同形成存储电容。
在本实施例中，所述次像素电极16作为所述存储电容的一个电极片，所述导电片18和所述公共电极14共同作为所述存储电容的另一个电极片，所述 公共电极14与所述次像素电极16之间形成第一正对面积S1，所述导电片18与所述次像素电极16之间形成第二正对面积S2，则所述存储电容的总正对面积S为所述第一正对面积S1和所述第二正对面积S2的和(S＝S1+S2)。由于所述存储电容的电容值与其两个电极片的正对面积成正比，而本实施例所述像素单元10通过增设所述导电片18，使得所述存储电容的所述总正对面积S相较于现有技术(现有技术的存储电容的正对面积为公共电极与次像素电极的正对面积)至少增加了所述第二正对面积S2，因此所述像素单元10显著地增大了所述存储电容的电容值，所述阵列基板1和所述显示面板100的所述存储电容的电容值较大，使得所述显示面板100在显示时的均一性变好，并能有效的降低跳变电压，避免引起残像(Image sticking)等显示异常。
可选的，所述第一绝缘层15和所述第二绝缘层17采用相同的材料，以降低成本。当然，在其他实施方式中，所述第一绝缘层15和所述第二绝缘层17也可采用不同的材料。
可选的，由于所述存储电容的电容值与其两个电极片之间的间距成反比，因此也可以通过减小所述公共电极14与所述次像素电极16之间的间距，和/或，减小所述次像素电极16与所述导电片18之间的间距，来增加所述存储电容的电容值。换言之，可通过减小所述第一绝缘层15和/或所述第二绝缘层17的厚度来增加所述存储电容的电容值。
可选的，所述第一绝缘层15设第一通孔151以露出部分所述公共电极14。所述次像素电极16与所述第一通孔151间隔设置，也即所述次像素电极16与所述第一通孔151之间不存在重叠部分，所述次像素电极16绕开所述第一通孔151设置。所述第二绝缘层17设连通所述第一通孔151的第二通孔171，所述第二通孔171正对所述第一通孔151设置。所述导电片18通过所述第二通孔171和所述第一通孔151连接至所述公共电极14，使得所述导电片18与所述公共电极14具有相同的电位，以成为所述存储电容的同一电极片。
可选的，每个所述像素单元10均具有薄膜晶体管20。所述薄膜晶体管20的源极21和漏极22与所述次像素电极16同层设置，且所述漏极22连接所述次像素电极16。所述源极21连接所述数据线13。
可选的，所述薄膜晶体管20的栅极23与所述公共电极14同层设置。所 述栅极23连接所述栅极线12。
请一并参阅图3至图8，作为一种可选实施例，每个所述像素单元10均具有透光区101(也称开口区域)和设于所述透光区101周边的遮光区102。所述遮光区102可由不透光的金属电极(例如栅极线12、数据线13、公共电极14等)所遮挡，也可以由彩膜基板2上的黑色矩阵(Black Matrix，BM)所遮挡。所述次像素电极16位于所述遮光区102。所述阵列基板1还包括位于所述透光区101的主像素电极19，所述主像素电极19电连接所述次像素电极16。
所述导电片18设于所述遮光区102。所述导电片18正对所述次像素电极16设置，以使所述第二正对面积S2尽可能大。在本申请中，由于所述导电片18设于所述遮光区102，因此所述阵列基板1和所述显示面板100能够在不损失开口率的情况下，有效地增加所述存储电容的电容值。
所述公共电极14采用金属电极，采用不透明材料。所述公共电极14在所述衬底11上的正投影覆盖所述次像素电极16在所述衬底11上的正投影。此时，所述次像素电极16的面积即为所述第一正对面积S1。
可选的，所述第二绝缘层17设第三通孔172以露出部分所述次像素电极16。所述主像素电极19通过所述第三通孔172连接所述次像素电极16。
可选的，所述导电片18与所述主像素电极19同层设置，所述导电片18与所述主像素电极19之间彼此绝缘。
所述导电片18的材料与所述主像素电极19的材料相同。此时，所述导电片18和所述主像素电极19可通过同一道蚀刻工艺完成，简化了所述阵列基板1的制备工艺，降低了所述阵列基板1和所述显示面板100的成本。
所述导电片18和所述主像素电极19可采用氧化铟锡(Indium tin oxide，ITO)材料，或其他透明导电材料。
当然，在其他实施方式中，所述导电片18的材料也可与所述主像素电极19不同，可以依据需求具体设置所述导电片18的材料和所述主像素电极19的材料。
请一并参阅图3、图7以及图9，作为一种可选实施例，所述公共电极14在所述主像素电极19上的正投影位于所述主像素电极19的周边区域。所述主 像素电极19的中心区域被所述主像素电极19的周边区域环绕，所述主像素电极19的中心区域的面积远大于所述主像素电极19的周边区域的面积，所述主像素电极19的中心区域位于所述透光区101内，所述主像素电极19的周边区域与所述公共电极14重叠、位于所述遮光区102内。此时，所述透光区101内不设所述公共电极14的走线。
现有技术中，经常在像素单元的透光区内设置公共电极的走线，且该走线为彼此垂直的交叉走线，则容易在蚀刻制程后，在交叉区域形成带有45°的斜边，从而影响液晶层内液晶分子的光线传输，使得显示面板在暗态显示时会有漏光现象，造成显示面板的对比度低。
本实施例通过不在所述透光区101内设置所述公共电极14的走线，从而避免因蚀刻制程的不良而导致出现暗态漏光现象，使得所述显示面板100具有较佳的显示效果。
当然，在其他实施方式中，也可以在所述透光区101内设置单一走线141，例如设置一条平行于所述数据线13(如图9所示)或所述栅极线12的走线。此时，由于单一走线不会在所述透光区101内形成交叉区域，因此也可避免因蚀刻制程的不良而导致出现暗态漏光现象，使得所述显示面板100具有较佳的显示效果。
以上对本发明实施例进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (20)

  1. 一种阵列基板，其中，具有呈矩阵排布的多个像素单元，每个所述像素单元均设有依次层叠设置的公共电极、第一绝缘层、次像素电极、第二绝缘层以及导电片，所述导电片电连接所述公共电极，所述公共电极与所述次像素电极之间形成第一正对面积，所述导电片与所述次像素电极之间形成第二正对面积，以使所述公共电极与次像素电极之间及所述导电片与所述次像素电极之间共同形成存储电容。
  2. 如权利要求1所述的阵列基板，其中，所述第一绝缘层设第一通孔以露出部分所述公共电极，所述次像素电极与所述第一通孔间隔设置，所述第二绝缘层设连通所述第一通孔的第二通孔，所述导电片通过所述第二通孔和所述第一通孔连接至所述公共电极。
  3. 如权利要求1所述的阵列基板，其中，每个所述像素单元均具有薄膜晶体管，所述薄膜晶体管的源极和漏极与所述次像素电极同层设置，且所述漏极连接所述次像素电极。
  4. 如权利要求3所述的阵列基板，其中，所述薄膜晶体管的栅极与所述公共电极同层设置。
  5. 如权利要求1所述的阵列基板，其中，每个所述像素单元均具有透光区和设于所述透光区周边的遮光区，所述次像素电极位于所述遮光区，所述阵列基板还包括位于所述透光区的主像素电极，所述主像素电极电连接所述次像素电极。
  6. 如权利要求2所述的阵列基板，其中，每个所述像素单元均具有透光区和设于所述透光区周边的遮光区，所述次像素电极位于所述遮光区，所述阵列基板还包括位于所述透光区的主像素电极，所述主像素电极电连接所述次像素电极。
  7. 如权利要求5所述的阵列基板，其中，所述第二绝缘层设第三通孔以露出部分所述次像素电极，所述主像素电极通过所述第三通孔连接所述次像素电极。
  8. 如权利要求5所述的阵列基板，其中，所述导电片与所述主像素电极同层设置，所述导电片与所述主像素电极之间彼此绝缘。
  9. 如权利要求8所述的阵列基板，其中，所述导电片的材料与所述主像素电极的材料相同。
  10. 如权利要求5所述的阵列基板，其中，所述公共电极在所述主像素电极上的正投影位于所述主像素电极的周边区域。
  11. 一种显示面板，其中，包括阵列基板，所述阵列基板具有呈矩阵排布的多个像素单元，每个所述像素单元均设有依次层叠设置的公共电极、第一绝缘层、次像素电极、第二绝缘层以及导电片，所述导电片电连接所述公共电极，所述公共电极与所述次像素电极之间形成第一正对面积，所述导电片与所述次像素电极之间形成第二正对面积，以使所述公共电极与次像素电极之间及所述导电片与所述次像素电极之间共同形成存储电容。
  12. 如权利要求11所述的显示面板，其中，所述第一绝缘层设第一通孔以露出部分所述公共电极，所述次像素电极与所述第一通孔间隔设置，所述第二绝缘层设连通所述第一通孔的第二通孔，所述导电片通过所述第二通孔和所述第一通孔连接至所述公共电极。
  13. 如权利要求11所述的显示面板，其中，每个所述像素单元均具有薄膜晶体管，所述薄膜晶体管的源极和漏极与所述次像素电极同层设置，且所述漏极连接所述次像素电极。
  14. 如权利要求13所述的显示面板，其中，所述薄膜晶体管的栅极与所述公共电极同层设置。
  15. 如权利要求11所述的显示面板，其中，每个所述像素单元均具有透光区和设于所述透光区周边的遮光区，所述次像素电极位于所述遮光区，所述阵列基板还包括位于所述透光区的主像素电极，所述主像素电极电连接所述次像素电极。
  16. 如权利要求12所述的显示面板，其中，每个所述像素单元均具有透光区和设于所述透光区周边的遮光区，所述次像素电极位于所述遮光区，所述阵列基板还包括位于所述透光区的主像素电极，所述主像素电极电连接所述次像素电极。
  17. 如权利要求15所述的显示面板，其中，所述第二绝缘层设第三通孔以露出部分所述次像素电极，所述主像素电极通过所述第三通孔连接所述次像素电极。
  18. 如权利要求15所述的显示面板，其中，所述导电片与所述主像素电极同层设置，所述导电片与所述主像素电极之间彼此绝缘。
  19. 如权利要求18所述的显示面板，其中，所述导电片的材料与所述主像素电极的材料相同。
  20. 如权利要求15所述的显示面板，其中，所述公共电极在所述主像素电极上的正投影位于所述主像素电极的周边区域。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110161766B (zh) * 2018-08-10 2022-02-18 友达光电股份有限公司 显示装置
CN110488546A (zh) * 2019-08-21 2019-11-22 深圳市华星光电半导体显示技术有限公司 阵列基板、液晶显示面板及液晶显示器
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110309397A1 (en) * 2010-06-22 2011-12-22 Au Optronics Corporation Pixel structure and manufacturing method thereof
CN103676359A (zh) * 2013-12-19 2014-03-26 京东方科技集团股份有限公司 一种液晶显示屏及显示装置
CN105487315A (zh) * 2016-01-19 2016-04-13 武汉华星光电技术有限公司 Tft阵列基板
CN106773423A (zh) * 2017-02-23 2017-05-31 深圳市华星光电技术有限公司 像素结构、阵列基板和液晶显示面板
CN106855670A (zh) * 2017-02-28 2017-06-16 厦门天马微电子有限公司 阵列基板、显示面板和显示装置
CN206258650U (zh) * 2016-12-02 2017-06-16 厦门天马微电子有限公司 一种液晶显示面板及显示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4047586B2 (ja) * 2002-01-10 2008-02-13 Ｎｅｃ液晶テクノロジー株式会社 横電界方式のアクティブマトリクス型液晶表示装置
TWI325639B (en) * 2007-03-15 2010-06-01 Au Optronics Corp Semiconductor structure and fabricating method thereof for liquid crystal display device
CN100505221C (zh) * 2007-03-28 2009-06-24 友达光电股份有限公司 液晶显示器的半导体结构及其制作方法
CN100521162C (zh) * 2007-04-29 2009-07-29 友达光电股份有限公司 显示装置的半导体结构及其制造方法
CN203444218U (zh) * 2013-08-22 2014-02-19 京东方科技集团股份有限公司 一种阵列基板及显示装置
CN103777418B (zh) * 2014-01-27 2016-05-04 京东方科技集团股份有限公司 一种阵列基板、液晶显示面板及显示装置
CN105527767B (zh) * 2016-01-25 2019-05-03 武汉华星光电技术有限公司 一种阵列基板以及液晶显示器

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110309397A1 (en) * 2010-06-22 2011-12-22 Au Optronics Corporation Pixel structure and manufacturing method thereof
CN103676359A (zh) * 2013-12-19 2014-03-26 京东方科技集团股份有限公司 一种液晶显示屏及显示装置
CN105487315A (zh) * 2016-01-19 2016-04-13 武汉华星光电技术有限公司 Tft阵列基板
CN206258650U (zh) * 2016-12-02 2017-06-16 厦门天马微电子有限公司 一种液晶显示面板及显示装置
CN106773423A (zh) * 2017-02-23 2017-05-31 深圳市华星光电技术有限公司 像素结构、阵列基板和液晶显示面板
CN106855670A (zh) * 2017-02-28 2017-06-16 厦门天马微电子有限公司 阵列基板、显示面板和显示装置

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