WO2020098001A1 - 显示面板及其制造方法和显示装置 - Google Patents

显示面板及其制造方法和显示装置 Download PDF

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Publication number
WO2020098001A1
WO2020098001A1 PCT/CN2018/118437 CN2018118437W WO2020098001A1 WO 2020098001 A1 WO2020098001 A1 WO 2020098001A1 CN 2018118437 W CN2018118437 W CN 2018118437W WO 2020098001 A1 WO2020098001 A1 WO 2020098001A1
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WIPO (PCT)
Prior art keywords
layer
metal layer
display panel
black color
color resist
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PCT/CN2018/118437
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English (en)
French (fr)
Inventor
杨春辉
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惠科股份有限公司
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Application filed by 惠科股份有限公司 filed Critical 惠科股份有限公司
Priority to US16/349,993 priority Critical patent/US11409171B2/en
Publication of WO2020098001A1 publication Critical patent/WO2020098001A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel, a manufacturing method, and a display device.
  • LCD Liquid crystal display
  • LCD TV mobile phone, personal digital assistant, digital camera, computer screen or laptop screen Etc.
  • LCD TV mobile phone, personal digital assistant, digital camera, computer screen or laptop screen Etc.
  • TFT thin film transistor
  • the present application provides a display panel, a manufacturing method, and a display device that can reduce circuit load.
  • a display panel including: a first substrate; a first metal layer formed on the first substrate; a second metal layer formed between the first metal layer and the second metal layer An insulating layer; and a black color resist layer formed between the first metal layer and the second metal layer.
  • the first metal layer is a scan line
  • the second metal layer is a data line
  • the insulating layer and the black color resist layer are provided at positions where the scan line and the data line cross.
  • the display panel includes a semiconductor layer, and the semiconductor layer is disposed between the first metal layer and the second metal layer.
  • the first metal layer forms a gate
  • the second metal layer forms a source and a drain, the source and the drain are independent of each other; the source is connected to the drain through the semiconductor layer Pole connection
  • the insulating layer is a gate insulating layer, and the gate insulating layer is formed between the gate and the semiconductor layer;
  • the black color resist layer is provided on the gate, part of the black color resist layer covers the gate, and the other part does not cover the gate; part of the source electrode is provided in the black color On the resistive layer, another part is provided on the semiconductor layer; at least a part of the drain is provided on the semiconductor layer.
  • the gate insulating layer is formed on the black color resist layer, and the semiconductor layer is formed on the gate insulating layer.
  • the area of the semiconductor layer is smaller than the area of the gate, and the location of the semiconductor layer corresponds to a non-edge area of the gate.
  • the black color resist layer is provided with an opening, and the distance from the periphery of the opening to the outer edge of the black color resist layer is greater than 0; the semiconductor layer is provided in the area of the opening.
  • This application also discloses a method for manufacturing a display panel, including the steps of:
  • the insulating layer and the black color resist layer are disposed between the first metal layer and the second metal layer.
  • the method further includes the step of forming a semiconductor layer.
  • the method further includes the steps of: forming a passivation layer on the second metal layer, and forming via holes on the passivation layer.
  • the method further includes the steps of: forming a transparent conductive layer, the transparent conductive layer being connected through the via hole Second metal layer.
  • the black color resist layer is formed with an opening for forming the gate insulating layer.
  • the distance from the periphery of the opening to the outer edge of the black color resist layer is greater than 0.
  • the semiconductor layer is disposed in the area of the opening.
  • the present application also discloses a display device.
  • the display device includes a display panel.
  • the display panel includes: a first substrate; a first metal layer formed on the first substrate; a second metal layer ; An insulating layer formed between the first metal layer and the second metal layer; and a black color resist layer formed between the first metal layer and the second metal layer.
  • the black color resist layer is not provided for the first metal layer and the second metal layer
  • the first metal layer and the second metal layer will produce a
  • the relatively large coupling capacitance due to the existence of the coupling capacitance, causes an increase in the circuit load of the first metal layer and the second metal, which in turn causes poor display panel quality.
  • a black color resist layer is added between the first metal layer and the second metal layer.
  • the distance between the first metal and the second metal layer is made Increased, can reduce the coupling capacitance between the first metal layer and the second metal layer, thereby reducing the circuit load of the first metal layer and the second metal layer;
  • the dielectric properties of the black color resist layer and ordinary The insulating layer is different, and the space for adjusting the film thickness of the black color resist layer is larger; at the same time, due to the increased distance between the first metal layer and the second metal layer, for the side shot between the first metal layer and the second metal layer For light, the possibility of light leakage between the first metal layer and the second metal layer is increased.
  • the black color resist layer can block lateral light, reduce light leakage, display better, and ensure the quality of the display panel.
  • FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another display panel according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another display panel according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a manufacturing process of a display panel according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a manufacturing process of a display panel according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a display panel manufacturing process according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a display panel manufacturing process according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a display panel according to an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a display panel manufacturing process according to another embodiment of the present application.
  • FIG. 11 is a schematic diagram of a display device according to another embodiment of the present application.
  • first and second are for descriptive purposes only, and cannot be understood as indicating relative importance, or implicitly indicating the number of technical features indicated.
  • the features defined as “first” and “second” may expressly or implicitly include one or more of the features; “multiple” means two or more.
  • the term “comprising” and any variations thereof are meant to be non-exclusive and one or more other features, integers, steps, operations, units, components, and / or combinations thereof may be present or added.
  • connection should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection It can also be an electrical connection; it can be directly connected, indirectly connected through an intermediary, or connected within two components.
  • the display panel 100 includes:
  • the black color resist layer 120 is not provided for the first metal layer 130 and the second metal layer 140 in this solution, when the distance between the first metal layer 130 and the second metal layer 140 is closer, the first metal layer 130 and the second metal layer 140 The two-metal layer 140 generates a relatively large coupling capacitance. Due to the existence of the coupling capacitance, the circuit load of the first metal layer 130 and the second metal increases, which in turn causes the display panel 100 to have poor quality. In this solution, a black color resist layer 120 is added between the first metal layer 130 and the second metal layer 140.
  • the black color resist layer 120 Since the black color resist layer 120 has a certain thickness, this makes the first metal and the second metal layer 140 The increased distance between them can reduce the coupling capacitance between the first metal layer 130 and the second metal layer 140, thereby reducing the circuit load of the first metal layer 130 and the second metal layer 140; in addition, the black color The dielectric performance of the resistor is different from that of the ordinary insulating layer, and the space for adjusting the film thickness of the black color resister is larger; at the same time, since the distance between the first metal layer 130 and the second metal layer 140 is increased, For light between the layer 130 and the second metal layer 140, the possibility of light leakage between the first metal layer 130 and the second metal layer 140 is increased, and the black color resister can block lateral light and reduce light leakage. The display effect is better, and the quality of the display panel 100 is guaranteed.
  • the first metal layer 130 is a scan line 132
  • the second metal layer 140 is a data line 143.
  • a The insulating layer 160 and the black color resist layer 120 At a position where the scan line 132 and the data line 143 cross, a The insulating layer 160 and the black color resist layer 120.
  • the scan line 130 and the data line 140 in the display panel 100 have interlaced and overlapping areas.
  • a parasitic capacitance is generated between the scan line 130 and the data line 140, thereby increasing the data line 140
  • the signal between the data line 140 and the scan line 130 may cause crosstalk, which may cause display defects in the display panel 100
  • a black color resist layer 120 and insulation are added between the data line 140 and the scan line 130
  • the distance between the data line 140 and the scan line 130 can be increased, thereby reducing the parasitic capacitance between the two, thereby avoiding signal interference between the two, and ensuring the performance of the display panel 100.
  • the display panel 100 includes a semiconductor layer 150, and the semiconductor layer 150 is disposed between the first metal layer 130 and the second metal layer 140;
  • the metal layer 130 forms a gate 131, and the second metal layer 140 forms a source 141 and a drain 142, the source 141 and the drain 142 are independent of each other; the source 141 is connected to the drain 142 through the semiconductor layer 150;
  • the insulating layer is a gate insulating layer 160.
  • the gate insulating layer 160 is formed between the gate 131 and the semiconductor layer 150; the black color resist layer 120 is disposed on the gate 131, and the black color resist layer 120 partially covers the gate 131, and A portion does not cover the gate 131; a portion of the source electrode 141 is disposed on the black color resist layer 120, and the other portion is disposed on the semiconductor layer 150; at least a portion of the drain electrode 142 is disposed on the semiconductor layer 150.
  • a portion of the source electrode is disposed on the black color resist layer, and another portion is disposed on the semiconductor layer; at least a portion of the drain electrode is disposed on the semiconductor layer; specifically, the source electrode 141 includes a first portion 1411 and The second part 1412, the first part 1411 and the second part 1412 are of an integrated structure, the first part 1411 is provided on the portion of the black color resist layer 120 covering the gate 131; the second part 1412 is provided on the black color resist layer 120 not covered The portion of the gate electrode 131; the drain electrode 142 includes a third portion 1421 and a fourth portion 1422, the first portion 1411 and the second portion 1412 are an integral structure, and the third portion 1421 is disposed on a portion of the black color resist layer 120 covering the gate electrode 131 The fourth portion 1422 is provided in a portion where the black color resist layer 120 does not cover the gate 131.
  • the black color resist layer 120 is disposed on the gate 131, and the black color resist layer 120 partially covers the gate 131 and a portion does not cover the gate 131; the source is divided into a first portion 1411 and a second portion 1412, the first The portion 1411 is provided in the portion where the black color resist layer 120 covers the gate 131; the second portion 1412 is provided in the portion where the black color resist layer 120 does not cover the gate 131. Due to the presence of the black color resist layer 120, the first portion 1411 and the semiconductor layer 150 is not in direct contact, but the distance between the first part 1411 and the gate 131 is greater than the distance between the second part 1412 and the gate 131. The coupling capacitance between the first part 1411 and the gate 131 is small.
  • the two parts 1412 are of an integrated structure, the overall capacitance of the source 141 is reduced, and the load of the corresponding source 141 is correspondingly reduced.
  • the second part 1412 is in contact with the semiconductor layer 150.
  • the third part 1421 of the drain 142 and The fourth part 1422 can also play the same role, and the load of the drain 142 is reduced accordingly.
  • the second and fourth portions 1422 are disposed on the uncovered portion of the black color resist, so that the second portion 1412 and the fourth portion 1422 are in contact with the semiconductor layer 150, so that the switch structure formed after the process of the display panel 100 is completed, such as a thin film transistor (Thin-Film Transistor, TFT), such a switch structure can reduce the load of the gate 131 and the source 141, the drain 142, and reduce the parasitic between the gate and the source, and the gate and the drain
  • TFT thin film transistor
  • the capacitance improves the performance of the TFT, and when the pixel electrode is charged, the influence of the parasitic capacitance on the charging of the pixel electrode is reduced, and the reverse voltage of the pixel electrode is reduced (KickBack) to ensure the performance of the display panel 100.
  • the gate insulating layer 160 is formed on the black color resist layer 120 and the semiconductor layer 150 is formed on the gate insulating layer 160.
  • the gate 131 is close to the backlight.
  • the gate 131 is insulated by a transparent insulating material.
  • a black color resist layer 120 is provided on the gate 131 to block the backlight and prevent the backlight from entering the semiconductor layer 150, which ensures the normal operation of the switch structure formed by this solution and the performance of the display panel 100.
  • the area of the semiconductor layer 150 is smaller than the area of the gate 131, and the semiconductor layer 150 is disposed corresponding to the non-edge area of the gate 131.
  • the semiconductor layer 150 is disposed on the edge area of the gate 131. Due to the manufacturing accuracy of the display panel 100, there is a misalignment between the semiconductor and the gate 131, so that light from the backlight may enter In the semiconductor, the semiconductor layer 150 generates current, which affects the normal display of the display panel 100.
  • the semiconductor layer 150 is disposed in a non-edge area corresponding to the gate electrode 131, so that the backlight can be prevented from entering the semiconductor layer 150, and the semiconductor layer 150 can eliminate the current generated by the light, so that the display panel 100 can display normally.
  • the black color resist layer 120 is provided with an opening 121, and the distance from the periphery of the opening 121 to the outer edge of the black color resist layer 120 is greater than 0; the semiconductor layer 150 is disposed in the area of the opening 121 in.
  • the black color resist layer 120 is provided with an opening 121, and the distance from the periphery of the opening 121 to the edge of the black color resist layer 120 is greater than 0, which means that the opening 121 is not provided in the edge area of the black color resist layer 120. If it is disposed at the edge area of the black color resist layer 120, the backlight may appear to leak light, which may affect the quality of the display panel 100.
  • the present application discloses a method for manufacturing the display panel 100, including the steps of:
  • S10 Provide a first substrate 110 to form a first metal layer 130;
  • the insulating layer and the black color resist layer 120 are disposed between the first metal layer 130 and the second metal layer 140.
  • a black color resist layer 120 is provided between the first metal layer 130 and the second metal layer 140. Since the black color resist layer 120 has a certain thickness, the first metal layer is increased by providing the black color resist layer 120 The distance between 130 and the second metal layer 140, which can reduce the coupling capacitance generated between the first metal layer 130 and the second metal layer 140, due to the coupling between the first metal layer 130 and the second metal layer 140 As the capacitance decreases, the circuit load of the first metal layer 130 and the second metal layer 140 decreases.
  • the method further includes the steps of:
  • step S13 of forming the second metal layer 140 the method further includes the steps of:
  • a transparent conductive layer 190 is formed, and the transparent conductive layer 190 is connected to the second metal layer 140 through the via 180.
  • This scheme forms a switching structure such as a thin film transistor (TFT).
  • a gate 131 is formed on the first substrate 110, a black color resist layer 120 is formed on the gate 131, an opening 121 is provided on the black color resist layer 120, then a gate insulating layer 160 is formed, and a semiconductor is provided at a position corresponding to the opening 121 In the layer 150, a source 141 and a drain 142 are formed independently on the semiconductor layer 150, followed by a passivation layer 170 and a via 180, and finally a transparent conductive layer 190 is formed, thus forming a complete thin film transistor (Thin Film Transistor) , TFT) structure.
  • Thin Film Transistor Thin Film Transistor
  • this scheme can also form data lines and scan lines.
  • the black color resist layer 120 between the data lines and the scan lines the distance between the two is increased, and the data lines and the scan lines are avoided during signal transmission. Without affecting, the display abnormality of the display panel 100 is reduced.
  • the black color resist layer 120 in the step of forming the black color resist layer 120, is formed with an opening 121 for the gate insulating layer 160 to form; the periphery of the opening 121 is black The distance of the outer edge of the color resist layer 120 is greater than 0; the semiconductor layer 150 is disposed in the area of the opening 121.
  • the opening 121 of the black color resist layer 120 only needs to set a light-shielding pattern related to the opening 121 on the photomask used during the exposure process, and then the opening 121 can be thought of as the black color resist layer.
  • the manufacturing process of 120 does not add any manufacturing steps, and the manufacturing process is simple and easy.
  • the distance from the periphery of the opening 121 to the outer edge of the black color resist layer 120 is greater than 0, which can prevent light from radiating into the semiconductor layer and the current generated by the semiconductor layer, thereby ensuring the performance of the display panel 100.
  • the present application discloses a display device 10 that includes the above-mentioned display panel 100.
  • the technical solution of the present application can be widely applied to various display panels, such as twisted nematic (TN) display panel, in-plane switching (IPS) display panel, and vertical alignment type (Vertical Alignment, VA) ) Display panel, multi-quadrant vertical alignment (Multi-Domain Vertical Alignment, MVA) display panel, of course, it can also be other types of display panels, such as organic light-emitting diode (Organic Light-Emitting Diode, OLED) display panel, both The above scheme is applicable.
  • TN twisted nematic
  • IPS in-plane switching
  • VA Vertical Alignment
  • MVA Multi-Domain Vertical Alignment
  • OLED Organic Light-Emitting Diode

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Abstract

本申请公开了一种显示面板、制造方法和显示装置。所述显示面板包括：形成于第一衬底上的第一金属层的第一衬底；第二金属层；以及形成于所述第一金属层和第二金属层之间的黑色色阻层；所述第一金属层为扫描线，所述第二金属层为数据线，所述扫描线和所述数据线交叉的位置处，设置有所述绝缘层和黑色色阻层。

Description

显示面板及其制造方法和显示装置
本申请要求于2018年11月12日提交中国专利局，申请号为CN201811338823.X，申请名称为“一种显示面板、制造方法和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板、制造方法和显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如：液晶电视、移动电话、个人数字助理、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。随着显示技术的不断发展，高品质显示面板的解析度和分辨率越来越高，但存在诸如交叉串扰(Crosstalk)，影像残留(Image Sticking)等缺陷。
以显示面板的开关结构薄膜晶体管(Thin Film Transistor，TFT)为例，如何减小薄膜晶体管(Thin Film Transistor，TFT)第一金属层和第二金属层之间寄生电容，进而减小第一金属层和第二金属层的负载成为了亟待解决的问题。
技术解决方案
为实现上述目的，本申请提供了一种可以减少电路负载的显示面板、制造方法和显示装置。
一种显示面板，所述显示面板包括：第一衬底；第一金属层，形成于所述第一衬底上第二金属层；形成于所述第一金属层和第二金属层之间的绝缘层；以及，形成于所述第一金属层和第二金属层之间的黑色色阻层。
可选的，所述第一金属层为扫描线，所述第二金属层为数据线，所述扫描线和所述数据线交叉的位置处，设置有所述绝缘层和黑色色阻层。
可选的，所述显示面板包括半导体层，所述半导体层设置在第一金属层和第二金属层之间。
可选的，所述第一金属层形成栅极，所述第二金属层形成源极和漏极,所述源极和漏极相互独立；所述源极通过所述半导体层与所述漏极连接；
可选的，所述绝缘层为栅极绝缘层，所述栅极绝缘层形成于栅极和半导体层之间；
可选的，所述黑色色阻层设置在栅极上，所述黑色色阻层一部分覆盖所述栅极，另一部分不覆盖所述栅极；所述源极一部分设置在所述的黑色色阻层上，另一部分设置在半导体层；所述漏极至少一部分设置在半导体层上。
可选的，所述栅极绝缘层形成于所述黑色色阻层上，所述半导体层形成于所述栅极绝缘层上。
可选的，所述半导体层的面积小于所述的栅极的面积，所述半导体层设置位置对应所述栅极的非边缘区域。
可选的，所所述黑色色阻层上设置有开口，所述开口四周距离黑色色阻层的外缘的距离大于0；所述半导体层设置在所述开口的区域中。
本申请还公开了一种显示面板的制作方法，包括步骤：
提供第一衬底，形成第一金属层；
形成黑色色阻层和绝缘层；
形成第二金属层；
其中，所述绝缘层和黑色色阻层设置在第一金属层和第二金属层之间。
可选的，形成黑色色阻层和绝缘层的步骤后，还包括步骤：形成半导体层。
可选的，形成第二金属层步骤后，还包括步骤：在所述第二金属层上形成钝化层，并在所述钝化层上形成过孔。
可选的，在所述第二金属层上形成钝化层，并在所述钝化层上形成过孔后，还包括步骤：形成透明导电层，所述透明导电层通过所述过孔连接第二金属层。
可选的，所述形成黑色色阻层步骤中，所述形成黑色色阻层步骤中，所述黑色色阻层形成有开口供所述栅极绝缘层形成。
可选的，所述开口四周距离黑色色阻层的外缘的距离大于0。
可选的，所述半导体层设置在所述开口的区域中。
本申请还公开了一种显示装置，所述显示装置显示装置包括显示面板，所述显示面板包括：第一衬底；形成于所述第一衬底上的第一金属层；第二金属层；形成于所述第一金属层和第二金属层之间的绝缘层；以及黑色色阻层，形成于所述第一金属层和第二金属层之间。
本方案相对于第一金属层和第二金属层没有设置黑色色阻层的方案，第一金属层和第二金属层距离在较近时，这样第一金属层和第二金属层会产生一个比较大的耦合电容，由于耦合电容的存在，造成第一金属层和第二金属的电路负载增加，进而造成显示面板品质不良。本方案在第一金属层和第二金属层之间增加了一层黑色色阻层，由于黑色色阻层是具有一定厚度的，这样使得了第一金属和第二金属层之间的相距距离增大，可以使得第一金属层和第 二金属层之间的耦合电容减小，进而减小第一金属层和第二金属层电路负载；另外，黑色色阻层的介电性能与普通的绝缘层不同，黑色色阻层的膜厚的调节空间更大；同时，由于第一金属层和第二金属层距离增大，对于侧向射向第一金属层和第二金属层之间的光线来说，第一金属层和第二金属层之间漏光的可能就增大了，黑色色阻层可以阻挡侧向的光线，减少了漏光，显示效果更好，保证了显示面板的品质。
附图说明
所包括的附图用来提供对本申请实施例的详细的理解，其构成了说明书的一部分，示例本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请的一实施例的一种显示面板的结构示意图；
图2是本申请的一实施例的另一种显示面板结构示意图；
图3是本申请的一实施例的另一种显示面板结构示意图；
图4是本申请的一实施例的一种显示面板制程示意图；
图5是本申请的一实施例的一张显示面板制程的示意图；
图6是本申请的一实施例的一种显示面板制程的示意图；
图7是本申请的一实施例的一种显示面板制程的示意图；
图8是本申请的一实施例的一种显示面板结构示意图；
图9是本申请的一实施例的一种显示面板的示意图；
图10是本申请的另一实施例的一种显示面板制程的示意图；
图11是本申请的另一实施例的一种显示装置的示意图。
具体实施方式
需要理解的是，这里所使用的术语、公开的具体结构和功能细节，仅仅是为了描述具体实施例，是代表性的，但是本申请可以通过许多替换形式来具体实现，不应被解释成仅受限于这里所阐述的实施例。
在本申请的描述中，术语“第一”、“第二”仅为描述目的，而不能理解为指示相对重要性，或者隐含指明所指示的技术特征的数量。由此，除非另有说明，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征；“多个”的含义是两个或两个以上。术语“包括”及其任何变形，意为不排他的包含，可能存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
另外，“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系的术语，是基于附图所示的方位或相对位置关系描述的，仅是为了便于描述本申请的简化描述，而不是指示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
此外，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，或是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
下面参考附图和可选的实施例对本申请作详细说明。
如图1至图11所示，本申请实施例公布一种显示面板100，显示面板100包括：
第一衬底110；，形成于所述第一衬底上的第一金属层130；第二金属层140；，形成于所述第一金属层和第二金属层之间的绝缘层160；以及，形成于所述第一金属层130和第二金属层140之间的黑色色阻层120。
本方案相对于第一金属层130和第二金属层140没有设置黑色色阻层120的方案，第一金属层130和第二金属层140距离在较近时，这样第一金属层130和第二金属层140会产生一个比较大的耦合电容，由于耦合电容的存在，造成第一金属层130和第二金属的电路负载增加，进而造成显示面板100品质不良。本方案在第一金属层130和第二金属层140之间增加了一层黑色色阻层120，由于黑色色阻层120是具有一定厚度的，这样使得了第一金属和第二金属层140之间的相距距离增大，可以使得第一金属层130和第二金属层140之间的耦合电容减小，进而减小第一金属层130和第二金属层140电路负载；另外，黑色色阻的介电性能与普通的绝缘层不同，黑色色阻的膜厚的调节空间更大；同时，由于第一金属层130和第二金属层140距离增大，对于侧向射向第一金属层130和第二金属层140之间的光线来说，第一金属层130和第二金属层140之间漏光的可能就增大了，黑色色阻可以阻挡侧向的光线，减少了漏光，显示效果更好，保证了显示面板100的品质。
在一实施例中，如图2所示，所述第一金属层130为扫描线132，第二金属层140为数据线143，扫描线132和所述数据线143交叉的位置处，设置有所述绝缘层160和黑色色阻层120。
本方案中，显示面板100中扫描线130和数据线140有存在交错互叠的区域，在交错重叠的区域，扫描线130和数据线140之间会产生一个寄生电容，进而增加了数据线140和扫描线130的线路负载，数据线140和扫描线130之间的信号会产生串扰进而导致显示面板100可能出现显示不良，在数据线140和扫描线130之间增加黑色色阻层120和绝缘层160后，可以增加数据线140和扫描线130之间的相距距离，进而减小两者之间的寄生电容，进 而避免两者产生信号的干扰，保障了显示面板100的性能。
在一实施例中，如图4、图5、图6、图7所示，显示面板100包括半导体层150，半导体层150设置在第一金属层130和第二金属层140之间；第一金属层130形成栅极131，第二金属层140形成源极141和漏极142,源极141和漏极142相互独立；源极141通过所述半导体层150与所述漏极142与连接；绝缘层为栅极绝缘层160，栅极绝缘层160形成于栅极131和半导体层150之间；黑色色阻层120设置在栅极131上，黑色色阻层120一部分覆盖栅极131，另一部分不覆盖栅极131；源极141有一部分设置在的黑色色阻层120上，另一部分设置在半导体层150；漏极142至少有一部分设置在半导体层150上。
所述源极有一部分设置在所述的黑色色阻层上，另一部分设置在半导体层；所述漏极至少有一部分设置在半导体层上；具体来说，源极141包括第一部1411和第二部1412，第一部1411和第二部1412为一体结构，第一部1411设置在黑色色阻层120覆盖栅极131的部分上；第二部1412设置在黑色色阻层120未覆盖栅极131的部分；漏极142包括第三部1421和第四部1422，第一部1411和第二部1412为一体结构，第三部1421设置在黑色色阻层120覆盖栅极131的部分；第四部1422设置在黑色色阻层120未覆盖栅极131的部分。
本方案中,黑色色阻层120设置在栅极131上，黑色色阻层120一部分覆盖栅极131，一部分不覆盖栅极131；源极分为第一部1411和第二部1412，第一部1411设置在黑色色阻层120覆盖栅极131的部分；第二部1412设置在黑色色阻层120未覆盖栅极131的部分，由于黑色色阻层120的存在第一部1411与半导体层150并不直接接触，但第一部1411距离栅极131的距离较第二部1412距离栅极131的距离大，第一部1411的与栅极131耦合电容小，由于第一部1411和第二部1412为一体结构，源极141的总体的电容减小，对应的源极141负载也相应减小，第二部1412与半导体层150接触，同理，漏极142的第三部1421和第四部1422也能起到相同的作用，漏极142负载也相应减小。第二和第四部1422由于设置在黑色色阻未覆盖部分上，这样第二部1412和第四部1422与半导体层150接触，这样完成显示面板100制程后形成成的开关结构，如薄膜晶体管(Thin-Film Transistor，TFT)后，这样的开关结构可以在减少栅极131和源极141、漏极142的负载，减小了栅极和源极、以及栅极和漏极之间的寄生电容，提高了TFT的性能，且在对像素电极进行充电时，减少了寄生电容对像素电极充电的影响，减少了像素电极的反向电压情况(Kick Back)，保证了显示面板100的性能。
在一实施例中，如图6和图7所示，栅极绝缘层160形成于黑色色阻层120上，半导体层150层形成于栅极绝缘层160上。
本方案相对于在栅极131上设置栅极绝缘层160的显示面板100来说，栅极131靠近背光源，示例的为了保障显示面板100的开口121率，栅极131绝缘会采用透明绝缘材料制成， 另外由于显示面板100制程存在误差，半导体层150设置在栅极131边缘处时，则容易被背光照射进而导致半导体层150产生电流，进而影响显示面板100的显示；本方案中，在栅极131上设置黑色色阻层120，则可以对背光进行遮挡，防止背光源入射到半导体层150，保证了本方案形成的开关结构正常工作，同时也保证了显示面板100的性能。
在一实施例中，半导体层150的面积小于的栅极131的面积，半导体层150与栅极131的非边缘区域对应设置。
本方案中相比半导体层150是设置在栅极131边缘区域的上的设置方式由于显示面板100制程精度的原因，半导体与栅极131坑出现错位的情况，这样背光源的会有光线入射到半导体中，进而使得半导体层150产生电流，这样会影响显示面板100的正常显示。将半导体层150设置在对应栅极131的非边缘区域，这样可以避免背光入射到半导体层150，消除半导体层150因为光照产生电流，可以使显示面板100的正常显示。
在一实施例中，参考图8、9，所黑色色阻层120上设置有开口121，开口121四周距离黑色色阻层120的外缘的距离大于0；半导体层150设置在开口121的区域中。
本方案中，黑色色阻层120上设置有开口121，开口121四周距离黑色色阻层120的边缘的距离大于0，则说明开口121不设置在黑色色阻层120的边缘区域，若开口121设置在黑色色阻层120的边缘区域，则可能导致背光源出现漏光的相像，进而影响显示面板100的品质。
在一实施例中，如图4、图5、图6、图7和图10所示，本申请公开了一种显示面板100的制作方法，包括步骤：
S10:提供第一衬底110，形成第一金属层130；
S11:形成黑色色阻层120和绝缘层；
S13:形成第二金属层140；
其中，绝缘层和黑色色阻层120设置在第一金属层130和第二金属层140之间。
本方案中，在第一金属层130和第二金属层140之间设置黑色色阻层120，由于黑色色阻层120是具有一定厚度的，这样通过设置黑色色阻层120增加第一金属层130和第二金属层140的相距的距离，这样可以减小第一金属层130和第二金属层140之间产生的耦合电容，由于第一金属层130和第二金属层140之间的耦合电容的减小，第一金属层130和第二金属层140的电路负载减小。
在一实施例中，参考图10、形成黑色色阻层120和绝缘层160的步骤后，还包括步骤：
S12:形成半导体层150；
形成第二金属层140步骤S13后，还包括步骤：
S14:在第二金属层140上形成钝化层170，并在钝化层170上形成过孔180；
S15:形成透明导电层190，透明导电层190通过过孔180连接第二金属层140。
这种方案形成开关结构如薄膜晶体管(TFT)。在第一衬底110上形成栅极131，栅极131上形成黑色色阻层120，黑色色阻层120上设置有一开口121，后形成栅极绝缘层160，在对应开口121的位置设置半导体层150，在半导体层150上形成相互独立的源极141和漏极142，后形成钝化层170和过孔180，最后形成透明导电层190，这样就形成一个完整的薄膜晶体管(Thin Film Transistor，TFT)结构。由于栅极131与源极141、漏极142存在一个黑色色阻层120，增大栅极131与源极141、漏极142之间的相距距离，减小了之间耦合电容，避免了显示面板100出现显示的异常。
当然这种方案也可以形成数据线和扫描线，同样由于数据线和扫描线之间存在黑色色阻层120，增大了两者的相距距离，避免在信号传输时，数据线和扫描线互不影响，减少显示面板100出现显示异常。
在一实施例中，参考图10，形成黑色色阻层120步骤中，形成黑色色阻层120步骤中，黑色色阻层120形成有开口121供栅极绝缘层160形成；开口121四周距离黑色色阻层120的外缘的距离大于0；半导体层150设置在开口121的区域中。
本方案中，黑色色阻层120的开口121，只需要在在曝光过程中所使用的光掩模上设置与开口121相关的遮光图案，后便可以想成开口121，在制作黑色色阻层120的制程中不增加制程步骤，制程简单易行。另外开口121四周距离黑色色阻层120的外缘的距离大于0，可以避免光线照射到半导体层中，避免半导体层产生电流，保证了显示面板100的性能。
在一实施例中，如图3、图7、图10、图11所示，本申请公开了一种显示装置10，显示装置10包括上述显示面板100。
需要说明的是，本方案中涉及到的各步骤的限定，在不影响具体方案实施的前提下，并不认定为对步骤先后顺序做出限定，写在前面的步骤可以是在先执行的，也可以是在后执行的，甚至也可以是同时执行的，只要能实施本方案，都应当视为属于本申请的保护范围。
本申请的技术方案可以广泛运用于各种显示面板，如扭曲向列型(Twisted Nematic，TN)显示面板、平面转换型(In-Plane Switching，IPS)显示面板、垂直配向型(Vertical Alignment，VA)显示面板、多象限垂直配向型(Multi-Domain Vertical Alignment，MVA)显示面板，当然，也可以是其他类型的显示面板，如有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板，均可适用上述方案。
以上内容是结合具体的实施方式对本申请所作的详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (17)

  1. 一种显示面板，所述显示面板包括：
    第一衬底；
    第一金属层，形成于所述第一衬底上；
    第二金属层；
    绝缘层，形成于所述第一金属层和第二金属层之间；以及
    黑色色阻层，形成于所述第一金属层和第二金属层之间。
  2. 如权利要求1所述一种显示面板，其中，所述第一金属层为扫描线，所述第二金属层为数据线，所述扫描线和所述数据线交叉的位置处，设置有所述绝缘层和黑色色阻层。
  3. 如权利要求1所述一种显示面板，其中，所述显示面板包括半导体层，所述半导体层设置在第一金属层和第二金属层之间；
  4. 如权利要求3所述一种显示面板，其中，所述第一金属层形成栅极，所述第二金属层形成源极和漏极,所述源极和漏极相互独立；所述源极通过所述半导体层与所述漏极连接。
  5. 如权利要求4所述一种显示面板，其中，所述绝缘层为栅极绝缘层，所述栅极绝缘层形成于栅极和半导体层之间。
  6. 如权利要求5所述一种显示面板，其中，所述黑色色阻层设置在栅极上，所述黑色色阻层一部分覆盖所述栅极，另一部分不覆盖所述栅极；所述源极一部分设置在所述的黑色色阻层上，另一部分设置在半导体层；所述漏极至少一部分设置在半导体层上。
  7. 如权利要求3所述一种显示面板，其中，所述栅极绝缘层形成于所述黑色色阻层上，所述半导体层形成于所述栅极绝缘层上。
  8. 如权利要求2所述一种显示面板，其中，所述半导体层的面积小于所述的栅极的面积，所述半导体层与所述栅极的非边缘区域对应设置。
  9. 如权利要求2所述一种显示面板，其中，所述黑色色阻层上设置有开口，所述开口距离黑色色阻层的外缘的距离大于0；所述半导体层设置在所述开口的区域中。
  10. 一种显示面板的制作方法，所述制作方法包括步骤：
    提供第一衬底，形成第一金属层；
    形成黑色色阻层和绝缘层；以及
    形成第二金属层；
    其中，所述绝缘层和黑色色阻层设置在第一金属层和第二金属层之间。
  11. 如权利要求10所述一种显示面板的制作方法，其中，所述形成黑色色阻层和绝缘层的步骤后，还包括步骤：
    形成半导体层。
  12. 如权利要求10所述一种显示面板的制作方法，其中，所述形成第二金属层步骤后，还包括步骤：
    在所述第二金属层上形成钝化层，并在所述钝化层上形成过孔。
  13. 如权利要求10所述一种显示面板的制作方法，其中，在所述第二金属层上形成钝化层，并在所述钝化层上形成过孔后，还包括步骤：
    形成透明导电层，所述透明导电层通过所述过孔连接第二金属层。
  14. 如权利要求10所述一种显示面板的制作方法，其中，所述形成黑色色阻层步骤中，所述黑色色阻层形成有开口供所述栅极绝缘层形成。
  15. 如权利要求14所述一种显示面板的制作方法，其中，所述开口四周距离黑色色阻层的外缘的距离大于0。
  16. 如权利要求15所述一种显示面板的制作方法，其中，所述半导体层设置在所述开口的区域中。
  17. 一种显示装置，所述显示装置包括显示面板，所述显示面板包括：
    第一衬底；
    第一金属层，形成于所述第一衬底上；
    第二金属层；
    绝缘层，形成于所述第一金属层和第二金属层之间；以及
    黑色色阻层，形成于所述第一金属层和第二金属层之间。
PCT/CN2018/118437 2018-11-12 2018-11-30 显示面板及其制造方法和显示装置 WO2020098001A1 (zh)

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