WO2023178560A1 - 显示基板、其制作方法及显示装置 - Google Patents

显示基板、其制作方法及显示装置 Download PDF

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Publication number
WO2023178560A1
WO2023178560A1 PCT/CN2022/082562 CN2022082562W WO2023178560A1 WO 2023178560 A1 WO2023178560 A1 WO 2023178560A1 CN 2022082562 W CN2022082562 W CN 2022082562W WO 2023178560 A1 WO2023178560 A1 WO 2023178560A1
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Prior art keywords
insulating layer
jumper
terminal
layer
channel
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PCT/CN2022/082562
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English (en)
French (fr)
Inventor
席文星
王为旺
邹振游
余雪
陈周煜
刘承俊
吴承隆
林滨
Original Assignee
京东方科技集团股份有限公司
福州京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 福州京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000503.1A priority Critical patent/CN117121203A/zh
Priority to PCT/CN2022/082562 priority patent/WO2023178560A1/zh
Publication of WO2023178560A1 publication Critical patent/WO2023178560A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a manufacturing method thereof, and a display device.
  • the present disclosure provides a display substrate, its manufacturing method and a display device.
  • the specific solutions are as follows:
  • embodiments of the present disclosure provide a display substrate, including:
  • a base substrate includes a display area, and a frame area located on at least one side of the display area;
  • a plurality of shift registers are located in the border area, and the plurality of shift registers are arranged in cascade;
  • the jumper terminals include a first jumper terminal and a second jumper terminal.
  • the first jumper terminal is connected to the shift register.
  • the register is electrically connected, and the second jumper terminal is located between the layer where the first jumper terminal is located and the substrate substrate;
  • a plurality of transfer terminals located between the shift register and the display area, the plurality of transfer terminals being located on a side of the layer where the first jumper terminal is located away from the base substrate;
  • An insulating layer is located in the display area and the frame area.
  • the insulating layer is located between the layer where the second jumper terminal is located and the layer where the multiple transfer terminals are located.
  • the insulating layer includes the exposed A channel of multiple jumper terminals; in the channel, the first jumper terminal and the second jumper terminal of the same jumper terminal are directly overlapped with the same transfer terminal respectively.
  • the above display substrate provided by the embodiment of the present disclosure further includes: a first conductive layer located on a side of the insulating layer away from the base substrate, and the plurality of transfer terminals are located on the side of the insulating layer away from the base substrate. first conductive layer.
  • the insulating layer includes a gate insulating layer sequentially provided on a side of the layer where the second jumper terminal is located facing the first conductive layer, a first inorganic insulation layer and an organic insulation layer;
  • the channel penetrates the gate insulating layer, the first insulating layer and the organic insulating layer in the thickness direction of the insulating layer.
  • the above display substrate provided by the embodiment of the present disclosure further includes: a second inorganic insulating layer located on a side of the first conductive layer away from the base substrate, the second inorganic insulating layer Cover the plurality of transfer terminals.
  • the above display substrate provided by the embodiment of the present disclosure further includes: a first conductive layer and a second conductive layer that are sequentially provided on a side of the insulating layer away from the base substrate and are insulated from each other. , the plurality of transfer terminals are located on the second conductive layer.
  • the insulating layer includes a gate insulating layer, a gate insulating layer, and a third conductive layer, which are sequentially provided on a side of the layer where the first jumper terminal is located facing the first conductive layer.
  • the channel penetrates the gate insulating layer, the first inorganic insulating layer, the organic insulating layer and the second inorganic insulating layer in the thickness direction of the insulating layer.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure further includes a plurality of transistors in the display area and between the first inorganic insulating layer and the base substrate;
  • the first jumper terminal is arranged on the same layer as the source and drain of the transistor, and the second jumper terminal is arranged on the same layer as the gate of the transistor.
  • the area between the transfer terminal and the first jumper terminal and the second jumper terminal is in contact with the base substrate, The first jumper terminal and the second jumper terminal are in direct contact.
  • the transfer terminal does not cover the edge of the first jumper terminal away from the second jumper terminal, and the transfer terminal The terminal does not cover the edge of the side of the second jumper terminal away from the first jumper terminal.
  • the orthographic projection area of the first jumper terminal on the substrate substrate is less than or equal to 8 ⁇ m ⁇ 5 ⁇ m
  • the second jumper terminal is on
  • the orthographic projection area on the base substrate is less than or equal to 8 ⁇ m ⁇ 5 ⁇ m
  • the orthographic projection area of the transfer terminal on the base substrate is less than or equal to 20 ⁇ m ⁇ 15 ⁇ m.
  • embodiments of the present disclosure provide a method for manufacturing the above-mentioned display substrate, including:
  • the base substrate includes a display area, and a frame area located on at least one side of the display area;
  • a plurality of jumper terminals and a plurality of shift registers arranged in cascade are formed in the frame area, wherein the plurality of jumper terminals are located between the plurality of shift registers and the display area, and the
  • the jumper terminal includes a first jumper terminal and a second jumper terminal.
  • the first jumper terminal is electrically connected to the shift register.
  • the second jumper terminal is located on the layer where the first jumper terminal is located. between the substrate substrates;
  • a plurality of transfer terminals are formed in the channel, so that the first jumper terminal and the second jumper terminal of the same jumper terminal are directly overlapped with the same transfer terminal respectively.
  • an insulating layer is formed on the entire surface of the layer where the second jumper terminal is located, and an insulating layer is formed between the multiple shift registers and the display area.
  • the areas between form channels that expose the plurality of jumper terminals, specifically including:
  • a first channel penetrating the organic insulating layer is formed in the area between the plurality of shift registers and the display area;
  • a second channel is formed at the first channel through the first inorganic insulating layer and the gate insulating layer and exposing the plurality of jumper terminals, wherein the gate insulating layer, the first inorganic The insulating layer and the organic insulation form an insulating layer, and the first channel and the second channel are connected to form a channel exposing the plurality of jumper terminals.
  • an insulating layer is formed on the entire surface of the layer where the second jumper terminal is located, and an insulating layer is formed between the shift register and the display area.
  • the area forms a channel that exposes the plurality of jumper terminals, specifically including:
  • a first channel penetrating the organic insulating layer is formed in a region between the plurality of shift registers and the display area;
  • a second inorganic insulating layer is formed on the entire surface of the organic insulating layer
  • a third channel is formed at the first channel through the second inorganic insulating layer and the gate insulating layer and exposing the plurality of jumper terminals; wherein the gate insulating layer, the first inorganic insulating layer , the organic insulating layer and the second inorganic insulating layer form an insulating layer, and the first channel, the second channel and the third channel are connected to form a channel exposing the plurality of jumper terminals.
  • embodiments of the present disclosure provide a display device, including an opposite display substrate and a counter substrate, and a liquid crystal layer located between the display substrate and the counter substrate, wherein the display The substrate is the above-mentioned display substrate provided by the embodiment of the present disclosure, and the liquid crystal layer is located in the display area.
  • Figure 1 is a schematic diagram of the short-circuiting principle of each transfer terminal in the related art
  • Figure 2 is a schematic structural diagram of short circuiting of each transfer terminal in the related art
  • Figure 3 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 4 is a cross-sectional view along line II' in Figure 3;
  • Figure 5 is a schematic structural diagram of a sub-pixel in the display substrate shown in Figure 3;
  • Figure 6 is another cross-sectional view along line II' in Figure 3;
  • Figure 7 is a schematic structural diagram of the display substrate shown in Figures 4 and 6 during the manufacturing process
  • Figure 8 is another structural schematic diagram of the display substrate shown in Figures 4 and 6 during the manufacturing process
  • Figure 9 is another structural schematic diagram of the display substrate shown in Figure 4 during the manufacturing process
  • Figure 10 is another structural schematic diagram of the display substrate shown in Figure 4 during the manufacturing process
  • Figure 11 is another structural schematic diagram of the display substrate shown in Figure 4 during the manufacturing process
  • Figure 12 is another structural schematic diagram of the display substrate shown in Figure 6 during the manufacturing process
  • Figure 13 is another structural schematic diagram of the display substrate shown in Figure 6 during the manufacturing process
  • Figure 14 is another structural schematic diagram of the display substrate shown in Figure 6 during the manufacturing process
  • Figure 15 is another structural schematic diagram of the display substrate shown in Figure 6 during the manufacturing process
  • FIG. 16 is a schematic structural diagram of a sub-pixel in a display panel according to an embodiment of the present disclosure.
  • the gate drive circuit (GOA) in the related art includes multiple shift registers arranged in cascade, with a penetrating organic insulating layer (ORG) between the gate drive circuit area and the display area AA. and the channel H of the first inorganic insulating layer (PVX 1 ).
  • the channel H is provided with a first jumper terminal (SD pad, SP) connected to the shift register and a second jumper terminal (Gate) connected to the gate line (GL).
  • the via hole of the layer (PVX 2 ) is electrically connected to the first jumper terminal (SP), and is connected to the second jumper terminal (GP) through the via hole penetrating the second inorganic insulating layer (PVX 2 ) and the gate insulating layer (GI). ) electrical connection.
  • the present disclosure found that after superimposing the subsequent second inorganic insulating layer (PVX 2 ) and the layer where the transfer terminal (ITO 2 ) is located in the channel H, the film layer is high and the step difference is large, which will cause the subsequent production of the transfer terminal (ITO 2 ) photoresist (PR) accumulates on the bottom and side walls of channel H (as shown in the Z area in Figure 1), resulting in insufficient exposure in the Z area, and residual R will appear in the Z area (as shown in Figure 2) , the residual R will cause the first connection terminal (SP) and the second connection terminal (GP) of the adjacent shift register to be short-circuited, which will appear as a half-screen or full-screen horizontal stripe defect in the display device.
  • Some products with a large process tolerance (Margin) of the layer where the transfer terminal (ITO 2 ) is located can be improved by increasing the exposure amount of 5mj to 10mj, but this will cause great pressure on the production capacity of the bottleneck exposure process section of the display substrate. Influence. More importantly, increasing the exposure will directly cause the slit of the slit electrode in the display area AA and the transfer terminal (ITO 2 ) to become smaller, which will not meet the original product design requirements.
  • the product production process tolerance is also passively reduced, and changes in the process specifications (Spec) of the layer where the transfer terminal (ITO 2 ) is located expose the product to a series of potential risks, such as uneven low and medium grayscale images (Mura) , affecting important product characteristics such as VT symmetry, Gamma curve (involving T-con modulation and layout), transmittance, etc.
  • Spec process specifications
  • Mura grayscale images
  • a display substrate as shown in Figures 3 and 4, including:
  • the base substrate 101 includes a display area AA and a frame area BB located on at least one side of the display area AA;
  • Multiple shift registers SR n (n is a positive integer) are located in the border area BB, and multiple shift registers SR n are set up in cascade;
  • a plurality of jumper terminals 102 are located between the shift register SR n and the display area AA.
  • the jumper terminals 102 include a first jumper terminal 1021 and a second jumper terminal 1022.
  • the first jumper terminal 1021 is connected to the shift register SR. n is electrically connected, and the second jumper terminal 1022 is located between the layer where the first jumper terminal 1021 is located and the base substrate 101;
  • a plurality of transfer terminals 103 are located between the shift register SR n and the display area AA.
  • the multiple transfer terminals 103 are located on the side of the layer where the first jumper terminal 1021 is located away from the base substrate 101;
  • the insulating layer 104 is located in the display area AA and the frame area BB.
  • the insulating layer 104 is located between the layer where the second jumper terminal 1022 is located and the layer where the multiple transfer terminals 103 are located.
  • the insulating layer 104 includes a layer where the multiple jumper terminals 102 are exposed.
  • Channel H In channel H, the first jumper terminal 1021 and the second jumper terminal 1022 of the same jumper terminal 102 are directly connected to the same transfer terminal 103 respectively.
  • the transfer terminal 103 is used to directly cover the first jumper terminal 1021 and the second jumper terminal 1022.
  • the transfer terminal 103 is electrically connected to the first jumper terminal 1021 and the second jumper terminal 1022 respectively through via holes, which can ensure the connection between the transfer terminal 103 and the first jumper terminal 1021 and the second jumper terminal 1022.
  • the larger contact area effectively improves the stability of electrical connections.
  • the transfer terminal 103, the first jumper terminal 1021, and the second jumper terminal 1022 can be made smaller, so that the transfer terminal 103, the first jumper terminal 1021, and the second jumper terminal 1022 are farther away from the H side of the channel.
  • the distance between the walls can be designed to be larger. Even if there is residue near the side wall of channel H, the risk of short circuit between the residue and the transfer terminal 103, the first jumper terminal 1021, and the second jumper terminal 1022 can be significantly reduced, thus effectively solving the problem. Defects in horizontal lines caused by residues can effectively improve product yield and increase product revenue.
  • the present disclosure does not require an increase in exposure, thereby effectively alleviating bottleneck process production pressure, thereby enhancing production capacity and saving production costs.
  • the orthographic projection area of the transfer terminal 103 on the base substrate 101 is designed to be 40 ⁇ m ⁇ 30 ⁇ m.
  • the orthographic projection areas of the first jumper terminal 1021 and the second jumper terminal 1022 on the base substrate 101 are respectively 16 ⁇ m ⁇ 10 ⁇ m.
  • the transfer terminal 103 and the first jumper terminal 1021 and the second jumper terminal 1022 is directly overlapped to ensure that the contact area between the transfer terminal 103 and the first jumper terminal 1021 and the second jumper terminal 1022 is larger.
  • the wire terminal 1022 can be appropriately reduced in size.
  • the size of the transfer terminal 103 and the first jumper terminal 1021 and the second jumper terminal 1022 can be less than or equal to half of the size in the related art, for example, the first The orthographic projection area of the jumper terminal 1021 on the base substrate 101 may be less than or equal to 8 ⁇ m ⁇ 5 ⁇ m, the orthographic projection area of the second jumper terminal 1022 on the base substrate 101 may be less than or equal to 8 ⁇ m ⁇ 5 ⁇ m, and the transfer terminal 103 is on the substrate.
  • the orthographic projection area on the base substrate 101 may be 20 ⁇ m ⁇ 15 ⁇ m or less.
  • the above display substrate provided by the embodiment of the present disclosure may also include: a first conductive layer (1ITO) located on the side of the insulating layer 104 away from the base substrate 101 105.
  • a plurality of transfer terminals 103 are located on the first conductive layer 105, so that the material of the first conductive layer 105 in the related art can be used to complete the production of the transfer terminals 103 without additional material cost and separate transfer terminals 103. mask process. In this case, as shown in FIGS.
  • the insulating layer 104 may include a gate insulating layer 1041 and a first inorganic insulating layer sequentially disposed on the side facing the first conductive layer 105 at the level where the second jumper terminal 1022 is located. 1042 and the organic insulating layer 1043; the channel H penetrates the gate insulating layer 1041, the first insulating layer 1042 and the organic insulating layer 1043 in the thickness direction of the insulating layer 104.
  • the above display substrate provided by the embodiment of the present disclosure may also include: a second inorganic insulating layer located on the side of the first conductive layer 105 away from the base substrate 101 1044.
  • the second inorganic insulation layer 1044 covers the plurality of transfer terminals 103, so that the second inorganic insulation layer 1044 is used as a packaging protective layer for the transfer terminals 103, which can effectively improve the stability of the transfer terminals 103.
  • the above-mentioned display substrate provided by the embodiments of the present disclosure may further include: a third layer of insulating layer 104 that is sequentially provided on a side away from the base substrate 101 and is insulated from each other.
  • a plurality of transfer terminals 103 can be located on the second conductive layer 106. In this way, the transfer terminals 103 can be made using the material of the second conductive layer 106 in the related art. , without additional material costs and a separate mask process for the transfer terminal 103. In this case, as shown in FIGS.
  • the insulating layer 104 may include a gate insulating layer 1041 and a first inorganic insulating layer that are sequentially disposed on the side facing the first conductive layer 105 at the level where the second jumper terminal 1022 is located. 1042.
  • the transfer terminal 103 is between the area between the first jumper terminal 1021 and the second jumper terminal 1022 and The base substrate 101, the first jumper terminal 1021, and the second jumper terminal 1022 are all in direct contact, so that the transfer terminal 103 and the first jumper terminal 1021 are away from the upper surface of the base substrate 101 and the first jumper terminal 1021.
  • the side surface of the second jumper terminal 1022 away from the upper surface of the base substrate 101 and the side surface of the second jumper terminal 1022 are all in contact with each other, further increasing the distance between the transfer terminal 103 and the first jumper terminal 1021 and the second jumper
  • the contact area of the terminal 1022 can further reduce the size of the transfer terminal 103 and the first jumper terminal 1021 and the second jumper terminal 1022, thereby solving the problem of defective horizontal stripes caused by residues in related technologies.
  • the transfer terminal 103 does not cover the first jumper terminal 1021 and is away from the second jumper terminal 1022. and the transfer terminal 103 does not cover the edge of the second jumper terminal 1022 away from the first jumper terminal 1021. This is more conducive to etching to form the transfer terminal 103 and avoids the etching process of forming the transfer terminal 103. Residues are generated at the bottom of channel H and the side walls of channel H.
  • the first jumper terminal 1021 can be placed on the same layer as the source and drain of the transistor TFT
  • the second jumper terminal 1022 can be placed on the same layer as the gate of the transistor TFT, so that the source and drain of the transistor TFT can be used
  • the material of the first jumper terminal 1021 is completed, and the material of the gate of the transistor TFT is used to complete the production of the second jumper terminal 1022 without additional material cost, and the first jumper terminal 1021 and the second jumper terminal are 1022 separate mask process.
  • “same layer arrangement” refers to a layer structure formed by using the same film formation process to form a film layer for making a specific pattern, and then using the same mask to form a patterning process. That is, one patterning process corresponds to one mask (also called photomask).
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous. These specific patterns may be at the same height or Have the same thickness, may be at different heights or have different thicknesses.
  • the transistor TFT provided by the embodiment of the present disclosure may be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS), which is not limited here.
  • the transistor TFT can be a P-type transistor or an N-type transistor.
  • the P-type transistor is turned on when the voltage difference V gs between its gate and its source and its threshold voltage V th satisfy the relationship V gs ⁇ V th . And it is turned off when the relationship V gs ⁇ V th is satisfied; the N-type transistor is turned on when the voltage difference V gs between its gate and its source and its threshold voltage V th satisfy the relationship V gs > V th , and is turned on when the relationship V is satisfied.
  • the active layer of the transistor TFT may be an amorphous silicon (a-Si) active layer, a polycrystalline silicon (P-Si) active layer, or an oxide (IGZO) active layer, which is not limited here.
  • the transistor TFT may be a bottom-gate transistor, a top-gate transistor or a double-gate transistor, which is not limited here.
  • embodiments of the present disclosure provide a method for manufacturing the above-mentioned display substrate. Since the principle of solving the problem of this manufacturing method is similar to the principle of solving the problem of the above-mentioned display substrate, therefore, the manufacturing method provided by the embodiment of the present disclosure is For implementation, reference may be made to the implementation of the above-mentioned display substrate provided by the embodiments of the present disclosure, and repeated details will not be described again.
  • embodiments of the present disclosure provide a method for manufacturing the above-mentioned display substrate, including the following steps:
  • a base substrate which includes a display area and a frame area located on at least one side of the display area;
  • a plurality of jumper terminals and a plurality of shift registers arranged in cascade are formed in the frame area.
  • the plurality of jumper terminals are located between the plurality of shift registers and the display area.
  • the jumper terminals include a first jumper terminal and a a second jumper terminal, the first jumper terminal is electrically connected to the shift register, and the second jumper terminal is located between the layer where the first jumper terminal is located and the base substrate;
  • a plurality of transfer terminals are formed in the channel, so that the first jumper terminal and the second jumper terminal of the same jumper terminal are directly connected to the same transfer terminal respectively.
  • an insulating layer is formed on the entire surface of the layer where the second jumper terminal is located, and an exposed layer is formed in the area between the multiple shift registers and the display area.
  • the channels of multiple jumper terminals can be implemented in the following ways:
  • a stacked gate insulating layer 1041 , a first inorganic insulating layer 1042 and an organic insulating layer 1043 are formed on the entire surface of the layer where the second jumper terminal 1022 is located;
  • a first channel H 1 penetrating the organic insulating layer 1043 is formed in the area between the multiple shift registers SR n and the display area AA;
  • the third step forming a penetrating first inorganic insulating layer 1042 and the gate insulating layer 1041 at the first channel H 1 and exposing a plurality of jumper terminals 1042 (including the first jumper terminal 1021 and the second The second channel H 2 of the jumper terminal 1022), in which the gate insulating layer 1041, the first inorganic insulating layer 1042 and the organic insulating layer 1043 constitute the insulating layer 104, and the first channel H 1 and the second channel H 2 are turned on to form an exposed Channel H of multiple jumper terminals 102 .
  • the first conductive layer 105 may be formed on the entire surface of the organic insulating layer 1043 , and the first conductive layer 105 may be formed on the organic insulating layer 1043 .
  • the layer 105 is patterned to form a transfer terminal 103 that directly covers the first jumper terminal 1021 and the second jumper terminal 1022 in the channel H (as shown in FIG. 11 ).
  • Electrode 105' (shown in Figure 5). Afterwards, as shown in FIG.
  • a second inorganic insulating layer 1044 can be formed on the entire surface of the first conductive layer 105 so that the second inorganic insulating layer 1044 protects the transfer terminal 103 in the frame area BB and simultaneously in the display area AA.
  • the mutual insulation between the pixel electrode 105' and the subsequent common electrode 106' (as shown in FIG. 5) is achieved.
  • the preparation of the pixel electrode 105' and the common electrode 106' can refer to related technologies and will not be described in detail here.
  • an insulating layer is formed on the entire surface of the layer where the second jumper terminal is located, and a plurality of exposed layers are formed in the area between the shift register and the display area.
  • the channel of the jumper terminal can also be realized in the following ways:
  • a stacked gate insulating layer 1041 , a first inorganic insulating layer 1042 and an organic insulating layer 1043 are formed on the entire surface of the layer where the second jumper terminal 1022 is located;
  • a first channel H 1 penetrating the organic insulating layer 1043 is formed in the area between the multiple shift registers SR n and the display area AA;
  • a second channel H 2 ′ is formed at the first channel H 1 that penetrates the first inorganic insulating layer 1042 and exposes a plurality of first jumper terminals 1021 ;
  • the fourth step forms a second inorganic insulating layer 1044 on the entire surface of the organic insulating layer 1043;
  • a third channel H3 is formed at the first channel H1 , penetrating the second inorganic insulation layer 1044 and the gate insulation layer 1041 and exposing a plurality of jumper terminals 102 ; wherein, the gate insulation The layer 1041, the first inorganic insulating layer 1042, the organic insulating layer 1043 and the second inorganic insulating layer 1044 constitute the insulating layer 104.
  • the first channel H 1 , the second channel H 2 and the third channel H 3 are conductive to expose a plurality of Jumper terminal 102 for channel H.
  • the second conductive layer 106 can also be formed on the entire surface of the second inorganic insulating layer 1044 , and the second conductive layer 106 can be formed on the second inorganic insulating layer 1044 .
  • the second conductive layer 106 is patterned to form a transfer terminal 103 that directly covers the first jumper terminal 1021 and the second jumper terminal 1022 in the channel H (as shown in FIG. 6 ).
  • a narrow strip can be formed in the display area AA.
  • Slit-shaped common electrode 106' (as shown in Figure 5).
  • the manufacturing process of the shift register SR n , the transistor TFT electrically connected to the pixel electrode 105 ′ in the display area AA, the first jumper terminal 1021 and the second jumper terminal 1022 can refer to the related art. , will not be described in detail here.
  • an embodiment of the present disclosure provides a display device, as shown in FIG. 16 , including an opposite display substrate 001 and a counter substrate 002, and a liquid crystal between the display substrate 001 and the counter substrate 002.
  • Layer 003 wherein the display substrate 001 is the above-mentioned display substrate 001 provided by the embodiment of the present disclosure, and the liquid crystal layer 003 is located in the display area AA. Since the principle of solving the problem of the display device is similar to the principle of solving the problem of the above-mentioned display substrate, therefore, the implementation of the display device provided by the embodiment of the present disclosure can be referred to the implementation of the above-mentioned display substrate provided by the embodiment of the present disclosure, and the duplication will not be repeated. Repeat.
  • the opposing substrate 002 may include a glass substrate 201, a color resistor 202, a black matrix 203, etc., and the display device may also include a sealing frame.
  • Glue 004, etc., and other essential components of the display device are all understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used to limit the present disclosure.
  • the above-mentioned display device may be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any other device with A product or component that displays functionality.
  • the display device includes but is not limited to: radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, memory, processor, power supply and other components.

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Abstract

本公开提供的显示基板、其制作方法及显示装置，包括衬底基板，其包括显示区，以及位于显示区至少一侧的边框区；在边框区级联设置的多个移位寄存器；多个跳线端子，位于移位寄存器与显示区之间，跳线端子包括第一跳线端子和第二跳线端子，第一跳线端子与移位寄存器电连接，第二跳线端子位于第一跳线端子所在层与衬底基板之间；多个转接端子，位于移位寄存器与显示区之间，多个转接端子位于第一跳线端子所在层远离衬底基板的一侧；绝缘层，位于显示区和边框区，绝缘层位于第二跳线端子所在层与多个转接端子所在层之间，绝缘层包括暴露出多个跳线端子的通道；在通道内，同一跳线端子的第一跳线端子和第二跳线端子分别与同一转接端子直接搭接。

Description

显示基板、其制作方法及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板、其制作方法及显示装置。
背景技术
目前，市场对高分辨率、高开口率、低功耗的高端平板&曲面(Flat&Curved)显示器的需求度越来越高。其中，具备高商业、教育、广泛娱乐应用场景的曲面显示器更是需要通过以有机膜技术获得。有机膜工艺由于具备高平坦度、以及功耗低等诸多优势，因此也被各大面板制造商越来越多的应用于高端笔记本/触摸屏(NB/TPC)的研发应用中。
发明内容
本公开提供的一种显示基板、其制作方法及显示装置，具体方案如下：
一方面，本公开实施例提供了一种显示基板，包括：
衬底基板，所述衬底基板包括显示区，以及位于所述显示区至少一侧的边框区；
多个移位寄存器，位于所述边框区，所述多个移位寄存器级联设置；
多个跳线端子，位于所述移位寄存器与所述显示区之间，所述跳线端子包括第一跳线端子和第二跳线端子，所述第一跳线端子与所述移位寄存器电连接，所述第二跳线端子位于所述第一跳线端子所在层与所述衬底基板之间；
多个转接端子，位于所述移位寄存器与所述显示区之间，所述多个转接端子位于所述第一跳线端子所在层远离所述衬底基板的一侧；
绝缘层，位于所述显示区和所述边框区，所述绝缘层位于所述第二跳线端子所在层与所述多个转接端子所在层之间，所述绝缘层包括暴露出所述多 个跳线端子的通道；在所述通道内，同一所述跳线端子的所述第一跳线端子和所述第二跳线端子分别与同一所述转接端子直接搭接。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括：位于所述绝缘层远离所述衬底基板一侧的第一导电层，所述多个转接端子位于所述第一导电层。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述绝缘层包括在所述第二跳线端子所在层面向所述第一导电层的一侧依次设置的栅绝缘层、第一无机绝缘层和有机绝缘层；
所述通道在所述绝缘层的厚度方向上贯穿所述栅绝缘层、所述第一绝缘层和所述有机绝缘层。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括：位于所述第一导电层远离所述衬底基板一侧的第二无机绝缘层，所述第二无机绝缘层覆盖所述多个转接端子。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括：在所述绝缘层远离所述衬底基板的一侧依次设置且相互绝缘的第一导电层和第二导电层，所述多个转接端子位于所述第二导电层。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述绝缘层包括所述第一跳线端子所在层面向所述第一导电层的一侧依次设置的栅绝缘层、第一无机绝缘层和有机绝缘层，以及在所述第一导电层与所述第二导电层之间的第二无机绝缘层；
所述通道在所述绝缘层的厚度方向上贯穿所述栅绝缘层、所述第一无机绝缘层、所述有机绝缘层和所述第二无机绝缘层。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括在所述显示区且位于所述第一无机绝缘层与所述衬底基板之间的多个晶体管；
所述第一跳线端子与所述晶体管的源漏极同层设置，所述第二跳线端子与所述晶体管的栅极同层设置。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述转接端 子在所述第一跳线端子与所述第二跳线端子之间的区域与所述衬底基板、所述第一跳线端子、所述第二跳线端子直接接触。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述转接端子未覆盖所述第一跳线端子远离所述第二跳线端子一侧的边缘，且所述转接端子未覆盖所述第二跳线端子远离所述第一跳线端子一侧的边缘。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第一跳线端子在所述衬底基板上的正投影面积小于等于8μm×5μm，所述第二跳线端子在所述衬底基板上的正投影面积小于等于8μm×5μm，所述转接端子在所述衬底基板上的正投影面积小于等于20μm×15μm。
另一方面，本公开实施例提供了一种上述显示基板的制作方法，包括：
提供一个衬底基板，所述衬底基板包括显示区，以及位于所述显示区至少一侧的边框区；
在所述边框区形成多个跳线端子、以及级联设置的多个移位寄存器，其中，所述多个跳线端子位于所述多个移位寄存器与所述显示区之间，所述跳线端子包括第一跳线端子和第二跳线端子，所述第一跳线端子与所述移位寄存器电连接，所述第二跳线端子位于所述第一跳线端子所在层与所述衬底基板之间；
在所述第二跳线端子所在层上整面形成绝缘层，并在所述多个移位寄存器与所述显示区之间的区域形成暴露出所述多个跳线端子的通道；
在所述通道内形成多个转接端子，使得同一所述跳线端子的所述第一跳线端子和所述第二跳线端子分别与同一所述转接端子直接搭接。
在一些实施例中，在本公开实施例提供的上述制作方法中，在所述第二跳线端子所在层上整面形成绝缘层，并在所述多个移位寄存器与所述显示区之间的区域形成暴露出所述多个跳线端子的通道，具体包括：
在所述第二跳线端子所在层上整面形成层叠设置的栅绝缘层、第一无机绝缘层和有机绝缘层；
在所述多个移位寄存器与所述显示区之间的区域形成贯穿所述有机绝缘 层的第一通道；
在所述第一通道处形成贯穿所述第一无机绝缘层和所述栅绝缘层且暴露出所述多个跳线端子的第二通道，其中，所述栅绝缘层、所述第一无机绝缘层和所述有机绝缘构成绝缘层，所述第一通道和所述第二通道导通构成暴露出所述多个跳线端子的通道。
在一些实施例中，在本公开实施例提供的上述制作方法中，在所述第二跳线端子所在层上整面形成绝缘层，并在所述移位寄存器与所述显示区之间的区域形成暴露出所述多个跳线端子的通道，具体包括：
在所述第二跳线端子所在层上整面形成层叠设置的栅绝缘层、第一无机绝缘层和有机绝缘层；
在所述多个移位寄存器与所述显示区之间的区域形成贯穿所述有机绝缘层的第一通道；
在所述第一通道处形成贯穿所述第一无机绝缘层且暴露出多个所述第一跳线端子的第二通道；
所述有机绝缘层上整面形成第二无机绝缘层；
在第一通道处形成贯穿所述第二无机绝缘层和所述栅绝缘层且暴露出所述多个跳线端子的第三通道；其中，所述栅绝缘层、所述第一无机绝缘层、所述有机绝缘层和所述第二无机绝缘层构成绝缘层，所述第一通道、所述第二通道和所述第三通道导通构成暴露出所述多个跳线端子的通道。
另一方面，本公开实施例提供了一种显示装置，包括相对而置的显示基板和对向基板，以及位于所述显示基板与所述对向基板之间的液晶层，其中，所述显示基板为本公开实施例提供的上述显示基板，所述液晶层位于所述显示区。
附图说明
图1为相关技术中各转接端子短接的原理示意图；
图2为相关技术中各转接端子短接的结构示意图；
图3为本公开实施例提供的显示基板的结构示意图；
图4为沿图3中I-I'线的一种剖面图；
图5为图3所示显示基板中一个子像素的结构示意图；
图6为沿图3中I-I'线的又一种剖面图；
图7为图4和图6所示显示基板在制作过程中的一种结构示意图；
图8为图4和图6所示显示基板在制作过程中的又一种结构示意图；
图9为图4所示显示基板在制作过程中的又一种结构示意图；
图10为图4所示显示基板在制作过程中的又一种结构示意图；
图11为图4所示显示基板在制作过程中的又一种结构示意图；
图12为图6所示显示基板在制作过程中的又一种结构示意图；
图13为图6所示显示基板在制作过程中的又一种结构示意图；
图14为图6所示显示基板在制作过程中的又一种结构示意图；
图15为图6所示显示基板在制作过程中的又一种结构示意图；
图16为本公开实施例提供的显示面板中一个子像素的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
除非另作定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于 表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
如图1和图2所示，相关技术中栅极驱动电路(GOA)包括级联设置的多个移位寄存器，在栅极驱动电路区和显示区AA之间具有贯穿有机绝缘层(ORG)和第一无机绝缘层(PVX 1)的通道H，通道H处设置有连接移位寄存器的第一跳线端子(SD pad，SP)、连接栅线(GL)的第二跳线端子(Gate pad，GP)、以及连接第一跳线端子(SP)和第二跳线端子(GP)的转接端子(2ITO pad，ITO 2)，并且转接端子(ITO 2)通过贯穿第二无机绝缘层(PVX 2)的过孔与第一跳线端子(SP)电连接，并通过贯穿第二无机绝缘层(PVX 2)和栅绝缘层(GI)的过孔与第二跳线端子(GP)电连接。
然而，本公开发现，在通道H叠加后续第二无机绝缘层(PVX 2)和转接端子(ITO 2)所在层后膜层高、段差大，会造成后续用于制作转接端子(ITO 2)的光刻胶(PR)在通道H底部及侧壁上堆积(如图1中Z区域所示)，致使Z区域曝光量不足，进而在Z区域会出现残留R(如图2所示)，该残留R会导致相邻移位寄存器的第一连线端子(SP)、第二连线端子(GP)短接，表现为显示装置出现半屏或满屏的横纹不良。部分转接端子(ITO 2)所在层的工艺容差(Margin)大的产品可通过加大5mj～10mj曝光量进行改善残留不良，但会对显示基板的瓶颈曝光工艺段的产能造成极大压力影响。更为重要的是，加大曝光量将直接导致显示区AA内与转接端子(ITO 2)同层设置的狭缝电极的狭缝(Slit)变小，达不到原有需求的产品设计规格，同时产品生产工艺容差也被动减小，并且转接端子(ITO 2)所在层的工艺规格(Spec)的变更使产品存在一系列潜在风险，例如中低灰阶画面不均匀(Mura)，影响VT对称性、Gamma曲线(涉及T-con调制定版)、透过率等重要产品特性。
为了改善相关技术中存在的上述技术问题，本公开实施例提供了一种显示基板，如图3和图4所示，包括：
衬底基板101，该衬底基板101包括显示区AA，以及位于显示区AA至少一侧的边框区BB；
多个移位寄存器SR n(n为正整数)，位于边框区BB，多个移位寄存器SR n级联设置；
多个跳线端子102，位于移位寄存器SR n与显示区AA之间，跳线端子102包括第一跳线端子1021和第二跳线端子1022，第一跳线端子1021与移位寄存器SR n电连接，第二跳线端子1022位于第一跳线端子1021所在层与衬底基板101之间；
多个转接端子103，位于移位寄存器SR n与显示区AA之间，多个转接端子103位于第一跳线端子1021所在层远离衬底基板101的一侧；
绝缘层104，位于显示区AA和边框区BB，绝缘层104位于第二跳线端子1022所在层与多个转接端子103所在层之间，绝缘层104包括暴露出多个跳线端子102的通道H；在通道H内，同一跳线端子102的第一跳线端子1021和第二跳线端子1022分别与同一转接端子103直接搭接。
在本公开实施例提供的上述显示基板中，在绝缘层104的通道H内，采用转接端子103直接覆盖第一跳线端子1021和第二跳线端子1022的方式，相较于相关技术中转接端子103与第一跳线端子1021、第二跳线端子1022分别经由过孔电连接的方式，可以保证转接端子103与第一跳线端子1021、第二跳线端子1022之间的接触面积较大，有效提高了电连接的稳定性。这样就可以将转接端子103、第一跳线端子1021、第二跳线端子1022做的较小，使得转接端子103、第一跳线端子1021、第二跳线端子1022距离通道H侧壁的距离可以设计更大，即使通道H侧壁附近存在残留，也可显著降低残留与转接端子103、第一跳线端子1021、第二跳线端子1022的短接风险，从而可有效解决残留导致的横纹不良，有效提高产品良率，提高产品收益。并且还避免了残留导致的横纹不良发生后，再进行显示区AA内狭缝电极规格变更并检讨，导致产品特性变化并存在的潜在风险。另外，本公开无需增大曝光量，因此有效缓解瓶颈工艺生产压力，从而增强了产能，并节约生产成本。
相关技术中，为了增强转接端子103与第一跳线端子1021、第二跳线端子1022的电连接的稳定性，设计转接端子103在衬底基板101上的正投影面 积为40μm×30μm，第一跳线端子1021和第二跳线端子1022在衬底基板101上的正投影面积分别为16μm×10μm，本公开中转接端子103与第一跳线端子1021、第二跳线端子1022直接搭接，可以保证转接端子103与第一跳线端子1021、第二跳线端子1022之间的接触面积较大，因此，转接端子103与第一跳线端子1021、第二跳线端子1022可以适当减小尺寸，可选地，在本公开中转接端子103与第一跳线端子1021、第二跳线端子1022的尺寸可以小于等于相关技术中尺寸的一半，例如第一跳线端子1021在衬底基板101上的正投影面积可以小于等于8μm×5μm，第二跳线端子1022在衬底基板101上的正投影面积可以小于等于8μm×5μm，转接端子103在衬底基板101上的正投影面积可以小于等于20μm×15μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图4和图5所示，还可以包括：位于绝缘层104远离衬底基板101一侧的第一导电层(1ITO)105，多个转接端子103位于第一导电层105，这样就可以采用相关技术中的第一导电层105的材料完成转接端子103的制作，无需额外增加材料成本、以及转接端子103单独的掩膜工艺。在此情况下，如图4和图5所示，绝缘层104可以包括在第二跳线端子1022所在层面向第一导电层105的一侧依次设置的栅绝缘层1041、第一无机绝缘层1042和有机绝缘层1043；通道H在绝缘层104的厚度方向上贯穿栅绝缘层1041、第一绝缘层1042和有机绝缘层1043。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图4和图5所示，还可以包括：位于第一导电层105远离衬底基板101一侧的第二无机绝缘层1044，第二无机绝缘层1044覆盖多个转接端子103，以将第二无机绝缘层1044作为转接端子103的封装保护层，可有效提升转接端子103的稳定性。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图5和图6所示，还可以包括：在绝缘层104远离衬底基板101的一侧依次设置且相互绝缘的第一导电层105和第二导电层(2ITO)106，多个转接端子103可以位 于第二导电层106，这样就可以采用相关技术中的第二导电层106的材料完成转接端子103的制作，无需额外增加材料成本、以及转接端子103单独的掩膜工艺。在此情况下，如图5和图6所示，绝缘层104可以包括在第二跳线端子1022所在层面向第一导电层105的一侧依次设置的栅绝缘层1041、第一无机绝缘层1042、有机绝缘层1043和第二无机绝缘层1044；通道H在绝缘层104的厚度方向上贯穿栅绝缘层1041、第一绝缘层1042、和有机绝缘层1043和第二无机绝缘层1044。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图4和图6所示，转接端子103在第一跳线端子1021与第二跳线端子1022之间的区域与衬底基板101、第一跳线端子1021、第二跳线端子1022均直接接触，这样使得转接端子103与第一跳线端子1021远离衬底基板101的上表面、第一跳线端子1021的侧面、第二跳线端子1022远离衬底基板101的上表面、第二跳线端子1022的侧面均接触设置，进一步增大了转接端子103与第一跳线端子1021、第二跳线端子1022的接触面积，从而可进一步减小转接端子103与第一跳线端子1021、第二跳线端子1022的尺寸，解决相关技术中残留导致的横纹不良问题。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图3、图4和图6所示，转接端子103未覆盖第一跳线端子1021远离第二跳线端子1022一侧的边缘，且转接端子103未覆盖第二跳线端子1022远离第一跳线端子1021一侧的边缘，这样更利于刻蚀形成转接端子103，避免刻蚀形成转接端子103的过程中在通道H的底部及通道H的侧壁产生残留。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图4至图6所示，还可以包括在显示区AA且位于第一无机绝缘层1042与衬底基板101之间的多个晶体管TFT；第一跳线端子1021可以与晶体管TFT的源漏极同层设置，第二跳线端子1022可以与晶体管TFT的栅极同层设置，这样就可以采用晶体管TFT的源漏极的材料完成第一跳线端子1021的制作，并采用晶体管TFT的栅极的材料完成第二跳线端子1022的制作，无需额外增加材料成本、 以及第一跳线端子1021和第二跳线端子1022分别单独掩膜的工艺。
需要说明的是，在本公开中，“同层设置”是指采用同一成膜工艺形成用于制作特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。即一次构图工艺对应一道掩模板(mask，也称光罩)。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而所形成层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形可能处于相同的高度或者具有相同的厚度、也可能处于不同的高度或者具有不同的厚度。
可选地，本公开实施例提供的晶体管TFT可以是薄膜晶体管(TFT)，也可以是金属氧化物半导体场效应管(MOS)，在此不做限定。晶体管TFT可以为P型晶体管或N型晶体管，在具体实施时，P型晶体管在其栅极与其源极之间的电压差V gs与其阈值电压V th满足关系V gs<V th时导通，并在满足关系V gs≥V th时截止；N型晶体管在其栅极与其源极之间的电压差V gs与其阈值电压V th满足关系V gs>V th时导通，并在满足关系V gs≤V th时截止。另外，晶体管TFT的有源层可以为非晶硅(a-Si)有源层、多晶硅(P-Si)有源层或氧化物(IGZO)有源层，在此不做限定。晶体管TFT可以为底栅型晶体管、顶栅型晶体管或双栅型晶体管，在此不做限定。
基于同一发明构思，本公开实施例提供了一种上述显示基板的制作方法，由于该制作方法解决问题的原理与上述显示基板解决问题的原理相似，因此，本公开实施例提供的该制作方法的实施可以参见本公开实施例提供的上述显示基板的实施，重复之处不再赘述。
具体地，本公开实施例提供了一种上述显示基板的制作方法，包括以下步骤：
提供一个衬底基板，衬底基板包括显示区，以及位于显示区至少一侧的边框区；
在边框区形成多个跳线端子、以及级联设置的多个移位寄存器，其中，多个跳线端子位于多个移位寄存器与显示区之间，跳线端子包括第一跳线端子和第二跳线端子，第一跳线端子与移位寄存器电连接，第二跳线端子位于 第一跳线端子所在层与衬底基板之间；
在第二跳线端子所在层上整面形成绝缘层，并在多个移位寄存器与显示区之间的区域形成暴露出多个跳线端子的通道；
在通道内形成多个转接端子，使得同一跳线端子的第一跳线端子和第二跳线端子分别与同一转接端子直接搭接。
在一些实施例中，在本公开实施例提供的上述制作方法中，在第二跳线端子所在层上整面形成绝缘层，并在多个移位寄存器与显示区之间的区域形成暴露出多个跳线端子的通道，具体可以通过以下方式进行实现：
第一步，如图7所示，在第二跳线端子1022所在层上整面形成层叠设置的栅绝缘层1041、第一无机绝缘层1042和有机绝缘层1043；
第二步，如图8所示，在多个移位寄存器SR n与显示区AA之间的区域形成贯穿有机绝缘层1043的第一通道H 1；
第三步，如图9所示，在第一通道H 1处形成贯穿第一无机绝缘层1042和栅绝缘层1041且暴露出多个跳线端子1042(包括第一跳线端子1021和第二跳线端子1022)的第二通道H 2，其中，栅绝缘层1041、第一无机绝缘层1042和有机绝缘1043构成绝缘层104，第一通道H 1和第二通道H 2导通构成暴露出多个跳线端子102的通道H。
可选地，如图10所示，在绝缘层104中形成暴露多个跳线端子102的通道H之后，还可以在有机绝缘层1043上整面形成第一导电层105，并对第一导电层105进行构图，形成在通道H内直接覆盖第一跳线端子1021和第二跳线端子1022的转接端子103(如图11所示)，同时还可以在显示区AA内形成多个像素电极105’(如图5所示)。之后，如图4所示，可在第一导电层105上整面形成第二无机绝缘层1044，使得第二无机绝缘层1044在边框区BB内保护转接端子103，同时在显示区AA内实现像素电极105’与后续公共电极106’(如图5所示)之间的相互绝缘。像素电极105’和公共电极106’的制备可参考相关技术，在此不做赘述。
在一些实施例中，在本公开实施例提供的上述制作方法中，在第二跳线 端子所在层上整面形成绝缘层，并在移位寄存器与显示区之间的区域形成暴露出多个跳线端子的通道，还可以通过以下方式进行实现：
第一步，如图7所示，在第二跳线端子1022所在层上整面形成层叠设置的栅绝缘层1041、第一无机绝缘层1042和有机绝缘层1043；
第二步，如图8所示，在多个移位寄存器SR n与显示区AA之间的区域形成贯穿有机绝缘层1043的第一通道H 1；
第三步，如图12所示，在第一通道H 1处形成贯穿第一无机绝缘层1042且暴露出多个第一跳线端子1021的第二通道H 2 ’；
第四步，如图13所示，在有机绝缘层1043上整面形成第二无机绝缘层1044；
第五步，如图14所示，在第一通道H 1处形成贯穿第二无机绝缘层1044和栅绝缘层1041且暴露出多个跳线端子102的第三通道H 3；其中，栅绝缘层1041、第一无机绝缘层1042、有机绝缘层1043和第二无机绝缘层1044构成绝缘层104，第一通道H 1、第二通道H 2和第三通道H 3导通构成暴露出多个跳线端子102的通道H。
可选地，如图15所示，在绝缘层104中形成暴露多个跳线端子102的通道H之后，还可以在第二无机绝缘层1044上整面形成第二导电层106，并对第二导电层106进行构图，形成在通道H内直接覆盖第一跳线端子1021和第二跳线端子1022的转接端子103(如图6所示)，同时还可以在显示区AA内形成狭缝状的公共电极106’(如图5所示)。
需要说明的是，在本公开中移位寄存器SR n、显示区AA内与像素电极105’电连接的晶体管TFT、第一跳线端子1021、第二跳线端子1022的制作工艺可以参考相关技术，在此不做赘述。
基于同一发明构思，本公开实施例提供了一种显示装置，如图16所示，包括相对而置的显示基板001和对向基板002，以及位于显示基板001与对向基板002之间的液晶层003，其中，显示基板001为本公开实施例提供的上述显示基板001，液晶层003位于显示区AA。由于该显示装置解决问题的原理 与上述显示基板解决问题的原理相似，因此，本公开实施例提供的该显示装置的实施可以参见本公开实施例提供的上述显示基板的实施，重复之处不再赘述。
在一些实施例中，在本公开实施例提供的上述显示装置中，如图16所示，对向基板002可以包括玻璃基板201、色阻202和黑矩阵203等，显示装置还可以包括封框胶004等，对于显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
在一些实施例中，本公开实施例提供的上述显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、智能手表、健身腕带、个人数字助理等任何具有显示功能的产品或部件。该显示装置包括但不限于：射频单元、网络模块、音频输出&输入单元、传感器、显示单元、用户输入单元、接口单元、存储器、处理器、以及电源等部件。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (14)

  1. 一种显示基板，其中，包括：
    衬底基板，所述衬底基板包括显示区，以及位于所述显示区至少一侧的边框区；
    多个移位寄存器，位于所述边框区，所述多个移位寄存器级联设置；
    多个跳线端子，位于所述移位寄存器与所述显示区之间，所述跳线端子包括第一跳线端子和第二跳线端子，所述第一跳线端子与所述移位寄存器电连接，所述第二跳线端子位于所述第一跳线端子所在层与所述衬底基板之间；
    多个转接端子，位于所述移位寄存器与所述显示区之间，所述多个转接端子位于所述第一跳线端子所在层远离所述衬底基板的一侧；
    绝缘层，位于所述显示区和所述边框区，所述绝缘层位于所述第二跳线端子所在层与所述多个转接端子所在层之间，所述绝缘层包括暴露出所述多个跳线端子的通道；在所述通道内，同一所述跳线端子的所述第一跳线端子和所述第二跳线端子分别与同一所述转接端子直接搭接。
  2. 如权利要求1所述的显示基板，其中，还包括：位于所述绝缘层远离所述衬底基板一侧的第一导电层，所述多个转接端子位于所述第一导电层。
  3. 如权利要求2所述的显示基板，其中，所述绝缘层包括在所述第二跳线端子所在层面向所述第一导电层的一侧依次设置的栅绝缘层、第一无机绝缘层和有机绝缘层；
    所述通道在所述绝缘层的厚度方向上贯穿所述栅绝缘层、所述第一绝缘层和所述有机绝缘层。
  4. 如权利要求3所述的显示基板，其中，还包括：位于所述第一导电层远离所述衬底基板一侧的第二无机绝缘层，所述第二无机绝缘层覆盖所述多个转接端子。
  5. 如权利要求1所述的显示基板，其中，还包括：在所述绝缘层远离所述衬底基板的一侧依次设置且相互绝缘的第一导电层和第二导电层，所述多 个转接端子位于所述第二导电层。
  6. 如权利要求5所述的显示基板，其中，所述绝缘层包括所述第一跳线端子所在层面向所述第一导电层的一侧依次设置的栅绝缘层、第一无机绝缘层和有机绝缘层，以及在所述第一导电层与所述第二导电层之间的第二无机绝缘层；
    所述通道在所述绝缘层的厚度方向上贯穿所述栅绝缘层、所述第一无机绝缘层、所述有机绝缘层和所述第二无机绝缘层。
  7. 如权利要求3、4或6所述的显示基板，其中，还包括在所述显示区且位于所述第一无机绝缘层与所述衬底基板之间的多个晶体管；
    所述第一跳线端子与所述晶体管的源漏极同层设置，所述第二跳线端子与所述晶体管的栅极同层设置。
  8. 如权利要求7所述的显示基板，其中，所述转接端子在所述第一跳线端子与所述第二跳线端子之间的区域与所述衬底基板、所述第一跳线端子、所述第二跳线端子直接接触。
  9. 如权利要求1～8任一项所述的显示基板，其中，所述转接端子未覆盖所述第一跳线端子远离所述第二跳线端子一侧的边缘，且所述转接端子未覆盖所述第二跳线端子远离所述第一跳线端子一侧的边缘。
  10. 如权利要求1～9任一项所述的显示基板，其中，所述第一跳线端子在所述衬底基板上的正投影面积小于等于8μm×5μm，所述第二跳线端子在所述衬底基板上的正投影面积小于等于8μm×5μm，所述转接端子在所述衬底基板上的正投影面积小于等于20μm×15μm。
  11. 一种如权利要求1～10任一项所述显示基板的制作方法，其中，包括：
    提供一个衬底基板，所述衬底基板包括显示区，以及位于所述显示区至少一侧的边框区；
    在所述边框区形成多个跳线端子、以及级联设置的多个移位寄存器，其中，所述多个跳线端子位于所述多个移位寄存器与所述显示区之间，所述跳线端子包括第一跳线端子和第二跳线端子，所述第一跳线端子与所述移位寄 存器电连接，所述第二跳线端子位于所述第一跳线端子所在层与所述衬底基板之间；
    在所述第二跳线端子所在层上整面形成绝缘层，并在所述多个移位寄存器与所述显示区之间的区域形成暴露出所述多个跳线端子的通道；
    在所述通道内形成多个转接端子，使得同一所述跳线端子的所述第一跳线端子和所述第二跳线端子分别与同一所述转接端子直接搭接。
  12. 如权利要求11所述的制作方法，其中，在所述第二跳线端子所在层上整面形成绝缘层，并在所述多个移位寄存器与所述显示区之间的区域形成暴露出所述多个跳线端子的通道，具体包括：
    在所述第二跳线端子所在层上整面形成层叠设置的栅绝缘层、第一无机绝缘层和有机绝缘层；
    在所述多个移位寄存器与所述显示区之间的区域形成贯穿所述有机绝缘层的第一通道；
    在所述第一通道处形成贯穿所述第一无机绝缘层和所述栅绝缘层且暴露出所述多个跳线端子的第二通道，其中，所述栅绝缘层、所述第一无机绝缘层和所述有机绝缘构成绝缘层，所述第一通道和所述第二通道导通构成暴露出所述多个跳线端子的通道。
  13. 如权利要求11所述的制作方法，其中，在所述第二跳线端子所在层上整面形成绝缘层，并在所述移位寄存器与所述显示区之间的区域形成暴露出所述多个跳线端子的通道，具体包括：
    在所述第二跳线端子所在层上整面形成层叠设置的栅绝缘层、第一无机绝缘层和有机绝缘层；
    在所述多个移位寄存器与所述显示区之间的区域形成贯穿所述有机绝缘层的第一通道；
    在所述第一通道处形成贯穿所述第一无机绝缘层且暴露出多个所述第一跳线端子的第二通道；
    所述有机绝缘层上整面形成第二无机绝缘层；
    在第一通道处形成贯穿所述第二无机绝缘层和所述栅绝缘层且暴露出所述多个跳线端子的第三通道；其中，所述栅绝缘层、所述第一无机绝缘层、所述有机绝缘层和所述第二无机绝缘层构成绝缘层，所述第一通道、所述第二通道和所述第三通道导通构成暴露出所述多个跳线端子的通道。
  14. 一种显示装置，其中，包括相对而置的显示基板和对向基板，以及位于所述显示基板与所述对向基板之间的液晶层，其中，所述显示基板为如权利要求1～10任一项所述的显示基板，所述液晶层位于所述显示区。
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CN111123591A (zh) * 2019-12-26 2020-05-08 厦门天马微电子有限公司 阵列基板、显示面板及显示装置
CN112054031A (zh) * 2019-06-06 2020-12-08 夏普株式会社 有源矩阵基板及其制造方法
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