WO2023184426A1 - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

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Publication number
WO2023184426A1
WO2023184426A1 PCT/CN2022/084629 CN2022084629W WO2023184426A1 WO 2023184426 A1 WO2023184426 A1 WO 2023184426A1 CN 2022084629 W CN2022084629 W CN 2022084629W WO 2023184426 A1 WO2023184426 A1 WO 2023184426A1
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Prior art keywords
pixel
common electrode
array substrate
pixel unit
line
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PCT/CN2022/084629
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English (en)
French (fr)
Inventor
王骁
马禹
闫岩
陈维涛
刘晓那
王建俊
沈丽娇
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000659.XA priority Critical patent/CN117157581A/zh
Priority to PCT/CN2022/084629 priority patent/WO2023184426A1/zh
Publication of WO2023184426A1 publication Critical patent/WO2023184426A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • Embodiments of the invention relate to an array substrate, a display panel and a display device.
  • a thin film transistor liquid crystal display includes an array substrate, a counter substrate, and a liquid crystal layer interposed between the array substrate and the counter substrate.
  • Thin film transistor liquid crystal displays can use changes in the electric field intensity on the liquid crystal layer between the array substrate and the opposite substrate to change the orientation of the liquid crystal molecules in the liquid crystal layer, thereby controlling the intensity of light transmission to display images.
  • the array substrate can include gate lines, data lines, driving transistors, pixel electrodes, common electrodes and other components; the gate lines are connected to the gates of the driving transistors, thereby controlling the on and off of the driving transistors; the data lines are connected to the sources of the driving transistors.
  • the pixel electrode is connected to the drain of the driving transistor.
  • the driving transistor When the driving transistor is turned on under the drive of the gate, the data line can apply a driving voltage to the pixel electrode through the driving transistor; the common electrode line is connected to the common electrode and is configured as By applying a common voltage to the common electrode, the pixel electrode and the common electrode can form a driving electric field, thereby changing the orientation of the liquid crystal molecules in the liquid crystal layer.
  • Embodiments of the present disclosure provide an array substrate, a display panel, and a display device.
  • the array substrate includes a base substrate, a plurality of pixel units and a common electrode line; the plurality of pixel units are located on one side of the base substrate; the common electrode line includes a horizontal common electrode line and a vertical common electrode line, and the horizontal common electrode line and the vertical common electrode line electrically connected to the common electrode line; a plurality of pixel units are arrayed along the first direction and the second direction to form a plurality of pixel rows and a plurality of pixel columns, each pixel row extends along the first direction, and each pixel column extends along the second direction.
  • the horizontal common electrode line extends along the first direction
  • the vertical common electrode line extends along the second direction
  • each pixel unit includes an effective display area
  • the horizontal common electrode line overlaps with multiple effective display areas of the same pixel row.
  • the horizontal common electrode lines overlap with multiple effective display areas of the same pixel row and are not set outside the effective display area in areas that need to be covered by the black matrix; although the horizontal common electrode lines themselves will block the effective display area.
  • the black matrix does not need to cover the lateral common electrode lines and the intervals between the lateral common electrode lines and adjacent gate lines, thereby reducing the width of the black matrix and effectively improving the aperture ratio of the display panel using the array substrate.
  • At least one embodiment of the present disclosure provides an array substrate, which includes: a base substrate; a plurality of pixel units located on one side of the base substrate; and common electrode lines, including lateral common electrode lines and vertical common electrode lines.
  • the horizontal common electrode line is electrically connected to the vertical common electrode line
  • the plurality of pixel units are arranged in an array along the first direction and the second direction to form a plurality of pixel rows and a plurality of pixel columns, each of which The pixel rows extend along the first direction, each of the pixel columns extends along the second direction, the lateral common electrode lines extend along the first direction, and the vertical common electrode lines extend along the second direction.
  • each of the pixel units includes an effective display area, and the horizontal common electrode line overlaps multiple effective display areas of the same pixel row.
  • the effective display area includes a first domain and a second domain arranged in the second direction, and the lateral common electrode line is located on the first domain. domain and the second domain.
  • an array substrate provided by an embodiment of the present disclosure further includes: a plurality of gate lines arranged along the second direction; and a plurality of data lines arranged along the first direction, and each gate line is arranged along the first direction.
  • the first direction extends, each of the data lines extends along the second direction, the plurality of gate lines and the plurality of data lines are arranged in different layers, and the transverse common electrode lines and the gate lines are arranged in the same layer.
  • the vertical common electrode lines include vertical conductive portions, the vertical conductive portions are arranged in the same layer as the gate lines, and the vertical conductive portions Located between two adjacent pixel units in the first direction, the vertical conductive portion is located between the two gate lines and intersects with the lateral common electrode line, and at the intersection position Forming an integrated cross-shaped conductive structure.
  • the vertical conductive portion is located between two adjacent data lines in the second direction, and the vertical conductive portion is between the two adjacent data lines in the second direction.
  • the orthographic projection on the base substrate is spaced apart from the orthographic projection of the data line on the base substrate.
  • the vertical common electrode line includes a vertical connection portion, the vertical connection portion is arranged in a different layer from the gate line, and will be connected to the first Two adjacent vertical conductive portions in two directions are connected.
  • two ends of the vertical connection portion are respectively connected to two vertical conductive lines adjacent in the second direction through a via connection structure.
  • the plurality of pixel units include a first color pixel unit, a second color pixel unit and a third color pixel unit, and the orthographic projection of the via hole connection structure on the base substrate is consistent with the third color pixel unit. Orthographic projections of the effective display areas of the pixel units on the base substrate at least partially overlap.
  • the light transmittance of the third color pixel unit is smaller than the light transmittance of the first color pixel unit and the light transmittance of the second color pixel unit. Rate.
  • the first color pixel unit is configured to emit light of the first color
  • the second color pixel unit is configured to emit light of the second color
  • the third color pixel unit is configured to emit light of a third color, and the wavelength of the third color is smaller than the wavelength of the first color and the wavelength of the second color.
  • each pixel unit further includes: a pixel electrode located on a side of the film layer where the data line is located away from the base substrate; and a common electrode,
  • the vertical connection portion is located on a side of the pixel electrode away from the base substrate, and is disposed on the same layer as the common electrode.
  • At least one of the pixel units further includes: a driving transistor including a gate, a source and a drain, and the gate is connected to the gate line, so The pixel electrode is connected to the drain electrode, the common electrode is connected to the common electrode line, the drain electrode includes a drain electrode body part and a drain extension part, and the drain extension part extends from the drain body part Extending toward the vertical connection portion, the pixel electrode includes a pixel electrode extension portion, and the pixel electrode extension portion is connected to the drain electrode extension portion in an overlapping manner.
  • the orthographic projection of the drain extension portion on the base substrate is spaced apart from the orthographic projection of the vertical connection portion on the base substrate. is provided, and the distance between the orthographic projection of the drain extension portion on the base substrate and the orthographic projection of the vertical connection portion on the base substrate ranges from 0 to 3 microns.
  • the orthographic projection of the drain extension portion on the base substrate is equal to the orthographic projection of the vertical connection portion on the base substrate.
  • the distance between them ranges from 1-2.5 microns.
  • each gate line includes a spacer support part, and the area where the spacer support part is located is configured to place spacers, and the spacer
  • the orthographic projection of the object support portion on the base substrate is located at the orthographic projection of the extension line of the first vertical conductive portion on the base substrate and the data line closest to the vertical conductive portion. between orthographic projections on the base substrate.
  • each gate line includes a spacer support part, and the area where the spacer support part is located is configured to place spacers, and the spacer
  • the orthographic projection of the object support portion on the base substrate at least partially overlaps the orthographic projection of the extension line of the vertical conductive portion on the base substrate.
  • two gate lines are provided between two adjacent pixel columns in the second direction.
  • each of the pixel rows includes a plurality of pixel groups, and each of the pixel groups includes a first color pixel unit, a second color pixel unit and a third color pixel unit arranged in sequence.
  • the plurality of pixel groups include a first pixel group and a second pixel group arranged sequentially along the first direction
  • the plurality of data lines include a first data line, a second data line arranged sequentially, third data lines and fourth data lines
  • the first data line is located on the side of the first color pixel unit in the first pixel group away from the second color pixel unit
  • the second data line is located on
  • the third data line is located between the first color pixel unit and the third color pixel unit in the second pixel group.
  • the fourth data line is located on a side of the third-color pixel unit in the second pixel group away from the second-color pixel unit.
  • the vertical common electrode lines include a first vertical conductive part, a second vertical conductive part and a third vertical conductive part, and the first vertical conductive part
  • the conductive part, the second vertical conductive part and the third vertical conductive part are all arranged in the same layer as the gate line, and the first vertical conductive part is located in the first pixel group.
  • the second vertical conductive portion is located between the third color pixel unit in the first pixel group and the third color pixel unit in the second pixel group.
  • the third vertical conductive part is located between the second color pixel unit and the third color pixel unit in the second pixel group, the first vertical conductive part, The second vertical conductive part and the third vertical conductive part are both located between the two gate lines, and respectively intersect with the transverse common electrode lines, and form three integrated cross shapes at the intersection positions. Conductive structure.
  • the vertical common electrode line further includes: a first vertical connection portion, which is arranged in a different layer from the gate line and will be connected in the second direction.
  • the two adjacent second vertical conductive portions are connected; and a second vertical connecting portion is arranged in a different layer from the gate line and connects the two adjacent second vertical conductive portions in the second direction.
  • the three vertical conductive parts are connected.
  • the two ends of the first vertical connection part are respectively connected to the two adjacent ones in the second direction through a first via connection structure.
  • the second vertical conductive part is connected, and the orthographic projection of the first via hole connection structure on the base substrate is at least the orthographic projection of the effective display area of the third color pixel unit on the base substrate.
  • the two ends of the second vertical connection part are respectively connected to the two adjacent third vertical conductive parts in the second direction through a second via hole connection structure, and the second The orthographic projection of the via-hole connection structure on the base substrate at least partially overlaps the orthographic projection of the effective display area of the third color pixel unit on the base substrate.
  • each gate line includes a plurality of spacer support parts, and the area where each spacer support part is located is configured to place spacers, so
  • the plurality of spacer support parts include a main spacer support part and an auxiliary spacer support part, and the orthographic projection of the main spacer support part on the substrate is located at the second vertical connection part
  • the data line whose orthographic projection on the base substrate is closest to the second vertical connection portion is between the orthographic projection on the base substrate, or the main spacer support portion is between
  • the orthographic projection on the base substrate is located on the third vertical connecting portion on the base substrate.
  • the data line closest to the third vertical connecting portion is on the base substrate. between the orthographic projections.
  • one main spacer support part and one auxiliary spacer support part are respectively provided at the second vertical connection part or the third Three vertical connecting parts are on both sides in the first direction.
  • the plurality of pixel rows include first pixel rows and second pixel rows arranged sequentially along the second direction
  • the plurality of gate lines include sequentially arranged A first gate line, a second gate line, a third gate line and a fourth gate line.
  • the first gate line is located on a side of the second pixel row away from the first pixel row.
  • the second gate line and the third gate line is located between the first pixel row and the second pixel row, the third gate line is located on a side of the second gate line away from the first gate line, and the The fourth gate line is located on a side of the first pixel row away from the second pixel row.
  • the first gate line and the first color pixel unit and the first color pixel unit in the first pixel group in the first pixel row are The first color pixel unit in the two pixel groups is connected, and the second gate line is connected to the second color pixel unit and the second pixel group in the first pixel group of the first pixel row.
  • the second color pixel unit is connected to the second color pixel unit in the second pixel row, and the third gate line is connected to the first color pixel unit in the first pixel group in the second pixel row and the second color pixel unit in the second pixel group.
  • the first color pixel unit is connected to the fourth gate line and the second color pixel unit in the first pixel group of the second pixel row and the second color pixel unit in the second pixel group. Two color pixel units are connected.
  • the first gate line is also connected to the third color pixel unit in the second pixel group in the first pixel row, so The second gate line is also connected to the third color pixel unit in the first pixel group in the first pixel row, and the third gate line is also connected to the third color pixel unit in the second pixel row.
  • the third color pixel unit in the second pixel group is connected, and the fourth gate line is also connected to the third color pixel unit in the first pixel group in the second pixel row.
  • At least one embodiment of the present disclosure also provides a display panel, including the array substrate described in any one of the above.
  • a display panel provided by an embodiment of the present disclosure further includes: a counter substrate disposed opposite to the array substrate; a main spacer located between the array substrate and the counter substrate; and a secondary spacer.
  • a spacer is located between the array substrate and the opposite substrate.
  • one main spacer is provided for every N pixel units, and the value range of N is 30-40.
  • the value of N is 36.
  • the main spacer is in contact with both the array substrate and the counter substrate, and the auxiliary spacer is in contact with the array substrate and the counter substrate. At least one of the substrates is placed in contact.
  • the main spacer has a first height in a direction perpendicular to the base substrate
  • the auxiliary spacer has a first height in a direction perpendicular to the base substrate.
  • At least one embodiment of the present disclosure also provides a display device, which includes the above-mentioned display panel.
  • Figure 1 is a schematic plan view of an array substrate in a liquid crystal panel
  • Figure 2 is a schematic cross-sectional view of a liquid crystal panel along the AB direction in Figure 1;
  • Figure 3 is a schematic cross-sectional view of a liquid crystal panel along the CD direction in Figure 1;
  • Figure 4 is a schematic plan view of an array substrate provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic diagram of the connection relationship between components in an array substrate according to an embodiment of the present disclosure
  • Figure 6 is a schematic cross-sectional view of a display panel along the EF direction in Figure 4 according to an embodiment of the present disclosure
  • Figure 7 is a schematic cross-sectional view of a display panel along the GH direction in Figure 4 according to an embodiment of the present disclosure
  • Figure 8 is a transmittance comparison chart of an array substrate provided by an embodiment of the present disclosure.
  • Figure 9 is an enlarged schematic diagram of an array substrate provided by an embodiment of the present disclosure in the area indicated by box 701 in Figure 4;
  • Figure 10A is a schematic cross-sectional view of an array substrate along the JK direction in Figure 9 according to an embodiment of the present disclosure
  • Figure 10B is a schematic cross-sectional view of another array substrate along the JK direction in Figure 9 according to an embodiment of the present disclosure
  • Figure 11 is an enlarged schematic diagram of an array substrate provided by an embodiment of the present disclosure in the area indicated by box 702 in Figure 4;
  • Figure 12 is a schematic cross-sectional view of an array substrate along the MN direction in Figure 11 according to an embodiment of the present disclosure
  • Figure 13 is a positional relationship diagram between a spacer support part and a spacer provided by an embodiment of the present disclosure
  • 14A-14D are schematic diagrams of the steps of a method for manufacturing an array substrate according to an embodiment of the present disclosure.
  • Figure 15 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • Figure 16 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
  • Figure 17 is a schematic diagram of the distribution of main spacers in a display panel according to an embodiment of the present disclosure.
  • FIG. 18 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • features such as “parallel”, “perpendicular” and “identical” used in the embodiments of the present disclosure include “parallel”, “perpendicular”, “identical” and the like in the strict sense, as well as “approximately parallel”, “Approximately perpendicular”, “approximately the same”, etc. include certain errors.
  • the above “approximately” may mean that the difference between the compared objects is 10% of the average value of the compared objects, or within 5%.
  • the quantity of a component or element is not specified in the following embodiments of the present disclosure, it means that the component or element can be one or more, or it can be understood as at least one.
  • At least one means one or more, and “plurality” means at least two.
  • “Same layer arrangement” in the embodiment of the present disclosure refers to the relationship between multiple film layers formed of the same material after going through the same step (for example, one-step patterning process). “Same layer” here does not always mean that the thickness of multiple film layers is the same or that the height of the multiple film layers in the cross-sectional view is the same.
  • thin film transistor liquid crystal displays can use a black matrix formed on a counter substrate to block the non-display area to avoid light leakage.
  • the common electrode covers the data lines between adjacent pixel units, thereby shielding the electric field of the data lines and forming a dark area; therefore, the size of the black matrix above the data lines can be greatly reduced, thus Can increase the opening rate.
  • the common electrode covers the data line, the parasitic capacitance formed between the common electrode and the data line is large, so the impedance on the common electrode or the common electrode line is large, resulting in increased coupling of the common electrode or the common electrode line, causing the common The voltage of the electrode or common electrode line recovers slowly, causing defects such as afterimages.
  • Figure 1 is a schematic plan view of an array substrate in a liquid crystal panel
  • Figure 2 is a schematic cross-sectional view of a liquid crystal panel along the AB direction in Figure 1
  • Figure 3 is a schematic cross-sectional view of a liquid crystal panel along the CD direction in Figure 1.
  • the liquid crystal panel 40 includes an array substrate 10 .
  • the array substrate 10 includes a base substrate 11 , a plurality of pixel units 12 , a gate line 13 , a data line 14 , a pixel electrode 15 , a common electrode 16 and a common electrode.
  • Electrode wire 17 A plurality of pixel units 12 are arranged in an array along the first direction X and the second direction Y and form a plurality of pixel rows 51 and a plurality of pixel columns 52; One direction X extends; a plurality of pixel columns 52 are arranged along the first direction X, and each pixel column 52 extends along the second direction Y.
  • Two gate lines 13 are provided between two adjacent pixel rows 51 in the second direction Y, and a data line 14 is provided for every two pixel columns 52 in the first direction X.
  • the liquid crystal panel 30 also includes a counter substrate 20 , which is spaced apart from the array substrate 10 .
  • the counter substrate 20 includes a base substrate 22 and a black matrix on the base substrate 22 . twenty one.
  • the common electrode 16 covers the data lines 14 between adjacent pixel units 12, thereby shielding the electric field of the data lines 14 and forming a dark area; therefore, the size of the black matrix 21 above the data lines 14 can be greatly reduced, thereby enabling Increase the opening rate.
  • the common electrode 16 covers the data line 14
  • the parasitic capacitance formed between the common electrode 16 and the data line 14 is relatively large, so the impedance on the common electrode 16 or the common electrode line 17 is relatively large, resulting in the common electrode 16 or the common electrode line being
  • the coupling of the common electrode 17 is aggravated, so that the voltage of the common electrode 16 or the common electrode line 17 recovers slowly, thereby causing defects such as afterimages.
  • the common electrode line 17 is designed to include a horizontal common electrode line 17A and a vertical common electrode line 17B.
  • the horizontal common electrode lines 17A and The vertical common electrode lines 17B can be electrically connected in the overlapping area 17C, thereby reducing the resistance of the common electrode lines in the entire display panel.
  • the lateral common electrode line 17A is disposed between the two gate lines 13 , so the black matrix 21 disposed on the gate line 13 needs to additionally cover the lateral common electrode line 17A and between the lateral common electrode line 17A and the two adjacent gate lines 13 spacing, resulting in a reduction in the aperture ratio of the display panel.
  • the display panel 30 also includes a driving transistor T1, a gate insulating layer 18, a passivation layer 19 and a spacer 31;
  • the driving transistor T1 includes a gate G1, an active layer A1, the first source electrode S1, the second source electrode S2 and the drain electrode D1;
  • the gate insulating layer 18 is provided between the gate electrode G1 and the active layer A1, and the passivation layer 19 is provided between the driving transistor T1 and the base substrate 11 side. Due to the presence of the driving transistor T1, the passivation layer 19 will form a protruding structure.
  • the data line 14 and the vertical common electrode line 17B are arranged between adjacent sub-pixel columns 52; since the thickness of the source and drain electrode layers where the data line 14 and the vertical common electrode line 17B are located is thicker, it is different from the thickness of the source and drain electrode layers where the driving transistor T1 is located. The position is similar.
  • the passivation layer 19 at the position where the data line 14 and the vertical common electrode line 17B are located will also form a protruding structure. Therefore, the flatness of the array substrate 10 is low at the positions where the data lines 14 and the vertical common electrode lines 17B are located.
  • the lateral common electrode line 17A includes a spacer bearing portion 17D.
  • the spacer bearing portion 17D is located at a position for placing a spacer 31 .
  • the spacer 31 is used to maintain the array substrate 10 and The cell thickness between the opposing substrates 20. Therefore, the array substrate 10 needs to maintain a certain degree of flatness at the location of the spacer carrying portion 17D to prevent the spacer 31 from being displaced, thereby avoiding defects such as dark state unevenness caused by the displacement of the spacer.
  • the passivation layer 19 will form a protruding structure at the position where the driving transistor T1, the data line 14 and the vertical common electrode line 17B are located, so the spacer carrying portion 17D needs to be away from the vertical common electrode line 17B and the data line 14 Therefore, the space of the effective display area needs to be squeezed out, which reduces the aperture ratio.
  • the passivation layer may also include other film layers, such as alignment layers, etc.; for the sake of simplicity, Figure 3 does not show the film layers on the passivation layer; it can be understood that Yes, when the array substrate includes other film layers mentioned above, since the passivation layer forms a protruding structure, the surface of the finally formed array substrate close to the opposite substrate will correspondingly form a protruding structure.
  • inventions of the present disclosure provide an array substrate, a display panel, and a display device.
  • the array substrate includes a base substrate, a plurality of pixel units and a common electrode line; the plurality of pixel units are located on one side of the base substrate; the common electrode line includes a horizontal common electrode line and a vertical common electrode line, and the horizontal common electrode line and the vertical common electrode line electrically connected to the common electrode line; a plurality of pixel units are arrayed along the first direction and the second direction to form a plurality of pixel rows and a plurality of pixel columns, each pixel row extends along the first direction, and each pixel column extends along the second direction.
  • the horizontal common electrode line extends along the first direction
  • the vertical common electrode line extends along the second direction
  • each pixel unit includes an effective display area
  • the horizontal common electrode line overlaps with multiple effective display areas of the same pixel row.
  • the horizontal common electrode lines overlap with multiple effective display areas of the same pixel row and are not set outside the effective display area in areas that need to be covered by the black matrix; although the horizontal common electrode lines themselves will block the effective display area.
  • the black matrix does not need to cover the lateral common electrode lines and the intervals between the lateral common electrode lines and adjacent gate lines, thereby reducing the width of the black matrix and effectively improving the aperture ratio of the display panel using the array substrate.
  • FIG. 4 is a schematic plan view of an array substrate provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of the connection relationship between components in an array substrate provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic view of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic cross-sectional view of a display panel provided by an embodiment of the present disclosure along the GH direction in FIG. 4.
  • the display panels shown in FIGS. 6 and 7 use the array substrate shown in FIG. 4 .
  • the array substrate 100 includes a base substrate 110, a plurality of pixel units 200 and a common electrode line 120; the plurality of pixel units 200 are located on one side of the base substrate 110; the common electrode line 120 includes a horizontal The common electrode line 122 and the vertical common electrode line 124, and the horizontal common electrode line 122 and the vertical common electrode line 124 are electrically connected, thereby reducing the resistance of the common electrode line 122.
  • the above-mentioned pixel unit may be a sub-pixel that emits monochromatic light.
  • a plurality of pixel units 200 are arranged in an array along the first direction X and the second direction Y to form a plurality of pixel rows 210 and a plurality of pixel columns 220 , and each pixel row 210 extends along the first direction X.
  • each pixel column 220 extends along the second direction Y; the horizontal common electrode line 122 extends along the first direction X, and the vertical common electrode line 124 extends along the second direction Y.
  • Each pixel unit 200 includes an effective display area 205, and the horizontal common electrode Line 122 overlaps multiple active display areas 205 of the same pixel row 210 .
  • the lateral common electrode lines overlap with multiple effective display areas of the same pixel row and are not provided in areas outside the effective display areas that need to be covered by the black matrix; although the lateral common electrode lines themselves will Blocks the light from the effective display area, but the black matrix does not need to cover the lateral common electrode lines and the intervals between the lateral common electrode lines and adjacent gate lines, thus reducing the width of the black matrix and effectively improving the display panel using this array substrate. opening rate.
  • the ratio of the area of the lateral common electrode line to the area of the array substrate is a, and the distance between the lateral common electrode line and the adjacent gate line is equal to the area of the array substrate
  • the ratio is b
  • the black matrix in addition to structures such as gate lines and drive transistors, the black matrix also needs to cover the lateral common electrode lines and the intervals between the lateral common electrode lines and adjacent gate lines. Therefore, the area of the black matrix is the same as that of the array substrate.
  • the ratio of the area is x+a+b or x+a+2b (dual-gate drive structure).
  • the above x is the ratio of the area of other components that the black matrix needs to cover to the area of the array substrate.
  • the lateral common electrode lines overlap with multiple effective display areas of the same pixel row, there is no area outside the effective display area that needs to be covered by the black matrix; although the lateral common electrode lines overlap
  • the ratio of the area of the line to the area of the array substrate is a, but the ratio of the area of the black matrix to the area of the array substrate is reduced by a+b or a+2b (dual-gate drive structure). It can be seen that the aperture ratio of the display panel using the array substrate can be increased by b or 2b, so the array substrate can effectively increase the aperture ratio of the display panel using the array substrate.
  • the array substrate of the display panel 400 adopts the above-mentioned array substrate 100 ; at this time, the display panel 400 also includes a counter substrate 300 , and the counter substrate 300 includes a substrate substrate 310 and a substrate. Black matrix 320 on substrate 310. It can be seen that since the lateral common electrode line 122 overlaps multiple effective display areas 205 of the same pixel row 210 , the black matrix 320 does not need to cover the lateral common electrode line 122 and the interval between the lateral common electrode line 122 and the gate line 130 . Therefore, the array substrate can effectively increase the aperture ratio of the display panel using the array substrate.
  • the array substrate 100 further includes a gate insulating layer 171 , a passivation layer 172 and an insulating layer 173 ; the gate insulating layer 171 is located in a film layer where the vertical conductive portion 1242 is located away from the substrate.
  • the passivation layer 172 is located on the side of the film layer where the data line 140 is located away from the base substrate 110; the insulating layer 173 is located between the pixel electrode 180 and the common electrode 190.
  • the effective display area 205 of the pixel unit 200 includes a first domain 205A and a second domain 205B arranged in the second direction Y; the lateral common electrode line 122 is located in the first domain 205A and the second domain 205B. Between the two domains 205B.
  • the area between the first domain 205A and the second domain 205B is generally a dark area (eg, a transparent area in the area between the first domain and the second domain).
  • the light transmittance is only 20-30%); therefore, although the lateral common electrode line is disposed between the first domain and the second domain, the loss caused by the lateral common electrode line to the light transmittance is low. Therefore, the array substrate can greatly reduce the adverse effects of arranging the lateral common electrode lines in the effective display area.
  • FIG. 8 is a transmittance comparison chart of an array substrate provided by an embodiment of the present disclosure. As shown in Figure 8, there is no lateral common electrode line between the first domain and the second domain of the array substrate on the left, and there is a lateral common electrode line between the first domain and the second domain of the array substrate on the right; It can be seen that although the lateral common electrode line is disposed between the first domain and the second domain, the loss caused by the lateral common electrode line to the light transmittance is low.
  • the pixel unit 200 includes a pixel electrode 180 and a common electrode 190 ; at least one of the pixel electrode 180 and the common electrode 190 is a slit electrode, that is, includes a plurality of slits or Multiple electrode strips arranged at intervals.
  • the above-mentioned slits or electrode strips may have different extending directions in different areas, so that the liquid crystals in different areas have different orientations, thereby increasing the viewing angle. Therefore, the above-mentioned different regions are also the above-mentioned domains.
  • both the pixel electrode 180 and the common electrode 190 may be made of transparent conductive oxide.
  • transparent conductive oxide For example: a combination or at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) and aluminum zinc oxide (AZO) species, the embodiments of the present invention are not limited here.
  • the extension direction of the slits or electrode strips included in the pixel electrode 180 located in the first domain 205A is different from the extending direction of the slits or electrode strips included in the pixel electrode 180 located in the second domain 205B.
  • the extension directions are different.
  • the common electrode 190 covers the data lines 140 between adjacent pixel units 200 , that is, the orthographic projection of the common electrode 190 on the base substrate 110 covers adjacent pixels. Orthographic projection of data lines 140 between cells 200 on base substrate 110 . Therefore, the common electrode 190 can shield the electric field of the data line 140 and form a dark area; therefore, the size of the black matrix 320 above the data line 140 can be greatly reduced, thereby improving the aperture ratio.
  • the array substrate 100 further includes a plurality of gate lines 130 and a plurality of data lines 140 ; the plurality of gate lines 130 are arranged along the second direction Y; and the plurality of data lines 140 are arranged along the second direction Y.
  • each gate line 130 extends along the first direction Line 130 is set on the same layer. Therefore, the lateral common electrode lines extending along the first direction and the data lines extending along the second direction Y are arranged in different layers. Therefore, the lateral common electrode lines can overlap with multiple effective display areas of the same pixel row.
  • the gate lines, data lines and common electrode lines are opaque metal lines.
  • the gate lines, data lines and common electrode lines may be made of any one or an alloy of at least two of copper, aluminum, tungsten, titanium, molybdenum, niobium and cobalt, which is not limited in this embodiment of the present invention.
  • the gate line can be a single-layer or multi-layer structure.
  • the gate line can be a single-layer copper line or a three-layer structure of molybdenum niobium/copper/molybdenum niobium. This is not limited in the embodiment of the present invention.
  • the vertical common electrode line 124 includes a vertical conductive portion 1242 , which is disposed on the same layer as the gate line 130 , and the vertical conductive portion 1242 is located in the first direction. Between two adjacent pixel units 200 on , and the interval is set. The vertical conductive portion 1242 intersects the horizontal common electrode line 122 and forms an integrated cross-shaped conductive structure at the intersection position. Therefore, the array substrate can reduce the resistance of the common electrode line through the above-mentioned cross-shaped conductive structure.
  • the vertical conductive portion 1242 is located between two adjacent data lines 140 in the second direction Y, and the vertical conductive portion 1242 is located on the front side of the base substrate 110 .
  • the projection and data lines 140 are spaced apart from the orthographic projection on the base substrate 110 .
  • the array substrate can avoid the formation of parasitic capacitance between the vertical conductive part and the data line by disposing the vertical conductive part between two adjacent data lines.
  • the vertical common electrode lines 124 include vertical connection portions 1246 , which are arranged in different layers with the gate lines 130 and will be adjacent in the second direction Y.
  • the two vertical conductive parts 1242 are connected. Therefore, on the one hand, the array substrate can reduce the resistance of the common electrode lines through the vertical connection portion; on the other hand, the array substrate can cause the common electrode lines to form a mesh structure through the vertical connection portion, thereby increasing the resistance of the entire array substrate.
  • the voltage uniformity and stability of the common electrode or common electrode line are examples of the common electrode lines 124 .
  • both ends of the vertical connection portion 1246 are respectively connected to two adjacent vertical conductive portions 1242 in the second direction Y through the via connection structures 150; and more
  • Each pixel unit 200 includes a first color pixel unit 200A, a second color pixel unit 200B and a third color pixel unit 200C.
  • the orthographic projection of the via connection structure 150 on the base substrate 110 and the effective display of the third color pixel unit 200C The orthographic projections of the regions on the base substrate 110 at least partially overlap. Since the via-hole connection structure may cause a loss of aperture ratio, by arranging the via-hole connection structure at least partially in a pixel unit with a low light transmittance, the array substrate can reduce the loss of the aperture ratio caused by the via-hole connection structure.
  • the above-mentioned via hole connection structure may include a via hole in the insulating layer between two conductive structures arranged in different layers and a connection structure in the via hole that electrically connects the two conductive structures.
  • the centers of the pixel units located in the same row shown in FIG. 5 are not located on the same straight line, the centers of the pixel units in the same row provided by embodiments of the present disclosure may be located on the same straight line.
  • the light transmittance of the third color pixel unit 200C is less than the light transmittance of the first color pixel unit 200A and the light transmittance of the second color pixel unit 200B.
  • the first color pixel unit 200A is configured to emit light of the first color
  • the second color pixel unit 200B is configured to emit light of the second color
  • the third color pixel unit 200A is configured to emit light of the first color
  • 200C is configured to emit light of a third color, the wavelength of the third color being smaller than the wavelength of the first color and the wavelength of the second color.
  • the first color may be red
  • the second color may be green
  • the third color may be blue.
  • embodiments of the present disclosure include, but are not limited to, this.
  • FIG. 9 is an enlarged schematic diagram of an array substrate in the area indicated by box 701 in FIG. 4 according to an embodiment of the present disclosure.
  • each pixel unit 200 also includes a pixel electrode 180 and a common electrode 190; the pixel electrode 180 is located on the side of the film layer where the data line 140 is located away from the base substrate 110; the common electrode 190 is located on On the side of the pixel electrode 180 away from the base substrate 110 , the vertical connection portion 1246 is arranged on the same layer as the common electrode 190 . That is to say, the vertical connection portion 1246 can be made of the conductive material layer used to make the common electrode 190 .
  • the embodiments of the present disclosure include but are not limited to this, and the vertical connection portion can also be made of other conductive material layers.
  • the vertical connection portion 1246 may be integrally formed with the common electrode 190 . That is to say, the vertical connection portion and the common electrode can be made using the same conductive layer and through the same mask process.
  • At least one pixel unit 200 further includes a driving transistor 160, a pixel electrode 180 and a common electrode 190;
  • the driving transistor 160 includes a gate electrode 161, a source electrode 162 and a drain electrode 163, and the gate electrode 161 and
  • the gate lines 130 are connected to each other, the pixel electrode 180 is connected to the drain electrode 163 , and the common electrode 190 is connected to the common electrode line 120 .
  • the drain 163 includes a drain body portion 1630 and a drain extension portion 1636, which extends from the drain body portion 1630 to the vertical connection portion 1246;
  • the pixel electrode 180 includes a pixel electrode extension portion 186, the pixel electrode extension portion 186 It is connected to the drain extension 1636 by overlapping.
  • the drain extension can reduce the resistance of the pixel electrode extension; on the other hand, the pixel electrode is connected to the drain through the pixel electrode extension in an overlapping manner, which can avoid the need for straight-line via hole connections between the pixel electrode and the drain. structure, thereby further improving the opening ratio.
  • the orthographic projection of drain extension 1636 on base substrate 110 is spaced apart from the orthographic projection of vertical connection 1246 on base substrate 110 , and drain extension 1636 is on
  • the distance d between the orthographic projection on the base substrate 110 and the orthographic projection of the vertical connection portion 1246 on the base substrate 110 ranges from 0-3 microns. Therefore, on the premise of ensuring that the overlapping area of the drain extension part and the pixel electrode extension part is large enough, the drain extension part and the vertical connection part are prevented from overlapping.
  • the distance d between the orthographic projection of the drain extension 1636 on the base substrate 110 and the orthographic projection of the vertical connection 1246 on the base substrate 110 ranges from 1 to 2.5 microns, for example, 2.1 microns.
  • the area where the pixel electrode extension 186 overlaps the drain extension 1636 is greater than 50% of the area of the pixel electrode extension 186 , thereby effectively reducing the resistance of the pixel electrode extension 186 .
  • FIG. 10A is a schematic cross-sectional view of an array substrate along the JK direction in FIG. 9 according to an embodiment of the present disclosure.
  • the array substrate 100 also includes a gate insulating layer 171 and a passivation layer 172; the gate insulating layer 171 is located on the side of the film layer where the vertical conductive portion 1242 is located away from the base substrate 110; the passivation layer 172 is located on the side of the film layer where the data line 140 is located away from the base substrate 110 .
  • the via connection structure 150 may include a via H located in the gate insulation layer 171 and the passivation layer 172 and a conductive structure 1502 located in the via H.
  • the conductive structure 1502 may be a part of the vertical connection portion 1246 .
  • FIG. 10B is a schematic cross-sectional view of an array substrate along the JK direction in FIG. 9 according to an embodiment of the present disclosure.
  • the gate insulating layer 171 and the passivation layer 172 have different etching rates; at this time, the gate insulating layer 171 will form The step portion 1712 facing the via hole H; the conductive structure 1502 is partially located on the step portion 1712.
  • FIG. 11 is an enlarged schematic diagram of an array substrate provided by an embodiment of the present disclosure in the area indicated by box 702 in Figure 4;
  • Figure 12 is a cross-section along the MN direction of Figure 11 of an array substrate provided by an embodiment of the present disclosure.
  • each gate line 130 includes a spacer support part 1305 , and the area where the spacer support part 1305 is located is configured to place the spacer 330 ; the spacer support part 1305 is on the base substrate 110
  • the orthographic projection on the vertical conductive portion 1242 is located between the orthographic projection of the extension line of the vertical conductive portion 1242 on the base substrate 110 and the orthographic projection of the data line 140 closest to the vertical conductive portion 1242 on the base substrate 110 .
  • embodiments of the present disclosure include, but are not limited to, the orthographic projection of the spacer support portion on the base substrate and the orthographic projection of the extension line of the vertical conductive portion on the base substrate at least partially overlap, so that better Utilize the area where the extension line of the vertical conductive part is located.
  • each pixel unit 200 includes a driving transistor 160 , a pixel electrode 180 and a common electrode 190 ;
  • the driving transistor 160 includes a gate electrode 161 , a source electrode 162 and a drain electrode 163 , and the gate electrode 161 It is connected to the gate line 130, the pixel electrode 180 is connected to the drain electrode 163, the common electrode 190 is connected to the common electrode line 120, and the pixel electrode 180 and the drain electrode 163 are connected in an overlapping manner. Therefore, the array substrate does not need to provide a via hole connection structure connecting the pixel electrode and the drain electrode, thereby further improving the aperture ratio.
  • the aperture ratio of the display panel using the array substrate when the array substrate adopts the above-mentioned common electrode line related design, can be increased by about 7%; when the array substrate adopts the above-mentioned spacer support part When related to the design, the aperture ratio of the display panel using the array substrate can be increased by about 3%; when the array substrate adopts the above-mentioned design in which the pixel electrode and the drain electrode are connected by overlapping, the display panel using the array substrate The opening ratio can be increased by about 2%. Therefore, when the array substrate adopts a combination of the various designs mentioned above, the aperture ratio of the display panel using the array substrate can be increased by more than 12%, which has a good effect.
  • the above-mentioned substrate substrate 110 may be a glass substrate, a plastic substrate, or a quartz substrate.
  • the embodiments of the present disclosure include but are not limited to this.
  • the material of the substrate may also be polyimide or the like.
  • the above-mentioned gate insulating layer 171 may be made of inorganic materials or organic materials.
  • the inorganic material may include one or more selected from silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiNxOy).
  • the organic material may include acrylic resin or polyimide resin.
  • the above-mentioned passivation layer 172 may be made of inorganic materials or organic materials.
  • the inorganic material may include one or more selected from silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiNxOy).
  • the organic material may include acrylic resin or polyimide resin.
  • the above-mentioned insulating layer 173 may be made of inorganic materials or organic materials.
  • the inorganic material may include one or more selected from silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiNxOy).
  • the organic material may include acrylic resin or polyimide resin.
  • the array substrate 100 includes a substrate substrate 110 , a plurality of gate lines 130 , a plurality of data lines 140 , a plurality of pixel units 200 and a common electrode line 120 ; a plurality of pixels
  • the unit 200 is located on one side of the base substrate 110; a plurality of pixel units 200 are arranged in an array along the first direction X extends, and each pixel column 220 extends along the second direction Y.
  • the plurality of gate lines 130 are arranged along the second direction Y; the plurality of data lines 140 are arranged along the first direction X; each gate line 130 extends along the first direction X, and each data line 140 extends along the second direction Y; the plurality of gate lines 130 and multiple data lines 140 are arranged in different layers.
  • the common electrode line 120 includes a horizontal common electrode line 122 and a vertical common electrode line 124 .
  • the horizontal common electrode line 122 is electrically connected to the vertical common electrode line 124 , so that the common electrode line 122 can be reduced.
  • the horizontal common electrode lines 122 and the gate lines 130 are arranged in the same layer and extend along the first direction X.
  • the vertical common electrode lines 124 extend along the second direction Y.
  • Each pixel unit 200 includes an effective display area 205.
  • the horizontal common electrode lines 122 and Multiple effective display areas 205 of the same pixel row 210 overlap.
  • the lateral common electrode lines overlap with multiple effective display areas of the same pixel row and are not provided in areas outside the effective display areas that need to be covered by the black matrix; although the lateral common electrode lines themselves will Blocks the light from the effective display area, but the black matrix does not need to cover the lateral common electrode lines and the intervals between the lateral common electrode lines and adjacent gate lines, thus reducing the width of the black matrix and effectively improving the display panel using this array substrate. opening rate.
  • two gate lines 130 are provided between two adjacent pixel columns 220 in the second direction Y.
  • the array substrate adopts a dual-gate driving mode, thereby reducing the number of data lines.
  • each pixel row 210 includes a plurality of pixel groups 215 , and each pixel 215 includes a first color pixel unit 200A, a second color pixel unit 200B, and a third color pixel arranged in sequence.
  • Unit 200C the plurality of pixel groups 215 includes a first pixel group 215A and a second pixel group 215B arranged in sequence along the first direction X, and the plurality of data lines 140 includes a first data line 141, a second data line 142, The third data line 143 and the fourth data line 144.
  • the first data line 141 is located on a side of the first color pixel unit 200A away from the second color pixel unit 200B in the first pixel group 215A
  • the second data line 142 is located on the side of the first color pixel unit 200A in the first pixel group 215A.
  • the third data line 143 is located between the first color pixel unit 200A and the second color pixel unit 200B in the second pixel group 215B.
  • the fourth data The line 144 is located on a side of the third color pixel unit 200C away from the second color pixel unit 200B in the second pixel group 215B.
  • the vertical common electrode line 124 includes a first vertical conductive portion 1242A, a second vertical conductive portion 1242B, and a third vertical conductive portion 1242C.
  • the portion 1242A, the second vertical conductive portion 1242B and the third vertical conductive portion 1242C are all arranged in the same layer as the gate line 130 .
  • the first vertical conductive portion 1242A is located between the first color pixel unit 200A and the second color pixel unit 200B in the first pixel group 215A
  • the second vertical conductive portion 1242B is located between the third color pixel unit 200C in the first pixel group 215A.
  • the third vertical conductive portion 1242C is located between the second color pixel unit 200B and the third color pixel unit 200C in the second pixel group 215B;
  • the conductive portion 1242A, the second vertical conductive portion 1242B and the third vertical conductive portion 1242C are all located between the two gate lines 130 and intersect with the lateral common electrode lines 122 respectively, forming three integrated ten-points at the intersection positions. Glyph conductive structure. Therefore, the array substrate can reduce the resistance of the common electrode line through the above-mentioned cross-shaped conductive structure.
  • the light transmittance of the third color pixel unit 200C is less than the light transmittance of the first color pixel unit 200A and the light transmittance of the second color pixel unit 200B.
  • the first color pixel unit 200A is configured to emit light of the first color
  • the second color pixel unit 200B is configured to emit light of the second color
  • the third color pixel unit 200A is configured to emit light of the first color
  • 200C is configured to emit light of a third color, the wavelength of the third color being smaller than the wavelength of the first color and the wavelength of the second color.
  • the first color may be red
  • the second color may be green
  • the third color may be blue.
  • embodiments of the present disclosure include, but are not limited to, this.
  • the vertical common electrode line 124 further includes a first vertical connection portion 1246A and a second vertical connection portion 1246B; the first vertical connection portion 1246A is different from the gate line 130
  • the second vertical connection portion 1246B and the gate line 130 are arranged in different layers and will be adjacent in the second direction Y.
  • the two third vertical conductive portions 1242C are connected.
  • both ends of the first vertical connection portion 1246A are respectively connected to two second vertical guides adjacent in the second direction Y through the first via connection structure 151 .
  • the electrical parts 1242B are connected; the orthographic projection of the first via hole connection structure 151 on the base substrate 110 at least partially overlaps the orthographic projection of the effective display area of the third color pixel unit 200C on the base substrate 110 . Since the first via hole connection structure may cause a loss of aperture ratio, by arranging the first via hole connection structure at least partially in the pixel unit with low light transmittance, the array substrate can reduce the first via hole connection structure Loss of opening ratio.
  • both ends of the second vertical connection portion 1246B are respectively connected to two third vertical guides adjacent in the second direction Y through the second via connection structure 152 .
  • the electrical parts 1242C are connected; the orthographic projection of the second via hole connection structure 152 on the base substrate 110 at least partially overlaps the orthographic projection of the effective display area of the third color pixel unit 200C on the base substrate 110 .
  • each grid line 130 includes a plurality of spacer support portions 1305 , and the area where each spacer support portion 1305 is located is configured to place spacers.
  • the object support part 1305 includes a main spacer support part 1305A and an auxiliary spacer support part 1305B; the orthographic projection of the main spacer support part 1305A on the substrate substrate 110 is located at the first vertical connection part 1246A on the substrate substrate 110
  • the data line 140 whose orthographic projection is closest to the first vertical connection portion 1246A is between the orthographic projections on the base substrate 110; or the orthographic projection of the main spacer support portion 1305A on the base substrate 110 is located at the second There is between an orthographic projection of the vertical connecting portion 1246B on the base substrate 110 and an orthographic projection of the data line 140 closest to the second vertical connecting portion 1246B on the base substrate 110 .
  • a main spacer support part 1305A and a secondary spacer support part 1305B are respectively provided at the first vertical connection part 1246A or the second vertical connection part 1246B. both sides in the first direction.
  • the orthographic projection of the auxiliary spacer support part on the base substrate can also be provided on The orthographic projection of the first vertical connecting portion on the base substrate is between the orthographic projection of the data line closest to the first vertical connecting portion on the base substrate, or is located between the orthogonal projection of the second vertical connecting portion on the base substrate.
  • the orthographic projection is between the orthographic projection and the data line closest to the second vertical connection portion on the base substrate.
  • embodiments of the present disclosure include, but are not limited to, the orthographic projection of the spacer support portion on the base substrate and the orthographic projection of the extension line of the vertical conductive portion on the base substrate at least partially overlap, or are located above the data line .
  • FIG. 13 is a positional relationship diagram between a spacer support part and a spacer according to an embodiment of the present disclosure.
  • a main spacer 330A may be provided on the main spacer support part 1305A
  • a secondary spacer 330B may be provided on the auxiliary spacer support part 1305B.
  • the shortest distance between the edge of the orthographic projection of the main spacer 330A on the base substrate 110 and the edge of the orthographic projection of the main spacer support 1305A on the base substrate ranges from 5 to 7 microns, such as 6.6 microns.
  • the array substrate can avoid arranging the main spacer at the edge part of the main spacer supporting part, thereby improving the main spacer.
  • the stability of the padding since the flatness of the middle part of the main spacer supporting part is greater than the flatness of the edge part, the array substrate can avoid arranging the main spacer at the edge part of the main spacer supporting part, thereby improving the main spacer. The stability of the padding.
  • the range of the shortest distance between the edge of the orthographic projection of the main spacer 330A on the base substrate 110 and the edge of the orthographic projection of the adjacent drain electrode 163 on the base substrate is: 10-12 microns, such as 11.1 microns. Since the drain electrode has a great influence on the flatness, the array substrate can avoid locating the main spacer far away from the drain electrode, thereby improving the stability of the main spacer.
  • the orthographic projection of the spacer support portion 1305 on the substrate 110 is located between the orthographic projection of the extension line of the first vertical conductive portion 1242A on the substrate 110 and The data line 140 closest to the first vertical conductive portion 1242A is between the orthographic projections on the base substrate 110 . Since the second via hole connection structure may cause a loss of aperture ratio, by arranging the second via hole connection structure at least partially in the pixel unit with low light transmittance, the array substrate can reduce the second via hole connection structure Loss of opening ratio.
  • embodiments of the present disclosure include, but are not limited to, the orthographic projection of the spacer support portion on the substrate and the orthographic projection of the extension line of the vertical conductive portion on the substrate at least partially overlap, so that better Utilize the area where the extension line of the vertical conductive part is located.
  • the two adjacent first vertical conductive parts in the second direction are not provided with vertical connecting parts, so the area where the extension line of the first vertical conductive part is located is flatter, thereby making the spacer more compact. Not prone to displacement.
  • each grid line 130 includes a spacer support 1305 , the area where the spacer support 1305 is located is configured to place the spacer 330 , the spacer support 1305
  • the orthographic projection on the base substrate 110 at least partially overlaps with the orthographic projection of the extension line of the first vertical conductive portion 1242A on the base substrate 110 .
  • the plurality of pixel rows 210 includes a first pixel row 210A and a second pixel row 210B arranged sequentially along the second direction Y
  • the plurality of gate lines 130 includes a sequentially arranged first pixel row 210A and a second pixel row 210B.
  • the third gate line 133 is located between the first pixel row 210A and the second pixel row 210B.
  • the third gate line 133 is located on a side of the second gate line 132 away from the first gate line 131 .
  • the fourth gate line 134 is located on the first pixel row.
  • Row 210A is on the side away from the second row of pixels 210B.
  • the first gate line 131 is connected to the first color pixel unit 200A in the first pixel group 215A in the first pixel row 210A and the first color pixel unit 200A in the second pixel group 215B.
  • the color pixel units 200A are connected; the second gate line 132 is connected to the second color pixel unit 200B in the first pixel group 215A of the first pixel row 210A and the second color pixel unit 200C in the second pixel group 215B; the third gate The line 133 is connected to the first color pixel unit 200A in the first pixel group 215A in the second pixel row 210B and the first color pixel unit 200A in the second pixel group 210B; the fourth gate line 134 is connected to the second pixel row 210B.
  • the second color pixel unit 200B in the first pixel group 215A is connected to the second color pixel unit 200B in the second pixel group 215B.
  • the brightness of the first color pixel unit and the second color pixel unit is higher than that of the third color pixel unit.
  • the array substrate can realize that multiple first color pixel units in the same pixel row are all driven by the same gate line, thereby ensuring consistent charging rates of multiple first color pixel units and preventing occurrence of undesirable phenomena such as fine lines.
  • the array substrate can realize that multiple second-color pixel units in the same pixel row are driven by the same gate line, thereby ensuring consistent charging rates of multiple second-color pixel units and preventing the occurrence of undesirable phenomena such as fine lines.
  • the first gate line 131 is also connected to the third color pixel unit 200C in the second pixel group 215B in the first pixel row 210A
  • the second gate line 132 is also connected to The third color pixel unit 200C in the first pixel group 215A in the first pixel row 210A
  • the third gate line 133 is also connected to the third color pixel unit 200C in the second pixel group 215B in the second pixel row 210B
  • the fourth gate line 134 is also connected to the third color pixel unit 200C in the first pixel group 215A in the second pixel row 210B.
  • the above-mentioned embodiments are explained using ADS and HADS modes as examples, but the embodiments of the disclosure are not limited thereto.
  • the embodiments of the disclosure can also be applied to In-Plane Switching (IPS), etc. model.
  • IPS In-Plane Switching
  • the above-mentioned embodiments take linear horizontal common electrode lines and vertical common electrode lines as examples for description.
  • the embodiments of the present disclosure are not limited thereto.
  • the common electrode lines and the vertical common electrode lines provided by the embodiments of the present disclosure may not be linear, as long as the horizontal common electrode lines generally extend along the first direction, and the vertical common electrode lines generally extend along the first direction. Just extend in the column direction.
  • An embodiment of the present disclosure also provides a method for manufacturing an array substrate.
  • 14A-14D are schematic diagrams of steps of a method for manufacturing an array substrate according to an embodiment of the present disclosure.
  • a gate layer 1300 is formed on the base substrate 110 ; the gate layer 1300 includes the above-mentioned gate lines 130 , gate electrodes 161 , horizontal common electrode lines 122 , and vertical conductive conductive lines of the vertical common electrode lines. Department 1242.
  • the vertical conductive portion 1242 is located between the two gate lines 130 . That is to say, the vertical conductive portion 1242 provided in the same layer as the gate line 130 is not connected to the gate line 130 and is arranged at intervals.
  • the vertical conductive portion 1242 intersects the horizontal common electrode line 122 and forms an integrated cross-shaped conductive structure at the intersection position. Therefore, the array substrate can reduce the resistance of the common electrode line through the above-mentioned cross-shaped conductive structure.
  • a source-drain electrode layer 1400 is formed on the side of the gate layer 1300 away from the base substrate 110; the source-drain electrode layer 1400 includes the above-mentioned data line 140, the source electrode 162 and the drain electrode 163 of the driving transistor 160. .
  • the vertical conductive portion 1242 is located between two adjacent data lines 140 , and the orthographic projection of the vertical conductive portion 1242 on the base substrate 110 is spaced apart from the orthographic projection of the data line 140 on the base substrate 110 .
  • the array substrate can avoid the formation of parasitic capacitance between the vertical conductive part and the data line by disposing the vertical conductive part between two adjacent data lines.
  • the drain electrode 163 further includes a drain body portion 1630 and a drain extension portion 1636 .
  • the drain extension portion 1636 extends from the drain body portion 1630 to the vertical conductive portion 1242 .
  • a first electrode layer 1800 is formed on the side of the source and drain electrode layer 1400 away from the base substrate 110 ; the first electrode layer 1800 includes a pixel electrode 180 ; the pixel electrode 180 includes a pixel electrode extension 186 , and the pixel electrode extends The portion 186 and the drain extension portion 1636 are connected by overlapping.
  • the drain extension can reduce the resistance of the pixel electrode extension; on the other hand, the pixel electrode is connected to the drain through the pixel electrode extension in an overlapping manner, which can avoid the need for straight-line via hole connections between the pixel electrode and the drain. structure, thereby further improving the opening ratio.
  • a second electrode layer 1900 is formed on the side of the first electrode layer 1800 away from the base substrate 110; the second electrode layer 1900 includes a common electrode 190 and a vertical conductive portion 1246; the vertical connection portion 1246 is connected to the gate
  • the lines 130 are arranged in different layers and connect two adjacent vertical conductive portions 1242 . Therefore, on the one hand, the array substrate can reduce the resistance of the common electrode lines through the vertical connection portion; on the other hand, the array substrate can cause the common electrode lines to form a mesh structure through the vertical connection portion, thereby increasing the resistance of the entire array substrate.
  • the voltage uniformity and stability of the common electrode or common electrode line is formed on the side of the first electrode layer 1800 away from the base substrate 110; the second electrode layer 1900 includes a common electrode 190 and a vertical conductive portion 1246; the vertical connection portion 1246 is connected to the gate
  • the lines 130 are arranged in different layers and connect two adjacent vertical conductive portions 1242 . Therefore, on the one hand, the array substrate can reduce the resistance of the common electrode lines through the vertical
  • both ends of the vertical connecting portion 1246 are respectively connected to two adjacent vertical conductive portions 1242 through the via connection structures 150 .
  • the above-mentioned manufacturing method of the array substrate also includes the steps of forming a necessary insulating layer, a passivation layer and a planarization layer.
  • FIG. 15 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • the display panel 400 includes the array substrate 100 described in any one of the above. Therefore, the display panel has beneficial effects corresponding to the beneficial effects of the array substrate. For example, this display panel reduces the width of the black matrix, effectively increasing the aperture ratio.
  • the display panel 400 also includes a counter substrate 300 , a liquid crystal layer 350 and a frame sealant 360 ; the counter substrate 300 is spaced apart from the array substrate 100 , and the liquid crystal layer 350 is disposed on the array substrate. Between the array substrate 100 and the opposite substrate 300 , the sealing glue 360 is used to seal the liquid crystal layer 350 between the array substrate 100 and the opposite substrate 300 .
  • FIG. 16 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
  • the display panel 400 includes a main spacer 330A and a auxiliary spacer 330B; the main spacer 330A is located between the array substrate 100 and the opposite substrate 300 ; the auxiliary spacer 330B is located between the array substrate 100 and the opposite substrate 300 . between the opposing substrates 300 .
  • the main spacer 330A is in contact with both the array substrate 110 and the opposite substrate 300 to play a main supporting role; the auxiliary spacer 330B is in contact with the array substrate 100 and the opposite substrate. At least one of the 300 contacts is set.
  • the auxiliary spacer 330B may be disposed only in contact with the opposite substrate 300 .
  • the main spacer 330A has a first height H1 in a direction perpendicular to the base substrate 110
  • the auxiliary spacer 330B has a second height H1 in a direction perpendicular to the base substrate 110 .
  • Height H2 the first height H1 is greater than the second height H2
  • the difference range between the first height H1 and the second height H2 is 0.2-0.6 microns.
  • FIG. 17 is a schematic diagram of the distribution of main spacers in a display panel according to an embodiment of the present disclosure. As shown in FIG. 17 , one main spacer 330A is provided for every N pixel units 200 , and the value range of N is 30-40.
  • one main spacer 330A is provided for every 36 pixel units 200 .
  • These 36 pixel units 200 can form a 6*6 matrix; at this time, a main spacer 330A is provided in the 6*6 matrix formed by the pixel units 200.
  • embodiments of the present disclosure include but are not limited to this, and the 36 pixel units 200 can also form other matrices.
  • the ratio of the area occupied by the primary spacer to the area of the display panel is 125 ⁇ m 2 /mm 2
  • the ratio of the area occupied by the secondary spacer to the area of the display panel is 6134 ⁇ m 2 /mm 2 .
  • FIG. 18 is a schematic diagram of a display device according to an embodiment of the present disclosure. As shown in FIG. 18 , the display device 500 includes the above-mentioned display panel 400 .
  • the display device can be a display device with a display function such as a television, a computer monitor, a notebook computer, a tablet computer, a smart phone, a navigator, an electronic picture frame, a vehicle-mounted monitor, or the like.
  • a display function such as a television, a computer monitor, a notebook computer, a tablet computer, a smart phone, a navigator, an electronic picture frame, a vehicle-mounted monitor, or the like.

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Abstract

一种阵列基板、显示面板和显示装置。该阵列基板包括衬底基板、多个像素单元和公共电极线；多个像素单元位于衬底基板的一侧；公共电极线包括横向公共电极线和竖向公共电极线，横向公共电极线与竖向公共电极线电性相连；多个像素单元沿第一方向和第二方向阵列设置以形成多个像素行和多个像素列，各像素行沿第一方向延伸，各像素列沿第二方向延伸；横向公共电极线沿第一方向延伸，竖向公共电极线沿第二方向延伸，各像素单元包括有效显示区，横向公共电极线与同一像素行的多个有效显示区重叠。该阵列基板有效地提高了采用该阵列基板的显示面板的开口率。

Description

阵列基板、显示面板及显示装置 技术领域
本发明的实施例涉及一种阵列基板、显示面板及显示装置。
背景技术
随着显示技术的不断发展，薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)逐渐成为市场上的主流显示器。通常，薄膜晶体管液晶显示器包括阵列基板、对置基板和夹设在阵列基板和对置基板之间的液晶层。薄膜晶体管液晶显示器可利用阵列基板和对置基板之间的液晶层上的电场强度的变化来改变液晶层中液晶分子的取向，从而控制透光的强弱来实现显示图像。
阵列基板可包括栅线、数据线、驱动晶体管、像素电极、公共电极等元件；栅线与驱动晶体管的栅极相连，从而可控制驱动晶体管的导通和关闭；数据线与驱动晶体管的源极相连，像素电极与驱动晶体管的漏极相连，当驱动晶体管在栅极的驱动下导通时，数据线可通过驱动晶体管向像素电极施加驱动电压；公共电极线与公共电极相连，并被配置为向公共电极施加公共电压，像素电极和公共电极可形成驱动电场，从而改变液晶层中液晶分子的取向。
发明内容
本公开实施例提供一种阵列基板、显示面板和显示装置。该阵列基板包括衬底基板、多个像素单元和公共电极线；多个像素单元位于衬底基板的一侧；公共电极线包括横向公共电极线和竖向公共电极线，横向公共电极线与竖向公共电极线电性相连；多个像素单元沿第一方向和第二方向阵列设置以形成多个像素行和多个像素列，各像素行沿第一方向延伸，各像素列沿第二方向延伸；横向公共电极线沿第一方向延伸，竖向公共电极线沿第二方向延伸，各像素单元包括有效显示区，横向公共电极线与同一像素行的多个有效显示区重叠。在该阵列基板中，横向公共电极线与同一像素行的多个有效显示区重叠，不设置在有效显示区之外需要被黑矩阵覆盖的区域；虽然横向公共电极线本身会遮挡有效显示区的出光，但是黑矩阵无需覆盖横向公共电极线和横向公共电极线与相邻栅线之间的间隔，从而降低了黑矩阵的宽度，有效地提高了采用该阵列基 板的显示面板的开口率。
本公开至少一个实施例提供一种阵列基板，其包括：衬底基板；多个像素单元，位于所述衬底基板的一侧；以及公共电极线，包括横向公共电极线和竖向公共电极线，所述横向公共电极线与所述竖向公共电极线电性相连，所述多个像素单元沿第一方向和第二方向阵列设置以形成多个像素行和多个像素列，各所述像素行沿所述第一方向延伸，各所述像素列沿所述第二方向延伸，所述横向公共电极线沿所述第一方向延伸，所述竖向公共电极线沿所述第二方向延伸，各所述像素单元包括有效显示区，所述横向公共电极线与同一所述像素行的多个有效显示区重叠。
例如，在本公开一实施例提供的一种阵列基板中，所述有效显示区包括在所述第二方向上排列的第一畴和第二畴，所述横向公共电极线位于所述第一畴和所述第二畴之间。
例如，本公开一实施例提供的一种阵列基板还包括：多条栅线，沿所述第二方向排列；以及多条数据线，沿所述第一方向排列，各所述栅线沿所述第一方向延伸，各所述数据线沿所述第二方向延伸，所述多条栅线与所述多条数据线异层设置，所述横向公共电极线与所述栅线同层设置。
例如，在本公开一实施例提供的一种阵列基板中，所述竖向公共电极线包括竖向导电部，所述竖向导电部与所述栅线同层设置，所述竖向导电部位于在所述第一方向上相邻的两个所述像素单元之间，所述竖向导电部位于两条所述栅线之间，且与所述横向公共电极线交叉，并在交叉位置形成一体的十字形导电结构。
例如，在本公开一实施例提供的一种阵列基板中，所述竖向导电部位于所述第二方向上相邻的两个所述数据线之间，所述竖向导电部在所述衬底基板上的正投影与所述数据线在所述衬底基板上的正投影间隔设置。
例如，在本公开一实施例提供的一种阵列基板中，所述竖向公共电极线包括竖向连接部，所述竖向连接部与所述栅线异层设置，且将在所述第二方向上相邻的两条所述竖向导电部相连。
例如，在本公开一实施例提供的一种阵列基板中，所述竖向连接部的两端部通过过孔连接结构分别与在所述第二方向上相邻的两条所述竖向导电部相连，所述多个像素单元包括第一颜色像素单元、第二颜色像素单元和第三颜色像素单元，所述过孔连接结构在所述衬底基板上的正投影与所述第三颜色像素 单元的有效显示区在所述衬底基板上的正投影至少部分重叠。
例如，在本公开一实施例提供的一种阵列基板中，所述第三颜色像素单元的透光率小于所述第一颜色像素单元的透光率和所述第二颜色像素单元的透光率。
例如，在本公开一实施例提供的一种阵列基板中，所述第一颜色像素单元被配置发第一颜色的光，所述第二颜色像素单元被配置为发第二颜色的光，所述第三颜色像素单元被配置为发第三颜色的光，所述第三颜色的波长小于所述第一颜色的波长和所述第二颜色的波长。
例如，在本公开一实施例提供的一种阵列基板中，各所述像素单元还包括：像素电极，位于所述数据线所在的膜层远离所述衬底基板的一侧；以及公共电极，位于所述像素电极远离所述衬底基板的一侧，所述竖向连接部与所述公共电极同层设置。
例如，在本公开一实施例提供的一种阵列基板中，至少一个所述像素单元还包括：驱动晶体管，包括栅极、源极和漏极，所述栅极与所述栅线相连，所述像素电极与所述漏极相连，所述公共电极与所述公共电极线相连，所述漏极包括漏极主体部和漏极延伸部，所述漏极延伸部从所述漏极主体部向所述竖向连接部延伸，所述像素电极包括像素电极延伸部，所述像素电极延伸部与所述漏极延伸部通过搭接的方式相连。
例如，在本公开一实施例提供的一种阵列基板中，所述漏极延伸部在所述衬底基板上的正投影与所述竖向连接部在所述衬底基板上的正投影间隔设置，且所述漏极延伸部在所述衬底基板上的正投影与所述竖向连接部在所述衬底基板上的正投影之间的距离的范围在0-3微米。
例如，在本公开一实施例提供的一种阵列基板中，所述漏极延伸部在所述衬底基板上的正投影与所述竖向连接部在所述衬底基板上的正投影之间的距离的范围在1-2.5微米。
例如，在本公开一实施例提供的一种阵列基板中，各所述栅线包括隔垫物支撑部，所述隔垫物支撑部所在的区域被配置为放置隔垫物，所述隔垫物支撑部在所述衬底基板上的正投影位于所述第一竖向导电部的延长线在所述衬底基板上的正投影和与所述竖向导电部距离最近的所述数据线在所述衬底基板上的正投影之间。
例如，在本公开一实施例提供的一种阵列基板中，各所述栅线包括隔垫物 支撑部，所述隔垫物支撑部所在的区域被配置为放置隔垫物，所述隔垫物支撑部在所述衬底基板上的正投影与所述竖向导电部的延长线在所述衬底基板上的正投影至少部分重叠。
例如，在本公开一实施例提供的一种阵列基板中，在所述第二方向上相邻的两个所述像素列之间设置有两条所述栅线。
例如，在本公开一实施例提供的一种阵列基板中，各所述像素行包括多个像素组，各所述像素组包括依次设置的第一颜色像素单元、第二颜色像素单元和第三颜色像素单元，所述多个像素组包括沿所述第一方向依次设置的第一像素组和第二像素组，所述多条数据线包括依次设置的第一数据线、第二数据线、第三数据线和第四数据线，所述第一数据线位于所述第一像素组中所述第一颜色像素单元远离所述第二颜色像素单元的一侧，所述第二数据线位于所述第一像素组中所述第二颜色像素单元和所述第三颜色像素单元之间，所述第三数据线位于所述第二像素组中所述第一颜色像素单元和所述第二颜色像素单元，所述第四数据线位于所述第二像素组中所述第三颜色像素单元远离所述第二颜色像素单元的一侧。
例如，在本公开一实施例提供的一种阵列基板中，所述竖向公共电极线包括第一竖向导电部、第二竖向导电部和第三竖向导电部，所述第一竖向导电部、所述第二竖向导电部和所述第三竖向导电部均与所述栅线同层设置，所述第一竖向导电部位于所述第一像素组中所述第一颜色像素单元和所述第二颜色像素单元之间，所述第二竖向导电部位于所述第一像素组中所述第三颜色像素单元和所述第二像素组中的所述第一颜色像素单元之间，所述第三竖向导电部位于所述第二像素组中所述第二颜色像素单元和所述第三颜色像素单元之间，所述第一竖向导电部、所述第二竖向导电部和所述第三竖向导电部均位于两条所述栅线之间，且分别与所述横向公共电极线交叉，并在交叉位置形成三个一体的十字形导电结构。
例如，在本公开一实施例提供的一种阵列基板中，所述竖向公共电极线还包括：第一竖向连接部，与所述栅线异层设置，并将在所述第二方向上相邻的两条所述第二竖向导电部相连；以及第二竖向连接部，与所述栅线异层设置，并将在所述第二方向上相邻的两条所述第三竖向导电部相连。
例如，在本公开一实施例提供的一种阵列基板中，所述第一竖向连接部的两端部分别通过第一过孔连接结构与在所述第二方向上相邻的两条所述第二 竖向导电部相连，所述第一过孔连接结构在所述衬底基板上的正投影与所述第三颜色像素单元的有效显示区在所述衬底基板上的正投影至少部分重叠，所述第二竖向连接部的两端部分别通过第二过孔连接结构与在所述第二方向上相邻的两条所述第三竖向导电部相连，所述第二过孔连接结构在所述衬底基板上的正投影与所述第三颜色像素单元的有效显示区在所述衬底基板上的正投影至少部分重叠。
例如，在本公开一实施例提供的一种阵列基板中，各所述栅线包括多个隔垫物支撑部，各所述隔垫物支撑部所在的区域被配置为放置隔垫物，所述多个隔垫物支撑部包括主隔垫物支撑部和副隔垫物支撑部，所述主隔垫物支撑部在所述衬底基板上的正投影位于所述第二竖向连接部在所述衬底基板上的正投影与所述第二竖向连接部距离最近的所述数据线在所述衬底基板上的正投影之间，或者所述主隔垫物支撑部在所述衬底基板上的正投影位于所述第三竖向连接部在所述衬底基板上的正投影与所述第三竖向连接部距离最近的所述数据线在所述衬底基板上的正投影之间。
例如，在本公开一实施例提供的一种阵列基板中，一个所述主隔垫物支撑部和一个所述副隔垫物支撑部分别设置在所述第二竖向连接部或所述第三竖向连接部在所述第一方向上的两侧。
例如，在本公开一实施例提供的一种阵列基板中，所述多个像素行包括沿第二方向依次设置的第一像素行和第二像素行，所述多条栅线包括依次设置的第一栅线、第二栅线、第三栅线和第四栅线，所述第一栅线位于所述第二像素行远离所述第一像素行的一侧，所述第二栅线和所述第三栅线位于所述第一像素行和所述第二像素行之间，所述第三栅线位于所述第二栅线远离所述第一栅线的一侧，所述第四栅线位于所述第一像素行远离所述第二像素行的一侧。
例如，在本公开一实施例提供的一种阵列基板中，所述第一栅线与所述第一像素行中的所述第一像素组中的所述第一颜色像素单元和所述第二像素组中的所述第一颜色像素单元相连，所述第二栅线与所述第一像素行的所述第一像素组中的所述第二颜色像素单元和所述第二像素组中的所述第二颜色像素单元相连，所述第三栅线与所述第二像素行中的所述第一像素组中的所述第一颜色像素单元和所述第二像素组中的所述第一颜色像素单元相连，所述第四栅线与所述第二像素行的所述第一像素组中的所述第二颜色像素单元和所述第二像素组中的所述第二颜色像素单元相连。
例如，在本公开一实施例提供的一种阵列基板中，所述第一栅线还与所述第一像素行中的所述第二像素组中的所述第三颜色像素单元相连，所述第二栅线还与所述第一像素行中的所述第一像素组中的所述第三颜色像素单元相连，所述第三栅线还与所述第二像素行中的所述第二像素组中的所述第三颜色像素单元相连，所述第四栅线还与所述第二像素行中的所述第一像素组中的所述第三颜色像素单元。
本公开至少一个实施例还提供一种显示面板，包括上述任一项所述的阵列基板。
例如，本公开一实施例提供的一种显示面板还包括：对置基板，与所述阵列基板相对设置；主隔垫物，位于所述阵列基板和所述对置基板之间；以及副隔垫物，位于所述阵列基板和所述对置基板之间。
例如，在本公开一实施例提供的显示面板中，每N个所述像素单元设置一个所述主隔垫物，N的取值范围为30-40。
例如，在本公开一实施例提供的显示面板中，N的取值为36。
例如，在本公开一实施例提供的显示面板中，所述主隔垫物与所述阵列基板和所述对置基板均接触设置，所述副隔垫物与所述阵列基板和所述对置基板中的至少之一接触设置。
例如，在本公开一实施例提供的显示面板中，所述主隔垫物在垂直于所述衬底基板的方向上具有第一高度，所述副隔垫物在垂直于所述衬底基板的方向上具有第二高度，所述第一高度大于所述第二高度，所述第一高度和所述第二高度的差值范围为0.2-0.6微米。
本公开至少一个实施例还提供一种显示装置，其包括上述的显示面板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种液晶面板中的阵列基板的平面示意图；
图2为一种液晶面板沿图1中AB方向的剖面示意图；
图3为一种液晶面板沿图1中CD方向的剖面示意图；
图4为本公开一实施例提供的一种阵列基板的平面示意图；
图5为本公开一实施例提供的一种阵列基板中各部件的连接关系的示意图；
图6为本公开一实施例提供的一种显示面板沿图4中EF方向的剖面示意图；
图7为本公开一实施例提供的一种显示面板沿图4中GH方向的剖面示意图；
图8为本公开一实施例提供的一种阵列基板的透过率对比图；
图9为本公开一实施例提供的一种阵列基板在图4中方框701所示的区域的放大示意图；
图10A为本公开一实施例提供的一种阵列基板沿图9中JK方向的剖面示意图；
图10B为本公开一实施例提供的另一种阵列基板沿图9中JK方向的剖面示意图；
图11为本公开一实施例提供的一种阵列基板在图4中方框702所示的区域的放大示意图；
图12为本公开一实施例提供的一种阵列基板沿图11中MN方向的剖面示意图；
图13为本公开一实施例提供的一种隔垫物支撑部与隔垫物的位置关系图；
图14A-14D为本公开一实施例提供的一种阵列基板的制作方法的步骤示意图
图15为本公开一实施例提供的一种显示面板的结构示意图；
图16为本公开一实施例提供的另一种显示面板的结构示意图；
图17为本公开一实施例提供的一种显示面板中主隔垫物的分布示意图；以及
图18为本公开一实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所 有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
除非另外定义，本公开实施例中使用的“平行”、“垂直”和“相同”等特征均包括严格意义上的“平行”、“垂直”、“相同”等情况，以及“大致平行”、“大致垂直”、“大致相同”等包含一定误差的情况。例如，上述的“大致”可表示所比较的对象的差值为所比较的对象的平均值的10％，或者5％之内。在本公开实施例的下文中没有特别指出一个部件或元件的数量时，意味着该部件或元件可以是一个也可以是多个，或可理解为至少一个。“至少一个”指一个或多个，“多个”指至少两个。本公开实施例中的“同层设置”指同一材料在经过同一步骤(例如，一步图案化工艺)后形成的多个膜层之间的关系。这里的“同层”并不总是指多个膜层的厚度相同或者多个膜层在截面图中的高度相同。
通常，薄膜晶体管液晶显示器可利用在对置基板上形成的黑矩阵遮挡非显示区，从而避免漏光的发生。在一种液晶显示器中，公共电极覆盖相邻像素单元之间的数据线，从而可屏蔽数据线的电场，并形成暗区；因此，在该数据线上方的黑矩阵的尺寸可大大减少，从而可提高开口率。然而，由于公共电极覆盖数据线，公共电极和数据线之间形成的寄生电容较大，因此公共电极或公共电极线上的阻抗较大，导致公共电极或公共电极线的耦合加重，从而使得公共电极或公共电极线的电压恢复缓慢，进而导致残像等不良。
图1为一种液晶面板中的阵列基板的平面示意图；图2为一种液晶面板沿图1中AB方向的剖面示意图；图3为一种液晶面板沿图1中CD方向的剖面示意图。
如图1和图2所示，该液晶面板40包括阵列基板10，阵列基板10包括衬底基板11、多个像素单元12、栅线13、数据线14、像素电极15、公共电极16和公共电极线17。多个像素单元12沿第一方向X和第二方向Y阵列设置，并形成多个像素行51和多个像素列52；多个像素行51沿第二方向Y排列， 各像素行51沿第一方向X延伸；多个像素列52沿第一方向X排列，各像素列52沿第二方向Y延伸。在第二方向Y上相邻的两个像素行51之间设置有两个栅线13，在第一方向X上每隔两个像素列52设置一条数据线14。
如图1和图2所示，该液晶面板30还包括对置基板20，对置基板20与阵列基板10相对间隔设置；对置基板20包括衬底基板22和衬底基板22上的黑矩阵21。公共电极16覆盖相邻像素单元12之间的数据线14，从而可屏蔽数据线14的电场，并形成暗区；因此，在该数据线14上方的黑矩阵21的尺寸可大大减少，从而可提高开口率。然而，由于公共电极16覆盖数据线14，公共电极16和数据线14之间形成的寄生电容较大，因此公共电极16或公共电极线17上的阻抗较大，导致公共电极16或公共电极线17的耦合加重，从而使得公共电极16或公共电极线17的电压恢复缓慢，进而导致残像等不良。
如图1和图3所示，为了减小公共电极16或公共电极线17的耦合，公共电极线17被设计为包括横向公共电极线17A和竖向公共电极线17B，横向公共电极线17A和竖向公共电极线17B可在交叠区域17C电性相连，从而可减小整个显示面板中的公共电极线的电阻。横向公共电极线17A设置在两条栅线13之间，因此设置在栅线13上的黑矩阵21需要额外覆盖横向公共电极线17A和横向公共电极线17A与相邻两条栅线13之间的间隔，从而导致该显示面板的开口率降低。
另一方面，如图1和图3所示，该显示面板30还包括驱动晶体管T1、栅极绝缘层18、钝化层19和隔垫物31；驱动晶体管T1包括栅极G1、有源层A1、第一源极S1、第二源极S2和漏极D1；栅极绝缘层18设置在栅极G1和有源层A1之间，钝化层19设置在驱动晶体管T1远离衬底基板11的一侧。由于驱动晶体管T1的存在，钝化层19会因此形成突起结构。数据线14和竖向公共电极线17B设置在相邻的子像素列52之间；由于数据线14和竖向公共电极线17B所在的源漏电极层的厚度较厚，与驱动晶体管T1所在的位置类似，数据线14和竖向公共电极线17B所在的位置的钝化层19也会形成突起结构。因此，阵列基板10在数据线14和竖向公共电极线17B所在的位置的平坦度较低。
如图1和图3所示，横向公共电极线17A包括隔垫物承载部17D，隔垫物承载部17D所在的位置用于放置隔垫物31，隔垫物31用于维持阵列基板10和对置基板20之间的盒厚。因此，阵列基板10在隔垫物承载部17D所在的位 置需要保持一定的平坦度，以防止隔垫物31发生位移，从而避免产生因隔垫物发生位移而导致暗态不均等不良。如上所述，钝化层19在驱动晶体管T1、数据线14和竖向公共电极线17B所在的位置会形成突起结构，因此隔垫物承载部17D需要远离竖向公共电极线17B和数据线14制作，从而需要挤占有效显示区的空间，使得开口率降低。需要说明的是，在通常的阵列基板中，钝化层之上还可包括其他膜层，例如配向层等；为了简洁起见，图3没有示出钝化层之上的膜层；可以理解的是，当阵列基板包括上述的其他膜层时，由于钝化层形成突起结构，最终形成的阵列基板靠近对置基板的表面会对应形成突起结构。
对此，本公开实施例提供一种阵列基板、显示面板和显示装置。该阵列基板包括衬底基板、多个像素单元和公共电极线；多个像素单元位于衬底基板的一侧；公共电极线包括横向公共电极线和竖向公共电极线，横向公共电极线与竖向公共电极线电性相连；多个像素单元沿第一方向和第二方向阵列设置以形成多个像素行和多个像素列，各像素行沿第一方向延伸，各像素列沿第二方向延伸；横向公共电极线沿第一方向延伸，竖向公共电极线沿第二方向延伸，各像素单元包括有效显示区，横向公共电极线与同一像素行的多个有效显示区重叠。在该阵列基板中，横向公共电极线与同一像素行的多个有效显示区重叠，不设置在有效显示区之外需要被黑矩阵覆盖的区域；虽然横向公共电极线本身会遮挡有效显示区的出光，但是黑矩阵无需覆盖横向公共电极线和横向公共电极线与相邻栅线之间的间隔，从而降低了黑矩阵的宽度，有效地提高了采用该阵列基板的显示面板的开口率。
下面，结合附图对本发明实施例提供的阵列基板、显示面板以及显示装置进行详细的说明。
本公开一实施例提供一种阵列基板。图4为本公开一实施例提供的一种阵列基板的平面示意图；图5为本公开一实施例提供的一种阵列基板中各部件的连接关系的示意图；图6为本公开一实施例提供的一种显示面板沿图4中EF方向的剖面示意图；图7为本公开一实施例提供的一种显示面板沿图4中GH方向的剖面示意图。图6和图7所示的显示面板采用图4所示的阵列基板。
如图4和图5所示，该阵列基板100包括衬底基板110、多个像素单元200和公共电极线120；多个像素单元200位于衬底基板110的一侧；公共电极线120包括横向公共电极线122和竖向公共电极线124，横向公共电极线122与 竖向公共电极线124电性相连，从而可降低公共电极线122的电阻。需要说明的是，上述的像素单元可为发单色光的子像素。
如图4和图5所示，多个像素单元200沿第一方向X和第二方向Y阵列设置以形成多个像素行210和多个像素列220，各像素行210沿第一方向X延伸，各像素列220沿第二方向Y延伸；横向公共电极线122沿第一方向X延伸，竖向公共电极线124沿第二方向Y延伸，各像素单元200包括有效显示区205，横向公共电极线122与同一像素行210的多个有效显示区205重叠。
在本公开实施例提供的阵列基板中，横向公共电极线与同一像素行的多个有效显示区重叠，不设置在有效显示区之外需要被黑矩阵覆盖的区域；虽然横向公共电极线本身会遮挡有效显示区的出光，但是黑矩阵无需覆盖横向公共电极线和横向公共电极线与相邻栅线之间的间隔，从而降低了黑矩阵的宽度，有效地提高了采用该阵列基板的显示面板的开口率。
需要说明的是，在通常的阵列基板中，当横向公共电极线的面积与阵列基板的面积的比例为a，而横向公共电极线与相邻的栅线之间的间隔与阵列基板的面积的比例为b时，除了栅线、驱动晶体管等结构之外，黑矩阵还需要覆盖横向公共电极线和横向公共电极线与相邻的栅线之间的间隔，因此黑矩阵的面积与阵列基板的面积的比例为x+a+b或者x+a+2b(双栅驱动结构)，上述的x为黑矩阵需要覆盖的其他部件的面积与阵列基板的面积的比例。然而，在本公开实施例提供的阵列基板中，由于横向公共电极线与同一像素行的多个有效显示区重叠，不设置在有效显示区之外需要被黑矩阵覆盖的区域；虽然横向公共电极线的面积与阵列基板的面积的比例为a，但是黑矩阵面积与阵列基板的面积的比例减少了a+b或者a+2b(双栅驱动结构)。可见，采用该阵列基板的显示面板的开口率可提高b或者2b，因此该阵列基板可有效地提高采用该阵列基板的显示面板的开口率。
例如，如图4和图6所示，显示面板400的阵列基板采用上述的阵列基板100；此时，该显示面板400还包括对置基板300，对置基板300包括衬底基板310和衬底基板310上的黑矩阵320。可见，由于横向公共电极线122与同一像素行210的多个有效显示区205重叠，黑矩阵320无需覆盖横向公共电极线122和横向公共电极线122与栅线130之间的间隔。因此，该阵列基板可有效地提高采用该阵列基板的显示面板的开口率。
在一些示例中，如图6所示，该阵列基板100还包括栅极绝缘层171、钝 化层172和绝缘层173；栅极绝缘层171位于竖向导电部1242所在的膜层远离衬底基板110的一侧；钝化层172位于数据线140所在膜层远离衬底基板110的一侧；绝缘层173位于像素电极180和公共电极190之间。
在一些示例中，如图4所示，像素单元200的有效显示区205包括在第二方向Y上排列的第一畴205A和第二畴205B；横向公共电极线122位于第一畴205A和第二畴205B之间。当像素单元200包括第一畴205A和第二畴205B时，第一畴205A和第二畴205B之间的区域通常为暗区(例如，在第一畴和第二畴之间的区域的透光率仅为20-30％)；因此，虽然横向公共电极线设置在第一畴和第二畴之间，但是该横向公共电极线对透光率造成的损失较低。由此，该阵列基板可大大降低将横向公共电极线设置在有效显示区的不良影响。
图8为本公开一实施例提供的一种阵列基板的透过率对比图。如图8所示，左侧的阵列基板的第一畴和第二畴之间没有设置横向公共电极线，右侧的阵列基板的第一畴和第二畴之间设置有横向公共电极线；可见，虽然横向公共电极线设置在第一畴和第二畴之间，但是该横向公共电极线对透光率造成的损失较低。
在一些示例中，如图4和图7所示，像素单元200包括像素电极180和公共电极190；像素电极180和公共电极190中的至少之一为狭缝电极，即包括多个狭缝或者间隔设置的多个电极条。在显示单元200的有效显示区205中，上述的狭缝或者电极条可在不同区域具有不同的延伸方向，从而使得不同区域的液晶具有不同的取向，从而增加可视角度。因此，上述的不同区域也即上述的畴。
例如，像素电极180和公共电极190的材料均可为透明导电氧化物。例如：氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化铟(In 2O 3)、氧化铟镓(IGO)和氧化铝锌(AZO)中的组合或至少一种，本发明实施例在此不作限制。
例如，如图4和图7所示，位于第一畴205A的像素电极180所包括的狭缝或者电极条的延伸方向与位于第二畴205B的像素电极180所包括的狭缝或者电极条的延伸方向不同。
在一些示例中，如图4和图7所示，公共电极190覆盖相邻像素单元200之间的数据线140，也就是说，公共电极190在衬底基板110上的正投影覆盖相邻像素单元200之间的数据线140在衬底基板110上的正投影。由此，公共 电极190可屏蔽数据线140的电场，并形成暗区；因此，在该数据线140上方的黑矩阵320的尺寸可大大减少，从而可提高开口率。
在一些示例中，如图4和图5所示，该阵列基板100还包括多条栅线130和多条数据线140；多条栅线130沿第二方向Y排列；多条数据线140沿第一方向X排列；各栅线130沿第一方向X延伸，各数据线140沿第二方向Y延伸；多条栅线130与多条数据线140异层设置，横向公共电极线122与栅线130同层设置。由此，沿第一方向延伸的横向公共电极线与沿第二方向Y延伸的数据线异层设置，由此，横向公共电极线可与同一像素行的多个有效显示区重叠。
例如，栅线、数据线以及公共电极线为不透明的金属线。例如，栅线、数据线以及公共电极线的材料可采用铜、铝、钨、钛、钼、铌和钴中的任一种或至少两种的合金，本发明实施例在此不作限制。
例如，栅线可为单层或多层结构，例如，栅线可为单层铜线，也可为钼铌/铜/钼铌的三层结构，本发明实施例在此不作限制。
在一些示例中，如图4和图5所示，竖向公共电极线124包括竖向导电部1242，竖向导电部1242与栅线130同层设置，竖向导电部1242位于在第一方向X上相邻的两个像素单元200之间；竖向导电部1242位于两条栅线130之间，也就是说，与栅线130同层设置的竖向导电部1242与栅线130不相连，且间隔设置。竖向导电部1242与横向公共电极线122交叉，并在交叉位置形成一体的十字形导电结构。由此，该阵列基板可通过上述的十字形导电结构降低公共电极线的电阻。
在一些示例中，如图4和图5所示，竖向导电部1242位于在第二方向Y上相邻的两个数据线140之间，竖向导电部1242在衬底基板110上的正投影与数据线140在衬底基板110上的正投影间隔设置。虽然，竖向导电部与数据线异层设置，但是该阵列基板通过将竖向导电部设置在相邻的两个数据线之间，可避免竖向导电部与数据线之间形成寄生电容。
在一些示例中，如图4和图5所示，竖向公共电极线124包括竖向连接部1246，竖向连接部1246与栅线130异层设置，且将在第二方向Y上相邻的两条竖向导电部1242相连。由此，一方面，该阵列基板可通过上述竖向连接部降低公共电极线的电阻；另一方面，该阵列基板可通过竖向连接部使得公共电极线形成网状结构，从而增加整个阵列基板的公共电极或公共电极线上的电压均一性和稳定性。
在一些示例中，如图4和图5所示，竖向连接部1246的两端部通过过孔连接结构150分别与在第二方向Y上相邻的两条竖向导电部1242相连；多个像素单元200包括第一颜色像素单元200A、第二颜色像素单元200B和第三颜色像素单元200C，过孔连接结构150在衬底基板110上的正投影与第三颜色像素单元200C的有效显示区在衬底基板110上的正投影至少部分重叠。由于过孔连接结构可能会造成开口率的损失，因此，通过将过孔连接结构至少部分设置在透光率较低的像素单元中，该阵列基板可降低过孔连接结构对开口率的损失。
需要说明的是，上述的过孔连接结构可包括异层设置的两个导电结构之间的绝缘层中过孔和过孔中将这两个导电结构电性相连的连接结构。另外，虽然图5所示的位于同一行的像素单元的中心不位于同一直线上，但是本公开实施例提供的同一行的像素单元的中心可位于同一直线上。
在一些示例中，如图4和图5所示，第三颜色像素单元200C的透光率小于第一颜色像素单元200A的透光率和第二颜色像素单元200B的透光率。
在一些示例中，如图4和图5所示，第一颜色像素单元200A被配置发第一颜色的光，第二颜色像素单元200B被配置为发第二颜色的光，第三颜色像素单元200C被配置为发第三颜色的光，第三颜色的波长小于第一颜色的波长和第二颜色的波长。
例如，第一颜色可为红色，第二颜色可为绿色，第三颜色可为蓝色。当然，本公开实施例包括但不限与此。
图9为本公开一实施例提供的一种阵列基板在图4中方框701所示的区域的放大示意图。如图4、图5和图9所示，各像素单元200还包括像素电极180和公共电极190；像素电极180位于数据线140所在的膜层远离衬底基板110的一侧；公共电极190位于像素电极180远离衬底基板110的一侧，竖向连接部1246与公共电极190同层设置。也就是说，竖向连接部1246可采用制作公共电极190的导电材料层制作。当然，本公开实施例包括但不限于此，竖向连接部也可采用其他导电材料层制作。
在一些示例中，如图9所示，竖向连接部1246可与公共电极190一体成型。也就是说，竖向连接部和公共电极可采用同一导电层通过同一掩膜工艺制作。
在一些示例中，如图9所示，至少一个像素单元200还包括驱动晶体管160、 像素电极180和公共电极190；驱动晶体管160包括栅极161、源极162和漏极163，栅极161与栅线130相连，像素电极180与漏极163相连，公共电极190与公共电极线120相连。漏极163包括漏极主体部1630和漏极延伸部1636，漏极延伸部1636从漏极主体部1630向竖向连接部1246延伸；像素电极180包括像素电极延伸部186，像素电极延伸部186与漏极延伸部1636通过搭接的方式相连。一方面，漏极延伸部可降低像素电极延伸部的电阻；另一方面，像素电极通过像素电极延伸部与漏极通过搭接的方式相连，可避免在像素电极和漏极直线设置过孔连接结构，从而可进一步提高开口率。
在一些示例中，如图9所示，漏极延伸部1636在衬底基板110上的正投影与竖向连接部1246在衬底基板110上的正投影间隔设置，且漏极延伸部1636在衬底基板110上的正投影与竖向连接部1246在衬底基板110上的正投影之间的距离d的范围在0-3微米。由此，在保证漏极延伸部与像素电极延伸部的交叠面积足够大的前提下，避免漏极延伸部与竖向连接部发生交叠。
在一些示例中，如图9所示，漏极延伸部1636在衬底基板110上的正投影与竖向连接部1246在衬底基板110上的正投影之间的距离d的范围在1-2.5微米，例如，2.1微米。
在一些示例中，如图9所示，像素电极延伸部186与漏极延伸部1636交叠的面积大于像素电极延伸部186的面积的50％，从而可有效地降低像素电极延伸部186的电阻。
图10A为本公开一实施例提供的一种阵列基板沿图9中JK方向的剖面示意图。如图10A所示，该阵列基板100还包括栅极绝缘层171和钝化层172；栅极绝缘层171位于竖向导电部1242所在的膜层远离衬底基板110的一侧；钝化层172位于数据线140所在膜层远离衬底基板110的一侧。该过孔连接结构150可包括位于栅极绝缘层171和钝化层172中的过孔H和位于过孔H中的导电结构1502，该导电结构1502可为竖向连接部1246的一部分。
图10B为本公开一实施例提供的一种阵列基板沿图9中JK方向的剖面示意图。如图10B所示，当栅极绝缘层171和钝化层172采用不同材料制作时，栅极绝缘层171和钝化层172具有不同的刻蚀速率；此时，栅极绝缘层171会形成朝向过孔H的台阶部1712；导电结构1502部分位于台阶部1712上。
图11为本公开一实施例提供的一种阵列基板在图4中方框702所示的区域的放大示意图；图12为本公开一实施例提供的一种阵列基板沿图11中MN 方向的剖面示意图。如图4和图11所示，各栅线130包括隔垫物支撑部1305，隔垫物支撑部1305所在的区域被配置为放置隔垫物330；隔垫物支撑部1305在衬底基板110上的正投影位于竖向导电部1242的延长线在衬底基板110上的正投影和与竖向导电部1242距离最近的数据线140在衬底基板110上的正投影之间。由于竖向导电部不会穿过栅线，因此在竖向导电部的延长线的位置没有设置竖向公共电极线或者数据线，较为平坦；隔垫物支撑部不用避开该区域。由此，隔垫物支撑部不用占用像素单元的有效显示区，从而可提高开口率。当然，本公开实施例包括但不限于此，隔垫物支撑部在衬底基板上的正投影与竖向导电部的延长线在衬底基板上的正投影至少部分重叠，从而可更好地利用竖向导电部的延伸线所在的区域。
在一些示例中，如图4和图11所示，各像素单元200包括驱动晶体管160、像素电极180和公共电极190；驱动晶体管160包括栅极161、源极162和漏极163，栅极161与栅线130相连，像素电极180与漏极163相连，公共电极190与公共电极线120相连，像素电极180与漏极163通过搭接的方式相连。由此，该阵列基板不用设置像素电极与漏极相连的过孔连接结构，从而可进一步提高开口率。
在本公开实施例中，当该阵列基板采用上述的公共电极线的相关设计时，采用该阵列基板的显示面板的开口率可提高约7％；当该阵列基板采用上述的隔垫物支撑部的相关设计时，采用该阵列基板的显示面板的开口率可提高约3％；当该阵列基板采用上述的像素电极与漏极通过搭接的方式相连的设计时，采用该阵列基板的显示面板的开口率可提高约2％。因此，当该阵列基板采用上述各种设计的组合时，采用该阵列基板的显示面板的开口率可提高12％以上，具有较好的效果。
在一些示例中，上述的衬底基板110可为玻璃基板、塑料基板或者石英基板。当然，本公开实施例包括但不限于此，该衬底基板的材料也可采用聚酰亚胺等。
在一些示例中，上述的栅极绝缘层171的材料可采用无机材料或有机材料。无机材料可包括选自氮化硅(SiNx)，氧化硅(SiOx)，氮氧化硅(SiNxOy)中的一种或多种。有机材料可包括亚克力树脂或聚酰亚胺树脂。
在一些示例中，上述的钝化层172的材料可采用无机材料或有机材料。无机材料可包括选自氮化硅(SiNx)，氧化硅(SiOx)，氮氧化硅(SiNxOy)中 的一种或多种。有机材料可包括亚克力树脂或聚酰亚胺树脂。
在一些示例中，上述的绝缘层173的材料可采用无机材料或有机材料。无机材料可包括选自氮化硅(SiNx)，氧化硅(SiOx)，氮氧化硅(SiNxOy)中的一种或多种。有机材料可包括亚克力树脂或聚酰亚胺树脂。
在一些示例中，如图4和图5所示，该阵列基板100包括衬底基板110、多条栅线130、多条数据线140、多个像素单元200和公共电极线120；多个像素单元200位于衬底基板110的一侧；多个像素单元200沿第一方向X和第二方向Y阵列设置以形成多个像素行210和多个像素列220，各像素行210沿第一方向X延伸，各像素列220沿第二方向Y延伸。多条栅线130沿第二方向Y排列；多条数据线140沿第一方向X排列；各栅线130沿第一方向X延伸，各数据线140沿第二方向Y延伸；多条栅线130与多条数据线140异层设置。
如图4和图5所示，公共电极线120包括横向公共电极线122和竖向公共电极线124，横向公共电极线122与竖向公共电极线124电性相连，从而可降低公共电极线122的电阻。横向公共电极线122与栅线130同层设置，且沿第一方向X延伸，竖向公共电极线124沿第二方向Y延伸，各像素单元200包括有效显示区205，横向公共电极线122与同一像素行210的多个有效显示区205重叠。
在本公开实施例提供的阵列基板中，横向公共电极线与同一像素行的多个有效显示区重叠，不设置在有效显示区之外需要被黑矩阵覆盖的区域；虽然横向公共电极线本身会遮挡有效显示区的出光，但是黑矩阵无需覆盖横向公共电极线和横向公共电极线与相邻栅线之间的间隔，从而降低了黑矩阵的宽度，有效地提高了采用该阵列基板的显示面板的开口率。
在一些示例中，如图4和图5所示，在第二方向Y上相邻的两个像素列220之间设置有两条栅线130。由此，该阵列基板采用双栅驱动模式，从而可降低数据线的数量。
在一些示例中，如图4和图5所示，各像素行210包括多个像素组215，各像素215包括依次设置的第一颜色像素单元200A、第二颜色像素单元200B和第三颜色像素单元200C；多个像素组215包括沿第一方向X依次设置的第一像素组215A和第二像素组215B，多条数据线140包括依次设置的第一数据线141、第二数据线142、第三数据线143和第四数据线144。
在一些示例中，如图4和图5所示，第一数据线141位于第一像素组215A 中第一颜色像素单元200A远离第二颜色像素单元200B的一侧，第二数据线142位于第一像素组215A中第二颜色像素单元200B和第三颜色像素单元200C之间，第三数据线143位于第二像素组215B中第一颜色像素单元200A和第二颜色像素单元200B，第四数据线144位于第二像素组215B中第三颜色像素单元200C远离第二颜色像素单元200B的一侧。
在一些示例中，如图4和图5所示，竖向公共电极线124包括第一竖向导电部1242A、第二竖向导电部1242B和第三竖向导电部1242C，第一竖向导电部1242A、第二竖向导电部1242B和第三竖向导电部1242C均与栅线130同层设置。第一竖向导电部1242A位于第一像素组215A中第一颜色像素单元200A和第二颜色像素单元200B之间，第二竖向导电部1242B位于第一像素组215A中第三颜色像素单元200C和第二像素组215B中的第一颜色像素单元200A之间，第三竖向导电部1242C位于第二像素组215B中第二颜色像素单元200B和第三颜色像素单元200C之间；第一竖向导电部1242A、第二竖向导电部1242B和第三竖向导电部1242C均位于两条栅线130之间，且分别与横向公共电极线122交叉，并在交叉位置形成三个一体的十字形导电结构。由此，该阵列基板可通过上述的十字形导电结构降低公共电极线的电阻。
在一些示例中，如图4和图5所示，第三颜色像素单元200C的透光率小于第一颜色像素单元200A的透光率和第二颜色像素单元200B的透光率。
在一些示例中，如图4和图5所示，第一颜色像素单元200A被配置发第一颜色的光，第二颜色像素单元200B被配置为发第二颜色的光，第三颜色像素单元200C被配置为发第三颜色的光，第三颜色的波长小于第一颜色的波长和第二颜色的波长。
例如，第一颜色可为红色，第二颜色可为绿色，第三颜色可为蓝色。当然，本公开实施例包括但不限与此。
在一些示例中，如图4和图5所示，竖向公共电极线124还包括第一竖向连接部1246A和第二竖向连接部1246B；第一竖向连接部1246A与栅线130异层设置，并将在第二方向Y上相邻的两条第二竖向导电部1242B相连；第二竖向连接部1246B与栅线130异层设置，并将在第二方向Y上相邻的两条第三竖向导电部1242C相连。
在一些示例中，如图4和图5所示，第一竖向连接部1246A的两端部分别通过第一过孔连接结构151与在第二方向Y上相邻的两条第二竖向导电部 1242B相连；第一过孔连接结构151在衬底基板110上的正投影与第三颜色像素单元200C的有效显示区在衬底基板110上的正投影至少部分重叠。由于第一过孔连接结构可能会造成开口率的损失，因此，通过将第一过孔连接结构至少部分设置在透光率较低的像素单元中，该阵列基板可降低第一过孔连接结构对开口率的损失。
在一些示例中，如图4和图5所示，第二竖向连接部1246B的两端部分别通过第二过孔连接结构152与在第二方向Y上相邻的两条第三竖向导电部1242C相连；第二过孔连接结构152在衬底基板110上的正投影与第三颜色像素单元200C的有效显示区在衬底基板110上的正投影至少部分重叠。
在一些示例中，如图4和图5所示，各栅线130包括多个隔垫物支撑部1305，各隔垫物支撑部1305所在的区域被配置为放置隔垫物，多个隔垫物支撑部1305包括主隔垫物支撑部1305A和副隔垫物支撑部1305B；主隔垫物支撑部1305A在衬底基板110上的正投影位于第一竖向连接部1246A在衬底基板110上的正投影与第一竖向连接部1246A距离最近的数据线140在衬底基板110上的正投影之间；或者主隔垫物支撑部1305A在衬底基板110上的正投影位于第二竖向连接部1246B在衬底基板110上的正投影与第二竖向连接部1246B距离最近的数据线140在衬底基板110上的正投影之间。
在一些示例中，如图4和图5所示，一个主隔垫物支撑部1305A和一个副隔垫物支撑部1305B分别设置在第一竖向连接部1246A或第二竖向连接部1246B在第一方向上的两侧。
需要说明的是，由于每N(例如，30-40)个像素单元仅需设置一个主隔垫物支撑部即可，因此副隔垫物支撑部在衬底基板上的正投影也可设置在第一竖向连接部在衬底基板上的正投影与第一竖向连接部距离最近的数据线在衬底基板上的正投影之间，或者位于第二竖向连接部在衬底基板上的正投影与第二竖向连接部距离最近的数据线在衬底基板上的正投影之间。当然，本公开实施例包括但不限于此，隔垫物支撑部在衬底基板上的正投影与竖向导电部的延长线在衬底基板上的正投影至少部分重叠，或者位于数据线上方。
图13为本公开一实施例提供的一种隔垫物支撑部与隔垫物的位置关系图。如图13所示，主隔垫物支撑部1305A上可设置主隔垫物330A，副隔垫物支撑部1305B上可设置副隔垫物330B。主隔垫物330A在衬底基板110上的正投影的边缘与主隔垫物支撑部1305A在衬底基板上的正投影的边缘的最短距离的 范围为5-7微米，例如6.6微米。由此，由于主隔垫物支撑部的中间部分的平坦度大于边缘部分的平坦度，该阵列基板可避免将主隔垫物设置在主隔垫物支撑部的边缘部分，从而可提高主隔垫物的稳定性。
在一些示例中，如图13所示，主隔垫物330A在衬底基板110上的正投影的边缘与相邻的漏极163在衬底基板上的正投影的边缘的最短距离的范围为10-12微米，例如11.1微米。由于漏极对于平坦度的影响较大，该阵列基板可避免将主隔垫物设置距离漏极较远，从而可提高主隔垫物的稳定性。
在一些示例中，如图4和图5所示，隔垫物支撑部1305在衬底基板110上的正投影位于第一竖向导电部1242A的延长线在衬底基板110上的正投影和与第一竖向导电部1242A距离最近的数据线140在衬底基板110上的正投影之间。由于第二过孔连接结构可能会造成开口率的损失，因此，通过将第二过孔连接结构至少部分设置在透光率较低的像素单元中，该阵列基板可降低第二过孔连接结构对开口率的损失。当然，本公开实施例包括但不限于此，隔垫物支撑部在衬底基板上的正投影与竖向导电部的延长线在衬底基板上的正投影至少部分重叠，从而可更好地利用竖向导电部的延伸线所在的区域。
另一方面，在第二方向上相邻的两个第一竖向导电部没有设置竖向连接部，因此第一竖向导电部的延长线所在的区域更加平坦，从而可使得隔垫物更不容易产生位移。
在一些示例中，如图4和图5所示，各栅线130包括隔垫物支撑部1305，隔垫物支撑部1305所在的区域被配置为放置隔垫物330，隔垫物支撑部1305在衬底基板110上的正投影与第一竖向导电部1242A的延长线在衬底基板110上的正投影至少部分重叠。
在一些示例中，如图4和图5所示，多个像素行210包括沿第二方向Y依次设置的第一像素行210A和第二像素行210B，多条栅线130包括依次设置的第一栅线131、第二栅线132、第三栅线133和第四栅线134；第一栅线131位于第二像素行210B远离第一像素行210A的一侧，第二栅线132和第三栅线133位于第一像素行210A和第二像素行210B之间，第三栅线133位于第二栅线132远离第一栅线131的一侧，第四栅线134位于第一像素行210A远离第二像素行210B的一侧。
在一些示例中，如图4和图5所示，第一栅线131与第一像素行210A中的第一像素组215A中的第一颜色像素单元200A和第二像素组215B中的第一 颜色像素单元200A相连；第二栅线132与第一像素行210A的第一像素组215A中的第二颜色像素单元200B和第二像素组215B中的第二颜色像素单元200C相连；第三栅线133与第二像素行210B中的第一像素组215A中的第一颜色像素单元200A和第二像素组210B中的第一颜色像素单元200A相连；第四栅线134与第二像素行210B的第一像素组215A中的第二颜色像素单元200B和第二像素组215B中的第二颜色像素单元200B相连。通常，第一颜色像素单元和第二颜色像素单元的亮度比第三颜色像素单元高。由此，该阵列基板可实现同一像素行中的多个第一颜色像素单元均由同一栅线驱动，从而可保证多个第一颜色像素单元的充电率一致，防止细纹等不良现象发生。同样地，该阵列基板可实现同一像素行中的多个第二颜色像素单元均由同一栅线驱动，从而可保证多个第二颜色像素单元的充电率一致，防止细纹等不良现象发生。
在一些示例中，如图4和图5所示，第一栅线131还与第一像素行210A中的第二像素组215B中的第三颜色像素单元200C相连，第二栅线132还与第一像素行210A中的第一像素组215A中的第三颜色像素单元200C相连，第三栅线133还与第二像素行210B中的第二像素组215B中的第三颜色像素单元200C相连，第四栅线134还与第二像素行210B中的第一像素组215A中的第三颜色像素单元200C。
需要说明的是，上述的各实施例以ADS、HADS模式为例进行说明，但本公开实施例包括不限于此，本公开实施例也可适用于面内开关(In-Plane Switching，IPS)等模式。另外，上述的各实施例以直线型的横向公共电极线和竖向公共电极线为例进行说明。但本公开实施例包括不限于此，本公开实施例提供的公共电极线和竖向公共电极线亦可不为直线型，只要横向公共电极线大体沿第一方向延伸，竖向公共电极线大体沿列方向延伸即可。
本公开一实施例还提供一种阵列基板的制作方法。图14A-14D为本公开一实施例提供的一种阵列基板的制作方法的步骤示意图。
如图14A所示，在衬底基板110上形成栅极层1300；该栅极层1300包括上述的栅线130、栅极161、横向公共电极线122、和竖向公共电极线的竖向导电部1242。竖向导电部1242位于两条栅线130之间，也就是说，与栅线130同层设置的竖向导电部1242与栅线130不相连，且间隔设置。竖向导电部1242与横向公共电极线122交叉，并在交叉位置形成一体的十字形导电结构。由此，该阵列基板可通过上述的十字形导电结构降低公共电极线的电阻。
如图14B所示，在栅极层1300远离衬底基板110的一侧形成源漏电极层1400；该源漏电极层1400包括上述的数据线140、驱动晶体管160的源极162和漏极163。竖向导电部1242位于相邻的两个数据线140之间，竖向导电部1242在衬底基板110上的正投影与数据线140在衬底基板110上的正投影间隔设置。虽然，竖向导电部与数据线异层设置，但是该阵列基板通过将竖向导电部设置在相邻的两个数据线之间，可避免竖向导电部与数据线之间形成寄生电容。
如图14B所示，漏极163还包括漏极主体部1630和漏极延伸部1636，漏极延伸部1636从漏极主体部1630向竖向导电部1242延伸。
如图14C所示，在源漏电极层1400远离衬底基板110的一侧形成第一电极层1800；第一电极层1800包括像素电极180；像素电极180包括像素电极延伸部186，像素电极延伸部186与漏极延伸部1636通过搭接的方式相连。一方面，漏极延伸部可降低像素电极延伸部的电阻；另一方面，像素电极通过像素电极延伸部与漏极通过搭接的方式相连，可避免在像素电极和漏极直线设置过孔连接结构，从而可进一步提高开口率。
如图14D所示，在第一电极层1800远离衬底基板110的一侧形成第二电极层1900；第二电极层1900包括公共电极190和竖向导电部1246；竖向连接部1246与栅线130异层设置，且将相邻的两条竖向导电部1242相连。由此，一方面，该阵列基板可通过上述竖向连接部降低公共电极线的电阻；另一方面，该阵列基板可通过竖向连接部使得公共电极线形成网状结构，从而增加整个阵列基板的公共电极或公共电极线上的电压均一性和稳定性。
如图14D所示，竖向连接部1246的两端部通过过孔连接结构150分别与相邻的两条竖向导电部1242相连。需要说明的是，在上述的阵列基板的制作方法中，还包括形成必要的绝缘层、钝化层和平坦层的步骤。
本公开一实施例还提供一种显示面板。图15为本公开一实施例提供的一种显示面板的结构示意图。如图15所示，该显示面板400包括上述任一项所述的阵列基板100。由此，该显示面板具有与该阵列基板的有益效果对应的有益效果。例如，该显示面板降低了黑矩阵的宽度，有效地提高了开口率。
在一些示例中，如图15所示，该显示面板400还包括对置基板300、液晶层350和封框胶360；对置基板300与阵列基板100相对间隔设置，液晶层350设置在阵列基板100和对置基板300之间，封框胶360用于将液晶层350密封 在阵列基板100和对置基板300之间。
图16为本公开一实施例提供的另一种显示面板的结构示意图。如图16所示，该显示面板400包括主隔垫物330A和副隔垫物330B；主隔垫物330A位于阵列基板100和对置基板300之间；副隔垫物330B位于阵列基板100和对置基板300之间。
在一些示例中，如图16所示，主隔垫物330A与阵列基板110和对置基板300均接触设置，以起到主要的支撑作用；副隔垫物330B与阵列基板100和对置基板300中的至少之一接触设置。例如，副隔垫物330B可仅与对置基板300接触设置。
在一些示例中，如图16所示，主隔垫物330A在垂直于衬底基板110的方向上具有第一高度H1，副隔垫物330B在垂直于衬底基板110的方向上具有第二高度H2，第一高度H1大于第二高度H2，第一高度H1和第二高度H2的差值范围为0.2-0.6微米。
图17为本公开一实施例提供的一种显示面板中主隔垫物的分布示意图。如图17所示，每N个像素单元200设置一个主隔垫物330A，N的取值范围为30-40。
例如，如图17所示，每36个像素单元200设置一个主隔垫物330A。这36个像素单元200可形成6*6的矩阵；此时，由像素单元200形成的6*6的矩阵中设置一个主隔垫物330A。当然，本公开实施例包括但不限于此，这36个像素单元200也可形成其他矩阵。
在一些示例中，主隔垫物所占的面积与显示面板的面积的比例为125μm 2/mm 2，副隔垫物所占的面积与显示面板的面积的比例为6134μm 2/mm 2。
本公开一实施例还提供一种显示装置。图18为本公开一实施例提供的一种显示装置的示意图。如图18所示，该显示装置500包括上述的显示面板400。
例如，该显示装置可为电视、电脑显示器、笔记本电脑、平板电脑、智能手机、导航仪、电子画框、车载显示器等具有显示功能的显示装置。
有以下几点需要说明：
(1)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开同一实施例及不同实施例中的特征可以相互组合。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (32)

  1. 一种阵列基板，包括：
    衬底基板；
    多个像素单元，位于所述衬底基板的一侧；以及
    公共电极线，包括横向公共电极线和竖向公共电极线，所述横向公共电极线与所述竖向公共电极线电性相连，
    其中，所述多个像素单元沿第一方向和第二方向阵列设置以形成多个像素行和多个像素列，各所述像素行沿所述第一方向延伸，各所述像素列沿所述第二方向延伸，
    所述横向公共电极线沿所述第一方向延伸，所述竖向公共电极线沿所述第二方向延伸，各所述像素单元包括有效显示区，所述横向公共电极线与同一所述像素行的多个有效显示区重叠。
  2. 根据权利要求1所述的阵列基板，其中，所述有效显示区包括在所述第二方向上排列的第一畴和第二畴，所述横向公共电极线位于所述第一畴和所述第二畴之间。
  3. 根据权利要求1所述的阵列基板，还包括：
    多条栅线，沿所述第二方向排列；以及
    多条数据线，沿所述第一方向排列，
    其中，各所述栅线沿所述第一方向延伸，各所述数据线沿所述第二方向延伸，所述多条栅线与所述多条数据线异层设置，所述横向公共电极线与所述栅线同层设置。
  4. 根据权利要求3所述的阵列基板，其中，所述竖向公共电极线包括竖向导电部，所述竖向导电部与所述栅线同层设置，所述竖向导电部位于在所述第一方向上相邻的两个所述像素单元之间，
    所述竖向导电部位于两条所述栅线之间，且与所述横向公共电极线交叉，并在交叉位置形成一体的十字形导电结构。
  5. 根据权利要求4所述的阵列基板，其中，所述竖向导电部位于所述第二方向上相邻的两个所述数据线之间，所述竖向导电部在所述衬底基板上的正投影与所述数据线在所述衬底基板上的正投影间隔设置。
  6. 根据权利要求4所述的阵列基板，其中，所述竖向公共电极线包括竖 向连接部，所述竖向连接部与所述栅线异层设置，且将在所述第二方向上相邻的两条所述竖向导电部相连。
  7. 根据权利要求6所述的阵列基板，其中，所述竖向连接部的两端部通过过孔连接结构分别与在所述第二方向上相邻的两条所述竖向导电部相连，
    所述多个像素单元包括第一颜色像素单元、第二颜色像素单元和第三颜色像素单元，所述过孔连接结构在所述衬底基板上的正投影与所述第三颜色像素单元的有效显示区在所述衬底基板上的正投影至少部分重叠。
  8. 根据权利要求7所述的阵列基板，其中，所述第三颜色像素单元的透光率小于所述第一颜色像素单元的透光率和所述第二颜色像素单元的透光率。
  9. 根据权利要求7所述的阵列基板，其中，所述第一颜色像素单元被配置发第一颜色的光，所述第二颜色像素单元被配置为发第二颜色的光，所述第三颜色像素单元被配置为发第三颜色的光，所述第三颜色的波长小于所述第一颜色的波长和所述第二颜色的波长。
  10. 根据权利要求6所述的阵列基板，其中，各所述像素单元还包括：
    像素电极，位于所述数据线所在的膜层远离所述衬底基板的一侧；以及
    公共电极，位于所述像素电极远离所述衬底基板的一侧，
    其中，所述竖向连接部与所述公共电极同层设置。
  11. 根据权利要求10所述的阵列基板，其中，至少一个所述像素单元还包括：
    驱动晶体管，包括栅极、源极和漏极，
    其中，所述栅极与所述栅线相连，所述像素电极与所述漏极相连，所述公共电极与所述公共电极线相连，所述漏极包括漏极主体部和漏极延伸部，所述漏极延伸部从所述漏极主体部向所述竖向连接部延伸，
    所述像素电极包括像素电极延伸部，所述像素电极延伸部与所述漏极延伸部通过搭接的方式相连。
  12. 根据权利要求11所述的阵列基板，其中，所述漏极延伸部在所述衬底基板上的正投影与所述竖向连接部在所述衬底基板上的正投影间隔设置，且所述漏极延伸部在所述衬底基板上的正投影与所述竖向连接部在所述衬底基板上的正投影之间的距离的范围在0-3微米。
  13. 根据权利要求12所述的阵列基板，其中，所述漏极延伸部在所述衬底基板上的正投影与所述竖向连接部在所述衬底基板上的正投影之间的距离 的范围在1-2.5微米。
  14. 根据权利要求4-13中任一项所述的阵列基板，其中，各所述栅线包括隔垫物支撑部，所述隔垫物支撑部所在的区域被配置为放置隔垫物，
    所述隔垫物支撑部在所述衬底基板上的正投影位于所述竖向导电部的延长线在所述衬底基板上的正投影和与所述竖向导电部距离最近的所述数据线在所述衬底基板上的正投影之间。
  15. 根据权利要求4-10中任一项所述的阵列基板，其中，各所述栅线包括隔垫物支撑部，所述隔垫物支撑部所在的区域被配置为放置隔垫物，
    所述隔垫物支撑部在所述衬底基板上的正投影与所述竖向导电部的延长线在所述衬底基板上的正投影至少部分重叠。
  16. 根据权利要求3-15中任一项所述的阵列基板，其中，在所述第二方向上相邻的两个所述像素列之间设置有两条所述栅线。
  17. 根据权利要求3所述的阵列基板，其中，各所述像素行包括多个像素组，各所述像素组包括依次设置的第一颜色像素单元、第二颜色像素单元和第三颜色像素单元，
    所述多个像素组包括沿所述第一方向依次设置的第一像素组和第二像素组，所述多条数据线包括依次设置的第一数据线、第二数据线、第三数据线和第四数据线，
    所述第一数据线位于所述第一像素组中所述第一颜色像素单元远离所述第二颜色像素单元的一侧，所述第二数据线位于所述第一像素组中所述第二颜色像素单元和所述第三颜色像素单元之间，所述第三数据线位于所述第二像素组中所述第一颜色像素单元和所述第二颜色像素单元，所述第四数据线位于所述第二像素组中所述第三颜色像素单元远离所述第二颜色像素单元的一侧。
  18. 根据权利要求17所述的阵列基板，其中，所述竖向公共电极线包括第一竖向导电部、第二竖向导电部和第三竖向导电部，所述第一竖向导电部、所述第二竖向导电部和所述第三竖向导电部均与所述栅线同层设置，
    所述第一竖向导电部位于所述第一像素组中所述第一颜色像素单元和所述第二颜色像素单元之间，所述第二竖向导电部位于所述第一像素组中所述第三颜色像素单元和所述第二像素组中的所述第一颜色像素单元之间，所述第三竖向导电部位于所述第二像素组中所述第二颜色像素单元和所述第三颜色像素单元之间，
    所述第一竖向导电部、所述第二竖向导电部和所述第三竖向导电部均位于两条所述栅线之间，且分别与所述横向公共电极线交叉，并在交叉位置形成三个一体的十字形导电结构。
  19. 根据权利要求18所述的阵列基板，其中，所述竖向公共电极线还包括：
    第一竖向连接部，与所述栅线异层设置，并将在所述第二方向上相邻的两条所述第二竖向导电部相连；以及
    第二竖向连接部，与所述栅线异层设置，并将在所述第二方向上相邻的两条所述第三竖向导电部相连。
  20. 根据权利要求19所述的阵列基板，其中，所述第一竖向连接部的两端部分别通过第一过孔连接结构与在所述第二方向上相邻的两条所述第二竖向导电部相连，
    所述第一过孔连接结构在所述衬底基板上的正投影与所述第三颜色像素单元的有效显示区在所述衬底基板上的正投影至少部分重叠，
    所述第二竖向连接部的两端部分别通过第二过孔连接结构与在所述第二方向上相邻的两条所述第三竖向导电部相连，
    所述第二过孔连接结构在所述衬底基板上的正投影与所述第三颜色像素单元的有效显示区在所述衬底基板上的正投影至少部分重叠。
  21. 根据权利要求19所述的阵列基板，其中，各所述栅线包括多个隔垫物支撑部，各所述隔垫物支撑部所在的区域被配置为放置隔垫物，所述多个隔垫物支撑部包括主隔垫物支撑部和副隔垫物支撑部，
    所述主隔垫物支撑部在所述衬底基板上的正投影位于所述第一竖向连接部在所述衬底基板上的正投影与所述第一竖向连接部距离最近的所述数据线在所述衬底基板上的正投影之间，或者所述主隔垫物支撑部在所述衬底基板上的正投影位于所述第二竖向连接部在所述衬底基板上的正投影与所述第二竖向连接部距离最近的所述数据线在所述衬底基板上的正投影之间。
  22. 根据权利要求21所述的阵列基板，其中，一个所述主隔垫物支撑部和一个所述副隔垫物支撑部分别设置在所述第一竖向连接部或所述第二竖向连接部在所述第一方向上的两侧。
  23. 根据权利要求17-22中任一项所述的阵列基板，其中，所述多个像素行包括沿第二方向依次设置的第一像素行和第二像素行，所述多条栅线包括依 次设置的第一栅线、第二栅线、第三栅线和第四栅线，
    所述第一栅线位于所述第二像素行远离所述第一像素行的一侧，所述第二栅线和所述第三栅线位于所述第一像素行和所述第二像素行之间，所述第三栅线位于所述第二栅线远离所述第一栅线的一侧，所述第四栅线位于所述第一像素行远离所述第二像素行的一侧。
  24. 根据权利要求23所述的阵列基板，其中，所述第一栅线与所述第一像素行中的所述第一像素组中的所述第一颜色像素单元和所述第二像素组中的所述第一颜色像素单元相连，
    所述第二栅线与所述第一像素行的所述第一像素组中的所述第二颜色像素单元和所述第二像素组中的所述第二颜色像素单元相连，
    所述第三栅线与所述第二像素行中的所述第一像素组中的所述第一颜色像素单元和所述第二像素组中的所述第一颜色像素单元相连，
    所述第四栅线与所述第二像素行的所述第一像素组中的所述第二颜色像素单元和所述第二像素组中的所述第二颜色像素单元相连。
  25. 根据权利要求24所述的阵列基板，其中，所述第一栅线还与所述第一像素行中的所述第二像素组中的所述第三颜色像素单元相连，所述第二栅线还与所述第一像素行中的所述第一像素组中的所述第三颜色像素单元相连，所述第三栅线还与所述第二像素行中的所述第二像素组中的所述第三颜色像素单元相连，所述第四栅线还与所述第二像素行中的所述第一像素组中的所述第三颜色像素单元。
  26. 一种显示面板，包括根据权利要求1-25中任一项所述的阵列基板。
  27. 根据权利要求26所述的显示面板，还包括：
    对置基板，与所述阵列基板相对设置；
    主隔垫物，位于所述阵列基板和所述对置基板之间；以及
    副隔垫物，位于所述阵列基板和所述对置基板之间。
  28. 根据权利要求27所述的显示面板，其中，每N个所述像素单元设置一个所述主隔垫物，N的取值范围为30-40。
  29. 根据权利要求28所述的显示面板，其中，N的取值为36。
  30. 根据权利要求27-29中任一项所述的显示面板，其中，所述主隔垫物与所述阵列基板和所述对置基板均接触设置，所述副隔垫物与所述阵列基板和所述对置基板中的至少之一接触设置。
  31. 根据权利要求30所述的显示面板，其中，所述主隔垫物在垂直于所述衬底基板的方向上具有第一高度，所述副隔垫物在垂直于所述衬底基板的方向上具有第二高度，所述第一高度大于所述第二高度，所述第一高度和所述第二高度的差值范围为0.2-0.6微米。
  32. 一种显示装置，包括根据权利要求26-31中任一项所述的显示面板。
PCT/CN2022/084629 2022-03-31 2022-03-31 阵列基板、显示面板及显示装置 WO2023184426A1 (zh)

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